1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetOptions.h"
56 using namespace dwarf;
58 STATISTIC(NumTailCalls, "Number of tail calls");
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static SDValue Insert128BitVector(SDValue Result,
70 static SDValue Extract128BitVector(SDValue Vec,
75 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
76 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
77 /// simple subregister reference. Idx is an index in the 128 bits we
78 /// want. It need not be aligned to a 128-bit bounday. That makes
79 /// lowering EXTRACT_VECTOR_ELT operations easier.
80 static SDValue Extract128BitVector(SDValue Vec,
84 EVT VT = Vec.getValueType();
85 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
86 EVT ElVT = VT.getVectorElementType();
87 int Factor = VT.getSizeInBits()/128;
88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
89 VT.getVectorNumElements()/Factor);
91 // Extract from UNDEF is UNDEF.
92 if (Vec.getOpcode() == ISD::UNDEF)
93 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
95 if (isa<ConstantSDNode>(Idx)) {
96 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
98 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
99 // we can match to VEXTRACTF128.
100 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
102 // This is the index of the first element of the 128-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
107 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
117 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
118 /// sets things up to match to an AVX VINSERTF128 instruction or a
119 /// simple superregister reference. Idx is an index in the 128 bits
120 /// we want. It need not be aligned to a 128-bit bounday. That makes
121 /// lowering INSERT_VECTOR_ELT operations easier.
122 static SDValue Insert128BitVector(SDValue Result,
127 if (isa<ConstantSDNode>(Idx)) {
128 EVT VT = Vec.getValueType();
129 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
131 EVT ElVT = VT.getVectorElementType();
132 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
133 EVT ResultVT = Result.getValueType();
135 // Insert the relevant 128 bits.
136 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
138 // This is the index of the first element of the 128-bit chunk
140 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
143 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
144 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
152 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
153 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
154 bool is64Bit = Subtarget->is64Bit();
156 if (Subtarget->isTargetEnvMacho()) {
158 return new X8664_MachoTargetObjectFile();
159 return new TargetLoweringObjectFileMachO();
162 if (Subtarget->isTargetELF())
163 return new TargetLoweringObjectFileELF();
164 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
165 return new TargetLoweringObjectFileCOFF();
166 llvm_unreachable("unknown subtarget type");
169 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
170 : TargetLowering(TM, createTLOF(TM)) {
171 Subtarget = &TM.getSubtarget<X86Subtarget>();
172 X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX();
173 X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX();
174 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
176 RegInfo = TM.getRegisterInfo();
177 TD = getTargetData();
179 // Set up the TargetLowering object.
180 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
182 // X86 is weird, it always uses i8 for shift amounts and setcc results.
183 setBooleanContents(ZeroOrOneBooleanContent);
185 // For 64-bit since we have so many registers use the ILP scheduler, for
186 // 32-bit code use the register pressure specific scheduling.
187 if (Subtarget->is64Bit())
188 setSchedulingPreference(Sched::ILP);
190 setSchedulingPreference(Sched::RegPressure);
191 setStackPointerRegisterToSaveRestore(X86StackPtr);
193 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
194 // Setup Windows compiler runtime calls.
195 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
196 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
197 setLibcallName(RTLIB::SREM_I64, "_allrem");
198 setLibcallName(RTLIB::UREM_I64, "_aullrem");
199 setLibcallName(RTLIB::MUL_I64, "_allmul");
200 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
201 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
202 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
203 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
207 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
208 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
211 if (Subtarget->isTargetDarwin()) {
212 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
213 setUseUnderscoreSetJmp(false);
214 setUseUnderscoreLongJmp(false);
215 } else if (Subtarget->isTargetMingw()) {
216 // MS runtime is weird: it exports _setjmp, but longjmp!
217 setUseUnderscoreSetJmp(true);
218 setUseUnderscoreLongJmp(false);
220 setUseUnderscoreSetJmp(true);
221 setUseUnderscoreLongJmp(true);
224 // Set up the register classes.
225 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
226 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
227 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
228 if (Subtarget->is64Bit())
229 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
231 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
233 // We don't accept any truncstore of integer registers.
234 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
235 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
236 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
237 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
238 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
239 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
241 // SETOEQ and SETUNE require checking two conditions.
242 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
243 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
244 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
246 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
247 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
249 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
251 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
253 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
255 if (Subtarget->is64Bit()) {
256 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
257 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
258 } else if (!UseSoftFloat) {
259 // We have an algorithm for SSE2->double, and we turn this into a
260 // 64-bit FILD followed by conditional FADD for other targets.
261 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
262 // We have an algorithm for SSE2, and we turn this into a 64-bit
263 // FILD for other targets.
264 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
267 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
269 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
270 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
273 // SSE has no i16 to fp conversion, only i32
274 if (X86ScalarSSEf32) {
275 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
276 // f32 and f64 cases are Legal, f80 case is not
277 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
280 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
284 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
287 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
288 // are Legal, f80 is custom lowered.
289 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
290 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
292 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
294 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
295 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
297 if (X86ScalarSSEf32) {
298 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
299 // f32 and f64 cases are Legal, f80 case is not
300 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
302 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
303 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
306 // Handle FP_TO_UINT by promoting the destination to a larger signed
308 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
310 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
312 if (Subtarget->is64Bit()) {
313 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
315 } else if (!UseSoftFloat) {
316 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
317 // Expand FP_TO_UINT into a select.
318 // FIXME: We would like to use a Custom expander here eventually to do
319 // the optimal thing for SSE vs. the default expansion in the legalizer.
320 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
322 // With SSE3 we can use fisttpll to convert to a signed i64; without
323 // SSE, we're stuck with a fistpll.
324 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
327 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
328 if (!X86ScalarSSEf64) {
329 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
330 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
331 if (Subtarget->is64Bit()) {
332 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
333 // Without SSE, i64->f64 goes through memory.
334 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
338 // Scalar integer divide and remainder are lowered to use operations that
339 // produce two results, to match the available instructions. This exposes
340 // the two-result form to trivial CSE, which is able to combine x/y and x%y
341 // into a single instruction.
343 // Scalar integer multiply-high is also lowered to use two-result
344 // operations, to match the available instructions. However, plain multiply
345 // (low) operations are left as Legal, as there are single-result
346 // instructions for this in x86. Using the two-result multiply instructions
347 // when both high and low results are needed must be arranged by dagcombine.
348 for (unsigned i = 0, e = 4; i != e; ++i) {
350 setOperationAction(ISD::MULHS, VT, Expand);
351 setOperationAction(ISD::MULHU, VT, Expand);
352 setOperationAction(ISD::SDIV, VT, Expand);
353 setOperationAction(ISD::UDIV, VT, Expand);
354 setOperationAction(ISD::SREM, VT, Expand);
355 setOperationAction(ISD::UREM, VT, Expand);
357 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
358 setOperationAction(ISD::ADDC, VT, Custom);
359 setOperationAction(ISD::ADDE, VT, Custom);
360 setOperationAction(ISD::SUBC, VT, Custom);
361 setOperationAction(ISD::SUBE, VT, Custom);
364 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
365 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
366 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
367 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
368 if (Subtarget->is64Bit())
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
373 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f32 , Expand);
375 setOperationAction(ISD::FREM , MVT::f64 , Expand);
376 setOperationAction(ISD::FREM , MVT::f80 , Expand);
377 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
379 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
380 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
381 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
382 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
383 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
384 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
385 if (Subtarget->is64Bit()) {
386 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
387 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
390 if (Subtarget->hasPOPCNT()) {
391 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
393 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
395 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
396 if (Subtarget->is64Bit())
397 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
400 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
403 // These should be promoted to a larger select which is supported.
404 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
405 // X86 wants to expand cmov itself.
406 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
407 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
409 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
412 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
415 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
418 if (Subtarget->is64Bit()) {
419 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
420 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
422 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
425 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
426 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
427 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
428 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
429 if (Subtarget->is64Bit())
430 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
431 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
432 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
433 if (Subtarget->is64Bit()) {
434 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
437 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
438 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
440 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
441 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
442 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
443 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
444 if (Subtarget->is64Bit()) {
445 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
446 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
447 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
450 if (Subtarget->hasXMM())
451 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
453 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
454 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
456 // On X86 and X86-64, atomic operations are lowered to locked instructions.
457 // Locked instructions, in turn, have implicit fence semantics (all memory
458 // operations are flushed before issuing the locked instruction, and they
459 // are not buffered), so we can fold away the common pattern of
460 // fence-atomic-fence.
461 setShouldFoldAtomicFences(true);
463 // Expand certain atomics
464 for (unsigned i = 0, e = 4; i != e; ++i) {
466 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
467 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
468 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
471 if (!Subtarget->is64Bit()) {
472 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
473 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
474 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
477 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
478 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
479 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
482 if (Subtarget->hasCmpxchg16b()) {
483 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
486 // FIXME - use subtarget debug flags
487 if (!Subtarget->isTargetDarwin() &&
488 !Subtarget->isTargetELF() &&
489 !Subtarget->isTargetCygMing()) {
490 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
493 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
494 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
495 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
496 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
497 if (Subtarget->is64Bit()) {
498 setExceptionPointerRegister(X86::RAX);
499 setExceptionSelectorRegister(X86::RDX);
501 setExceptionPointerRegister(X86::EAX);
502 setExceptionSelectorRegister(X86::EDX);
504 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
505 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
507 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
509 setOperationAction(ISD::TRAP, MVT::Other, Legal);
511 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
512 setOperationAction(ISD::VASTART , MVT::Other, Custom);
513 setOperationAction(ISD::VAEND , MVT::Other, Expand);
514 if (Subtarget->is64Bit()) {
515 setOperationAction(ISD::VAARG , MVT::Other, Custom);
516 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
518 setOperationAction(ISD::VAARG , MVT::Other, Expand);
519 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
522 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
523 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
525 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
526 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
527 MVT::i64 : MVT::i32, Custom);
528 else if (EnableSegmentedStacks)
529 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
530 MVT::i64 : MVT::i32, Custom);
532 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
533 MVT::i64 : MVT::i32, Expand);
535 if (!UseSoftFloat && X86ScalarSSEf64) {
536 // f32 and f64 use SSE.
537 // Set up the FP register classes.
538 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
539 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
541 // Use ANDPD to simulate FABS.
542 setOperationAction(ISD::FABS , MVT::f64, Custom);
543 setOperationAction(ISD::FABS , MVT::f32, Custom);
545 // Use XORP to simulate FNEG.
546 setOperationAction(ISD::FNEG , MVT::f64, Custom);
547 setOperationAction(ISD::FNEG , MVT::f32, Custom);
549 // Use ANDPD and ORPD to simulate FCOPYSIGN.
550 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
551 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
553 // Lower this to FGETSIGNx86 plus an AND.
554 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
555 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
557 // We don't support sin/cos/fmod
558 setOperationAction(ISD::FSIN , MVT::f64, Expand);
559 setOperationAction(ISD::FCOS , MVT::f64, Expand);
560 setOperationAction(ISD::FSIN , MVT::f32, Expand);
561 setOperationAction(ISD::FCOS , MVT::f32, Expand);
563 // Expand FP immediates into loads from the stack, except for the special
565 addLegalFPImmediate(APFloat(+0.0)); // xorpd
566 addLegalFPImmediate(APFloat(+0.0f)); // xorps
567 } else if (!UseSoftFloat && X86ScalarSSEf32) {
568 // Use SSE for f32, x87 for f64.
569 // Set up the FP register classes.
570 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
571 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
573 // Use ANDPS to simulate FABS.
574 setOperationAction(ISD::FABS , MVT::f32, Custom);
576 // Use XORP to simulate FNEG.
577 setOperationAction(ISD::FNEG , MVT::f32, Custom);
579 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
581 // Use ANDPS and ORPS to simulate FCOPYSIGN.
582 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
583 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
585 // We don't support sin/cos/fmod
586 setOperationAction(ISD::FSIN , MVT::f32, Expand);
587 setOperationAction(ISD::FCOS , MVT::f32, Expand);
589 // Special cases we handle for FP constants.
590 addLegalFPImmediate(APFloat(+0.0f)); // xorps
591 addLegalFPImmediate(APFloat(+0.0)); // FLD0
592 addLegalFPImmediate(APFloat(+1.0)); // FLD1
593 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
594 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
597 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
598 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
600 } else if (!UseSoftFloat) {
601 // f32 and f64 in x87.
602 // Set up the FP register classes.
603 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
604 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
606 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
607 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
608 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
609 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
612 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
613 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
615 addLegalFPImmediate(APFloat(+0.0)); // FLD0
616 addLegalFPImmediate(APFloat(+1.0)); // FLD1
617 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
618 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
619 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
620 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
621 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
622 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
625 // We don't support FMA.
626 setOperationAction(ISD::FMA, MVT::f64, Expand);
627 setOperationAction(ISD::FMA, MVT::f32, Expand);
629 // Long double always uses X87.
631 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
632 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
633 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
635 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
636 addLegalFPImmediate(TmpFlt); // FLD0
638 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
641 APFloat TmpFlt2(+1.0);
642 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
644 addLegalFPImmediate(TmpFlt2); // FLD1
645 TmpFlt2.changeSign();
646 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
650 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
651 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
654 setOperationAction(ISD::FMA, MVT::f80, Expand);
657 // Always use a library call for pow.
658 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
660 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
662 setOperationAction(ISD::FLOG, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
664 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP, MVT::f80, Expand);
666 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
668 // First set operation action for all vector types to either promote
669 // (for widening) or expand (for scalarization). Then we will selectively
670 // turn on ones that can be effectively codegen'd.
671 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
672 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
673 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
674 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
675 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
676 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
677 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
678 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
679 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
680 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
681 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
682 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
683 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
684 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
685 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
691 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
692 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
693 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
694 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
723 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
727 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
728 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
729 setTruncStoreAction((MVT::SimpleValueType)VT,
730 (MVT::SimpleValueType)InnerVT, Expand);
731 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
732 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
733 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
736 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
737 // with -msoft-float, disable use of MMX as well.
738 if (!UseSoftFloat && Subtarget->hasMMX()) {
739 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
740 // No operations on x86mmx supported, everything uses intrinsics.
743 // MMX-sized vectors (other than x86mmx) are expected to be expanded
744 // into smaller operations.
745 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
746 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
747 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
748 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
749 setOperationAction(ISD::AND, MVT::v8i8, Expand);
750 setOperationAction(ISD::AND, MVT::v4i16, Expand);
751 setOperationAction(ISD::AND, MVT::v2i32, Expand);
752 setOperationAction(ISD::AND, MVT::v1i64, Expand);
753 setOperationAction(ISD::OR, MVT::v8i8, Expand);
754 setOperationAction(ISD::OR, MVT::v4i16, Expand);
755 setOperationAction(ISD::OR, MVT::v2i32, Expand);
756 setOperationAction(ISD::OR, MVT::v1i64, Expand);
757 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
758 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
759 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
760 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
761 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
762 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
763 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
764 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
765 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
766 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
767 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
768 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
769 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
770 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
771 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
772 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
773 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
775 if (!UseSoftFloat && Subtarget->hasXMM()) {
776 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
778 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
780 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
781 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
782 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
783 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
784 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
785 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
786 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
787 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
788 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
789 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
792 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
793 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
795 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
796 // registers cannot be used even for integer operations.
797 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
798 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
799 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
800 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
802 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
803 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
804 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
805 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
806 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
807 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
808 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
809 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
810 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
811 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
812 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
813 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
814 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
815 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
816 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
817 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
819 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
820 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
821 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
822 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
824 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
825 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
826 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
827 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
828 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
830 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
831 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
832 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
833 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
834 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
836 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
837 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
838 EVT VT = (MVT::SimpleValueType)i;
839 // Do not attempt to custom lower non-power-of-2 vectors
840 if (!isPowerOf2_32(VT.getVectorNumElements()))
842 // Do not attempt to custom lower non-128-bit vectors
843 if (!VT.is128BitVector())
845 setOperationAction(ISD::BUILD_VECTOR,
846 VT.getSimpleVT().SimpleTy, Custom);
847 setOperationAction(ISD::VECTOR_SHUFFLE,
848 VT.getSimpleVT().SimpleTy, Custom);
849 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
850 VT.getSimpleVT().SimpleTy, Custom);
853 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
854 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
855 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
856 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
857 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
858 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
860 if (Subtarget->is64Bit()) {
861 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
862 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
865 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
866 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
867 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
870 // Do not attempt to promote non-128-bit vectors
871 if (!VT.is128BitVector())
874 setOperationAction(ISD::AND, SVT, Promote);
875 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
876 setOperationAction(ISD::OR, SVT, Promote);
877 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
878 setOperationAction(ISD::XOR, SVT, Promote);
879 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
880 setOperationAction(ISD::LOAD, SVT, Promote);
881 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
882 setOperationAction(ISD::SELECT, SVT, Promote);
883 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
886 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
888 // Custom lower v2i64 and v2f64 selects.
889 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
890 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
891 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
892 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
894 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
895 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
898 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
899 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
900 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
901 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
902 setOperationAction(ISD::FRINT, MVT::f32, Legal);
903 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
904 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
905 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
906 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
907 setOperationAction(ISD::FRINT, MVT::f64, Legal);
908 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
910 // FIXME: Do we need to handle scalar-to-vector here?
911 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
913 // Can turn SHL into an integer multiply.
914 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
915 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
917 // i8 and i16 vectors are custom , because the source register and source
918 // source memory operand types are not the same width. f32 vectors are
919 // custom since the immediate controlling the insert encodes additional
921 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
922 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
923 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
924 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
926 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
927 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
928 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
929 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
931 if (Subtarget->is64Bit()) {
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
933 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
937 if (Subtarget->hasSSE2() || Subtarget->hasAVX()) {
938 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
939 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
940 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
941 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
943 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
944 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
945 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
947 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
948 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
951 if (Subtarget->hasSSE42() || Subtarget->hasAVX())
952 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
954 if (!UseSoftFloat && Subtarget->hasAVX()) {
955 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
956 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
957 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
958 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
959 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
960 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
962 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
963 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
964 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
966 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
967 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
968 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
969 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
970 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
971 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
973 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
974 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
975 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
976 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
977 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
978 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
980 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
981 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
982 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
984 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
985 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
986 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
987 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
988 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
989 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
991 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
992 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
993 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
994 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
996 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
997 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
998 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
999 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1001 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1002 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1004 setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
1005 setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
1006 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
1007 setOperationAction(ISD::VSETCC, MVT::v4i64, Custom);
1009 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1010 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1011 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1013 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1014 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1015 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1016 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1018 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1019 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1020 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1021 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1023 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1024 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1025 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1026 // Don't lower v32i8 because there is no 128-bit byte mul
1028 // Custom lower several nodes for 256-bit types.
1029 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1030 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1031 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1034 // Extract subvector is special because the value type
1035 // (result) is 128-bit but the source is 256-bit wide.
1036 if (VT.is128BitVector())
1037 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1039 // Do not attempt to custom lower other non-256-bit vectors
1040 if (!VT.is256BitVector())
1043 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1044 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1045 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1046 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1047 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1048 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1051 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1052 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1053 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1056 // Do not attempt to promote non-256-bit vectors
1057 if (!VT.is256BitVector())
1060 setOperationAction(ISD::AND, SVT, Promote);
1061 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1062 setOperationAction(ISD::OR, SVT, Promote);
1063 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1064 setOperationAction(ISD::XOR, SVT, Promote);
1065 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1066 setOperationAction(ISD::LOAD, SVT, Promote);
1067 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1068 setOperationAction(ISD::SELECT, SVT, Promote);
1069 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1073 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1074 // of this type with custom code.
1075 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1076 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1077 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1080 // We want to custom lower some of our intrinsics.
1081 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1084 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1085 // handle type legalization for these operations here.
1087 // FIXME: We really should do custom legalization for addition and
1088 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1089 // than generic legalization for 64-bit multiplication-with-overflow, though.
1090 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1091 // Add/Sub/Mul with overflow operations are custom lowered.
1093 setOperationAction(ISD::SADDO, VT, Custom);
1094 setOperationAction(ISD::UADDO, VT, Custom);
1095 setOperationAction(ISD::SSUBO, VT, Custom);
1096 setOperationAction(ISD::USUBO, VT, Custom);
1097 setOperationAction(ISD::SMULO, VT, Custom);
1098 setOperationAction(ISD::UMULO, VT, Custom);
1101 // There are no 8-bit 3-address imul/mul instructions
1102 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1103 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1105 if (!Subtarget->is64Bit()) {
1106 // These libcalls are not available in 32-bit.
1107 setLibcallName(RTLIB::SHL_I128, 0);
1108 setLibcallName(RTLIB::SRL_I128, 0);
1109 setLibcallName(RTLIB::SRA_I128, 0);
1112 // We have target-specific dag combine patterns for the following nodes:
1113 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1114 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1115 setTargetDAGCombine(ISD::BUILD_VECTOR);
1116 setTargetDAGCombine(ISD::SELECT);
1117 setTargetDAGCombine(ISD::SHL);
1118 setTargetDAGCombine(ISD::SRA);
1119 setTargetDAGCombine(ISD::SRL);
1120 setTargetDAGCombine(ISD::OR);
1121 setTargetDAGCombine(ISD::AND);
1122 setTargetDAGCombine(ISD::ADD);
1123 setTargetDAGCombine(ISD::SUB);
1124 setTargetDAGCombine(ISD::STORE);
1125 setTargetDAGCombine(ISD::ZERO_EXTEND);
1126 setTargetDAGCombine(ISD::SINT_TO_FP);
1127 if (Subtarget->is64Bit())
1128 setTargetDAGCombine(ISD::MUL);
1130 computeRegisterProperties();
1132 // On Darwin, -Os means optimize for size without hurting performance,
1133 // do not reduce the limit.
1134 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1135 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1136 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1137 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1138 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1139 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1140 setPrefLoopAlignment(16);
1141 benefitFromCodePlacementOpt = true;
1143 setPrefFunctionAlignment(4);
1147 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1152 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1153 /// the desired ByVal argument alignment.
1154 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1157 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1158 if (VTy->getBitWidth() == 128)
1160 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1161 unsigned EltAlign = 0;
1162 getMaxByValAlign(ATy->getElementType(), EltAlign);
1163 if (EltAlign > MaxAlign)
1164 MaxAlign = EltAlign;
1165 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1166 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1167 unsigned EltAlign = 0;
1168 getMaxByValAlign(STy->getElementType(i), EltAlign);
1169 if (EltAlign > MaxAlign)
1170 MaxAlign = EltAlign;
1178 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1179 /// function arguments in the caller parameter area. For X86, aggregates
1180 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1181 /// are at 4-byte boundaries.
1182 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1183 if (Subtarget->is64Bit()) {
1184 // Max of 8 and alignment of type.
1185 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1192 if (Subtarget->hasXMM())
1193 getMaxByValAlign(Ty, Align);
1197 /// getOptimalMemOpType - Returns the target specific optimal type for load
1198 /// and store operations as a result of memset, memcpy, and memmove
1199 /// lowering. If DstAlign is zero that means it's safe to destination
1200 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1201 /// means there isn't a need to check it against alignment requirement,
1202 /// probably because the source does not need to be loaded. If
1203 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1204 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1205 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1206 /// constant so it does not need to be loaded.
1207 /// It returns EVT::Other if the type should be determined using generic
1208 /// target-independent logic.
1210 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1211 unsigned DstAlign, unsigned SrcAlign,
1212 bool NonScalarIntSafe,
1214 MachineFunction &MF) const {
1215 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1216 // linux. This is because the stack realignment code can't handle certain
1217 // cases like PR2962. This should be removed when PR2962 is fixed.
1218 const Function *F = MF.getFunction();
1219 if (NonScalarIntSafe &&
1220 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1222 (Subtarget->isUnalignedMemAccessFast() ||
1223 ((DstAlign == 0 || DstAlign >= 16) &&
1224 (SrcAlign == 0 || SrcAlign >= 16))) &&
1225 Subtarget->getStackAlignment() >= 16) {
1226 if (Subtarget->hasSSE2())
1228 if (Subtarget->hasSSE1())
1230 } else if (!MemcpyStrSrc && Size >= 8 &&
1231 !Subtarget->is64Bit() &&
1232 Subtarget->getStackAlignment() >= 8 &&
1233 Subtarget->hasXMMInt()) {
1234 // Do not use f64 to lower memcpy if source is string constant. It's
1235 // better to use i32 to avoid the loads.
1239 if (Subtarget->is64Bit() && Size >= 8)
1244 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1245 /// current function. The returned value is a member of the
1246 /// MachineJumpTableInfo::JTEntryKind enum.
1247 unsigned X86TargetLowering::getJumpTableEncoding() const {
1248 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1250 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1251 Subtarget->isPICStyleGOT())
1252 return MachineJumpTableInfo::EK_Custom32;
1254 // Otherwise, use the normal jump table encoding heuristics.
1255 return TargetLowering::getJumpTableEncoding();
1259 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1260 const MachineBasicBlock *MBB,
1261 unsigned uid,MCContext &Ctx) const{
1262 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1263 Subtarget->isPICStyleGOT());
1264 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1266 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1267 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1270 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1272 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1273 SelectionDAG &DAG) const {
1274 if (!Subtarget->is64Bit())
1275 // This doesn't have DebugLoc associated with it, but is not really the
1276 // same as a Register.
1277 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1281 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1282 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1284 const MCExpr *X86TargetLowering::
1285 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1286 MCContext &Ctx) const {
1287 // X86-64 uses RIP relative addressing based on the jump table label.
1288 if (Subtarget->isPICStyleRIPRel())
1289 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1291 // Otherwise, the reference is relative to the PIC base.
1292 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1295 // FIXME: Why this routine is here? Move to RegInfo!
1296 std::pair<const TargetRegisterClass*, uint8_t>
1297 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1298 const TargetRegisterClass *RRC = 0;
1300 switch (VT.getSimpleVT().SimpleTy) {
1302 return TargetLowering::findRepresentativeClass(VT);
1303 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1304 RRC = (Subtarget->is64Bit()
1305 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1308 RRC = X86::VR64RegisterClass;
1310 case MVT::f32: case MVT::f64:
1311 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1312 case MVT::v4f32: case MVT::v2f64:
1313 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1315 RRC = X86::VR128RegisterClass;
1318 return std::make_pair(RRC, Cost);
1321 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1322 unsigned &Offset) const {
1323 if (!Subtarget->isTargetLinux())
1326 if (Subtarget->is64Bit()) {
1327 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1329 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1342 //===----------------------------------------------------------------------===//
1343 // Return Value Calling Convention Implementation
1344 //===----------------------------------------------------------------------===//
1346 #include "X86GenCallingConv.inc"
1349 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1350 MachineFunction &MF, bool isVarArg,
1351 const SmallVectorImpl<ISD::OutputArg> &Outs,
1352 LLVMContext &Context) const {
1353 SmallVector<CCValAssign, 16> RVLocs;
1354 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1356 return CCInfo.CheckReturn(Outs, RetCC_X86);
1360 X86TargetLowering::LowerReturn(SDValue Chain,
1361 CallingConv::ID CallConv, bool isVarArg,
1362 const SmallVectorImpl<ISD::OutputArg> &Outs,
1363 const SmallVectorImpl<SDValue> &OutVals,
1364 DebugLoc dl, SelectionDAG &DAG) const {
1365 MachineFunction &MF = DAG.getMachineFunction();
1366 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1368 SmallVector<CCValAssign, 16> RVLocs;
1369 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1370 RVLocs, *DAG.getContext());
1371 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1373 // Add the regs to the liveout set for the function.
1374 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1375 for (unsigned i = 0; i != RVLocs.size(); ++i)
1376 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1377 MRI.addLiveOut(RVLocs[i].getLocReg());
1381 SmallVector<SDValue, 6> RetOps;
1382 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1383 // Operand #1 = Bytes To Pop
1384 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1387 // Copy the result values into the output registers.
1388 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1389 CCValAssign &VA = RVLocs[i];
1390 assert(VA.isRegLoc() && "Can only return in registers!");
1391 SDValue ValToCopy = OutVals[i];
1392 EVT ValVT = ValToCopy.getValueType();
1394 // If this is x86-64, and we disabled SSE, we can't return FP values,
1395 // or SSE or MMX vectors.
1396 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1397 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1398 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1399 report_fatal_error("SSE register return with SSE disabled");
1401 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1402 // llvm-gcc has never done it right and no one has noticed, so this
1403 // should be OK for now.
1404 if (ValVT == MVT::f64 &&
1405 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1406 report_fatal_error("SSE2 register return with SSE2 disabled");
1408 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1409 // the RET instruction and handled by the FP Stackifier.
1410 if (VA.getLocReg() == X86::ST0 ||
1411 VA.getLocReg() == X86::ST1) {
1412 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1413 // change the value to the FP stack register class.
1414 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1415 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1416 RetOps.push_back(ValToCopy);
1417 // Don't emit a copytoreg.
1421 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1422 // which is returned in RAX / RDX.
1423 if (Subtarget->is64Bit()) {
1424 if (ValVT == MVT::x86mmx) {
1425 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1426 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1427 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1429 // If we don't have SSE2 available, convert to v4f32 so the generated
1430 // register is legal.
1431 if (!Subtarget->hasSSE2())
1432 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1437 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1438 Flag = Chain.getValue(1);
1441 // The x86-64 ABI for returning structs by value requires that we copy
1442 // the sret argument into %rax for the return. We saved the argument into
1443 // a virtual register in the entry block, so now we copy the value out
1445 if (Subtarget->is64Bit() &&
1446 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1447 MachineFunction &MF = DAG.getMachineFunction();
1448 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1449 unsigned Reg = FuncInfo->getSRetReturnReg();
1451 "SRetReturnReg should have been set in LowerFormalArguments().");
1452 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1454 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1455 Flag = Chain.getValue(1);
1457 // RAX now acts like a return value.
1458 MRI.addLiveOut(X86::RAX);
1461 RetOps[0] = Chain; // Update chain.
1463 // Add the flag if we have it.
1465 RetOps.push_back(Flag);
1467 return DAG.getNode(X86ISD::RET_FLAG, dl,
1468 MVT::Other, &RetOps[0], RetOps.size());
1471 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1472 if (N->getNumValues() != 1)
1474 if (!N->hasNUsesOfValue(1, 0))
1477 SDNode *Copy = *N->use_begin();
1478 if (Copy->getOpcode() != ISD::CopyToReg &&
1479 Copy->getOpcode() != ISD::FP_EXTEND)
1482 bool HasRet = false;
1483 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1485 if (UI->getOpcode() != X86ISD::RET_FLAG)
1494 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1495 ISD::NodeType ExtendKind) const {
1497 // TODO: Is this also valid on 32-bit?
1498 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1499 ReturnMVT = MVT::i8;
1501 ReturnMVT = MVT::i32;
1503 EVT MinVT = getRegisterType(Context, ReturnMVT);
1504 return VT.bitsLT(MinVT) ? MinVT : VT;
1507 /// LowerCallResult - Lower the result values of a call into the
1508 /// appropriate copies out of appropriate physical registers.
1511 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1512 CallingConv::ID CallConv, bool isVarArg,
1513 const SmallVectorImpl<ISD::InputArg> &Ins,
1514 DebugLoc dl, SelectionDAG &DAG,
1515 SmallVectorImpl<SDValue> &InVals) const {
1517 // Assign locations to each value returned by this call.
1518 SmallVector<CCValAssign, 16> RVLocs;
1519 bool Is64Bit = Subtarget->is64Bit();
1520 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1521 getTargetMachine(), RVLocs, *DAG.getContext());
1522 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1524 // Copy all of the result registers out of their specified physreg.
1525 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1526 CCValAssign &VA = RVLocs[i];
1527 EVT CopyVT = VA.getValVT();
1529 // If this is x86-64, and we disabled SSE, we can't return FP values
1530 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1531 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1532 report_fatal_error("SSE register return with SSE disabled");
1537 // If this is a call to a function that returns an fp value on the floating
1538 // point stack, we must guarantee the the value is popped from the stack, so
1539 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1540 // if the return value is not used. We use the FpPOP_RETVAL instruction
1542 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1543 // If we prefer to use the value in xmm registers, copy it out as f80 and
1544 // use a truncate to move it from fp stack reg to xmm reg.
1545 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1546 SDValue Ops[] = { Chain, InFlag };
1547 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1548 MVT::Other, MVT::Glue, Ops, 2), 1);
1549 Val = Chain.getValue(0);
1551 // Round the f80 to the right size, which also moves it to the appropriate
1553 if (CopyVT != VA.getValVT())
1554 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1555 // This truncation won't change the value.
1556 DAG.getIntPtrConstant(1));
1558 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1559 CopyVT, InFlag).getValue(1);
1560 Val = Chain.getValue(0);
1562 InFlag = Chain.getValue(2);
1563 InVals.push_back(Val);
1570 //===----------------------------------------------------------------------===//
1571 // C & StdCall & Fast Calling Convention implementation
1572 //===----------------------------------------------------------------------===//
1573 // StdCall calling convention seems to be standard for many Windows' API
1574 // routines and around. It differs from C calling convention just a little:
1575 // callee should clean up the stack, not caller. Symbols should be also
1576 // decorated in some fancy way :) It doesn't support any vector arguments.
1577 // For info on fast calling convention see Fast Calling Convention (tail call)
1578 // implementation LowerX86_32FastCCCallTo.
1580 /// CallIsStructReturn - Determines whether a call uses struct return
1582 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1586 return Outs[0].Flags.isSRet();
1589 /// ArgsAreStructReturn - Determines whether a function uses struct
1590 /// return semantics.
1592 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1596 return Ins[0].Flags.isSRet();
1599 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1600 /// by "Src" to address "Dst" with size and alignment information specified by
1601 /// the specific parameter attribute. The copy will be passed as a byval
1602 /// function parameter.
1604 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1605 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1607 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1609 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1610 /*isVolatile*/false, /*AlwaysInline=*/true,
1611 MachinePointerInfo(), MachinePointerInfo());
1614 /// IsTailCallConvention - Return true if the calling convention is one that
1615 /// supports tail call optimization.
1616 static bool IsTailCallConvention(CallingConv::ID CC) {
1617 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1620 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1621 if (!CI->isTailCall())
1625 CallingConv::ID CalleeCC = CS.getCallingConv();
1626 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1632 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1633 /// a tailcall target by changing its ABI.
1634 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1635 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1639 X86TargetLowering::LowerMemArgument(SDValue Chain,
1640 CallingConv::ID CallConv,
1641 const SmallVectorImpl<ISD::InputArg> &Ins,
1642 DebugLoc dl, SelectionDAG &DAG,
1643 const CCValAssign &VA,
1644 MachineFrameInfo *MFI,
1646 // Create the nodes corresponding to a load from this parameter slot.
1647 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1648 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1649 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1652 // If value is passed by pointer we have address passed instead of the value
1654 if (VA.getLocInfo() == CCValAssign::Indirect)
1655 ValVT = VA.getLocVT();
1657 ValVT = VA.getValVT();
1659 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1660 // changed with more analysis.
1661 // In case of tail call optimization mark all arguments mutable. Since they
1662 // could be overwritten by lowering of arguments in case of a tail call.
1663 if (Flags.isByVal()) {
1664 unsigned Bytes = Flags.getByValSize();
1665 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1666 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1667 return DAG.getFrameIndex(FI, getPointerTy());
1669 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1670 VA.getLocMemOffset(), isImmutable);
1671 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1672 return DAG.getLoad(ValVT, dl, Chain, FIN,
1673 MachinePointerInfo::getFixedStack(FI),
1679 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1680 CallingConv::ID CallConv,
1682 const SmallVectorImpl<ISD::InputArg> &Ins,
1685 SmallVectorImpl<SDValue> &InVals)
1687 MachineFunction &MF = DAG.getMachineFunction();
1688 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1690 const Function* Fn = MF.getFunction();
1691 if (Fn->hasExternalLinkage() &&
1692 Subtarget->isTargetCygMing() &&
1693 Fn->getName() == "main")
1694 FuncInfo->setForceFramePointer(true);
1696 MachineFrameInfo *MFI = MF.getFrameInfo();
1697 bool Is64Bit = Subtarget->is64Bit();
1698 bool IsWin64 = Subtarget->isTargetWin64();
1700 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1701 "Var args not supported with calling convention fastcc or ghc");
1703 // Assign locations to all of the incoming arguments.
1704 SmallVector<CCValAssign, 16> ArgLocs;
1705 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1706 ArgLocs, *DAG.getContext());
1708 // Allocate shadow area for Win64
1710 CCInfo.AllocateStack(32, 8);
1713 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1715 unsigned LastVal = ~0U;
1717 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1718 CCValAssign &VA = ArgLocs[i];
1719 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1721 assert(VA.getValNo() != LastVal &&
1722 "Don't support value assigned to multiple locs yet");
1723 LastVal = VA.getValNo();
1725 if (VA.isRegLoc()) {
1726 EVT RegVT = VA.getLocVT();
1727 TargetRegisterClass *RC = NULL;
1728 if (RegVT == MVT::i32)
1729 RC = X86::GR32RegisterClass;
1730 else if (Is64Bit && RegVT == MVT::i64)
1731 RC = X86::GR64RegisterClass;
1732 else if (RegVT == MVT::f32)
1733 RC = X86::FR32RegisterClass;
1734 else if (RegVT == MVT::f64)
1735 RC = X86::FR64RegisterClass;
1736 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1737 RC = X86::VR256RegisterClass;
1738 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1739 RC = X86::VR128RegisterClass;
1740 else if (RegVT == MVT::x86mmx)
1741 RC = X86::VR64RegisterClass;
1743 llvm_unreachable("Unknown argument type!");
1745 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1746 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1748 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1749 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1751 if (VA.getLocInfo() == CCValAssign::SExt)
1752 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1753 DAG.getValueType(VA.getValVT()));
1754 else if (VA.getLocInfo() == CCValAssign::ZExt)
1755 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1756 DAG.getValueType(VA.getValVT()));
1757 else if (VA.getLocInfo() == CCValAssign::BCvt)
1758 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1760 if (VA.isExtInLoc()) {
1761 // Handle MMX values passed in XMM regs.
1762 if (RegVT.isVector()) {
1763 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1766 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1769 assert(VA.isMemLoc());
1770 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1773 // If value is passed via pointer - do a load.
1774 if (VA.getLocInfo() == CCValAssign::Indirect)
1775 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1776 MachinePointerInfo(), false, false, 0);
1778 InVals.push_back(ArgValue);
1781 // The x86-64 ABI for returning structs by value requires that we copy
1782 // the sret argument into %rax for the return. Save the argument into
1783 // a virtual register so that we can access it from the return points.
1784 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1785 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1786 unsigned Reg = FuncInfo->getSRetReturnReg();
1788 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1789 FuncInfo->setSRetReturnReg(Reg);
1791 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1792 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1795 unsigned StackSize = CCInfo.getNextStackOffset();
1796 // Align stack specially for tail calls.
1797 if (FuncIsMadeTailCallSafe(CallConv))
1798 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1800 // If the function takes variable number of arguments, make a frame index for
1801 // the start of the first vararg value... for expansion of llvm.va_start.
1803 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1804 CallConv != CallingConv::X86_ThisCall)) {
1805 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1808 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1810 // FIXME: We should really autogenerate these arrays
1811 static const unsigned GPR64ArgRegsWin64[] = {
1812 X86::RCX, X86::RDX, X86::R8, X86::R9
1814 static const unsigned GPR64ArgRegs64Bit[] = {
1815 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1817 static const unsigned XMMArgRegs64Bit[] = {
1818 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1819 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1821 const unsigned *GPR64ArgRegs;
1822 unsigned NumXMMRegs = 0;
1825 // The XMM registers which might contain var arg parameters are shadowed
1826 // in their paired GPR. So we only need to save the GPR to their home
1828 TotalNumIntRegs = 4;
1829 GPR64ArgRegs = GPR64ArgRegsWin64;
1831 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1832 GPR64ArgRegs = GPR64ArgRegs64Bit;
1834 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1836 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1839 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1840 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1841 "SSE register cannot be used when SSE is disabled!");
1842 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1843 "SSE register cannot be used when SSE is disabled!");
1844 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1845 // Kernel mode asks for SSE to be disabled, so don't push them
1847 TotalNumXMMRegs = 0;
1850 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1851 // Get to the caller-allocated home save location. Add 8 to account
1852 // for the return address.
1853 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1854 FuncInfo->setRegSaveFrameIndex(
1855 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1856 // Fixup to set vararg frame on shadow area (4 x i64).
1858 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1860 // For X86-64, if there are vararg parameters that are passed via
1861 // registers, then we must store them to their spots on the stack so they
1862 // may be loaded by deferencing the result of va_next.
1863 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1864 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1865 FuncInfo->setRegSaveFrameIndex(
1866 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1870 // Store the integer parameter registers.
1871 SmallVector<SDValue, 8> MemOps;
1872 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1874 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1875 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1876 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1877 DAG.getIntPtrConstant(Offset));
1878 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1879 X86::GR64RegisterClass);
1880 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1882 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1883 MachinePointerInfo::getFixedStack(
1884 FuncInfo->getRegSaveFrameIndex(), Offset),
1886 MemOps.push_back(Store);
1890 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1891 // Now store the XMM (fp + vector) parameter registers.
1892 SmallVector<SDValue, 11> SaveXMMOps;
1893 SaveXMMOps.push_back(Chain);
1895 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1896 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1897 SaveXMMOps.push_back(ALVal);
1899 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1900 FuncInfo->getRegSaveFrameIndex()));
1901 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1902 FuncInfo->getVarArgsFPOffset()));
1904 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1905 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1906 X86::VR128RegisterClass);
1907 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1908 SaveXMMOps.push_back(Val);
1910 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1912 &SaveXMMOps[0], SaveXMMOps.size()));
1915 if (!MemOps.empty())
1916 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1917 &MemOps[0], MemOps.size());
1921 // Some CCs need callee pop.
1922 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
1923 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1925 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1926 // If this is an sret function, the return should pop the hidden pointer.
1927 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1928 FuncInfo->setBytesToPopOnReturn(4);
1932 // RegSaveFrameIndex is X86-64 only.
1933 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1934 if (CallConv == CallingConv::X86_FastCall ||
1935 CallConv == CallingConv::X86_ThisCall)
1936 // fastcc functions can't have varargs.
1937 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1940 FuncInfo->setArgumentStackSize(StackSize);
1946 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1947 SDValue StackPtr, SDValue Arg,
1948 DebugLoc dl, SelectionDAG &DAG,
1949 const CCValAssign &VA,
1950 ISD::ArgFlagsTy Flags) const {
1951 unsigned LocMemOffset = VA.getLocMemOffset();
1952 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1953 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1954 if (Flags.isByVal())
1955 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1957 return DAG.getStore(Chain, dl, Arg, PtrOff,
1958 MachinePointerInfo::getStack(LocMemOffset),
1962 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1963 /// optimization is performed and it is required.
1965 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1966 SDValue &OutRetAddr, SDValue Chain,
1967 bool IsTailCall, bool Is64Bit,
1968 int FPDiff, DebugLoc dl) const {
1969 // Adjust the Return address stack slot.
1970 EVT VT = getPointerTy();
1971 OutRetAddr = getReturnAddressFrameIndex(DAG);
1973 // Load the "old" Return address.
1974 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1976 return SDValue(OutRetAddr.getNode(), 1);
1979 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
1980 /// optimization is performed and it is required (FPDiff!=0).
1982 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1983 SDValue Chain, SDValue RetAddrFrIdx,
1984 bool Is64Bit, int FPDiff, DebugLoc dl) {
1985 // Store the return address to the appropriate stack slot.
1986 if (!FPDiff) return Chain;
1987 // Calculate the new stack slot for the return address.
1988 int SlotSize = Is64Bit ? 8 : 4;
1989 int NewReturnAddrFI =
1990 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1991 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1992 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1993 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1994 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2000 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2001 CallingConv::ID CallConv, bool isVarArg,
2003 const SmallVectorImpl<ISD::OutputArg> &Outs,
2004 const SmallVectorImpl<SDValue> &OutVals,
2005 const SmallVectorImpl<ISD::InputArg> &Ins,
2006 DebugLoc dl, SelectionDAG &DAG,
2007 SmallVectorImpl<SDValue> &InVals) const {
2008 MachineFunction &MF = DAG.getMachineFunction();
2009 bool Is64Bit = Subtarget->is64Bit();
2010 bool IsWin64 = Subtarget->isTargetWin64();
2011 bool IsStructRet = CallIsStructReturn(Outs);
2012 bool IsSibcall = false;
2015 // Check if it's really possible to do a tail call.
2016 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2017 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2018 Outs, OutVals, Ins, DAG);
2020 // Sibcalls are automatically detected tailcalls which do not require
2022 if (!GuaranteedTailCallOpt && isTailCall)
2029 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2030 "Var args not supported with calling convention fastcc or ghc");
2032 // Analyze operands of the call, assigning locations to each operand.
2033 SmallVector<CCValAssign, 16> ArgLocs;
2034 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2035 ArgLocs, *DAG.getContext());
2037 // Allocate shadow area for Win64
2039 CCInfo.AllocateStack(32, 8);
2042 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2044 // Get a count of how many bytes are to be pushed on the stack.
2045 unsigned NumBytes = CCInfo.getNextStackOffset();
2047 // This is a sibcall. The memory operands are available in caller's
2048 // own caller's stack.
2050 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2051 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2054 if (isTailCall && !IsSibcall) {
2055 // Lower arguments at fp - stackoffset + fpdiff.
2056 unsigned NumBytesCallerPushed =
2057 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2058 FPDiff = NumBytesCallerPushed - NumBytes;
2060 // Set the delta of movement of the returnaddr stackslot.
2061 // But only set if delta is greater than previous delta.
2062 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2063 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2067 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2069 SDValue RetAddrFrIdx;
2070 // Load return address for tail calls.
2071 if (isTailCall && FPDiff)
2072 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2073 Is64Bit, FPDiff, dl);
2075 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2076 SmallVector<SDValue, 8> MemOpChains;
2079 // Walk the register/memloc assignments, inserting copies/loads. In the case
2080 // of tail call optimization arguments are handle later.
2081 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2082 CCValAssign &VA = ArgLocs[i];
2083 EVT RegVT = VA.getLocVT();
2084 SDValue Arg = OutVals[i];
2085 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2086 bool isByVal = Flags.isByVal();
2088 // Promote the value if needed.
2089 switch (VA.getLocInfo()) {
2090 default: llvm_unreachable("Unknown loc info!");
2091 case CCValAssign::Full: break;
2092 case CCValAssign::SExt:
2093 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2095 case CCValAssign::ZExt:
2096 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2098 case CCValAssign::AExt:
2099 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2100 // Special case: passing MMX values in XMM registers.
2101 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2102 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2103 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2105 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2107 case CCValAssign::BCvt:
2108 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2110 case CCValAssign::Indirect: {
2111 // Store the argument.
2112 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2113 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2114 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2115 MachinePointerInfo::getFixedStack(FI),
2122 if (VA.isRegLoc()) {
2123 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2124 if (isVarArg && IsWin64) {
2125 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2126 // shadow reg if callee is a varargs function.
2127 unsigned ShadowReg = 0;
2128 switch (VA.getLocReg()) {
2129 case X86::XMM0: ShadowReg = X86::RCX; break;
2130 case X86::XMM1: ShadowReg = X86::RDX; break;
2131 case X86::XMM2: ShadowReg = X86::R8; break;
2132 case X86::XMM3: ShadowReg = X86::R9; break;
2135 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2137 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2138 assert(VA.isMemLoc());
2139 if (StackPtr.getNode() == 0)
2140 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2141 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2142 dl, DAG, VA, Flags));
2146 if (!MemOpChains.empty())
2147 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2148 &MemOpChains[0], MemOpChains.size());
2150 // Build a sequence of copy-to-reg nodes chained together with token chain
2151 // and flag operands which copy the outgoing args into registers.
2153 // Tail call byval lowering might overwrite argument registers so in case of
2154 // tail call optimization the copies to registers are lowered later.
2156 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2157 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2158 RegsToPass[i].second, InFlag);
2159 InFlag = Chain.getValue(1);
2162 if (Subtarget->isPICStyleGOT()) {
2163 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2166 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2167 DAG.getNode(X86ISD::GlobalBaseReg,
2168 DebugLoc(), getPointerTy()),
2170 InFlag = Chain.getValue(1);
2172 // If we are tail calling and generating PIC/GOT style code load the
2173 // address of the callee into ECX. The value in ecx is used as target of
2174 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2175 // for tail calls on PIC/GOT architectures. Normally we would just put the
2176 // address of GOT into ebx and then call target@PLT. But for tail calls
2177 // ebx would be restored (since ebx is callee saved) before jumping to the
2180 // Note: The actual moving to ECX is done further down.
2181 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2182 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2183 !G->getGlobal()->hasProtectedVisibility())
2184 Callee = LowerGlobalAddress(Callee, DAG);
2185 else if (isa<ExternalSymbolSDNode>(Callee))
2186 Callee = LowerExternalSymbol(Callee, DAG);
2190 if (Is64Bit && isVarArg && !IsWin64) {
2191 // From AMD64 ABI document:
2192 // For calls that may call functions that use varargs or stdargs
2193 // (prototype-less calls or calls to functions containing ellipsis (...) in
2194 // the declaration) %al is used as hidden argument to specify the number
2195 // of SSE registers used. The contents of %al do not need to match exactly
2196 // the number of registers, but must be an ubound on the number of SSE
2197 // registers used and is in the range 0 - 8 inclusive.
2199 // Count the number of XMM registers allocated.
2200 static const unsigned XMMArgRegs[] = {
2201 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2202 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2204 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2205 assert((Subtarget->hasXMM() || !NumXMMRegs)
2206 && "SSE registers cannot be used when SSE is disabled");
2208 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2209 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2210 InFlag = Chain.getValue(1);
2214 // For tail calls lower the arguments to the 'real' stack slot.
2216 // Force all the incoming stack arguments to be loaded from the stack
2217 // before any new outgoing arguments are stored to the stack, because the
2218 // outgoing stack slots may alias the incoming argument stack slots, and
2219 // the alias isn't otherwise explicit. This is slightly more conservative
2220 // than necessary, because it means that each store effectively depends
2221 // on every argument instead of just those arguments it would clobber.
2222 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2224 SmallVector<SDValue, 8> MemOpChains2;
2227 // Do not flag preceding copytoreg stuff together with the following stuff.
2229 if (GuaranteedTailCallOpt) {
2230 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2231 CCValAssign &VA = ArgLocs[i];
2234 assert(VA.isMemLoc());
2235 SDValue Arg = OutVals[i];
2236 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2237 // Create frame index.
2238 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2239 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2240 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2241 FIN = DAG.getFrameIndex(FI, getPointerTy());
2243 if (Flags.isByVal()) {
2244 // Copy relative to framepointer.
2245 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2246 if (StackPtr.getNode() == 0)
2247 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2249 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2251 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2255 // Store relative to framepointer.
2256 MemOpChains2.push_back(
2257 DAG.getStore(ArgChain, dl, Arg, FIN,
2258 MachinePointerInfo::getFixedStack(FI),
2264 if (!MemOpChains2.empty())
2265 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2266 &MemOpChains2[0], MemOpChains2.size());
2268 // Copy arguments to their registers.
2269 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2270 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2271 RegsToPass[i].second, InFlag);
2272 InFlag = Chain.getValue(1);
2276 // Store the return address to the appropriate stack slot.
2277 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2281 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2282 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2283 // In the 64-bit large code model, we have to make all calls
2284 // through a register, since the call instruction's 32-bit
2285 // pc-relative offset may not be large enough to hold the whole
2287 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2288 // If the callee is a GlobalAddress node (quite common, every direct call
2289 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2292 // We should use extra load for direct calls to dllimported functions in
2294 const GlobalValue *GV = G->getGlobal();
2295 if (!GV->hasDLLImportLinkage()) {
2296 unsigned char OpFlags = 0;
2297 bool ExtraLoad = false;
2298 unsigned WrapperKind = ISD::DELETED_NODE;
2300 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2301 // external symbols most go through the PLT in PIC mode. If the symbol
2302 // has hidden or protected visibility, or if it is static or local, then
2303 // we don't need to use the PLT - we can directly call it.
2304 if (Subtarget->isTargetELF() &&
2305 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2306 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2307 OpFlags = X86II::MO_PLT;
2308 } else if (Subtarget->isPICStyleStubAny() &&
2309 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2310 (!Subtarget->getTargetTriple().isMacOSX() ||
2311 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2312 // PC-relative references to external symbols should go through $stub,
2313 // unless we're building with the leopard linker or later, which
2314 // automatically synthesizes these stubs.
2315 OpFlags = X86II::MO_DARWIN_STUB;
2316 } else if (Subtarget->isPICStyleRIPRel() &&
2317 isa<Function>(GV) &&
2318 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2319 // If the function is marked as non-lazy, generate an indirect call
2320 // which loads from the GOT directly. This avoids runtime overhead
2321 // at the cost of eager binding (and one extra byte of encoding).
2322 OpFlags = X86II::MO_GOTPCREL;
2323 WrapperKind = X86ISD::WrapperRIP;
2327 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2328 G->getOffset(), OpFlags);
2330 // Add a wrapper if needed.
2331 if (WrapperKind != ISD::DELETED_NODE)
2332 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2333 // Add extra indirection if needed.
2335 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2336 MachinePointerInfo::getGOT(),
2339 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2340 unsigned char OpFlags = 0;
2342 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2343 // external symbols should go through the PLT.
2344 if (Subtarget->isTargetELF() &&
2345 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2346 OpFlags = X86II::MO_PLT;
2347 } else if (Subtarget->isPICStyleStubAny() &&
2348 (!Subtarget->getTargetTriple().isMacOSX() ||
2349 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2350 // PC-relative references to external symbols should go through $stub,
2351 // unless we're building with the leopard linker or later, which
2352 // automatically synthesizes these stubs.
2353 OpFlags = X86II::MO_DARWIN_STUB;
2356 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2360 // Returns a chain & a flag for retval copy to use.
2361 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2362 SmallVector<SDValue, 8> Ops;
2364 if (!IsSibcall && isTailCall) {
2365 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2366 DAG.getIntPtrConstant(0, true), InFlag);
2367 InFlag = Chain.getValue(1);
2370 Ops.push_back(Chain);
2371 Ops.push_back(Callee);
2374 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2376 // Add argument registers to the end of the list so that they are known live
2378 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2379 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2380 RegsToPass[i].second.getValueType()));
2382 // Add an implicit use GOT pointer in EBX.
2383 if (!isTailCall && Subtarget->isPICStyleGOT())
2384 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2386 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2387 if (Is64Bit && isVarArg && !IsWin64)
2388 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2390 if (InFlag.getNode())
2391 Ops.push_back(InFlag);
2395 //// If this is the first return lowered for this function, add the regs
2396 //// to the liveout set for the function.
2397 // This isn't right, although it's probably harmless on x86; liveouts
2398 // should be computed from returns not tail calls. Consider a void
2399 // function making a tail call to a function returning int.
2400 return DAG.getNode(X86ISD::TC_RETURN, dl,
2401 NodeTys, &Ops[0], Ops.size());
2404 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2405 InFlag = Chain.getValue(1);
2407 // Create the CALLSEQ_END node.
2408 unsigned NumBytesForCalleeToPush;
2409 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2410 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2411 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2412 // If this is a call to a struct-return function, the callee
2413 // pops the hidden struct pointer, so we have to push it back.
2414 // This is common for Darwin/X86, Linux & Mingw32 targets.
2415 NumBytesForCalleeToPush = 4;
2417 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2419 // Returns a flag for retval copy to use.
2421 Chain = DAG.getCALLSEQ_END(Chain,
2422 DAG.getIntPtrConstant(NumBytes, true),
2423 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2426 InFlag = Chain.getValue(1);
2429 // Handle result values, copying them out of physregs into vregs that we
2431 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2432 Ins, dl, DAG, InVals);
2436 //===----------------------------------------------------------------------===//
2437 // Fast Calling Convention (tail call) implementation
2438 //===----------------------------------------------------------------------===//
2440 // Like std call, callee cleans arguments, convention except that ECX is
2441 // reserved for storing the tail called function address. Only 2 registers are
2442 // free for argument passing (inreg). Tail call optimization is performed
2444 // * tailcallopt is enabled
2445 // * caller/callee are fastcc
2446 // On X86_64 architecture with GOT-style position independent code only local
2447 // (within module) calls are supported at the moment.
2448 // To keep the stack aligned according to platform abi the function
2449 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2450 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2451 // If a tail called function callee has more arguments than the caller the
2452 // caller needs to make sure that there is room to move the RETADDR to. This is
2453 // achieved by reserving an area the size of the argument delta right after the
2454 // original REtADDR, but before the saved framepointer or the spilled registers
2455 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2467 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2468 /// for a 16 byte align requirement.
2470 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2471 SelectionDAG& DAG) const {
2472 MachineFunction &MF = DAG.getMachineFunction();
2473 const TargetMachine &TM = MF.getTarget();
2474 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2475 unsigned StackAlignment = TFI.getStackAlignment();
2476 uint64_t AlignMask = StackAlignment - 1;
2477 int64_t Offset = StackSize;
2478 uint64_t SlotSize = TD->getPointerSize();
2479 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2480 // Number smaller than 12 so just add the difference.
2481 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2483 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2484 Offset = ((~AlignMask) & Offset) + StackAlignment +
2485 (StackAlignment-SlotSize);
2490 /// MatchingStackOffset - Return true if the given stack call argument is
2491 /// already available in the same position (relatively) of the caller's
2492 /// incoming argument stack.
2494 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2495 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2496 const X86InstrInfo *TII) {
2497 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2499 if (Arg.getOpcode() == ISD::CopyFromReg) {
2500 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2501 if (!TargetRegisterInfo::isVirtualRegister(VR))
2503 MachineInstr *Def = MRI->getVRegDef(VR);
2506 if (!Flags.isByVal()) {
2507 if (!TII->isLoadFromStackSlot(Def, FI))
2510 unsigned Opcode = Def->getOpcode();
2511 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2512 Def->getOperand(1).isFI()) {
2513 FI = Def->getOperand(1).getIndex();
2514 Bytes = Flags.getByValSize();
2518 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2519 if (Flags.isByVal())
2520 // ByVal argument is passed in as a pointer but it's now being
2521 // dereferenced. e.g.
2522 // define @foo(%struct.X* %A) {
2523 // tail call @bar(%struct.X* byval %A)
2526 SDValue Ptr = Ld->getBasePtr();
2527 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2530 FI = FINode->getIndex();
2531 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2532 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2533 FI = FINode->getIndex();
2534 Bytes = Flags.getByValSize();
2538 assert(FI != INT_MAX);
2539 if (!MFI->isFixedObjectIndex(FI))
2541 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2544 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2545 /// for tail call optimization. Targets which want to do tail call
2546 /// optimization should implement this function.
2548 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2549 CallingConv::ID CalleeCC,
2551 bool isCalleeStructRet,
2552 bool isCallerStructRet,
2553 const SmallVectorImpl<ISD::OutputArg> &Outs,
2554 const SmallVectorImpl<SDValue> &OutVals,
2555 const SmallVectorImpl<ISD::InputArg> &Ins,
2556 SelectionDAG& DAG) const {
2557 if (!IsTailCallConvention(CalleeCC) &&
2558 CalleeCC != CallingConv::C)
2561 // If -tailcallopt is specified, make fastcc functions tail-callable.
2562 const MachineFunction &MF = DAG.getMachineFunction();
2563 const Function *CallerF = DAG.getMachineFunction().getFunction();
2564 CallingConv::ID CallerCC = CallerF->getCallingConv();
2565 bool CCMatch = CallerCC == CalleeCC;
2567 if (GuaranteedTailCallOpt) {
2568 if (IsTailCallConvention(CalleeCC) && CCMatch)
2573 // Look for obvious safe cases to perform tail call optimization that do not
2574 // require ABI changes. This is what gcc calls sibcall.
2576 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2577 // emit a special epilogue.
2578 if (RegInfo->needsStackRealignment(MF))
2581 // Also avoid sibcall optimization if either caller or callee uses struct
2582 // return semantics.
2583 if (isCalleeStructRet || isCallerStructRet)
2586 // An stdcall caller is expected to clean up its arguments; the callee
2587 // isn't going to do that.
2588 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2591 // Do not sibcall optimize vararg calls unless all arguments are passed via
2593 if (isVarArg && !Outs.empty()) {
2595 // Optimizing for varargs on Win64 is unlikely to be safe without
2596 // additional testing.
2597 if (Subtarget->isTargetWin64())
2600 SmallVector<CCValAssign, 16> ArgLocs;
2601 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2602 getTargetMachine(), ArgLocs, *DAG.getContext());
2604 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2605 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2606 if (!ArgLocs[i].isRegLoc())
2610 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2611 // Therefore if it's not used by the call it is not safe to optimize this into
2613 bool Unused = false;
2614 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2621 SmallVector<CCValAssign, 16> RVLocs;
2622 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2623 getTargetMachine(), RVLocs, *DAG.getContext());
2624 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2625 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2626 CCValAssign &VA = RVLocs[i];
2627 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2632 // If the calling conventions do not match, then we'd better make sure the
2633 // results are returned in the same way as what the caller expects.
2635 SmallVector<CCValAssign, 16> RVLocs1;
2636 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2637 getTargetMachine(), RVLocs1, *DAG.getContext());
2638 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2640 SmallVector<CCValAssign, 16> RVLocs2;
2641 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2642 getTargetMachine(), RVLocs2, *DAG.getContext());
2643 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2645 if (RVLocs1.size() != RVLocs2.size())
2647 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2648 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2650 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2652 if (RVLocs1[i].isRegLoc()) {
2653 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2656 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2662 // If the callee takes no arguments then go on to check the results of the
2664 if (!Outs.empty()) {
2665 // Check if stack adjustment is needed. For now, do not do this if any
2666 // argument is passed on the stack.
2667 SmallVector<CCValAssign, 16> ArgLocs;
2668 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2669 getTargetMachine(), ArgLocs, *DAG.getContext());
2671 // Allocate shadow area for Win64
2672 if (Subtarget->isTargetWin64()) {
2673 CCInfo.AllocateStack(32, 8);
2676 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2677 if (CCInfo.getNextStackOffset()) {
2678 MachineFunction &MF = DAG.getMachineFunction();
2679 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2682 // Check if the arguments are already laid out in the right way as
2683 // the caller's fixed stack objects.
2684 MachineFrameInfo *MFI = MF.getFrameInfo();
2685 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2686 const X86InstrInfo *TII =
2687 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2688 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2689 CCValAssign &VA = ArgLocs[i];
2690 SDValue Arg = OutVals[i];
2691 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2692 if (VA.getLocInfo() == CCValAssign::Indirect)
2694 if (!VA.isRegLoc()) {
2695 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2702 // If the tailcall address may be in a register, then make sure it's
2703 // possible to register allocate for it. In 32-bit, the call address can
2704 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2705 // callee-saved registers are restored. These happen to be the same
2706 // registers used to pass 'inreg' arguments so watch out for those.
2707 if (!Subtarget->is64Bit() &&
2708 !isa<GlobalAddressSDNode>(Callee) &&
2709 !isa<ExternalSymbolSDNode>(Callee)) {
2710 unsigned NumInRegs = 0;
2711 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2712 CCValAssign &VA = ArgLocs[i];
2715 unsigned Reg = VA.getLocReg();
2718 case X86::EAX: case X86::EDX: case X86::ECX:
2719 if (++NumInRegs == 3)
2731 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2732 return X86::createFastISel(funcInfo);
2736 //===----------------------------------------------------------------------===//
2737 // Other Lowering Hooks
2738 //===----------------------------------------------------------------------===//
2740 static bool MayFoldLoad(SDValue Op) {
2741 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2744 static bool MayFoldIntoStore(SDValue Op) {
2745 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2748 static bool isTargetShuffle(unsigned Opcode) {
2750 default: return false;
2751 case X86ISD::PSHUFD:
2752 case X86ISD::PSHUFHW:
2753 case X86ISD::PSHUFLW:
2754 case X86ISD::SHUFPD:
2755 case X86ISD::PALIGN:
2756 case X86ISD::SHUFPS:
2757 case X86ISD::MOVLHPS:
2758 case X86ISD::MOVLHPD:
2759 case X86ISD::MOVHLPS:
2760 case X86ISD::MOVLPS:
2761 case X86ISD::MOVLPD:
2762 case X86ISD::MOVSHDUP:
2763 case X86ISD::MOVSLDUP:
2764 case X86ISD::MOVDDUP:
2767 case X86ISD::UNPCKLPS:
2768 case X86ISD::UNPCKLPD:
2769 case X86ISD::VUNPCKLPSY:
2770 case X86ISD::VUNPCKLPDY:
2771 case X86ISD::PUNPCKLWD:
2772 case X86ISD::PUNPCKLBW:
2773 case X86ISD::PUNPCKLDQ:
2774 case X86ISD::PUNPCKLQDQ:
2775 case X86ISD::UNPCKHPS:
2776 case X86ISD::UNPCKHPD:
2777 case X86ISD::VUNPCKHPSY:
2778 case X86ISD::VUNPCKHPDY:
2779 case X86ISD::PUNPCKHWD:
2780 case X86ISD::PUNPCKHBW:
2781 case X86ISD::PUNPCKHDQ:
2782 case X86ISD::PUNPCKHQDQ:
2783 case X86ISD::VPERMILPS:
2784 case X86ISD::VPERMILPSY:
2785 case X86ISD::VPERMILPD:
2786 case X86ISD::VPERMILPDY:
2787 case X86ISD::VPERM2F128:
2793 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2794 SDValue V1, SelectionDAG &DAG) {
2796 default: llvm_unreachable("Unknown x86 shuffle node");
2797 case X86ISD::MOVSHDUP:
2798 case X86ISD::MOVSLDUP:
2799 case X86ISD::MOVDDUP:
2800 return DAG.getNode(Opc, dl, VT, V1);
2806 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2807 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2809 default: llvm_unreachable("Unknown x86 shuffle node");
2810 case X86ISD::PSHUFD:
2811 case X86ISD::PSHUFHW:
2812 case X86ISD::PSHUFLW:
2813 case X86ISD::VPERMILPS:
2814 case X86ISD::VPERMILPSY:
2815 case X86ISD::VPERMILPD:
2816 case X86ISD::VPERMILPDY:
2817 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2823 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2824 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2826 default: llvm_unreachable("Unknown x86 shuffle node");
2827 case X86ISD::PALIGN:
2828 case X86ISD::SHUFPD:
2829 case X86ISD::SHUFPS:
2830 case X86ISD::VPERM2F128:
2831 return DAG.getNode(Opc, dl, VT, V1, V2,
2832 DAG.getConstant(TargetMask, MVT::i8));
2837 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2838 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2840 default: llvm_unreachable("Unknown x86 shuffle node");
2841 case X86ISD::MOVLHPS:
2842 case X86ISD::MOVLHPD:
2843 case X86ISD::MOVHLPS:
2844 case X86ISD::MOVLPS:
2845 case X86ISD::MOVLPD:
2848 case X86ISD::UNPCKLPS:
2849 case X86ISD::UNPCKLPD:
2850 case X86ISD::VUNPCKLPSY:
2851 case X86ISD::VUNPCKLPDY:
2852 case X86ISD::PUNPCKLWD:
2853 case X86ISD::PUNPCKLBW:
2854 case X86ISD::PUNPCKLDQ:
2855 case X86ISD::PUNPCKLQDQ:
2856 case X86ISD::UNPCKHPS:
2857 case X86ISD::UNPCKHPD:
2858 case X86ISD::VUNPCKHPSY:
2859 case X86ISD::VUNPCKHPDY:
2860 case X86ISD::PUNPCKHWD:
2861 case X86ISD::PUNPCKHBW:
2862 case X86ISD::PUNPCKHDQ:
2863 case X86ISD::PUNPCKHQDQ:
2864 return DAG.getNode(Opc, dl, VT, V1, V2);
2869 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2870 MachineFunction &MF = DAG.getMachineFunction();
2871 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2872 int ReturnAddrIndex = FuncInfo->getRAIndex();
2874 if (ReturnAddrIndex == 0) {
2875 // Set up a frame object for the return address.
2876 uint64_t SlotSize = TD->getPointerSize();
2877 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2879 FuncInfo->setRAIndex(ReturnAddrIndex);
2882 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2886 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2887 bool hasSymbolicDisplacement) {
2888 // Offset should fit into 32 bit immediate field.
2889 if (!isInt<32>(Offset))
2892 // If we don't have a symbolic displacement - we don't have any extra
2894 if (!hasSymbolicDisplacement)
2897 // FIXME: Some tweaks might be needed for medium code model.
2898 if (M != CodeModel::Small && M != CodeModel::Kernel)
2901 // For small code model we assume that latest object is 16MB before end of 31
2902 // bits boundary. We may also accept pretty large negative constants knowing
2903 // that all objects are in the positive half of address space.
2904 if (M == CodeModel::Small && Offset < 16*1024*1024)
2907 // For kernel code model we know that all object resist in the negative half
2908 // of 32bits address space. We may not accept negative offsets, since they may
2909 // be just off and we may accept pretty large positive ones.
2910 if (M == CodeModel::Kernel && Offset > 0)
2916 /// isCalleePop - Determines whether the callee is required to pop its
2917 /// own arguments. Callee pop is necessary to support tail calls.
2918 bool X86::isCalleePop(CallingConv::ID CallingConv,
2919 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2923 switch (CallingConv) {
2926 case CallingConv::X86_StdCall:
2928 case CallingConv::X86_FastCall:
2930 case CallingConv::X86_ThisCall:
2932 case CallingConv::Fast:
2934 case CallingConv::GHC:
2939 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2940 /// specific condition code, returning the condition code and the LHS/RHS of the
2941 /// comparison to make.
2942 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2943 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2945 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2946 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2947 // X > -1 -> X == 0, jump !sign.
2948 RHS = DAG.getConstant(0, RHS.getValueType());
2949 return X86::COND_NS;
2950 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2951 // X < 0 -> X == 0, jump on sign.
2953 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2955 RHS = DAG.getConstant(0, RHS.getValueType());
2956 return X86::COND_LE;
2960 switch (SetCCOpcode) {
2961 default: llvm_unreachable("Invalid integer condition!");
2962 case ISD::SETEQ: return X86::COND_E;
2963 case ISD::SETGT: return X86::COND_G;
2964 case ISD::SETGE: return X86::COND_GE;
2965 case ISD::SETLT: return X86::COND_L;
2966 case ISD::SETLE: return X86::COND_LE;
2967 case ISD::SETNE: return X86::COND_NE;
2968 case ISD::SETULT: return X86::COND_B;
2969 case ISD::SETUGT: return X86::COND_A;
2970 case ISD::SETULE: return X86::COND_BE;
2971 case ISD::SETUGE: return X86::COND_AE;
2975 // First determine if it is required or is profitable to flip the operands.
2977 // If LHS is a foldable load, but RHS is not, flip the condition.
2978 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
2979 !ISD::isNON_EXTLoad(RHS.getNode())) {
2980 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2981 std::swap(LHS, RHS);
2984 switch (SetCCOpcode) {
2990 std::swap(LHS, RHS);
2994 // On a floating point condition, the flags are set as follows:
2996 // 0 | 0 | 0 | X > Y
2997 // 0 | 0 | 1 | X < Y
2998 // 1 | 0 | 0 | X == Y
2999 // 1 | 1 | 1 | unordered
3000 switch (SetCCOpcode) {
3001 default: llvm_unreachable("Condcode should be pre-legalized away");
3003 case ISD::SETEQ: return X86::COND_E;
3004 case ISD::SETOLT: // flipped
3006 case ISD::SETGT: return X86::COND_A;
3007 case ISD::SETOLE: // flipped
3009 case ISD::SETGE: return X86::COND_AE;
3010 case ISD::SETUGT: // flipped
3012 case ISD::SETLT: return X86::COND_B;
3013 case ISD::SETUGE: // flipped
3015 case ISD::SETLE: return X86::COND_BE;
3017 case ISD::SETNE: return X86::COND_NE;
3018 case ISD::SETUO: return X86::COND_P;
3019 case ISD::SETO: return X86::COND_NP;
3021 case ISD::SETUNE: return X86::COND_INVALID;
3025 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3026 /// code. Current x86 isa includes the following FP cmov instructions:
3027 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3028 static bool hasFPCMov(unsigned X86CC) {
3044 /// isFPImmLegal - Returns true if the target can instruction select the
3045 /// specified FP immediate natively. If false, the legalizer will
3046 /// materialize the FP immediate as a load from a constant pool.
3047 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3048 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3049 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3055 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3056 /// the specified range (L, H].
3057 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3058 return (Val < 0) || (Val >= Low && Val < Hi);
3061 /// isUndefOrInRange - Return true if every element in Mask, begining
3062 /// from position Pos and ending in Pos+Size, falls within the specified
3063 /// range (L, L+Pos]. or is undef.
3064 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3065 int Pos, int Size, int Low, int Hi) {
3066 for (int i = Pos, e = Pos+Size; i != e; ++i)
3067 if (!isUndefOrInRange(Mask[i], Low, Hi))
3072 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3073 /// specified value.
3074 static bool isUndefOrEqual(int Val, int CmpVal) {
3075 if (Val < 0 || Val == CmpVal)
3080 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3081 /// from position Pos and ending in Pos+Size, falls within the specified
3082 /// sequential range (L, L+Pos]. or is undef.
3083 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3084 int Pos, int Size, int Low) {
3085 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3086 if (!isUndefOrEqual(Mask[i], Low))
3091 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3092 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3093 /// the second operand.
3094 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3095 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3096 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3097 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3098 return (Mask[0] < 2 && Mask[1] < 2);
3102 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3103 SmallVector<int, 8> M;
3105 return ::isPSHUFDMask(M, N->getValueType(0));
3108 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3109 /// is suitable for input to PSHUFHW.
3110 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3111 if (VT != MVT::v8i16)
3114 // Lower quadword copied in order or undef.
3115 for (int i = 0; i != 4; ++i)
3116 if (Mask[i] >= 0 && Mask[i] != i)
3119 // Upper quadword shuffled.
3120 for (int i = 4; i != 8; ++i)
3121 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3127 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3128 SmallVector<int, 8> M;
3130 return ::isPSHUFHWMask(M, N->getValueType(0));
3133 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3134 /// is suitable for input to PSHUFLW.
3135 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3136 if (VT != MVT::v8i16)
3139 // Upper quadword copied in order.
3140 for (int i = 4; i != 8; ++i)
3141 if (Mask[i] >= 0 && Mask[i] != i)
3144 // Lower quadword shuffled.
3145 for (int i = 0; i != 4; ++i)
3152 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3153 SmallVector<int, 8> M;
3155 return ::isPSHUFLWMask(M, N->getValueType(0));
3158 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3159 /// is suitable for input to PALIGNR.
3160 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3162 int i, e = VT.getVectorNumElements();
3163 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64)
3166 // Do not handle v2i64 / v2f64 shuffles with palignr.
3167 if (e < 4 || !hasSSSE3)
3170 for (i = 0; i != e; ++i)
3174 // All undef, not a palignr.
3178 // Make sure we're shifting in the right direction.
3182 int s = Mask[i] - i;
3184 // Check the rest of the elements to see if they are consecutive.
3185 for (++i; i != e; ++i) {
3187 if (m >= 0 && m != s+i)
3193 /// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand
3194 /// specifies a shuffle of elements that is suitable for input to 256-bit
3196 static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3197 const X86Subtarget *Subtarget) {
3198 int NumElems = VT.getVectorNumElements();
3200 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3206 // VSHUFPSY divides the resulting vector into 4 chunks.
3207 // The sources are also splitted into 4 chunks, and each destination
3208 // chunk must come from a different source chunk.
3210 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3211 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3213 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3214 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3216 int QuarterSize = NumElems/4;
3217 int HalfSize = QuarterSize*2;
3218 for (int i = 0; i < QuarterSize; ++i)
3219 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3221 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3222 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3225 // The mask of the second half must be the same as the first but with
3226 // the appropriate offsets. This works in the same way as VPERMILPS
3227 // works with masks.
3228 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) {
3229 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3231 int FstHalfIdx = i-HalfSize;
3232 if (Mask[FstHalfIdx] < 0)
3234 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3237 for (int i = QuarterSize*3; i < NumElems; ++i) {
3238 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3240 int FstHalfIdx = i-HalfSize;
3241 if (Mask[FstHalfIdx] < 0)
3243 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3251 /// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle
3252 /// the specified VECTOR_MASK mask with VSHUFPSY instruction.
3253 static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) {
3254 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3255 EVT VT = SVOp->getValueType(0);
3256 int NumElems = VT.getVectorNumElements();
3258 assert(NumElems == 8 && VT.getSizeInBits() == 256 &&
3259 "Only supports v8i32 and v8f32 types");
3261 int HalfSize = NumElems/2;
3263 for (int i = 0; i != NumElems ; ++i) {
3264 if (SVOp->getMaskElt(i) < 0)
3266 // The mask of the first half must be equal to the second one.
3267 unsigned Shamt = (i%HalfSize)*2;
3268 unsigned Elt = SVOp->getMaskElt(i) % HalfSize;
3269 Mask |= Elt << Shamt;
3275 /// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand
3276 /// specifies a shuffle of elements that is suitable for input to 256-bit
3277 /// VSHUFPDY. This shuffle doesn't have the same restriction as the PS
3278 /// version and the mask of the second half isn't binded with the first
3280 static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3281 const X86Subtarget *Subtarget) {
3282 int NumElems = VT.getVectorNumElements();
3284 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3290 // VSHUFPSY divides the resulting vector into 4 chunks.
3291 // The sources are also splitted into 4 chunks, and each destination
3292 // chunk must come from a different source chunk.
3294 // SRC1 => X3 X2 X1 X0
3295 // SRC2 => Y3 Y2 Y1 Y0
3297 // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0
3299 int QuarterSize = NumElems/4;
3300 int HalfSize = QuarterSize*2;
3301 for (int i = 0; i < QuarterSize; ++i)
3302 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3304 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3305 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3307 for (int i = QuarterSize*2; i < QuarterSize*3; ++i)
3308 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3310 for (int i = QuarterSize*3; i < NumElems; ++i)
3311 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3317 /// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle
3318 /// the specified VECTOR_MASK mask with VSHUFPDY instruction.
3319 static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) {
3320 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3321 EVT VT = SVOp->getValueType(0);
3322 int NumElems = VT.getVectorNumElements();
3324 assert(NumElems == 4 && VT.getSizeInBits() == 256 &&
3325 "Only supports v4i64 and v4f64 types");
3327 int HalfSize = NumElems/2;
3329 for (int i = 0; i != NumElems ; ++i) {
3330 if (SVOp->getMaskElt(i) < 0)
3332 int Elt = SVOp->getMaskElt(i) % HalfSize;
3339 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3340 /// specifies a shuffle of elements that is suitable for input to 128-bit
3341 /// SHUFPS and SHUFPD.
3342 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3343 int NumElems = VT.getVectorNumElements();
3345 if (VT.getSizeInBits() != 128)
3348 if (NumElems != 2 && NumElems != 4)
3351 int Half = NumElems / 2;
3352 for (int i = 0; i < Half; ++i)
3353 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3355 for (int i = Half; i < NumElems; ++i)
3356 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3362 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3363 SmallVector<int, 8> M;
3365 return ::isSHUFPMask(M, N->getValueType(0));
3368 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3369 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3370 /// half elements to come from vector 1 (which would equal the dest.) and
3371 /// the upper half to come from vector 2.
3372 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3373 int NumElems = VT.getVectorNumElements();
3375 if (NumElems != 2 && NumElems != 4)
3378 int Half = NumElems / 2;
3379 for (int i = 0; i < Half; ++i)
3380 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3382 for (int i = Half; i < NumElems; ++i)
3383 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3388 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3389 SmallVector<int, 8> M;
3391 return isCommutedSHUFPMask(M, N->getValueType(0));
3394 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3395 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3396 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3397 EVT VT = N->getValueType(0);
3398 unsigned NumElems = VT.getVectorNumElements();
3400 if (VT.getSizeInBits() != 128)
3406 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3407 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3408 isUndefOrEqual(N->getMaskElt(1), 7) &&
3409 isUndefOrEqual(N->getMaskElt(2), 2) &&
3410 isUndefOrEqual(N->getMaskElt(3), 3);
3413 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3414 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3416 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3417 EVT VT = N->getValueType(0);
3418 unsigned NumElems = VT.getVectorNumElements();
3420 if (VT.getSizeInBits() != 128)
3426 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3427 isUndefOrEqual(N->getMaskElt(1), 3) &&
3428 isUndefOrEqual(N->getMaskElt(2), 2) &&
3429 isUndefOrEqual(N->getMaskElt(3), 3);
3432 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3433 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3434 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3435 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3437 if (NumElems != 2 && NumElems != 4)
3440 for (unsigned i = 0; i < NumElems/2; ++i)
3441 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3444 for (unsigned i = NumElems/2; i < NumElems; ++i)
3445 if (!isUndefOrEqual(N->getMaskElt(i), i))
3451 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3452 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3453 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3454 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3456 if ((NumElems != 2 && NumElems != 4)
3457 || N->getValueType(0).getSizeInBits() > 128)
3460 for (unsigned i = 0; i < NumElems/2; ++i)
3461 if (!isUndefOrEqual(N->getMaskElt(i), i))
3464 for (unsigned i = 0; i < NumElems/2; ++i)
3465 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3471 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3472 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3473 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3474 bool V2IsSplat = false) {
3475 int NumElts = VT.getVectorNumElements();
3477 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3478 "Unsupported vector type for unpckh");
3480 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3483 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3484 // independently on 128-bit lanes.
3485 unsigned NumLanes = VT.getSizeInBits()/128;
3486 unsigned NumLaneElts = NumElts/NumLanes;
3489 unsigned End = NumLaneElts;
3490 for (unsigned s = 0; s < NumLanes; ++s) {
3491 for (unsigned i = Start, j = s * NumLaneElts;
3495 int BitI1 = Mask[i+1];
3496 if (!isUndefOrEqual(BitI, j))
3499 if (!isUndefOrEqual(BitI1, NumElts))
3502 if (!isUndefOrEqual(BitI1, j + NumElts))
3506 // Process the next 128 bits.
3507 Start += NumLaneElts;
3514 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3515 SmallVector<int, 8> M;
3517 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3520 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3521 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3522 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3523 bool V2IsSplat = false) {
3524 int NumElts = VT.getVectorNumElements();
3526 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3527 "Unsupported vector type for unpckh");
3529 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3532 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3533 // independently on 128-bit lanes.
3534 unsigned NumLanes = VT.getSizeInBits()/128;
3535 unsigned NumLaneElts = NumElts/NumLanes;
3538 unsigned End = NumLaneElts;
3539 for (unsigned l = 0; l != NumLanes; ++l) {
3540 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3541 i != End; i += 2, ++j) {
3543 int BitI1 = Mask[i+1];
3544 if (!isUndefOrEqual(BitI, j))
3547 if (isUndefOrEqual(BitI1, NumElts))
3550 if (!isUndefOrEqual(BitI1, j+NumElts))
3554 // Process the next 128 bits.
3555 Start += NumLaneElts;
3561 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3562 SmallVector<int, 8> M;
3564 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3567 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3568 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3570 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3571 int NumElems = VT.getVectorNumElements();
3572 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3575 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3576 // FIXME: Need a better way to get rid of this, there's no latency difference
3577 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3578 // the former later. We should also remove the "_undef" special mask.
3579 if (NumElems == 4 && VT.getSizeInBits() == 256)
3582 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3583 // independently on 128-bit lanes.
3584 unsigned NumLanes = VT.getSizeInBits() / 128;
3585 unsigned NumLaneElts = NumElems / NumLanes;
3587 for (unsigned s = 0; s < NumLanes; ++s) {
3588 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3589 i != NumLaneElts * (s + 1);
3592 int BitI1 = Mask[i+1];
3594 if (!isUndefOrEqual(BitI, j))
3596 if (!isUndefOrEqual(BitI1, j))
3604 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3605 SmallVector<int, 8> M;
3607 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3610 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3611 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3613 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3614 int NumElems = VT.getVectorNumElements();
3615 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3618 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3620 int BitI1 = Mask[i+1];
3621 if (!isUndefOrEqual(BitI, j))
3623 if (!isUndefOrEqual(BitI1, j))
3629 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3630 SmallVector<int, 8> M;
3632 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3635 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3636 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3637 /// MOVSD, and MOVD, i.e. setting the lowest element.
3638 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3639 if (VT.getVectorElementType().getSizeInBits() < 32)
3642 int NumElts = VT.getVectorNumElements();
3644 if (!isUndefOrEqual(Mask[0], NumElts))
3647 for (int i = 1; i < NumElts; ++i)
3648 if (!isUndefOrEqual(Mask[i], i))
3654 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3655 SmallVector<int, 8> M;
3657 return ::isMOVLMask(M, N->getValueType(0));
3660 /// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered
3661 /// as permutations between 128-bit chunks or halves. As an example: this
3663 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3664 /// The first half comes from the second half of V1 and the second half from the
3665 /// the second half of V2.
3666 static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3667 const X86Subtarget *Subtarget) {
3668 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3671 // The shuffle result is divided into half A and half B. In total the two
3672 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3673 // B must come from C, D, E or F.
3674 int HalfSize = VT.getVectorNumElements()/2;
3675 bool MatchA = false, MatchB = false;
3677 // Check if A comes from one of C, D, E, F.
3678 for (int Half = 0; Half < 4; ++Half) {
3679 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3685 // Check if B comes from one of C, D, E, F.
3686 for (int Half = 0; Half < 4; ++Half) {
3687 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3693 return MatchA && MatchB;
3696 /// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle
3697 /// the specified VECTOR_MASK mask with VPERM2F128 instructions.
3698 static unsigned getShuffleVPERM2F128Immediate(SDNode *N) {
3699 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3700 EVT VT = SVOp->getValueType(0);
3702 int HalfSize = VT.getVectorNumElements()/2;
3704 int FstHalf = 0, SndHalf = 0;
3705 for (int i = 0; i < HalfSize; ++i) {
3706 if (SVOp->getMaskElt(i) > 0) {
3707 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3711 for (int i = HalfSize; i < HalfSize*2; ++i) {
3712 if (SVOp->getMaskElt(i) > 0) {
3713 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3718 return (FstHalf | (SndHalf << 4));
3721 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3722 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3723 /// Note that VPERMIL mask matching is different depending whether theunderlying
3724 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3725 /// to the same elements of the low, but to the higher half of the source.
3726 /// In VPERMILPD the two lanes could be shuffled independently of each other
3727 /// with the same restriction that lanes can't be crossed.
3728 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
3729 const X86Subtarget *Subtarget) {
3730 int NumElts = VT.getVectorNumElements();
3731 int NumLanes = VT.getSizeInBits()/128;
3733 if (!Subtarget->hasAVX())
3736 // Match any permutation of 128-bit vector with 64-bit types
3737 if (NumLanes == 1 && NumElts != 2)
3740 // Only match 256-bit with 32 types
3741 if (VT.getSizeInBits() == 256 && NumElts != 4)
3744 // The mask on the high lane is independent of the low. Both can match
3745 // any element in inside its own lane, but can't cross.
3746 int LaneSize = NumElts/NumLanes;
3747 for (int l = 0; l < NumLanes; ++l)
3748 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3749 int LaneStart = l*LaneSize;
3750 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize))
3757 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3758 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*.
3759 /// Note that VPERMIL mask matching is different depending whether theunderlying
3760 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3761 /// to the same elements of the low, but to the higher half of the source.
3762 /// In VPERMILPD the two lanes could be shuffled independently of each other
3763 /// with the same restriction that lanes can't be crossed.
3764 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
3765 const X86Subtarget *Subtarget) {
3766 unsigned NumElts = VT.getVectorNumElements();
3767 unsigned NumLanes = VT.getSizeInBits()/128;
3769 if (!Subtarget->hasAVX())
3772 // Match any permutation of 128-bit vector with 32-bit types
3773 if (NumLanes == 1 && NumElts != 4)
3776 // Only match 256-bit with 32 types
3777 if (VT.getSizeInBits() == 256 && NumElts != 8)
3780 // The mask on the high lane should be the same as the low. Actually,
3781 // they can differ if any of the corresponding index in a lane is undef
3782 // and the other stays in range.
3783 int LaneSize = NumElts/NumLanes;
3784 for (int i = 0; i < LaneSize; ++i) {
3785 int HighElt = i+LaneSize;
3786 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts);
3787 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize);
3789 if (!HighValid || !LowValid)
3791 if (Mask[i] < 0 || Mask[HighElt] < 0)
3793 if (Mask[HighElt]-Mask[i] != LaneSize)
3800 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle
3801 /// the specified VECTOR_MASK mask with VPERMILPS* instructions.
3802 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) {
3803 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3804 EVT VT = SVOp->getValueType(0);
3806 int NumElts = VT.getVectorNumElements();
3807 int NumLanes = VT.getSizeInBits()/128;
3808 int LaneSize = NumElts/NumLanes;
3810 // Although the mask is equal for both lanes do it twice to get the cases
3811 // where a mask will match because the same mask element is undef on the
3812 // first half but valid on the second. This would get pathological cases
3813 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3815 for (int l = 0; l < NumLanes; ++l) {
3816 for (int i = 0; i < LaneSize; ++i) {
3817 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize));
3820 if (MaskElt >= LaneSize)
3821 MaskElt -= LaneSize;
3822 Mask |= MaskElt << (i*2);
3829 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle
3830 /// the specified VECTOR_MASK mask with VPERMILPD* instructions.
3831 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) {
3832 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3833 EVT VT = SVOp->getValueType(0);
3835 int NumElts = VT.getVectorNumElements();
3836 int NumLanes = VT.getSizeInBits()/128;
3839 int LaneSize = NumElts/NumLanes;
3840 for (int l = 0; l < NumLanes; ++l)
3841 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3842 int MaskElt = SVOp->getMaskElt(i);
3845 Mask |= (MaskElt-l*LaneSize) << i;
3851 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3852 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3853 /// element of vector 2 and the other elements to come from vector 1 in order.
3854 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3855 bool V2IsSplat = false, bool V2IsUndef = false) {
3856 int NumOps = VT.getVectorNumElements();
3857 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3860 if (!isUndefOrEqual(Mask[0], 0))
3863 for (int i = 1; i < NumOps; ++i)
3864 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3865 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3866 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3872 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3873 bool V2IsUndef = false) {
3874 SmallVector<int, 8> M;
3876 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3879 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3880 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3881 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3882 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3883 const X86Subtarget *Subtarget) {
3884 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3887 // The second vector must be undef
3888 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3891 EVT VT = N->getValueType(0);
3892 unsigned NumElems = VT.getVectorNumElements();
3894 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3895 (VT.getSizeInBits() == 256 && NumElems != 8))
3898 // "i+1" is the value the indexed mask element must have
3899 for (unsigned i = 0; i < NumElems; i += 2)
3900 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3901 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3907 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3908 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3909 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3910 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3911 const X86Subtarget *Subtarget) {
3912 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3915 // The second vector must be undef
3916 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3919 EVT VT = N->getValueType(0);
3920 unsigned NumElems = VT.getVectorNumElements();
3922 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3923 (VT.getSizeInBits() == 256 && NumElems != 8))
3926 // "i" is the value the indexed mask element must have
3927 for (unsigned i = 0; i < NumElems; i += 2)
3928 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3929 !isUndefOrEqual(N->getMaskElt(i+1), i))
3935 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3936 /// specifies a shuffle of elements that is suitable for input to 256-bit
3937 /// version of MOVDDUP.
3938 static bool isMOVDDUPYMask(ShuffleVectorSDNode *N,
3939 const X86Subtarget *Subtarget) {
3940 EVT VT = N->getValueType(0);
3941 int NumElts = VT.getVectorNumElements();
3942 bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF;
3944 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 ||
3945 !V2IsUndef || NumElts != 4)
3948 for (int i = 0; i != NumElts/2; ++i)
3949 if (!isUndefOrEqual(N->getMaskElt(i), 0))
3951 for (int i = NumElts/2; i != NumElts; ++i)
3952 if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2))
3957 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3958 /// specifies a shuffle of elements that is suitable for input to 128-bit
3959 /// version of MOVDDUP.
3960 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3961 EVT VT = N->getValueType(0);
3963 if (VT.getSizeInBits() != 128)
3966 int e = VT.getVectorNumElements() / 2;
3967 for (int i = 0; i < e; ++i)
3968 if (!isUndefOrEqual(N->getMaskElt(i), i))
3970 for (int i = 0; i < e; ++i)
3971 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3976 /// isVEXTRACTF128Index - Return true if the specified
3977 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3978 /// suitable for input to VEXTRACTF128.
3979 bool X86::isVEXTRACTF128Index(SDNode *N) {
3980 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3983 // The index should be aligned on a 128-bit boundary.
3985 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3987 unsigned VL = N->getValueType(0).getVectorNumElements();
3988 unsigned VBits = N->getValueType(0).getSizeInBits();
3989 unsigned ElSize = VBits / VL;
3990 bool Result = (Index * ElSize) % 128 == 0;
3995 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3996 /// operand specifies a subvector insert that is suitable for input to
3998 bool X86::isVINSERTF128Index(SDNode *N) {
3999 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4002 // The index should be aligned on a 128-bit boundary.
4004 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4006 unsigned VL = N->getValueType(0).getVectorNumElements();
4007 unsigned VBits = N->getValueType(0).getSizeInBits();
4008 unsigned ElSize = VBits / VL;
4009 bool Result = (Index * ElSize) % 128 == 0;
4014 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4015 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4016 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
4017 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4018 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
4020 unsigned Shift = (NumOperands == 4) ? 2 : 1;
4022 for (int i = 0; i < NumOperands; ++i) {
4023 int Val = SVOp->getMaskElt(NumOperands-i-1);
4024 if (Val < 0) Val = 0;
4025 if (Val >= NumOperands) Val -= NumOperands;
4027 if (i != NumOperands - 1)
4033 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4034 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4035 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
4036 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4038 // 8 nodes, but we only care about the last 4.
4039 for (unsigned i = 7; i >= 4; --i) {
4040 int Val = SVOp->getMaskElt(i);
4049 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4050 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4051 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
4052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4054 // 8 nodes, but we only care about the first 4.
4055 for (int i = 3; i >= 0; --i) {
4056 int Val = SVOp->getMaskElt(i);
4065 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4066 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4067 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
4068 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4069 EVT VVT = N->getValueType(0);
4070 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
4074 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
4075 Val = SVOp->getMaskElt(i);
4079 assert(Val - i > 0 && "PALIGNR imm should be positive");
4080 return (Val - i) * EltSize;
4083 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4084 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4086 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4087 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4088 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4091 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4093 EVT VecVT = N->getOperand(0).getValueType();
4094 EVT ElVT = VecVT.getVectorElementType();
4096 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4097 return Index / NumElemsPerChunk;
4100 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4101 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4103 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4104 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4105 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4108 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4110 EVT VecVT = N->getValueType(0);
4111 EVT ElVT = VecVT.getVectorElementType();
4113 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4114 return Index / NumElemsPerChunk;
4117 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4119 bool X86::isZeroNode(SDValue Elt) {
4120 return ((isa<ConstantSDNode>(Elt) &&
4121 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4122 (isa<ConstantFPSDNode>(Elt) &&
4123 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4126 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4127 /// their permute mask.
4128 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4129 SelectionDAG &DAG) {
4130 EVT VT = SVOp->getValueType(0);
4131 unsigned NumElems = VT.getVectorNumElements();
4132 SmallVector<int, 8> MaskVec;
4134 for (unsigned i = 0; i != NumElems; ++i) {
4135 int idx = SVOp->getMaskElt(i);
4137 MaskVec.push_back(idx);
4138 else if (idx < (int)NumElems)
4139 MaskVec.push_back(idx + NumElems);
4141 MaskVec.push_back(idx - NumElems);
4143 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4144 SVOp->getOperand(0), &MaskVec[0]);
4147 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4148 /// the two vector operands have swapped position.
4149 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
4150 unsigned NumElems = VT.getVectorNumElements();
4151 for (unsigned i = 0; i != NumElems; ++i) {
4155 else if (idx < (int)NumElems)
4156 Mask[i] = idx + NumElems;
4158 Mask[i] = idx - NumElems;
4162 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4163 /// match movhlps. The lower half elements should come from upper half of
4164 /// V1 (and in order), and the upper half elements should come from the upper
4165 /// half of V2 (and in order).
4166 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4167 EVT VT = Op->getValueType(0);
4168 if (VT.getSizeInBits() != 128)
4170 if (VT.getVectorNumElements() != 4)
4172 for (unsigned i = 0, e = 2; i != e; ++i)
4173 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4175 for (unsigned i = 2; i != 4; ++i)
4176 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4181 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4182 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4184 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4185 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4187 N = N->getOperand(0).getNode();
4188 if (!ISD::isNON_EXTLoad(N))
4191 *LD = cast<LoadSDNode>(N);
4195 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4196 /// match movlp{s|d}. The lower half elements should come from lower half of
4197 /// V1 (and in order), and the upper half elements should come from the upper
4198 /// half of V2 (and in order). And since V1 will become the source of the
4199 /// MOVLP, it must be either a vector load or a scalar load to vector.
4200 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4201 ShuffleVectorSDNode *Op) {
4202 EVT VT = Op->getValueType(0);
4203 if (VT.getSizeInBits() != 128)
4206 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4208 // Is V2 is a vector load, don't do this transformation. We will try to use
4209 // load folding shufps op.
4210 if (ISD::isNON_EXTLoad(V2))
4213 unsigned NumElems = VT.getVectorNumElements();
4215 if (NumElems != 2 && NumElems != 4)
4217 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4218 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4220 for (unsigned i = NumElems/2; i != NumElems; ++i)
4221 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4226 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4228 static bool isSplatVector(SDNode *N) {
4229 if (N->getOpcode() != ISD::BUILD_VECTOR)
4232 SDValue SplatValue = N->getOperand(0);
4233 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4234 if (N->getOperand(i) != SplatValue)
4239 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4240 /// to an zero vector.
4241 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4242 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4243 SDValue V1 = N->getOperand(0);
4244 SDValue V2 = N->getOperand(1);
4245 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4246 for (unsigned i = 0; i != NumElems; ++i) {
4247 int Idx = N->getMaskElt(i);
4248 if (Idx >= (int)NumElems) {
4249 unsigned Opc = V2.getOpcode();
4250 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4252 if (Opc != ISD::BUILD_VECTOR ||
4253 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4255 } else if (Idx >= 0) {
4256 unsigned Opc = V1.getOpcode();
4257 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4259 if (Opc != ISD::BUILD_VECTOR ||
4260 !X86::isZeroNode(V1.getOperand(Idx)))
4267 /// getZeroVector - Returns a vector of specified type with all zero elements.
4269 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
4271 assert(VT.isVector() && "Expected a vector type");
4273 // Always build SSE zero vectors as <4 x i32> bitcasted
4274 // to their dest type. This ensures they get CSE'd.
4276 if (VT.getSizeInBits() == 128) { // SSE
4277 if (HasSSE2) { // SSE2
4278 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4279 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4281 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4282 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4284 } else if (VT.getSizeInBits() == 256) { // AVX
4285 // 256-bit logic and arithmetic instructions in AVX are
4286 // all floating-point, no support for integer ops. Default
4287 // to emitting fp zeroed vectors then.
4288 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4289 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4290 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4292 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4295 /// getOnesVector - Returns a vector of specified type with all bits set.
4296 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two
4297 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
4298 /// original type, ensuring they get CSE'd.
4299 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4300 assert(VT.isVector() && "Expected a vector type");
4301 assert((VT.is128BitVector() || VT.is256BitVector())
4302 && "Expected a 128-bit or 256-bit vector type");
4304 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4305 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
4306 Cst, Cst, Cst, Cst);
4308 if (VT.is256BitVector()) {
4309 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4310 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4311 Vec = Insert128BitVector(InsV, Vec,
4312 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4315 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4318 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4319 /// that point to V2 points to its first element.
4320 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4321 EVT VT = SVOp->getValueType(0);
4322 unsigned NumElems = VT.getVectorNumElements();
4324 bool Changed = false;
4325 SmallVector<int, 8> MaskVec;
4326 SVOp->getMask(MaskVec);
4328 for (unsigned i = 0; i != NumElems; ++i) {
4329 if (MaskVec[i] > (int)NumElems) {
4330 MaskVec[i] = NumElems;
4335 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4336 SVOp->getOperand(1), &MaskVec[0]);
4337 return SDValue(SVOp, 0);
4340 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4341 /// operation of specified width.
4342 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4344 unsigned NumElems = VT.getVectorNumElements();
4345 SmallVector<int, 8> Mask;
4346 Mask.push_back(NumElems);
4347 for (unsigned i = 1; i != NumElems; ++i)
4349 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4352 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4353 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4355 unsigned NumElems = VT.getVectorNumElements();
4356 SmallVector<int, 8> Mask;
4357 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4359 Mask.push_back(i + NumElems);
4361 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4364 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4365 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4367 unsigned NumElems = VT.getVectorNumElements();
4368 unsigned Half = NumElems/2;
4369 SmallVector<int, 8> Mask;
4370 for (unsigned i = 0; i != Half; ++i) {
4371 Mask.push_back(i + Half);
4372 Mask.push_back(i + NumElems + Half);
4374 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4377 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4378 // a generic shuffle instruction because the target has no such instructions.
4379 // Generate shuffles which repeat i16 and i8 several times until they can be
4380 // represented by v4f32 and then be manipulated by target suported shuffles.
4381 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4382 EVT VT = V.getValueType();
4383 int NumElems = VT.getVectorNumElements();
4384 DebugLoc dl = V.getDebugLoc();
4386 while (NumElems > 4) {
4387 if (EltNo < NumElems/2) {
4388 V = getUnpackl(DAG, dl, VT, V, V);
4390 V = getUnpackh(DAG, dl, VT, V, V);
4391 EltNo -= NumElems/2;
4398 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4399 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4400 EVT VT = V.getValueType();
4401 DebugLoc dl = V.getDebugLoc();
4402 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4403 && "Vector size not supported");
4405 if (VT.getSizeInBits() == 128) {
4406 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4407 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4408 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4411 // To use VPERMILPS to splat scalars, the second half of indicies must
4412 // refer to the higher part, which is a duplication of the lower one,
4413 // because VPERMILPS can only handle in-lane permutations.
4414 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4415 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4417 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4418 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4422 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4425 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4426 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4427 EVT SrcVT = SV->getValueType(0);
4428 SDValue V1 = SV->getOperand(0);
4429 DebugLoc dl = SV->getDebugLoc();
4431 int EltNo = SV->getSplatIndex();
4432 int NumElems = SrcVT.getVectorNumElements();
4433 unsigned Size = SrcVT.getSizeInBits();
4435 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4436 "Unknown how to promote splat for type");
4438 // Extract the 128-bit part containing the splat element and update
4439 // the splat element index when it refers to the higher register.
4441 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4442 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4444 EltNo -= NumElems/2;
4447 // All i16 and i8 vector types can't be used directly by a generic shuffle
4448 // instruction because the target has no such instruction. Generate shuffles
4449 // which repeat i16 and i8 several times until they fit in i32, and then can
4450 // be manipulated by target suported shuffles.
4451 EVT EltVT = SrcVT.getVectorElementType();
4452 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4453 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4455 // Recreate the 256-bit vector and place the same 128-bit vector
4456 // into the low and high part. This is necessary because we want
4457 // to use VPERM* to shuffle the vectors
4459 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4460 DAG.getConstant(0, MVT::i32), DAG, dl);
4461 V1 = Insert128BitVector(InsV, V1,
4462 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4465 return getLegalSplat(DAG, V1, EltNo);
4468 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4469 /// vector of zero or undef vector. This produces a shuffle where the low
4470 /// element of V2 is swizzled into the zero/undef vector, landing at element
4471 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4472 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4473 bool isZero, bool HasSSE2,
4474 SelectionDAG &DAG) {
4475 EVT VT = V2.getValueType();
4477 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4478 unsigned NumElems = VT.getVectorNumElements();
4479 SmallVector<int, 16> MaskVec;
4480 for (unsigned i = 0; i != NumElems; ++i)
4481 // If this is the insertion idx, put the low elt of V2 here.
4482 MaskVec.push_back(i == Idx ? NumElems : i);
4483 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4486 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4487 /// element of the result of the vector shuffle.
4488 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4491 return SDValue(); // Limit search depth.
4493 SDValue V = SDValue(N, 0);
4494 EVT VT = V.getValueType();
4495 unsigned Opcode = V.getOpcode();
4497 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4498 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4499 Index = SV->getMaskElt(Index);
4502 return DAG.getUNDEF(VT.getVectorElementType());
4504 int NumElems = VT.getVectorNumElements();
4505 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4506 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4509 // Recurse into target specific vector shuffles to find scalars.
4510 if (isTargetShuffle(Opcode)) {
4511 int NumElems = VT.getVectorNumElements();
4512 SmallVector<unsigned, 16> ShuffleMask;
4516 case X86ISD::SHUFPS:
4517 case X86ISD::SHUFPD:
4518 ImmN = N->getOperand(N->getNumOperands()-1);
4519 DecodeSHUFPSMask(NumElems,
4520 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4523 case X86ISD::PUNPCKHBW:
4524 case X86ISD::PUNPCKHWD:
4525 case X86ISD::PUNPCKHDQ:
4526 case X86ISD::PUNPCKHQDQ:
4527 DecodePUNPCKHMask(NumElems, ShuffleMask);
4529 case X86ISD::UNPCKHPS:
4530 case X86ISD::UNPCKHPD:
4531 case X86ISD::VUNPCKHPSY:
4532 case X86ISD::VUNPCKHPDY:
4533 DecodeUNPCKHPMask(NumElems, ShuffleMask);
4535 case X86ISD::PUNPCKLBW:
4536 case X86ISD::PUNPCKLWD:
4537 case X86ISD::PUNPCKLDQ:
4538 case X86ISD::PUNPCKLQDQ:
4539 DecodePUNPCKLMask(VT, ShuffleMask);
4541 case X86ISD::UNPCKLPS:
4542 case X86ISD::UNPCKLPD:
4543 case X86ISD::VUNPCKLPSY:
4544 case X86ISD::VUNPCKLPDY:
4545 DecodeUNPCKLPMask(VT, ShuffleMask);
4547 case X86ISD::MOVHLPS:
4548 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4550 case X86ISD::MOVLHPS:
4551 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4553 case X86ISD::PSHUFD:
4554 ImmN = N->getOperand(N->getNumOperands()-1);
4555 DecodePSHUFMask(NumElems,
4556 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4559 case X86ISD::PSHUFHW:
4560 ImmN = N->getOperand(N->getNumOperands()-1);
4561 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4564 case X86ISD::PSHUFLW:
4565 ImmN = N->getOperand(N->getNumOperands()-1);
4566 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4570 case X86ISD::MOVSD: {
4571 // The index 0 always comes from the first element of the second source,
4572 // this is why MOVSS and MOVSD are used in the first place. The other
4573 // elements come from the other positions of the first source vector.
4574 unsigned OpNum = (Index == 0) ? 1 : 0;
4575 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4578 case X86ISD::VPERMILPS:
4579 ImmN = N->getOperand(N->getNumOperands()-1);
4580 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4583 case X86ISD::VPERMILPSY:
4584 ImmN = N->getOperand(N->getNumOperands()-1);
4585 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4588 case X86ISD::VPERMILPD:
4589 ImmN = N->getOperand(N->getNumOperands()-1);
4590 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4593 case X86ISD::VPERMILPDY:
4594 ImmN = N->getOperand(N->getNumOperands()-1);
4595 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4598 case X86ISD::VPERM2F128:
4599 ImmN = N->getOperand(N->getNumOperands()-1);
4600 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4604 assert("not implemented for target shuffle node");
4608 Index = ShuffleMask[Index];
4610 return DAG.getUNDEF(VT.getVectorElementType());
4612 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4613 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4617 // Actual nodes that may contain scalar elements
4618 if (Opcode == ISD::BITCAST) {
4619 V = V.getOperand(0);
4620 EVT SrcVT = V.getValueType();
4621 unsigned NumElems = VT.getVectorNumElements();
4623 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4627 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4628 return (Index == 0) ? V.getOperand(0)
4629 : DAG.getUNDEF(VT.getVectorElementType());
4631 if (V.getOpcode() == ISD::BUILD_VECTOR)
4632 return V.getOperand(Index);
4637 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4638 /// shuffle operation which come from a consecutively from a zero. The
4639 /// search can start in two different directions, from left or right.
4641 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4642 bool ZerosFromLeft, SelectionDAG &DAG) {
4645 while (i < NumElems) {
4646 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4647 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4648 if (!(Elt.getNode() &&
4649 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4657 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4658 /// MaskE correspond consecutively to elements from one of the vector operands,
4659 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4661 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4662 int OpIdx, int NumElems, unsigned &OpNum) {
4663 bool SeenV1 = false;
4664 bool SeenV2 = false;
4666 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4667 int Idx = SVOp->getMaskElt(i);
4668 // Ignore undef indicies
4677 // Only accept consecutive elements from the same vector
4678 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4682 OpNum = SeenV1 ? 0 : 1;
4686 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4687 /// logical left shift of a vector.
4688 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4689 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4690 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4691 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4692 false /* check zeros from right */, DAG);
4698 // Considering the elements in the mask that are not consecutive zeros,
4699 // check if they consecutively come from only one of the source vectors.
4701 // V1 = {X, A, B, C} 0
4703 // vector_shuffle V1, V2 <1, 2, 3, X>
4705 if (!isShuffleMaskConsecutive(SVOp,
4706 0, // Mask Start Index
4707 NumElems-NumZeros-1, // Mask End Index
4708 NumZeros, // Where to start looking in the src vector
4709 NumElems, // Number of elements in vector
4710 OpSrc)) // Which source operand ?
4715 ShVal = SVOp->getOperand(OpSrc);
4719 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4720 /// logical left shift of a vector.
4721 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4722 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4723 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4724 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4725 true /* check zeros from left */, DAG);
4731 // Considering the elements in the mask that are not consecutive zeros,
4732 // check if they consecutively come from only one of the source vectors.
4734 // 0 { A, B, X, X } = V2
4736 // vector_shuffle V1, V2 <X, X, 4, 5>
4738 if (!isShuffleMaskConsecutive(SVOp,
4739 NumZeros, // Mask Start Index
4740 NumElems-1, // Mask End Index
4741 0, // Where to start looking in the src vector
4742 NumElems, // Number of elements in vector
4743 OpSrc)) // Which source operand ?
4748 ShVal = SVOp->getOperand(OpSrc);
4752 /// isVectorShift - Returns true if the shuffle can be implemented as a
4753 /// logical left or right shift of a vector.
4754 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4755 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4756 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4757 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4763 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4765 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4766 unsigned NumNonZero, unsigned NumZero,
4768 const TargetLowering &TLI) {
4772 DebugLoc dl = Op.getDebugLoc();
4775 for (unsigned i = 0; i < 16; ++i) {
4776 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4777 if (ThisIsNonZero && First) {
4779 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4781 V = DAG.getUNDEF(MVT::v8i16);
4786 SDValue ThisElt(0, 0), LastElt(0, 0);
4787 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4788 if (LastIsNonZero) {
4789 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4790 MVT::i16, Op.getOperand(i-1));
4792 if (ThisIsNonZero) {
4793 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4794 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4795 ThisElt, DAG.getConstant(8, MVT::i8));
4797 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4801 if (ThisElt.getNode())
4802 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4803 DAG.getIntPtrConstant(i/2));
4807 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4810 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4812 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4813 unsigned NumNonZero, unsigned NumZero,
4815 const TargetLowering &TLI) {
4819 DebugLoc dl = Op.getDebugLoc();
4822 for (unsigned i = 0; i < 8; ++i) {
4823 bool isNonZero = (NonZeros & (1 << i)) != 0;
4827 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4829 V = DAG.getUNDEF(MVT::v8i16);
4832 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4833 MVT::v8i16, V, Op.getOperand(i),
4834 DAG.getIntPtrConstant(i));
4841 /// getVShift - Return a vector logical shift node.
4843 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4844 unsigned NumBits, SelectionDAG &DAG,
4845 const TargetLowering &TLI, DebugLoc dl) {
4846 EVT ShVT = MVT::v2i64;
4847 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4848 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4849 return DAG.getNode(ISD::BITCAST, dl, VT,
4850 DAG.getNode(Opc, dl, ShVT, SrcOp,
4851 DAG.getConstant(NumBits,
4852 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4856 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4857 SelectionDAG &DAG) const {
4859 // Check if the scalar load can be widened into a vector load. And if
4860 // the address is "base + cst" see if the cst can be "absorbed" into
4861 // the shuffle mask.
4862 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4863 SDValue Ptr = LD->getBasePtr();
4864 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4866 EVT PVT = LD->getValueType(0);
4867 if (PVT != MVT::i32 && PVT != MVT::f32)
4872 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4873 FI = FINode->getIndex();
4875 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4876 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4877 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4878 Offset = Ptr.getConstantOperandVal(1);
4879 Ptr = Ptr.getOperand(0);
4884 // FIXME: 256-bit vector instructions don't require a strict alignment,
4885 // improve this code to support it better.
4886 unsigned RequiredAlign = VT.getSizeInBits()/8;
4887 SDValue Chain = LD->getChain();
4888 // Make sure the stack object alignment is at least 16 or 32.
4889 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4890 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4891 if (MFI->isFixedObjectIndex(FI)) {
4892 // Can't change the alignment. FIXME: It's possible to compute
4893 // the exact stack offset and reference FI + adjust offset instead.
4894 // If someone *really* cares about this. That's the way to implement it.
4897 MFI->setObjectAlignment(FI, RequiredAlign);
4901 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4902 // Ptr + (Offset & ~15).
4905 if ((Offset % RequiredAlign) & 3)
4907 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4909 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4910 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4912 int EltNo = (Offset - StartOffset) >> 2;
4913 int NumElems = VT.getVectorNumElements();
4915 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4916 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4917 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4918 LD->getPointerInfo().getWithOffset(StartOffset),
4921 // Canonicalize it to a v4i32 or v8i32 shuffle.
4922 SmallVector<int, 8> Mask;
4923 for (int i = 0; i < NumElems; ++i)
4924 Mask.push_back(EltNo);
4926 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4927 return DAG.getNode(ISD::BITCAST, dl, NVT,
4928 DAG.getVectorShuffle(CanonVT, dl, V1,
4929 DAG.getUNDEF(CanonVT),&Mask[0]));
4935 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4936 /// vector of type 'VT', see if the elements can be replaced by a single large
4937 /// load which has the same value as a build_vector whose operands are 'elts'.
4939 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4941 /// FIXME: we'd also like to handle the case where the last elements are zero
4942 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4943 /// There's even a handy isZeroNode for that purpose.
4944 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4945 DebugLoc &DL, SelectionDAG &DAG) {
4946 EVT EltVT = VT.getVectorElementType();
4947 unsigned NumElems = Elts.size();
4949 LoadSDNode *LDBase = NULL;
4950 unsigned LastLoadedElt = -1U;
4952 // For each element in the initializer, see if we've found a load or an undef.
4953 // If we don't find an initial load element, or later load elements are
4954 // non-consecutive, bail out.
4955 for (unsigned i = 0; i < NumElems; ++i) {
4956 SDValue Elt = Elts[i];
4958 if (!Elt.getNode() ||
4959 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4962 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4964 LDBase = cast<LoadSDNode>(Elt.getNode());
4968 if (Elt.getOpcode() == ISD::UNDEF)
4971 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4972 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4977 // If we have found an entire vector of loads and undefs, then return a large
4978 // load of the entire vector width starting at the base pointer. If we found
4979 // consecutive loads for the low half, generate a vzext_load node.
4980 if (LastLoadedElt == NumElems - 1) {
4981 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4982 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4983 LDBase->getPointerInfo(),
4984 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4985 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4986 LDBase->getPointerInfo(),
4987 LDBase->isVolatile(), LDBase->isNonTemporal(),
4988 LDBase->getAlignment());
4989 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4990 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4991 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4992 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4993 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4995 LDBase->getMemOperand());
4996 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5002 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5003 DebugLoc dl = Op.getDebugLoc();
5005 EVT VT = Op.getValueType();
5006 EVT ExtVT = VT.getVectorElementType();
5007 unsigned NumElems = Op.getNumOperands();
5009 // Vectors containing all zeros can be matched by pxor and xorps later
5010 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5011 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5012 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5013 if (Op.getValueType() == MVT::v4i32 ||
5014 Op.getValueType() == MVT::v8i32)
5017 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
5020 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5021 // vectors or broken into v4i32 operations on 256-bit vectors.
5022 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5023 if (Op.getValueType() == MVT::v4i32)
5026 return getOnesVector(Op.getValueType(), DAG, dl);
5029 unsigned EVTBits = ExtVT.getSizeInBits();
5031 unsigned NumZero = 0;
5032 unsigned NumNonZero = 0;
5033 unsigned NonZeros = 0;
5034 bool IsAllConstants = true;
5035 SmallSet<SDValue, 8> Values;
5036 for (unsigned i = 0; i < NumElems; ++i) {
5037 SDValue Elt = Op.getOperand(i);
5038 if (Elt.getOpcode() == ISD::UNDEF)
5041 if (Elt.getOpcode() != ISD::Constant &&
5042 Elt.getOpcode() != ISD::ConstantFP)
5043 IsAllConstants = false;
5044 if (X86::isZeroNode(Elt))
5047 NonZeros |= (1 << i);
5052 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5053 if (NumNonZero == 0)
5054 return DAG.getUNDEF(VT);
5056 // Special case for single non-zero, non-undef, element.
5057 if (NumNonZero == 1) {
5058 unsigned Idx = CountTrailingZeros_32(NonZeros);
5059 SDValue Item = Op.getOperand(Idx);
5061 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5062 // the value are obviously zero, truncate the value to i32 and do the
5063 // insertion that way. Only do this if the value is non-constant or if the
5064 // value is a constant being inserted into element 0. It is cheaper to do
5065 // a constant pool load than it is to do a movd + shuffle.
5066 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5067 (!IsAllConstants || Idx == 0)) {
5068 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5070 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5071 EVT VecVT = MVT::v4i32;
5072 unsigned VecElts = 4;
5074 // Truncate the value (which may itself be a constant) to i32, and
5075 // convert it to a vector with movd (S2V+shuffle to zero extend).
5076 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5077 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5078 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5079 Subtarget->hasSSE2(), DAG);
5081 // Now we have our 32-bit value zero extended in the low element of
5082 // a vector. If Idx != 0, swizzle it into place.
5084 SmallVector<int, 4> Mask;
5085 Mask.push_back(Idx);
5086 for (unsigned i = 1; i != VecElts; ++i)
5088 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5089 DAG.getUNDEF(Item.getValueType()),
5092 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5096 // If we have a constant or non-constant insertion into the low element of
5097 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5098 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5099 // depending on what the source datatype is.
5102 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5103 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5104 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5105 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5106 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5107 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
5109 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5110 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5111 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5112 EVT MiddleVT = MVT::v4i32;
5113 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
5114 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5115 Subtarget->hasSSE2(), DAG);
5116 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5120 // Is it a vector logical left shift?
5121 if (NumElems == 2 && Idx == 1 &&
5122 X86::isZeroNode(Op.getOperand(0)) &&
5123 !X86::isZeroNode(Op.getOperand(1))) {
5124 unsigned NumBits = VT.getSizeInBits();
5125 return getVShift(true, VT,
5126 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5127 VT, Op.getOperand(1)),
5128 NumBits/2, DAG, *this, dl);
5131 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5134 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5135 // is a non-constant being inserted into an element other than the low one,
5136 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5137 // movd/movss) to move this into the low element, then shuffle it into
5139 if (EVTBits == 32) {
5140 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5142 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5143 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
5144 Subtarget->hasSSE2(), DAG);
5145 SmallVector<int, 8> MaskVec;
5146 for (unsigned i = 0; i < NumElems; i++)
5147 MaskVec.push_back(i == Idx ? 0 : 1);
5148 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5152 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5153 if (Values.size() == 1) {
5154 if (EVTBits == 32) {
5155 // Instead of a shuffle like this:
5156 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5157 // Check if it's possible to issue this instead.
5158 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5159 unsigned Idx = CountTrailingZeros_32(NonZeros);
5160 SDValue Item = Op.getOperand(Idx);
5161 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5162 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5167 // A vector full of immediates; various special cases are already
5168 // handled, so this is best done with a single constant-pool load.
5172 // For AVX-length vectors, build the individual 128-bit pieces and use
5173 // shuffles to put them in place.
5174 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5175 SmallVector<SDValue, 32> V;
5176 for (unsigned i = 0; i < NumElems; ++i)
5177 V.push_back(Op.getOperand(i));
5179 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5181 // Build both the lower and upper subvector.
5182 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5183 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5186 // Recreate the wider vector with the lower and upper part.
5187 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5188 DAG.getConstant(0, MVT::i32), DAG, dl);
5189 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5193 // Let legalizer expand 2-wide build_vectors.
5194 if (EVTBits == 64) {
5195 if (NumNonZero == 1) {
5196 // One half is zero or undef.
5197 unsigned Idx = CountTrailingZeros_32(NonZeros);
5198 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5199 Op.getOperand(Idx));
5200 return getShuffleVectorZeroOrUndef(V2, Idx, true,
5201 Subtarget->hasSSE2(), DAG);
5206 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5207 if (EVTBits == 8 && NumElems == 16) {
5208 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5210 if (V.getNode()) return V;
5213 if (EVTBits == 16 && NumElems == 8) {
5214 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5216 if (V.getNode()) return V;
5219 // If element VT is == 32 bits, turn it into a number of shuffles.
5220 SmallVector<SDValue, 8> V;
5222 if (NumElems == 4 && NumZero > 0) {
5223 for (unsigned i = 0; i < 4; ++i) {
5224 bool isZero = !(NonZeros & (1 << i));
5226 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5228 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5231 for (unsigned i = 0; i < 2; ++i) {
5232 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5235 V[i] = V[i*2]; // Must be a zero vector.
5238 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5241 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5244 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5249 SmallVector<int, 8> MaskVec;
5250 bool Reverse = (NonZeros & 0x3) == 2;
5251 for (unsigned i = 0; i < 2; ++i)
5252 MaskVec.push_back(Reverse ? 1-i : i);
5253 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5254 for (unsigned i = 0; i < 2; ++i)
5255 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5256 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5259 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5260 // Check for a build vector of consecutive loads.
5261 for (unsigned i = 0; i < NumElems; ++i)
5262 V[i] = Op.getOperand(i);
5264 // Check for elements which are consecutive loads.
5265 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5269 // For SSE 4.1, use insertps to put the high elements into the low element.
5270 if (getSubtarget()->hasSSE41()) {
5272 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5273 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5275 Result = DAG.getUNDEF(VT);
5277 for (unsigned i = 1; i < NumElems; ++i) {
5278 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5279 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5280 Op.getOperand(i), DAG.getIntPtrConstant(i));
5285 // Otherwise, expand into a number of unpckl*, start by extending each of
5286 // our (non-undef) elements to the full vector width with the element in the
5287 // bottom slot of the vector (which generates no code for SSE).
5288 for (unsigned i = 0; i < NumElems; ++i) {
5289 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5290 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5292 V[i] = DAG.getUNDEF(VT);
5295 // Next, we iteratively mix elements, e.g. for v4f32:
5296 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5297 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5298 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5299 unsigned EltStride = NumElems >> 1;
5300 while (EltStride != 0) {
5301 for (unsigned i = 0; i < EltStride; ++i) {
5302 // If V[i+EltStride] is undef and this is the first round of mixing,
5303 // then it is safe to just drop this shuffle: V[i] is already in the
5304 // right place, the one element (since it's the first round) being
5305 // inserted as undef can be dropped. This isn't safe for successive
5306 // rounds because they will permute elements within both vectors.
5307 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5308 EltStride == NumElems/2)
5311 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5320 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5321 // them in a MMX register. This is better than doing a stack convert.
5322 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5323 DebugLoc dl = Op.getDebugLoc();
5324 EVT ResVT = Op.getValueType();
5326 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5327 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5329 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5330 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5331 InVec = Op.getOperand(1);
5332 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5333 unsigned NumElts = ResVT.getVectorNumElements();
5334 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5335 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5336 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5338 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5339 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5340 Mask[0] = 0; Mask[1] = 2;
5341 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5343 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5346 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5347 // to create 256-bit vectors from two other 128-bit ones.
5348 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5349 DebugLoc dl = Op.getDebugLoc();
5350 EVT ResVT = Op.getValueType();
5352 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5354 SDValue V1 = Op.getOperand(0);
5355 SDValue V2 = Op.getOperand(1);
5356 unsigned NumElems = ResVT.getVectorNumElements();
5358 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5359 DAG.getConstant(0, MVT::i32), DAG, dl);
5360 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5365 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5366 EVT ResVT = Op.getValueType();
5368 assert(Op.getNumOperands() == 2);
5369 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5370 "Unsupported CONCAT_VECTORS for value type");
5372 // We support concatenate two MMX registers and place them in a MMX register.
5373 // This is better than doing a stack convert.
5374 if (ResVT.is128BitVector())
5375 return LowerMMXCONCAT_VECTORS(Op, DAG);
5377 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5378 // from two other 128-bit ones.
5379 return LowerAVXCONCAT_VECTORS(Op, DAG);
5382 // v8i16 shuffles - Prefer shuffles in the following order:
5383 // 1. [all] pshuflw, pshufhw, optional move
5384 // 2. [ssse3] 1 x pshufb
5385 // 3. [ssse3] 2 x pshufb + 1 x por
5386 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5388 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5389 SelectionDAG &DAG) const {
5390 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5391 SDValue V1 = SVOp->getOperand(0);
5392 SDValue V2 = SVOp->getOperand(1);
5393 DebugLoc dl = SVOp->getDebugLoc();
5394 SmallVector<int, 8> MaskVals;
5396 // Determine if more than 1 of the words in each of the low and high quadwords
5397 // of the result come from the same quadword of one of the two inputs. Undef
5398 // mask values count as coming from any quadword, for better codegen.
5399 SmallVector<unsigned, 4> LoQuad(4);
5400 SmallVector<unsigned, 4> HiQuad(4);
5401 BitVector InputQuads(4);
5402 for (unsigned i = 0; i < 8; ++i) {
5403 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
5404 int EltIdx = SVOp->getMaskElt(i);
5405 MaskVals.push_back(EltIdx);
5414 InputQuads.set(EltIdx / 4);
5417 int BestLoQuad = -1;
5418 unsigned MaxQuad = 1;
5419 for (unsigned i = 0; i < 4; ++i) {
5420 if (LoQuad[i] > MaxQuad) {
5422 MaxQuad = LoQuad[i];
5426 int BestHiQuad = -1;
5428 for (unsigned i = 0; i < 4; ++i) {
5429 if (HiQuad[i] > MaxQuad) {
5431 MaxQuad = HiQuad[i];
5435 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5436 // of the two input vectors, shuffle them into one input vector so only a
5437 // single pshufb instruction is necessary. If There are more than 2 input
5438 // quads, disable the next transformation since it does not help SSSE3.
5439 bool V1Used = InputQuads[0] || InputQuads[1];
5440 bool V2Used = InputQuads[2] || InputQuads[3];
5441 if (Subtarget->hasSSSE3()) {
5442 if (InputQuads.count() == 2 && V1Used && V2Used) {
5443 BestLoQuad = InputQuads.find_first();
5444 BestHiQuad = InputQuads.find_next(BestLoQuad);
5446 if (InputQuads.count() > 2) {
5452 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5453 // the shuffle mask. If a quad is scored as -1, that means that it contains
5454 // words from all 4 input quadwords.
5456 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5457 SmallVector<int, 8> MaskV;
5458 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5459 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5460 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5461 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5462 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5463 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5465 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5466 // source words for the shuffle, to aid later transformations.
5467 bool AllWordsInNewV = true;
5468 bool InOrder[2] = { true, true };
5469 for (unsigned i = 0; i != 8; ++i) {
5470 int idx = MaskVals[i];
5472 InOrder[i/4] = false;
5473 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5475 AllWordsInNewV = false;
5479 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5480 if (AllWordsInNewV) {
5481 for (int i = 0; i != 8; ++i) {
5482 int idx = MaskVals[i];
5485 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5486 if ((idx != i) && idx < 4)
5488 if ((idx != i) && idx > 3)
5497 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5498 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5499 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5500 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5501 unsigned TargetMask = 0;
5502 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5503 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5504 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5505 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5506 V1 = NewV.getOperand(0);
5507 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5511 // If we have SSSE3, and all words of the result are from 1 input vector,
5512 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5513 // is present, fall back to case 4.
5514 if (Subtarget->hasSSSE3()) {
5515 SmallVector<SDValue,16> pshufbMask;
5517 // If we have elements from both input vectors, set the high bit of the
5518 // shuffle mask element to zero out elements that come from V2 in the V1
5519 // mask, and elements that come from V1 in the V2 mask, so that the two
5520 // results can be OR'd together.
5521 bool TwoInputs = V1Used && V2Used;
5522 for (unsigned i = 0; i != 8; ++i) {
5523 int EltIdx = MaskVals[i] * 2;
5524 if (TwoInputs && (EltIdx >= 16)) {
5525 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5526 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5529 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5530 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5532 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5533 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5534 DAG.getNode(ISD::BUILD_VECTOR, dl,
5535 MVT::v16i8, &pshufbMask[0], 16));
5537 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5539 // Calculate the shuffle mask for the second input, shuffle it, and
5540 // OR it with the first shuffled input.
5542 for (unsigned i = 0; i != 8; ++i) {
5543 int EltIdx = MaskVals[i] * 2;
5545 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5546 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5549 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5550 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5552 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5553 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5554 DAG.getNode(ISD::BUILD_VECTOR, dl,
5555 MVT::v16i8, &pshufbMask[0], 16));
5556 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5557 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5560 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5561 // and update MaskVals with new element order.
5562 BitVector InOrder(8);
5563 if (BestLoQuad >= 0) {
5564 SmallVector<int, 8> MaskV;
5565 for (int i = 0; i != 4; ++i) {
5566 int idx = MaskVals[i];
5568 MaskV.push_back(-1);
5570 } else if ((idx / 4) == BestLoQuad) {
5571 MaskV.push_back(idx & 3);
5574 MaskV.push_back(-1);
5577 for (unsigned i = 4; i != 8; ++i)
5579 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5582 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5583 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5585 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5589 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5590 // and update MaskVals with the new element order.
5591 if (BestHiQuad >= 0) {
5592 SmallVector<int, 8> MaskV;
5593 for (unsigned i = 0; i != 4; ++i)
5595 for (unsigned i = 4; i != 8; ++i) {
5596 int idx = MaskVals[i];
5598 MaskV.push_back(-1);
5600 } else if ((idx / 4) == BestHiQuad) {
5601 MaskV.push_back((idx & 3) + 4);
5604 MaskV.push_back(-1);
5607 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5610 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5611 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5613 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5617 // In case BestHi & BestLo were both -1, which means each quadword has a word
5618 // from each of the four input quadwords, calculate the InOrder bitvector now
5619 // before falling through to the insert/extract cleanup.
5620 if (BestLoQuad == -1 && BestHiQuad == -1) {
5622 for (int i = 0; i != 8; ++i)
5623 if (MaskVals[i] < 0 || MaskVals[i] == i)
5627 // The other elements are put in the right place using pextrw and pinsrw.
5628 for (unsigned i = 0; i != 8; ++i) {
5631 int EltIdx = MaskVals[i];
5634 SDValue ExtOp = (EltIdx < 8)
5635 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5636 DAG.getIntPtrConstant(EltIdx))
5637 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5638 DAG.getIntPtrConstant(EltIdx - 8));
5639 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5640 DAG.getIntPtrConstant(i));
5645 // v16i8 shuffles - Prefer shuffles in the following order:
5646 // 1. [ssse3] 1 x pshufb
5647 // 2. [ssse3] 2 x pshufb + 1 x por
5648 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5650 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5652 const X86TargetLowering &TLI) {
5653 SDValue V1 = SVOp->getOperand(0);
5654 SDValue V2 = SVOp->getOperand(1);
5655 DebugLoc dl = SVOp->getDebugLoc();
5656 SmallVector<int, 16> MaskVals;
5657 SVOp->getMask(MaskVals);
5659 // If we have SSSE3, case 1 is generated when all result bytes come from
5660 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5661 // present, fall back to case 3.
5662 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5665 for (unsigned i = 0; i < 16; ++i) {
5666 int EltIdx = MaskVals[i];
5675 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5676 if (TLI.getSubtarget()->hasSSSE3()) {
5677 SmallVector<SDValue,16> pshufbMask;
5679 // If all result elements are from one input vector, then only translate
5680 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5682 // Otherwise, we have elements from both input vectors, and must zero out
5683 // elements that come from V2 in the first mask, and V1 in the second mask
5684 // so that we can OR them together.
5685 bool TwoInputs = !(V1Only || V2Only);
5686 for (unsigned i = 0; i != 16; ++i) {
5687 int EltIdx = MaskVals[i];
5688 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5689 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5692 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5694 // If all the elements are from V2, assign it to V1 and return after
5695 // building the first pshufb.
5698 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5699 DAG.getNode(ISD::BUILD_VECTOR, dl,
5700 MVT::v16i8, &pshufbMask[0], 16));
5704 // Calculate the shuffle mask for the second input, shuffle it, and
5705 // OR it with the first shuffled input.
5707 for (unsigned i = 0; i != 16; ++i) {
5708 int EltIdx = MaskVals[i];
5710 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5713 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5715 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5716 DAG.getNode(ISD::BUILD_VECTOR, dl,
5717 MVT::v16i8, &pshufbMask[0], 16));
5718 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5721 // No SSSE3 - Calculate in place words and then fix all out of place words
5722 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5723 // the 16 different words that comprise the two doublequadword input vectors.
5724 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5725 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5726 SDValue NewV = V2Only ? V2 : V1;
5727 for (int i = 0; i != 8; ++i) {
5728 int Elt0 = MaskVals[i*2];
5729 int Elt1 = MaskVals[i*2+1];
5731 // This word of the result is all undef, skip it.
5732 if (Elt0 < 0 && Elt1 < 0)
5735 // This word of the result is already in the correct place, skip it.
5736 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5738 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5741 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5742 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5745 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5746 // using a single extract together, load it and store it.
5747 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5748 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5749 DAG.getIntPtrConstant(Elt1 / 2));
5750 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5751 DAG.getIntPtrConstant(i));
5755 // If Elt1 is defined, extract it from the appropriate source. If the
5756 // source byte is not also odd, shift the extracted word left 8 bits
5757 // otherwise clear the bottom 8 bits if we need to do an or.
5759 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5760 DAG.getIntPtrConstant(Elt1 / 2));
5761 if ((Elt1 & 1) == 0)
5762 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5764 TLI.getShiftAmountTy(InsElt.getValueType())));
5766 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5767 DAG.getConstant(0xFF00, MVT::i16));
5769 // If Elt0 is defined, extract it from the appropriate source. If the
5770 // source byte is not also even, shift the extracted word right 8 bits. If
5771 // Elt1 was also defined, OR the extracted values together before
5772 // inserting them in the result.
5774 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5775 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5776 if ((Elt0 & 1) != 0)
5777 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5779 TLI.getShiftAmountTy(InsElt0.getValueType())));
5781 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5782 DAG.getConstant(0x00FF, MVT::i16));
5783 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5786 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5787 DAG.getIntPtrConstant(i));
5789 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5792 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5793 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5794 /// done when every pair / quad of shuffle mask elements point to elements in
5795 /// the right sequence. e.g.
5796 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5798 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5799 SelectionDAG &DAG, DebugLoc dl) {
5800 EVT VT = SVOp->getValueType(0);
5801 SDValue V1 = SVOp->getOperand(0);
5802 SDValue V2 = SVOp->getOperand(1);
5803 unsigned NumElems = VT.getVectorNumElements();
5804 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5806 switch (VT.getSimpleVT().SimpleTy) {
5807 default: assert(false && "Unexpected!");
5808 case MVT::v4f32: NewVT = MVT::v2f64; break;
5809 case MVT::v4i32: NewVT = MVT::v2i64; break;
5810 case MVT::v8i16: NewVT = MVT::v4i32; break;
5811 case MVT::v16i8: NewVT = MVT::v4i32; break;
5814 int Scale = NumElems / NewWidth;
5815 SmallVector<int, 8> MaskVec;
5816 for (unsigned i = 0; i < NumElems; i += Scale) {
5818 for (int j = 0; j < Scale; ++j) {
5819 int EltIdx = SVOp->getMaskElt(i+j);
5823 StartIdx = EltIdx - (EltIdx % Scale);
5824 if (EltIdx != StartIdx + j)
5828 MaskVec.push_back(-1);
5830 MaskVec.push_back(StartIdx / Scale);
5833 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5834 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5835 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5838 /// getVZextMovL - Return a zero-extending vector move low node.
5840 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5841 SDValue SrcOp, SelectionDAG &DAG,
5842 const X86Subtarget *Subtarget, DebugLoc dl) {
5843 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5844 LoadSDNode *LD = NULL;
5845 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5846 LD = dyn_cast<LoadSDNode>(SrcOp);
5848 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5850 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5851 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5852 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5853 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5854 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5856 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5857 return DAG.getNode(ISD::BITCAST, dl, VT,
5858 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5859 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5867 return DAG.getNode(ISD::BITCAST, dl, VT,
5868 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5869 DAG.getNode(ISD::BITCAST, dl,
5873 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5874 /// shuffle node referes to only one lane in the sources.
5875 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5876 EVT VT = SVOp->getValueType(0);
5877 int NumElems = VT.getVectorNumElements();
5878 int HalfSize = NumElems/2;
5879 SmallVector<int, 16> M;
5881 bool MatchA = false, MatchB = false;
5883 for (int l = 0; l < NumElems*2; l += HalfSize) {
5884 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5890 for (int l = 0; l < NumElems*2; l += HalfSize) {
5891 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5897 return MatchA && MatchB;
5900 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5901 /// which could not be matched by any known target speficic shuffle
5903 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5904 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5905 // If each half of a vector shuffle node referes to only one lane in the
5906 // source vectors, extract each used 128-bit lane and shuffle them using
5907 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5908 // the work to the legalizer.
5909 DebugLoc dl = SVOp->getDebugLoc();
5910 EVT VT = SVOp->getValueType(0);
5911 int NumElems = VT.getVectorNumElements();
5912 int HalfSize = NumElems/2;
5914 // Extract the reference for each half
5915 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5916 int FstVecOpNum = 0, SndVecOpNum = 0;
5917 for (int i = 0; i < HalfSize; ++i) {
5918 int Elt = SVOp->getMaskElt(i);
5919 if (SVOp->getMaskElt(i) < 0)
5921 FstVecOpNum = Elt/NumElems;
5922 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5925 for (int i = HalfSize; i < NumElems; ++i) {
5926 int Elt = SVOp->getMaskElt(i);
5927 if (SVOp->getMaskElt(i) < 0)
5929 SndVecOpNum = Elt/NumElems;
5930 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5934 // Extract the subvectors
5935 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5936 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5937 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5938 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5940 // Generate 128-bit shuffles
5941 SmallVector<int, 16> MaskV1, MaskV2;
5942 for (int i = 0; i < HalfSize; ++i) {
5943 int Elt = SVOp->getMaskElt(i);
5944 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5946 for (int i = HalfSize; i < NumElems; ++i) {
5947 int Elt = SVOp->getMaskElt(i);
5948 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5951 EVT NVT = V1.getValueType();
5952 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5953 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5955 // Concatenate the result back
5956 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5957 DAG.getConstant(0, MVT::i32), DAG, dl);
5958 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5965 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5966 /// 4 elements, and match them with several different shuffle types.
5968 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5969 SDValue V1 = SVOp->getOperand(0);
5970 SDValue V2 = SVOp->getOperand(1);
5971 DebugLoc dl = SVOp->getDebugLoc();
5972 EVT VT = SVOp->getValueType(0);
5974 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5976 SmallVector<std::pair<int, int>, 8> Locs;
5978 SmallVector<int, 8> Mask1(4U, -1);
5979 SmallVector<int, 8> PermMask;
5980 SVOp->getMask(PermMask);
5984 for (unsigned i = 0; i != 4; ++i) {
5985 int Idx = PermMask[i];
5987 Locs[i] = std::make_pair(-1, -1);
5989 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5991 Locs[i] = std::make_pair(0, NumLo);
5995 Locs[i] = std::make_pair(1, NumHi);
5997 Mask1[2+NumHi] = Idx;
6003 if (NumLo <= 2 && NumHi <= 2) {
6004 // If no more than two elements come from either vector. This can be
6005 // implemented with two shuffles. First shuffle gather the elements.
6006 // The second shuffle, which takes the first shuffle as both of its
6007 // vector operands, put the elements into the right order.
6008 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6010 SmallVector<int, 8> Mask2(4U, -1);
6012 for (unsigned i = 0; i != 4; ++i) {
6013 if (Locs[i].first == -1)
6016 unsigned Idx = (i < 2) ? 0 : 4;
6017 Idx += Locs[i].first * 2 + Locs[i].second;
6022 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6023 } else if (NumLo == 3 || NumHi == 3) {
6024 // Otherwise, we must have three elements from one vector, call it X, and
6025 // one element from the other, call it Y. First, use a shufps to build an
6026 // intermediate vector with the one element from Y and the element from X
6027 // that will be in the same half in the final destination (the indexes don't
6028 // matter). Then, use a shufps to build the final vector, taking the half
6029 // containing the element from Y from the intermediate, and the other half
6032 // Normalize it so the 3 elements come from V1.
6033 CommuteVectorShuffleMask(PermMask, VT);
6037 // Find the element from V2.
6039 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6040 int Val = PermMask[HiIndex];
6047 Mask1[0] = PermMask[HiIndex];
6049 Mask1[2] = PermMask[HiIndex^1];
6051 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6054 Mask1[0] = PermMask[0];
6055 Mask1[1] = PermMask[1];
6056 Mask1[2] = HiIndex & 1 ? 6 : 4;
6057 Mask1[3] = HiIndex & 1 ? 4 : 6;
6058 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6060 Mask1[0] = HiIndex & 1 ? 2 : 0;
6061 Mask1[1] = HiIndex & 1 ? 0 : 2;
6062 Mask1[2] = PermMask[2];
6063 Mask1[3] = PermMask[3];
6068 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6072 // Break it into (shuffle shuffle_hi, shuffle_lo).
6075 SmallVector<int,8> LoMask(4U, -1);
6076 SmallVector<int,8> HiMask(4U, -1);
6078 SmallVector<int,8> *MaskPtr = &LoMask;
6079 unsigned MaskIdx = 0;
6082 for (unsigned i = 0; i != 4; ++i) {
6089 int Idx = PermMask[i];
6091 Locs[i] = std::make_pair(-1, -1);
6092 } else if (Idx < 4) {
6093 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6094 (*MaskPtr)[LoIdx] = Idx;
6097 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6098 (*MaskPtr)[HiIdx] = Idx;
6103 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6104 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6105 SmallVector<int, 8> MaskOps;
6106 for (unsigned i = 0; i != 4; ++i) {
6107 if (Locs[i].first == -1) {
6108 MaskOps.push_back(-1);
6110 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6111 MaskOps.push_back(Idx);
6114 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6117 static bool MayFoldVectorLoad(SDValue V) {
6118 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6119 V = V.getOperand(0);
6120 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6121 V = V.getOperand(0);
6127 // FIXME: the version above should always be used. Since there's
6128 // a bug where several vector shuffles can't be folded because the
6129 // DAG is not updated during lowering and a node claims to have two
6130 // uses while it only has one, use this version, and let isel match
6131 // another instruction if the load really happens to have more than
6132 // one use. Remove this version after this bug get fixed.
6133 // rdar://8434668, PR8156
6134 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6135 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6136 V = V.getOperand(0);
6137 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6138 V = V.getOperand(0);
6139 if (ISD::isNormalLoad(V.getNode()))
6144 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6145 /// a vector extract, and if both can be later optimized into a single load.
6146 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6147 /// here because otherwise a target specific shuffle node is going to be
6148 /// emitted for this shuffle, and the optimization not done.
6149 /// FIXME: This is probably not the best approach, but fix the problem
6150 /// until the right path is decided.
6152 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6153 const TargetLowering &TLI) {
6154 EVT VT = V.getValueType();
6155 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6157 // Be sure that the vector shuffle is present in a pattern like this:
6158 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6162 SDNode *N = *V.getNode()->use_begin();
6163 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6166 SDValue EltNo = N->getOperand(1);
6167 if (!isa<ConstantSDNode>(EltNo))
6170 // If the bit convert changed the number of elements, it is unsafe
6171 // to examine the mask.
6172 bool HasShuffleIntoBitcast = false;
6173 if (V.getOpcode() == ISD::BITCAST) {
6174 EVT SrcVT = V.getOperand(0).getValueType();
6175 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6177 V = V.getOperand(0);
6178 HasShuffleIntoBitcast = true;
6181 // Select the input vector, guarding against out of range extract vector.
6182 unsigned NumElems = VT.getVectorNumElements();
6183 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6184 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6185 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6187 // Skip one more bit_convert if necessary
6188 if (V.getOpcode() == ISD::BITCAST)
6189 V = V.getOperand(0);
6191 if (ISD::isNormalLoad(V.getNode())) {
6192 // Is the original load suitable?
6193 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6195 // FIXME: avoid the multi-use bug that is preventing lots of
6196 // of foldings to be detected, this is still wrong of course, but
6197 // give the temporary desired behavior, and if it happens that
6198 // the load has real more uses, during isel it will not fold, and
6199 // will generate poor code.
6200 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
6203 if (!HasShuffleIntoBitcast)
6206 // If there's a bitcast before the shuffle, check if the load type and
6207 // alignment is valid.
6208 unsigned Align = LN0->getAlignment();
6210 TLI.getTargetData()->getABITypeAlignment(
6211 VT.getTypeForEVT(*DAG.getContext()));
6213 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6221 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6222 EVT VT = Op.getValueType();
6224 // Canonizalize to v2f64.
6225 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6226 return DAG.getNode(ISD::BITCAST, dl, VT,
6227 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6232 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6234 SDValue V1 = Op.getOperand(0);
6235 SDValue V2 = Op.getOperand(1);
6236 EVT VT = Op.getValueType();
6238 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6240 if (HasSSE2 && VT == MVT::v2f64)
6241 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6243 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6244 return DAG.getNode(ISD::BITCAST, dl, VT,
6245 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6246 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6247 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6251 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6252 SDValue V1 = Op.getOperand(0);
6253 SDValue V2 = Op.getOperand(1);
6254 EVT VT = Op.getValueType();
6256 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6257 "unsupported shuffle type");
6259 if (V2.getOpcode() == ISD::UNDEF)
6263 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6266 static inline unsigned getSHUFPOpcode(EVT VT) {
6267 switch(VT.getSimpleVT().SimpleTy) {
6268 case MVT::v8i32: // Use fp unit for int unpack.
6270 case MVT::v4i32: // Use fp unit for int unpack.
6271 case MVT::v4f32: return X86ISD::SHUFPS;
6272 case MVT::v4i64: // Use fp unit for int unpack.
6274 case MVT::v2i64: // Use fp unit for int unpack.
6275 case MVT::v2f64: return X86ISD::SHUFPD;
6277 llvm_unreachable("Unknown type for shufp*");
6283 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6284 SDValue V1 = Op.getOperand(0);
6285 SDValue V2 = Op.getOperand(1);
6286 EVT VT = Op.getValueType();
6287 unsigned NumElems = VT.getVectorNumElements();
6289 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6290 // operand of these instructions is only memory, so check if there's a
6291 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6293 bool CanFoldLoad = false;
6295 // Trivial case, when V2 comes from a load.
6296 if (MayFoldVectorLoad(V2))
6299 // When V1 is a load, it can be folded later into a store in isel, example:
6300 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6302 // (MOVLPSmr addr:$src1, VR128:$src2)
6303 // So, recognize this potential and also use MOVLPS or MOVLPD
6304 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6307 // Both of them can't be memory operations though.
6308 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
6309 CanFoldLoad = false;
6312 if (HasSSE2 && NumElems == 2)
6313 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6316 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6319 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6320 // movl and movlp will both match v2i64, but v2i64 is never matched by
6321 // movl earlier because we make it strict to avoid messing with the movlp load
6322 // folding logic (see the code above getMOVLP call). Match it here then,
6323 // this is horrible, but will stay like this until we move all shuffle
6324 // matching to x86 specific nodes. Note that for the 1st condition all
6325 // types are matched with movsd.
6328 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6329 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6332 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6334 // Invert the operand order and use SHUFPS to match it.
6335 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1,
6336 X86::getShuffleSHUFImmediate(SVOp), DAG);
6339 static inline unsigned getUNPCKLOpcode(EVT VT) {
6340 switch(VT.getSimpleVT().SimpleTy) {
6341 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
6342 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
6343 case MVT::v4f32: return X86ISD::UNPCKLPS;
6344 case MVT::v2f64: return X86ISD::UNPCKLPD;
6345 case MVT::v8i32: // Use fp unit for int unpack.
6346 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
6347 case MVT::v4i64: // Use fp unit for int unpack.
6348 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
6349 case MVT::v16i8: return X86ISD::PUNPCKLBW;
6350 case MVT::v8i16: return X86ISD::PUNPCKLWD;
6352 llvm_unreachable("Unknown type for unpckl");
6357 static inline unsigned getUNPCKHOpcode(EVT VT) {
6358 switch(VT.getSimpleVT().SimpleTy) {
6359 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
6360 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
6361 case MVT::v4f32: return X86ISD::UNPCKHPS;
6362 case MVT::v2f64: return X86ISD::UNPCKHPD;
6363 case MVT::v8i32: // Use fp unit for int unpack.
6364 case MVT::v8f32: return X86ISD::VUNPCKHPSY;
6365 case MVT::v4i64: // Use fp unit for int unpack.
6366 case MVT::v4f64: return X86ISD::VUNPCKHPDY;
6367 case MVT::v16i8: return X86ISD::PUNPCKHBW;
6368 case MVT::v8i16: return X86ISD::PUNPCKHWD;
6370 llvm_unreachable("Unknown type for unpckh");
6375 static inline unsigned getVPERMILOpcode(EVT VT) {
6376 switch(VT.getSimpleVT().SimpleTy) {
6378 case MVT::v4f32: return X86ISD::VPERMILPS;
6380 case MVT::v2f64: return X86ISD::VPERMILPD;
6382 case MVT::v8f32: return X86ISD::VPERMILPSY;
6384 case MVT::v4f64: return X86ISD::VPERMILPDY;
6386 llvm_unreachable("Unknown type for vpermil");
6391 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
6392 /// a vbroadcast node. The nodes are suitable whenever we can fold a load coming
6393 /// from a 32 or 64 bit scalar. Update Op to the desired load to be folded.
6394 static bool isVectorBroadcast(SDValue &Op) {
6395 EVT VT = Op.getValueType();
6396 bool Is256 = VT.getSizeInBits() == 256;
6398 assert((VT.getSizeInBits() == 128 || Is256) &&
6399 "Unsupported type for vbroadcast node");
6402 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6403 V = V.getOperand(0);
6405 if (Is256 && !(V.hasOneUse() &&
6406 V.getOpcode() == ISD::INSERT_SUBVECTOR &&
6407 V.getOperand(0).getOpcode() == ISD::UNDEF))
6411 V = V.getOperand(1);
6416 // Check the source scalar_to_vector type. 256-bit broadcasts are
6417 // supported for 32/64-bit sizes, while 128-bit ones are only supported
6418 // for 32-bit scalars.
6419 if (V.getOpcode() != ISD::SCALAR_TO_VECTOR)
6422 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits();
6423 if (ScalarSize != 32 && ScalarSize != 64)
6425 if (!Is256 && ScalarSize == 64)
6428 V = V.getOperand(0);
6429 if (!MayFoldLoad(V))
6432 // Return the load node
6438 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6439 const TargetLowering &TLI,
6440 const X86Subtarget *Subtarget) {
6441 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6442 EVT VT = Op.getValueType();
6443 DebugLoc dl = Op.getDebugLoc();
6444 SDValue V1 = Op.getOperand(0);
6445 SDValue V2 = Op.getOperand(1);
6447 if (isZeroShuffle(SVOp))
6448 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
6450 // Handle splat operations
6451 if (SVOp->isSplat()) {
6452 unsigned NumElem = VT.getVectorNumElements();
6453 int Size = VT.getSizeInBits();
6454 // Special case, this is the only place now where it's allowed to return
6455 // a vector_shuffle operation without using a target specific node, because
6456 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6457 // this be moved to DAGCombine instead?
6458 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6461 // Use vbroadcast whenever the splat comes from a foldable load
6462 if (Subtarget->hasAVX() && isVectorBroadcast(V1))
6463 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1);
6465 // Handle splats by matching through known shuffle masks
6466 if ((Size == 128 && NumElem <= 4) ||
6467 (Size == 256 && NumElem < 8))
6470 // All remaning splats are promoted to target supported vector shuffles.
6471 return PromoteSplat(SVOp, DAG);
6474 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6476 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6477 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6478 if (NewOp.getNode())
6479 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6480 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6481 // FIXME: Figure out a cleaner way to do this.
6482 // Try to make use of movq to zero out the top part.
6483 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6484 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6485 if (NewOp.getNode()) {
6486 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6487 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6488 DAG, Subtarget, dl);
6490 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6491 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6492 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6493 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6494 DAG, Subtarget, dl);
6501 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6502 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6503 SDValue V1 = Op.getOperand(0);
6504 SDValue V2 = Op.getOperand(1);
6505 EVT VT = Op.getValueType();
6506 DebugLoc dl = Op.getDebugLoc();
6507 unsigned NumElems = VT.getVectorNumElements();
6508 bool isMMX = VT.getSizeInBits() == 64;
6509 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6510 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6511 bool V1IsSplat = false;
6512 bool V2IsSplat = false;
6513 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
6514 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
6515 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
6516 MachineFunction &MF = DAG.getMachineFunction();
6517 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6519 // Shuffle operations on MMX not supported.
6523 // Vector shuffle lowering takes 3 steps:
6525 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6526 // narrowing and commutation of operands should be handled.
6527 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6529 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6530 // so the shuffle can be broken into other shuffles and the legalizer can
6531 // try the lowering again.
6533 // The general ideia is that no vector_shuffle operation should be left to
6534 // be matched during isel, all of them must be converted to a target specific
6537 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6538 // narrowing and commutation of operands should be handled. The actual code
6539 // doesn't include all of those, work in progress...
6540 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6541 if (NewOp.getNode())
6544 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6545 // unpckh_undef). Only use pshufd if speed is more important than size.
6546 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
6547 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6548 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
6549 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6551 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
6552 RelaxedMayFoldVectorLoad(V1))
6553 return getMOVDDup(Op, dl, V1, DAG);
6555 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6556 return getMOVHighToLow(Op, dl, DAG);
6558 // Use to match splats
6559 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
6560 (VT == MVT::v2f64 || VT == MVT::v2i64))
6561 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6563 if (X86::isPSHUFDMask(SVOp)) {
6564 // The actual implementation will match the mask in the if above and then
6565 // during isel it can match several different instructions, not only pshufd
6566 // as its name says, sad but true, emulate the behavior for now...
6567 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6568 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6570 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6572 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6573 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6575 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1,
6579 // Check if this can be converted into a logical shift.
6580 bool isLeft = false;
6583 bool isShift = getSubtarget()->hasSSE2() &&
6584 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6585 if (isShift && ShVal.hasOneUse()) {
6586 // If the shifted value has multiple uses, it may be cheaper to use
6587 // v_set0 + movlhps or movhlps, etc.
6588 EVT EltVT = VT.getVectorElementType();
6589 ShAmt *= EltVT.getSizeInBits();
6590 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6593 if (X86::isMOVLMask(SVOp)) {
6596 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6597 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6598 if (!X86::isMOVLPMask(SVOp)) {
6599 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6600 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6602 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6603 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6607 // FIXME: fold these into legal mask.
6608 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
6609 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6611 if (X86::isMOVHLPSMask(SVOp))
6612 return getMOVHighToLow(Op, dl, DAG);
6614 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6615 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6617 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6618 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6620 if (X86::isMOVLPMask(SVOp))
6621 return getMOVLP(Op, dl, DAG, HasSSE2);
6623 if (ShouldXformToMOVHLPS(SVOp) ||
6624 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6625 return CommuteVectorShuffle(SVOp, DAG);
6628 // No better options. Use a vshl / vsrl.
6629 EVT EltVT = VT.getVectorElementType();
6630 ShAmt *= EltVT.getSizeInBits();
6631 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6634 bool Commuted = false;
6635 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6636 // 1,1,1,1 -> v8i16 though.
6637 V1IsSplat = isSplatVector(V1.getNode());
6638 V2IsSplat = isSplatVector(V2.getNode());
6640 // Canonicalize the splat or undef, if present, to be on the RHS.
6641 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
6642 Op = CommuteVectorShuffle(SVOp, DAG);
6643 SVOp = cast<ShuffleVectorSDNode>(Op);
6644 V1 = SVOp->getOperand(0);
6645 V2 = SVOp->getOperand(1);
6646 std::swap(V1IsSplat, V2IsSplat);
6647 std::swap(V1IsUndef, V2IsUndef);
6651 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
6652 // Shuffling low element of v1 into undef, just return v1.
6655 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6656 // the instruction selector will not match, so get a canonical MOVL with
6657 // swapped operands to undo the commute.
6658 return getMOVL(DAG, dl, VT, V2, V1);
6661 if (X86::isUNPCKLMask(SVOp))
6662 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
6664 if (X86::isUNPCKHMask(SVOp))
6665 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
6668 // Normalize mask so all entries that point to V2 points to its first
6669 // element then try to match unpck{h|l} again. If match, return a
6670 // new vector_shuffle with the corrected mask.
6671 SDValue NewMask = NormalizeMask(SVOp, DAG);
6672 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6673 if (NSVOp != SVOp) {
6674 if (X86::isUNPCKLMask(NSVOp, true)) {
6676 } else if (X86::isUNPCKHMask(NSVOp, true)) {
6683 // Commute is back and try unpck* again.
6684 // FIXME: this seems wrong.
6685 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6686 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6688 if (X86::isUNPCKLMask(NewSVOp))
6689 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
6691 if (X86::isUNPCKHMask(NewSVOp))
6692 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
6695 // Normalize the node to match x86 shuffle ops if needed
6696 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
6697 return CommuteVectorShuffle(SVOp, DAG);
6699 // The checks below are all present in isShuffleMaskLegal, but they are
6700 // inlined here right now to enable us to directly emit target specific
6701 // nodes, and remove one by one until they don't return Op anymore.
6702 SmallVector<int, 16> M;
6705 if (isPALIGNRMask(M, VT, HasSSSE3))
6706 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6707 X86::getShufflePALIGNRImmediate(SVOp),
6710 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6711 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6712 if (VT == MVT::v2f64)
6713 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
6714 if (VT == MVT::v2i64)
6715 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
6718 if (isPSHUFHWMask(M, VT))
6719 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6720 X86::getShufflePSHUFHWImmediate(SVOp),
6723 if (isPSHUFLWMask(M, VT))
6724 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6725 X86::getShufflePSHUFLWImmediate(SVOp),
6728 if (isSHUFPMask(M, VT))
6729 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6730 X86::getShuffleSHUFImmediate(SVOp), DAG);
6732 if (X86::isUNPCKL_v_undef_Mask(SVOp))
6733 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6734 if (X86::isUNPCKH_v_undef_Mask(SVOp))
6735 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6737 //===--------------------------------------------------------------------===//
6738 // Generate target specific nodes for 128 or 256-bit shuffles only
6739 // supported in the AVX instruction set.
6742 // Handle VMOVDDUPY permutations
6743 if (isMOVDDUPYMask(SVOp, Subtarget))
6744 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6746 // Handle VPERMILPS* permutations
6747 if (isVPERMILPSMask(M, VT, Subtarget))
6748 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6749 getShuffleVPERMILPSImmediate(SVOp), DAG);
6751 // Handle VPERMILPD* permutations
6752 if (isVPERMILPDMask(M, VT, Subtarget))
6753 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6754 getShuffleVPERMILPDImmediate(SVOp), DAG);
6756 // Handle VPERM2F128 permutations
6757 if (isVPERM2F128Mask(M, VT, Subtarget))
6758 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2,
6759 getShuffleVPERM2F128Immediate(SVOp), DAG);
6761 // Handle VSHUFPSY permutations
6762 if (isVSHUFPSYMask(M, VT, Subtarget))
6763 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6764 getShuffleVSHUFPSYImmediate(SVOp), DAG);
6766 // Handle VSHUFPDY permutations
6767 if (isVSHUFPDYMask(M, VT, Subtarget))
6768 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6769 getShuffleVSHUFPDYImmediate(SVOp), DAG);
6771 //===--------------------------------------------------------------------===//
6772 // Since no target specific shuffle was selected for this generic one,
6773 // lower it into other known shuffles. FIXME: this isn't true yet, but
6774 // this is the plan.
6777 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6778 if (VT == MVT::v8i16) {
6779 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6780 if (NewOp.getNode())
6784 if (VT == MVT::v16i8) {
6785 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6786 if (NewOp.getNode())
6790 // Handle all 128-bit wide vectors with 4 elements, and match them with
6791 // several different shuffle types.
6792 if (NumElems == 4 && VT.getSizeInBits() == 128)
6793 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6795 // Handle general 256-bit shuffles
6796 if (VT.is256BitVector())
6797 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6803 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6804 SelectionDAG &DAG) const {
6805 EVT VT = Op.getValueType();
6806 DebugLoc dl = Op.getDebugLoc();
6808 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6811 if (VT.getSizeInBits() == 8) {
6812 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6813 Op.getOperand(0), Op.getOperand(1));
6814 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6815 DAG.getValueType(VT));
6816 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6817 } else if (VT.getSizeInBits() == 16) {
6818 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6819 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6821 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6822 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6823 DAG.getNode(ISD::BITCAST, dl,
6827 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6828 Op.getOperand(0), Op.getOperand(1));
6829 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6830 DAG.getValueType(VT));
6831 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6832 } else if (VT == MVT::f32) {
6833 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6834 // the result back to FR32 register. It's only worth matching if the
6835 // result has a single use which is a store or a bitcast to i32. And in
6836 // the case of a store, it's not worth it if the index is a constant 0,
6837 // because a MOVSSmr can be used instead, which is smaller and faster.
6838 if (!Op.hasOneUse())
6840 SDNode *User = *Op.getNode()->use_begin();
6841 if ((User->getOpcode() != ISD::STORE ||
6842 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6843 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6844 (User->getOpcode() != ISD::BITCAST ||
6845 User->getValueType(0) != MVT::i32))
6847 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6848 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6851 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6852 } else if (VT == MVT::i32) {
6853 // ExtractPS works with constant index.
6854 if (isa<ConstantSDNode>(Op.getOperand(1)))
6862 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6863 SelectionDAG &DAG) const {
6864 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6867 SDValue Vec = Op.getOperand(0);
6868 EVT VecVT = Vec.getValueType();
6870 // If this is a 256-bit vector result, first extract the 128-bit vector and
6871 // then extract the element from the 128-bit vector.
6872 if (VecVT.getSizeInBits() == 256) {
6873 DebugLoc dl = Op.getNode()->getDebugLoc();
6874 unsigned NumElems = VecVT.getVectorNumElements();
6875 SDValue Idx = Op.getOperand(1);
6876 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6878 // Get the 128-bit vector.
6879 bool Upper = IdxVal >= NumElems/2;
6880 Vec = Extract128BitVector(Vec,
6881 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6883 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6884 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6887 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6889 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
6890 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6895 EVT VT = Op.getValueType();
6896 DebugLoc dl = Op.getDebugLoc();
6897 // TODO: handle v16i8.
6898 if (VT.getSizeInBits() == 16) {
6899 SDValue Vec = Op.getOperand(0);
6900 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6902 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6903 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6904 DAG.getNode(ISD::BITCAST, dl,
6907 // Transform it so it match pextrw which produces a 32-bit result.
6908 EVT EltVT = MVT::i32;
6909 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6910 Op.getOperand(0), Op.getOperand(1));
6911 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6912 DAG.getValueType(VT));
6913 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6914 } else if (VT.getSizeInBits() == 32) {
6915 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6919 // SHUFPS the element to the lowest double word, then movss.
6920 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6921 EVT VVT = Op.getOperand(0).getValueType();
6922 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6923 DAG.getUNDEF(VVT), Mask);
6924 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6925 DAG.getIntPtrConstant(0));
6926 } else if (VT.getSizeInBits() == 64) {
6927 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6928 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6929 // to match extract_elt for f64.
6930 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6934 // UNPCKHPD the element to the lowest double word, then movsd.
6935 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6936 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6937 int Mask[2] = { 1, -1 };
6938 EVT VVT = Op.getOperand(0).getValueType();
6939 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6940 DAG.getUNDEF(VVT), Mask);
6941 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6942 DAG.getIntPtrConstant(0));
6949 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6950 SelectionDAG &DAG) const {
6951 EVT VT = Op.getValueType();
6952 EVT EltVT = VT.getVectorElementType();
6953 DebugLoc dl = Op.getDebugLoc();
6955 SDValue N0 = Op.getOperand(0);
6956 SDValue N1 = Op.getOperand(1);
6957 SDValue N2 = Op.getOperand(2);
6959 if (VT.getSizeInBits() == 256)
6962 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6963 isa<ConstantSDNode>(N2)) {
6965 if (VT == MVT::v8i16)
6966 Opc = X86ISD::PINSRW;
6967 else if (VT == MVT::v16i8)
6968 Opc = X86ISD::PINSRB;
6970 Opc = X86ISD::PINSRB;
6972 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6974 if (N1.getValueType() != MVT::i32)
6975 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6976 if (N2.getValueType() != MVT::i32)
6977 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6978 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6979 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6980 // Bits [7:6] of the constant are the source select. This will always be
6981 // zero here. The DAG Combiner may combine an extract_elt index into these
6982 // bits. For example (insert (extract, 3), 2) could be matched by putting
6983 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6984 // Bits [5:4] of the constant are the destination select. This is the
6985 // value of the incoming immediate.
6986 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6987 // combine either bitwise AND or insert of float 0.0 to set these bits.
6988 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6989 // Create this as a scalar to vector..
6990 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6991 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6992 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
6993 // PINSR* works with constant index.
7000 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7001 EVT VT = Op.getValueType();
7002 EVT EltVT = VT.getVectorElementType();
7004 DebugLoc dl = Op.getDebugLoc();
7005 SDValue N0 = Op.getOperand(0);
7006 SDValue N1 = Op.getOperand(1);
7007 SDValue N2 = Op.getOperand(2);
7009 // If this is a 256-bit vector result, first extract the 128-bit vector,
7010 // insert the element into the extracted half and then place it back.
7011 if (VT.getSizeInBits() == 256) {
7012 if (!isa<ConstantSDNode>(N2))
7015 // Get the desired 128-bit vector half.
7016 unsigned NumElems = VT.getVectorNumElements();
7017 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7018 bool Upper = IdxVal >= NumElems/2;
7019 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
7020 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
7022 // Insert the element into the desired half.
7023 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
7024 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
7026 // Insert the changed part back to the 256-bit vector
7027 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
7030 if (Subtarget->hasSSE41() || Subtarget->hasAVX())
7031 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7033 if (EltVT == MVT::i8)
7036 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7037 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7038 // as its second argument.
7039 if (N1.getValueType() != MVT::i32)
7040 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7041 if (N2.getValueType() != MVT::i32)
7042 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7043 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7049 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7050 LLVMContext *Context = DAG.getContext();
7051 DebugLoc dl = Op.getDebugLoc();
7052 EVT OpVT = Op.getValueType();
7054 // If this is a 256-bit vector result, first insert into a 128-bit
7055 // vector and then insert into the 256-bit vector.
7056 if (OpVT.getSizeInBits() > 128) {
7057 // Insert into a 128-bit vector.
7058 EVT VT128 = EVT::getVectorVT(*Context,
7059 OpVT.getVectorElementType(),
7060 OpVT.getVectorNumElements() / 2);
7062 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7064 // Insert the 128-bit vector.
7065 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
7066 DAG.getConstant(0, MVT::i32),
7070 if (Op.getValueType() == MVT::v1i64 &&
7071 Op.getOperand(0).getValueType() == MVT::i64)
7072 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7074 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7075 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7076 "Expected an SSE type!");
7077 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7078 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7081 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7082 // a simple subregister reference or explicit instructions to grab
7083 // upper bits of a vector.
7085 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7086 if (Subtarget->hasAVX()) {
7087 DebugLoc dl = Op.getNode()->getDebugLoc();
7088 SDValue Vec = Op.getNode()->getOperand(0);
7089 SDValue Idx = Op.getNode()->getOperand(1);
7091 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7092 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7093 return Extract128BitVector(Vec, Idx, DAG, dl);
7099 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7100 // simple superregister reference or explicit instructions to insert
7101 // the upper bits of a vector.
7103 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7104 if (Subtarget->hasAVX()) {
7105 DebugLoc dl = Op.getNode()->getDebugLoc();
7106 SDValue Vec = Op.getNode()->getOperand(0);
7107 SDValue SubVec = Op.getNode()->getOperand(1);
7108 SDValue Idx = Op.getNode()->getOperand(2);
7110 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7111 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7112 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7118 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7119 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7120 // one of the above mentioned nodes. It has to be wrapped because otherwise
7121 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7122 // be used to form addressing mode. These wrapped nodes will be selected
7125 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7126 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7128 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7130 unsigned char OpFlag = 0;
7131 unsigned WrapperKind = X86ISD::Wrapper;
7132 CodeModel::Model M = getTargetMachine().getCodeModel();
7134 if (Subtarget->isPICStyleRIPRel() &&
7135 (M == CodeModel::Small || M == CodeModel::Kernel))
7136 WrapperKind = X86ISD::WrapperRIP;
7137 else if (Subtarget->isPICStyleGOT())
7138 OpFlag = X86II::MO_GOTOFF;
7139 else if (Subtarget->isPICStyleStubPIC())
7140 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7142 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7144 CP->getOffset(), OpFlag);
7145 DebugLoc DL = CP->getDebugLoc();
7146 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7147 // With PIC, the address is actually $g + Offset.
7149 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7150 DAG.getNode(X86ISD::GlobalBaseReg,
7151 DebugLoc(), getPointerTy()),
7158 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7159 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7161 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7163 unsigned char OpFlag = 0;
7164 unsigned WrapperKind = X86ISD::Wrapper;
7165 CodeModel::Model M = getTargetMachine().getCodeModel();
7167 if (Subtarget->isPICStyleRIPRel() &&
7168 (M == CodeModel::Small || M == CodeModel::Kernel))
7169 WrapperKind = X86ISD::WrapperRIP;
7170 else if (Subtarget->isPICStyleGOT())
7171 OpFlag = X86II::MO_GOTOFF;
7172 else if (Subtarget->isPICStyleStubPIC())
7173 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7175 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7177 DebugLoc DL = JT->getDebugLoc();
7178 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7180 // With PIC, the address is actually $g + Offset.
7182 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7183 DAG.getNode(X86ISD::GlobalBaseReg,
7184 DebugLoc(), getPointerTy()),
7191 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7192 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7194 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7196 unsigned char OpFlag = 0;
7197 unsigned WrapperKind = X86ISD::Wrapper;
7198 CodeModel::Model M = getTargetMachine().getCodeModel();
7200 if (Subtarget->isPICStyleRIPRel() &&
7201 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7202 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7203 OpFlag = X86II::MO_GOTPCREL;
7204 WrapperKind = X86ISD::WrapperRIP;
7205 } else if (Subtarget->isPICStyleGOT()) {
7206 OpFlag = X86II::MO_GOT;
7207 } else if (Subtarget->isPICStyleStubPIC()) {
7208 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7209 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7210 OpFlag = X86II::MO_DARWIN_NONLAZY;
7213 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7215 DebugLoc DL = Op.getDebugLoc();
7216 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7219 // With PIC, the address is actually $g + Offset.
7220 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7221 !Subtarget->is64Bit()) {
7222 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7223 DAG.getNode(X86ISD::GlobalBaseReg,
7224 DebugLoc(), getPointerTy()),
7228 // For symbols that require a load from a stub to get the address, emit the
7230 if (isGlobalStubReference(OpFlag))
7231 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7232 MachinePointerInfo::getGOT(), false, false, 0);
7238 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7239 // Create the TargetBlockAddressAddress node.
7240 unsigned char OpFlags =
7241 Subtarget->ClassifyBlockAddressReference();
7242 CodeModel::Model M = getTargetMachine().getCodeModel();
7243 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7244 DebugLoc dl = Op.getDebugLoc();
7245 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7246 /*isTarget=*/true, OpFlags);
7248 if (Subtarget->isPICStyleRIPRel() &&
7249 (M == CodeModel::Small || M == CodeModel::Kernel))
7250 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7252 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7254 // With PIC, the address is actually $g + Offset.
7255 if (isGlobalRelativeToPICBase(OpFlags)) {
7256 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7257 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7265 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7267 SelectionDAG &DAG) const {
7268 // Create the TargetGlobalAddress node, folding in the constant
7269 // offset if it is legal.
7270 unsigned char OpFlags =
7271 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7272 CodeModel::Model M = getTargetMachine().getCodeModel();
7274 if (OpFlags == X86II::MO_NO_FLAG &&
7275 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7276 // A direct static reference to a global.
7277 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7280 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7283 if (Subtarget->isPICStyleRIPRel() &&
7284 (M == CodeModel::Small || M == CodeModel::Kernel))
7285 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7287 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7289 // With PIC, the address is actually $g + Offset.
7290 if (isGlobalRelativeToPICBase(OpFlags)) {
7291 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7292 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7296 // For globals that require a load from a stub to get the address, emit the
7298 if (isGlobalStubReference(OpFlags))
7299 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7300 MachinePointerInfo::getGOT(), false, false, 0);
7302 // If there was a non-zero offset that we didn't fold, create an explicit
7305 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7306 DAG.getConstant(Offset, getPointerTy()));
7312 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7313 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7314 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7315 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7319 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7320 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7321 unsigned char OperandFlags) {
7322 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7323 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7324 DebugLoc dl = GA->getDebugLoc();
7325 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7326 GA->getValueType(0),
7330 SDValue Ops[] = { Chain, TGA, *InFlag };
7331 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7333 SDValue Ops[] = { Chain, TGA };
7334 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7337 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7338 MFI->setAdjustsStack(true);
7340 SDValue Flag = Chain.getValue(1);
7341 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7344 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7346 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7349 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7350 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7351 DAG.getNode(X86ISD::GlobalBaseReg,
7352 DebugLoc(), PtrVT), InFlag);
7353 InFlag = Chain.getValue(1);
7355 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7358 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7360 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7362 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7363 X86::RAX, X86II::MO_TLSGD);
7366 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7367 // "local exec" model.
7368 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7369 const EVT PtrVT, TLSModel::Model model,
7371 DebugLoc dl = GA->getDebugLoc();
7373 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7374 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7375 is64Bit ? 257 : 256));
7377 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7378 DAG.getIntPtrConstant(0),
7379 MachinePointerInfo(Ptr), false, false, 0);
7381 unsigned char OperandFlags = 0;
7382 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7384 unsigned WrapperKind = X86ISD::Wrapper;
7385 if (model == TLSModel::LocalExec) {
7386 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7387 } else if (is64Bit) {
7388 assert(model == TLSModel::InitialExec);
7389 OperandFlags = X86II::MO_GOTTPOFF;
7390 WrapperKind = X86ISD::WrapperRIP;
7392 assert(model == TLSModel::InitialExec);
7393 OperandFlags = X86II::MO_INDNTPOFF;
7396 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7398 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7399 GA->getValueType(0),
7400 GA->getOffset(), OperandFlags);
7401 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7403 if (model == TLSModel::InitialExec)
7404 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7405 MachinePointerInfo::getGOT(), false, false, 0);
7407 // The address of the thread local variable is the add of the thread
7408 // pointer with the offset of the variable.
7409 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7413 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7415 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7416 const GlobalValue *GV = GA->getGlobal();
7418 if (Subtarget->isTargetELF()) {
7419 // TODO: implement the "local dynamic" model
7420 // TODO: implement the "initial exec"model for pic executables
7422 // If GV is an alias then use the aliasee for determining
7423 // thread-localness.
7424 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7425 GV = GA->resolveAliasedGlobal(false);
7427 TLSModel::Model model
7428 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7431 case TLSModel::GeneralDynamic:
7432 case TLSModel::LocalDynamic: // not implemented
7433 if (Subtarget->is64Bit())
7434 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7435 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7437 case TLSModel::InitialExec:
7438 case TLSModel::LocalExec:
7439 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7440 Subtarget->is64Bit());
7442 } else if (Subtarget->isTargetDarwin()) {
7443 // Darwin only has one model of TLS. Lower to that.
7444 unsigned char OpFlag = 0;
7445 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7446 X86ISD::WrapperRIP : X86ISD::Wrapper;
7448 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7450 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7451 !Subtarget->is64Bit();
7453 OpFlag = X86II::MO_TLVP_PIC_BASE;
7455 OpFlag = X86II::MO_TLVP;
7456 DebugLoc DL = Op.getDebugLoc();
7457 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7458 GA->getValueType(0),
7459 GA->getOffset(), OpFlag);
7460 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7462 // With PIC32, the address is actually $g + Offset.
7464 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7465 DAG.getNode(X86ISD::GlobalBaseReg,
7466 DebugLoc(), getPointerTy()),
7469 // Lowering the machine isd will make sure everything is in the right
7471 SDValue Chain = DAG.getEntryNode();
7472 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7473 SDValue Args[] = { Chain, Offset };
7474 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7476 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7477 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7478 MFI->setAdjustsStack(true);
7480 // And our return value (tls address) is in the standard call return value
7482 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7483 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
7487 "TLS not implemented for this target.");
7489 llvm_unreachable("Unreachable");
7494 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7495 /// take a 2 x i32 value to shift plus a shift amount.
7496 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7497 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7498 EVT VT = Op.getValueType();
7499 unsigned VTBits = VT.getSizeInBits();
7500 DebugLoc dl = Op.getDebugLoc();
7501 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7502 SDValue ShOpLo = Op.getOperand(0);
7503 SDValue ShOpHi = Op.getOperand(1);
7504 SDValue ShAmt = Op.getOperand(2);
7505 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7506 DAG.getConstant(VTBits - 1, MVT::i8))
7507 : DAG.getConstant(0, VT);
7510 if (Op.getOpcode() == ISD::SHL_PARTS) {
7511 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7512 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7514 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7515 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7518 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7519 DAG.getConstant(VTBits, MVT::i8));
7520 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7521 AndNode, DAG.getConstant(0, MVT::i8));
7524 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7525 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7526 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7528 if (Op.getOpcode() == ISD::SHL_PARTS) {
7529 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7530 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7532 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7533 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7536 SDValue Ops[2] = { Lo, Hi };
7537 return DAG.getMergeValues(Ops, 2, dl);
7540 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7541 SelectionDAG &DAG) const {
7542 EVT SrcVT = Op.getOperand(0).getValueType();
7544 if (SrcVT.isVector())
7547 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7548 "Unknown SINT_TO_FP to lower!");
7550 // These are really Legal; return the operand so the caller accepts it as
7552 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7554 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7555 Subtarget->is64Bit()) {
7559 DebugLoc dl = Op.getDebugLoc();
7560 unsigned Size = SrcVT.getSizeInBits()/8;
7561 MachineFunction &MF = DAG.getMachineFunction();
7562 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7563 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7564 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7566 MachinePointerInfo::getFixedStack(SSFI),
7568 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7571 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7573 SelectionDAG &DAG) const {
7575 DebugLoc DL = Op.getDebugLoc();
7577 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7579 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7581 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7583 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7585 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7586 MachineMemOperand *MMO;
7588 int SSFI = FI->getIndex();
7590 DAG.getMachineFunction()
7591 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7592 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7594 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7595 StackSlot = StackSlot.getOperand(1);
7597 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7598 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7600 Tys, Ops, array_lengthof(Ops),
7604 Chain = Result.getValue(1);
7605 SDValue InFlag = Result.getValue(2);
7607 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7608 // shouldn't be necessary except that RFP cannot be live across
7609 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7610 MachineFunction &MF = DAG.getMachineFunction();
7611 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7612 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7613 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7614 Tys = DAG.getVTList(MVT::Other);
7616 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7618 MachineMemOperand *MMO =
7619 DAG.getMachineFunction()
7620 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7621 MachineMemOperand::MOStore, SSFISize, SSFISize);
7623 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7624 Ops, array_lengthof(Ops),
7625 Op.getValueType(), MMO);
7626 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7627 MachinePointerInfo::getFixedStack(SSFI),
7634 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7635 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7636 SelectionDAG &DAG) const {
7637 // This algorithm is not obvious. Here it is in C code, more or less:
7639 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7640 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7641 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7643 // Copy ints to xmm registers.
7644 __m128i xh = _mm_cvtsi32_si128( hi );
7645 __m128i xl = _mm_cvtsi32_si128( lo );
7647 // Combine into low half of a single xmm register.
7648 __m128i x = _mm_unpacklo_epi32( xh, xl );
7652 // Merge in appropriate exponents to give the integer bits the right
7654 x = _mm_unpacklo_epi32( x, exp );
7656 // Subtract away the biases to deal with the IEEE-754 double precision
7658 d = _mm_sub_pd( (__m128d) x, bias );
7660 // All conversions up to here are exact. The correctly rounded result is
7661 // calculated using the current rounding mode using the following
7663 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7664 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7665 // store doesn't really need to be here (except
7666 // maybe to zero the other double)
7671 DebugLoc dl = Op.getDebugLoc();
7672 LLVMContext *Context = DAG.getContext();
7674 // Build some magic constants.
7675 std::vector<Constant*> CV0;
7676 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7677 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7678 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7679 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7680 Constant *C0 = ConstantVector::get(CV0);
7681 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7683 std::vector<Constant*> CV1;
7685 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7687 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7688 Constant *C1 = ConstantVector::get(CV1);
7689 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7691 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7692 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7694 DAG.getIntPtrConstant(1)));
7695 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7696 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7698 DAG.getIntPtrConstant(0)));
7699 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7700 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7701 MachinePointerInfo::getConstantPool(),
7703 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7704 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7705 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7706 MachinePointerInfo::getConstantPool(),
7708 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7710 // Add the halves; easiest way is to swap them into another reg first.
7711 int ShufMask[2] = { 1, -1 };
7712 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7713 DAG.getUNDEF(MVT::v2f64), ShufMask);
7714 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7715 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7716 DAG.getIntPtrConstant(0));
7719 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7720 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7721 SelectionDAG &DAG) const {
7722 DebugLoc dl = Op.getDebugLoc();
7723 // FP constant to bias correct the final result.
7724 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7727 // Load the 32-bit value into an XMM register.
7728 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7731 // Zero out the upper parts of the register.
7732 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasSSE2(), DAG);
7734 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7735 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7736 DAG.getIntPtrConstant(0));
7738 // Or the load with the bias.
7739 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7740 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7741 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7743 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7744 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7745 MVT::v2f64, Bias)));
7746 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7747 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7748 DAG.getIntPtrConstant(0));
7750 // Subtract the bias.
7751 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7753 // Handle final rounding.
7754 EVT DestVT = Op.getValueType();
7756 if (DestVT.bitsLT(MVT::f64)) {
7757 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7758 DAG.getIntPtrConstant(0));
7759 } else if (DestVT.bitsGT(MVT::f64)) {
7760 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7763 // Handle final rounding.
7767 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7768 SelectionDAG &DAG) const {
7769 SDValue N0 = Op.getOperand(0);
7770 DebugLoc dl = Op.getDebugLoc();
7772 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7773 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7774 // the optimization here.
7775 if (DAG.SignBitIsZero(N0))
7776 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7778 EVT SrcVT = N0.getValueType();
7779 EVT DstVT = Op.getValueType();
7780 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7781 return LowerUINT_TO_FP_i64(Op, DAG);
7782 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7783 return LowerUINT_TO_FP_i32(Op, DAG);
7785 // Make a 64-bit buffer, and use it to build an FILD.
7786 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7787 if (SrcVT == MVT::i32) {
7788 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7789 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7790 getPointerTy(), StackSlot, WordOff);
7791 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7792 StackSlot, MachinePointerInfo(),
7794 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7795 OffsetSlot, MachinePointerInfo(),
7797 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7801 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7802 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7803 StackSlot, MachinePointerInfo(),
7805 // For i64 source, we need to add the appropriate power of 2 if the input
7806 // was negative. This is the same as the optimization in
7807 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7808 // we must be careful to do the computation in x87 extended precision, not
7809 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7810 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7811 MachineMemOperand *MMO =
7812 DAG.getMachineFunction()
7813 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7814 MachineMemOperand::MOLoad, 8, 8);
7816 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7817 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7818 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7821 APInt FF(32, 0x5F800000ULL);
7823 // Check whether the sign bit is set.
7824 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7825 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7828 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7829 SDValue FudgePtr = DAG.getConstantPool(
7830 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7833 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7834 SDValue Zero = DAG.getIntPtrConstant(0);
7835 SDValue Four = DAG.getIntPtrConstant(4);
7836 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7838 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7840 // Load the value out, extending it from f32 to f80.
7841 // FIXME: Avoid the extend by constructing the right constant pool?
7842 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7843 FudgePtr, MachinePointerInfo::getConstantPool(),
7844 MVT::f32, false, false, 4);
7845 // Extend everything to 80 bits to force it to be done on x87.
7846 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7847 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7850 std::pair<SDValue,SDValue> X86TargetLowering::
7851 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7852 DebugLoc DL = Op.getDebugLoc();
7854 EVT DstTy = Op.getValueType();
7857 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7861 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7862 DstTy.getSimpleVT() >= MVT::i16 &&
7863 "Unknown FP_TO_SINT to lower!");
7865 // These are really Legal.
7866 if (DstTy == MVT::i32 &&
7867 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7868 return std::make_pair(SDValue(), SDValue());
7869 if (Subtarget->is64Bit() &&
7870 DstTy == MVT::i64 &&
7871 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7872 return std::make_pair(SDValue(), SDValue());
7874 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7876 MachineFunction &MF = DAG.getMachineFunction();
7877 unsigned MemSize = DstTy.getSizeInBits()/8;
7878 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7879 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7884 switch (DstTy.getSimpleVT().SimpleTy) {
7885 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7886 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7887 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7888 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7891 SDValue Chain = DAG.getEntryNode();
7892 SDValue Value = Op.getOperand(0);
7893 EVT TheVT = Op.getOperand(0).getValueType();
7894 if (isScalarFPTypeInSSEReg(TheVT)) {
7895 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7896 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7897 MachinePointerInfo::getFixedStack(SSFI),
7899 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7901 Chain, StackSlot, DAG.getValueType(TheVT)
7904 MachineMemOperand *MMO =
7905 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7906 MachineMemOperand::MOLoad, MemSize, MemSize);
7907 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7909 Chain = Value.getValue(1);
7910 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7911 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7914 MachineMemOperand *MMO =
7915 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7916 MachineMemOperand::MOStore, MemSize, MemSize);
7918 // Build the FP_TO_INT*_IN_MEM
7919 SDValue Ops[] = { Chain, Value, StackSlot };
7920 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7921 Ops, 3, DstTy, MMO);
7923 return std::make_pair(FIST, StackSlot);
7926 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7927 SelectionDAG &DAG) const {
7928 if (Op.getValueType().isVector())
7931 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7932 SDValue FIST = Vals.first, StackSlot = Vals.second;
7933 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7934 if (FIST.getNode() == 0) return Op;
7937 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7938 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7941 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7942 SelectionDAG &DAG) const {
7943 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7944 SDValue FIST = Vals.first, StackSlot = Vals.second;
7945 assert(FIST.getNode() && "Unexpected failure");
7948 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7949 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7952 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7953 SelectionDAG &DAG) const {
7954 LLVMContext *Context = DAG.getContext();
7955 DebugLoc dl = Op.getDebugLoc();
7956 EVT VT = Op.getValueType();
7959 EltVT = VT.getVectorElementType();
7960 std::vector<Constant*> CV;
7961 if (EltVT == MVT::f64) {
7962 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7966 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7972 Constant *C = ConstantVector::get(CV);
7973 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7974 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7975 MachinePointerInfo::getConstantPool(),
7977 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7980 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7981 LLVMContext *Context = DAG.getContext();
7982 DebugLoc dl = Op.getDebugLoc();
7983 EVT VT = Op.getValueType();
7986 EltVT = VT.getVectorElementType();
7987 std::vector<Constant*> CV;
7988 if (EltVT == MVT::f64) {
7989 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7993 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7999 Constant *C = ConstantVector::get(CV);
8000 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8001 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8002 MachinePointerInfo::getConstantPool(),
8004 if (VT.isVector()) {
8005 return DAG.getNode(ISD::BITCAST, dl, VT,
8006 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
8007 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8009 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
8011 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8015 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8016 LLVMContext *Context = DAG.getContext();
8017 SDValue Op0 = Op.getOperand(0);
8018 SDValue Op1 = Op.getOperand(1);
8019 DebugLoc dl = Op.getDebugLoc();
8020 EVT VT = Op.getValueType();
8021 EVT SrcVT = Op1.getValueType();
8023 // If second operand is smaller, extend it first.
8024 if (SrcVT.bitsLT(VT)) {
8025 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8028 // And if it is bigger, shrink it first.
8029 if (SrcVT.bitsGT(VT)) {
8030 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8034 // At this point the operands and the result should have the same
8035 // type, and that won't be f80 since that is not custom lowered.
8037 // First get the sign bit of second operand.
8038 std::vector<Constant*> CV;
8039 if (SrcVT == MVT::f64) {
8040 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8041 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8043 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8044 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8045 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8046 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8048 Constant *C = ConstantVector::get(CV);
8049 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8050 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8051 MachinePointerInfo::getConstantPool(),
8053 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8055 // Shift sign bit right or left if the two operands have different types.
8056 if (SrcVT.bitsGT(VT)) {
8057 // Op0 is MVT::f32, Op1 is MVT::f64.
8058 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8059 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8060 DAG.getConstant(32, MVT::i32));
8061 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8062 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8063 DAG.getIntPtrConstant(0));
8066 // Clear first operand sign bit.
8068 if (VT == MVT::f64) {
8069 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8070 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8072 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8073 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8074 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8075 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8077 C = ConstantVector::get(CV);
8078 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8079 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8080 MachinePointerInfo::getConstantPool(),
8082 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8084 // Or the value with the sign bit.
8085 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8088 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8089 SDValue N0 = Op.getOperand(0);
8090 DebugLoc dl = Op.getDebugLoc();
8091 EVT VT = Op.getValueType();
8093 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8094 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8095 DAG.getConstant(1, VT));
8096 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8099 /// Emit nodes that will be selected as "test Op0,Op0", or something
8101 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8102 SelectionDAG &DAG) const {
8103 DebugLoc dl = Op.getDebugLoc();
8105 // CF and OF aren't always set the way we want. Determine which
8106 // of these we need.
8107 bool NeedCF = false;
8108 bool NeedOF = false;
8111 case X86::COND_A: case X86::COND_AE:
8112 case X86::COND_B: case X86::COND_BE:
8115 case X86::COND_G: case X86::COND_GE:
8116 case X86::COND_L: case X86::COND_LE:
8117 case X86::COND_O: case X86::COND_NO:
8122 // See if we can use the EFLAGS value from the operand instead of
8123 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8124 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8125 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8126 // Emit a CMP with 0, which is the TEST pattern.
8127 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8128 DAG.getConstant(0, Op.getValueType()));
8130 unsigned Opcode = 0;
8131 unsigned NumOperands = 0;
8132 switch (Op.getNode()->getOpcode()) {
8134 // Due to an isel shortcoming, be conservative if this add is likely to be
8135 // selected as part of a load-modify-store instruction. When the root node
8136 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8137 // uses of other nodes in the match, such as the ADD in this case. This
8138 // leads to the ADD being left around and reselected, with the result being
8139 // two adds in the output. Alas, even if none our users are stores, that
8140 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8141 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8142 // climbing the DAG back to the root, and it doesn't seem to be worth the
8144 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8145 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8146 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
8149 if (ConstantSDNode *C =
8150 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8151 // An add of one will be selected as an INC.
8152 if (C->getAPIntValue() == 1) {
8153 Opcode = X86ISD::INC;
8158 // An add of negative one (subtract of one) will be selected as a DEC.
8159 if (C->getAPIntValue().isAllOnesValue()) {
8160 Opcode = X86ISD::DEC;
8166 // Otherwise use a regular EFLAGS-setting add.
8167 Opcode = X86ISD::ADD;
8171 // If the primary and result isn't used, don't bother using X86ISD::AND,
8172 // because a TEST instruction will be better.
8173 bool NonFlagUse = false;
8174 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8175 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8177 unsigned UOpNo = UI.getOperandNo();
8178 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8179 // Look pass truncate.
8180 UOpNo = User->use_begin().getOperandNo();
8181 User = *User->use_begin();
8184 if (User->getOpcode() != ISD::BRCOND &&
8185 User->getOpcode() != ISD::SETCC &&
8186 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8199 // Due to the ISEL shortcoming noted above, be conservative if this op is
8200 // likely to be selected as part of a load-modify-store instruction.
8201 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8202 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8203 if (UI->getOpcode() == ISD::STORE)
8206 // Otherwise use a regular EFLAGS-setting instruction.
8207 switch (Op.getNode()->getOpcode()) {
8208 default: llvm_unreachable("unexpected operator!");
8209 case ISD::SUB: Opcode = X86ISD::SUB; break;
8210 case ISD::OR: Opcode = X86ISD::OR; break;
8211 case ISD::XOR: Opcode = X86ISD::XOR; break;
8212 case ISD::AND: Opcode = X86ISD::AND; break;
8224 return SDValue(Op.getNode(), 1);
8231 // Emit a CMP with 0, which is the TEST pattern.
8232 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8233 DAG.getConstant(0, Op.getValueType()));
8235 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8236 SmallVector<SDValue, 4> Ops;
8237 for (unsigned i = 0; i != NumOperands; ++i)
8238 Ops.push_back(Op.getOperand(i));
8240 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8241 DAG.ReplaceAllUsesWith(Op, New);
8242 return SDValue(New.getNode(), 1);
8245 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8247 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8248 SelectionDAG &DAG) const {
8249 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8250 if (C->getAPIntValue() == 0)
8251 return EmitTest(Op0, X86CC, DAG);
8253 DebugLoc dl = Op0.getDebugLoc();
8254 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8257 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8258 /// if it's possible.
8259 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8260 DebugLoc dl, SelectionDAG &DAG) const {
8261 SDValue Op0 = And.getOperand(0);
8262 SDValue Op1 = And.getOperand(1);
8263 if (Op0.getOpcode() == ISD::TRUNCATE)
8264 Op0 = Op0.getOperand(0);
8265 if (Op1.getOpcode() == ISD::TRUNCATE)
8266 Op1 = Op1.getOperand(0);
8269 if (Op1.getOpcode() == ISD::SHL)
8270 std::swap(Op0, Op1);
8271 if (Op0.getOpcode() == ISD::SHL) {
8272 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8273 if (And00C->getZExtValue() == 1) {
8274 // If we looked past a truncate, check that it's only truncating away
8276 unsigned BitWidth = Op0.getValueSizeInBits();
8277 unsigned AndBitWidth = And.getValueSizeInBits();
8278 if (BitWidth > AndBitWidth) {
8279 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8280 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8281 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8285 RHS = Op0.getOperand(1);
8287 } else if (Op1.getOpcode() == ISD::Constant) {
8288 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8289 SDValue AndLHS = Op0;
8290 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
8291 LHS = AndLHS.getOperand(0);
8292 RHS = AndLHS.getOperand(1);
8296 if (LHS.getNode()) {
8297 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8298 // instruction. Since the shift amount is in-range-or-undefined, we know
8299 // that doing a bittest on the i32 value is ok. We extend to i32 because
8300 // the encoding for the i16 version is larger than the i32 version.
8301 // Also promote i16 to i32 for performance / code size reason.
8302 if (LHS.getValueType() == MVT::i8 ||
8303 LHS.getValueType() == MVT::i16)
8304 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8306 // If the operand types disagree, extend the shift amount to match. Since
8307 // BT ignores high bits (like shifts) we can use anyextend.
8308 if (LHS.getValueType() != RHS.getValueType())
8309 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8311 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8312 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8313 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8314 DAG.getConstant(Cond, MVT::i8), BT);
8320 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8321 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8322 SDValue Op0 = Op.getOperand(0);
8323 SDValue Op1 = Op.getOperand(1);
8324 DebugLoc dl = Op.getDebugLoc();
8325 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8327 // Optimize to BT if possible.
8328 // Lower (X & (1 << N)) == 0 to BT(X, N).
8329 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8330 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8331 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8332 Op1.getOpcode() == ISD::Constant &&
8333 cast<ConstantSDNode>(Op1)->isNullValue() &&
8334 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8335 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8336 if (NewSetCC.getNode())
8340 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8342 if (Op1.getOpcode() == ISD::Constant &&
8343 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8344 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8345 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8347 // If the input is a setcc, then reuse the input setcc or use a new one with
8348 // the inverted condition.
8349 if (Op0.getOpcode() == X86ISD::SETCC) {
8350 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8351 bool Invert = (CC == ISD::SETNE) ^
8352 cast<ConstantSDNode>(Op1)->isNullValue();
8353 if (!Invert) return Op0;
8355 CCode = X86::GetOppositeBranchCondition(CCode);
8356 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8357 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8361 bool isFP = Op1.getValueType().isFloatingPoint();
8362 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8363 if (X86CC == X86::COND_INVALID)
8366 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8367 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8368 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8371 // Lower256IntVETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8372 // ones, and then concatenate the result back.
8373 static SDValue Lower256IntVETCC(SDValue Op, SelectionDAG &DAG) {
8374 EVT VT = Op.getValueType();
8376 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::VSETCC &&
8377 "Unsupported value type for operation");
8379 int NumElems = VT.getVectorNumElements();
8380 DebugLoc dl = Op.getDebugLoc();
8381 SDValue CC = Op.getOperand(2);
8382 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8383 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8385 // Extract the LHS vectors
8386 SDValue LHS = Op.getOperand(0);
8387 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8388 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8390 // Extract the RHS vectors
8391 SDValue RHS = Op.getOperand(1);
8392 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8393 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8395 // Issue the operation on the smaller types and concatenate the result back
8396 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8397 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8398 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8399 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8400 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8404 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8406 SDValue Op0 = Op.getOperand(0);
8407 SDValue Op1 = Op.getOperand(1);
8408 SDValue CC = Op.getOperand(2);
8409 EVT VT = Op.getValueType();
8410 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8411 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8412 DebugLoc dl = Op.getDebugLoc();
8416 EVT EltVT = Op0.getValueType().getVectorElementType();
8417 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8419 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8422 switch (SetCCOpcode) {
8425 case ISD::SETEQ: SSECC = 0; break;
8427 case ISD::SETGT: Swap = true; // Fallthrough
8429 case ISD::SETOLT: SSECC = 1; break;
8431 case ISD::SETGE: Swap = true; // Fallthrough
8433 case ISD::SETOLE: SSECC = 2; break;
8434 case ISD::SETUO: SSECC = 3; break;
8436 case ISD::SETNE: SSECC = 4; break;
8437 case ISD::SETULE: Swap = true;
8438 case ISD::SETUGE: SSECC = 5; break;
8439 case ISD::SETULT: Swap = true;
8440 case ISD::SETUGT: SSECC = 6; break;
8441 case ISD::SETO: SSECC = 7; break;
8444 std::swap(Op0, Op1);
8446 // In the two special cases we can't handle, emit two comparisons.
8448 if (SetCCOpcode == ISD::SETUEQ) {
8450 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8451 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8452 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8454 else if (SetCCOpcode == ISD::SETONE) {
8456 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8457 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8458 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8460 llvm_unreachable("Illegal FP comparison");
8462 // Handle all other FP comparisons here.
8463 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8466 // Break 256-bit integer vector compare into smaller ones.
8467 if (!isFP && VT.getSizeInBits() == 256)
8468 return Lower256IntVETCC(Op, DAG);
8470 // We are handling one of the integer comparisons here. Since SSE only has
8471 // GT and EQ comparisons for integer, swapping operands and multiple
8472 // operations may be required for some comparisons.
8473 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8474 bool Swap = false, Invert = false, FlipSigns = false;
8476 switch (VT.getSimpleVT().SimpleTy) {
8478 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8479 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8480 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8481 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8484 switch (SetCCOpcode) {
8486 case ISD::SETNE: Invert = true;
8487 case ISD::SETEQ: Opc = EQOpc; break;
8488 case ISD::SETLT: Swap = true;
8489 case ISD::SETGT: Opc = GTOpc; break;
8490 case ISD::SETGE: Swap = true;
8491 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8492 case ISD::SETULT: Swap = true;
8493 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8494 case ISD::SETUGE: Swap = true;
8495 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8498 std::swap(Op0, Op1);
8500 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8501 // bits of the inputs before performing those operations.
8503 EVT EltVT = VT.getVectorElementType();
8504 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8506 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8507 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8509 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8510 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8513 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8515 // If the logical-not of the result is required, perform that now.
8517 Result = DAG.getNOT(dl, Result, VT);
8522 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8523 static bool isX86LogicalCmp(SDValue Op) {
8524 unsigned Opc = Op.getNode()->getOpcode();
8525 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8527 if (Op.getResNo() == 1 &&
8528 (Opc == X86ISD::ADD ||
8529 Opc == X86ISD::SUB ||
8530 Opc == X86ISD::ADC ||
8531 Opc == X86ISD::SBB ||
8532 Opc == X86ISD::SMUL ||
8533 Opc == X86ISD::UMUL ||
8534 Opc == X86ISD::INC ||
8535 Opc == X86ISD::DEC ||
8536 Opc == X86ISD::OR ||
8537 Opc == X86ISD::XOR ||
8538 Opc == X86ISD::AND))
8541 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8547 static bool isZero(SDValue V) {
8548 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8549 return C && C->isNullValue();
8552 static bool isAllOnes(SDValue V) {
8553 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8554 return C && C->isAllOnesValue();
8557 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8558 bool addTest = true;
8559 SDValue Cond = Op.getOperand(0);
8560 SDValue Op1 = Op.getOperand(1);
8561 SDValue Op2 = Op.getOperand(2);
8562 DebugLoc DL = Op.getDebugLoc();
8565 if (Cond.getOpcode() == ISD::SETCC) {
8566 SDValue NewCond = LowerSETCC(Cond, DAG);
8567 if (NewCond.getNode())
8571 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8572 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8573 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8574 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8575 if (Cond.getOpcode() == X86ISD::SETCC &&
8576 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8577 isZero(Cond.getOperand(1).getOperand(1))) {
8578 SDValue Cmp = Cond.getOperand(1);
8580 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8582 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8583 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8584 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8586 SDValue CmpOp0 = Cmp.getOperand(0);
8587 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8588 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8590 SDValue Res = // Res = 0 or -1.
8591 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8592 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8594 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8595 Res = DAG.getNOT(DL, Res, Res.getValueType());
8597 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8598 if (N2C == 0 || !N2C->isNullValue())
8599 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8604 // Look past (and (setcc_carry (cmp ...)), 1).
8605 if (Cond.getOpcode() == ISD::AND &&
8606 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8607 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8608 if (C && C->getAPIntValue() == 1)
8609 Cond = Cond.getOperand(0);
8612 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8613 // setting operand in place of the X86ISD::SETCC.
8614 if (Cond.getOpcode() == X86ISD::SETCC ||
8615 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8616 CC = Cond.getOperand(0);
8618 SDValue Cmp = Cond.getOperand(1);
8619 unsigned Opc = Cmp.getOpcode();
8620 EVT VT = Op.getValueType();
8622 bool IllegalFPCMov = false;
8623 if (VT.isFloatingPoint() && !VT.isVector() &&
8624 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8625 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8627 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8628 Opc == X86ISD::BT) { // FIXME
8635 // Look pass the truncate.
8636 if (Cond.getOpcode() == ISD::TRUNCATE)
8637 Cond = Cond.getOperand(0);
8639 // We know the result of AND is compared against zero. Try to match
8641 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8642 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8643 if (NewSetCC.getNode()) {
8644 CC = NewSetCC.getOperand(0);
8645 Cond = NewSetCC.getOperand(1);
8652 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8653 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8656 // a < b ? -1 : 0 -> RES = ~setcc_carry
8657 // a < b ? 0 : -1 -> RES = setcc_carry
8658 // a >= b ? -1 : 0 -> RES = setcc_carry
8659 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8660 if (Cond.getOpcode() == X86ISD::CMP) {
8661 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8663 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8664 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8665 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8666 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8667 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8668 return DAG.getNOT(DL, Res, Res.getValueType());
8673 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8674 // condition is true.
8675 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8676 SDValue Ops[] = { Op2, Op1, CC, Cond };
8677 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8680 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8681 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8682 // from the AND / OR.
8683 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8684 Opc = Op.getOpcode();
8685 if (Opc != ISD::OR && Opc != ISD::AND)
8687 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8688 Op.getOperand(0).hasOneUse() &&
8689 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8690 Op.getOperand(1).hasOneUse());
8693 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8694 // 1 and that the SETCC node has a single use.
8695 static bool isXor1OfSetCC(SDValue Op) {
8696 if (Op.getOpcode() != ISD::XOR)
8698 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8699 if (N1C && N1C->getAPIntValue() == 1) {
8700 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8701 Op.getOperand(0).hasOneUse();
8706 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8707 bool addTest = true;
8708 SDValue Chain = Op.getOperand(0);
8709 SDValue Cond = Op.getOperand(1);
8710 SDValue Dest = Op.getOperand(2);
8711 DebugLoc dl = Op.getDebugLoc();
8714 if (Cond.getOpcode() == ISD::SETCC) {
8715 SDValue NewCond = LowerSETCC(Cond, DAG);
8716 if (NewCond.getNode())
8720 // FIXME: LowerXALUO doesn't handle these!!
8721 else if (Cond.getOpcode() == X86ISD::ADD ||
8722 Cond.getOpcode() == X86ISD::SUB ||
8723 Cond.getOpcode() == X86ISD::SMUL ||
8724 Cond.getOpcode() == X86ISD::UMUL)
8725 Cond = LowerXALUO(Cond, DAG);
8728 // Look pass (and (setcc_carry (cmp ...)), 1).
8729 if (Cond.getOpcode() == ISD::AND &&
8730 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8731 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8732 if (C && C->getAPIntValue() == 1)
8733 Cond = Cond.getOperand(0);
8736 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8737 // setting operand in place of the X86ISD::SETCC.
8738 if (Cond.getOpcode() == X86ISD::SETCC ||
8739 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8740 CC = Cond.getOperand(0);
8742 SDValue Cmp = Cond.getOperand(1);
8743 unsigned Opc = Cmp.getOpcode();
8744 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8745 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8749 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8753 // These can only come from an arithmetic instruction with overflow,
8754 // e.g. SADDO, UADDO.
8755 Cond = Cond.getNode()->getOperand(1);
8762 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8763 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8764 if (CondOpc == ISD::OR) {
8765 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8766 // two branches instead of an explicit OR instruction with a
8768 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8769 isX86LogicalCmp(Cmp)) {
8770 CC = Cond.getOperand(0).getOperand(0);
8771 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8772 Chain, Dest, CC, Cmp);
8773 CC = Cond.getOperand(1).getOperand(0);
8777 } else { // ISD::AND
8778 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8779 // two branches instead of an explicit AND instruction with a
8780 // separate test. However, we only do this if this block doesn't
8781 // have a fall-through edge, because this requires an explicit
8782 // jmp when the condition is false.
8783 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8784 isX86LogicalCmp(Cmp) &&
8785 Op.getNode()->hasOneUse()) {
8786 X86::CondCode CCode =
8787 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8788 CCode = X86::GetOppositeBranchCondition(CCode);
8789 CC = DAG.getConstant(CCode, MVT::i8);
8790 SDNode *User = *Op.getNode()->use_begin();
8791 // Look for an unconditional branch following this conditional branch.
8792 // We need this because we need to reverse the successors in order
8793 // to implement FCMP_OEQ.
8794 if (User->getOpcode() == ISD::BR) {
8795 SDValue FalseBB = User->getOperand(1);
8797 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8798 assert(NewBR == User);
8802 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8803 Chain, Dest, CC, Cmp);
8804 X86::CondCode CCode =
8805 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8806 CCode = X86::GetOppositeBranchCondition(CCode);
8807 CC = DAG.getConstant(CCode, MVT::i8);
8813 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8814 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8815 // It should be transformed during dag combiner except when the condition
8816 // is set by a arithmetics with overflow node.
8817 X86::CondCode CCode =
8818 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8819 CCode = X86::GetOppositeBranchCondition(CCode);
8820 CC = DAG.getConstant(CCode, MVT::i8);
8821 Cond = Cond.getOperand(0).getOperand(1);
8827 // Look pass the truncate.
8828 if (Cond.getOpcode() == ISD::TRUNCATE)
8829 Cond = Cond.getOperand(0);
8831 // We know the result of AND is compared against zero. Try to match
8833 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8834 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8835 if (NewSetCC.getNode()) {
8836 CC = NewSetCC.getOperand(0);
8837 Cond = NewSetCC.getOperand(1);
8844 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8845 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8847 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8848 Chain, Dest, CC, Cond);
8852 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8853 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8854 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8855 // that the guard pages used by the OS virtual memory manager are allocated in
8856 // correct sequence.
8858 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8859 SelectionDAG &DAG) const {
8860 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8861 EnableSegmentedStacks) &&
8862 "This should be used only on Windows targets or when segmented stacks "
8864 assert(!Subtarget->isTargetEnvMacho());
8865 DebugLoc dl = Op.getDebugLoc();
8868 SDValue Chain = Op.getOperand(0);
8869 SDValue Size = Op.getOperand(1);
8870 // FIXME: Ensure alignment here
8872 bool Is64Bit = Subtarget->is64Bit();
8873 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8875 if (EnableSegmentedStacks) {
8876 MachineFunction &MF = DAG.getMachineFunction();
8877 MachineRegisterInfo &MRI = MF.getRegInfo();
8880 // The 64 bit implementation of segmented stacks needs to clobber both r10
8881 // r11. This makes it impossible to use it along with nested paramenters.
8882 const Function *F = MF.getFunction();
8884 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8886 if (I->hasNestAttr())
8887 report_fatal_error("Cannot use segmented stacks with functions that "
8888 "have nested arguments.");
8891 const TargetRegisterClass *AddrRegClass =
8892 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8893 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8894 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8895 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8896 DAG.getRegister(Vreg, SPTy));
8897 SDValue Ops1[2] = { Value, Chain };
8898 return DAG.getMergeValues(Ops1, 2, dl);
8901 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8903 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8904 Flag = Chain.getValue(1);
8905 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8907 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8908 Flag = Chain.getValue(1);
8910 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8912 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8913 return DAG.getMergeValues(Ops1, 2, dl);
8917 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8918 MachineFunction &MF = DAG.getMachineFunction();
8919 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8921 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8922 DebugLoc DL = Op.getDebugLoc();
8924 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8925 // vastart just stores the address of the VarArgsFrameIndex slot into the
8926 // memory location argument.
8927 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8929 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8930 MachinePointerInfo(SV), false, false, 0);
8934 // gp_offset (0 - 6 * 8)
8935 // fp_offset (48 - 48 + 8 * 16)
8936 // overflow_arg_area (point to parameters coming in memory).
8938 SmallVector<SDValue, 8> MemOps;
8939 SDValue FIN = Op.getOperand(1);
8941 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8942 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
8944 FIN, MachinePointerInfo(SV), false, false, 0);
8945 MemOps.push_back(Store);
8948 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8949 FIN, DAG.getIntPtrConstant(4));
8950 Store = DAG.getStore(Op.getOperand(0), DL,
8951 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8953 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8954 MemOps.push_back(Store);
8956 // Store ptr to overflow_arg_area
8957 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8958 FIN, DAG.getIntPtrConstant(4));
8959 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8961 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
8962 MachinePointerInfo(SV, 8),
8964 MemOps.push_back(Store);
8966 // Store ptr to reg_save_area.
8967 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8968 FIN, DAG.getIntPtrConstant(8));
8969 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
8971 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
8972 MachinePointerInfo(SV, 16), false, false, 0);
8973 MemOps.push_back(Store);
8974 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
8975 &MemOps[0], MemOps.size());
8978 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
8979 assert(Subtarget->is64Bit() &&
8980 "LowerVAARG only handles 64-bit va_arg!");
8981 assert((Subtarget->isTargetLinux() ||
8982 Subtarget->isTargetDarwin()) &&
8983 "Unhandled target in LowerVAARG");
8984 assert(Op.getNode()->getNumOperands() == 4);
8985 SDValue Chain = Op.getOperand(0);
8986 SDValue SrcPtr = Op.getOperand(1);
8987 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8988 unsigned Align = Op.getConstantOperandVal(3);
8989 DebugLoc dl = Op.getDebugLoc();
8991 EVT ArgVT = Op.getNode()->getValueType(0);
8992 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
8993 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
8996 // Decide which area this value should be read from.
8997 // TODO: Implement the AMD64 ABI in its entirety. This simple
8998 // selection mechanism works only for the basic types.
8999 if (ArgVT == MVT::f80) {
9000 llvm_unreachable("va_arg for f80 not yet implemented");
9001 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9002 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9003 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9004 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9006 llvm_unreachable("Unhandled argument type in LowerVAARG");
9010 // Sanity Check: Make sure using fp_offset makes sense.
9011 assert(!UseSoftFloat &&
9012 !(DAG.getMachineFunction()
9013 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9014 Subtarget->hasXMM());
9017 // Insert VAARG_64 node into the DAG
9018 // VAARG_64 returns two values: Variable Argument Address, Chain
9019 SmallVector<SDValue, 11> InstOps;
9020 InstOps.push_back(Chain);
9021 InstOps.push_back(SrcPtr);
9022 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9023 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9024 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9025 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9026 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9027 VTs, &InstOps[0], InstOps.size(),
9029 MachinePointerInfo(SV),
9034 Chain = VAARG.getValue(1);
9036 // Load the next argument and return it
9037 return DAG.getLoad(ArgVT, dl,
9040 MachinePointerInfo(),
9044 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9045 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9046 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9047 SDValue Chain = Op.getOperand(0);
9048 SDValue DstPtr = Op.getOperand(1);
9049 SDValue SrcPtr = Op.getOperand(2);
9050 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9051 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9052 DebugLoc DL = Op.getDebugLoc();
9054 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9055 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9057 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9061 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9062 DebugLoc dl = Op.getDebugLoc();
9063 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9065 default: return SDValue(); // Don't custom lower most intrinsics.
9066 // Comparison intrinsics.
9067 case Intrinsic::x86_sse_comieq_ss:
9068 case Intrinsic::x86_sse_comilt_ss:
9069 case Intrinsic::x86_sse_comile_ss:
9070 case Intrinsic::x86_sse_comigt_ss:
9071 case Intrinsic::x86_sse_comige_ss:
9072 case Intrinsic::x86_sse_comineq_ss:
9073 case Intrinsic::x86_sse_ucomieq_ss:
9074 case Intrinsic::x86_sse_ucomilt_ss:
9075 case Intrinsic::x86_sse_ucomile_ss:
9076 case Intrinsic::x86_sse_ucomigt_ss:
9077 case Intrinsic::x86_sse_ucomige_ss:
9078 case Intrinsic::x86_sse_ucomineq_ss:
9079 case Intrinsic::x86_sse2_comieq_sd:
9080 case Intrinsic::x86_sse2_comilt_sd:
9081 case Intrinsic::x86_sse2_comile_sd:
9082 case Intrinsic::x86_sse2_comigt_sd:
9083 case Intrinsic::x86_sse2_comige_sd:
9084 case Intrinsic::x86_sse2_comineq_sd:
9085 case Intrinsic::x86_sse2_ucomieq_sd:
9086 case Intrinsic::x86_sse2_ucomilt_sd:
9087 case Intrinsic::x86_sse2_ucomile_sd:
9088 case Intrinsic::x86_sse2_ucomigt_sd:
9089 case Intrinsic::x86_sse2_ucomige_sd:
9090 case Intrinsic::x86_sse2_ucomineq_sd: {
9092 ISD::CondCode CC = ISD::SETCC_INVALID;
9095 case Intrinsic::x86_sse_comieq_ss:
9096 case Intrinsic::x86_sse2_comieq_sd:
9100 case Intrinsic::x86_sse_comilt_ss:
9101 case Intrinsic::x86_sse2_comilt_sd:
9105 case Intrinsic::x86_sse_comile_ss:
9106 case Intrinsic::x86_sse2_comile_sd:
9110 case Intrinsic::x86_sse_comigt_ss:
9111 case Intrinsic::x86_sse2_comigt_sd:
9115 case Intrinsic::x86_sse_comige_ss:
9116 case Intrinsic::x86_sse2_comige_sd:
9120 case Intrinsic::x86_sse_comineq_ss:
9121 case Intrinsic::x86_sse2_comineq_sd:
9125 case Intrinsic::x86_sse_ucomieq_ss:
9126 case Intrinsic::x86_sse2_ucomieq_sd:
9127 Opc = X86ISD::UCOMI;
9130 case Intrinsic::x86_sse_ucomilt_ss:
9131 case Intrinsic::x86_sse2_ucomilt_sd:
9132 Opc = X86ISD::UCOMI;
9135 case Intrinsic::x86_sse_ucomile_ss:
9136 case Intrinsic::x86_sse2_ucomile_sd:
9137 Opc = X86ISD::UCOMI;
9140 case Intrinsic::x86_sse_ucomigt_ss:
9141 case Intrinsic::x86_sse2_ucomigt_sd:
9142 Opc = X86ISD::UCOMI;
9145 case Intrinsic::x86_sse_ucomige_ss:
9146 case Intrinsic::x86_sse2_ucomige_sd:
9147 Opc = X86ISD::UCOMI;
9150 case Intrinsic::x86_sse_ucomineq_ss:
9151 case Intrinsic::x86_sse2_ucomineq_sd:
9152 Opc = X86ISD::UCOMI;
9157 SDValue LHS = Op.getOperand(1);
9158 SDValue RHS = Op.getOperand(2);
9159 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9160 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9161 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9162 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9163 DAG.getConstant(X86CC, MVT::i8), Cond);
9164 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9166 // ptest and testp intrinsics. The intrinsic these come from are designed to
9167 // return an integer value, not just an instruction so lower it to the ptest
9168 // or testp pattern and a setcc for the result.
9169 case Intrinsic::x86_sse41_ptestz:
9170 case Intrinsic::x86_sse41_ptestc:
9171 case Intrinsic::x86_sse41_ptestnzc:
9172 case Intrinsic::x86_avx_ptestz_256:
9173 case Intrinsic::x86_avx_ptestc_256:
9174 case Intrinsic::x86_avx_ptestnzc_256:
9175 case Intrinsic::x86_avx_vtestz_ps:
9176 case Intrinsic::x86_avx_vtestc_ps:
9177 case Intrinsic::x86_avx_vtestnzc_ps:
9178 case Intrinsic::x86_avx_vtestz_pd:
9179 case Intrinsic::x86_avx_vtestc_pd:
9180 case Intrinsic::x86_avx_vtestnzc_pd:
9181 case Intrinsic::x86_avx_vtestz_ps_256:
9182 case Intrinsic::x86_avx_vtestc_ps_256:
9183 case Intrinsic::x86_avx_vtestnzc_ps_256:
9184 case Intrinsic::x86_avx_vtestz_pd_256:
9185 case Intrinsic::x86_avx_vtestc_pd_256:
9186 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9187 bool IsTestPacked = false;
9190 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9191 case Intrinsic::x86_avx_vtestz_ps:
9192 case Intrinsic::x86_avx_vtestz_pd:
9193 case Intrinsic::x86_avx_vtestz_ps_256:
9194 case Intrinsic::x86_avx_vtestz_pd_256:
9195 IsTestPacked = true; // Fallthrough
9196 case Intrinsic::x86_sse41_ptestz:
9197 case Intrinsic::x86_avx_ptestz_256:
9199 X86CC = X86::COND_E;
9201 case Intrinsic::x86_avx_vtestc_ps:
9202 case Intrinsic::x86_avx_vtestc_pd:
9203 case Intrinsic::x86_avx_vtestc_ps_256:
9204 case Intrinsic::x86_avx_vtestc_pd_256:
9205 IsTestPacked = true; // Fallthrough
9206 case Intrinsic::x86_sse41_ptestc:
9207 case Intrinsic::x86_avx_ptestc_256:
9209 X86CC = X86::COND_B;
9211 case Intrinsic::x86_avx_vtestnzc_ps:
9212 case Intrinsic::x86_avx_vtestnzc_pd:
9213 case Intrinsic::x86_avx_vtestnzc_ps_256:
9214 case Intrinsic::x86_avx_vtestnzc_pd_256:
9215 IsTestPacked = true; // Fallthrough
9216 case Intrinsic::x86_sse41_ptestnzc:
9217 case Intrinsic::x86_avx_ptestnzc_256:
9219 X86CC = X86::COND_A;
9223 SDValue LHS = Op.getOperand(1);
9224 SDValue RHS = Op.getOperand(2);
9225 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9226 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9227 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9228 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9229 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9232 // Fix vector shift instructions where the last operand is a non-immediate
9234 case Intrinsic::x86_sse2_pslli_w:
9235 case Intrinsic::x86_sse2_pslli_d:
9236 case Intrinsic::x86_sse2_pslli_q:
9237 case Intrinsic::x86_sse2_psrli_w:
9238 case Intrinsic::x86_sse2_psrli_d:
9239 case Intrinsic::x86_sse2_psrli_q:
9240 case Intrinsic::x86_sse2_psrai_w:
9241 case Intrinsic::x86_sse2_psrai_d:
9242 case Intrinsic::x86_mmx_pslli_w:
9243 case Intrinsic::x86_mmx_pslli_d:
9244 case Intrinsic::x86_mmx_pslli_q:
9245 case Intrinsic::x86_mmx_psrli_w:
9246 case Intrinsic::x86_mmx_psrli_d:
9247 case Intrinsic::x86_mmx_psrli_q:
9248 case Intrinsic::x86_mmx_psrai_w:
9249 case Intrinsic::x86_mmx_psrai_d: {
9250 SDValue ShAmt = Op.getOperand(2);
9251 if (isa<ConstantSDNode>(ShAmt))
9254 unsigned NewIntNo = 0;
9255 EVT ShAmtVT = MVT::v4i32;
9257 case Intrinsic::x86_sse2_pslli_w:
9258 NewIntNo = Intrinsic::x86_sse2_psll_w;
9260 case Intrinsic::x86_sse2_pslli_d:
9261 NewIntNo = Intrinsic::x86_sse2_psll_d;
9263 case Intrinsic::x86_sse2_pslli_q:
9264 NewIntNo = Intrinsic::x86_sse2_psll_q;
9266 case Intrinsic::x86_sse2_psrli_w:
9267 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9269 case Intrinsic::x86_sse2_psrli_d:
9270 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9272 case Intrinsic::x86_sse2_psrli_q:
9273 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9275 case Intrinsic::x86_sse2_psrai_w:
9276 NewIntNo = Intrinsic::x86_sse2_psra_w;
9278 case Intrinsic::x86_sse2_psrai_d:
9279 NewIntNo = Intrinsic::x86_sse2_psra_d;
9282 ShAmtVT = MVT::v2i32;
9284 case Intrinsic::x86_mmx_pslli_w:
9285 NewIntNo = Intrinsic::x86_mmx_psll_w;
9287 case Intrinsic::x86_mmx_pslli_d:
9288 NewIntNo = Intrinsic::x86_mmx_psll_d;
9290 case Intrinsic::x86_mmx_pslli_q:
9291 NewIntNo = Intrinsic::x86_mmx_psll_q;
9293 case Intrinsic::x86_mmx_psrli_w:
9294 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9296 case Intrinsic::x86_mmx_psrli_d:
9297 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9299 case Intrinsic::x86_mmx_psrli_q:
9300 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9302 case Intrinsic::x86_mmx_psrai_w:
9303 NewIntNo = Intrinsic::x86_mmx_psra_w;
9305 case Intrinsic::x86_mmx_psrai_d:
9306 NewIntNo = Intrinsic::x86_mmx_psra_d;
9308 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9314 // The vector shift intrinsics with scalars uses 32b shift amounts but
9315 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9319 ShOps[1] = DAG.getConstant(0, MVT::i32);
9320 if (ShAmtVT == MVT::v4i32) {
9321 ShOps[2] = DAG.getUNDEF(MVT::i32);
9322 ShOps[3] = DAG.getUNDEF(MVT::i32);
9323 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9325 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9326 // FIXME this must be lowered to get rid of the invalid type.
9329 EVT VT = Op.getValueType();
9330 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9331 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9332 DAG.getConstant(NewIntNo, MVT::i32),
9333 Op.getOperand(1), ShAmt);
9338 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9339 SelectionDAG &DAG) const {
9340 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9341 MFI->setReturnAddressIsTaken(true);
9343 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9344 DebugLoc dl = Op.getDebugLoc();
9347 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9349 DAG.getConstant(TD->getPointerSize(),
9350 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9351 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9352 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9354 MachinePointerInfo(), false, false, 0);
9357 // Just load the return address.
9358 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9359 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9360 RetAddrFI, MachinePointerInfo(), false, false, 0);
9363 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9364 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9365 MFI->setFrameAddressIsTaken(true);
9367 EVT VT = Op.getValueType();
9368 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9369 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9370 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9371 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9373 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9374 MachinePointerInfo(),
9379 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9380 SelectionDAG &DAG) const {
9381 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9384 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9385 MachineFunction &MF = DAG.getMachineFunction();
9386 SDValue Chain = Op.getOperand(0);
9387 SDValue Offset = Op.getOperand(1);
9388 SDValue Handler = Op.getOperand(2);
9389 DebugLoc dl = Op.getDebugLoc();
9391 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9392 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9394 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9396 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9397 DAG.getIntPtrConstant(TD->getPointerSize()));
9398 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9399 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9401 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9402 MF.getRegInfo().addLiveOut(StoreAddrReg);
9404 return DAG.getNode(X86ISD::EH_RETURN, dl,
9406 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9409 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
9410 SelectionDAG &DAG) const {
9411 SDValue Root = Op.getOperand(0);
9412 SDValue Trmp = Op.getOperand(1); // trampoline
9413 SDValue FPtr = Op.getOperand(2); // nested function
9414 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9415 DebugLoc dl = Op.getDebugLoc();
9417 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9419 if (Subtarget->is64Bit()) {
9420 SDValue OutChains[6];
9422 // Large code-model.
9423 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9424 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9426 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9427 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9429 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9431 // Load the pointer to the nested function into R11.
9432 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9433 SDValue Addr = Trmp;
9434 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9435 Addr, MachinePointerInfo(TrmpAddr),
9438 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9439 DAG.getConstant(2, MVT::i64));
9440 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9441 MachinePointerInfo(TrmpAddr, 2),
9444 // Load the 'nest' parameter value into R10.
9445 // R10 is specified in X86CallingConv.td
9446 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9447 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9448 DAG.getConstant(10, MVT::i64));
9449 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9450 Addr, MachinePointerInfo(TrmpAddr, 10),
9453 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9454 DAG.getConstant(12, MVT::i64));
9455 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9456 MachinePointerInfo(TrmpAddr, 12),
9459 // Jump to the nested function.
9460 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9461 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9462 DAG.getConstant(20, MVT::i64));
9463 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9464 Addr, MachinePointerInfo(TrmpAddr, 20),
9467 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9468 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9469 DAG.getConstant(22, MVT::i64));
9470 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9471 MachinePointerInfo(TrmpAddr, 22),
9475 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
9476 return DAG.getMergeValues(Ops, 2, dl);
9478 const Function *Func =
9479 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9480 CallingConv::ID CC = Func->getCallingConv();
9485 llvm_unreachable("Unsupported calling convention");
9486 case CallingConv::C:
9487 case CallingConv::X86_StdCall: {
9488 // Pass 'nest' parameter in ECX.
9489 // Must be kept in sync with X86CallingConv.td
9492 // Check that ECX wasn't needed by an 'inreg' parameter.
9493 FunctionType *FTy = Func->getFunctionType();
9494 const AttrListPtr &Attrs = Func->getAttributes();
9496 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9497 unsigned InRegCount = 0;
9500 for (FunctionType::param_iterator I = FTy->param_begin(),
9501 E = FTy->param_end(); I != E; ++I, ++Idx)
9502 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9503 // FIXME: should only count parameters that are lowered to integers.
9504 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9506 if (InRegCount > 2) {
9507 report_fatal_error("Nest register in use - reduce number of inreg"
9513 case CallingConv::X86_FastCall:
9514 case CallingConv::X86_ThisCall:
9515 case CallingConv::Fast:
9516 // Pass 'nest' parameter in EAX.
9517 // Must be kept in sync with X86CallingConv.td
9522 SDValue OutChains[4];
9525 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9526 DAG.getConstant(10, MVT::i32));
9527 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9529 // This is storing the opcode for MOV32ri.
9530 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9531 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9532 OutChains[0] = DAG.getStore(Root, dl,
9533 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9534 Trmp, MachinePointerInfo(TrmpAddr),
9537 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9538 DAG.getConstant(1, MVT::i32));
9539 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9540 MachinePointerInfo(TrmpAddr, 1),
9543 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9544 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9545 DAG.getConstant(5, MVT::i32));
9546 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9547 MachinePointerInfo(TrmpAddr, 5),
9550 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9551 DAG.getConstant(6, MVT::i32));
9552 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9553 MachinePointerInfo(TrmpAddr, 6),
9557 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
9558 return DAG.getMergeValues(Ops, 2, dl);
9562 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9563 SelectionDAG &DAG) const {
9565 The rounding mode is in bits 11:10 of FPSR, and has the following
9572 FLT_ROUNDS, on the other hand, expects the following:
9579 To perform the conversion, we do:
9580 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9583 MachineFunction &MF = DAG.getMachineFunction();
9584 const TargetMachine &TM = MF.getTarget();
9585 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9586 unsigned StackAlignment = TFI.getStackAlignment();
9587 EVT VT = Op.getValueType();
9588 DebugLoc DL = Op.getDebugLoc();
9590 // Save FP Control Word to stack slot
9591 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9592 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9595 MachineMemOperand *MMO =
9596 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9597 MachineMemOperand::MOStore, 2, 2);
9599 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9600 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9601 DAG.getVTList(MVT::Other),
9602 Ops, 2, MVT::i16, MMO);
9604 // Load FP Control Word from stack slot
9605 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9606 MachinePointerInfo(), false, false, 0);
9608 // Transform as necessary
9610 DAG.getNode(ISD::SRL, DL, MVT::i16,
9611 DAG.getNode(ISD::AND, DL, MVT::i16,
9612 CWD, DAG.getConstant(0x800, MVT::i16)),
9613 DAG.getConstant(11, MVT::i8));
9615 DAG.getNode(ISD::SRL, DL, MVT::i16,
9616 DAG.getNode(ISD::AND, DL, MVT::i16,
9617 CWD, DAG.getConstant(0x400, MVT::i16)),
9618 DAG.getConstant(9, MVT::i8));
9621 DAG.getNode(ISD::AND, DL, MVT::i16,
9622 DAG.getNode(ISD::ADD, DL, MVT::i16,
9623 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9624 DAG.getConstant(1, MVT::i16)),
9625 DAG.getConstant(3, MVT::i16));
9628 return DAG.getNode((VT.getSizeInBits() < 16 ?
9629 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9632 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9633 EVT VT = Op.getValueType();
9635 unsigned NumBits = VT.getSizeInBits();
9636 DebugLoc dl = Op.getDebugLoc();
9638 Op = Op.getOperand(0);
9639 if (VT == MVT::i8) {
9640 // Zero extend to i32 since there is not an i8 bsr.
9642 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9645 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9646 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9647 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9649 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9652 DAG.getConstant(NumBits+NumBits-1, OpVT),
9653 DAG.getConstant(X86::COND_E, MVT::i8),
9656 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9658 // Finally xor with NumBits-1.
9659 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9662 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9666 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9667 EVT VT = Op.getValueType();
9669 unsigned NumBits = VT.getSizeInBits();
9670 DebugLoc dl = Op.getDebugLoc();
9672 Op = Op.getOperand(0);
9673 if (VT == MVT::i8) {
9675 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9678 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9679 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9680 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9682 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9685 DAG.getConstant(NumBits, OpVT),
9686 DAG.getConstant(X86::COND_E, MVT::i8),
9689 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9692 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9696 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9697 // ones, and then concatenate the result back.
9698 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9699 EVT VT = Op.getValueType();
9701 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9702 "Unsupported value type for operation");
9704 int NumElems = VT.getVectorNumElements();
9705 DebugLoc dl = Op.getDebugLoc();
9706 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9707 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9709 // Extract the LHS vectors
9710 SDValue LHS = Op.getOperand(0);
9711 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9712 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9714 // Extract the RHS vectors
9715 SDValue RHS = Op.getOperand(1);
9716 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9717 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9719 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9720 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9722 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9723 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9724 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9727 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9728 assert(Op.getValueType().getSizeInBits() == 256 &&
9729 Op.getValueType().isInteger() &&
9730 "Only handle AVX 256-bit vector integer operation");
9731 return Lower256IntArith(Op, DAG);
9734 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9735 assert(Op.getValueType().getSizeInBits() == 256 &&
9736 Op.getValueType().isInteger() &&
9737 "Only handle AVX 256-bit vector integer operation");
9738 return Lower256IntArith(Op, DAG);
9741 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9742 EVT VT = Op.getValueType();
9744 // Decompose 256-bit ops into smaller 128-bit ops.
9745 if (VT.getSizeInBits() == 256)
9746 return Lower256IntArith(Op, DAG);
9748 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9749 DebugLoc dl = Op.getDebugLoc();
9751 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9752 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9753 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9754 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9755 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9757 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9758 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9759 // return AloBlo + AloBhi + AhiBlo;
9761 SDValue A = Op.getOperand(0);
9762 SDValue B = Op.getOperand(1);
9764 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9765 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9766 A, DAG.getConstant(32, MVT::i32));
9767 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9768 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9769 B, DAG.getConstant(32, MVT::i32));
9770 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9771 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9773 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9774 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9776 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9777 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9779 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9780 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9781 AloBhi, DAG.getConstant(32, MVT::i32));
9782 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9783 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9784 AhiBlo, DAG.getConstant(32, MVT::i32));
9785 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9786 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9790 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9792 EVT VT = Op.getValueType();
9793 DebugLoc dl = Op.getDebugLoc();
9794 SDValue R = Op.getOperand(0);
9795 SDValue Amt = Op.getOperand(1);
9796 LLVMContext *Context = DAG.getContext();
9798 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
9801 // Decompose 256-bit shifts into smaller 128-bit shifts.
9802 if (VT.getSizeInBits() == 256) {
9803 int NumElems = VT.getVectorNumElements();
9804 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9805 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9807 // Extract the two vectors
9808 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
9809 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
9812 // Recreate the shift amount vectors
9814 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
9815 // Constant shift amount
9816 SmallVector<SDValue, 4> Amt1Csts;
9817 SmallVector<SDValue, 4> Amt2Csts;
9818 for (int i = 0; i < NumElems/2; ++i)
9819 Amt1Csts.push_back(Amt->getOperand(i));
9820 for (int i = NumElems/2; i < NumElems; ++i)
9821 Amt2Csts.push_back(Amt->getOperand(i));
9823 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9824 &Amt1Csts[0], NumElems/2);
9825 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9826 &Amt2Csts[0], NumElems/2);
9828 // Variable shift amount
9829 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
9830 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
9834 // Issue new vector shifts for the smaller types
9835 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
9836 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
9838 // Concatenate the result back
9839 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
9842 // Optimize shl/srl/sra with constant shift amount.
9843 if (isSplatVector(Amt.getNode())) {
9844 SDValue SclrAmt = Amt->getOperand(0);
9845 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9846 uint64_t ShiftAmt = C->getZExtValue();
9848 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
9849 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9850 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9851 R, DAG.getConstant(ShiftAmt, MVT::i32));
9853 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
9854 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9855 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9856 R, DAG.getConstant(ShiftAmt, MVT::i32));
9858 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
9859 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9860 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9861 R, DAG.getConstant(ShiftAmt, MVT::i32));
9863 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
9864 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9865 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9866 R, DAG.getConstant(ShiftAmt, MVT::i32));
9868 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
9869 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9870 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9871 R, DAG.getConstant(ShiftAmt, MVT::i32));
9873 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
9874 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9875 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9876 R, DAG.getConstant(ShiftAmt, MVT::i32));
9878 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
9879 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9880 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9881 R, DAG.getConstant(ShiftAmt, MVT::i32));
9883 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9884 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9885 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9886 R, DAG.getConstant(ShiftAmt, MVT::i32));
9890 // Lower SHL with variable shift amount.
9891 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
9892 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9893 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9894 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
9896 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
9898 std::vector<Constant*> CV(4, CI);
9899 Constant *C = ConstantVector::get(CV);
9900 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9901 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9902 MachinePointerInfo::getConstantPool(),
9905 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
9906 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
9907 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
9908 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
9910 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
9912 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9913 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9914 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
9916 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
9917 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
9919 std::vector<Constant*> CVM1(16, CM1);
9920 std::vector<Constant*> CVM2(16, CM2);
9921 Constant *C = ConstantVector::get(CVM1);
9922 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9923 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9924 MachinePointerInfo::getConstantPool(),
9927 // r = pblendv(r, psllw(r & (char16)15, 4), a);
9928 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9929 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9930 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9931 DAG.getConstant(4, MVT::i32));
9932 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9934 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9936 C = ConstantVector::get(CVM2);
9937 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9938 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9939 MachinePointerInfo::getConstantPool(),
9942 // r = pblendv(r, psllw(r & (char16)63, 2), a);
9943 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9944 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9945 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9946 DAG.getConstant(2, MVT::i32));
9947 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9949 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9951 // return pblendv(r, r+r, a);
9952 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
9953 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
9959 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
9960 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
9961 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
9962 // looks for this combo and may remove the "setcc" instruction if the "setcc"
9963 // has only one use.
9964 SDNode *N = Op.getNode();
9965 SDValue LHS = N->getOperand(0);
9966 SDValue RHS = N->getOperand(1);
9967 unsigned BaseOp = 0;
9969 DebugLoc DL = Op.getDebugLoc();
9970 switch (Op.getOpcode()) {
9971 default: llvm_unreachable("Unknown ovf instruction!");
9973 // A subtract of one will be selected as a INC. Note that INC doesn't
9974 // set CF, so we can't do this for UADDO.
9975 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9977 BaseOp = X86ISD::INC;
9981 BaseOp = X86ISD::ADD;
9985 BaseOp = X86ISD::ADD;
9989 // A subtract of one will be selected as a DEC. Note that DEC doesn't
9990 // set CF, so we can't do this for USUBO.
9991 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9993 BaseOp = X86ISD::DEC;
9997 BaseOp = X86ISD::SUB;
10001 BaseOp = X86ISD::SUB;
10002 Cond = X86::COND_B;
10005 BaseOp = X86ISD::SMUL;
10006 Cond = X86::COND_O;
10008 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10009 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10011 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10014 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10015 DAG.getConstant(X86::COND_O, MVT::i32),
10016 SDValue(Sum.getNode(), 2));
10018 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10022 // Also sets EFLAGS.
10023 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10024 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10027 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10028 DAG.getConstant(Cond, MVT::i32),
10029 SDValue(Sum.getNode(), 1));
10031 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10034 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
10035 DebugLoc dl = Op.getDebugLoc();
10036 SDNode* Node = Op.getNode();
10037 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
10038 EVT VT = Node->getValueType(0);
10040 if (Subtarget->hasSSE2() && VT.isVector()) {
10041 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10042 ExtraVT.getScalarType().getSizeInBits();
10043 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10045 unsigned SHLIntrinsicsID = 0;
10046 unsigned SRAIntrinsicsID = 0;
10047 switch (VT.getSimpleVT().SimpleTy) {
10051 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q;
10052 SRAIntrinsicsID = 0;
10056 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10057 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10061 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10062 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10067 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10068 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10069 Node->getOperand(0), ShAmt);
10071 // In case of 1 bit sext, no need to shr
10072 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
10074 if (SRAIntrinsicsID) {
10075 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10076 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10086 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10087 DebugLoc dl = Op.getDebugLoc();
10089 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10090 // There isn't any reason to disable it if the target processor supports it.
10091 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10092 SDValue Chain = Op.getOperand(0);
10093 SDValue Zero = DAG.getConstant(0, MVT::i32);
10095 DAG.getRegister(X86::ESP, MVT::i32), // Base
10096 DAG.getTargetConstant(1, MVT::i8), // Scale
10097 DAG.getRegister(0, MVT::i32), // Index
10098 DAG.getTargetConstant(0, MVT::i32), // Disp
10099 DAG.getRegister(0, MVT::i32), // Segment.
10104 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10105 array_lengthof(Ops));
10106 return SDValue(Res, 0);
10109 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10111 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10113 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10114 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10115 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10116 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10118 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10119 if (!Op1 && !Op2 && !Op3 && Op4)
10120 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10122 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10123 if (Op1 && !Op2 && !Op3 && !Op4)
10124 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10126 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10128 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10131 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10132 SelectionDAG &DAG) const {
10133 DebugLoc dl = Op.getDebugLoc();
10134 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10135 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10136 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10137 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10139 // The only fence that needs an instruction is a sequentially-consistent
10140 // cross-thread fence.
10141 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10142 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10143 // no-sse2). There isn't any reason to disable it if the target processor
10145 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10146 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10148 SDValue Chain = Op.getOperand(0);
10149 SDValue Zero = DAG.getConstant(0, MVT::i32);
10151 DAG.getRegister(X86::ESP, MVT::i32), // Base
10152 DAG.getTargetConstant(1, MVT::i8), // Scale
10153 DAG.getRegister(0, MVT::i32), // Index
10154 DAG.getTargetConstant(0, MVT::i32), // Disp
10155 DAG.getRegister(0, MVT::i32), // Segment.
10160 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10161 array_lengthof(Ops));
10162 return SDValue(Res, 0);
10165 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10166 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10170 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10171 EVT T = Op.getValueType();
10172 DebugLoc DL = Op.getDebugLoc();
10175 switch(T.getSimpleVT().SimpleTy) {
10177 assert(false && "Invalid value type!");
10178 case MVT::i8: Reg = X86::AL; size = 1; break;
10179 case MVT::i16: Reg = X86::AX; size = 2; break;
10180 case MVT::i32: Reg = X86::EAX; size = 4; break;
10182 assert(Subtarget->is64Bit() && "Node not type legal!");
10183 Reg = X86::RAX; size = 8;
10186 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10187 Op.getOperand(2), SDValue());
10188 SDValue Ops[] = { cpIn.getValue(0),
10191 DAG.getTargetConstant(size, MVT::i8),
10192 cpIn.getValue(1) };
10193 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10194 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10195 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10198 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10202 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10203 SelectionDAG &DAG) const {
10204 assert(Subtarget->is64Bit() && "Result not type legalized?");
10205 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10206 SDValue TheChain = Op.getOperand(0);
10207 DebugLoc dl = Op.getDebugLoc();
10208 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10209 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10210 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10212 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10213 DAG.getConstant(32, MVT::i8));
10215 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10218 return DAG.getMergeValues(Ops, 2, dl);
10221 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10222 SelectionDAG &DAG) const {
10223 EVT SrcVT = Op.getOperand(0).getValueType();
10224 EVT DstVT = Op.getValueType();
10225 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10226 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10227 assert((DstVT == MVT::i64 ||
10228 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10229 "Unexpected custom BITCAST");
10230 // i64 <=> MMX conversions are Legal.
10231 if (SrcVT==MVT::i64 && DstVT.isVector())
10233 if (DstVT==MVT::i64 && SrcVT.isVector())
10235 // MMX <=> MMX conversions are Legal.
10236 if (SrcVT.isVector() && DstVT.isVector())
10238 // All other conversions need to be expanded.
10242 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10243 SDNode *Node = Op.getNode();
10244 DebugLoc dl = Node->getDebugLoc();
10245 EVT T = Node->getValueType(0);
10246 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10247 DAG.getConstant(0, T), Node->getOperand(2));
10248 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10249 cast<AtomicSDNode>(Node)->getMemoryVT(),
10250 Node->getOperand(0),
10251 Node->getOperand(1), negOp,
10252 cast<AtomicSDNode>(Node)->getSrcValue(),
10253 cast<AtomicSDNode>(Node)->getAlignment(),
10254 cast<AtomicSDNode>(Node)->getOrdering(),
10255 cast<AtomicSDNode>(Node)->getSynchScope());
10258 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10259 SDNode *Node = Op.getNode();
10260 DebugLoc dl = Node->getDebugLoc();
10261 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10263 // Convert seq_cst store -> xchg
10264 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10265 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10266 // (The only way to get a 16-byte store is cmpxchg16b)
10267 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10268 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10269 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10270 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10271 cast<AtomicSDNode>(Node)->getMemoryVT(),
10272 Node->getOperand(0),
10273 Node->getOperand(1), Node->getOperand(2),
10274 cast<AtomicSDNode>(Node)->getMemOperand(),
10275 cast<AtomicSDNode>(Node)->getOrdering(),
10276 cast<AtomicSDNode>(Node)->getSynchScope());
10277 return Swap.getValue(1);
10279 // Other atomic stores have a simple pattern.
10283 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10284 EVT VT = Op.getNode()->getValueType(0);
10286 // Let legalize expand this if it isn't a legal type yet.
10287 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10290 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10293 bool ExtraOp = false;
10294 switch (Op.getOpcode()) {
10295 default: assert(0 && "Invalid code");
10296 case ISD::ADDC: Opc = X86ISD::ADD; break;
10297 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10298 case ISD::SUBC: Opc = X86ISD::SUB; break;
10299 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10303 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10305 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10306 Op.getOperand(1), Op.getOperand(2));
10309 /// LowerOperation - Provide custom lowering hooks for some operations.
10311 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10312 switch (Op.getOpcode()) {
10313 default: llvm_unreachable("Should not custom lower this!");
10314 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10315 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10316 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10317 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10318 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10319 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10320 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10321 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10322 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10323 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10324 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10325 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10326 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10327 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10328 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10329 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10330 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10331 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10332 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10333 case ISD::SHL_PARTS:
10334 case ISD::SRA_PARTS:
10335 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10336 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10337 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10338 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10339 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10340 case ISD::FABS: return LowerFABS(Op, DAG);
10341 case ISD::FNEG: return LowerFNEG(Op, DAG);
10342 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10343 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10344 case ISD::SETCC: return LowerSETCC(Op, DAG);
10345 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
10346 case ISD::SELECT: return LowerSELECT(Op, DAG);
10347 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10348 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10349 case ISD::VASTART: return LowerVASTART(Op, DAG);
10350 case ISD::VAARG: return LowerVAARG(Op, DAG);
10351 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10352 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10353 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10354 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10355 case ISD::FRAME_TO_ARGS_OFFSET:
10356 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10357 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10358 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10359 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
10360 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10361 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10362 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10363 case ISD::MUL: return LowerMUL(Op, DAG);
10366 case ISD::SHL: return LowerShift(Op, DAG);
10372 case ISD::UMULO: return LowerXALUO(Op, DAG);
10373 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10374 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10378 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10379 case ISD::ADD: return LowerADD(Op, DAG);
10380 case ISD::SUB: return LowerSUB(Op, DAG);
10384 static void ReplaceATOMIC_LOAD(SDNode *Node,
10385 SmallVectorImpl<SDValue> &Results,
10386 SelectionDAG &DAG) {
10387 DebugLoc dl = Node->getDebugLoc();
10388 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10390 // Convert wide load -> cmpxchg8b/cmpxchg16b
10391 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10392 // (The only way to get a 16-byte load is cmpxchg16b)
10393 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10394 SDValue Zero = DAG.getConstant(0, VT);
10395 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10396 Node->getOperand(0),
10397 Node->getOperand(1), Zero, Zero,
10398 cast<AtomicSDNode>(Node)->getMemOperand(),
10399 cast<AtomicSDNode>(Node)->getOrdering(),
10400 cast<AtomicSDNode>(Node)->getSynchScope());
10401 Results.push_back(Swap.getValue(0));
10402 Results.push_back(Swap.getValue(1));
10405 void X86TargetLowering::
10406 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10407 SelectionDAG &DAG, unsigned NewOp) const {
10408 EVT T = Node->getValueType(0);
10409 DebugLoc dl = Node->getDebugLoc();
10410 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
10412 SDValue Chain = Node->getOperand(0);
10413 SDValue In1 = Node->getOperand(1);
10414 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10415 Node->getOperand(2), DAG.getIntPtrConstant(0));
10416 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10417 Node->getOperand(2), DAG.getIntPtrConstant(1));
10418 SDValue Ops[] = { Chain, In1, In2L, In2H };
10419 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10421 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10422 cast<MemSDNode>(Node)->getMemOperand());
10423 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10424 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10425 Results.push_back(Result.getValue(2));
10428 /// ReplaceNodeResults - Replace a node with an illegal result type
10429 /// with a new node built out of custom code.
10430 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10431 SmallVectorImpl<SDValue>&Results,
10432 SelectionDAG &DAG) const {
10433 DebugLoc dl = N->getDebugLoc();
10434 switch (N->getOpcode()) {
10436 assert(false && "Do not know how to custom type legalize this operation!");
10438 case ISD::SIGN_EXTEND_INREG:
10443 // We don't want to expand or promote these.
10445 case ISD::FP_TO_SINT: {
10446 std::pair<SDValue,SDValue> Vals =
10447 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10448 SDValue FIST = Vals.first, StackSlot = Vals.second;
10449 if (FIST.getNode() != 0) {
10450 EVT VT = N->getValueType(0);
10451 // Return a load from the stack slot.
10452 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10453 MachinePointerInfo(), false, false, 0));
10457 case ISD::READCYCLECOUNTER: {
10458 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10459 SDValue TheChain = N->getOperand(0);
10460 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10461 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10463 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10465 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10466 SDValue Ops[] = { eax, edx };
10467 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10468 Results.push_back(edx.getValue(1));
10471 case ISD::ATOMIC_CMP_SWAP: {
10472 EVT T = N->getValueType(0);
10473 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10474 bool Regs64bit = T == MVT::i128;
10475 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10476 SDValue cpInL, cpInH;
10477 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10478 DAG.getConstant(0, HalfT));
10479 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10480 DAG.getConstant(1, HalfT));
10481 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10482 Regs64bit ? X86::RAX : X86::EAX,
10484 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10485 Regs64bit ? X86::RDX : X86::EDX,
10486 cpInH, cpInL.getValue(1));
10487 SDValue swapInL, swapInH;
10488 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10489 DAG.getConstant(0, HalfT));
10490 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10491 DAG.getConstant(1, HalfT));
10492 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10493 Regs64bit ? X86::RBX : X86::EBX,
10494 swapInL, cpInH.getValue(1));
10495 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10496 Regs64bit ? X86::RCX : X86::ECX,
10497 swapInH, swapInL.getValue(1));
10498 SDValue Ops[] = { swapInH.getValue(0),
10500 swapInH.getValue(1) };
10501 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10502 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10503 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10504 X86ISD::LCMPXCHG8_DAG;
10505 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10507 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10508 Regs64bit ? X86::RAX : X86::EAX,
10509 HalfT, Result.getValue(1));
10510 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10511 Regs64bit ? X86::RDX : X86::EDX,
10512 HalfT, cpOutL.getValue(2));
10513 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10514 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10515 Results.push_back(cpOutH.getValue(1));
10518 case ISD::ATOMIC_LOAD_ADD:
10519 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10521 case ISD::ATOMIC_LOAD_AND:
10522 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10524 case ISD::ATOMIC_LOAD_NAND:
10525 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10527 case ISD::ATOMIC_LOAD_OR:
10528 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10530 case ISD::ATOMIC_LOAD_SUB:
10531 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10533 case ISD::ATOMIC_LOAD_XOR:
10534 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10536 case ISD::ATOMIC_SWAP:
10537 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10539 case ISD::ATOMIC_LOAD:
10540 ReplaceATOMIC_LOAD(N, Results, DAG);
10544 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10546 default: return NULL;
10547 case X86ISD::BSF: return "X86ISD::BSF";
10548 case X86ISD::BSR: return "X86ISD::BSR";
10549 case X86ISD::SHLD: return "X86ISD::SHLD";
10550 case X86ISD::SHRD: return "X86ISD::SHRD";
10551 case X86ISD::FAND: return "X86ISD::FAND";
10552 case X86ISD::FOR: return "X86ISD::FOR";
10553 case X86ISD::FXOR: return "X86ISD::FXOR";
10554 case X86ISD::FSRL: return "X86ISD::FSRL";
10555 case X86ISD::FILD: return "X86ISD::FILD";
10556 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10557 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10558 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10559 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10560 case X86ISD::FLD: return "X86ISD::FLD";
10561 case X86ISD::FST: return "X86ISD::FST";
10562 case X86ISD::CALL: return "X86ISD::CALL";
10563 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10564 case X86ISD::BT: return "X86ISD::BT";
10565 case X86ISD::CMP: return "X86ISD::CMP";
10566 case X86ISD::COMI: return "X86ISD::COMI";
10567 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10568 case X86ISD::SETCC: return "X86ISD::SETCC";
10569 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10570 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10571 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10572 case X86ISD::CMOV: return "X86ISD::CMOV";
10573 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10574 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10575 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10576 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10577 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10578 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10579 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10580 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10581 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10582 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10583 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10584 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10585 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10586 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10587 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
10588 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
10589 case X86ISD::PSIGND: return "X86ISD::PSIGND";
10590 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
10591 case X86ISD::FMAX: return "X86ISD::FMAX";
10592 case X86ISD::FMIN: return "X86ISD::FMIN";
10593 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10594 case X86ISD::FRCP: return "X86ISD::FRCP";
10595 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10596 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10597 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10598 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10599 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10600 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10601 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10602 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10603 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10604 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10605 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10606 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10607 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10608 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10609 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10610 case X86ISD::VSHL: return "X86ISD::VSHL";
10611 case X86ISD::VSRL: return "X86ISD::VSRL";
10612 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10613 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10614 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10615 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10616 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10617 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10618 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10619 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10620 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10621 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10622 case X86ISD::ADD: return "X86ISD::ADD";
10623 case X86ISD::SUB: return "X86ISD::SUB";
10624 case X86ISD::ADC: return "X86ISD::ADC";
10625 case X86ISD::SBB: return "X86ISD::SBB";
10626 case X86ISD::SMUL: return "X86ISD::SMUL";
10627 case X86ISD::UMUL: return "X86ISD::UMUL";
10628 case X86ISD::INC: return "X86ISD::INC";
10629 case X86ISD::DEC: return "X86ISD::DEC";
10630 case X86ISD::OR: return "X86ISD::OR";
10631 case X86ISD::XOR: return "X86ISD::XOR";
10632 case X86ISD::AND: return "X86ISD::AND";
10633 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10634 case X86ISD::PTEST: return "X86ISD::PTEST";
10635 case X86ISD::TESTP: return "X86ISD::TESTP";
10636 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10637 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10638 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10639 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10640 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10641 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10642 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10643 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10644 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10645 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10646 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10647 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
10648 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10649 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10650 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10651 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10652 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10653 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10654 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10655 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10656 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10657 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
10658 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
10659 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
10660 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
10661 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
10662 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
10663 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
10664 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
10665 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
10666 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
10667 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
10668 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
10669 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
10670 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10671 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
10672 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
10673 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
10674 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
10675 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
10676 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10677 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10678 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10679 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10680 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
10684 // isLegalAddressingMode - Return true if the addressing mode represented
10685 // by AM is legal for this target, for a load/store of the specified type.
10686 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10688 // X86 supports extremely general addressing modes.
10689 CodeModel::Model M = getTargetMachine().getCodeModel();
10690 Reloc::Model R = getTargetMachine().getRelocationModel();
10692 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10693 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10698 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10700 // If a reference to this global requires an extra load, we can't fold it.
10701 if (isGlobalStubReference(GVFlags))
10704 // If BaseGV requires a register for the PIC base, we cannot also have a
10705 // BaseReg specified.
10706 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
10709 // If lower 4G is not available, then we must use rip-relative addressing.
10710 if ((M != CodeModel::Small || R != Reloc::Static) &&
10711 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
10715 switch (AM.Scale) {
10721 // These scales always work.
10726 // These scales are formed with basereg+scalereg. Only accept if there is
10731 default: // Other stuff never works.
10739 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
10740 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10742 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
10743 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
10744 if (NumBits1 <= NumBits2)
10749 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
10750 if (!VT1.isInteger() || !VT2.isInteger())
10752 unsigned NumBits1 = VT1.getSizeInBits();
10753 unsigned NumBits2 = VT2.getSizeInBits();
10754 if (NumBits1 <= NumBits2)
10759 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
10760 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10761 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
10764 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
10765 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10766 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
10769 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
10770 // i16 instructions are longer (0x66 prefix) and potentially slower.
10771 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
10774 /// isShuffleMaskLegal - Targets can use this to indicate that they only
10775 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
10776 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
10777 /// are assumed to be legal.
10779 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
10781 // Very little shuffling can be done for 64-bit vectors right now.
10782 if (VT.getSizeInBits() == 64)
10783 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
10785 // FIXME: pshufb, blends, shifts.
10786 return (VT.getVectorNumElements() == 2 ||
10787 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
10788 isMOVLMask(M, VT) ||
10789 isSHUFPMask(M, VT) ||
10790 isPSHUFDMask(M, VT) ||
10791 isPSHUFHWMask(M, VT) ||
10792 isPSHUFLWMask(M, VT) ||
10793 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
10794 isUNPCKLMask(M, VT) ||
10795 isUNPCKHMask(M, VT) ||
10796 isUNPCKL_v_undef_Mask(M, VT) ||
10797 isUNPCKH_v_undef_Mask(M, VT));
10801 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
10803 unsigned NumElts = VT.getVectorNumElements();
10804 // FIXME: This collection of masks seems suspect.
10807 if (NumElts == 4 && VT.getSizeInBits() == 128) {
10808 return (isMOVLMask(Mask, VT) ||
10809 isCommutedMOVLMask(Mask, VT, true) ||
10810 isSHUFPMask(Mask, VT) ||
10811 isCommutedSHUFPMask(Mask, VT));
10816 //===----------------------------------------------------------------------===//
10817 // X86 Scheduler Hooks
10818 //===----------------------------------------------------------------------===//
10820 // private utility function
10821 MachineBasicBlock *
10822 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
10823 MachineBasicBlock *MBB,
10830 TargetRegisterClass *RC,
10831 bool invSrc) const {
10832 // For the atomic bitwise operator, we generate
10835 // ld t1 = [bitinstr.addr]
10836 // op t2 = t1, [bitinstr.val]
10838 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10840 // fallthrough -->nextMBB
10841 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10842 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10843 MachineFunction::iterator MBBIter = MBB;
10846 /// First build the CFG
10847 MachineFunction *F = MBB->getParent();
10848 MachineBasicBlock *thisMBB = MBB;
10849 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10850 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10851 F->insert(MBBIter, newMBB);
10852 F->insert(MBBIter, nextMBB);
10854 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10855 nextMBB->splice(nextMBB->begin(), thisMBB,
10856 llvm::next(MachineBasicBlock::iterator(bInstr)),
10858 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10860 // Update thisMBB to fall through to newMBB
10861 thisMBB->addSuccessor(newMBB);
10863 // newMBB jumps to itself and fall through to nextMBB
10864 newMBB->addSuccessor(nextMBB);
10865 newMBB->addSuccessor(newMBB);
10867 // Insert instructions into newMBB based on incoming instruction
10868 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10869 "unexpected number of operands");
10870 DebugLoc dl = bInstr->getDebugLoc();
10871 MachineOperand& destOper = bInstr->getOperand(0);
10872 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10873 int numArgs = bInstr->getNumOperands() - 1;
10874 for (int i=0; i < numArgs; ++i)
10875 argOpers[i] = &bInstr->getOperand(i+1);
10877 // x86 address has 4 operands: base, index, scale, and displacement
10878 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10879 int valArgIndx = lastAddrIndx + 1;
10881 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10882 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
10883 for (int i=0; i <= lastAddrIndx; ++i)
10884 (*MIB).addOperand(*argOpers[i]);
10886 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
10888 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
10893 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10894 assert((argOpers[valArgIndx]->isReg() ||
10895 argOpers[valArgIndx]->isImm()) &&
10896 "invalid operand");
10897 if (argOpers[valArgIndx]->isReg())
10898 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
10900 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
10902 (*MIB).addOperand(*argOpers[valArgIndx]);
10904 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
10907 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
10908 for (int i=0; i <= lastAddrIndx; ++i)
10909 (*MIB).addOperand(*argOpers[i]);
10911 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10912 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10913 bInstr->memoperands_end());
10915 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10916 MIB.addReg(EAXreg);
10919 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10921 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10925 // private utility function: 64 bit atomics on 32 bit host.
10926 MachineBasicBlock *
10927 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
10928 MachineBasicBlock *MBB,
10933 bool invSrc) const {
10934 // For the atomic bitwise operator, we generate
10935 // thisMBB (instructions are in pairs, except cmpxchg8b)
10936 // ld t1,t2 = [bitinstr.addr]
10938 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
10939 // op t5, t6 <- out1, out2, [bitinstr.val]
10940 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
10941 // mov ECX, EBX <- t5, t6
10942 // mov EAX, EDX <- t1, t2
10943 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
10944 // mov t3, t4 <- EAX, EDX
10946 // result in out1, out2
10947 // fallthrough -->nextMBB
10949 const TargetRegisterClass *RC = X86::GR32RegisterClass;
10950 const unsigned LoadOpc = X86::MOV32rm;
10951 const unsigned NotOpc = X86::NOT32r;
10952 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10953 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10954 MachineFunction::iterator MBBIter = MBB;
10957 /// First build the CFG
10958 MachineFunction *F = MBB->getParent();
10959 MachineBasicBlock *thisMBB = MBB;
10960 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10961 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10962 F->insert(MBBIter, newMBB);
10963 F->insert(MBBIter, nextMBB);
10965 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10966 nextMBB->splice(nextMBB->begin(), thisMBB,
10967 llvm::next(MachineBasicBlock::iterator(bInstr)),
10969 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10971 // Update thisMBB to fall through to newMBB
10972 thisMBB->addSuccessor(newMBB);
10974 // newMBB jumps to itself and fall through to nextMBB
10975 newMBB->addSuccessor(nextMBB);
10976 newMBB->addSuccessor(newMBB);
10978 DebugLoc dl = bInstr->getDebugLoc();
10979 // Insert instructions into newMBB based on incoming instruction
10980 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
10981 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
10982 "unexpected number of operands");
10983 MachineOperand& dest1Oper = bInstr->getOperand(0);
10984 MachineOperand& dest2Oper = bInstr->getOperand(1);
10985 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10986 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
10987 argOpers[i] = &bInstr->getOperand(i+2);
10989 // We use some of the operands multiple times, so conservatively just
10990 // clear any kill flags that might be present.
10991 if (argOpers[i]->isReg() && argOpers[i]->isUse())
10992 argOpers[i]->setIsKill(false);
10995 // x86 address has 5 operands: base, index, scale, displacement, and segment.
10996 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10998 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10999 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11000 for (int i=0; i <= lastAddrIndx; ++i)
11001 (*MIB).addOperand(*argOpers[i]);
11002 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11003 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11004 // add 4 to displacement.
11005 for (int i=0; i <= lastAddrIndx-2; ++i)
11006 (*MIB).addOperand(*argOpers[i]);
11007 MachineOperand newOp3 = *(argOpers[3]);
11008 if (newOp3.isImm())
11009 newOp3.setImm(newOp3.getImm()+4);
11011 newOp3.setOffset(newOp3.getOffset()+4);
11012 (*MIB).addOperand(newOp3);
11013 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11015 // t3/4 are defined later, at the bottom of the loop
11016 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11017 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11018 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11019 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11020 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11021 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11023 // The subsequent operations should be using the destination registers of
11024 //the PHI instructions.
11026 t1 = F->getRegInfo().createVirtualRegister(RC);
11027 t2 = F->getRegInfo().createVirtualRegister(RC);
11028 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11029 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11031 t1 = dest1Oper.getReg();
11032 t2 = dest2Oper.getReg();
11035 int valArgIndx = lastAddrIndx + 1;
11036 assert((argOpers[valArgIndx]->isReg() ||
11037 argOpers[valArgIndx]->isImm()) &&
11038 "invalid operand");
11039 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11040 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11041 if (argOpers[valArgIndx]->isReg())
11042 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11044 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11045 if (regOpcL != X86::MOV32rr)
11047 (*MIB).addOperand(*argOpers[valArgIndx]);
11048 assert(argOpers[valArgIndx + 1]->isReg() ==
11049 argOpers[valArgIndx]->isReg());
11050 assert(argOpers[valArgIndx + 1]->isImm() ==
11051 argOpers[valArgIndx]->isImm());
11052 if (argOpers[valArgIndx + 1]->isReg())
11053 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11055 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11056 if (regOpcH != X86::MOV32rr)
11058 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11060 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11062 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11065 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11067 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11070 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11071 for (int i=0; i <= lastAddrIndx; ++i)
11072 (*MIB).addOperand(*argOpers[i]);
11074 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11075 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11076 bInstr->memoperands_end());
11078 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11079 MIB.addReg(X86::EAX);
11080 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11081 MIB.addReg(X86::EDX);
11084 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11086 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11090 // private utility function
11091 MachineBasicBlock *
11092 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11093 MachineBasicBlock *MBB,
11094 unsigned cmovOpc) const {
11095 // For the atomic min/max operator, we generate
11098 // ld t1 = [min/max.addr]
11099 // mov t2 = [min/max.val]
11101 // cmov[cond] t2 = t1
11103 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11105 // fallthrough -->nextMBB
11107 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11108 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11109 MachineFunction::iterator MBBIter = MBB;
11112 /// First build the CFG
11113 MachineFunction *F = MBB->getParent();
11114 MachineBasicBlock *thisMBB = MBB;
11115 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11116 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11117 F->insert(MBBIter, newMBB);
11118 F->insert(MBBIter, nextMBB);
11120 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11121 nextMBB->splice(nextMBB->begin(), thisMBB,
11122 llvm::next(MachineBasicBlock::iterator(mInstr)),
11124 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11126 // Update thisMBB to fall through to newMBB
11127 thisMBB->addSuccessor(newMBB);
11129 // newMBB jumps to newMBB and fall through to nextMBB
11130 newMBB->addSuccessor(nextMBB);
11131 newMBB->addSuccessor(newMBB);
11133 DebugLoc dl = mInstr->getDebugLoc();
11134 // Insert instructions into newMBB based on incoming instruction
11135 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11136 "unexpected number of operands");
11137 MachineOperand& destOper = mInstr->getOperand(0);
11138 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11139 int numArgs = mInstr->getNumOperands() - 1;
11140 for (int i=0; i < numArgs; ++i)
11141 argOpers[i] = &mInstr->getOperand(i+1);
11143 // x86 address has 4 operands: base, index, scale, and displacement
11144 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11145 int valArgIndx = lastAddrIndx + 1;
11147 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11148 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11149 for (int i=0; i <= lastAddrIndx; ++i)
11150 (*MIB).addOperand(*argOpers[i]);
11152 // We only support register and immediate values
11153 assert((argOpers[valArgIndx]->isReg() ||
11154 argOpers[valArgIndx]->isImm()) &&
11155 "invalid operand");
11157 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11158 if (argOpers[valArgIndx]->isReg())
11159 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11161 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11162 (*MIB).addOperand(*argOpers[valArgIndx]);
11164 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11167 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11172 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11173 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11177 // Cmp and exchange if none has modified the memory location
11178 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11179 for (int i=0; i <= lastAddrIndx; ++i)
11180 (*MIB).addOperand(*argOpers[i]);
11182 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11183 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11184 mInstr->memoperands_end());
11186 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11187 MIB.addReg(X86::EAX);
11190 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11192 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11196 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11197 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11198 // in the .td file.
11199 MachineBasicBlock *
11200 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11201 unsigned numArgs, bool memArg) const {
11202 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
11203 "Target must have SSE4.2 or AVX features enabled");
11205 DebugLoc dl = MI->getDebugLoc();
11206 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11208 if (!Subtarget->hasAVX()) {
11210 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11212 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11215 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11217 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11220 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11221 for (unsigned i = 0; i < numArgs; ++i) {
11222 MachineOperand &Op = MI->getOperand(i+1);
11223 if (!(Op.isReg() && Op.isImplicit()))
11224 MIB.addOperand(Op);
11226 BuildMI(*BB, MI, dl,
11227 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11228 MI->getOperand(0).getReg())
11229 .addReg(X86::XMM0);
11231 MI->eraseFromParent();
11235 MachineBasicBlock *
11236 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11237 DebugLoc dl = MI->getDebugLoc();
11238 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11240 // Address into RAX/EAX, other two args into ECX, EDX.
11241 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11242 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11243 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11244 for (int i = 0; i < X86::AddrNumOperands; ++i)
11245 MIB.addOperand(MI->getOperand(i));
11247 unsigned ValOps = X86::AddrNumOperands;
11248 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11249 .addReg(MI->getOperand(ValOps).getReg());
11250 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11251 .addReg(MI->getOperand(ValOps+1).getReg());
11253 // The instruction doesn't actually take any operands though.
11254 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11256 MI->eraseFromParent(); // The pseudo is gone now.
11260 MachineBasicBlock *
11261 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11262 DebugLoc dl = MI->getDebugLoc();
11263 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11265 // First arg in ECX, the second in EAX.
11266 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11267 .addReg(MI->getOperand(0).getReg());
11268 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11269 .addReg(MI->getOperand(1).getReg());
11271 // The instruction doesn't actually take any operands though.
11272 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11274 MI->eraseFromParent(); // The pseudo is gone now.
11278 MachineBasicBlock *
11279 X86TargetLowering::EmitVAARG64WithCustomInserter(
11281 MachineBasicBlock *MBB) const {
11282 // Emit va_arg instruction on X86-64.
11284 // Operands to this pseudo-instruction:
11285 // 0 ) Output : destination address (reg)
11286 // 1-5) Input : va_list address (addr, i64mem)
11287 // 6 ) ArgSize : Size (in bytes) of vararg type
11288 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11289 // 8 ) Align : Alignment of type
11290 // 9 ) EFLAGS (implicit-def)
11292 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11293 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11295 unsigned DestReg = MI->getOperand(0).getReg();
11296 MachineOperand &Base = MI->getOperand(1);
11297 MachineOperand &Scale = MI->getOperand(2);
11298 MachineOperand &Index = MI->getOperand(3);
11299 MachineOperand &Disp = MI->getOperand(4);
11300 MachineOperand &Segment = MI->getOperand(5);
11301 unsigned ArgSize = MI->getOperand(6).getImm();
11302 unsigned ArgMode = MI->getOperand(7).getImm();
11303 unsigned Align = MI->getOperand(8).getImm();
11305 // Memory Reference
11306 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11307 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11308 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11310 // Machine Information
11311 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11312 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11313 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11314 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11315 DebugLoc DL = MI->getDebugLoc();
11317 // struct va_list {
11320 // i64 overflow_area (address)
11321 // i64 reg_save_area (address)
11323 // sizeof(va_list) = 24
11324 // alignment(va_list) = 8
11326 unsigned TotalNumIntRegs = 6;
11327 unsigned TotalNumXMMRegs = 8;
11328 bool UseGPOffset = (ArgMode == 1);
11329 bool UseFPOffset = (ArgMode == 2);
11330 unsigned MaxOffset = TotalNumIntRegs * 8 +
11331 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11333 /* Align ArgSize to a multiple of 8 */
11334 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11335 bool NeedsAlign = (Align > 8);
11337 MachineBasicBlock *thisMBB = MBB;
11338 MachineBasicBlock *overflowMBB;
11339 MachineBasicBlock *offsetMBB;
11340 MachineBasicBlock *endMBB;
11342 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11343 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11344 unsigned OffsetReg = 0;
11346 if (!UseGPOffset && !UseFPOffset) {
11347 // If we only pull from the overflow region, we don't create a branch.
11348 // We don't need to alter control flow.
11349 OffsetDestReg = 0; // unused
11350 OverflowDestReg = DestReg;
11353 overflowMBB = thisMBB;
11356 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11357 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11358 // If not, pull from overflow_area. (branch to overflowMBB)
11363 // offsetMBB overflowMBB
11368 // Registers for the PHI in endMBB
11369 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11370 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11372 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11373 MachineFunction *MF = MBB->getParent();
11374 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11375 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11376 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11378 MachineFunction::iterator MBBIter = MBB;
11381 // Insert the new basic blocks
11382 MF->insert(MBBIter, offsetMBB);
11383 MF->insert(MBBIter, overflowMBB);
11384 MF->insert(MBBIter, endMBB);
11386 // Transfer the remainder of MBB and its successor edges to endMBB.
11387 endMBB->splice(endMBB->begin(), thisMBB,
11388 llvm::next(MachineBasicBlock::iterator(MI)),
11390 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11392 // Make offsetMBB and overflowMBB successors of thisMBB
11393 thisMBB->addSuccessor(offsetMBB);
11394 thisMBB->addSuccessor(overflowMBB);
11396 // endMBB is a successor of both offsetMBB and overflowMBB
11397 offsetMBB->addSuccessor(endMBB);
11398 overflowMBB->addSuccessor(endMBB);
11400 // Load the offset value into a register
11401 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11402 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11406 .addDisp(Disp, UseFPOffset ? 4 : 0)
11407 .addOperand(Segment)
11408 .setMemRefs(MMOBegin, MMOEnd);
11410 // Check if there is enough room left to pull this argument.
11411 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11413 .addImm(MaxOffset + 8 - ArgSizeA8);
11415 // Branch to "overflowMBB" if offset >= max
11416 // Fall through to "offsetMBB" otherwise
11417 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11418 .addMBB(overflowMBB);
11421 // In offsetMBB, emit code to use the reg_save_area.
11423 assert(OffsetReg != 0);
11425 // Read the reg_save_area address.
11426 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11427 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11432 .addOperand(Segment)
11433 .setMemRefs(MMOBegin, MMOEnd);
11435 // Zero-extend the offset
11436 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11437 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11440 .addImm(X86::sub_32bit);
11442 // Add the offset to the reg_save_area to get the final address.
11443 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11444 .addReg(OffsetReg64)
11445 .addReg(RegSaveReg);
11447 // Compute the offset for the next argument
11448 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11449 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11451 .addImm(UseFPOffset ? 16 : 8);
11453 // Store it back into the va_list.
11454 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11458 .addDisp(Disp, UseFPOffset ? 4 : 0)
11459 .addOperand(Segment)
11460 .addReg(NextOffsetReg)
11461 .setMemRefs(MMOBegin, MMOEnd);
11464 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11469 // Emit code to use overflow area
11472 // Load the overflow_area address into a register.
11473 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11474 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11479 .addOperand(Segment)
11480 .setMemRefs(MMOBegin, MMOEnd);
11482 // If we need to align it, do so. Otherwise, just copy the address
11483 // to OverflowDestReg.
11485 // Align the overflow address
11486 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11487 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11489 // aligned_addr = (addr + (align-1)) & ~(align-1)
11490 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11491 .addReg(OverflowAddrReg)
11494 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11496 .addImm(~(uint64_t)(Align-1));
11498 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11499 .addReg(OverflowAddrReg);
11502 // Compute the next overflow address after this argument.
11503 // (the overflow address should be kept 8-byte aligned)
11504 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11505 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11506 .addReg(OverflowDestReg)
11507 .addImm(ArgSizeA8);
11509 // Store the new overflow address.
11510 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11515 .addOperand(Segment)
11516 .addReg(NextAddrReg)
11517 .setMemRefs(MMOBegin, MMOEnd);
11519 // If we branched, emit the PHI to the front of endMBB.
11521 BuildMI(*endMBB, endMBB->begin(), DL,
11522 TII->get(X86::PHI), DestReg)
11523 .addReg(OffsetDestReg).addMBB(offsetMBB)
11524 .addReg(OverflowDestReg).addMBB(overflowMBB);
11527 // Erase the pseudo instruction
11528 MI->eraseFromParent();
11533 MachineBasicBlock *
11534 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11536 MachineBasicBlock *MBB) const {
11537 // Emit code to save XMM registers to the stack. The ABI says that the
11538 // number of registers to save is given in %al, so it's theoretically
11539 // possible to do an indirect jump trick to avoid saving all of them,
11540 // however this code takes a simpler approach and just executes all
11541 // of the stores if %al is non-zero. It's less code, and it's probably
11542 // easier on the hardware branch predictor, and stores aren't all that
11543 // expensive anyway.
11545 // Create the new basic blocks. One block contains all the XMM stores,
11546 // and one block is the final destination regardless of whether any
11547 // stores were performed.
11548 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11549 MachineFunction *F = MBB->getParent();
11550 MachineFunction::iterator MBBIter = MBB;
11552 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11553 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11554 F->insert(MBBIter, XMMSaveMBB);
11555 F->insert(MBBIter, EndMBB);
11557 // Transfer the remainder of MBB and its successor edges to EndMBB.
11558 EndMBB->splice(EndMBB->begin(), MBB,
11559 llvm::next(MachineBasicBlock::iterator(MI)),
11561 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11563 // The original block will now fall through to the XMM save block.
11564 MBB->addSuccessor(XMMSaveMBB);
11565 // The XMMSaveMBB will fall through to the end block.
11566 XMMSaveMBB->addSuccessor(EndMBB);
11568 // Now add the instructions.
11569 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11570 DebugLoc DL = MI->getDebugLoc();
11572 unsigned CountReg = MI->getOperand(0).getReg();
11573 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11574 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11576 if (!Subtarget->isTargetWin64()) {
11577 // If %al is 0, branch around the XMM save block.
11578 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11579 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11580 MBB->addSuccessor(EndMBB);
11583 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11584 // In the XMM save block, save all the XMM argument registers.
11585 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11586 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11587 MachineMemOperand *MMO =
11588 F->getMachineMemOperand(
11589 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11590 MachineMemOperand::MOStore,
11591 /*Size=*/16, /*Align=*/16);
11592 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11593 .addFrameIndex(RegSaveFrameIndex)
11594 .addImm(/*Scale=*/1)
11595 .addReg(/*IndexReg=*/0)
11596 .addImm(/*Disp=*/Offset)
11597 .addReg(/*Segment=*/0)
11598 .addReg(MI->getOperand(i).getReg())
11599 .addMemOperand(MMO);
11602 MI->eraseFromParent(); // The pseudo instruction is gone now.
11607 MachineBasicBlock *
11608 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11609 MachineBasicBlock *BB) const {
11610 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11611 DebugLoc DL = MI->getDebugLoc();
11613 // To "insert" a SELECT_CC instruction, we actually have to insert the
11614 // diamond control-flow pattern. The incoming instruction knows the
11615 // destination vreg to set, the condition code register to branch on, the
11616 // true/false values to select between, and a branch opcode to use.
11617 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11618 MachineFunction::iterator It = BB;
11624 // cmpTY ccX, r1, r2
11626 // fallthrough --> copy0MBB
11627 MachineBasicBlock *thisMBB = BB;
11628 MachineFunction *F = BB->getParent();
11629 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11630 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11631 F->insert(It, copy0MBB);
11632 F->insert(It, sinkMBB);
11634 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11635 // live into the sink and copy blocks.
11636 const MachineFunction *MF = BB->getParent();
11637 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
11638 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
11640 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
11641 const MachineOperand &MO = MI->getOperand(I);
11642 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
11643 unsigned Reg = MO.getReg();
11644 if (Reg != X86::EFLAGS) continue;
11645 copy0MBB->addLiveIn(Reg);
11646 sinkMBB->addLiveIn(Reg);
11649 // Transfer the remainder of BB and its successor edges to sinkMBB.
11650 sinkMBB->splice(sinkMBB->begin(), BB,
11651 llvm::next(MachineBasicBlock::iterator(MI)),
11653 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11655 // Add the true and fallthrough blocks as its successors.
11656 BB->addSuccessor(copy0MBB);
11657 BB->addSuccessor(sinkMBB);
11659 // Create the conditional branch instruction.
11661 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11662 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11665 // %FalseValue = ...
11666 // # fallthrough to sinkMBB
11667 copy0MBB->addSuccessor(sinkMBB);
11670 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11672 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11673 TII->get(X86::PHI), MI->getOperand(0).getReg())
11674 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11675 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11677 MI->eraseFromParent(); // The pseudo instruction is gone now.
11681 MachineBasicBlock *
11682 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
11683 bool Is64Bit) const {
11684 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11685 DebugLoc DL = MI->getDebugLoc();
11686 MachineFunction *MF = BB->getParent();
11687 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11689 assert(EnableSegmentedStacks);
11691 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
11692 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
11695 // ... [Till the alloca]
11696 // If stacklet is not large enough, jump to mallocMBB
11699 // Allocate by subtracting from RSP
11700 // Jump to continueMBB
11703 // Allocate by call to runtime
11707 // [rest of original BB]
11710 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11711 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11712 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11714 MachineRegisterInfo &MRI = MF->getRegInfo();
11715 const TargetRegisterClass *AddrRegClass =
11716 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
11718 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
11719 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
11720 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
11721 sizeVReg = MI->getOperand(1).getReg(),
11722 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
11724 MachineFunction::iterator MBBIter = BB;
11727 MF->insert(MBBIter, bumpMBB);
11728 MF->insert(MBBIter, mallocMBB);
11729 MF->insert(MBBIter, continueMBB);
11731 continueMBB->splice(continueMBB->begin(), BB, llvm::next
11732 (MachineBasicBlock::iterator(MI)), BB->end());
11733 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
11735 // Add code to the main basic block to check if the stack limit has been hit,
11736 // and if so, jump to mallocMBB otherwise to bumpMBB.
11737 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
11738 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), tmpSPVReg)
11739 .addReg(tmpSPVReg).addReg(sizeVReg);
11740 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
11741 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg)
11742 .addReg(tmpSPVReg);
11743 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
11745 // bumpMBB simply decreases the stack pointer, since we know the current
11746 // stacklet has enough space.
11747 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
11748 .addReg(tmpSPVReg);
11749 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
11750 .addReg(tmpSPVReg);
11751 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
11753 // Calls into a routine in libgcc to allocate more space from the heap.
11755 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
11757 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
11758 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
11760 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
11762 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
11763 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
11764 .addExternalSymbol("__morestack_allocate_stack_space");
11768 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
11771 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
11772 .addReg(Is64Bit ? X86::RAX : X86::EAX);
11773 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
11775 // Set up the CFG correctly.
11776 BB->addSuccessor(bumpMBB);
11777 BB->addSuccessor(mallocMBB);
11778 mallocMBB->addSuccessor(continueMBB);
11779 bumpMBB->addSuccessor(continueMBB);
11781 // Take care of the PHI nodes.
11782 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
11783 MI->getOperand(0).getReg())
11784 .addReg(mallocPtrVReg).addMBB(mallocMBB)
11785 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
11787 // Delete the original pseudo instruction.
11788 MI->eraseFromParent();
11791 return continueMBB;
11794 MachineBasicBlock *
11795 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
11796 MachineBasicBlock *BB) const {
11797 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11798 DebugLoc DL = MI->getDebugLoc();
11800 assert(!Subtarget->isTargetEnvMacho());
11802 // The lowering is pretty easy: we're just emitting the call to _alloca. The
11803 // non-trivial part is impdef of ESP.
11805 if (Subtarget->isTargetWin64()) {
11806 if (Subtarget->isTargetCygMing()) {
11807 // ___chkstk(Mingw64):
11808 // Clobbers R10, R11, RAX and EFLAGS.
11810 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11811 .addExternalSymbol("___chkstk")
11812 .addReg(X86::RAX, RegState::Implicit)
11813 .addReg(X86::RSP, RegState::Implicit)
11814 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
11815 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
11816 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11818 // __chkstk(MSVCRT): does not update stack pointer.
11819 // Clobbers R10, R11 and EFLAGS.
11820 // FIXME: RAX(allocated size) might be reused and not killed.
11821 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11822 .addExternalSymbol("__chkstk")
11823 .addReg(X86::RAX, RegState::Implicit)
11824 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11825 // RAX has the offset to subtracted from RSP.
11826 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
11831 const char *StackProbeSymbol =
11832 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
11834 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
11835 .addExternalSymbol(StackProbeSymbol)
11836 .addReg(X86::EAX, RegState::Implicit)
11837 .addReg(X86::ESP, RegState::Implicit)
11838 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
11839 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
11840 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11843 MI->eraseFromParent(); // The pseudo instruction is gone now.
11847 MachineBasicBlock *
11848 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
11849 MachineBasicBlock *BB) const {
11850 // This is pretty easy. We're taking the value that we received from
11851 // our load from the relocation, sticking it in either RDI (x86-64)
11852 // or EAX and doing an indirect call. The return value will then
11853 // be in the normal return register.
11854 const X86InstrInfo *TII
11855 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
11856 DebugLoc DL = MI->getDebugLoc();
11857 MachineFunction *F = BB->getParent();
11859 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
11860 assert(MI->getOperand(3).isGlobal() && "This should be a global");
11862 if (Subtarget->is64Bit()) {
11863 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11864 TII->get(X86::MOV64rm), X86::RDI)
11866 .addImm(0).addReg(0)
11867 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11868 MI->getOperand(3).getTargetFlags())
11870 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
11871 addDirectMem(MIB, X86::RDI);
11872 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
11873 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11874 TII->get(X86::MOV32rm), X86::EAX)
11876 .addImm(0).addReg(0)
11877 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11878 MI->getOperand(3).getTargetFlags())
11880 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11881 addDirectMem(MIB, X86::EAX);
11883 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11884 TII->get(X86::MOV32rm), X86::EAX)
11885 .addReg(TII->getGlobalBaseReg(F))
11886 .addImm(0).addReg(0)
11887 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11888 MI->getOperand(3).getTargetFlags())
11890 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11891 addDirectMem(MIB, X86::EAX);
11894 MI->eraseFromParent(); // The pseudo instruction is gone now.
11898 MachineBasicBlock *
11899 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
11900 MachineBasicBlock *BB) const {
11901 switch (MI->getOpcode()) {
11902 default: assert(false && "Unexpected instr type to insert");
11903 case X86::TAILJMPd64:
11904 case X86::TAILJMPr64:
11905 case X86::TAILJMPm64:
11906 assert(!"TAILJMP64 would not be touched here.");
11907 case X86::TCRETURNdi64:
11908 case X86::TCRETURNri64:
11909 case X86::TCRETURNmi64:
11910 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
11911 // On AMD64, additional defs should be added before register allocation.
11912 if (!Subtarget->isTargetWin64()) {
11913 MI->addRegisterDefined(X86::RSI);
11914 MI->addRegisterDefined(X86::RDI);
11915 MI->addRegisterDefined(X86::XMM6);
11916 MI->addRegisterDefined(X86::XMM7);
11917 MI->addRegisterDefined(X86::XMM8);
11918 MI->addRegisterDefined(X86::XMM9);
11919 MI->addRegisterDefined(X86::XMM10);
11920 MI->addRegisterDefined(X86::XMM11);
11921 MI->addRegisterDefined(X86::XMM12);
11922 MI->addRegisterDefined(X86::XMM13);
11923 MI->addRegisterDefined(X86::XMM14);
11924 MI->addRegisterDefined(X86::XMM15);
11927 case X86::WIN_ALLOCA:
11928 return EmitLoweredWinAlloca(MI, BB);
11929 case X86::SEG_ALLOCA_32:
11930 return EmitLoweredSegAlloca(MI, BB, false);
11931 case X86::SEG_ALLOCA_64:
11932 return EmitLoweredSegAlloca(MI, BB, true);
11933 case X86::TLSCall_32:
11934 case X86::TLSCall_64:
11935 return EmitLoweredTLSCall(MI, BB);
11936 case X86::CMOV_GR8:
11937 case X86::CMOV_FR32:
11938 case X86::CMOV_FR64:
11939 case X86::CMOV_V4F32:
11940 case X86::CMOV_V2F64:
11941 case X86::CMOV_V2I64:
11942 case X86::CMOV_V8F32:
11943 case X86::CMOV_V4F64:
11944 case X86::CMOV_V4I64:
11945 case X86::CMOV_GR16:
11946 case X86::CMOV_GR32:
11947 case X86::CMOV_RFP32:
11948 case X86::CMOV_RFP64:
11949 case X86::CMOV_RFP80:
11950 return EmitLoweredSelect(MI, BB);
11952 case X86::FP32_TO_INT16_IN_MEM:
11953 case X86::FP32_TO_INT32_IN_MEM:
11954 case X86::FP32_TO_INT64_IN_MEM:
11955 case X86::FP64_TO_INT16_IN_MEM:
11956 case X86::FP64_TO_INT32_IN_MEM:
11957 case X86::FP64_TO_INT64_IN_MEM:
11958 case X86::FP80_TO_INT16_IN_MEM:
11959 case X86::FP80_TO_INT32_IN_MEM:
11960 case X86::FP80_TO_INT64_IN_MEM: {
11961 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11962 DebugLoc DL = MI->getDebugLoc();
11964 // Change the floating point control register to use "round towards zero"
11965 // mode when truncating to an integer value.
11966 MachineFunction *F = BB->getParent();
11967 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
11968 addFrameReference(BuildMI(*BB, MI, DL,
11969 TII->get(X86::FNSTCW16m)), CWFrameIdx);
11971 // Load the old value of the high byte of the control word...
11973 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
11974 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
11977 // Set the high part to be round to zero...
11978 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
11981 // Reload the modified control word now...
11982 addFrameReference(BuildMI(*BB, MI, DL,
11983 TII->get(X86::FLDCW16m)), CWFrameIdx);
11985 // Restore the memory image of control word to original value
11986 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
11989 // Get the X86 opcode to use.
11991 switch (MI->getOpcode()) {
11992 default: llvm_unreachable("illegal opcode!");
11993 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
11994 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
11995 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
11996 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
11997 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
11998 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
11999 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12000 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12001 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12005 MachineOperand &Op = MI->getOperand(0);
12007 AM.BaseType = X86AddressMode::RegBase;
12008 AM.Base.Reg = Op.getReg();
12010 AM.BaseType = X86AddressMode::FrameIndexBase;
12011 AM.Base.FrameIndex = Op.getIndex();
12013 Op = MI->getOperand(1);
12015 AM.Scale = Op.getImm();
12016 Op = MI->getOperand(2);
12018 AM.IndexReg = Op.getImm();
12019 Op = MI->getOperand(3);
12020 if (Op.isGlobal()) {
12021 AM.GV = Op.getGlobal();
12023 AM.Disp = Op.getImm();
12025 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12026 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12028 // Reload the original control word now.
12029 addFrameReference(BuildMI(*BB, MI, DL,
12030 TII->get(X86::FLDCW16m)), CWFrameIdx);
12032 MI->eraseFromParent(); // The pseudo instruction is gone now.
12035 // String/text processing lowering.
12036 case X86::PCMPISTRM128REG:
12037 case X86::VPCMPISTRM128REG:
12038 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12039 case X86::PCMPISTRM128MEM:
12040 case X86::VPCMPISTRM128MEM:
12041 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12042 case X86::PCMPESTRM128REG:
12043 case X86::VPCMPESTRM128REG:
12044 return EmitPCMP(MI, BB, 5, false /* in mem */);
12045 case X86::PCMPESTRM128MEM:
12046 case X86::VPCMPESTRM128MEM:
12047 return EmitPCMP(MI, BB, 5, true /* in mem */);
12049 // Thread synchronization.
12051 return EmitMonitor(MI, BB);
12053 return EmitMwait(MI, BB);
12055 // Atomic Lowering.
12056 case X86::ATOMAND32:
12057 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12058 X86::AND32ri, X86::MOV32rm,
12060 X86::NOT32r, X86::EAX,
12061 X86::GR32RegisterClass);
12062 case X86::ATOMOR32:
12063 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12064 X86::OR32ri, X86::MOV32rm,
12066 X86::NOT32r, X86::EAX,
12067 X86::GR32RegisterClass);
12068 case X86::ATOMXOR32:
12069 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12070 X86::XOR32ri, X86::MOV32rm,
12072 X86::NOT32r, X86::EAX,
12073 X86::GR32RegisterClass);
12074 case X86::ATOMNAND32:
12075 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12076 X86::AND32ri, X86::MOV32rm,
12078 X86::NOT32r, X86::EAX,
12079 X86::GR32RegisterClass, true);
12080 case X86::ATOMMIN32:
12081 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12082 case X86::ATOMMAX32:
12083 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12084 case X86::ATOMUMIN32:
12085 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12086 case X86::ATOMUMAX32:
12087 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12089 case X86::ATOMAND16:
12090 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12091 X86::AND16ri, X86::MOV16rm,
12093 X86::NOT16r, X86::AX,
12094 X86::GR16RegisterClass);
12095 case X86::ATOMOR16:
12096 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12097 X86::OR16ri, X86::MOV16rm,
12099 X86::NOT16r, X86::AX,
12100 X86::GR16RegisterClass);
12101 case X86::ATOMXOR16:
12102 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12103 X86::XOR16ri, X86::MOV16rm,
12105 X86::NOT16r, X86::AX,
12106 X86::GR16RegisterClass);
12107 case X86::ATOMNAND16:
12108 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12109 X86::AND16ri, X86::MOV16rm,
12111 X86::NOT16r, X86::AX,
12112 X86::GR16RegisterClass, true);
12113 case X86::ATOMMIN16:
12114 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12115 case X86::ATOMMAX16:
12116 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12117 case X86::ATOMUMIN16:
12118 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12119 case X86::ATOMUMAX16:
12120 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12122 case X86::ATOMAND8:
12123 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12124 X86::AND8ri, X86::MOV8rm,
12126 X86::NOT8r, X86::AL,
12127 X86::GR8RegisterClass);
12129 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12130 X86::OR8ri, X86::MOV8rm,
12132 X86::NOT8r, X86::AL,
12133 X86::GR8RegisterClass);
12134 case X86::ATOMXOR8:
12135 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12136 X86::XOR8ri, X86::MOV8rm,
12138 X86::NOT8r, X86::AL,
12139 X86::GR8RegisterClass);
12140 case X86::ATOMNAND8:
12141 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12142 X86::AND8ri, X86::MOV8rm,
12144 X86::NOT8r, X86::AL,
12145 X86::GR8RegisterClass, true);
12146 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12147 // This group is for 64-bit host.
12148 case X86::ATOMAND64:
12149 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12150 X86::AND64ri32, X86::MOV64rm,
12152 X86::NOT64r, X86::RAX,
12153 X86::GR64RegisterClass);
12154 case X86::ATOMOR64:
12155 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12156 X86::OR64ri32, X86::MOV64rm,
12158 X86::NOT64r, X86::RAX,
12159 X86::GR64RegisterClass);
12160 case X86::ATOMXOR64:
12161 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12162 X86::XOR64ri32, X86::MOV64rm,
12164 X86::NOT64r, X86::RAX,
12165 X86::GR64RegisterClass);
12166 case X86::ATOMNAND64:
12167 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12168 X86::AND64ri32, X86::MOV64rm,
12170 X86::NOT64r, X86::RAX,
12171 X86::GR64RegisterClass, true);
12172 case X86::ATOMMIN64:
12173 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12174 case X86::ATOMMAX64:
12175 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12176 case X86::ATOMUMIN64:
12177 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12178 case X86::ATOMUMAX64:
12179 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12181 // This group does 64-bit operations on a 32-bit host.
12182 case X86::ATOMAND6432:
12183 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12184 X86::AND32rr, X86::AND32rr,
12185 X86::AND32ri, X86::AND32ri,
12187 case X86::ATOMOR6432:
12188 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12189 X86::OR32rr, X86::OR32rr,
12190 X86::OR32ri, X86::OR32ri,
12192 case X86::ATOMXOR6432:
12193 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12194 X86::XOR32rr, X86::XOR32rr,
12195 X86::XOR32ri, X86::XOR32ri,
12197 case X86::ATOMNAND6432:
12198 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12199 X86::AND32rr, X86::AND32rr,
12200 X86::AND32ri, X86::AND32ri,
12202 case X86::ATOMADD6432:
12203 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12204 X86::ADD32rr, X86::ADC32rr,
12205 X86::ADD32ri, X86::ADC32ri,
12207 case X86::ATOMSUB6432:
12208 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12209 X86::SUB32rr, X86::SBB32rr,
12210 X86::SUB32ri, X86::SBB32ri,
12212 case X86::ATOMSWAP6432:
12213 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12214 X86::MOV32rr, X86::MOV32rr,
12215 X86::MOV32ri, X86::MOV32ri,
12217 case X86::VASTART_SAVE_XMM_REGS:
12218 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12220 case X86::VAARG_64:
12221 return EmitVAARG64WithCustomInserter(MI, BB);
12225 //===----------------------------------------------------------------------===//
12226 // X86 Optimization Hooks
12227 //===----------------------------------------------------------------------===//
12229 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12233 const SelectionDAG &DAG,
12234 unsigned Depth) const {
12235 unsigned Opc = Op.getOpcode();
12236 assert((Opc >= ISD::BUILTIN_OP_END ||
12237 Opc == ISD::INTRINSIC_WO_CHAIN ||
12238 Opc == ISD::INTRINSIC_W_CHAIN ||
12239 Opc == ISD::INTRINSIC_VOID) &&
12240 "Should use MaskedValueIsZero if you don't know whether Op"
12241 " is a target node!");
12243 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12257 // These nodes' second result is a boolean.
12258 if (Op.getResNo() == 0)
12261 case X86ISD::SETCC:
12262 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12263 Mask.getBitWidth() - 1);
12268 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12269 unsigned Depth) const {
12270 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12271 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12272 return Op.getValueType().getScalarType().getSizeInBits();
12278 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12279 /// node is a GlobalAddress + offset.
12280 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12281 const GlobalValue* &GA,
12282 int64_t &Offset) const {
12283 if (N->getOpcode() == X86ISD::Wrapper) {
12284 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12285 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12286 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12290 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12293 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12294 /// same as extracting the high 128-bit part of 256-bit vector and then
12295 /// inserting the result into the low part of a new 256-bit vector
12296 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12297 EVT VT = SVOp->getValueType(0);
12298 int NumElems = VT.getVectorNumElements();
12300 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12301 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12302 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12303 SVOp->getMaskElt(j) >= 0)
12309 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12310 /// same as extracting the low 128-bit part of 256-bit vector and then
12311 /// inserting the result into the high part of a new 256-bit vector
12312 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12313 EVT VT = SVOp->getValueType(0);
12314 int NumElems = VT.getVectorNumElements();
12316 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12317 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12318 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12319 SVOp->getMaskElt(j) >= 0)
12325 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12326 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12327 TargetLowering::DAGCombinerInfo &DCI) {
12328 DebugLoc dl = N->getDebugLoc();
12329 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12330 SDValue V1 = SVOp->getOperand(0);
12331 SDValue V2 = SVOp->getOperand(1);
12332 EVT VT = SVOp->getValueType(0);
12333 int NumElems = VT.getVectorNumElements();
12335 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12336 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12340 // V UNDEF BUILD_VECTOR UNDEF
12342 // CONCAT_VECTOR CONCAT_VECTOR
12345 // RESULT: V + zero extended
12347 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12348 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12349 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12352 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12355 // To match the shuffle mask, the first half of the mask should
12356 // be exactly the first vector, and all the rest a splat with the
12357 // first element of the second one.
12358 for (int i = 0; i < NumElems/2; ++i)
12359 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12360 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12363 // Emit a zeroed vector and insert the desired subvector on its
12365 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl);
12366 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12367 DAG.getConstant(0, MVT::i32), DAG, dl);
12368 return DCI.CombineTo(N, InsV);
12371 //===--------------------------------------------------------------------===//
12372 // Combine some shuffles into subvector extracts and inserts:
12375 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12376 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12377 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12379 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12380 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12381 return DCI.CombineTo(N, InsV);
12384 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12385 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12386 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12387 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12388 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12389 return DCI.CombineTo(N, InsV);
12395 /// PerformShuffleCombine - Performs several different shuffle combines.
12396 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12397 TargetLowering::DAGCombinerInfo &DCI,
12398 const X86Subtarget *Subtarget) {
12399 DebugLoc dl = N->getDebugLoc();
12400 EVT VT = N->getValueType(0);
12402 // Don't create instructions with illegal types after legalize types has run.
12403 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12404 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12407 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12408 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12409 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12410 return PerformShuffleCombine256(N, DAG, DCI);
12412 // Only handle 128 wide vector from here on.
12413 if (VT.getSizeInBits() != 128)
12416 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12417 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12418 // consecutive, non-overlapping, and in the right order.
12419 SmallVector<SDValue, 16> Elts;
12420 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12421 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12423 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12426 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12427 /// generation and convert it from being a bunch of shuffles and extracts
12428 /// to a simple store and scalar loads to extract the elements.
12429 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12430 const TargetLowering &TLI) {
12431 SDValue InputVector = N->getOperand(0);
12433 // Only operate on vectors of 4 elements, where the alternative shuffling
12434 // gets to be more expensive.
12435 if (InputVector.getValueType() != MVT::v4i32)
12438 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12439 // single use which is a sign-extend or zero-extend, and all elements are
12441 SmallVector<SDNode *, 4> Uses;
12442 unsigned ExtractedElements = 0;
12443 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12444 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12445 if (UI.getUse().getResNo() != InputVector.getResNo())
12448 SDNode *Extract = *UI;
12449 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12452 if (Extract->getValueType(0) != MVT::i32)
12454 if (!Extract->hasOneUse())
12456 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12457 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12459 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12462 // Record which element was extracted.
12463 ExtractedElements |=
12464 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12466 Uses.push_back(Extract);
12469 // If not all the elements were used, this may not be worthwhile.
12470 if (ExtractedElements != 15)
12473 // Ok, we've now decided to do the transformation.
12474 DebugLoc dl = InputVector.getDebugLoc();
12476 // Store the value to a temporary stack slot.
12477 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12478 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12479 MachinePointerInfo(), false, false, 0);
12481 // Replace each use (extract) with a load of the appropriate element.
12482 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12483 UE = Uses.end(); UI != UE; ++UI) {
12484 SDNode *Extract = *UI;
12486 // cOMpute the element's address.
12487 SDValue Idx = Extract->getOperand(1);
12489 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12490 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12491 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12493 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12494 StackPtr, OffsetVal);
12496 // Load the scalar.
12497 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12498 ScalarAddr, MachinePointerInfo(),
12501 // Replace the exact with the load.
12502 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12505 // The replacement was made in place; don't return anything.
12509 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
12510 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12511 const X86Subtarget *Subtarget) {
12512 DebugLoc DL = N->getDebugLoc();
12513 SDValue Cond = N->getOperand(0);
12514 // Get the LHS/RHS of the select.
12515 SDValue LHS = N->getOperand(1);
12516 SDValue RHS = N->getOperand(2);
12518 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12519 // instructions match the semantics of the common C idiom x<y?x:y but not
12520 // x<=y?x:y, because of how they handle negative zero (which can be
12521 // ignored in unsafe-math mode).
12522 if (Subtarget->hasSSE2() &&
12523 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
12524 Cond.getOpcode() == ISD::SETCC) {
12525 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12527 unsigned Opcode = 0;
12528 // Check for x CC y ? x : y.
12529 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12530 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12534 // Converting this to a min would handle NaNs incorrectly, and swapping
12535 // the operands would cause it to handle comparisons between positive
12536 // and negative zero incorrectly.
12537 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12538 if (!UnsafeFPMath &&
12539 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12541 std::swap(LHS, RHS);
12543 Opcode = X86ISD::FMIN;
12546 // Converting this to a min would handle comparisons between positive
12547 // and negative zero incorrectly.
12548 if (!UnsafeFPMath &&
12549 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12551 Opcode = X86ISD::FMIN;
12554 // Converting this to a min would handle both negative zeros and NaNs
12555 // incorrectly, but we can swap the operands to fix both.
12556 std::swap(LHS, RHS);
12560 Opcode = X86ISD::FMIN;
12564 // Converting this to a max would handle comparisons between positive
12565 // and negative zero incorrectly.
12566 if (!UnsafeFPMath &&
12567 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12569 Opcode = X86ISD::FMAX;
12572 // Converting this to a max would handle NaNs incorrectly, and swapping
12573 // the operands would cause it to handle comparisons between positive
12574 // and negative zero incorrectly.
12575 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12576 if (!UnsafeFPMath &&
12577 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12579 std::swap(LHS, RHS);
12581 Opcode = X86ISD::FMAX;
12584 // Converting this to a max would handle both negative zeros and NaNs
12585 // incorrectly, but we can swap the operands to fix both.
12586 std::swap(LHS, RHS);
12590 Opcode = X86ISD::FMAX;
12593 // Check for x CC y ? y : x -- a min/max with reversed arms.
12594 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12595 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12599 // Converting this to a min would handle comparisons between positive
12600 // and negative zero incorrectly, and swapping the operands would
12601 // cause it to handle NaNs incorrectly.
12602 if (!UnsafeFPMath &&
12603 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12604 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12606 std::swap(LHS, RHS);
12608 Opcode = X86ISD::FMIN;
12611 // Converting this to a min would handle NaNs incorrectly.
12612 if (!UnsafeFPMath &&
12613 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12615 Opcode = X86ISD::FMIN;
12618 // Converting this to a min would handle both negative zeros and NaNs
12619 // incorrectly, but we can swap the operands to fix both.
12620 std::swap(LHS, RHS);
12624 Opcode = X86ISD::FMIN;
12628 // Converting this to a max would handle NaNs incorrectly.
12629 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12631 Opcode = X86ISD::FMAX;
12634 // Converting this to a max would handle comparisons between positive
12635 // and negative zero incorrectly, and swapping the operands would
12636 // cause it to handle NaNs incorrectly.
12637 if (!UnsafeFPMath &&
12638 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12639 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12641 std::swap(LHS, RHS);
12643 Opcode = X86ISD::FMAX;
12646 // Converting this to a max would handle both negative zeros and NaNs
12647 // incorrectly, but we can swap the operands to fix both.
12648 std::swap(LHS, RHS);
12652 Opcode = X86ISD::FMAX;
12658 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
12661 // If this is a select between two integer constants, try to do some
12663 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
12664 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
12665 // Don't do this for crazy integer types.
12666 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
12667 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
12668 // so that TrueC (the true value) is larger than FalseC.
12669 bool NeedsCondInvert = false;
12671 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
12672 // Efficiently invertible.
12673 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
12674 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
12675 isa<ConstantSDNode>(Cond.getOperand(1))))) {
12676 NeedsCondInvert = true;
12677 std::swap(TrueC, FalseC);
12680 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
12681 if (FalseC->getAPIntValue() == 0 &&
12682 TrueC->getAPIntValue().isPowerOf2()) {
12683 if (NeedsCondInvert) // Invert the condition if needed.
12684 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12685 DAG.getConstant(1, Cond.getValueType()));
12687 // Zero extend the condition if needed.
12688 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
12690 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12691 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
12692 DAG.getConstant(ShAmt, MVT::i8));
12695 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
12696 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12697 if (NeedsCondInvert) // Invert the condition if needed.
12698 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12699 DAG.getConstant(1, Cond.getValueType()));
12701 // Zero extend the condition if needed.
12702 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12703 FalseC->getValueType(0), Cond);
12704 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12705 SDValue(FalseC, 0));
12708 // Optimize cases that will turn into an LEA instruction. This requires
12709 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12710 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12711 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12712 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12714 bool isFastMultiplier = false;
12716 switch ((unsigned char)Diff) {
12718 case 1: // result = add base, cond
12719 case 2: // result = lea base( , cond*2)
12720 case 3: // result = lea base(cond, cond*2)
12721 case 4: // result = lea base( , cond*4)
12722 case 5: // result = lea base(cond, cond*4)
12723 case 8: // result = lea base( , cond*8)
12724 case 9: // result = lea base(cond, cond*8)
12725 isFastMultiplier = true;
12730 if (isFastMultiplier) {
12731 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12732 if (NeedsCondInvert) // Invert the condition if needed.
12733 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12734 DAG.getConstant(1, Cond.getValueType()));
12736 // Zero extend the condition if needed.
12737 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12739 // Scale the condition by the difference.
12741 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12742 DAG.getConstant(Diff, Cond.getValueType()));
12744 // Add the base if non-zero.
12745 if (FalseC->getAPIntValue() != 0)
12746 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12747 SDValue(FalseC, 0));
12757 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
12758 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
12759 TargetLowering::DAGCombinerInfo &DCI) {
12760 DebugLoc DL = N->getDebugLoc();
12762 // If the flag operand isn't dead, don't touch this CMOV.
12763 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
12766 SDValue FalseOp = N->getOperand(0);
12767 SDValue TrueOp = N->getOperand(1);
12768 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
12769 SDValue Cond = N->getOperand(3);
12770 if (CC == X86::COND_E || CC == X86::COND_NE) {
12771 switch (Cond.getOpcode()) {
12775 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
12776 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
12777 return (CC == X86::COND_E) ? FalseOp : TrueOp;
12781 // If this is a select between two integer constants, try to do some
12782 // optimizations. Note that the operands are ordered the opposite of SELECT
12784 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
12785 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
12786 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
12787 // larger than FalseC (the false value).
12788 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
12789 CC = X86::GetOppositeBranchCondition(CC);
12790 std::swap(TrueC, FalseC);
12793 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
12794 // This is efficient for any integer data type (including i8/i16) and
12796 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
12797 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12798 DAG.getConstant(CC, MVT::i8), Cond);
12800 // Zero extend the condition if needed.
12801 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
12803 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12804 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
12805 DAG.getConstant(ShAmt, MVT::i8));
12806 if (N->getNumValues() == 2) // Dead flag value?
12807 return DCI.CombineTo(N, Cond, SDValue());
12811 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
12812 // for any integer data type, including i8/i16.
12813 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12814 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12815 DAG.getConstant(CC, MVT::i8), Cond);
12817 // Zero extend the condition if needed.
12818 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12819 FalseC->getValueType(0), Cond);
12820 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12821 SDValue(FalseC, 0));
12823 if (N->getNumValues() == 2) // Dead flag value?
12824 return DCI.CombineTo(N, Cond, SDValue());
12828 // Optimize cases that will turn into an LEA instruction. This requires
12829 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12830 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12831 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12832 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12834 bool isFastMultiplier = false;
12836 switch ((unsigned char)Diff) {
12838 case 1: // result = add base, cond
12839 case 2: // result = lea base( , cond*2)
12840 case 3: // result = lea base(cond, cond*2)
12841 case 4: // result = lea base( , cond*4)
12842 case 5: // result = lea base(cond, cond*4)
12843 case 8: // result = lea base( , cond*8)
12844 case 9: // result = lea base(cond, cond*8)
12845 isFastMultiplier = true;
12850 if (isFastMultiplier) {
12851 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12852 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12853 DAG.getConstant(CC, MVT::i8), Cond);
12854 // Zero extend the condition if needed.
12855 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12857 // Scale the condition by the difference.
12859 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12860 DAG.getConstant(Diff, Cond.getValueType()));
12862 // Add the base if non-zero.
12863 if (FalseC->getAPIntValue() != 0)
12864 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12865 SDValue(FalseC, 0));
12866 if (N->getNumValues() == 2) // Dead flag value?
12867 return DCI.CombineTo(N, Cond, SDValue());
12877 /// PerformMulCombine - Optimize a single multiply with constant into two
12878 /// in order to implement it with two cheaper instructions, e.g.
12879 /// LEA + SHL, LEA + LEA.
12880 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
12881 TargetLowering::DAGCombinerInfo &DCI) {
12882 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
12885 EVT VT = N->getValueType(0);
12886 if (VT != MVT::i64)
12889 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
12892 uint64_t MulAmt = C->getZExtValue();
12893 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
12896 uint64_t MulAmt1 = 0;
12897 uint64_t MulAmt2 = 0;
12898 if ((MulAmt % 9) == 0) {
12900 MulAmt2 = MulAmt / 9;
12901 } else if ((MulAmt % 5) == 0) {
12903 MulAmt2 = MulAmt / 5;
12904 } else if ((MulAmt % 3) == 0) {
12906 MulAmt2 = MulAmt / 3;
12909 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
12910 DebugLoc DL = N->getDebugLoc();
12912 if (isPowerOf2_64(MulAmt2) &&
12913 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
12914 // If second multiplifer is pow2, issue it first. We want the multiply by
12915 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
12917 std::swap(MulAmt1, MulAmt2);
12920 if (isPowerOf2_64(MulAmt1))
12921 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
12922 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
12924 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
12925 DAG.getConstant(MulAmt1, VT));
12927 if (isPowerOf2_64(MulAmt2))
12928 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
12929 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
12931 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
12932 DAG.getConstant(MulAmt2, VT));
12934 // Do not add new nodes to DAG combiner worklist.
12935 DCI.CombineTo(N, NewMul, false);
12940 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
12941 SDValue N0 = N->getOperand(0);
12942 SDValue N1 = N->getOperand(1);
12943 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
12944 EVT VT = N0.getValueType();
12946 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
12947 // since the result of setcc_c is all zero's or all ones.
12948 if (N1C && N0.getOpcode() == ISD::AND &&
12949 N0.getOperand(1).getOpcode() == ISD::Constant) {
12950 SDValue N00 = N0.getOperand(0);
12951 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
12952 ((N00.getOpcode() == ISD::ANY_EXTEND ||
12953 N00.getOpcode() == ISD::ZERO_EXTEND) &&
12954 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
12955 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
12956 APInt ShAmt = N1C->getAPIntValue();
12957 Mask = Mask.shl(ShAmt);
12959 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
12960 N00, DAG.getConstant(Mask, VT));
12967 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
12969 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
12970 const X86Subtarget *Subtarget) {
12971 EVT VT = N->getValueType(0);
12972 if (!VT.isVector() && VT.isInteger() &&
12973 N->getOpcode() == ISD::SHL)
12974 return PerformSHLCombine(N, DAG);
12976 // On X86 with SSE2 support, we can transform this to a vector shift if
12977 // all elements are shifted by the same amount. We can't do this in legalize
12978 // because the a constant vector is typically transformed to a constant pool
12979 // so we have no knowledge of the shift amount.
12980 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
12983 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
12986 SDValue ShAmtOp = N->getOperand(1);
12987 EVT EltVT = VT.getVectorElementType();
12988 DebugLoc DL = N->getDebugLoc();
12989 SDValue BaseShAmt = SDValue();
12990 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
12991 unsigned NumElts = VT.getVectorNumElements();
12993 for (; i != NumElts; ++i) {
12994 SDValue Arg = ShAmtOp.getOperand(i);
12995 if (Arg.getOpcode() == ISD::UNDEF) continue;
12999 for (; i != NumElts; ++i) {
13000 SDValue Arg = ShAmtOp.getOperand(i);
13001 if (Arg.getOpcode() == ISD::UNDEF) continue;
13002 if (Arg != BaseShAmt) {
13006 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13007 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13008 SDValue InVec = ShAmtOp.getOperand(0);
13009 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13010 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13012 for (; i != NumElts; ++i) {
13013 SDValue Arg = InVec.getOperand(i);
13014 if (Arg.getOpcode() == ISD::UNDEF) continue;
13018 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13019 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13020 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13021 if (C->getZExtValue() == SplatIdx)
13022 BaseShAmt = InVec.getOperand(1);
13025 if (BaseShAmt.getNode() == 0)
13026 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13027 DAG.getIntPtrConstant(0));
13031 // The shift amount is an i32.
13032 if (EltVT.bitsGT(MVT::i32))
13033 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13034 else if (EltVT.bitsLT(MVT::i32))
13035 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13037 // The shift amount is identical so we can do a vector shift.
13038 SDValue ValOp = N->getOperand(0);
13039 switch (N->getOpcode()) {
13041 llvm_unreachable("Unknown shift opcode!");
13044 if (VT == MVT::v2i64)
13045 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13046 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
13048 if (VT == MVT::v4i32)
13049 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13050 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
13052 if (VT == MVT::v8i16)
13053 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13054 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
13058 if (VT == MVT::v4i32)
13059 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13060 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
13062 if (VT == MVT::v8i16)
13063 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13064 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
13068 if (VT == MVT::v2i64)
13069 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13070 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
13072 if (VT == MVT::v4i32)
13073 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13074 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
13076 if (VT == MVT::v8i16)
13077 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13078 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
13086 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13087 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13088 // and friends. Likewise for OR -> CMPNEQSS.
13089 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13090 TargetLowering::DAGCombinerInfo &DCI,
13091 const X86Subtarget *Subtarget) {
13094 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13095 // we're requiring SSE2 for both.
13096 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13097 SDValue N0 = N->getOperand(0);
13098 SDValue N1 = N->getOperand(1);
13099 SDValue CMP0 = N0->getOperand(1);
13100 SDValue CMP1 = N1->getOperand(1);
13101 DebugLoc DL = N->getDebugLoc();
13103 // The SETCCs should both refer to the same CMP.
13104 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13107 SDValue CMP00 = CMP0->getOperand(0);
13108 SDValue CMP01 = CMP0->getOperand(1);
13109 EVT VT = CMP00.getValueType();
13111 if (VT == MVT::f32 || VT == MVT::f64) {
13112 bool ExpectingFlags = false;
13113 // Check for any users that want flags:
13114 for (SDNode::use_iterator UI = N->use_begin(),
13116 !ExpectingFlags && UI != UE; ++UI)
13117 switch (UI->getOpcode()) {
13122 ExpectingFlags = true;
13124 case ISD::CopyToReg:
13125 case ISD::SIGN_EXTEND:
13126 case ISD::ZERO_EXTEND:
13127 case ISD::ANY_EXTEND:
13131 if (!ExpectingFlags) {
13132 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13133 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13135 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13136 X86::CondCode tmp = cc0;
13141 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13142 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13143 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13144 X86ISD::NodeType NTOperator = is64BitFP ?
13145 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13146 // FIXME: need symbolic constants for these magic numbers.
13147 // See X86ATTInstPrinter.cpp:printSSECC().
13148 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13149 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13150 DAG.getConstant(x86cc, MVT::i8));
13151 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13153 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13154 DAG.getConstant(1, MVT::i32));
13155 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13156 return OneBitOfTruth;
13164 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13165 /// so it can be folded inside ANDNP.
13166 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13167 EVT VT = N->getValueType(0);
13169 // Match direct AllOnes for 128 and 256-bit vectors
13170 if (ISD::isBuildVectorAllOnes(N))
13173 // Look through a bit convert.
13174 if (N->getOpcode() == ISD::BITCAST)
13175 N = N->getOperand(0).getNode();
13177 // Sometimes the operand may come from a insert_subvector building a 256-bit
13179 if (VT.getSizeInBits() == 256 &&
13180 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13181 SDValue V1 = N->getOperand(0);
13182 SDValue V2 = N->getOperand(1);
13184 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13185 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13186 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13187 ISD::isBuildVectorAllOnes(V2.getNode()))
13194 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13195 TargetLowering::DAGCombinerInfo &DCI,
13196 const X86Subtarget *Subtarget) {
13197 if (DCI.isBeforeLegalizeOps())
13200 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13204 // Want to form ANDNP nodes:
13205 // 1) In the hopes of then easily combining them with OR and AND nodes
13206 // to form PBLEND/PSIGN.
13207 // 2) To match ANDN packed intrinsics
13208 EVT VT = N->getValueType(0);
13209 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13212 SDValue N0 = N->getOperand(0);
13213 SDValue N1 = N->getOperand(1);
13214 DebugLoc DL = N->getDebugLoc();
13216 // Check LHS for vnot
13217 if (N0.getOpcode() == ISD::XOR &&
13218 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13219 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13220 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13222 // Check RHS for vnot
13223 if (N1.getOpcode() == ISD::XOR &&
13224 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13225 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13226 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13231 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13232 TargetLowering::DAGCombinerInfo &DCI,
13233 const X86Subtarget *Subtarget) {
13234 if (DCI.isBeforeLegalizeOps())
13237 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13241 EVT VT = N->getValueType(0);
13242 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
13245 SDValue N0 = N->getOperand(0);
13246 SDValue N1 = N->getOperand(1);
13248 // look for psign/blend
13249 if (Subtarget->hasSSSE3()) {
13250 if (VT == MVT::v2i64) {
13251 // Canonicalize pandn to RHS
13252 if (N0.getOpcode() == X86ISD::ANDNP)
13254 // or (and (m, x), (pandn m, y))
13255 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13256 SDValue Mask = N1.getOperand(0);
13257 SDValue X = N1.getOperand(1);
13259 if (N0.getOperand(0) == Mask)
13260 Y = N0.getOperand(1);
13261 if (N0.getOperand(1) == Mask)
13262 Y = N0.getOperand(0);
13264 // Check to see if the mask appeared in both the AND and ANDNP and
13268 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13269 if (Mask.getOpcode() != ISD::BITCAST ||
13270 X.getOpcode() != ISD::BITCAST ||
13271 Y.getOpcode() != ISD::BITCAST)
13274 // Look through mask bitcast.
13275 Mask = Mask.getOperand(0);
13276 EVT MaskVT = Mask.getValueType();
13278 // Validate that the Mask operand is a vector sra node. The sra node
13279 // will be an intrinsic.
13280 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13283 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13284 // there is no psrai.b
13285 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13286 case Intrinsic::x86_sse2_psrai_w:
13287 case Intrinsic::x86_sse2_psrai_d:
13289 default: return SDValue();
13292 // Check that the SRA is all signbits.
13293 SDValue SraC = Mask.getOperand(2);
13294 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13295 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13296 if ((SraAmt + 1) != EltBits)
13299 DebugLoc DL = N->getDebugLoc();
13301 // Now we know we at least have a plendvb with the mask val. See if
13302 // we can form a psignb/w/d.
13303 // psign = x.type == y.type == mask.type && y = sub(0, x);
13304 X = X.getOperand(0);
13305 Y = Y.getOperand(0);
13306 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13307 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13308 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
13311 case 8: Opc = X86ISD::PSIGNB; break;
13312 case 16: Opc = X86ISD::PSIGNW; break;
13313 case 32: Opc = X86ISD::PSIGND; break;
13317 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
13318 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
13321 // PBLENDVB only available on SSE 4.1
13322 if (!Subtarget->hasSSE41())
13325 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
13326 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
13327 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
13328 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
13329 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
13334 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13335 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13337 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13339 if (!N0.hasOneUse() || !N1.hasOneUse())
13342 SDValue ShAmt0 = N0.getOperand(1);
13343 if (ShAmt0.getValueType() != MVT::i8)
13345 SDValue ShAmt1 = N1.getOperand(1);
13346 if (ShAmt1.getValueType() != MVT::i8)
13348 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13349 ShAmt0 = ShAmt0.getOperand(0);
13350 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13351 ShAmt1 = ShAmt1.getOperand(0);
13353 DebugLoc DL = N->getDebugLoc();
13354 unsigned Opc = X86ISD::SHLD;
13355 SDValue Op0 = N0.getOperand(0);
13356 SDValue Op1 = N1.getOperand(0);
13357 if (ShAmt0.getOpcode() == ISD::SUB) {
13358 Opc = X86ISD::SHRD;
13359 std::swap(Op0, Op1);
13360 std::swap(ShAmt0, ShAmt1);
13363 unsigned Bits = VT.getSizeInBits();
13364 if (ShAmt1.getOpcode() == ISD::SUB) {
13365 SDValue Sum = ShAmt1.getOperand(0);
13366 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13367 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13368 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13369 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13370 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13371 return DAG.getNode(Opc, DL, VT,
13373 DAG.getNode(ISD::TRUNCATE, DL,
13376 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13377 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13379 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13380 return DAG.getNode(Opc, DL, VT,
13381 N0.getOperand(0), N1.getOperand(0),
13382 DAG.getNode(ISD::TRUNCATE, DL,
13389 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13390 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13391 const X86Subtarget *Subtarget) {
13392 StoreSDNode *St = cast<StoreSDNode>(N);
13393 EVT VT = St->getValue().getValueType();
13394 EVT StVT = St->getMemoryVT();
13395 DebugLoc dl = St->getDebugLoc();
13396 SDValue StoredVal = St->getOperand(1);
13397 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13399 // If we are saving a concatination of two XMM registers, perform two stores.
13400 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13401 // 128-bit ones. If in the future the cost becomes only one memory access the
13402 // first version would be better.
13403 if (VT.getSizeInBits() == 256 &&
13404 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
13405 StoredVal.getNumOperands() == 2) {
13407 SDValue Value0 = StoredVal.getOperand(0);
13408 SDValue Value1 = StoredVal.getOperand(1);
13410 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
13411 SDValue Ptr0 = St->getBasePtr();
13412 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
13414 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
13415 St->getPointerInfo(), St->isVolatile(),
13416 St->isNonTemporal(), St->getAlignment());
13417 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
13418 St->getPointerInfo(), St->isVolatile(),
13419 St->isNonTemporal(), St->getAlignment());
13420 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
13423 // Optimize trunc store (of multiple scalars) to shuffle and store.
13424 // First, pack all of the elements in one place. Next, store to memory
13425 // in fewer chunks.
13426 if (St->isTruncatingStore() && VT.isVector()) {
13427 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13428 unsigned NumElems = VT.getVectorNumElements();
13429 assert(StVT != VT && "Cannot truncate to the same type");
13430 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
13431 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
13433 // From, To sizes and ElemCount must be pow of two
13434 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
13435 // We are going to use the original vector elt for storing.
13436 // accumulated smaller vector elements must be a multiple of bigger size.
13437 if (0 != (NumElems * ToSz) % FromSz) return SDValue();
13438 unsigned SizeRatio = FromSz / ToSz;
13440 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
13442 // Create a type on which we perform the shuffle
13443 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
13444 StVT.getScalarType(), NumElems*SizeRatio);
13446 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
13448 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
13449 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13450 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
13452 // Can't shuffle using an illegal type
13453 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13455 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
13456 DAG.getUNDEF(WideVec.getValueType()),
13457 ShuffleVec.data());
13458 // At this point all of the data is stored at the bottom of the
13459 // register. We now need to save it to mem.
13461 // Find the largest store unit
13462 MVT StoreType = MVT::i8;
13463 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13464 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13465 MVT Tp = (MVT::SimpleValueType)tp;
13466 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
13470 // Bitcast the original vector into a vector of store-size units
13471 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
13472 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
13473 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
13474 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
13475 SmallVector<SDValue, 8> Chains;
13476 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
13477 TLI.getPointerTy());
13478 SDValue Ptr = St->getBasePtr();
13480 // Perform one or more big stores into memory.
13481 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
13482 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
13483 StoreType, ShuffWide,
13484 DAG.getIntPtrConstant(i));
13485 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
13486 St->getPointerInfo(), St->isVolatile(),
13487 St->isNonTemporal(), St->getAlignment());
13488 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13489 Chains.push_back(Ch);
13492 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
13497 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
13498 // the FP state in cases where an emms may be missing.
13499 // A preferable solution to the general problem is to figure out the right
13500 // places to insert EMMS. This qualifies as a quick hack.
13502 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
13503 if (VT.getSizeInBits() != 64)
13506 const Function *F = DAG.getMachineFunction().getFunction();
13507 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
13508 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
13509 && Subtarget->hasSSE2();
13510 if ((VT.isVector() ||
13511 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
13512 isa<LoadSDNode>(St->getValue()) &&
13513 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
13514 St->getChain().hasOneUse() && !St->isVolatile()) {
13515 SDNode* LdVal = St->getValue().getNode();
13516 LoadSDNode *Ld = 0;
13517 int TokenFactorIndex = -1;
13518 SmallVector<SDValue, 8> Ops;
13519 SDNode* ChainVal = St->getChain().getNode();
13520 // Must be a store of a load. We currently handle two cases: the load
13521 // is a direct child, and it's under an intervening TokenFactor. It is
13522 // possible to dig deeper under nested TokenFactors.
13523 if (ChainVal == LdVal)
13524 Ld = cast<LoadSDNode>(St->getChain());
13525 else if (St->getValue().hasOneUse() &&
13526 ChainVal->getOpcode() == ISD::TokenFactor) {
13527 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
13528 if (ChainVal->getOperand(i).getNode() == LdVal) {
13529 TokenFactorIndex = i;
13530 Ld = cast<LoadSDNode>(St->getValue());
13532 Ops.push_back(ChainVal->getOperand(i));
13536 if (!Ld || !ISD::isNormalLoad(Ld))
13539 // If this is not the MMX case, i.e. we are just turning i64 load/store
13540 // into f64 load/store, avoid the transformation if there are multiple
13541 // uses of the loaded value.
13542 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
13545 DebugLoc LdDL = Ld->getDebugLoc();
13546 DebugLoc StDL = N->getDebugLoc();
13547 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
13548 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
13550 if (Subtarget->is64Bit() || F64IsLegal) {
13551 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
13552 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
13553 Ld->getPointerInfo(), Ld->isVolatile(),
13554 Ld->isNonTemporal(), Ld->getAlignment());
13555 SDValue NewChain = NewLd.getValue(1);
13556 if (TokenFactorIndex != -1) {
13557 Ops.push_back(NewChain);
13558 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13561 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
13562 St->getPointerInfo(),
13563 St->isVolatile(), St->isNonTemporal(),
13564 St->getAlignment());
13567 // Otherwise, lower to two pairs of 32-bit loads / stores.
13568 SDValue LoAddr = Ld->getBasePtr();
13569 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
13570 DAG.getConstant(4, MVT::i32));
13572 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
13573 Ld->getPointerInfo(),
13574 Ld->isVolatile(), Ld->isNonTemporal(),
13575 Ld->getAlignment());
13576 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
13577 Ld->getPointerInfo().getWithOffset(4),
13578 Ld->isVolatile(), Ld->isNonTemporal(),
13579 MinAlign(Ld->getAlignment(), 4));
13581 SDValue NewChain = LoLd.getValue(1);
13582 if (TokenFactorIndex != -1) {
13583 Ops.push_back(LoLd);
13584 Ops.push_back(HiLd);
13585 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13589 LoAddr = St->getBasePtr();
13590 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
13591 DAG.getConstant(4, MVT::i32));
13593 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
13594 St->getPointerInfo(),
13595 St->isVolatile(), St->isNonTemporal(),
13596 St->getAlignment());
13597 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
13598 St->getPointerInfo().getWithOffset(4),
13600 St->isNonTemporal(),
13601 MinAlign(St->getAlignment(), 4));
13602 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
13607 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
13608 /// X86ISD::FXOR nodes.
13609 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
13610 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
13611 // F[X]OR(0.0, x) -> x
13612 // F[X]OR(x, 0.0) -> x
13613 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13614 if (C->getValueAPF().isPosZero())
13615 return N->getOperand(1);
13616 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13617 if (C->getValueAPF().isPosZero())
13618 return N->getOperand(0);
13622 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
13623 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
13624 // FAND(0.0, x) -> 0.0
13625 // FAND(x, 0.0) -> 0.0
13626 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13627 if (C->getValueAPF().isPosZero())
13628 return N->getOperand(0);
13629 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13630 if (C->getValueAPF().isPosZero())
13631 return N->getOperand(1);
13635 static SDValue PerformBTCombine(SDNode *N,
13637 TargetLowering::DAGCombinerInfo &DCI) {
13638 // BT ignores high bits in the bit index operand.
13639 SDValue Op1 = N->getOperand(1);
13640 if (Op1.hasOneUse()) {
13641 unsigned BitWidth = Op1.getValueSizeInBits();
13642 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
13643 APInt KnownZero, KnownOne;
13644 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
13645 !DCI.isBeforeLegalizeOps());
13646 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13647 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
13648 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
13649 DCI.CommitTargetLoweringOpt(TLO);
13654 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
13655 SDValue Op = N->getOperand(0);
13656 if (Op.getOpcode() == ISD::BITCAST)
13657 Op = Op.getOperand(0);
13658 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
13659 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
13660 VT.getVectorElementType().getSizeInBits() ==
13661 OpVT.getVectorElementType().getSizeInBits()) {
13662 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
13667 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
13668 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
13669 // (and (i32 x86isd::setcc_carry), 1)
13670 // This eliminates the zext. This transformation is necessary because
13671 // ISD::SETCC is always legalized to i8.
13672 DebugLoc dl = N->getDebugLoc();
13673 SDValue N0 = N->getOperand(0);
13674 EVT VT = N->getValueType(0);
13675 if (N0.getOpcode() == ISD::AND &&
13677 N0.getOperand(0).hasOneUse()) {
13678 SDValue N00 = N0.getOperand(0);
13679 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
13681 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
13682 if (!C || C->getZExtValue() != 1)
13684 return DAG.getNode(ISD::AND, dl, VT,
13685 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
13686 N00.getOperand(0), N00.getOperand(1)),
13687 DAG.getConstant(1, VT));
13693 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
13694 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
13695 unsigned X86CC = N->getConstantOperandVal(0);
13696 SDValue EFLAG = N->getOperand(1);
13697 DebugLoc DL = N->getDebugLoc();
13699 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
13700 // a zext and produces an all-ones bit which is more useful than 0/1 in some
13702 if (X86CC == X86::COND_B)
13703 return DAG.getNode(ISD::AND, DL, MVT::i8,
13704 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
13705 DAG.getConstant(X86CC, MVT::i8), EFLAG),
13706 DAG.getConstant(1, MVT::i8));
13711 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
13712 const X86TargetLowering *XTLI) {
13713 SDValue Op0 = N->getOperand(0);
13714 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
13715 // a 32-bit target where SSE doesn't support i64->FP operations.
13716 if (Op0.getOpcode() == ISD::LOAD) {
13717 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
13718 EVT VT = Ld->getValueType(0);
13719 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
13720 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
13721 !XTLI->getSubtarget()->is64Bit() &&
13722 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13723 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
13724 Ld->getChain(), Op0, DAG);
13725 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
13732 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
13733 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
13734 X86TargetLowering::DAGCombinerInfo &DCI) {
13735 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
13736 // the result is either zero or one (depending on the input carry bit).
13737 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
13738 if (X86::isZeroNode(N->getOperand(0)) &&
13739 X86::isZeroNode(N->getOperand(1)) &&
13740 // We don't have a good way to replace an EFLAGS use, so only do this when
13742 SDValue(N, 1).use_empty()) {
13743 DebugLoc DL = N->getDebugLoc();
13744 EVT VT = N->getValueType(0);
13745 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
13746 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
13747 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
13748 DAG.getConstant(X86::COND_B,MVT::i8),
13750 DAG.getConstant(1, VT));
13751 return DCI.CombineTo(N, Res1, CarryOut);
13757 // fold (add Y, (sete X, 0)) -> adc 0, Y
13758 // (add Y, (setne X, 0)) -> sbb -1, Y
13759 // (sub (sete X, 0), Y) -> sbb 0, Y
13760 // (sub (setne X, 0), Y) -> adc -1, Y
13761 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
13762 DebugLoc DL = N->getDebugLoc();
13764 // Look through ZExts.
13765 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
13766 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
13769 SDValue SetCC = Ext.getOperand(0);
13770 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
13773 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
13774 if (CC != X86::COND_E && CC != X86::COND_NE)
13777 SDValue Cmp = SetCC.getOperand(1);
13778 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
13779 !X86::isZeroNode(Cmp.getOperand(1)) ||
13780 !Cmp.getOperand(0).getValueType().isInteger())
13783 SDValue CmpOp0 = Cmp.getOperand(0);
13784 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
13785 DAG.getConstant(1, CmpOp0.getValueType()));
13787 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
13788 if (CC == X86::COND_NE)
13789 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
13790 DL, OtherVal.getValueType(), OtherVal,
13791 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
13792 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
13793 DL, OtherVal.getValueType(), OtherVal,
13794 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
13797 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
13798 SDValue Op0 = N->getOperand(0);
13799 SDValue Op1 = N->getOperand(1);
13801 // X86 can't encode an immediate LHS of a sub. See if we can push the
13802 // negation into a preceding instruction.
13803 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
13804 // If the RHS of the sub is a XOR with one use and a constant, invert the
13805 // immediate. Then add one to the LHS of the sub so we can turn
13806 // X-Y -> X+~Y+1, saving one register.
13807 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
13808 isa<ConstantSDNode>(Op1.getOperand(1))) {
13809 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
13810 EVT VT = Op0.getValueType();
13811 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
13813 DAG.getConstant(~XorC, VT));
13814 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
13815 DAG.getConstant(C->getAPIntValue()+1, VT));
13819 return OptimizeConditionalInDecrement(N, DAG);
13822 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
13823 DAGCombinerInfo &DCI) const {
13824 SelectionDAG &DAG = DCI.DAG;
13825 switch (N->getOpcode()) {
13827 case ISD::EXTRACT_VECTOR_ELT:
13828 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
13829 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
13830 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
13831 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
13832 case ISD::SUB: return PerformSubCombine(N, DAG);
13833 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
13834 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
13837 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
13838 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
13839 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
13840 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
13841 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
13843 case X86ISD::FOR: return PerformFORCombine(N, DAG);
13844 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
13845 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
13846 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
13847 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
13848 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
13849 case X86ISD::SHUFPS: // Handle all target specific shuffles
13850 case X86ISD::SHUFPD:
13851 case X86ISD::PALIGN:
13852 case X86ISD::PUNPCKHBW:
13853 case X86ISD::PUNPCKHWD:
13854 case X86ISD::PUNPCKHDQ:
13855 case X86ISD::PUNPCKHQDQ:
13856 case X86ISD::UNPCKHPS:
13857 case X86ISD::UNPCKHPD:
13858 case X86ISD::VUNPCKHPSY:
13859 case X86ISD::VUNPCKHPDY:
13860 case X86ISD::PUNPCKLBW:
13861 case X86ISD::PUNPCKLWD:
13862 case X86ISD::PUNPCKLDQ:
13863 case X86ISD::PUNPCKLQDQ:
13864 case X86ISD::UNPCKLPS:
13865 case X86ISD::UNPCKLPD:
13866 case X86ISD::VUNPCKLPSY:
13867 case X86ISD::VUNPCKLPDY:
13868 case X86ISD::MOVHLPS:
13869 case X86ISD::MOVLHPS:
13870 case X86ISD::PSHUFD:
13871 case X86ISD::PSHUFHW:
13872 case X86ISD::PSHUFLW:
13873 case X86ISD::MOVSS:
13874 case X86ISD::MOVSD:
13875 case X86ISD::VPERMILPS:
13876 case X86ISD::VPERMILPSY:
13877 case X86ISD::VPERMILPD:
13878 case X86ISD::VPERMILPDY:
13879 case X86ISD::VPERM2F128:
13880 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
13886 /// isTypeDesirableForOp - Return true if the target has native support for
13887 /// the specified value type and it is 'desirable' to use the type for the
13888 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
13889 /// instruction encodings are longer and some i16 instructions are slow.
13890 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
13891 if (!isTypeLegal(VT))
13893 if (VT != MVT::i16)
13900 case ISD::SIGN_EXTEND:
13901 case ISD::ZERO_EXTEND:
13902 case ISD::ANY_EXTEND:
13915 /// IsDesirableToPromoteOp - This method query the target whether it is
13916 /// beneficial for dag combiner to promote the specified node. If true, it
13917 /// should return the desired promotion type by reference.
13918 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
13919 EVT VT = Op.getValueType();
13920 if (VT != MVT::i16)
13923 bool Promote = false;
13924 bool Commute = false;
13925 switch (Op.getOpcode()) {
13928 LoadSDNode *LD = cast<LoadSDNode>(Op);
13929 // If the non-extending load has a single use and it's not live out, then it
13930 // might be folded.
13931 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
13932 Op.hasOneUse()*/) {
13933 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13934 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
13935 // The only case where we'd want to promote LOAD (rather then it being
13936 // promoted as an operand is when it's only use is liveout.
13937 if (UI->getOpcode() != ISD::CopyToReg)
13944 case ISD::SIGN_EXTEND:
13945 case ISD::ZERO_EXTEND:
13946 case ISD::ANY_EXTEND:
13951 SDValue N0 = Op.getOperand(0);
13952 // Look out for (store (shl (load), x)).
13953 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
13966 SDValue N0 = Op.getOperand(0);
13967 SDValue N1 = Op.getOperand(1);
13968 if (!Commute && MayFoldLoad(N1))
13970 // Avoid disabling potential load folding opportunities.
13971 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
13973 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
13983 //===----------------------------------------------------------------------===//
13984 // X86 Inline Assembly Support
13985 //===----------------------------------------------------------------------===//
13987 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
13988 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
13990 std::string AsmStr = IA->getAsmString();
13992 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
13993 SmallVector<StringRef, 4> AsmPieces;
13994 SplitString(AsmStr, AsmPieces, ";\n");
13996 switch (AsmPieces.size()) {
13997 default: return false;
13999 AsmStr = AsmPieces[0];
14001 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
14003 // FIXME: this should verify that we are targeting a 486 or better. If not,
14004 // we will turn this bswap into something that will be lowered to logical ops
14005 // instead of emitting the bswap asm. For now, we don't support 486 or lower
14006 // so don't worry about this.
14008 if (AsmPieces.size() == 2 &&
14009 (AsmPieces[0] == "bswap" ||
14010 AsmPieces[0] == "bswapq" ||
14011 AsmPieces[0] == "bswapl") &&
14012 (AsmPieces[1] == "$0" ||
14013 AsmPieces[1] == "${0:q}")) {
14014 // No need to check constraints, nothing other than the equivalent of
14015 // "=r,0" would be valid here.
14016 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14017 if (!Ty || Ty->getBitWidth() % 16 != 0)
14019 return IntrinsicLowering::LowerToByteSwap(CI);
14021 // rorw $$8, ${0:w} --> llvm.bswap.i16
14022 if (CI->getType()->isIntegerTy(16) &&
14023 AsmPieces.size() == 3 &&
14024 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
14025 AsmPieces[1] == "$$8," &&
14026 AsmPieces[2] == "${0:w}" &&
14027 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
14029 const std::string &ConstraintsStr = IA->getConstraintString();
14030 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14031 std::sort(AsmPieces.begin(), AsmPieces.end());
14032 if (AsmPieces.size() == 4 &&
14033 AsmPieces[0] == "~{cc}" &&
14034 AsmPieces[1] == "~{dirflag}" &&
14035 AsmPieces[2] == "~{flags}" &&
14036 AsmPieces[3] == "~{fpsr}") {
14037 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14038 if (!Ty || Ty->getBitWidth() % 16 != 0)
14040 return IntrinsicLowering::LowerToByteSwap(CI);
14045 if (CI->getType()->isIntegerTy(32) &&
14046 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
14047 SmallVector<StringRef, 4> Words;
14048 SplitString(AsmPieces[0], Words, " \t,");
14049 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
14050 Words[2] == "${0:w}") {
14052 SplitString(AsmPieces[1], Words, " \t,");
14053 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
14054 Words[2] == "$0") {
14056 SplitString(AsmPieces[2], Words, " \t,");
14057 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
14058 Words[2] == "${0:w}") {
14060 const std::string &ConstraintsStr = IA->getConstraintString();
14061 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14062 std::sort(AsmPieces.begin(), AsmPieces.end());
14063 if (AsmPieces.size() == 4 &&
14064 AsmPieces[0] == "~{cc}" &&
14065 AsmPieces[1] == "~{dirflag}" &&
14066 AsmPieces[2] == "~{flags}" &&
14067 AsmPieces[3] == "~{fpsr}") {
14068 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14069 if (!Ty || Ty->getBitWidth() % 16 != 0)
14071 return IntrinsicLowering::LowerToByteSwap(CI);
14078 if (CI->getType()->isIntegerTy(64)) {
14079 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
14080 if (Constraints.size() >= 2 &&
14081 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
14082 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
14083 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14084 SmallVector<StringRef, 4> Words;
14085 SplitString(AsmPieces[0], Words, " \t");
14086 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
14088 SplitString(AsmPieces[1], Words, " \t");
14089 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
14091 SplitString(AsmPieces[2], Words, " \t,");
14092 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
14093 Words[2] == "%edx") {
14094 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14095 if (!Ty || Ty->getBitWidth() % 16 != 0)
14097 return IntrinsicLowering::LowerToByteSwap(CI);
14110 /// getConstraintType - Given a constraint letter, return the type of
14111 /// constraint it is for this target.
14112 X86TargetLowering::ConstraintType
14113 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
14114 if (Constraint.size() == 1) {
14115 switch (Constraint[0]) {
14126 return C_RegisterClass;
14150 return TargetLowering::getConstraintType(Constraint);
14153 /// Examine constraint type and operand type and determine a weight value.
14154 /// This object must already have been set up with the operand type
14155 /// and the current alternative constraint selected.
14156 TargetLowering::ConstraintWeight
14157 X86TargetLowering::getSingleConstraintMatchWeight(
14158 AsmOperandInfo &info, const char *constraint) const {
14159 ConstraintWeight weight = CW_Invalid;
14160 Value *CallOperandVal = info.CallOperandVal;
14161 // If we don't have a value, we can't do a match,
14162 // but allow it at the lowest weight.
14163 if (CallOperandVal == NULL)
14165 Type *type = CallOperandVal->getType();
14166 // Look at the constraint type.
14167 switch (*constraint) {
14169 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14180 if (CallOperandVal->getType()->isIntegerTy())
14181 weight = CW_SpecificReg;
14186 if (type->isFloatingPointTy())
14187 weight = CW_SpecificReg;
14190 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14191 weight = CW_SpecificReg;
14195 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
14196 weight = CW_Register;
14199 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14200 if (C->getZExtValue() <= 31)
14201 weight = CW_Constant;
14205 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14206 if (C->getZExtValue() <= 63)
14207 weight = CW_Constant;
14211 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14212 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14213 weight = CW_Constant;
14217 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14218 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14219 weight = CW_Constant;
14223 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14224 if (C->getZExtValue() <= 3)
14225 weight = CW_Constant;
14229 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14230 if (C->getZExtValue() <= 0xff)
14231 weight = CW_Constant;
14236 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14237 weight = CW_Constant;
14241 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14242 if ((C->getSExtValue() >= -0x80000000LL) &&
14243 (C->getSExtValue() <= 0x7fffffffLL))
14244 weight = CW_Constant;
14248 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14249 if (C->getZExtValue() <= 0xffffffff)
14250 weight = CW_Constant;
14257 /// LowerXConstraint - try to replace an X constraint, which matches anything,
14258 /// with another that has more specific requirements based on the type of the
14259 /// corresponding operand.
14260 const char *X86TargetLowering::
14261 LowerXConstraint(EVT ConstraintVT) const {
14262 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
14263 // 'f' like normal targets.
14264 if (ConstraintVT.isFloatingPoint()) {
14265 if (Subtarget->hasXMMInt())
14267 if (Subtarget->hasXMM())
14271 return TargetLowering::LowerXConstraint(ConstraintVT);
14274 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
14275 /// vector. If it is invalid, don't add anything to Ops.
14276 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
14277 std::string &Constraint,
14278 std::vector<SDValue>&Ops,
14279 SelectionDAG &DAG) const {
14280 SDValue Result(0, 0);
14282 // Only support length 1 constraints for now.
14283 if (Constraint.length() > 1) return;
14285 char ConstraintLetter = Constraint[0];
14286 switch (ConstraintLetter) {
14289 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14290 if (C->getZExtValue() <= 31) {
14291 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14297 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14298 if (C->getZExtValue() <= 63) {
14299 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14305 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14306 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
14307 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14313 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14314 if (C->getZExtValue() <= 255) {
14315 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14321 // 32-bit signed value
14322 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14323 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14324 C->getSExtValue())) {
14325 // Widen to 64 bits here to get it sign extended.
14326 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
14329 // FIXME gcc accepts some relocatable values here too, but only in certain
14330 // memory models; it's complicated.
14335 // 32-bit unsigned value
14336 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14337 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14338 C->getZExtValue())) {
14339 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14343 // FIXME gcc accepts some relocatable values here too, but only in certain
14344 // memory models; it's complicated.
14348 // Literal immediates are always ok.
14349 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
14350 // Widen to 64 bits here to get it sign extended.
14351 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
14355 // In any sort of PIC mode addresses need to be computed at runtime by
14356 // adding in a register or some sort of table lookup. These can't
14357 // be used as immediates.
14358 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
14361 // If we are in non-pic codegen mode, we allow the address of a global (with
14362 // an optional displacement) to be used with 'i'.
14363 GlobalAddressSDNode *GA = 0;
14364 int64_t Offset = 0;
14366 // Match either (GA), (GA+C), (GA+C1+C2), etc.
14368 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
14369 Offset += GA->getOffset();
14371 } else if (Op.getOpcode() == ISD::ADD) {
14372 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14373 Offset += C->getZExtValue();
14374 Op = Op.getOperand(0);
14377 } else if (Op.getOpcode() == ISD::SUB) {
14378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14379 Offset += -C->getZExtValue();
14380 Op = Op.getOperand(0);
14385 // Otherwise, this isn't something we can handle, reject it.
14389 const GlobalValue *GV = GA->getGlobal();
14390 // If we require an extra load to get this address, as in PIC mode, we
14391 // can't accept it.
14392 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
14393 getTargetMachine())))
14396 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
14397 GA->getValueType(0), Offset);
14402 if (Result.getNode()) {
14403 Ops.push_back(Result);
14406 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
14409 std::pair<unsigned, const TargetRegisterClass*>
14410 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
14412 // First, see if this is a constraint that directly corresponds to an LLVM
14414 if (Constraint.size() == 1) {
14415 // GCC Constraint Letters
14416 switch (Constraint[0]) {
14418 // TODO: Slight differences here in allocation order and leaving
14419 // RIP in the class. Do they matter any more here than they do
14420 // in the normal allocation?
14421 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
14422 if (Subtarget->is64Bit()) {
14423 if (VT == MVT::i32 || VT == MVT::f32)
14424 return std::make_pair(0U, X86::GR32RegisterClass);
14425 else if (VT == MVT::i16)
14426 return std::make_pair(0U, X86::GR16RegisterClass);
14427 else if (VT == MVT::i8 || VT == MVT::i1)
14428 return std::make_pair(0U, X86::GR8RegisterClass);
14429 else if (VT == MVT::i64 || VT == MVT::f64)
14430 return std::make_pair(0U, X86::GR64RegisterClass);
14433 // 32-bit fallthrough
14434 case 'Q': // Q_REGS
14435 if (VT == MVT::i32 || VT == MVT::f32)
14436 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
14437 else if (VT == MVT::i16)
14438 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
14439 else if (VT == MVT::i8 || VT == MVT::i1)
14440 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
14441 else if (VT == MVT::i64)
14442 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
14444 case 'r': // GENERAL_REGS
14445 case 'l': // INDEX_REGS
14446 if (VT == MVT::i8 || VT == MVT::i1)
14447 return std::make_pair(0U, X86::GR8RegisterClass);
14448 if (VT == MVT::i16)
14449 return std::make_pair(0U, X86::GR16RegisterClass);
14450 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
14451 return std::make_pair(0U, X86::GR32RegisterClass);
14452 return std::make_pair(0U, X86::GR64RegisterClass);
14453 case 'R': // LEGACY_REGS
14454 if (VT == MVT::i8 || VT == MVT::i1)
14455 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
14456 if (VT == MVT::i16)
14457 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
14458 if (VT == MVT::i32 || !Subtarget->is64Bit())
14459 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
14460 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
14461 case 'f': // FP Stack registers.
14462 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
14463 // value to the correct fpstack register class.
14464 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
14465 return std::make_pair(0U, X86::RFP32RegisterClass);
14466 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
14467 return std::make_pair(0U, X86::RFP64RegisterClass);
14468 return std::make_pair(0U, X86::RFP80RegisterClass);
14469 case 'y': // MMX_REGS if MMX allowed.
14470 if (!Subtarget->hasMMX()) break;
14471 return std::make_pair(0U, X86::VR64RegisterClass);
14472 case 'Y': // SSE_REGS if SSE2 allowed
14473 if (!Subtarget->hasXMMInt()) break;
14475 case 'x': // SSE_REGS if SSE1 allowed
14476 if (!Subtarget->hasXMM()) break;
14478 switch (VT.getSimpleVT().SimpleTy) {
14480 // Scalar SSE types.
14483 return std::make_pair(0U, X86::FR32RegisterClass);
14486 return std::make_pair(0U, X86::FR64RegisterClass);
14494 return std::make_pair(0U, X86::VR128RegisterClass);
14500 // Use the default implementation in TargetLowering to convert the register
14501 // constraint into a member of a register class.
14502 std::pair<unsigned, const TargetRegisterClass*> Res;
14503 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
14505 // Not found as a standard register?
14506 if (Res.second == 0) {
14507 // Map st(0) -> st(7) -> ST0
14508 if (Constraint.size() == 7 && Constraint[0] == '{' &&
14509 tolower(Constraint[1]) == 's' &&
14510 tolower(Constraint[2]) == 't' &&
14511 Constraint[3] == '(' &&
14512 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
14513 Constraint[5] == ')' &&
14514 Constraint[6] == '}') {
14516 Res.first = X86::ST0+Constraint[4]-'0';
14517 Res.second = X86::RFP80RegisterClass;
14521 // GCC allows "st(0)" to be called just plain "st".
14522 if (StringRef("{st}").equals_lower(Constraint)) {
14523 Res.first = X86::ST0;
14524 Res.second = X86::RFP80RegisterClass;
14529 if (StringRef("{flags}").equals_lower(Constraint)) {
14530 Res.first = X86::EFLAGS;
14531 Res.second = X86::CCRRegisterClass;
14535 // 'A' means EAX + EDX.
14536 if (Constraint == "A") {
14537 Res.first = X86::EAX;
14538 Res.second = X86::GR32_ADRegisterClass;
14544 // Otherwise, check to see if this is a register class of the wrong value
14545 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
14546 // turn into {ax},{dx}.
14547 if (Res.second->hasType(VT))
14548 return Res; // Correct type already, nothing to do.
14550 // All of the single-register GCC register classes map their values onto
14551 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
14552 // really want an 8-bit or 32-bit register, map to the appropriate register
14553 // class and return the appropriate register.
14554 if (Res.second == X86::GR16RegisterClass) {
14555 if (VT == MVT::i8) {
14556 unsigned DestReg = 0;
14557 switch (Res.first) {
14559 case X86::AX: DestReg = X86::AL; break;
14560 case X86::DX: DestReg = X86::DL; break;
14561 case X86::CX: DestReg = X86::CL; break;
14562 case X86::BX: DestReg = X86::BL; break;
14565 Res.first = DestReg;
14566 Res.second = X86::GR8RegisterClass;
14568 } else if (VT == MVT::i32) {
14569 unsigned DestReg = 0;
14570 switch (Res.first) {
14572 case X86::AX: DestReg = X86::EAX; break;
14573 case X86::DX: DestReg = X86::EDX; break;
14574 case X86::CX: DestReg = X86::ECX; break;
14575 case X86::BX: DestReg = X86::EBX; break;
14576 case X86::SI: DestReg = X86::ESI; break;
14577 case X86::DI: DestReg = X86::EDI; break;
14578 case X86::BP: DestReg = X86::EBP; break;
14579 case X86::SP: DestReg = X86::ESP; break;
14582 Res.first = DestReg;
14583 Res.second = X86::GR32RegisterClass;
14585 } else if (VT == MVT::i64) {
14586 unsigned DestReg = 0;
14587 switch (Res.first) {
14589 case X86::AX: DestReg = X86::RAX; break;
14590 case X86::DX: DestReg = X86::RDX; break;
14591 case X86::CX: DestReg = X86::RCX; break;
14592 case X86::BX: DestReg = X86::RBX; break;
14593 case X86::SI: DestReg = X86::RSI; break;
14594 case X86::DI: DestReg = X86::RDI; break;
14595 case X86::BP: DestReg = X86::RBP; break;
14596 case X86::SP: DestReg = X86::RSP; break;
14599 Res.first = DestReg;
14600 Res.second = X86::GR64RegisterClass;
14603 } else if (Res.second == X86::FR32RegisterClass ||
14604 Res.second == X86::FR64RegisterClass ||
14605 Res.second == X86::VR128RegisterClass) {
14606 // Handle references to XMM physical registers that got mapped into the
14607 // wrong class. This can happen with constraints like {xmm0} where the
14608 // target independent register mapper will just pick the first match it can
14609 // find, ignoring the required type.
14610 if (VT == MVT::f32)
14611 Res.second = X86::FR32RegisterClass;
14612 else if (VT == MVT::f64)
14613 Res.second = X86::FR64RegisterClass;
14614 else if (X86::VR128RegisterClass->hasType(VT))
14615 Res.second = X86::VR128RegisterClass;