1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
203 // are Legal, f80 is custom lowered.
204 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
207 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
209 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
210 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
212 if (X86ScalarSSEf32) {
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
214 // f32 and f64 cases are Legal, f80 case is not
215 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
221 // Handle FP_TO_UINT by promoting the destination to a larger signed
223 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
225 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
227 if (Subtarget->is64Bit()) {
228 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
229 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
230 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
234 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 } else if (!Subtarget->useSoftFloat()) {
237 // Since AVX is a superset of SSE3, only check for SSE here.
238 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
239 // Expand FP_TO_UINT into a select.
240 // FIXME: We would like to use a Custom expander here eventually to do
241 // the optimal thing for SSE vs. the default expansion in the legalizer.
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
244 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
249 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
252 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
253 if (!X86ScalarSSEf64) {
254 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
255 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
258 // Without SSE, i64->f64 goes through memory.
259 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
263 // Scalar integer divide and remainder are lowered to use operations that
264 // produce two results, to match the available instructions. This exposes
265 // the two-result form to trivial CSE, which is able to combine x/y and x%y
266 // into a single instruction.
268 // Scalar integer multiply-high is also lowered to use two-result
269 // operations, to match the available instructions. However, plain multiply
270 // (low) operations are left as Legal, as there are single-result
271 // instructions for this in x86. Using the two-result multiply instructions
272 // when both high and low results are needed must be arranged by dagcombine.
273 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
275 setOperationAction(ISD::MULHS, VT, Expand);
276 setOperationAction(ISD::MULHU, VT, Expand);
277 setOperationAction(ISD::SDIV, VT, Expand);
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
282 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
283 setOperationAction(ISD::ADDC, VT, Custom);
284 setOperationAction(ISD::ADDE, VT, Custom);
285 setOperationAction(ISD::SUBC, VT, Custom);
286 setOperationAction(ISD::SUBE, VT, Custom);
289 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
290 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
291 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
296 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
305 if (Subtarget->is64Bit())
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
308 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
309 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
310 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
312 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
313 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
314 // is. We should promote the value to 64-bits to solve this.
315 // This is what the CRT headers do - `fmodf` is an inline header
316 // function casting to f64 and calling `fmod`.
317 setOperationAction(ISD::FREM , MVT::f32 , Promote);
319 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->isTarget64BitLP64()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit()) {
502 setOperationAction(ISD::VAARG , MVT::Other, Custom);
503 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
505 // TargetInfo::CharPtrBuiltinVaList
506 setOperationAction(ISD::VAARG , MVT::Other, Expand);
507 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
510 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
511 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
513 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
515 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
516 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
517 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
519 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
520 // f32 and f64 use SSE.
521 // Set up the FP register classes.
522 addRegisterClass(MVT::f32, &X86::FR32RegClass);
523 addRegisterClass(MVT::f64, &X86::FR64RegClass);
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS , MVT::f64, Custom);
527 setOperationAction(ISD::FABS , MVT::f32, Custom);
529 // Use XORP to simulate FNEG.
530 setOperationAction(ISD::FNEG , MVT::f64, Custom);
531 setOperationAction(ISD::FNEG , MVT::f32, Custom);
533 // Use ANDPD and ORPD to simulate FCOPYSIGN.
534 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
535 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
537 // Lower this to FGETSIGNx86 plus an AND.
538 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
539 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
541 // We don't support sin/cos/fmod
542 setOperationAction(ISD::FSIN , MVT::f64, Expand);
543 setOperationAction(ISD::FCOS , MVT::f64, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
545 setOperationAction(ISD::FSIN , MVT::f32, Expand);
546 setOperationAction(ISD::FCOS , MVT::f32, Expand);
547 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
549 // Expand FP immediates into loads from the stack, except for the special
551 addLegalFPImmediate(APFloat(+0.0)); // xorpd
552 addLegalFPImmediate(APFloat(+0.0f)); // xorps
553 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
554 // Use SSE for f32, x87 for f64.
555 // Set up the FP register classes.
556 addRegisterClass(MVT::f32, &X86::FR32RegClass);
557 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
559 // Use ANDPS to simulate FABS.
560 setOperationAction(ISD::FABS , MVT::f32, Custom);
562 // Use XORP to simulate FNEG.
563 setOperationAction(ISD::FNEG , MVT::f32, Custom);
565 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
567 // Use ANDPS and ORPS to simulate FCOPYSIGN.
568 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
569 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
571 // We don't support sin/cos/fmod
572 setOperationAction(ISD::FSIN , MVT::f32, Expand);
573 setOperationAction(ISD::FCOS , MVT::f32, Expand);
574 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
576 // Special cases we handle for FP constants.
577 addLegalFPImmediate(APFloat(+0.0f)); // xorps
578 addLegalFPImmediate(APFloat(+0.0)); // FLD0
579 addLegalFPImmediate(APFloat(+1.0)); // FLD1
580 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
581 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
583 if (!TM.Options.UnsafeFPMath) {
584 setOperationAction(ISD::FSIN , MVT::f64, Expand);
585 setOperationAction(ISD::FCOS , MVT::f64, Expand);
586 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
588 } else if (!Subtarget->useSoftFloat()) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
592 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
599 if (!TM.Options.UnsafeFPMath) {
600 setOperationAction(ISD::FSIN , MVT::f64, Expand);
601 setOperationAction(ISD::FSIN , MVT::f32, Expand);
602 setOperationAction(ISD::FCOS , MVT::f64, Expand);
603 setOperationAction(ISD::FCOS , MVT::f32, Expand);
604 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
607 addLegalFPImmediate(APFloat(+0.0)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
611 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
617 // We don't support FMA.
618 setOperationAction(ISD::FMA, MVT::f64, Expand);
619 setOperationAction(ISD::FMA, MVT::f32, Expand);
621 // Long double always uses X87.
622 if (!Subtarget->useSoftFloat()) {
623 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
624 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
625 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
627 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
628 addLegalFPImmediate(TmpFlt); // FLD0
630 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
633 APFloat TmpFlt2(+1.0);
634 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
636 addLegalFPImmediate(TmpFlt2); // FLD1
637 TmpFlt2.changeSign();
638 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
641 if (!TM.Options.UnsafeFPMath) {
642 setOperationAction(ISD::FSIN , MVT::f80, Expand);
643 setOperationAction(ISD::FCOS , MVT::f80, Expand);
644 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
647 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
648 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
649 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
650 setOperationAction(ISD::FRINT, MVT::f80, Expand);
651 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
652 setOperationAction(ISD::FMA, MVT::f80, Expand);
655 // Always use a library call for pow.
656 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
657 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
660 setOperationAction(ISD::FLOG, MVT::f80, Expand);
661 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
663 setOperationAction(ISD::FEXP, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
665 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
666 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
668 // First set operation action for all vector types to either promote
669 // (for widening) or expand (for scalarization). Then we will selectively
670 // turn on ones that can be effectively codegen'd.
671 for (MVT VT : MVT::vector_valuetypes()) {
672 setOperationAction(ISD::ADD , VT, Expand);
673 setOperationAction(ISD::SUB , VT, Expand);
674 setOperationAction(ISD::FADD, VT, Expand);
675 setOperationAction(ISD::FNEG, VT, Expand);
676 setOperationAction(ISD::FSUB, VT, Expand);
677 setOperationAction(ISD::MUL , VT, Expand);
678 setOperationAction(ISD::FMUL, VT, Expand);
679 setOperationAction(ISD::SDIV, VT, Expand);
680 setOperationAction(ISD::UDIV, VT, Expand);
681 setOperationAction(ISD::FDIV, VT, Expand);
682 setOperationAction(ISD::SREM, VT, Expand);
683 setOperationAction(ISD::UREM, VT, Expand);
684 setOperationAction(ISD::LOAD, VT, Expand);
685 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
686 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
687 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
688 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
689 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::FABS, VT, Expand);
691 setOperationAction(ISD::FSIN, VT, Expand);
692 setOperationAction(ISD::FSINCOS, VT, Expand);
693 setOperationAction(ISD::FCOS, VT, Expand);
694 setOperationAction(ISD::FSINCOS, VT, Expand);
695 setOperationAction(ISD::FREM, VT, Expand);
696 setOperationAction(ISD::FMA, VT, Expand);
697 setOperationAction(ISD::FPOWI, VT, Expand);
698 setOperationAction(ISD::FSQRT, VT, Expand);
699 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
700 setOperationAction(ISD::FFLOOR, VT, Expand);
701 setOperationAction(ISD::FCEIL, VT, Expand);
702 setOperationAction(ISD::FTRUNC, VT, Expand);
703 setOperationAction(ISD::FRINT, VT, Expand);
704 setOperationAction(ISD::FNEARBYINT, VT, Expand);
705 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
706 setOperationAction(ISD::MULHS, VT, Expand);
707 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
708 setOperationAction(ISD::MULHU, VT, Expand);
709 setOperationAction(ISD::SDIVREM, VT, Expand);
710 setOperationAction(ISD::UDIVREM, VT, Expand);
711 setOperationAction(ISD::FPOW, VT, Expand);
712 setOperationAction(ISD::CTPOP, VT, Expand);
713 setOperationAction(ISD::CTTZ, VT, Expand);
714 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
715 setOperationAction(ISD::CTLZ, VT, Expand);
716 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
717 setOperationAction(ISD::SHL, VT, Expand);
718 setOperationAction(ISD::SRA, VT, Expand);
719 setOperationAction(ISD::SRL, VT, Expand);
720 setOperationAction(ISD::ROTL, VT, Expand);
721 setOperationAction(ISD::ROTR, VT, Expand);
722 setOperationAction(ISD::BSWAP, VT, Expand);
723 setOperationAction(ISD::SETCC, VT, Expand);
724 setOperationAction(ISD::FLOG, VT, Expand);
725 setOperationAction(ISD::FLOG2, VT, Expand);
726 setOperationAction(ISD::FLOG10, VT, Expand);
727 setOperationAction(ISD::FEXP, VT, Expand);
728 setOperationAction(ISD::FEXP2, VT, Expand);
729 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
730 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
731 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
732 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
734 setOperationAction(ISD::TRUNCATE, VT, Expand);
735 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
736 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
737 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
738 setOperationAction(ISD::VSELECT, VT, Expand);
739 setOperationAction(ISD::SELECT_CC, VT, Expand);
740 for (MVT InnerVT : MVT::vector_valuetypes()) {
741 setTruncStoreAction(InnerVT, VT, Expand);
743 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
744 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
746 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
747 // types, we have to deal with them whether we ask for Expansion or not.
748 // Setting Expand causes its own optimisation problems though, so leave
750 if (VT.getVectorElementType() == MVT::i1)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
753 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
754 // split/scalarized right now.
755 if (VT.getVectorElementType() == MVT::f16)
756 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
760 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
761 // with -msoft-float, disable use of MMX as well.
762 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
763 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
764 // No operations on x86mmx supported, everything uses intrinsics.
767 // MMX-sized vectors (other than x86mmx) are expected to be expanded
768 // into smaller operations.
769 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
770 setOperationAction(ISD::MULHS, MMXTy, Expand);
771 setOperationAction(ISD::AND, MMXTy, Expand);
772 setOperationAction(ISD::OR, MMXTy, Expand);
773 setOperationAction(ISD::XOR, MMXTy, Expand);
774 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
775 setOperationAction(ISD::SELECT, MMXTy, Expand);
776 setOperationAction(ISD::BITCAST, MMXTy, Expand);
778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
780 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
781 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
783 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
785 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
786 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
788 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
789 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
790 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
791 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
792 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
793 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
795 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
796 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
799 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
800 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
802 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
803 // registers cannot be used even for integer operations.
804 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
805 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
806 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
807 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
809 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
810 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
811 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
812 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
813 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
814 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
815 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
816 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
817 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
819 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
820 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
821 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
822 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
823 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
824 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
825 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
827 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
828 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
829 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
830 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
831 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
833 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
834 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
835 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
836 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
838 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
839 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
840 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
841 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
843 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
854 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
857 // ISD::CTTZ v2i64 - scalarization is faster.
858 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
861 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
863 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
864 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
865 MVT VT = (MVT::SimpleValueType)i;
866 // Do not attempt to custom lower non-power-of-2 vectors
867 if (!isPowerOf2_32(VT.getVectorNumElements()))
869 // Do not attempt to custom lower non-128-bit vectors
870 if (!VT.is128BitVector())
872 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
873 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
874 setOperationAction(ISD::VSELECT, VT, Custom);
875 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
878 // We support custom legalizing of sext and anyext loads for specific
879 // memory vector types which we can load as a scalar (or sequence of
880 // scalars) and extend in-register to a legal 128-bit vector type. For sext
881 // loads these must work with a single scalar load.
882 for (MVT VT : MVT::integer_vector_valuetypes()) {
883 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
886 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
887 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
888 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
889 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
890 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
891 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
899 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
908 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
909 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
910 MVT VT = (MVT::SimpleValueType)i;
912 // Do not attempt to promote non-128-bit vectors
913 if (!VT.is128BitVector())
916 setOperationAction(ISD::AND, VT, Promote);
917 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
918 setOperationAction(ISD::OR, VT, Promote);
919 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
920 setOperationAction(ISD::XOR, VT, Promote);
921 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, VT, Promote);
923 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, VT, Promote);
925 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
939 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
941 // As there is no 64-bit GPR available, we need build a special custom
942 // sequence to convert from v2i32 to v2f32.
943 if (!Subtarget->is64Bit())
944 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
949 for (MVT VT : MVT::fp_vector_valuetypes())
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
953 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
957 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
958 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
959 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
961 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
962 setOperationAction(ISD::FRINT, RoundedTy, Legal);
963 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
966 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
967 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
970 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
971 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
975 // FIXME: Do we need to handle scalar-to-vector here?
976 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
978 // We directly match byte blends in the backend as they match the VSELECT
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
982 // SSE41 brings specific instructions for doing vector sign extend even in
983 // cases where we don't have SRA.
984 for (MVT VT : MVT::integer_vector_valuetypes()) {
985 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
990 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
991 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1005 // i8 and i16 vectors are custom because the source register and source
1006 // source memory operand types are not the same width. f32 vectors are
1007 // custom since the immediate controlling the insert encodes additional
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1019 // FIXME: these should be Legal, but that's only for the case where
1020 // the index is constant. For now custom expand to deal with that.
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1027 if (Subtarget->hasSSE2()) {
1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1032 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1041 // In the customized shift lowering, the legal cases in AVX2 will be
1043 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1049 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1053 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1054 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1059 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1061 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1063 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1065 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1075 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1076 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1078 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1088 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1089 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1091 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1092 // even though v8i16 is a legal type.
1093 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1095 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1098 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1099 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1102 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1104 for (MVT VT : MVT::fp_vector_valuetypes())
1105 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1110 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1111 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1114 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1123 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1127 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1130 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1133 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1136 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1146 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1150 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1152 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1153 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1155 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1156 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1157 setOperationAction(ISD::FMA, MVT::f32, Legal);
1158 setOperationAction(ISD::FMA, MVT::f64, Legal);
1161 if (Subtarget->hasInt256()) {
1162 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1163 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1164 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1165 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1167 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1168 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1169 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1170 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1172 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1173 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1174 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1177 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1179 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1180 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1184 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1187 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1190 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1193 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1195 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1196 // when we have a 256bit-wide blend with immediate.
1197 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1199 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1205 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1212 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1214 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1231 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1234 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1240 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1243 // In the customized shift lowering, the legal cases in AVX2 will be
1245 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1246 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1248 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1254 // Custom lower several nodes for 256-bit types.
1255 for (MVT VT : MVT::vector_valuetypes()) {
1256 if (VT.getScalarSizeInBits() >= 32) {
1257 setOperationAction(ISD::MLOAD, VT, Legal);
1258 setOperationAction(ISD::MSTORE, VT, Legal);
1260 // Extract subvector is special because the value type
1261 // (result) is 128-bit but the source is 256-bit wide.
1262 if (VT.is128BitVector()) {
1263 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1265 // Do not attempt to custom lower other non-256-bit vectors
1266 if (!VT.is256BitVector())
1269 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1270 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1271 setOperationAction(ISD::VSELECT, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 if (Subtarget->hasInt256())
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1310 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1311 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1313 for (MVT VT : MVT::fp_vector_valuetypes())
1314 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1316 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1317 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1318 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1319 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1320 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1321 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1322 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1323 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1324 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1325 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1326 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1327 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1329 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1330 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1331 setOperationAction(ISD::XOR, MVT::i1, Legal);
1332 setOperationAction(ISD::OR, MVT::i1, Legal);
1333 setOperationAction(ISD::AND, MVT::i1, Legal);
1334 setOperationAction(ISD::SUB, MVT::i1, Custom);
1335 setOperationAction(ISD::ADD, MVT::i1, Custom);
1336 setOperationAction(ISD::MUL, MVT::i1, Custom);
1337 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1339 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1340 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1341 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1343 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1345 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1347 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1350 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1356 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1357 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1359 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1360 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1361 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1362 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1363 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1364 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1365 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1366 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1367 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1368 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1370 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1371 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1372 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1373 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1374 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1376 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1377 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1378 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1379 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1380 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1381 if (Subtarget->hasVLX()){
1382 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1383 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1384 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1385 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1386 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1388 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1389 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1390 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1391 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1392 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1394 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1396 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1397 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1398 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1399 if (Subtarget->hasDQI()) {
1400 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1401 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1407 if (Subtarget->hasVLX()) {
1408 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1418 if (Subtarget->hasVLX()) {
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1422 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1425 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1426 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1440 if (Subtarget->hasDQI()) {
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1444 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1448 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1449 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1450 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1451 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1452 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1453 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1461 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1464 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1466 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1468 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1470 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1476 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1478 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1479 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1480 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1481 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1482 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1483 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1484 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1485 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1487 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1488 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1490 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1491 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1493 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1495 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1498 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1499 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1501 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1502 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1504 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1505 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1506 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1507 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1508 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1509 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1511 if (Subtarget->hasCDI()) {
1512 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1513 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1517 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1518 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1520 if (Subtarget->hasVLX() && Subtarget->hasCDI()) {
1521 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1522 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1523 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1524 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1527 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1531 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1532 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1535 if (Subtarget->hasDQI()) {
1536 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1537 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1538 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1540 // Custom lower several nodes.
1541 for (MVT VT : MVT::vector_valuetypes()) {
1542 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1544 setOperationAction(ISD::AND, VT, Legal);
1545 setOperationAction(ISD::OR, VT, Legal);
1546 setOperationAction(ISD::XOR, VT, Legal);
1548 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1549 setOperationAction(ISD::MGATHER, VT, Custom);
1550 setOperationAction(ISD::MSCATTER, VT, Custom);
1552 // Extract subvector is special because the value type
1553 // (result) is 256/128-bit but the source is 512-bit wide.
1554 if (VT.is128BitVector() || VT.is256BitVector()) {
1555 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1557 if (VT.getVectorElementType() == MVT::i1)
1558 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1560 // Do not attempt to custom lower other non-512-bit vectors
1561 if (!VT.is512BitVector())
1564 if (EltSize >= 32) {
1565 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1566 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1567 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1568 setOperationAction(ISD::VSELECT, VT, Legal);
1569 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1570 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1571 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1572 setOperationAction(ISD::MLOAD, VT, Legal);
1573 setOperationAction(ISD::MSTORE, VT, Legal);
1576 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1577 MVT VT = (MVT::SimpleValueType)i;
1579 // Do not attempt to promote non-512-bit vectors.
1580 if (!VT.is512BitVector())
1583 setOperationAction(ISD::SELECT, VT, Promote);
1584 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1588 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1589 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1590 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1592 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1593 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1595 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1596 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1597 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1598 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1599 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1600 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1601 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1602 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1603 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1604 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1605 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1606 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1607 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1608 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1609 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1610 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1611 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1612 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1613 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1614 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1615 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1616 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1617 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1618 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1619 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1620 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1621 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1622 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1623 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1624 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1625 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1626 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1629 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1630 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1631 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1632 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1633 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1634 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1635 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1636 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1638 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1639 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1640 if (Subtarget->hasVLX())
1641 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1643 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1644 const MVT VT = (MVT::SimpleValueType)i;
1646 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1648 // Do not attempt to promote non-512-bit vectors.
1649 if (!VT.is512BitVector())
1653 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1654 setOperationAction(ISD::VSELECT, VT, Legal);
1659 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1660 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1661 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1663 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1664 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1665 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1666 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1667 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1668 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1669 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1670 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1671 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1672 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1676 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1677 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1678 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1679 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1680 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1681 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1682 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1683 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1685 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1686 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1687 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1688 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1689 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1690 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1691 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1692 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1695 // We want to custom lower some of our intrinsics.
1696 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1697 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1698 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1699 if (!Subtarget->is64Bit())
1700 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1702 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1703 // handle type legalization for these operations here.
1705 // FIXME: We really should do custom legalization for addition and
1706 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1707 // than generic legalization for 64-bit multiplication-with-overflow, though.
1708 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1709 // Add/Sub/Mul with overflow operations are custom lowered.
1711 setOperationAction(ISD::SADDO, VT, Custom);
1712 setOperationAction(ISD::UADDO, VT, Custom);
1713 setOperationAction(ISD::SSUBO, VT, Custom);
1714 setOperationAction(ISD::USUBO, VT, Custom);
1715 setOperationAction(ISD::SMULO, VT, Custom);
1716 setOperationAction(ISD::UMULO, VT, Custom);
1719 if (!Subtarget->is64Bit()) {
1720 // These libcalls are not available in 32-bit.
1721 setLibcallName(RTLIB::SHL_I128, nullptr);
1722 setLibcallName(RTLIB::SRL_I128, nullptr);
1723 setLibcallName(RTLIB::SRA_I128, nullptr);
1726 // Combine sin / cos into one node or libcall if possible.
1727 if (Subtarget->hasSinCos()) {
1728 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1729 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1730 if (Subtarget->isTargetDarwin()) {
1731 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1732 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1733 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1734 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1738 if (Subtarget->isTargetWin64()) {
1739 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1740 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1741 setOperationAction(ISD::SREM, MVT::i128, Custom);
1742 setOperationAction(ISD::UREM, MVT::i128, Custom);
1743 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1744 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1747 // We have target-specific dag combine patterns for the following nodes:
1748 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1749 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1750 setTargetDAGCombine(ISD::BITCAST);
1751 setTargetDAGCombine(ISD::VSELECT);
1752 setTargetDAGCombine(ISD::SELECT);
1753 setTargetDAGCombine(ISD::SHL);
1754 setTargetDAGCombine(ISD::SRA);
1755 setTargetDAGCombine(ISD::SRL);
1756 setTargetDAGCombine(ISD::OR);
1757 setTargetDAGCombine(ISD::AND);
1758 setTargetDAGCombine(ISD::ADD);
1759 setTargetDAGCombine(ISD::FADD);
1760 setTargetDAGCombine(ISD::FSUB);
1761 setTargetDAGCombine(ISD::FMA);
1762 setTargetDAGCombine(ISD::SUB);
1763 setTargetDAGCombine(ISD::LOAD);
1764 setTargetDAGCombine(ISD::MLOAD);
1765 setTargetDAGCombine(ISD::STORE);
1766 setTargetDAGCombine(ISD::MSTORE);
1767 setTargetDAGCombine(ISD::ZERO_EXTEND);
1768 setTargetDAGCombine(ISD::ANY_EXTEND);
1769 setTargetDAGCombine(ISD::SIGN_EXTEND);
1770 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1771 setTargetDAGCombine(ISD::SINT_TO_FP);
1772 setTargetDAGCombine(ISD::UINT_TO_FP);
1773 setTargetDAGCombine(ISD::SETCC);
1774 setTargetDAGCombine(ISD::BUILD_VECTOR);
1775 setTargetDAGCombine(ISD::MUL);
1776 setTargetDAGCombine(ISD::XOR);
1778 computeRegisterProperties(Subtarget->getRegisterInfo());
1780 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1781 MaxStoresPerMemsetOptSize = 8;
1782 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1783 MaxStoresPerMemcpyOptSize = 4;
1784 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1785 MaxStoresPerMemmoveOptSize = 4;
1786 setPrefLoopAlignment(4); // 2^4 bytes.
1788 // A predictable cmov does not hurt on an in-order CPU.
1789 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1790 PredictableSelectIsExpensive = !Subtarget->isAtom();
1791 EnableExtLdPromotion = true;
1792 setPrefFunctionAlignment(4); // 2^4 bytes.
1794 verifyIntrinsicTables();
1797 // This has so far only been implemented for 64-bit MachO.
1798 bool X86TargetLowering::useLoadStackGuardNode() const {
1799 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1802 TargetLoweringBase::LegalizeTypeAction
1803 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1804 if (ExperimentalVectorWideningLegalization &&
1805 VT.getVectorNumElements() != 1 &&
1806 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1807 return TypeWidenVector;
1809 return TargetLoweringBase::getPreferredVectorAction(VT);
1812 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1815 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1817 const unsigned NumElts = VT.getVectorNumElements();
1818 const EVT EltVT = VT.getVectorElementType();
1819 if (VT.is512BitVector()) {
1820 if (Subtarget->hasAVX512())
1821 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1822 EltVT == MVT::f32 || EltVT == MVT::f64)
1824 case 8: return MVT::v8i1;
1825 case 16: return MVT::v16i1;
1827 if (Subtarget->hasBWI())
1828 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1830 case 32: return MVT::v32i1;
1831 case 64: return MVT::v64i1;
1835 if (VT.is256BitVector() || VT.is128BitVector()) {
1836 if (Subtarget->hasVLX())
1837 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1838 EltVT == MVT::f32 || EltVT == MVT::f64)
1840 case 2: return MVT::v2i1;
1841 case 4: return MVT::v4i1;
1842 case 8: return MVT::v8i1;
1844 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1845 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1847 case 8: return MVT::v8i1;
1848 case 16: return MVT::v16i1;
1849 case 32: return MVT::v32i1;
1853 return VT.changeVectorElementTypeToInteger();
1856 /// Helper for getByValTypeAlignment to determine
1857 /// the desired ByVal argument alignment.
1858 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1861 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1862 if (VTy->getBitWidth() == 128)
1864 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1865 unsigned EltAlign = 0;
1866 getMaxByValAlign(ATy->getElementType(), EltAlign);
1867 if (EltAlign > MaxAlign)
1868 MaxAlign = EltAlign;
1869 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1870 for (auto *EltTy : STy->elements()) {
1871 unsigned EltAlign = 0;
1872 getMaxByValAlign(EltTy, EltAlign);
1873 if (EltAlign > MaxAlign)
1874 MaxAlign = EltAlign;
1881 /// Return the desired alignment for ByVal aggregate
1882 /// function arguments in the caller parameter area. For X86, aggregates
1883 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1884 /// are at 4-byte boundaries.
1885 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1886 const DataLayout &DL) const {
1887 if (Subtarget->is64Bit()) {
1888 // Max of 8 and alignment of type.
1889 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1896 if (Subtarget->hasSSE1())
1897 getMaxByValAlign(Ty, Align);
1901 /// Returns the target specific optimal type for load
1902 /// and store operations as a result of memset, memcpy, and memmove
1903 /// lowering. If DstAlign is zero that means it's safe to destination
1904 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1905 /// means there isn't a need to check it against alignment requirement,
1906 /// probably because the source does not need to be loaded. If 'IsMemset' is
1907 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1908 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1909 /// source is constant so it does not need to be loaded.
1910 /// It returns EVT::Other if the type should be determined using generic
1911 /// target-independent logic.
1913 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1914 unsigned DstAlign, unsigned SrcAlign,
1915 bool IsMemset, bool ZeroMemset,
1917 MachineFunction &MF) const {
1918 const Function *F = MF.getFunction();
1919 if ((!IsMemset || ZeroMemset) &&
1920 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1922 (!Subtarget->isUnalignedMem16Slow() ||
1923 ((DstAlign == 0 || DstAlign >= 16) &&
1924 (SrcAlign == 0 || SrcAlign >= 16)))) {
1926 // FIXME: Check if unaligned 32-byte accesses are slow.
1927 if (Subtarget->hasInt256())
1929 if (Subtarget->hasFp256())
1932 if (Subtarget->hasSSE2())
1934 if (Subtarget->hasSSE1())
1936 } else if (!MemcpyStrSrc && Size >= 8 &&
1937 !Subtarget->is64Bit() &&
1938 Subtarget->hasSSE2()) {
1939 // Do not use f64 to lower memcpy if source is string constant. It's
1940 // better to use i32 to avoid the loads.
1944 // This is a compromise. If we reach here, unaligned accesses may be slow on
1945 // this target. However, creating smaller, aligned accesses could be even
1946 // slower and would certainly be a lot more code.
1947 if (Subtarget->is64Bit() && Size >= 8)
1952 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1954 return X86ScalarSSEf32;
1955 else if (VT == MVT::f64)
1956 return X86ScalarSSEf64;
1961 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1966 switch (VT.getSizeInBits()) {
1968 // 8-byte and under are always assumed to be fast.
1972 *Fast = !Subtarget->isUnalignedMem16Slow();
1975 *Fast = !Subtarget->isUnalignedMem32Slow();
1977 // TODO: What about AVX-512 (512-bit) accesses?
1980 // Misaligned accesses of any size are always allowed.
1984 /// Return the entry encoding for a jump table in the
1985 /// current function. The returned value is a member of the
1986 /// MachineJumpTableInfo::JTEntryKind enum.
1987 unsigned X86TargetLowering::getJumpTableEncoding() const {
1988 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1990 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1991 Subtarget->isPICStyleGOT())
1992 return MachineJumpTableInfo::EK_Custom32;
1994 // Otherwise, use the normal jump table encoding heuristics.
1995 return TargetLowering::getJumpTableEncoding();
1998 bool X86TargetLowering::useSoftFloat() const {
1999 return Subtarget->useSoftFloat();
2003 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2004 const MachineBasicBlock *MBB,
2005 unsigned uid,MCContext &Ctx) const{
2006 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2007 Subtarget->isPICStyleGOT());
2008 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2010 return MCSymbolRefExpr::create(MBB->getSymbol(),
2011 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2014 /// Returns relocation base for the given PIC jumptable.
2015 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2016 SelectionDAG &DAG) const {
2017 if (!Subtarget->is64Bit())
2018 // This doesn't have SDLoc associated with it, but is not really the
2019 // same as a Register.
2020 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2021 getPointerTy(DAG.getDataLayout()));
2025 /// This returns the relocation base for the given PIC jumptable,
2026 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2027 const MCExpr *X86TargetLowering::
2028 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2029 MCContext &Ctx) const {
2030 // X86-64 uses RIP relative addressing based on the jump table label.
2031 if (Subtarget->isPICStyleRIPRel())
2032 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2034 // Otherwise, the reference is relative to the PIC base.
2035 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2038 std::pair<const TargetRegisterClass *, uint8_t>
2039 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2041 const TargetRegisterClass *RRC = nullptr;
2043 switch (VT.SimpleTy) {
2045 return TargetLowering::findRepresentativeClass(TRI, VT);
2046 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2047 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2050 RRC = &X86::VR64RegClass;
2052 case MVT::f32: case MVT::f64:
2053 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2054 case MVT::v4f32: case MVT::v2f64:
2055 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2057 RRC = &X86::VR128RegClass;
2060 return std::make_pair(RRC, Cost);
2063 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2064 unsigned &Offset) const {
2065 if (!Subtarget->isTargetLinux())
2068 if (Subtarget->is64Bit()) {
2069 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2071 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2083 /// Android provides a fixed TLS slot for the SafeStack pointer.
2084 /// See the definition of TLS_SLOT_SAFESTACK in
2085 /// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2086 bool X86TargetLowering::getSafeStackPointerLocation(unsigned &AddressSpace,
2087 unsigned &Offset) const {
2088 if (!Subtarget->isTargetAndroid())
2091 if (Subtarget->is64Bit()) {
2092 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2094 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2106 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2107 unsigned DestAS) const {
2108 assert(SrcAS != DestAS && "Expected different address spaces!");
2110 return SrcAS < 256 && DestAS < 256;
2113 //===----------------------------------------------------------------------===//
2114 // Return Value Calling Convention Implementation
2115 //===----------------------------------------------------------------------===//
2117 #include "X86GenCallingConv.inc"
2119 bool X86TargetLowering::CanLowerReturn(
2120 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2121 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2122 SmallVector<CCValAssign, 16> RVLocs;
2123 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2124 return CCInfo.CheckReturn(Outs, RetCC_X86);
2127 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2128 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2133 X86TargetLowering::LowerReturn(SDValue Chain,
2134 CallingConv::ID CallConv, bool isVarArg,
2135 const SmallVectorImpl<ISD::OutputArg> &Outs,
2136 const SmallVectorImpl<SDValue> &OutVals,
2137 SDLoc dl, SelectionDAG &DAG) const {
2138 MachineFunction &MF = DAG.getMachineFunction();
2139 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2141 SmallVector<CCValAssign, 16> RVLocs;
2142 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2143 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2146 SmallVector<SDValue, 6> RetOps;
2147 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2148 // Operand #1 = Bytes To Pop
2149 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2152 // Copy the result values into the output registers.
2153 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2154 CCValAssign &VA = RVLocs[i];
2155 assert(VA.isRegLoc() && "Can only return in registers!");
2156 SDValue ValToCopy = OutVals[i];
2157 EVT ValVT = ValToCopy.getValueType();
2159 // Promote values to the appropriate types.
2160 if (VA.getLocInfo() == CCValAssign::SExt)
2161 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2162 else if (VA.getLocInfo() == CCValAssign::ZExt)
2163 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2164 else if (VA.getLocInfo() == CCValAssign::AExt) {
2165 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2166 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2168 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2170 else if (VA.getLocInfo() == CCValAssign::BCvt)
2171 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2173 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2174 "Unexpected FP-extend for return value.");
2176 // If this is x86-64, and we disabled SSE, we can't return FP values,
2177 // or SSE or MMX vectors.
2178 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2179 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2180 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2181 report_fatal_error("SSE register return with SSE disabled");
2183 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2184 // llvm-gcc has never done it right and no one has noticed, so this
2185 // should be OK for now.
2186 if (ValVT == MVT::f64 &&
2187 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2188 report_fatal_error("SSE2 register return with SSE2 disabled");
2190 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2191 // the RET instruction and handled by the FP Stackifier.
2192 if (VA.getLocReg() == X86::FP0 ||
2193 VA.getLocReg() == X86::FP1) {
2194 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2195 // change the value to the FP stack register class.
2196 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2197 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2198 RetOps.push_back(ValToCopy);
2199 // Don't emit a copytoreg.
2203 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2204 // which is returned in RAX / RDX.
2205 if (Subtarget->is64Bit()) {
2206 if (ValVT == MVT::x86mmx) {
2207 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2208 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2209 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2211 // If we don't have SSE2 available, convert to v4f32 so the generated
2212 // register is legal.
2213 if (!Subtarget->hasSSE2())
2214 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2219 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2220 Flag = Chain.getValue(1);
2221 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2224 // All x86 ABIs require that for returning structs by value we copy
2225 // the sret argument into %rax/%eax (depending on ABI) for the return.
2226 // We saved the argument into a virtual register in the entry block,
2227 // so now we copy the value out and into %rax/%eax.
2229 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2230 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2231 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2232 // either case FuncInfo->setSRetReturnReg() will have been called.
2233 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2234 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2235 getPointerTy(MF.getDataLayout()));
2238 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2239 X86::RAX : X86::EAX;
2240 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2241 Flag = Chain.getValue(1);
2243 // RAX/EAX now acts like a return value.
2245 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2248 RetOps[0] = Chain; // Update chain.
2250 // Add the flag if we have it.
2252 RetOps.push_back(Flag);
2254 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2257 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2258 if (N->getNumValues() != 1)
2260 if (!N->hasNUsesOfValue(1, 0))
2263 SDValue TCChain = Chain;
2264 SDNode *Copy = *N->use_begin();
2265 if (Copy->getOpcode() == ISD::CopyToReg) {
2266 // If the copy has a glue operand, we conservatively assume it isn't safe to
2267 // perform a tail call.
2268 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2270 TCChain = Copy->getOperand(0);
2271 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2274 bool HasRet = false;
2275 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2277 if (UI->getOpcode() != X86ISD::RET_FLAG)
2279 // If we are returning more than one value, we can definitely
2280 // not make a tail call see PR19530
2281 if (UI->getNumOperands() > 4)
2283 if (UI->getNumOperands() == 4 &&
2284 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2297 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2298 ISD::NodeType ExtendKind) const {
2300 // TODO: Is this also valid on 32-bit?
2301 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2302 ReturnMVT = MVT::i8;
2304 ReturnMVT = MVT::i32;
2306 EVT MinVT = getRegisterType(Context, ReturnMVT);
2307 return VT.bitsLT(MinVT) ? MinVT : VT;
2310 /// Lower the result values of a call into the
2311 /// appropriate copies out of appropriate physical registers.
2314 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2315 CallingConv::ID CallConv, bool isVarArg,
2316 const SmallVectorImpl<ISD::InputArg> &Ins,
2317 SDLoc dl, SelectionDAG &DAG,
2318 SmallVectorImpl<SDValue> &InVals) const {
2320 // Assign locations to each value returned by this call.
2321 SmallVector<CCValAssign, 16> RVLocs;
2322 bool Is64Bit = Subtarget->is64Bit();
2323 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2325 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2327 // Copy all of the result registers out of their specified physreg.
2328 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2329 CCValAssign &VA = RVLocs[i];
2330 EVT CopyVT = VA.getLocVT();
2332 // If this is x86-64, and we disabled SSE, we can't return FP values
2333 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2334 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2335 report_fatal_error("SSE register return with SSE disabled");
2338 // If we prefer to use the value in xmm registers, copy it out as f80 and
2339 // use a truncate to move it from fp stack reg to xmm reg.
2340 bool RoundAfterCopy = false;
2341 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2342 isScalarFPTypeInSSEReg(VA.getValVT())) {
2344 RoundAfterCopy = (CopyVT != VA.getLocVT());
2347 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2348 CopyVT, InFlag).getValue(1);
2349 SDValue Val = Chain.getValue(0);
2352 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2353 // This truncation won't change the value.
2354 DAG.getIntPtrConstant(1, dl));
2356 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2357 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2359 InFlag = Chain.getValue(2);
2360 InVals.push_back(Val);
2366 //===----------------------------------------------------------------------===//
2367 // C & StdCall & Fast Calling Convention implementation
2368 //===----------------------------------------------------------------------===//
2369 // StdCall calling convention seems to be standard for many Windows' API
2370 // routines and around. It differs from C calling convention just a little:
2371 // callee should clean up the stack, not caller. Symbols should be also
2372 // decorated in some fancy way :) It doesn't support any vector arguments.
2373 // For info on fast calling convention see Fast Calling Convention (tail call)
2374 // implementation LowerX86_32FastCCCallTo.
2376 /// CallIsStructReturn - Determines whether a call uses struct return
2378 enum StructReturnType {
2383 static StructReturnType
2384 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2386 return NotStructReturn;
2388 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2389 if (!Flags.isSRet())
2390 return NotStructReturn;
2391 if (Flags.isInReg())
2392 return RegStructReturn;
2393 return StackStructReturn;
2396 /// Determines whether a function uses struct return semantics.
2397 static StructReturnType
2398 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2400 return NotStructReturn;
2402 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2403 if (!Flags.isSRet())
2404 return NotStructReturn;
2405 if (Flags.isInReg())
2406 return RegStructReturn;
2407 return StackStructReturn;
2410 /// Make a copy of an aggregate at address specified by "Src" to address
2411 /// "Dst" with size and alignment information specified by the specific
2412 /// parameter attribute. The copy will be passed as a byval function parameter.
2414 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2415 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2417 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2419 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2420 /*isVolatile*/false, /*AlwaysInline=*/true,
2421 /*isTailCall*/false,
2422 MachinePointerInfo(), MachinePointerInfo());
2425 /// Return true if the calling convention is one that
2426 /// supports tail call optimization.
2427 static bool IsTailCallConvention(CallingConv::ID CC) {
2428 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2429 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2432 /// \brief Return true if the calling convention is a C calling convention.
2433 static bool IsCCallConvention(CallingConv::ID CC) {
2434 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2435 CC == CallingConv::X86_64_SysV);
2438 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2440 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2441 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2445 CallingConv::ID CalleeCC = CS.getCallingConv();
2446 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2452 /// Return true if the function is being made into
2453 /// a tailcall target by changing its ABI.
2454 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2455 bool GuaranteedTailCallOpt) {
2456 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2460 X86TargetLowering::LowerMemArgument(SDValue Chain,
2461 CallingConv::ID CallConv,
2462 const SmallVectorImpl<ISD::InputArg> &Ins,
2463 SDLoc dl, SelectionDAG &DAG,
2464 const CCValAssign &VA,
2465 MachineFrameInfo *MFI,
2467 // Create the nodes corresponding to a load from this parameter slot.
2468 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2469 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2470 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2471 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2474 // If value is passed by pointer we have address passed instead of the value
2476 bool ExtendedInMem = VA.isExtInLoc() &&
2477 VA.getValVT().getScalarType() == MVT::i1;
2479 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2480 ValVT = VA.getLocVT();
2482 ValVT = VA.getValVT();
2484 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2485 // changed with more analysis.
2486 // In case of tail call optimization mark all arguments mutable. Since they
2487 // could be overwritten by lowering of arguments in case of a tail call.
2488 if (Flags.isByVal()) {
2489 unsigned Bytes = Flags.getByValSize();
2490 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2491 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2492 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2494 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2495 VA.getLocMemOffset(), isImmutable);
2496 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2497 SDValue Val = DAG.getLoad(
2498 ValVT, dl, Chain, FIN,
2499 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2501 return ExtendedInMem ?
2502 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2506 // FIXME: Get this from tablegen.
2507 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2508 const X86Subtarget *Subtarget) {
2509 assert(Subtarget->is64Bit());
2511 if (Subtarget->isCallingConvWin64(CallConv)) {
2512 static const MCPhysReg GPR64ArgRegsWin64[] = {
2513 X86::RCX, X86::RDX, X86::R8, X86::R9
2515 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2518 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2519 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2521 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2524 // FIXME: Get this from tablegen.
2525 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2526 CallingConv::ID CallConv,
2527 const X86Subtarget *Subtarget) {
2528 assert(Subtarget->is64Bit());
2529 if (Subtarget->isCallingConvWin64(CallConv)) {
2530 // The XMM registers which might contain var arg parameters are shadowed
2531 // in their paired GPR. So we only need to save the GPR to their home
2533 // TODO: __vectorcall will change this.
2537 const Function *Fn = MF.getFunction();
2538 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2539 bool isSoftFloat = Subtarget->useSoftFloat();
2540 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2541 "SSE register cannot be used when SSE is disabled!");
2542 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2543 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2547 static const MCPhysReg XMMArgRegs64Bit[] = {
2548 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2549 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2551 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2554 SDValue X86TargetLowering::LowerFormalArguments(
2555 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2556 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2557 SmallVectorImpl<SDValue> &InVals) const {
2558 MachineFunction &MF = DAG.getMachineFunction();
2559 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2560 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2562 const Function* Fn = MF.getFunction();
2563 if (Fn->hasExternalLinkage() &&
2564 Subtarget->isTargetCygMing() &&
2565 Fn->getName() == "main")
2566 FuncInfo->setForceFramePointer(true);
2568 MachineFrameInfo *MFI = MF.getFrameInfo();
2569 bool Is64Bit = Subtarget->is64Bit();
2570 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2572 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2573 "Var args not supported with calling convention fastcc, ghc or hipe");
2575 // Assign locations to all of the incoming arguments.
2576 SmallVector<CCValAssign, 16> ArgLocs;
2577 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2579 // Allocate shadow area for Win64
2581 CCInfo.AllocateStack(32, 8);
2583 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2585 unsigned LastVal = ~0U;
2587 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2588 CCValAssign &VA = ArgLocs[i];
2589 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2591 assert(VA.getValNo() != LastVal &&
2592 "Don't support value assigned to multiple locs yet");
2594 LastVal = VA.getValNo();
2596 if (VA.isRegLoc()) {
2597 EVT RegVT = VA.getLocVT();
2598 const TargetRegisterClass *RC;
2599 if (RegVT == MVT::i32)
2600 RC = &X86::GR32RegClass;
2601 else if (Is64Bit && RegVT == MVT::i64)
2602 RC = &X86::GR64RegClass;
2603 else if (RegVT == MVT::f32)
2604 RC = &X86::FR32RegClass;
2605 else if (RegVT == MVT::f64)
2606 RC = &X86::FR64RegClass;
2607 else if (RegVT.is512BitVector())
2608 RC = &X86::VR512RegClass;
2609 else if (RegVT.is256BitVector())
2610 RC = &X86::VR256RegClass;
2611 else if (RegVT.is128BitVector())
2612 RC = &X86::VR128RegClass;
2613 else if (RegVT == MVT::x86mmx)
2614 RC = &X86::VR64RegClass;
2615 else if (RegVT == MVT::i1)
2616 RC = &X86::VK1RegClass;
2617 else if (RegVT == MVT::v8i1)
2618 RC = &X86::VK8RegClass;
2619 else if (RegVT == MVT::v16i1)
2620 RC = &X86::VK16RegClass;
2621 else if (RegVT == MVT::v32i1)
2622 RC = &X86::VK32RegClass;
2623 else if (RegVT == MVT::v64i1)
2624 RC = &X86::VK64RegClass;
2626 llvm_unreachable("Unknown argument type!");
2628 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2629 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2631 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2632 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2634 if (VA.getLocInfo() == CCValAssign::SExt)
2635 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2636 DAG.getValueType(VA.getValVT()));
2637 else if (VA.getLocInfo() == CCValAssign::ZExt)
2638 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2639 DAG.getValueType(VA.getValVT()));
2640 else if (VA.getLocInfo() == CCValAssign::BCvt)
2641 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2643 if (VA.isExtInLoc()) {
2644 // Handle MMX values passed in XMM regs.
2645 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2646 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2648 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2651 assert(VA.isMemLoc());
2652 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2655 // If value is passed via pointer - do a load.
2656 if (VA.getLocInfo() == CCValAssign::Indirect)
2657 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2658 MachinePointerInfo(), false, false, false, 0);
2660 InVals.push_back(ArgValue);
2663 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2664 // All x86 ABIs require that for returning structs by value we copy the
2665 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2666 // the argument into a virtual register so that we can access it from the
2668 if (Ins[i].Flags.isSRet()) {
2669 unsigned Reg = FuncInfo->getSRetReturnReg();
2671 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2672 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2673 FuncInfo->setSRetReturnReg(Reg);
2675 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2676 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2681 unsigned StackSize = CCInfo.getNextStackOffset();
2682 // Align stack specially for tail calls.
2683 if (FuncIsMadeTailCallSafe(CallConv,
2684 MF.getTarget().Options.GuaranteedTailCallOpt))
2685 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2687 // If the function takes variable number of arguments, make a frame index for
2688 // the start of the first vararg value... for expansion of llvm.va_start. We
2689 // can skip this if there are no va_start calls.
2690 if (MFI->hasVAStart() &&
2691 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2692 CallConv != CallingConv::X86_ThisCall))) {
2693 FuncInfo->setVarArgsFrameIndex(
2694 MFI->CreateFixedObject(1, StackSize, true));
2697 MachineModuleInfo &MMI = MF.getMMI();
2698 const Function *WinEHParent = nullptr;
2699 if (MMI.hasWinEHFuncInfo(Fn))
2700 WinEHParent = MMI.getWinEHParent(Fn);
2701 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2703 // Figure out if XMM registers are in use.
2704 assert(!(Subtarget->useSoftFloat() &&
2705 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2706 "SSE register cannot be used when SSE is disabled!");
2708 // 64-bit calling conventions support varargs and register parameters, so we
2709 // have to do extra work to spill them in the prologue.
2710 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2711 // Find the first unallocated argument registers.
2712 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2713 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2714 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2715 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2716 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2717 "SSE register cannot be used when SSE is disabled!");
2719 // Gather all the live in physical registers.
2720 SmallVector<SDValue, 6> LiveGPRs;
2721 SmallVector<SDValue, 8> LiveXMMRegs;
2723 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2724 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2726 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2728 if (!ArgXMMs.empty()) {
2729 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2730 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2731 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2732 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2733 LiveXMMRegs.push_back(
2734 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2739 // Get to the caller-allocated home save location. Add 8 to account
2740 // for the return address.
2741 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2742 FuncInfo->setRegSaveFrameIndex(
2743 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2744 // Fixup to set vararg frame on shadow area (4 x i64).
2746 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2748 // For X86-64, if there are vararg parameters that are passed via
2749 // registers, then we must store them to their spots on the stack so
2750 // they may be loaded by deferencing the result of va_next.
2751 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2752 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2753 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2754 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2757 // Store the integer parameter registers.
2758 SmallVector<SDValue, 8> MemOps;
2759 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2760 getPointerTy(DAG.getDataLayout()));
2761 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2762 for (SDValue Val : LiveGPRs) {
2763 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2764 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2766 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2767 MachinePointerInfo::getFixedStack(
2768 DAG.getMachineFunction(),
2769 FuncInfo->getRegSaveFrameIndex(), Offset),
2771 MemOps.push_back(Store);
2775 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2776 // Now store the XMM (fp + vector) parameter registers.
2777 SmallVector<SDValue, 12> SaveXMMOps;
2778 SaveXMMOps.push_back(Chain);
2779 SaveXMMOps.push_back(ALVal);
2780 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2781 FuncInfo->getRegSaveFrameIndex(), dl));
2782 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2783 FuncInfo->getVarArgsFPOffset(), dl));
2784 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2786 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2787 MVT::Other, SaveXMMOps));
2790 if (!MemOps.empty())
2791 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2794 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2795 // Find the largest legal vector type.
2796 MVT VecVT = MVT::Other;
2797 // FIXME: Only some x86_32 calling conventions support AVX512.
2798 if (Subtarget->hasAVX512() &&
2799 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2800 CallConv == CallingConv::Intel_OCL_BI)))
2801 VecVT = MVT::v16f32;
2802 else if (Subtarget->hasAVX())
2804 else if (Subtarget->hasSSE2())
2807 // We forward some GPRs and some vector types.
2808 SmallVector<MVT, 2> RegParmTypes;
2809 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2810 RegParmTypes.push_back(IntVT);
2811 if (VecVT != MVT::Other)
2812 RegParmTypes.push_back(VecVT);
2814 // Compute the set of forwarded registers. The rest are scratch.
2815 SmallVectorImpl<ForwardedRegister> &Forwards =
2816 FuncInfo->getForwardedMustTailRegParms();
2817 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2819 // Conservatively forward AL on x86_64, since it might be used for varargs.
2820 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2821 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2822 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2825 // Copy all forwards from physical to virtual registers.
2826 for (ForwardedRegister &F : Forwards) {
2827 // FIXME: Can we use a less constrained schedule?
2828 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2829 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2830 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2834 // Some CCs need callee pop.
2835 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2836 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2837 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2839 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2840 // If this is an sret function, the return should pop the hidden pointer.
2841 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2842 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2843 argsAreStructReturn(Ins) == StackStructReturn)
2844 FuncInfo->setBytesToPopOnReturn(4);
2848 // RegSaveFrameIndex is X86-64 only.
2849 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2850 if (CallConv == CallingConv::X86_FastCall ||
2851 CallConv == CallingConv::X86_ThisCall)
2852 // fastcc functions can't have varargs.
2853 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2856 FuncInfo->setArgumentStackSize(StackSize);
2858 if (IsWinEHParent) {
2860 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2861 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2862 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2863 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2864 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2865 MachinePointerInfo::getFixedStack(
2866 DAG.getMachineFunction(), UnwindHelpFI),
2867 /*isVolatile=*/true,
2868 /*isNonTemporal=*/false, /*Alignment=*/0);
2870 // Functions using Win32 EH are considered to have opaque SP adjustments
2871 // to force local variables to be addressed from the frame or base
2873 MFI->setHasOpaqueSPAdjustment(true);
2881 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2882 SDValue StackPtr, SDValue Arg,
2883 SDLoc dl, SelectionDAG &DAG,
2884 const CCValAssign &VA,
2885 ISD::ArgFlagsTy Flags) const {
2886 unsigned LocMemOffset = VA.getLocMemOffset();
2887 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2888 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2890 if (Flags.isByVal())
2891 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2893 return DAG.getStore(
2894 Chain, dl, Arg, PtrOff,
2895 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2899 /// Emit a load of return address if tail call
2900 /// optimization is performed and it is required.
2902 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2903 SDValue &OutRetAddr, SDValue Chain,
2904 bool IsTailCall, bool Is64Bit,
2905 int FPDiff, SDLoc dl) const {
2906 // Adjust the Return address stack slot.
2907 EVT VT = getPointerTy(DAG.getDataLayout());
2908 OutRetAddr = getReturnAddressFrameIndex(DAG);
2910 // Load the "old" Return address.
2911 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2912 false, false, false, 0);
2913 return SDValue(OutRetAddr.getNode(), 1);
2916 /// Emit a store of the return address if tail call
2917 /// optimization is performed and it is required (FPDiff!=0).
2918 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2919 SDValue Chain, SDValue RetAddrFrIdx,
2920 EVT PtrVT, unsigned SlotSize,
2921 int FPDiff, SDLoc dl) {
2922 // Store the return address to the appropriate stack slot.
2923 if (!FPDiff) return Chain;
2924 // Calculate the new stack slot for the return address.
2925 int NewReturnAddrFI =
2926 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2928 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2929 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2930 MachinePointerInfo::getFixedStack(
2931 DAG.getMachineFunction(), NewReturnAddrFI),
2936 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2937 /// operation of specified width.
2938 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2940 unsigned NumElems = VT.getVectorNumElements();
2941 SmallVector<int, 8> Mask;
2942 Mask.push_back(NumElems);
2943 for (unsigned i = 1; i != NumElems; ++i)
2945 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2949 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2950 SmallVectorImpl<SDValue> &InVals) const {
2951 SelectionDAG &DAG = CLI.DAG;
2953 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2954 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2955 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2956 SDValue Chain = CLI.Chain;
2957 SDValue Callee = CLI.Callee;
2958 CallingConv::ID CallConv = CLI.CallConv;
2959 bool &isTailCall = CLI.IsTailCall;
2960 bool isVarArg = CLI.IsVarArg;
2962 MachineFunction &MF = DAG.getMachineFunction();
2963 bool Is64Bit = Subtarget->is64Bit();
2964 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2965 StructReturnType SR = callIsStructReturn(Outs);
2966 bool IsSibcall = false;
2967 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2968 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2970 if (Attr.getValueAsString() == "true")
2973 if (Subtarget->isPICStyleGOT() &&
2974 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2975 // If we are using a GOT, disable tail calls to external symbols with
2976 // default visibility. Tail calling such a symbol requires using a GOT
2977 // relocation, which forces early binding of the symbol. This breaks code
2978 // that require lazy function symbol resolution. Using musttail or
2979 // GuaranteedTailCallOpt will override this.
2980 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2981 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2982 G->getGlobal()->hasDefaultVisibility()))
2986 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2988 // Force this to be a tail call. The verifier rules are enough to ensure
2989 // that we can lower this successfully without moving the return address
2992 } else if (isTailCall) {
2993 // Check if it's really possible to do a tail call.
2994 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2995 isVarArg, SR != NotStructReturn,
2996 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2997 Outs, OutVals, Ins, DAG);
2999 // Sibcalls are automatically detected tailcalls which do not require
3001 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3008 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
3009 "Var args not supported with calling convention fastcc, ghc or hipe");
3011 // Analyze operands of the call, assigning locations to each operand.
3012 SmallVector<CCValAssign, 16> ArgLocs;
3013 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3015 // Allocate shadow area for Win64
3017 CCInfo.AllocateStack(32, 8);
3019 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3021 // Get a count of how many bytes are to be pushed on the stack.
3022 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3024 // This is a sibcall. The memory operands are available in caller's
3025 // own caller's stack.
3027 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3028 IsTailCallConvention(CallConv))
3029 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3032 if (isTailCall && !IsSibcall && !IsMustTail) {
3033 // Lower arguments at fp - stackoffset + fpdiff.
3034 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3036 FPDiff = NumBytesCallerPushed - NumBytes;
3038 // Set the delta of movement of the returnaddr stackslot.
3039 // But only set if delta is greater than previous delta.
3040 if (FPDiff < X86Info->getTCReturnAddrDelta())
3041 X86Info->setTCReturnAddrDelta(FPDiff);
3044 unsigned NumBytesToPush = NumBytes;
3045 unsigned NumBytesToPop = NumBytes;
3047 // If we have an inalloca argument, all stack space has already been allocated
3048 // for us and be right at the top of the stack. We don't support multiple
3049 // arguments passed in memory when using inalloca.
3050 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3052 if (!ArgLocs.back().isMemLoc())
3053 report_fatal_error("cannot use inalloca attribute on a register "
3055 if (ArgLocs.back().getLocMemOffset() != 0)
3056 report_fatal_error("any parameter with the inalloca attribute must be "
3057 "the only memory argument");
3061 Chain = DAG.getCALLSEQ_START(
3062 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3064 SDValue RetAddrFrIdx;
3065 // Load return address for tail calls.
3066 if (isTailCall && FPDiff)
3067 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3068 Is64Bit, FPDiff, dl);
3070 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3071 SmallVector<SDValue, 8> MemOpChains;
3074 // Walk the register/memloc assignments, inserting copies/loads. In the case
3075 // of tail call optimization arguments are handle later.
3076 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3077 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3078 // Skip inalloca arguments, they have already been written.
3079 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3080 if (Flags.isInAlloca())
3083 CCValAssign &VA = ArgLocs[i];
3084 EVT RegVT = VA.getLocVT();
3085 SDValue Arg = OutVals[i];
3086 bool isByVal = Flags.isByVal();
3088 // Promote the value if needed.
3089 switch (VA.getLocInfo()) {
3090 default: llvm_unreachable("Unknown loc info!");
3091 case CCValAssign::Full: break;
3092 case CCValAssign::SExt:
3093 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3095 case CCValAssign::ZExt:
3096 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3098 case CCValAssign::AExt:
3099 if (Arg.getValueType().isVector() &&
3100 Arg.getValueType().getScalarType() == MVT::i1)
3101 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3102 else if (RegVT.is128BitVector()) {
3103 // Special case: passing MMX values in XMM registers.
3104 Arg = DAG.getBitcast(MVT::i64, Arg);
3105 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3106 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3108 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3110 case CCValAssign::BCvt:
3111 Arg = DAG.getBitcast(RegVT, Arg);
3113 case CCValAssign::Indirect: {
3114 // Store the argument.
3115 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3116 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3117 Chain = DAG.getStore(
3118 Chain, dl, Arg, SpillSlot,
3119 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3126 if (VA.isRegLoc()) {
3127 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3128 if (isVarArg && IsWin64) {
3129 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3130 // shadow reg if callee is a varargs function.
3131 unsigned ShadowReg = 0;
3132 switch (VA.getLocReg()) {
3133 case X86::XMM0: ShadowReg = X86::RCX; break;
3134 case X86::XMM1: ShadowReg = X86::RDX; break;
3135 case X86::XMM2: ShadowReg = X86::R8; break;
3136 case X86::XMM3: ShadowReg = X86::R9; break;
3139 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3141 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3142 assert(VA.isMemLoc());
3143 if (!StackPtr.getNode())
3144 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3145 getPointerTy(DAG.getDataLayout()));
3146 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3147 dl, DAG, VA, Flags));
3151 if (!MemOpChains.empty())
3152 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3154 if (Subtarget->isPICStyleGOT()) {
3155 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3158 RegsToPass.push_back(std::make_pair(
3159 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3160 getPointerTy(DAG.getDataLayout()))));
3162 // If we are tail calling and generating PIC/GOT style code load the
3163 // address of the callee into ECX. The value in ecx is used as target of
3164 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3165 // for tail calls on PIC/GOT architectures. Normally we would just put the
3166 // address of GOT into ebx and then call target@PLT. But for tail calls
3167 // ebx would be restored (since ebx is callee saved) before jumping to the
3170 // Note: The actual moving to ECX is done further down.
3171 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3172 if (G && !G->getGlobal()->hasLocalLinkage() &&
3173 G->getGlobal()->hasDefaultVisibility())
3174 Callee = LowerGlobalAddress(Callee, DAG);
3175 else if (isa<ExternalSymbolSDNode>(Callee))
3176 Callee = LowerExternalSymbol(Callee, DAG);
3180 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3181 // From AMD64 ABI document:
3182 // For calls that may call functions that use varargs or stdargs
3183 // (prototype-less calls or calls to functions containing ellipsis (...) in
3184 // the declaration) %al is used as hidden argument to specify the number
3185 // of SSE registers used. The contents of %al do not need to match exactly
3186 // the number of registers, but must be an ubound on the number of SSE
3187 // registers used and is in the range 0 - 8 inclusive.
3189 // Count the number of XMM registers allocated.
3190 static const MCPhysReg XMMArgRegs[] = {
3191 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3192 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3194 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3195 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3196 && "SSE registers cannot be used when SSE is disabled");
3198 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3199 DAG.getConstant(NumXMMRegs, dl,
3203 if (isVarArg && IsMustTail) {
3204 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3205 for (const auto &F : Forwards) {
3206 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3207 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3211 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3212 // don't need this because the eligibility check rejects calls that require
3213 // shuffling arguments passed in memory.
3214 if (!IsSibcall && isTailCall) {
3215 // Force all the incoming stack arguments to be loaded from the stack
3216 // before any new outgoing arguments are stored to the stack, because the
3217 // outgoing stack slots may alias the incoming argument stack slots, and
3218 // the alias isn't otherwise explicit. This is slightly more conservative
3219 // than necessary, because it means that each store effectively depends
3220 // on every argument instead of just those arguments it would clobber.
3221 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3223 SmallVector<SDValue, 8> MemOpChains2;
3226 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3227 CCValAssign &VA = ArgLocs[i];
3230 assert(VA.isMemLoc());
3231 SDValue Arg = OutVals[i];
3232 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3233 // Skip inalloca arguments. They don't require any work.
3234 if (Flags.isInAlloca())
3236 // Create frame index.
3237 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3238 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3239 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3240 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3242 if (Flags.isByVal()) {
3243 // Copy relative to framepointer.
3244 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3245 if (!StackPtr.getNode())
3246 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3247 getPointerTy(DAG.getDataLayout()));
3248 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3251 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3255 // Store relative to framepointer.
3256 MemOpChains2.push_back(DAG.getStore(
3257 ArgChain, dl, Arg, FIN,
3258 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3263 if (!MemOpChains2.empty())
3264 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3266 // Store the return address to the appropriate stack slot.
3267 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3268 getPointerTy(DAG.getDataLayout()),
3269 RegInfo->getSlotSize(), FPDiff, dl);
3272 // Build a sequence of copy-to-reg nodes chained together with token chain
3273 // and flag operands which copy the outgoing args into registers.
3275 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3276 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3277 RegsToPass[i].second, InFlag);
3278 InFlag = Chain.getValue(1);
3281 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3282 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3283 // In the 64-bit large code model, we have to make all calls
3284 // through a register, since the call instruction's 32-bit
3285 // pc-relative offset may not be large enough to hold the whole
3287 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3288 // If the callee is a GlobalAddress node (quite common, every direct call
3289 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3291 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3293 // We should use extra load for direct calls to dllimported functions in
3295 const GlobalValue *GV = G->getGlobal();
3296 if (!GV->hasDLLImportStorageClass()) {
3297 unsigned char OpFlags = 0;
3298 bool ExtraLoad = false;
3299 unsigned WrapperKind = ISD::DELETED_NODE;
3301 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3302 // external symbols most go through the PLT in PIC mode. If the symbol
3303 // has hidden or protected visibility, or if it is static or local, then
3304 // we don't need to use the PLT - we can directly call it.
3305 if (Subtarget->isTargetELF() &&
3306 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3307 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3308 OpFlags = X86II::MO_PLT;
3309 } else if (Subtarget->isPICStyleStubAny() &&
3310 !GV->isStrongDefinitionForLinker() &&
3311 (!Subtarget->getTargetTriple().isMacOSX() ||
3312 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3313 // PC-relative references to external symbols should go through $stub,
3314 // unless we're building with the leopard linker or later, which
3315 // automatically synthesizes these stubs.
3316 OpFlags = X86II::MO_DARWIN_STUB;
3317 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3318 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3319 // If the function is marked as non-lazy, generate an indirect call
3320 // which loads from the GOT directly. This avoids runtime overhead
3321 // at the cost of eager binding (and one extra byte of encoding).
3322 OpFlags = X86II::MO_GOTPCREL;
3323 WrapperKind = X86ISD::WrapperRIP;
3327 Callee = DAG.getTargetGlobalAddress(
3328 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3330 // Add a wrapper if needed.
3331 if (WrapperKind != ISD::DELETED_NODE)
3332 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3333 getPointerTy(DAG.getDataLayout()), Callee);
3334 // Add extra indirection if needed.
3336 Callee = DAG.getLoad(
3337 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3338 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3341 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3342 unsigned char OpFlags = 0;
3344 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3345 // external symbols should go through the PLT.
3346 if (Subtarget->isTargetELF() &&
3347 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3348 OpFlags = X86II::MO_PLT;
3349 } else if (Subtarget->isPICStyleStubAny() &&
3350 (!Subtarget->getTargetTriple().isMacOSX() ||
3351 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3352 // PC-relative references to external symbols should go through $stub,
3353 // unless we're building with the leopard linker or later, which
3354 // automatically synthesizes these stubs.
3355 OpFlags = X86II::MO_DARWIN_STUB;
3358 Callee = DAG.getTargetExternalSymbol(
3359 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3360 } else if (Subtarget->isTarget64BitILP32() &&
3361 Callee->getValueType(0) == MVT::i32) {
3362 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3363 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3366 // Returns a chain & a flag for retval copy to use.
3367 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3368 SmallVector<SDValue, 8> Ops;
3370 if (!IsSibcall && isTailCall) {
3371 Chain = DAG.getCALLSEQ_END(Chain,
3372 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3373 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3374 InFlag = Chain.getValue(1);
3377 Ops.push_back(Chain);
3378 Ops.push_back(Callee);
3381 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3383 // Add argument registers to the end of the list so that they are known live
3385 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3386 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3387 RegsToPass[i].second.getValueType()));
3389 // Add a register mask operand representing the call-preserved registers.
3390 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3391 assert(Mask && "Missing call preserved mask for calling convention");
3393 // If this is an invoke in a 32-bit function using an MSVC personality, assume
3394 // the function clobbers all registers. If an exception is thrown, the runtime
3395 // will not restore CSRs.
3396 // FIXME: Model this more precisely so that we can register allocate across
3397 // the normal edge and spill and fill across the exceptional edge.
3398 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3399 const Function *CallerFn = MF.getFunction();
3400 EHPersonality Pers =
3401 CallerFn->hasPersonalityFn()
3402 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3403 : EHPersonality::Unknown;
3404 if (isMSVCEHPersonality(Pers))
3405 Mask = RegInfo->getNoPreservedMask();
3408 Ops.push_back(DAG.getRegisterMask(Mask));
3410 if (InFlag.getNode())
3411 Ops.push_back(InFlag);
3415 //// If this is the first return lowered for this function, add the regs
3416 //// to the liveout set for the function.
3417 // This isn't right, although it's probably harmless on x86; liveouts
3418 // should be computed from returns not tail calls. Consider a void
3419 // function making a tail call to a function returning int.
3420 MF.getFrameInfo()->setHasTailCall();
3421 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3424 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3425 InFlag = Chain.getValue(1);
3427 // Create the CALLSEQ_END node.
3428 unsigned NumBytesForCalleeToPop;
3429 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3430 DAG.getTarget().Options.GuaranteedTailCallOpt))
3431 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3432 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3433 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3434 SR == StackStructReturn)
3435 // If this is a call to a struct-return function, the callee
3436 // pops the hidden struct pointer, so we have to push it back.
3437 // This is common for Darwin/X86, Linux & Mingw32 targets.
3438 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3439 NumBytesForCalleeToPop = 4;
3441 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3443 // Returns a flag for retval copy to use.
3445 Chain = DAG.getCALLSEQ_END(Chain,
3446 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3447 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3450 InFlag = Chain.getValue(1);
3453 // Handle result values, copying them out of physregs into vregs that we
3455 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3456 Ins, dl, DAG, InVals);
3459 //===----------------------------------------------------------------------===//
3460 // Fast Calling Convention (tail call) implementation
3461 //===----------------------------------------------------------------------===//
3463 // Like std call, callee cleans arguments, convention except that ECX is
3464 // reserved for storing the tail called function address. Only 2 registers are
3465 // free for argument passing (inreg). Tail call optimization is performed
3467 // * tailcallopt is enabled
3468 // * caller/callee are fastcc
3469 // On X86_64 architecture with GOT-style position independent code only local
3470 // (within module) calls are supported at the moment.
3471 // To keep the stack aligned according to platform abi the function
3472 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3473 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3474 // If a tail called function callee has more arguments than the caller the
3475 // caller needs to make sure that there is room to move the RETADDR to. This is
3476 // achieved by reserving an area the size of the argument delta right after the
3477 // original RETADDR, but before the saved framepointer or the spilled registers
3478 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3490 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3493 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3494 SelectionDAG& DAG) const {
3495 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3496 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3497 unsigned StackAlignment = TFI.getStackAlignment();
3498 uint64_t AlignMask = StackAlignment - 1;
3499 int64_t Offset = StackSize;
3500 unsigned SlotSize = RegInfo->getSlotSize();
3501 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3502 // Number smaller than 12 so just add the difference.
3503 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3505 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3506 Offset = ((~AlignMask) & Offset) + StackAlignment +
3507 (StackAlignment-SlotSize);
3512 /// Return true if the given stack call argument is already available in the
3513 /// same position (relatively) of the caller's incoming argument stack.
3515 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3516 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3517 const X86InstrInfo *TII) {
3518 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3520 if (Arg.getOpcode() == ISD::CopyFromReg) {
3521 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3522 if (!TargetRegisterInfo::isVirtualRegister(VR))
3524 MachineInstr *Def = MRI->getVRegDef(VR);
3527 if (!Flags.isByVal()) {
3528 if (!TII->isLoadFromStackSlot(Def, FI))
3531 unsigned Opcode = Def->getOpcode();
3532 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3533 Opcode == X86::LEA64_32r) &&
3534 Def->getOperand(1).isFI()) {
3535 FI = Def->getOperand(1).getIndex();
3536 Bytes = Flags.getByValSize();
3540 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3541 if (Flags.isByVal())
3542 // ByVal argument is passed in as a pointer but it's now being
3543 // dereferenced. e.g.
3544 // define @foo(%struct.X* %A) {
3545 // tail call @bar(%struct.X* byval %A)
3548 SDValue Ptr = Ld->getBasePtr();
3549 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3552 FI = FINode->getIndex();
3553 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3554 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3555 FI = FINode->getIndex();
3556 Bytes = Flags.getByValSize();
3560 assert(FI != INT_MAX);
3561 if (!MFI->isFixedObjectIndex(FI))
3563 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3566 /// Check whether the call is eligible for tail call optimization. Targets
3567 /// that want to do tail call optimization should implement this function.
3568 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3569 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3570 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3571 const SmallVectorImpl<ISD::OutputArg> &Outs,
3572 const SmallVectorImpl<SDValue> &OutVals,
3573 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3574 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3577 // If -tailcallopt is specified, make fastcc functions tail-callable.
3578 const MachineFunction &MF = DAG.getMachineFunction();
3579 const Function *CallerF = MF.getFunction();
3581 // If the function return type is x86_fp80 and the callee return type is not,
3582 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3583 // perform a tailcall optimization here.
3584 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3587 CallingConv::ID CallerCC = CallerF->getCallingConv();
3588 bool CCMatch = CallerCC == CalleeCC;
3589 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3590 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3592 // Win64 functions have extra shadow space for argument homing. Don't do the
3593 // sibcall if the caller and callee have mismatched expectations for this
3595 if (IsCalleeWin64 != IsCallerWin64)
3598 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3599 if (IsTailCallConvention(CalleeCC) && CCMatch)
3604 // Look for obvious safe cases to perform tail call optimization that do not
3605 // require ABI changes. This is what gcc calls sibcall.
3607 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3608 // emit a special epilogue.
3609 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3610 if (RegInfo->needsStackRealignment(MF))
3613 // Also avoid sibcall optimization if either caller or callee uses struct
3614 // return semantics.
3615 if (isCalleeStructRet || isCallerStructRet)
3618 // An stdcall/thiscall caller is expected to clean up its arguments; the
3619 // callee isn't going to do that.
3620 // FIXME: this is more restrictive than needed. We could produce a tailcall
3621 // when the stack adjustment matches. For example, with a thiscall that takes
3622 // only one argument.
3623 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3624 CallerCC == CallingConv::X86_ThisCall))
3627 // Do not sibcall optimize vararg calls unless all arguments are passed via
3629 if (isVarArg && !Outs.empty()) {
3631 // Optimizing for varargs on Win64 is unlikely to be safe without
3632 // additional testing.
3633 if (IsCalleeWin64 || IsCallerWin64)
3636 SmallVector<CCValAssign, 16> ArgLocs;
3637 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3640 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3641 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3642 if (!ArgLocs[i].isRegLoc())
3646 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3647 // stack. Therefore, if it's not used by the call it is not safe to optimize
3648 // this into a sibcall.
3649 bool Unused = false;
3650 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3657 SmallVector<CCValAssign, 16> RVLocs;
3658 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3660 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3661 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3662 CCValAssign &VA = RVLocs[i];
3663 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3668 // If the calling conventions do not match, then we'd better make sure the
3669 // results are returned in the same way as what the caller expects.
3671 SmallVector<CCValAssign, 16> RVLocs1;
3672 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3674 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3676 SmallVector<CCValAssign, 16> RVLocs2;
3677 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3679 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3681 if (RVLocs1.size() != RVLocs2.size())
3683 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3684 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3686 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3688 if (RVLocs1[i].isRegLoc()) {
3689 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3692 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3698 // If the callee takes no arguments then go on to check the results of the
3700 if (!Outs.empty()) {
3701 // Check if stack adjustment is needed. For now, do not do this if any
3702 // argument is passed on the stack.
3703 SmallVector<CCValAssign, 16> ArgLocs;
3704 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3707 // Allocate shadow area for Win64
3709 CCInfo.AllocateStack(32, 8);
3711 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3712 if (CCInfo.getNextStackOffset()) {
3713 MachineFunction &MF = DAG.getMachineFunction();
3714 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3717 // Check if the arguments are already laid out in the right way as
3718 // the caller's fixed stack objects.
3719 MachineFrameInfo *MFI = MF.getFrameInfo();
3720 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3721 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3722 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3723 CCValAssign &VA = ArgLocs[i];
3724 SDValue Arg = OutVals[i];
3725 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3726 if (VA.getLocInfo() == CCValAssign::Indirect)
3728 if (!VA.isRegLoc()) {
3729 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3736 // If the tailcall address may be in a register, then make sure it's
3737 // possible to register allocate for it. In 32-bit, the call address can
3738 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3739 // callee-saved registers are restored. These happen to be the same
3740 // registers used to pass 'inreg' arguments so watch out for those.
3741 if (!Subtarget->is64Bit() &&
3742 ((!isa<GlobalAddressSDNode>(Callee) &&
3743 !isa<ExternalSymbolSDNode>(Callee)) ||
3744 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3745 unsigned NumInRegs = 0;
3746 // In PIC we need an extra register to formulate the address computation
3748 unsigned MaxInRegs =
3749 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3751 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3752 CCValAssign &VA = ArgLocs[i];
3755 unsigned Reg = VA.getLocReg();
3758 case X86::EAX: case X86::EDX: case X86::ECX:
3759 if (++NumInRegs == MaxInRegs)
3771 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3772 const TargetLibraryInfo *libInfo) const {
3773 return X86::createFastISel(funcInfo, libInfo);
3776 //===----------------------------------------------------------------------===//
3777 // Other Lowering Hooks
3778 //===----------------------------------------------------------------------===//
3780 static bool MayFoldLoad(SDValue Op) {
3781 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3784 static bool MayFoldIntoStore(SDValue Op) {
3785 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3788 static bool isTargetShuffle(unsigned Opcode) {
3790 default: return false;
3791 case X86ISD::BLENDI:
3792 case X86ISD::PSHUFB:
3793 case X86ISD::PSHUFD:
3794 case X86ISD::PSHUFHW:
3795 case X86ISD::PSHUFLW:
3797 case X86ISD::PALIGNR:
3798 case X86ISD::MOVLHPS:
3799 case X86ISD::MOVLHPD:
3800 case X86ISD::MOVHLPS:
3801 case X86ISD::MOVLPS:
3802 case X86ISD::MOVLPD:
3803 case X86ISD::MOVSHDUP:
3804 case X86ISD::MOVSLDUP:
3805 case X86ISD::MOVDDUP:
3808 case X86ISD::UNPCKL:
3809 case X86ISD::UNPCKH:
3810 case X86ISD::VPERMILPI:
3811 case X86ISD::VPERM2X128:
3812 case X86ISD::VPERMI:
3813 case X86ISD::VPERMV:
3814 case X86ISD::VPERMV3:
3819 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3820 SDValue V1, unsigned TargetMask,
3821 SelectionDAG &DAG) {
3823 default: llvm_unreachable("Unknown x86 shuffle node");
3824 case X86ISD::PSHUFD:
3825 case X86ISD::PSHUFHW:
3826 case X86ISD::PSHUFLW:
3827 case X86ISD::VPERMILPI:
3828 case X86ISD::VPERMI:
3829 return DAG.getNode(Opc, dl, VT, V1,
3830 DAG.getConstant(TargetMask, dl, MVT::i8));
3834 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3835 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3837 default: llvm_unreachable("Unknown x86 shuffle node");
3838 case X86ISD::MOVLHPS:
3839 case X86ISD::MOVLHPD:
3840 case X86ISD::MOVHLPS:
3841 case X86ISD::MOVLPS:
3842 case X86ISD::MOVLPD:
3845 case X86ISD::UNPCKL:
3846 case X86ISD::UNPCKH:
3847 return DAG.getNode(Opc, dl, VT, V1, V2);
3851 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3852 MachineFunction &MF = DAG.getMachineFunction();
3853 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3854 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3855 int ReturnAddrIndex = FuncInfo->getRAIndex();
3857 if (ReturnAddrIndex == 0) {
3858 // Set up a frame object for the return address.
3859 unsigned SlotSize = RegInfo->getSlotSize();
3860 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3863 FuncInfo->setRAIndex(ReturnAddrIndex);
3866 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3869 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3870 bool hasSymbolicDisplacement) {
3871 // Offset should fit into 32 bit immediate field.
3872 if (!isInt<32>(Offset))
3875 // If we don't have a symbolic displacement - we don't have any extra
3877 if (!hasSymbolicDisplacement)
3880 // FIXME: Some tweaks might be needed for medium code model.
3881 if (M != CodeModel::Small && M != CodeModel::Kernel)
3884 // For small code model we assume that latest object is 16MB before end of 31
3885 // bits boundary. We may also accept pretty large negative constants knowing
3886 // that all objects are in the positive half of address space.
3887 if (M == CodeModel::Small && Offset < 16*1024*1024)
3890 // For kernel code model we know that all object resist in the negative half
3891 // of 32bits address space. We may not accept negative offsets, since they may
3892 // be just off and we may accept pretty large positive ones.
3893 if (M == CodeModel::Kernel && Offset >= 0)
3899 /// Determines whether the callee is required to pop its own arguments.
3900 /// Callee pop is necessary to support tail calls.
3901 bool X86::isCalleePop(CallingConv::ID CallingConv,
3902 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3904 if (IsTailCallConvention(CallingConv))
3905 return IsVarArg ? false : TailCallOpt;
3907 switch (CallingConv) {
3910 case CallingConv::X86_StdCall:
3911 case CallingConv::X86_FastCall:
3912 case CallingConv::X86_ThisCall:
3917 /// \brief Return true if the condition is an unsigned comparison operation.
3918 static bool isX86CCUnsigned(unsigned X86CC) {
3920 default: llvm_unreachable("Invalid integer condition!");
3921 case X86::COND_E: return true;
3922 case X86::COND_G: return false;
3923 case X86::COND_GE: return false;
3924 case X86::COND_L: return false;
3925 case X86::COND_LE: return false;
3926 case X86::COND_NE: return true;
3927 case X86::COND_B: return true;
3928 case X86::COND_A: return true;
3929 case X86::COND_BE: return true;
3930 case X86::COND_AE: return true;
3932 llvm_unreachable("covered switch fell through?!");
3935 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3936 /// condition code, returning the condition code and the LHS/RHS of the
3937 /// comparison to make.
3938 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3939 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3941 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3942 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3943 // X > -1 -> X == 0, jump !sign.
3944 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3945 return X86::COND_NS;
3947 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3948 // X < 0 -> X == 0, jump on sign.
3951 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3953 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3954 return X86::COND_LE;
3958 switch (SetCCOpcode) {
3959 default: llvm_unreachable("Invalid integer condition!");
3960 case ISD::SETEQ: return X86::COND_E;
3961 case ISD::SETGT: return X86::COND_G;
3962 case ISD::SETGE: return X86::COND_GE;
3963 case ISD::SETLT: return X86::COND_L;
3964 case ISD::SETLE: return X86::COND_LE;
3965 case ISD::SETNE: return X86::COND_NE;
3966 case ISD::SETULT: return X86::COND_B;
3967 case ISD::SETUGT: return X86::COND_A;
3968 case ISD::SETULE: return X86::COND_BE;
3969 case ISD::SETUGE: return X86::COND_AE;
3973 // First determine if it is required or is profitable to flip the operands.
3975 // If LHS is a foldable load, but RHS is not, flip the condition.
3976 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3977 !ISD::isNON_EXTLoad(RHS.getNode())) {
3978 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3979 std::swap(LHS, RHS);
3982 switch (SetCCOpcode) {
3988 std::swap(LHS, RHS);
3992 // On a floating point condition, the flags are set as follows:
3994 // 0 | 0 | 0 | X > Y
3995 // 0 | 0 | 1 | X < Y
3996 // 1 | 0 | 0 | X == Y
3997 // 1 | 1 | 1 | unordered
3998 switch (SetCCOpcode) {
3999 default: llvm_unreachable("Condcode should be pre-legalized away");
4001 case ISD::SETEQ: return X86::COND_E;
4002 case ISD::SETOLT: // flipped
4004 case ISD::SETGT: return X86::COND_A;
4005 case ISD::SETOLE: // flipped
4007 case ISD::SETGE: return X86::COND_AE;
4008 case ISD::SETUGT: // flipped
4010 case ISD::SETLT: return X86::COND_B;
4011 case ISD::SETUGE: // flipped
4013 case ISD::SETLE: return X86::COND_BE;
4015 case ISD::SETNE: return X86::COND_NE;
4016 case ISD::SETUO: return X86::COND_P;
4017 case ISD::SETO: return X86::COND_NP;
4019 case ISD::SETUNE: return X86::COND_INVALID;
4023 /// Is there a floating point cmov for the specific X86 condition code?
4024 /// Current x86 isa includes the following FP cmov instructions:
4025 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4026 static bool hasFPCMov(unsigned X86CC) {
4042 /// Returns true if the target can instruction select the
4043 /// specified FP immediate natively. If false, the legalizer will
4044 /// materialize the FP immediate as a load from a constant pool.
4045 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4046 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4047 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4053 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4054 ISD::LoadExtType ExtTy,
4056 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4057 // relocation target a movq or addq instruction: don't let the load shrink.
4058 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4059 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4060 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4061 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4065 /// \brief Returns true if it is beneficial to convert a load of a constant
4066 /// to just the constant itself.
4067 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4069 assert(Ty->isIntegerTy());
4071 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4072 if (BitSize == 0 || BitSize > 64)
4077 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4078 unsigned Index) const {
4079 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4082 return (Index == 0 || Index == ResVT.getVectorNumElements());
4085 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4086 // Speculate cttz only if we can directly use TZCNT.
4087 return Subtarget->hasBMI();
4090 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4091 // Speculate ctlz only if we can directly use LZCNT.
4092 return Subtarget->hasLZCNT();
4095 /// Return true if every element in Mask, beginning
4096 /// from position Pos and ending in Pos+Size is undef.
4097 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4098 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4104 /// Return true if Val is undef or if its value falls within the
4105 /// specified range (L, H].
4106 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4107 return (Val < 0) || (Val >= Low && Val < Hi);
4110 /// Val is either less than zero (undef) or equal to the specified value.
4111 static bool isUndefOrEqual(int Val, int CmpVal) {
4112 return (Val < 0 || Val == CmpVal);
4115 /// Return true if every element in Mask, beginning
4116 /// from position Pos and ending in Pos+Size, falls within the specified
4117 /// sequential range (Low, Low+Size]. or is undef.
4118 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4119 unsigned Pos, unsigned Size, int Low) {
4120 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4121 if (!isUndefOrEqual(Mask[i], Low))
4126 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4127 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4128 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4129 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4130 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4133 // The index should be aligned on a vecWidth-bit boundary.
4135 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4137 MVT VT = N->getSimpleValueType(0);
4138 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4139 bool Result = (Index * ElSize) % vecWidth == 0;
4144 /// Return true if the specified INSERT_SUBVECTOR
4145 /// operand specifies a subvector insert that is suitable for input to
4146 /// insertion of 128 or 256-bit subvectors
4147 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4148 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4149 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4151 // The index should be aligned on a vecWidth-bit boundary.
4153 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4155 MVT VT = N->getSimpleValueType(0);
4156 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4157 bool Result = (Index * ElSize) % vecWidth == 0;
4162 bool X86::isVINSERT128Index(SDNode *N) {
4163 return isVINSERTIndex(N, 128);
4166 bool X86::isVINSERT256Index(SDNode *N) {
4167 return isVINSERTIndex(N, 256);
4170 bool X86::isVEXTRACT128Index(SDNode *N) {
4171 return isVEXTRACTIndex(N, 128);
4174 bool X86::isVEXTRACT256Index(SDNode *N) {
4175 return isVEXTRACTIndex(N, 256);
4178 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4179 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4180 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4181 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4184 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4186 MVT VecVT = N->getOperand(0).getSimpleValueType();
4187 MVT ElVT = VecVT.getVectorElementType();
4189 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4190 return Index / NumElemsPerChunk;
4193 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4194 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4195 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4196 llvm_unreachable("Illegal insert subvector for VINSERT");
4199 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4201 MVT VecVT = N->getSimpleValueType(0);
4202 MVT ElVT = VecVT.getVectorElementType();
4204 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4205 return Index / NumElemsPerChunk;
4208 /// Return the appropriate immediate to extract the specified
4209 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4210 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4211 return getExtractVEXTRACTImmediate(N, 128);
4214 /// Return the appropriate immediate to extract the specified
4215 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4216 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4217 return getExtractVEXTRACTImmediate(N, 256);
4220 /// Return the appropriate immediate to insert at the specified
4221 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4222 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4223 return getInsertVINSERTImmediate(N, 128);
4226 /// Return the appropriate immediate to insert at the specified
4227 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4228 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4229 return getInsertVINSERTImmediate(N, 256);
4232 /// Returns true if Elt is a constant integer zero
4233 static bool isZero(SDValue V) {
4234 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4235 return C && C->isNullValue();
4238 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4239 bool X86::isZeroNode(SDValue Elt) {
4242 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4243 return CFP->getValueAPF().isPosZero();
4247 /// Returns a vector of specified type with all zero elements.
4248 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4249 SelectionDAG &DAG, SDLoc dl) {
4250 assert(VT.isVector() && "Expected a vector type");
4252 // Always build SSE zero vectors as <4 x i32> bitcasted
4253 // to their dest type. This ensures they get CSE'd.
4255 if (VT.is128BitVector()) { // SSE
4256 if (Subtarget->hasSSE2()) { // SSE2
4257 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4258 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4260 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4261 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4263 } else if (VT.is256BitVector()) { // AVX
4264 if (Subtarget->hasInt256()) { // AVX2
4265 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4266 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4267 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4269 // 256-bit logic and arithmetic instructions in AVX are all
4270 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4271 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4272 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4273 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4275 } else if (VT.is512BitVector()) { // AVX-512
4276 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4277 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4278 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4279 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4280 } else if (VT.getScalarType() == MVT::i1) {
4282 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4283 && "Unexpected vector type");
4284 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4285 && "Unexpected vector type");
4286 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4287 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4288 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4290 llvm_unreachable("Unexpected vector type");
4292 return DAG.getBitcast(VT, Vec);
4295 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4296 SelectionDAG &DAG, SDLoc dl,
4297 unsigned vectorWidth) {
4298 assert((vectorWidth == 128 || vectorWidth == 256) &&
4299 "Unsupported vector width");
4300 EVT VT = Vec.getValueType();
4301 EVT ElVT = VT.getVectorElementType();
4302 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4303 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4304 VT.getVectorNumElements()/Factor);
4306 // Extract from UNDEF is UNDEF.
4307 if (Vec.getOpcode() == ISD::UNDEF)
4308 return DAG.getUNDEF(ResultVT);
4310 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4311 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4313 // This is the index of the first element of the vectorWidth-bit chunk
4315 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4318 // If the input is a buildvector just emit a smaller one.
4319 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4320 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4321 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4324 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4325 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4328 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4329 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4330 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4331 /// instructions or a simple subregister reference. Idx is an index in the
4332 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4333 /// lowering EXTRACT_VECTOR_ELT operations easier.
4334 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4335 SelectionDAG &DAG, SDLoc dl) {
4336 assert((Vec.getValueType().is256BitVector() ||
4337 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4338 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4341 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4342 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4343 SelectionDAG &DAG, SDLoc dl) {
4344 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4345 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4348 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4349 unsigned IdxVal, SelectionDAG &DAG,
4350 SDLoc dl, unsigned vectorWidth) {
4351 assert((vectorWidth == 128 || vectorWidth == 256) &&
4352 "Unsupported vector width");
4353 // Inserting UNDEF is Result
4354 if (Vec.getOpcode() == ISD::UNDEF)
4356 EVT VT = Vec.getValueType();
4357 EVT ElVT = VT.getVectorElementType();
4358 EVT ResultVT = Result.getValueType();
4360 // Insert the relevant vectorWidth bits.
4361 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4363 // This is the index of the first element of the vectorWidth-bit chunk
4365 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4368 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4369 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4372 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4373 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4374 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4375 /// simple superregister reference. Idx is an index in the 128 bits
4376 /// we want. It need not be aligned to a 128-bit boundary. That makes
4377 /// lowering INSERT_VECTOR_ELT operations easier.
4378 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4379 SelectionDAG &DAG, SDLoc dl) {
4380 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4382 // For insertion into the zero index (low half) of a 256-bit vector, it is
4383 // more efficient to generate a blend with immediate instead of an insert*128.
4384 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4385 // extend the subvector to the size of the result vector. Make sure that
4386 // we are not recursing on that node by checking for undef here.
4387 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4388 Result.getOpcode() != ISD::UNDEF) {
4389 EVT ResultVT = Result.getValueType();
4390 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4391 SDValue Undef = DAG.getUNDEF(ResultVT);
4392 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4395 // The blend instruction, and therefore its mask, depend on the data type.
4396 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4397 if (ScalarType.isFloatingPoint()) {
4398 // Choose either vblendps (float) or vblendpd (double).
4399 unsigned ScalarSize = ScalarType.getSizeInBits();
4400 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4401 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4402 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4403 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4406 const X86Subtarget &Subtarget =
4407 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4409 // AVX2 is needed for 256-bit integer blend support.
4410 // Integers must be cast to 32-bit because there is only vpblendd;
4411 // vpblendw can't be used for this because it has a handicapped mask.
4413 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4414 // is still more efficient than using the wrong domain vinsertf128 that
4415 // will be created by InsertSubVector().
4416 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4418 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4419 Vec256 = DAG.getBitcast(CastVT, Vec256);
4420 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4421 return DAG.getBitcast(ResultVT, Vec256);
4424 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4427 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4428 SelectionDAG &DAG, SDLoc dl) {
4429 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4430 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4433 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4434 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4435 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4436 /// large BUILD_VECTORS.
4437 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4438 unsigned NumElems, SelectionDAG &DAG,
4440 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4441 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4444 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4445 unsigned NumElems, SelectionDAG &DAG,
4447 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4448 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4451 /// Returns a vector of specified type with all bits set.
4452 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4453 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4454 /// Then bitcast to their original type, ensuring they get CSE'd.
4455 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4456 SelectionDAG &DAG, SDLoc dl) {
4457 assert(VT.isVector() && "Expected a vector type");
4459 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4461 if (VT.is512BitVector()) {
4462 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4463 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4464 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4465 } else if (VT.is256BitVector()) {
4466 if (Subtarget->hasInt256()) { // AVX2
4467 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4468 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4470 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4471 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4473 } else if (VT.is128BitVector()) {
4474 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4476 llvm_unreachable("Unexpected vector type");
4478 return DAG.getBitcast(VT, Vec);
4481 /// Returns a vector_shuffle node for an unpackl operation.
4482 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4484 unsigned NumElems = VT.getVectorNumElements();
4485 SmallVector<int, 8> Mask;
4486 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4488 Mask.push_back(i + NumElems);
4490 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4493 /// Returns a vector_shuffle node for an unpackh operation.
4494 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4496 unsigned NumElems = VT.getVectorNumElements();
4497 SmallVector<int, 8> Mask;
4498 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4499 Mask.push_back(i + Half);
4500 Mask.push_back(i + NumElems + Half);
4502 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4505 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4506 /// This produces a shuffle where the low element of V2 is swizzled into the
4507 /// zero/undef vector, landing at element Idx.
4508 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4509 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4511 const X86Subtarget *Subtarget,
4512 SelectionDAG &DAG) {
4513 MVT VT = V2.getSimpleValueType();
4515 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4516 unsigned NumElems = VT.getVectorNumElements();
4517 SmallVector<int, 16> MaskVec;
4518 for (unsigned i = 0; i != NumElems; ++i)
4519 // If this is the insertion idx, put the low elt of V2 here.
4520 MaskVec.push_back(i == Idx ? NumElems : i);
4521 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4524 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4525 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4526 /// uses one source. Note that this will set IsUnary for shuffles which use a
4527 /// single input multiple times, and in those cases it will
4528 /// adjust the mask to only have indices within that single input.
4529 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4530 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4531 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4532 unsigned NumElems = VT.getVectorNumElements();
4536 bool IsFakeUnary = false;
4537 switch(N->getOpcode()) {
4538 case X86ISD::BLENDI:
4539 ImmN = N->getOperand(N->getNumOperands()-1);
4540 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4543 ImmN = N->getOperand(N->getNumOperands()-1);
4544 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4545 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4547 case X86ISD::UNPCKH:
4548 DecodeUNPCKHMask(VT, Mask);
4549 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4551 case X86ISD::UNPCKL:
4552 DecodeUNPCKLMask(VT, Mask);
4553 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4555 case X86ISD::MOVHLPS:
4556 DecodeMOVHLPSMask(NumElems, Mask);
4557 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4559 case X86ISD::MOVLHPS:
4560 DecodeMOVLHPSMask(NumElems, Mask);
4561 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4563 case X86ISD::PALIGNR:
4564 ImmN = N->getOperand(N->getNumOperands()-1);
4565 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4567 case X86ISD::PSHUFD:
4568 case X86ISD::VPERMILPI:
4569 ImmN = N->getOperand(N->getNumOperands()-1);
4570 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4573 case X86ISD::PSHUFHW:
4574 ImmN = N->getOperand(N->getNumOperands()-1);
4575 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4578 case X86ISD::PSHUFLW:
4579 ImmN = N->getOperand(N->getNumOperands()-1);
4580 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4583 case X86ISD::PSHUFB: {
4585 SDValue MaskNode = N->getOperand(1);
4586 while (MaskNode->getOpcode() == ISD::BITCAST)
4587 MaskNode = MaskNode->getOperand(0);
4589 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4590 // If we have a build-vector, then things are easy.
4591 EVT VT = MaskNode.getValueType();
4592 assert(VT.isVector() &&
4593 "Can't produce a non-vector with a build_vector!");
4594 if (!VT.isInteger())
4597 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4599 SmallVector<uint64_t, 32> RawMask;
4600 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4601 SDValue Op = MaskNode->getOperand(i);
4602 if (Op->getOpcode() == ISD::UNDEF) {
4603 RawMask.push_back((uint64_t)SM_SentinelUndef);
4606 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4609 APInt MaskElement = CN->getAPIntValue();
4611 // We now have to decode the element which could be any integer size and
4612 // extract each byte of it.
4613 for (int j = 0; j < NumBytesPerElement; ++j) {
4614 // Note that this is x86 and so always little endian: the low byte is
4615 // the first byte of the mask.
4616 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4617 MaskElement = MaskElement.lshr(8);
4620 DecodePSHUFBMask(RawMask, Mask);
4624 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4628 SDValue Ptr = MaskLoad->getBasePtr();
4629 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4630 Ptr->getOpcode() == X86ISD::WrapperRIP)
4631 Ptr = Ptr->getOperand(0);
4633 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4634 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4637 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4638 DecodePSHUFBMask(C, Mask);
4646 case X86ISD::VPERMI:
4647 ImmN = N->getOperand(N->getNumOperands()-1);
4648 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4653 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4655 case X86ISD::VPERM2X128:
4656 ImmN = N->getOperand(N->getNumOperands()-1);
4657 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4658 if (Mask.empty()) return false;
4659 // Mask only contains negative index if an element is zero.
4660 if (std::any_of(Mask.begin(), Mask.end(),
4661 [](int M){ return M == SM_SentinelZero; }))
4664 case X86ISD::MOVSLDUP:
4665 DecodeMOVSLDUPMask(VT, Mask);
4668 case X86ISD::MOVSHDUP:
4669 DecodeMOVSHDUPMask(VT, Mask);
4672 case X86ISD::MOVDDUP:
4673 DecodeMOVDDUPMask(VT, Mask);
4676 case X86ISD::MOVLHPD:
4677 case X86ISD::MOVLPD:
4678 case X86ISD::MOVLPS:
4679 // Not yet implemented
4681 case X86ISD::VPERMV: {
4683 SDValue MaskNode = N->getOperand(0);
4684 while (MaskNode->getOpcode() == ISD::BITCAST)
4685 MaskNode = MaskNode->getOperand(0);
4687 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4688 SmallVector<uint64_t, 32> RawMask;
4689 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4690 // If we have a build-vector, then things are easy.
4691 assert(MaskNode.getValueType().isInteger() &&
4692 MaskNode.getValueType().getVectorNumElements() ==
4693 VT.getVectorNumElements());
4695 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4696 SDValue Op = MaskNode->getOperand(i);
4697 if (Op->getOpcode() == ISD::UNDEF)
4698 RawMask.push_back((uint64_t)SM_SentinelUndef);
4699 else if (isa<ConstantSDNode>(Op)) {
4700 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4701 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4705 DecodeVPERMVMask(RawMask, Mask);
4708 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4709 unsigned NumEltsInMask = MaskNode->getNumOperands();
4710 MaskNode = MaskNode->getOperand(0);
4711 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4713 APInt MaskEltValue = CN->getAPIntValue();
4714 for (unsigned i = 0; i < NumEltsInMask; ++i)
4715 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4716 DecodeVPERMVMask(RawMask, Mask);
4719 // It may be a scalar load
4722 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4726 SDValue Ptr = MaskLoad->getBasePtr();
4727 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4728 Ptr->getOpcode() == X86ISD::WrapperRIP)
4729 Ptr = Ptr->getOperand(0);
4731 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4732 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4735 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4737 DecodeVPERMVMask(C, VT, Mask);
4744 case X86ISD::VPERMV3: {
4746 SDValue MaskNode = N->getOperand(1);
4747 while (MaskNode->getOpcode() == ISD::BITCAST)
4748 MaskNode = MaskNode->getOperand(1);
4750 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4751 // If we have a build-vector, then things are easy.
4752 assert(MaskNode.getValueType().isInteger() &&
4753 MaskNode.getValueType().getVectorNumElements() ==
4754 VT.getVectorNumElements());
4756 SmallVector<uint64_t, 32> RawMask;
4757 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4759 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4760 SDValue Op = MaskNode->getOperand(i);
4761 if (Op->getOpcode() == ISD::UNDEF)
4762 RawMask.push_back((uint64_t)SM_SentinelUndef);
4764 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4767 APInt MaskElement = CN->getAPIntValue();
4768 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4771 DecodeVPERMV3Mask(RawMask, Mask);
4775 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4779 SDValue Ptr = MaskLoad->getBasePtr();
4780 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4781 Ptr->getOpcode() == X86ISD::WrapperRIP)
4782 Ptr = Ptr->getOperand(0);
4784 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4785 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4788 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4790 DecodeVPERMV3Mask(C, VT, Mask);
4797 default: llvm_unreachable("unknown target shuffle node");
4800 // If we have a fake unary shuffle, the shuffle mask is spread across two
4801 // inputs that are actually the same node. Re-map the mask to always point
4802 // into the first input.
4805 if (M >= (int)Mask.size())
4811 /// Returns the scalar element that will make up the ith
4812 /// element of the result of the vector shuffle.
4813 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4816 return SDValue(); // Limit search depth.
4818 SDValue V = SDValue(N, 0);
4819 EVT VT = V.getValueType();
4820 unsigned Opcode = V.getOpcode();
4822 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4823 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4824 int Elt = SV->getMaskElt(Index);
4827 return DAG.getUNDEF(VT.getVectorElementType());
4829 unsigned NumElems = VT.getVectorNumElements();
4830 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4831 : SV->getOperand(1);
4832 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4835 // Recurse into target specific vector shuffles to find scalars.
4836 if (isTargetShuffle(Opcode)) {
4837 MVT ShufVT = V.getSimpleValueType();
4838 unsigned NumElems = ShufVT.getVectorNumElements();
4839 SmallVector<int, 16> ShuffleMask;
4842 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4845 int Elt = ShuffleMask[Index];
4847 return DAG.getUNDEF(ShufVT.getVectorElementType());
4849 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4851 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4855 // Actual nodes that may contain scalar elements
4856 if (Opcode == ISD::BITCAST) {
4857 V = V.getOperand(0);
4858 EVT SrcVT = V.getValueType();
4859 unsigned NumElems = VT.getVectorNumElements();
4861 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4865 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4866 return (Index == 0) ? V.getOperand(0)
4867 : DAG.getUNDEF(VT.getVectorElementType());
4869 if (V.getOpcode() == ISD::BUILD_VECTOR)
4870 return V.getOperand(Index);
4875 /// Custom lower build_vector of v16i8.
4876 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4877 unsigned NumNonZero, unsigned NumZero,
4879 const X86Subtarget* Subtarget,
4880 const TargetLowering &TLI) {
4888 // SSE4.1 - use PINSRB to insert each byte directly.
4889 if (Subtarget->hasSSE41()) {
4890 for (unsigned i = 0; i < 16; ++i) {
4891 bool isNonZero = (NonZeros & (1 << i)) != 0;
4895 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4897 V = DAG.getUNDEF(MVT::v16i8);
4900 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4901 MVT::v16i8, V, Op.getOperand(i),
4902 DAG.getIntPtrConstant(i, dl));
4909 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4910 for (unsigned i = 0; i < 16; ++i) {
4911 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4912 if (ThisIsNonZero && First) {
4914 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4916 V = DAG.getUNDEF(MVT::v8i16);
4921 SDValue ThisElt, LastElt;
4922 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4923 if (LastIsNonZero) {
4924 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4925 MVT::i16, Op.getOperand(i-1));
4927 if (ThisIsNonZero) {
4928 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4929 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4930 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4932 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4936 if (ThisElt.getNode())
4937 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4938 DAG.getIntPtrConstant(i/2, dl));
4942 return DAG.getBitcast(MVT::v16i8, V);
4945 /// Custom lower build_vector of v8i16.
4946 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4947 unsigned NumNonZero, unsigned NumZero,
4949 const X86Subtarget* Subtarget,
4950 const TargetLowering &TLI) {
4957 for (unsigned i = 0; i < 8; ++i) {
4958 bool isNonZero = (NonZeros & (1 << i)) != 0;
4962 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4964 V = DAG.getUNDEF(MVT::v8i16);
4967 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4968 MVT::v8i16, V, Op.getOperand(i),
4969 DAG.getIntPtrConstant(i, dl));
4976 /// Custom lower build_vector of v4i32 or v4f32.
4977 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4978 const X86Subtarget *Subtarget,
4979 const TargetLowering &TLI) {
4980 // Find all zeroable elements.
4981 std::bitset<4> Zeroable;
4982 for (int i=0; i < 4; ++i) {
4983 SDValue Elt = Op->getOperand(i);
4984 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4986 assert(Zeroable.size() - Zeroable.count() > 1 &&
4987 "We expect at least two non-zero elements!");
4989 // We only know how to deal with build_vector nodes where elements are either
4990 // zeroable or extract_vector_elt with constant index.
4991 SDValue FirstNonZero;
4992 unsigned FirstNonZeroIdx;
4993 for (unsigned i=0; i < 4; ++i) {
4996 SDValue Elt = Op->getOperand(i);
4997 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4998 !isa<ConstantSDNode>(Elt.getOperand(1)))
5000 // Make sure that this node is extracting from a 128-bit vector.
5001 MVT VT = Elt.getOperand(0).getSimpleValueType();
5002 if (!VT.is128BitVector())
5004 if (!FirstNonZero.getNode()) {
5006 FirstNonZeroIdx = i;
5010 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5011 SDValue V1 = FirstNonZero.getOperand(0);
5012 MVT VT = V1.getSimpleValueType();
5014 // See if this build_vector can be lowered as a blend with zero.
5016 unsigned EltMaskIdx, EltIdx;
5018 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5019 if (Zeroable[EltIdx]) {
5020 // The zero vector will be on the right hand side.
5021 Mask[EltIdx] = EltIdx+4;
5025 Elt = Op->getOperand(EltIdx);
5026 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5027 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5028 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5030 Mask[EltIdx] = EltIdx;
5034 // Let the shuffle legalizer deal with blend operations.
5035 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5036 if (V1.getSimpleValueType() != VT)
5037 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5038 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5041 // See if we can lower this build_vector to a INSERTPS.
5042 if (!Subtarget->hasSSE41())
5045 SDValue V2 = Elt.getOperand(0);
5046 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5049 bool CanFold = true;
5050 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5054 SDValue Current = Op->getOperand(i);
5055 SDValue SrcVector = Current->getOperand(0);
5058 CanFold = SrcVector == V1 &&
5059 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5065 assert(V1.getNode() && "Expected at least two non-zero elements!");
5066 if (V1.getSimpleValueType() != MVT::v4f32)
5067 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5068 if (V2.getSimpleValueType() != MVT::v4f32)
5069 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5071 // Ok, we can emit an INSERTPS instruction.
5072 unsigned ZMask = Zeroable.to_ulong();
5074 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5075 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5077 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5078 DAG.getIntPtrConstant(InsertPSMask, DL));
5079 return DAG.getBitcast(VT, Result);
5082 /// Return a vector logical shift node.
5083 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5084 unsigned NumBits, SelectionDAG &DAG,
5085 const TargetLowering &TLI, SDLoc dl) {
5086 assert(VT.is128BitVector() && "Unknown type for VShift");
5087 MVT ShVT = MVT::v2i64;
5088 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5089 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5090 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5091 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5092 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5093 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5097 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5099 // Check if the scalar load can be widened into a vector load. And if
5100 // the address is "base + cst" see if the cst can be "absorbed" into
5101 // the shuffle mask.
5102 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5103 SDValue Ptr = LD->getBasePtr();
5104 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5106 EVT PVT = LD->getValueType(0);
5107 if (PVT != MVT::i32 && PVT != MVT::f32)
5112 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5113 FI = FINode->getIndex();
5115 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5116 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5117 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5118 Offset = Ptr.getConstantOperandVal(1);
5119 Ptr = Ptr.getOperand(0);
5124 // FIXME: 256-bit vector instructions don't require a strict alignment,
5125 // improve this code to support it better.
5126 unsigned RequiredAlign = VT.getSizeInBits()/8;
5127 SDValue Chain = LD->getChain();
5128 // Make sure the stack object alignment is at least 16 or 32.
5129 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5130 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5131 if (MFI->isFixedObjectIndex(FI)) {
5132 // Can't change the alignment. FIXME: It's possible to compute
5133 // the exact stack offset and reference FI + adjust offset instead.
5134 // If someone *really* cares about this. That's the way to implement it.
5137 MFI->setObjectAlignment(FI, RequiredAlign);
5141 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5142 // Ptr + (Offset & ~15).
5145 if ((Offset % RequiredAlign) & 3)
5147 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5150 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5151 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5154 int EltNo = (Offset - StartOffset) >> 2;
5155 unsigned NumElems = VT.getVectorNumElements();
5157 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5158 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5159 LD->getPointerInfo().getWithOffset(StartOffset),
5160 false, false, false, 0);
5162 SmallVector<int, 8> Mask(NumElems, EltNo);
5164 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5170 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5171 /// elements can be replaced by a single large load which has the same value as
5172 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5174 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5176 /// FIXME: we'd also like to handle the case where the last elements are zero
5177 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5178 /// There's even a handy isZeroNode for that purpose.
5179 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5180 SDLoc &DL, SelectionDAG &DAG,
5181 bool isAfterLegalize) {
5182 unsigned NumElems = Elts.size();
5184 LoadSDNode *LDBase = nullptr;
5185 unsigned LastLoadedElt = -1U;
5187 // For each element in the initializer, see if we've found a load or an undef.
5188 // If we don't find an initial load element, or later load elements are
5189 // non-consecutive, bail out.
5190 for (unsigned i = 0; i < NumElems; ++i) {
5191 SDValue Elt = Elts[i];
5192 // Look through a bitcast.
5193 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5194 Elt = Elt.getOperand(0);
5195 if (!Elt.getNode() ||
5196 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5199 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5201 LDBase = cast<LoadSDNode>(Elt.getNode());
5205 if (Elt.getOpcode() == ISD::UNDEF)
5208 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5209 EVT LdVT = Elt.getValueType();
5210 // Each loaded element must be the correct fractional portion of the
5211 // requested vector load.
5212 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5214 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5219 // If we have found an entire vector of loads and undefs, then return a large
5220 // load of the entire vector width starting at the base pointer. If we found
5221 // consecutive loads for the low half, generate a vzext_load node.
5222 if (LastLoadedElt == NumElems - 1) {
5223 assert(LDBase && "Did not find base load for merging consecutive loads");
5224 EVT EltVT = LDBase->getValueType(0);
5225 // Ensure that the input vector size for the merged loads matches the
5226 // cumulative size of the input elements.
5227 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5230 if (isAfterLegalize &&
5231 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5234 SDValue NewLd = SDValue();
5236 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5237 LDBase->getPointerInfo(), LDBase->isVolatile(),
5238 LDBase->isNonTemporal(), LDBase->isInvariant(),
5239 LDBase->getAlignment());
5241 if (LDBase->hasAnyUseOfValue(1)) {
5242 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5244 SDValue(NewLd.getNode(), 1));
5245 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5246 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5247 SDValue(NewLd.getNode(), 1));
5253 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5254 //of a v4i32 / v4f32. It's probably worth generalizing.
5255 EVT EltVT = VT.getVectorElementType();
5256 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5257 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5258 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5259 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5261 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5262 LDBase->getPointerInfo(),
5263 LDBase->getAlignment(),
5264 false/*isVolatile*/, true/*ReadMem*/,
5267 // Make sure the newly-created LOAD is in the same position as LDBase in
5268 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5269 // update uses of LDBase's output chain to use the TokenFactor.
5270 if (LDBase->hasAnyUseOfValue(1)) {
5271 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5272 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5273 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5274 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5275 SDValue(ResNode.getNode(), 1));
5278 return DAG.getBitcast(VT, ResNode);
5283 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5284 /// to generate a splat value for the following cases:
5285 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5286 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5287 /// a scalar load, or a constant.
5288 /// The VBROADCAST node is returned when a pattern is found,
5289 /// or SDValue() otherwise.
5290 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5291 SelectionDAG &DAG) {
5292 // VBROADCAST requires AVX.
5293 // TODO: Splats could be generated for non-AVX CPUs using SSE
5294 // instructions, but there's less potential gain for only 128-bit vectors.
5295 if (!Subtarget->hasAVX())
5298 MVT VT = Op.getSimpleValueType();
5301 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5302 "Unsupported vector type for broadcast.");
5307 switch (Op.getOpcode()) {
5309 // Unknown pattern found.
5312 case ISD::BUILD_VECTOR: {
5313 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5314 BitVector UndefElements;
5315 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5317 // We need a splat of a single value to use broadcast, and it doesn't
5318 // make any sense if the value is only in one element of the vector.
5319 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5323 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5324 Ld.getOpcode() == ISD::ConstantFP);
5326 // Make sure that all of the users of a non-constant load are from the
5327 // BUILD_VECTOR node.
5328 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5333 case ISD::VECTOR_SHUFFLE: {
5334 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5336 // Shuffles must have a splat mask where the first element is
5338 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5341 SDValue Sc = Op.getOperand(0);
5342 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5343 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5345 if (!Subtarget->hasInt256())
5348 // Use the register form of the broadcast instruction available on AVX2.
5349 if (VT.getSizeInBits() >= 256)
5350 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5351 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5354 Ld = Sc.getOperand(0);
5355 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5356 Ld.getOpcode() == ISD::ConstantFP);
5358 // The scalar_to_vector node and the suspected
5359 // load node must have exactly one user.
5360 // Constants may have multiple users.
5362 // AVX-512 has register version of the broadcast
5363 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5364 Ld.getValueType().getSizeInBits() >= 32;
5365 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5372 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5373 bool IsGE256 = (VT.getSizeInBits() >= 256);
5375 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5376 // instruction to save 8 or more bytes of constant pool data.
5377 // TODO: If multiple splats are generated to load the same constant,
5378 // it may be detrimental to overall size. There needs to be a way to detect
5379 // that condition to know if this is truly a size win.
5380 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5382 // Handle broadcasting a single constant scalar from the constant pool
5384 // On Sandybridge (no AVX2), it is still better to load a constant vector
5385 // from the constant pool and not to broadcast it from a scalar.
5386 // But override that restriction when optimizing for size.
5387 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5388 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5389 EVT CVT = Ld.getValueType();
5390 assert(!CVT.isVector() && "Must not broadcast a vector type");
5392 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5393 // For size optimization, also splat v2f64 and v2i64, and for size opt
5394 // with AVX2, also splat i8 and i16.
5395 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5396 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5397 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5398 const Constant *C = nullptr;
5399 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5400 C = CI->getConstantIntValue();
5401 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5402 C = CF->getConstantFPValue();
5404 assert(C && "Invalid constant type");
5406 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5408 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5409 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5411 CVT, dl, DAG.getEntryNode(), CP,
5412 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5413 false, false, Alignment);
5415 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5419 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5421 // Handle AVX2 in-register broadcasts.
5422 if (!IsLoad && Subtarget->hasInt256() &&
5423 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5424 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5426 // The scalar source must be a normal load.
5430 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5431 (Subtarget->hasVLX() && ScalarSize == 64))
5432 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5434 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5435 // double since there is no vbroadcastsd xmm
5436 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5437 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5438 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5441 // Unsupported broadcast.
5445 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5446 /// underlying vector and index.
5448 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5450 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5452 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5453 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5456 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5458 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5460 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5461 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5464 // In this case the vector is the extract_subvector expression and the index
5465 // is 2, as specified by the shuffle.
5466 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5467 SDValue ShuffleVec = SVOp->getOperand(0);
5468 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5469 assert(ShuffleVecVT.getVectorElementType() ==
5470 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5472 int ShuffleIdx = SVOp->getMaskElt(Idx);
5473 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5474 ExtractedFromVec = ShuffleVec;
5480 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5481 MVT VT = Op.getSimpleValueType();
5483 // Skip if insert_vec_elt is not supported.
5484 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5485 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5489 unsigned NumElems = Op.getNumOperands();
5493 SmallVector<unsigned, 4> InsertIndices;
5494 SmallVector<int, 8> Mask(NumElems, -1);
5496 for (unsigned i = 0; i != NumElems; ++i) {
5497 unsigned Opc = Op.getOperand(i).getOpcode();
5499 if (Opc == ISD::UNDEF)
5502 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5503 // Quit if more than 1 elements need inserting.
5504 if (InsertIndices.size() > 1)
5507 InsertIndices.push_back(i);
5511 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5512 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5513 // Quit if non-constant index.
5514 if (!isa<ConstantSDNode>(ExtIdx))
5516 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5518 // Quit if extracted from vector of different type.
5519 if (ExtractedFromVec.getValueType() != VT)
5522 if (!VecIn1.getNode())
5523 VecIn1 = ExtractedFromVec;
5524 else if (VecIn1 != ExtractedFromVec) {
5525 if (!VecIn2.getNode())
5526 VecIn2 = ExtractedFromVec;
5527 else if (VecIn2 != ExtractedFromVec)
5528 // Quit if more than 2 vectors to shuffle
5532 if (ExtractedFromVec == VecIn1)
5534 else if (ExtractedFromVec == VecIn2)
5535 Mask[i] = Idx + NumElems;
5538 if (!VecIn1.getNode())
5541 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5542 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5543 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5544 unsigned Idx = InsertIndices[i];
5545 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5546 DAG.getIntPtrConstant(Idx, DL));
5552 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5553 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5554 Op.getScalarValueSizeInBits() == 1 &&
5555 "Can not convert non-constant vector");
5556 uint64_t Immediate = 0;
5557 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5558 SDValue In = Op.getOperand(idx);
5559 if (In.getOpcode() != ISD::UNDEF)
5560 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5564 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5565 return DAG.getConstant(Immediate, dl, VT);
5567 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5569 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5571 MVT VT = Op.getSimpleValueType();
5572 assert((VT.getVectorElementType() == MVT::i1) &&
5573 "Unexpected type in LowerBUILD_VECTORvXi1!");
5576 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5577 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5578 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5579 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5582 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5583 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5584 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5585 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5588 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5589 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5590 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5591 return DAG.getBitcast(VT, Imm);
5592 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5593 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5594 DAG.getIntPtrConstant(0, dl));
5597 // Vector has one or more non-const elements
5598 uint64_t Immediate = 0;
5599 SmallVector<unsigned, 16> NonConstIdx;
5600 bool IsSplat = true;
5601 bool HasConstElts = false;
5603 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5604 SDValue In = Op.getOperand(idx);
5605 if (In.getOpcode() == ISD::UNDEF)
5607 if (!isa<ConstantSDNode>(In))
5608 NonConstIdx.push_back(idx);
5610 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5611 HasConstElts = true;
5615 else if (In != Op.getOperand(SplatIdx))
5619 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5621 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5622 DAG.getConstant(1, dl, VT),
5623 DAG.getConstant(0, dl, VT));
5625 // insert elements one by one
5629 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5630 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5632 else if (HasConstElts)
5633 Imm = DAG.getConstant(0, dl, VT);
5635 Imm = DAG.getUNDEF(VT);
5636 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5637 DstVec = DAG.getBitcast(VT, Imm);
5639 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5640 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5641 DAG.getIntPtrConstant(0, dl));
5644 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5645 unsigned InsertIdx = NonConstIdx[i];
5646 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5647 Op.getOperand(InsertIdx),
5648 DAG.getIntPtrConstant(InsertIdx, dl));
5653 /// \brief Return true if \p N implements a horizontal binop and return the
5654 /// operands for the horizontal binop into V0 and V1.
5656 /// This is a helper function of LowerToHorizontalOp().
5657 /// This function checks that the build_vector \p N in input implements a
5658 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5659 /// operation to match.
5660 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5661 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5662 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5665 /// This function only analyzes elements of \p N whose indices are
5666 /// in range [BaseIdx, LastIdx).
5667 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5669 unsigned BaseIdx, unsigned LastIdx,
5670 SDValue &V0, SDValue &V1) {
5671 EVT VT = N->getValueType(0);
5673 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5674 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5675 "Invalid Vector in input!");
5677 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5678 bool CanFold = true;
5679 unsigned ExpectedVExtractIdx = BaseIdx;
5680 unsigned NumElts = LastIdx - BaseIdx;
5681 V0 = DAG.getUNDEF(VT);
5682 V1 = DAG.getUNDEF(VT);
5684 // Check if N implements a horizontal binop.
5685 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5686 SDValue Op = N->getOperand(i + BaseIdx);
5689 if (Op->getOpcode() == ISD::UNDEF) {
5690 // Update the expected vector extract index.
5691 if (i * 2 == NumElts)
5692 ExpectedVExtractIdx = BaseIdx;
5693 ExpectedVExtractIdx += 2;
5697 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5702 SDValue Op0 = Op.getOperand(0);
5703 SDValue Op1 = Op.getOperand(1);
5705 // Try to match the following pattern:
5706 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5707 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5708 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5709 Op0.getOperand(0) == Op1.getOperand(0) &&
5710 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5711 isa<ConstantSDNode>(Op1.getOperand(1)));
5715 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5716 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5718 if (i * 2 < NumElts) {
5719 if (V0.getOpcode() == ISD::UNDEF) {
5720 V0 = Op0.getOperand(0);
5721 if (V0.getValueType() != VT)
5725 if (V1.getOpcode() == ISD::UNDEF) {
5726 V1 = Op0.getOperand(0);
5727 if (V1.getValueType() != VT)
5730 if (i * 2 == NumElts)
5731 ExpectedVExtractIdx = BaseIdx;
5734 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5735 if (I0 == ExpectedVExtractIdx)
5736 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5737 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5738 // Try to match the following dag sequence:
5739 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5740 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5744 ExpectedVExtractIdx += 2;
5750 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5751 /// a concat_vector.
5753 /// This is a helper function of LowerToHorizontalOp().
5754 /// This function expects two 256-bit vectors called V0 and V1.
5755 /// At first, each vector is split into two separate 128-bit vectors.
5756 /// Then, the resulting 128-bit vectors are used to implement two
5757 /// horizontal binary operations.
5759 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5761 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5762 /// the two new horizontal binop.
5763 /// When Mode is set, the first horizontal binop dag node would take as input
5764 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5765 /// horizontal binop dag node would take as input the lower 128-bit of V1
5766 /// and the upper 128-bit of V1.
5768 /// HADD V0_LO, V0_HI
5769 /// HADD V1_LO, V1_HI
5771 /// Otherwise, the first horizontal binop dag node takes as input the lower
5772 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5773 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5775 /// HADD V0_LO, V1_LO
5776 /// HADD V0_HI, V1_HI
5778 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5779 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5780 /// the upper 128-bits of the result.
5781 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5782 SDLoc DL, SelectionDAG &DAG,
5783 unsigned X86Opcode, bool Mode,
5784 bool isUndefLO, bool isUndefHI) {
5785 EVT VT = V0.getValueType();
5786 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5787 "Invalid nodes in input!");
5789 unsigned NumElts = VT.getVectorNumElements();
5790 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5791 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5792 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5793 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5794 EVT NewVT = V0_LO.getValueType();
5796 SDValue LO = DAG.getUNDEF(NewVT);
5797 SDValue HI = DAG.getUNDEF(NewVT);
5800 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5801 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5802 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5803 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5804 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5806 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5807 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5808 V1_LO->getOpcode() != ISD::UNDEF))
5809 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5811 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5812 V1_HI->getOpcode() != ISD::UNDEF))
5813 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5816 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5819 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5821 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5822 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5823 EVT VT = BV->getValueType(0);
5824 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5825 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5829 unsigned NumElts = VT.getVectorNumElements();
5830 SDValue InVec0 = DAG.getUNDEF(VT);
5831 SDValue InVec1 = DAG.getUNDEF(VT);
5833 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5834 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5836 // Odd-numbered elements in the input build vector are obtained from
5837 // adding two integer/float elements.
5838 // Even-numbered elements in the input build vector are obtained from
5839 // subtracting two integer/float elements.
5840 unsigned ExpectedOpcode = ISD::FSUB;
5841 unsigned NextExpectedOpcode = ISD::FADD;
5842 bool AddFound = false;
5843 bool SubFound = false;
5845 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5846 SDValue Op = BV->getOperand(i);
5848 // Skip 'undef' values.
5849 unsigned Opcode = Op.getOpcode();
5850 if (Opcode == ISD::UNDEF) {
5851 std::swap(ExpectedOpcode, NextExpectedOpcode);
5855 // Early exit if we found an unexpected opcode.
5856 if (Opcode != ExpectedOpcode)
5859 SDValue Op0 = Op.getOperand(0);
5860 SDValue Op1 = Op.getOperand(1);
5862 // Try to match the following pattern:
5863 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5864 // Early exit if we cannot match that sequence.
5865 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5866 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5867 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5868 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5869 Op0.getOperand(1) != Op1.getOperand(1))
5872 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5876 // We found a valid add/sub node. Update the information accordingly.
5882 // Update InVec0 and InVec1.
5883 if (InVec0.getOpcode() == ISD::UNDEF) {
5884 InVec0 = Op0.getOperand(0);
5885 if (InVec0.getValueType() != VT)
5888 if (InVec1.getOpcode() == ISD::UNDEF) {
5889 InVec1 = Op1.getOperand(0);
5890 if (InVec1.getValueType() != VT)
5894 // Make sure that operands in input to each add/sub node always
5895 // come from a same pair of vectors.
5896 if (InVec0 != Op0.getOperand(0)) {
5897 if (ExpectedOpcode == ISD::FSUB)
5900 // FADD is commutable. Try to commute the operands
5901 // and then test again.
5902 std::swap(Op0, Op1);
5903 if (InVec0 != Op0.getOperand(0))
5907 if (InVec1 != Op1.getOperand(0))
5910 // Update the pair of expected opcodes.
5911 std::swap(ExpectedOpcode, NextExpectedOpcode);
5914 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5915 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5916 InVec1.getOpcode() != ISD::UNDEF)
5917 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5922 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5923 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5924 const X86Subtarget *Subtarget,
5925 SelectionDAG &DAG) {
5926 EVT VT = BV->getValueType(0);
5927 unsigned NumElts = VT.getVectorNumElements();
5928 unsigned NumUndefsLO = 0;
5929 unsigned NumUndefsHI = 0;
5930 unsigned Half = NumElts/2;
5932 // Count the number of UNDEF operands in the build_vector in input.
5933 for (unsigned i = 0, e = Half; i != e; ++i)
5934 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5937 for (unsigned i = Half, e = NumElts; i != e; ++i)
5938 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5941 // Early exit if this is either a build_vector of all UNDEFs or all the
5942 // operands but one are UNDEF.
5943 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5947 SDValue InVec0, InVec1;
5948 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5949 // Try to match an SSE3 float HADD/HSUB.
5950 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5951 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5953 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5954 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5955 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5956 // Try to match an SSSE3 integer HADD/HSUB.
5957 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5958 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5960 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5961 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5964 if (!Subtarget->hasAVX())
5967 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5968 // Try to match an AVX horizontal add/sub of packed single/double
5969 // precision floating point values from 256-bit vectors.
5970 SDValue InVec2, InVec3;
5971 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5972 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5973 ((InVec0.getOpcode() == ISD::UNDEF ||
5974 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5975 ((InVec1.getOpcode() == ISD::UNDEF ||
5976 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5977 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5979 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5980 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5981 ((InVec0.getOpcode() == ISD::UNDEF ||
5982 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5983 ((InVec1.getOpcode() == ISD::UNDEF ||
5984 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5985 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5986 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5987 // Try to match an AVX2 horizontal add/sub of signed integers.
5988 SDValue InVec2, InVec3;
5990 bool CanFold = true;
5992 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5993 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5994 ((InVec0.getOpcode() == ISD::UNDEF ||
5995 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5996 ((InVec1.getOpcode() == ISD::UNDEF ||
5997 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5998 X86Opcode = X86ISD::HADD;
5999 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6000 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6001 ((InVec0.getOpcode() == ISD::UNDEF ||
6002 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6003 ((InVec1.getOpcode() == ISD::UNDEF ||
6004 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6005 X86Opcode = X86ISD::HSUB;
6010 // Fold this build_vector into a single horizontal add/sub.
6011 // Do this only if the target has AVX2.
6012 if (Subtarget->hasAVX2())
6013 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6015 // Do not try to expand this build_vector into a pair of horizontal
6016 // add/sub if we can emit a pair of scalar add/sub.
6017 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6020 // Convert this build_vector into a pair of horizontal binop followed by
6022 bool isUndefLO = NumUndefsLO == Half;
6023 bool isUndefHI = NumUndefsHI == Half;
6024 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6025 isUndefLO, isUndefHI);
6029 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6030 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6032 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6033 X86Opcode = X86ISD::HADD;
6034 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6035 X86Opcode = X86ISD::HSUB;
6036 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6037 X86Opcode = X86ISD::FHADD;
6038 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6039 X86Opcode = X86ISD::FHSUB;
6043 // Don't try to expand this build_vector into a pair of horizontal add/sub
6044 // if we can simply emit a pair of scalar add/sub.
6045 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6048 // Convert this build_vector into two horizontal add/sub followed by
6050 bool isUndefLO = NumUndefsLO == Half;
6051 bool isUndefHI = NumUndefsHI == Half;
6052 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6053 isUndefLO, isUndefHI);
6060 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6063 MVT VT = Op.getSimpleValueType();
6064 MVT ExtVT = VT.getVectorElementType();
6065 unsigned NumElems = Op.getNumOperands();
6067 // Generate vectors for predicate vectors.
6068 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6069 return LowerBUILD_VECTORvXi1(Op, DAG);
6071 // Vectors containing all zeros can be matched by pxor and xorps later
6072 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6073 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6074 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6075 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6078 return getZeroVector(VT, Subtarget, DAG, dl);
6081 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6082 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6083 // vpcmpeqd on 256-bit vectors.
6084 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6085 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6088 if (!VT.is512BitVector())
6089 return getOnesVector(VT, Subtarget, DAG, dl);
6092 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6093 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6095 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6096 return HorizontalOp;
6097 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6100 unsigned EVTBits = ExtVT.getSizeInBits();
6102 unsigned NumZero = 0;
6103 unsigned NumNonZero = 0;
6104 unsigned NonZeros = 0;
6105 bool IsAllConstants = true;
6106 SmallSet<SDValue, 8> Values;
6107 for (unsigned i = 0; i < NumElems; ++i) {
6108 SDValue Elt = Op.getOperand(i);
6109 if (Elt.getOpcode() == ISD::UNDEF)
6112 if (Elt.getOpcode() != ISD::Constant &&
6113 Elt.getOpcode() != ISD::ConstantFP)
6114 IsAllConstants = false;
6115 if (X86::isZeroNode(Elt))
6118 NonZeros |= (1 << i);
6123 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6124 if (NumNonZero == 0)
6125 return DAG.getUNDEF(VT);
6127 // Special case for single non-zero, non-undef, element.
6128 if (NumNonZero == 1) {
6129 unsigned Idx = countTrailingZeros(NonZeros);
6130 SDValue Item = Op.getOperand(Idx);
6132 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6133 // the value are obviously zero, truncate the value to i32 and do the
6134 // insertion that way. Only do this if the value is non-constant or if the
6135 // value is a constant being inserted into element 0. It is cheaper to do
6136 // a constant pool load than it is to do a movd + shuffle.
6137 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6138 (!IsAllConstants || Idx == 0)) {
6139 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6141 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6142 EVT VecVT = MVT::v4i32;
6144 // Truncate the value (which may itself be a constant) to i32, and
6145 // convert it to a vector with movd (S2V+shuffle to zero extend).
6146 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6147 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6148 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6149 Item, Idx * 2, true, Subtarget, DAG));
6153 // If we have a constant or non-constant insertion into the low element of
6154 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6155 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6156 // depending on what the source datatype is.
6159 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6161 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6162 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6163 if (VT.is512BitVector()) {
6164 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6165 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6166 Item, DAG.getIntPtrConstant(0, dl));
6168 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6169 "Expected an SSE value type!");
6170 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6171 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6172 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6175 // We can't directly insert an i8 or i16 into a vector, so zero extend
6177 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6178 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6179 if (VT.is256BitVector()) {
6180 if (Subtarget->hasAVX()) {
6181 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6182 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6184 // Without AVX, we need to extend to a 128-bit vector and then
6185 // insert into the 256-bit vector.
6186 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6187 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6188 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6191 assert(VT.is128BitVector() && "Expected an SSE value type!");
6192 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6193 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6195 return DAG.getBitcast(VT, Item);
6199 // Is it a vector logical left shift?
6200 if (NumElems == 2 && Idx == 1 &&
6201 X86::isZeroNode(Op.getOperand(0)) &&
6202 !X86::isZeroNode(Op.getOperand(1))) {
6203 unsigned NumBits = VT.getSizeInBits();
6204 return getVShift(true, VT,
6205 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6206 VT, Op.getOperand(1)),
6207 NumBits/2, DAG, *this, dl);
6210 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6213 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6214 // is a non-constant being inserted into an element other than the low one,
6215 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6216 // movd/movss) to move this into the low element, then shuffle it into
6218 if (EVTBits == 32) {
6219 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6220 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6224 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6225 if (Values.size() == 1) {
6226 if (EVTBits == 32) {
6227 // Instead of a shuffle like this:
6228 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6229 // Check if it's possible to issue this instead.
6230 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6231 unsigned Idx = countTrailingZeros(NonZeros);
6232 SDValue Item = Op.getOperand(Idx);
6233 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6234 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6239 // A vector full of immediates; various special cases are already
6240 // handled, so this is best done with a single constant-pool load.
6244 // For AVX-length vectors, see if we can use a vector load to get all of the
6245 // elements, otherwise build the individual 128-bit pieces and use
6246 // shuffles to put them in place.
6247 if (VT.is256BitVector() || VT.is512BitVector()) {
6248 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6250 // Check for a build vector of consecutive loads.
6251 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6254 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6256 // Build both the lower and upper subvector.
6257 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6258 makeArrayRef(&V[0], NumElems/2));
6259 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6260 makeArrayRef(&V[NumElems / 2], NumElems/2));
6262 // Recreate the wider vector with the lower and upper part.
6263 if (VT.is256BitVector())
6264 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6265 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6268 // Let legalizer expand 2-wide build_vectors.
6269 if (EVTBits == 64) {
6270 if (NumNonZero == 1) {
6271 // One half is zero or undef.
6272 unsigned Idx = countTrailingZeros(NonZeros);
6273 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6274 Op.getOperand(Idx));
6275 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6280 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6281 if (EVTBits == 8 && NumElems == 16)
6282 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6286 if (EVTBits == 16 && NumElems == 8)
6287 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6291 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6292 if (EVTBits == 32 && NumElems == 4)
6293 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6296 // If element VT is == 32 bits, turn it into a number of shuffles.
6297 SmallVector<SDValue, 8> V(NumElems);
6298 if (NumElems == 4 && NumZero > 0) {
6299 for (unsigned i = 0; i < 4; ++i) {
6300 bool isZero = !(NonZeros & (1 << i));
6302 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6304 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6307 for (unsigned i = 0; i < 2; ++i) {
6308 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6311 V[i] = V[i*2]; // Must be a zero vector.
6314 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6317 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6320 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6325 bool Reverse1 = (NonZeros & 0x3) == 2;
6326 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6330 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6331 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6333 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6336 if (Values.size() > 1 && VT.is128BitVector()) {
6337 // Check for a build vector of consecutive loads.
6338 for (unsigned i = 0; i < NumElems; ++i)
6339 V[i] = Op.getOperand(i);
6341 // Check for elements which are consecutive loads.
6342 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6345 // Check for a build vector from mostly shuffle plus few inserting.
6346 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6349 // For SSE 4.1, use insertps to put the high elements into the low element.
6350 if (Subtarget->hasSSE41()) {
6352 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6353 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6355 Result = DAG.getUNDEF(VT);
6357 for (unsigned i = 1; i < NumElems; ++i) {
6358 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6359 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6360 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6365 // Otherwise, expand into a number of unpckl*, start by extending each of
6366 // our (non-undef) elements to the full vector width with the element in the
6367 // bottom slot of the vector (which generates no code for SSE).
6368 for (unsigned i = 0; i < NumElems; ++i) {
6369 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6370 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6372 V[i] = DAG.getUNDEF(VT);
6375 // Next, we iteratively mix elements, e.g. for v4f32:
6376 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6377 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6378 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6379 unsigned EltStride = NumElems >> 1;
6380 while (EltStride != 0) {
6381 for (unsigned i = 0; i < EltStride; ++i) {
6382 // If V[i+EltStride] is undef and this is the first round of mixing,
6383 // then it is safe to just drop this shuffle: V[i] is already in the
6384 // right place, the one element (since it's the first round) being
6385 // inserted as undef can be dropped. This isn't safe for successive
6386 // rounds because they will permute elements within both vectors.
6387 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6388 EltStride == NumElems/2)
6391 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6400 // 256-bit AVX can use the vinsertf128 instruction
6401 // to create 256-bit vectors from two other 128-bit ones.
6402 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6404 MVT ResVT = Op.getSimpleValueType();
6406 assert((ResVT.is256BitVector() ||
6407 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6409 SDValue V1 = Op.getOperand(0);
6410 SDValue V2 = Op.getOperand(1);
6411 unsigned NumElems = ResVT.getVectorNumElements();
6412 if (ResVT.is256BitVector())
6413 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6415 if (Op.getNumOperands() == 4) {
6416 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6417 ResVT.getVectorNumElements()/2);
6418 SDValue V3 = Op.getOperand(2);
6419 SDValue V4 = Op.getOperand(3);
6420 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6421 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6423 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6426 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6427 const X86Subtarget *Subtarget,
6428 SelectionDAG & DAG) {
6430 MVT ResVT = Op.getSimpleValueType();
6431 unsigned NumOfOperands = Op.getNumOperands();
6433 assert(isPowerOf2_32(NumOfOperands) &&
6434 "Unexpected number of operands in CONCAT_VECTORS");
6436 if (NumOfOperands > 2) {
6437 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6438 ResVT.getVectorNumElements()/2);
6439 SmallVector<SDValue, 2> Ops;
6440 for (unsigned i = 0; i < NumOfOperands/2; i++)
6441 Ops.push_back(Op.getOperand(i));
6442 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6444 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6445 Ops.push_back(Op.getOperand(i));
6446 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6447 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6450 SDValue V1 = Op.getOperand(0);
6451 SDValue V2 = Op.getOperand(1);
6452 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6453 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6455 if (IsZeroV1 && IsZeroV2)
6456 return getZeroVector(ResVT, Subtarget, DAG, dl);
6458 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6459 SDValue Undef = DAG.getUNDEF(ResVT);
6460 unsigned NumElems = ResVT.getVectorNumElements();
6461 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6463 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6464 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6468 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6469 // Zero the upper bits of V1
6470 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6471 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6474 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6477 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6478 const X86Subtarget *Subtarget,
6479 SelectionDAG &DAG) {
6480 MVT VT = Op.getSimpleValueType();
6481 if (VT.getVectorElementType() == MVT::i1)
6482 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6484 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6485 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6486 Op.getNumOperands() == 4)));
6488 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6489 // from two other 128-bit ones.
6491 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6492 return LowerAVXCONCAT_VECTORS(Op, DAG);
6495 //===----------------------------------------------------------------------===//
6496 // Vector shuffle lowering
6498 // This is an experimental code path for lowering vector shuffles on x86. It is
6499 // designed to handle arbitrary vector shuffles and blends, gracefully
6500 // degrading performance as necessary. It works hard to recognize idiomatic
6501 // shuffles and lower them to optimal instruction patterns without leaving
6502 // a framework that allows reasonably efficient handling of all vector shuffle
6504 //===----------------------------------------------------------------------===//
6506 /// \brief Tiny helper function to identify a no-op mask.
6508 /// This is a somewhat boring predicate function. It checks whether the mask
6509 /// array input, which is assumed to be a single-input shuffle mask of the kind
6510 /// used by the X86 shuffle instructions (not a fully general
6511 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6512 /// in-place shuffle are 'no-op's.
6513 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6514 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6515 if (Mask[i] != -1 && Mask[i] != i)
6520 /// \brief Helper function to classify a mask as a single-input mask.
6522 /// This isn't a generic single-input test because in the vector shuffle
6523 /// lowering we canonicalize single inputs to be the first input operand. This
6524 /// means we can more quickly test for a single input by only checking whether
6525 /// an input from the second operand exists. We also assume that the size of
6526 /// mask corresponds to the size of the input vectors which isn't true in the
6527 /// fully general case.
6528 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6530 if (M >= (int)Mask.size())
6535 /// \brief Test whether there are elements crossing 128-bit lanes in this
6538 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6539 /// and we routinely test for these.
6540 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6541 int LaneSize = 128 / VT.getScalarSizeInBits();
6542 int Size = Mask.size();
6543 for (int i = 0; i < Size; ++i)
6544 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6549 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6551 /// This checks a shuffle mask to see if it is performing the same
6552 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6553 /// that it is also not lane-crossing. It may however involve a blend from the
6554 /// same lane of a second vector.
6556 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6557 /// non-trivial to compute in the face of undef lanes. The representation is
6558 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6559 /// entries from both V1 and V2 inputs to the wider mask.
6561 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6562 SmallVectorImpl<int> &RepeatedMask) {
6563 int LaneSize = 128 / VT.getScalarSizeInBits();
6564 RepeatedMask.resize(LaneSize, -1);
6565 int Size = Mask.size();
6566 for (int i = 0; i < Size; ++i) {
6569 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6570 // This entry crosses lanes, so there is no way to model this shuffle.
6573 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6574 if (RepeatedMask[i % LaneSize] == -1)
6575 // This is the first non-undef entry in this slot of a 128-bit lane.
6576 RepeatedMask[i % LaneSize] =
6577 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6578 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6579 // Found a mismatch with the repeated mask.
6585 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6588 /// This is a fast way to test a shuffle mask against a fixed pattern:
6590 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6592 /// It returns true if the mask is exactly as wide as the argument list, and
6593 /// each element of the mask is either -1 (signifying undef) or the value given
6594 /// in the argument.
6595 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6596 ArrayRef<int> ExpectedMask) {
6597 if (Mask.size() != ExpectedMask.size())
6600 int Size = Mask.size();
6602 // If the values are build vectors, we can look through them to find
6603 // equivalent inputs that make the shuffles equivalent.
6604 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6605 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6607 for (int i = 0; i < Size; ++i)
6608 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6609 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6610 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6611 if (!MaskBV || !ExpectedBV ||
6612 MaskBV->getOperand(Mask[i] % Size) !=
6613 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6620 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6622 /// This helper function produces an 8-bit shuffle immediate corresponding to
6623 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6624 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6627 /// NB: We rely heavily on "undef" masks preserving the input lane.
6628 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6629 SelectionDAG &DAG) {
6630 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6631 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6632 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6633 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6634 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6637 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6638 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6639 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6640 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6641 return DAG.getConstant(Imm, DL, MVT::i8);
6644 /// \brief Compute whether each element of a shuffle is zeroable.
6646 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6647 /// Either it is an undef element in the shuffle mask, the element of the input
6648 /// referenced is undef, or the element of the input referenced is known to be
6649 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6650 /// as many lanes with this technique as possible to simplify the remaining
6652 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6653 SDValue V1, SDValue V2) {
6654 SmallBitVector Zeroable(Mask.size(), false);
6656 while (V1.getOpcode() == ISD::BITCAST)
6657 V1 = V1->getOperand(0);
6658 while (V2.getOpcode() == ISD::BITCAST)
6659 V2 = V2->getOperand(0);
6661 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6662 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6664 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6666 // Handle the easy cases.
6667 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6672 // If this is an index into a build_vector node (which has the same number
6673 // of elements), dig out the input value and use it.
6674 SDValue V = M < Size ? V1 : V2;
6675 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6678 SDValue Input = V.getOperand(M % Size);
6679 // The UNDEF opcode check really should be dead code here, but not quite
6680 // worth asserting on (it isn't invalid, just unexpected).
6681 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6688 // X86 has dedicated unpack instructions that can handle specific blend
6689 // operations: UNPCKH and UNPCKL.
6690 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6691 SDValue V1, SDValue V2,
6692 SelectionDAG &DAG) {
6693 int NumElts = VT.getVectorNumElements();
6696 bool UnpcklSwapped = true;
6697 bool UnpckhSwapped = true;
6698 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6700 for (int i = 0; i < NumElts; ++i) {
6701 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6703 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6704 int HiPos = LoPos + NumEltsInLane / 2;
6705 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
6706 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
6710 if (Mask[i] != LoPos)
6712 if (Mask[i] != HiPos)
6714 if (Mask[i] != LoPosSwapped)
6715 UnpcklSwapped = false;
6716 if (Mask[i] != HiPosSwapped)
6717 UnpckhSwapped = false;
6718 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
6722 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6724 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6726 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6728 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6730 llvm_unreachable("Unexpected result of UNPCK mask analysis");
6734 /// \brief Try to emit a bitmask instruction for a shuffle.
6736 /// This handles cases where we can model a blend exactly as a bitmask due to
6737 /// one of the inputs being zeroable.
6738 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6739 SDValue V2, ArrayRef<int> Mask,
6740 SelectionDAG &DAG) {
6741 MVT EltVT = VT.getScalarType();
6742 int NumEltBits = EltVT.getSizeInBits();
6743 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6744 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6745 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6747 if (EltVT.isFloatingPoint()) {
6748 Zero = DAG.getBitcast(EltVT, Zero);
6749 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6751 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6752 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6754 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6757 if (Mask[i] % Size != i)
6758 return SDValue(); // Not a blend.
6760 V = Mask[i] < Size ? V1 : V2;
6761 else if (V != (Mask[i] < Size ? V1 : V2))
6762 return SDValue(); // Can only let one input through the mask.
6764 VMaskOps[i] = AllOnes;
6767 return SDValue(); // No non-zeroable elements!
6769 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6770 V = DAG.getNode(VT.isFloatingPoint()
6771 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6776 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6778 /// This is used as a fallback approach when first class blend instructions are
6779 /// unavailable. Currently it is only suitable for integer vectors, but could
6780 /// be generalized for floating point vectors if desirable.
6781 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6782 SDValue V2, ArrayRef<int> Mask,
6783 SelectionDAG &DAG) {
6784 assert(VT.isInteger() && "Only supports integer vector types!");
6785 MVT EltVT = VT.getScalarType();
6786 int NumEltBits = EltVT.getSizeInBits();
6787 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6788 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6790 SmallVector<SDValue, 16> MaskOps;
6791 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6792 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6793 return SDValue(); // Shuffled input!
6794 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6797 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6798 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6799 // We have to cast V2 around.
6800 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6801 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6802 DAG.getBitcast(MaskVT, V1Mask),
6803 DAG.getBitcast(MaskVT, V2)));
6804 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6807 /// \brief Try to emit a blend instruction for a shuffle.
6809 /// This doesn't do any checks for the availability of instructions for blending
6810 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6811 /// be matched in the backend with the type given. What it does check for is
6812 /// that the shuffle mask is in fact a blend.
6813 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6814 SDValue V2, ArrayRef<int> Mask,
6815 const X86Subtarget *Subtarget,
6816 SelectionDAG &DAG) {
6817 unsigned BlendMask = 0;
6818 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6819 if (Mask[i] >= Size) {
6820 if (Mask[i] != i + Size)
6821 return SDValue(); // Shuffled V2 input!
6822 BlendMask |= 1u << i;
6825 if (Mask[i] >= 0 && Mask[i] != i)
6826 return SDValue(); // Shuffled V1 input!
6828 switch (VT.SimpleTy) {
6833 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6834 DAG.getConstant(BlendMask, DL, MVT::i8));
6838 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6842 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6843 // that instruction.
6844 if (Subtarget->hasAVX2()) {
6845 // Scale the blend by the number of 32-bit dwords per element.
6846 int Scale = VT.getScalarSizeInBits() / 32;
6848 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6849 if (Mask[i] >= Size)
6850 for (int j = 0; j < Scale; ++j)
6851 BlendMask |= 1u << (i * Scale + j);
6853 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6854 V1 = DAG.getBitcast(BlendVT, V1);
6855 V2 = DAG.getBitcast(BlendVT, V2);
6856 return DAG.getBitcast(
6857 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6858 DAG.getConstant(BlendMask, DL, MVT::i8)));
6862 // For integer shuffles we need to expand the mask and cast the inputs to
6863 // v8i16s prior to blending.
6864 int Scale = 8 / VT.getVectorNumElements();
6866 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6867 if (Mask[i] >= Size)
6868 for (int j = 0; j < Scale; ++j)
6869 BlendMask |= 1u << (i * Scale + j);
6871 V1 = DAG.getBitcast(MVT::v8i16, V1);
6872 V2 = DAG.getBitcast(MVT::v8i16, V2);
6873 return DAG.getBitcast(VT,
6874 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6875 DAG.getConstant(BlendMask, DL, MVT::i8)));
6879 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6880 SmallVector<int, 8> RepeatedMask;
6881 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6882 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6883 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6885 for (int i = 0; i < 8; ++i)
6886 if (RepeatedMask[i] >= 16)
6887 BlendMask |= 1u << i;
6888 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6889 DAG.getConstant(BlendMask, DL, MVT::i8));
6895 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6896 "256-bit byte-blends require AVX2 support!");
6898 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6899 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6902 // Scale the blend by the number of bytes per element.
6903 int Scale = VT.getScalarSizeInBits() / 8;
6905 // This form of blend is always done on bytes. Compute the byte vector
6907 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6909 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6910 // mix of LLVM's code generator and the x86 backend. We tell the code
6911 // generator that boolean values in the elements of an x86 vector register
6912 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6913 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6914 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6915 // of the element (the remaining are ignored) and 0 in that high bit would
6916 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6917 // the LLVM model for boolean values in vector elements gets the relevant
6918 // bit set, it is set backwards and over constrained relative to x86's
6920 SmallVector<SDValue, 32> VSELECTMask;
6921 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6922 for (int j = 0; j < Scale; ++j)
6923 VSELECTMask.push_back(
6924 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6925 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6928 V1 = DAG.getBitcast(BlendVT, V1);
6929 V2 = DAG.getBitcast(BlendVT, V2);
6930 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6931 DAG.getNode(ISD::BUILD_VECTOR, DL,
6932 BlendVT, VSELECTMask),
6937 llvm_unreachable("Not a supported integer vector type!");
6941 /// \brief Try to lower as a blend of elements from two inputs followed by
6942 /// a single-input permutation.
6944 /// This matches the pattern where we can blend elements from two inputs and
6945 /// then reduce the shuffle to a single-input permutation.
6946 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6949 SelectionDAG &DAG) {
6950 // We build up the blend mask while checking whether a blend is a viable way
6951 // to reduce the shuffle.
6952 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6953 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6955 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6959 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6961 if (BlendMask[Mask[i] % Size] == -1)
6962 BlendMask[Mask[i] % Size] = Mask[i];
6963 else if (BlendMask[Mask[i] % Size] != Mask[i])
6964 return SDValue(); // Can't blend in the needed input!
6966 PermuteMask[i] = Mask[i] % Size;
6969 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6970 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6973 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6974 /// blends and permutes.
6976 /// This matches the extremely common pattern for handling combined
6977 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6978 /// operations. It will try to pick the best arrangement of shuffles and
6980 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6984 SelectionDAG &DAG) {
6985 // Shuffle the input elements into the desired positions in V1 and V2 and
6986 // blend them together.
6987 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6988 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6989 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6990 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6991 if (Mask[i] >= 0 && Mask[i] < Size) {
6992 V1Mask[i] = Mask[i];
6994 } else if (Mask[i] >= Size) {
6995 V2Mask[i] = Mask[i] - Size;
6996 BlendMask[i] = i + Size;
6999 // Try to lower with the simpler initial blend strategy unless one of the
7000 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7001 // shuffle may be able to fold with a load or other benefit. However, when
7002 // we'll have to do 2x as many shuffles in order to achieve this, blending
7003 // first is a better strategy.
7004 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7005 if (SDValue BlendPerm =
7006 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7009 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7010 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7011 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7014 /// \brief Try to lower a vector shuffle as a byte rotation.
7016 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7017 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7018 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7019 /// try to generically lower a vector shuffle through such an pattern. It
7020 /// does not check for the profitability of lowering either as PALIGNR or
7021 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7022 /// This matches shuffle vectors that look like:
7024 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7026 /// Essentially it concatenates V1 and V2, shifts right by some number of
7027 /// elements, and takes the low elements as the result. Note that while this is
7028 /// specified as a *right shift* because x86 is little-endian, it is a *left
7029 /// rotate* of the vector lanes.
7030 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7033 const X86Subtarget *Subtarget,
7034 SelectionDAG &DAG) {
7035 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7037 int NumElts = Mask.size();
7038 int NumLanes = VT.getSizeInBits() / 128;
7039 int NumLaneElts = NumElts / NumLanes;
7041 // We need to detect various ways of spelling a rotation:
7042 // [11, 12, 13, 14, 15, 0, 1, 2]
7043 // [-1, 12, 13, 14, -1, -1, 1, -1]
7044 // [-1, -1, -1, -1, -1, -1, 1, 2]
7045 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7046 // [-1, 4, 5, 6, -1, -1, 9, -1]
7047 // [-1, 4, 5, 6, -1, -1, -1, -1]
7050 for (int l = 0; l < NumElts; l += NumLaneElts) {
7051 for (int i = 0; i < NumLaneElts; ++i) {
7052 if (Mask[l + i] == -1)
7054 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7056 // Get the mod-Size index and lane correct it.
7057 int LaneIdx = (Mask[l + i] % NumElts) - l;
7058 // Make sure it was in this lane.
7059 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7062 // Determine where a rotated vector would have started.
7063 int StartIdx = i - LaneIdx;
7065 // The identity rotation isn't interesting, stop.
7068 // If we found the tail of a vector the rotation must be the missing
7069 // front. If we found the head of a vector, it must be how much of the
7071 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7074 Rotation = CandidateRotation;
7075 else if (Rotation != CandidateRotation)
7076 // The rotations don't match, so we can't match this mask.
7079 // Compute which value this mask is pointing at.
7080 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7082 // Compute which of the two target values this index should be assigned
7083 // to. This reflects whether the high elements are remaining or the low
7084 // elements are remaining.
7085 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7087 // Either set up this value if we've not encountered it before, or check
7088 // that it remains consistent.
7091 else if (TargetV != MaskV)
7092 // This may be a rotation, but it pulls from the inputs in some
7093 // unsupported interleaving.
7098 // Check that we successfully analyzed the mask, and normalize the results.
7099 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7100 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7106 // The actual rotate instruction rotates bytes, so we need to scale the
7107 // rotation based on how many bytes are in the vector lane.
7108 int Scale = 16 / NumLaneElts;
7110 // SSSE3 targets can use the palignr instruction.
7111 if (Subtarget->hasSSSE3()) {
7112 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7113 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7114 Lo = DAG.getBitcast(AlignVT, Lo);
7115 Hi = DAG.getBitcast(AlignVT, Hi);
7117 return DAG.getBitcast(
7118 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7119 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7122 assert(VT.getSizeInBits() == 128 &&
7123 "Rotate-based lowering only supports 128-bit lowering!");
7124 assert(Mask.size() <= 16 &&
7125 "Can shuffle at most 16 bytes in a 128-bit vector!");
7127 // Default SSE2 implementation
7128 int LoByteShift = 16 - Rotation * Scale;
7129 int HiByteShift = Rotation * Scale;
7131 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7132 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7133 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7135 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7136 DAG.getConstant(LoByteShift, DL, MVT::i8));
7137 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7138 DAG.getConstant(HiByteShift, DL, MVT::i8));
7139 return DAG.getBitcast(VT,
7140 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7143 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7145 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7146 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7147 /// matches elements from one of the input vectors shuffled to the left or
7148 /// right with zeroable elements 'shifted in'. It handles both the strictly
7149 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7152 /// PSHL : (little-endian) left bit shift.
7153 /// [ zz, 0, zz, 2 ]
7154 /// [ -1, 4, zz, -1 ]
7155 /// PSRL : (little-endian) right bit shift.
7157 /// [ -1, -1, 7, zz]
7158 /// PSLLDQ : (little-endian) left byte shift
7159 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7160 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7161 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7162 /// PSRLDQ : (little-endian) right byte shift
7163 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7164 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7165 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7166 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7167 SDValue V2, ArrayRef<int> Mask,
7168 SelectionDAG &DAG) {
7169 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7171 int Size = Mask.size();
7172 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7174 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7175 for (int i = 0; i < Size; i += Scale)
7176 for (int j = 0; j < Shift; ++j)
7177 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7183 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7184 for (int i = 0; i != Size; i += Scale) {
7185 unsigned Pos = Left ? i + Shift : i;
7186 unsigned Low = Left ? i : i + Shift;
7187 unsigned Len = Scale - Shift;
7188 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7189 Low + (V == V1 ? 0 : Size)))
7193 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7194 bool ByteShift = ShiftEltBits > 64;
7195 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7196 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7197 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7199 // Normalize the scale for byte shifts to still produce an i64 element
7201 Scale = ByteShift ? Scale / 2 : Scale;
7203 // We need to round trip through the appropriate type for the shift.
7204 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7205 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7206 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7207 "Illegal integer vector type");
7208 V = DAG.getBitcast(ShiftVT, V);
7210 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7211 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7212 return DAG.getBitcast(VT, V);
7215 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7216 // keep doubling the size of the integer elements up to that. We can
7217 // then shift the elements of the integer vector by whole multiples of
7218 // their width within the elements of the larger integer vector. Test each
7219 // multiple to see if we can find a match with the moved element indices
7220 // and that the shifted in elements are all zeroable.
7221 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7222 for (int Shift = 1; Shift != Scale; ++Shift)
7223 for (bool Left : {true, false})
7224 if (CheckZeros(Shift, Scale, Left))
7225 for (SDValue V : {V1, V2})
7226 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7233 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7234 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7235 SDValue V2, ArrayRef<int> Mask,
7236 SelectionDAG &DAG) {
7237 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7238 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7240 int Size = Mask.size();
7241 int HalfSize = Size / 2;
7242 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7244 // Upper half must be undefined.
7245 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7248 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7249 // Remainder of lower half result is zero and upper half is all undef.
7250 auto LowerAsEXTRQ = [&]() {
7251 // Determine the extraction length from the part of the
7252 // lower half that isn't zeroable.
7254 for (; Len >= 0; --Len)
7255 if (!Zeroable[Len - 1])
7257 assert(Len > 0 && "Zeroable shuffle mask");
7259 // Attempt to match first Len sequential elements from the lower half.
7262 for (int i = 0; i != Len; ++i) {
7266 SDValue &V = (M < Size ? V1 : V2);
7269 // All mask elements must be in the lower half.
7273 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7284 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7285 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7286 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7287 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7288 DAG.getConstant(BitLen, DL, MVT::i8),
7289 DAG.getConstant(BitIdx, DL, MVT::i8));
7292 if (SDValue ExtrQ = LowerAsEXTRQ())
7295 // INSERTQ: Extract lowest Len elements from lower half of second source and
7296 // insert over first source, starting at Idx.
7297 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7298 auto LowerAsInsertQ = [&]() {
7299 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7302 // Attempt to match first source from mask before insertion point.
7303 if (isUndefInRange(Mask, 0, Idx)) {
7305 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7307 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7313 // Extend the extraction length looking to match both the insertion of
7314 // the second source and the remaining elements of the first.
7315 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7320 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7322 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7328 // Match the remaining elements of the lower half.
7329 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7331 } else if ((!Base || (Base == V1)) &&
7332 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7334 } else if ((!Base || (Base == V2)) &&
7335 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7342 // We may not have a base (first source) - this can safely be undefined.
7344 Base = DAG.getUNDEF(VT);
7346 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7347 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7348 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7349 DAG.getConstant(BitLen, DL, MVT::i8),
7350 DAG.getConstant(BitIdx, DL, MVT::i8));
7357 if (SDValue InsertQ = LowerAsInsertQ())
7363 /// \brief Lower a vector shuffle as a zero or any extension.
7365 /// Given a specific number of elements, element bit width, and extension
7366 /// stride, produce either a zero or any extension based on the available
7367 /// features of the subtarget. The extended elements are consecutive and
7368 /// begin and can start from an offseted element index in the input; to
7369 /// avoid excess shuffling the offset must either being in the bottom lane
7370 /// or at the start of a higher lane. All extended elements must be from
7372 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7373 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7374 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7375 assert(Scale > 1 && "Need a scale to extend.");
7376 int EltBits = VT.getScalarSizeInBits();
7377 int NumElements = VT.getVectorNumElements();
7378 int NumEltsPerLane = 128 / EltBits;
7379 int OffsetLane = Offset / NumEltsPerLane;
7380 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7381 "Only 8, 16, and 32 bit elements can be extended.");
7382 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7383 assert(0 <= Offset && "Extension offset must be positive.");
7384 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7385 "Extension offset must be in the first lane or start an upper lane.");
7387 // Check that an index is in same lane as the base offset.
7388 auto SafeOffset = [&](int Idx) {
7389 return OffsetLane == (Idx / NumEltsPerLane);
7392 // Shift along an input so that the offset base moves to the first element.
7393 auto ShuffleOffset = [&](SDValue V) {
7397 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7398 for (int i = 0; i * Scale < NumElements; ++i) {
7399 int SrcIdx = i + Offset;
7400 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7402 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7405 // Found a valid zext mask! Try various lowering strategies based on the
7406 // input type and available ISA extensions.
7407 if (Subtarget->hasSSE41()) {
7408 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7409 // PUNPCK will catch this in a later shuffle match.
7410 if (Offset && Scale == 2 && VT.getSizeInBits() == 128)
7412 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7413 NumElements / Scale);
7414 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7415 return DAG.getBitcast(VT, InputV);
7418 assert(VT.getSizeInBits() == 128 && "Only 128-bit vectors can be extended.");
7420 // For any extends we can cheat for larger element sizes and use shuffle
7421 // instructions that can fold with a load and/or copy.
7422 if (AnyExt && EltBits == 32) {
7423 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7425 return DAG.getBitcast(
7426 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7427 DAG.getBitcast(MVT::v4i32, InputV),
7428 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7430 if (AnyExt && EltBits == 16 && Scale > 2) {
7431 int PSHUFDMask[4] = {Offset / 2, -1,
7432 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7433 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7434 DAG.getBitcast(MVT::v4i32, InputV),
7435 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7436 int PSHUFWMask[4] = {1, -1, -1, -1};
7437 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7438 return DAG.getBitcast(
7439 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7440 DAG.getBitcast(MVT::v8i16, InputV),
7441 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7444 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7446 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7447 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7448 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7450 int LoIdx = Offset * EltBits;
7451 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7452 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7453 DAG.getConstant(EltBits, DL, MVT::i8),
7454 DAG.getConstant(LoIdx, DL, MVT::i8)));
7456 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7457 !SafeOffset(Offset + 1))
7458 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7460 int HiIdx = (Offset + 1) * EltBits;
7461 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7462 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7463 DAG.getConstant(EltBits, DL, MVT::i8),
7464 DAG.getConstant(HiIdx, DL, MVT::i8)));
7465 return DAG.getNode(ISD::BITCAST, DL, VT,
7466 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7469 // If this would require more than 2 unpack instructions to expand, use
7470 // pshufb when available. We can only use more than 2 unpack instructions
7471 // when zero extending i8 elements which also makes it easier to use pshufb.
7472 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7473 assert(NumElements == 16 && "Unexpected byte vector width!");
7474 SDValue PSHUFBMask[16];
7475 for (int i = 0; i < 16; ++i) {
7476 int Idx = Offset + (i / Scale);
7477 PSHUFBMask[i] = DAG.getConstant(
7478 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7480 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7481 return DAG.getBitcast(VT,
7482 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7483 DAG.getNode(ISD::BUILD_VECTOR, DL,
7484 MVT::v16i8, PSHUFBMask)));
7487 // If we are extending from an offset, ensure we start on a boundary that
7488 // we can unpack from.
7489 int AlignToUnpack = Offset % (NumElements / Scale);
7490 if (AlignToUnpack) {
7491 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7492 for (int i = AlignToUnpack; i < NumElements; ++i)
7493 ShMask[i - AlignToUnpack] = i;
7494 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7495 Offset -= AlignToUnpack;
7498 // Otherwise emit a sequence of unpacks.
7500 unsigned UnpackLoHi = X86ISD::UNPCKL;
7501 if (Offset >= (NumElements / 2)) {
7502 UnpackLoHi = X86ISD::UNPCKH;
7503 Offset -= (NumElements / 2);
7506 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7507 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7508 : getZeroVector(InputVT, Subtarget, DAG, DL);
7509 InputV = DAG.getBitcast(InputVT, InputV);
7510 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7514 } while (Scale > 1);
7515 return DAG.getBitcast(VT, InputV);
7518 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7520 /// This routine will try to do everything in its power to cleverly lower
7521 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7522 /// check for the profitability of this lowering, it tries to aggressively
7523 /// match this pattern. It will use all of the micro-architectural details it
7524 /// can to emit an efficient lowering. It handles both blends with all-zero
7525 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7526 /// masking out later).
7528 /// The reason we have dedicated lowering for zext-style shuffles is that they
7529 /// are both incredibly common and often quite performance sensitive.
7530 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7531 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7532 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7533 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7535 int Bits = VT.getSizeInBits();
7536 int NumLanes = Bits / 128;
7537 int NumElements = VT.getVectorNumElements();
7538 int NumEltsPerLane = NumElements / NumLanes;
7539 assert(VT.getScalarSizeInBits() <= 32 &&
7540 "Exceeds 32-bit integer zero extension limit");
7541 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7543 // Define a helper function to check a particular ext-scale and lower to it if
7545 auto Lower = [&](int Scale) -> SDValue {
7550 for (int i = 0; i < NumElements; ++i) {
7553 continue; // Valid anywhere but doesn't tell us anything.
7554 if (i % Scale != 0) {
7555 // Each of the extended elements need to be zeroable.
7559 // We no longer are in the anyext case.
7564 // Each of the base elements needs to be consecutive indices into the
7565 // same input vector.
7566 SDValue V = M < NumElements ? V1 : V2;
7567 M = M % NumElements;
7570 Offset = M - (i / Scale);
7571 } else if (InputV != V)
7572 return SDValue(); // Flip-flopping inputs.
7574 // Offset must start in the lowest 128-bit lane or at the start of an
7576 // FIXME: Is it ever worth allowing a negative base offset?
7577 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7578 (Offset % NumEltsPerLane) == 0))
7581 // If we are offsetting, all referenced entries must come from the same
7583 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7586 if ((M % NumElements) != (Offset + (i / Scale)))
7587 return SDValue(); // Non-consecutive strided elements.
7591 // If we fail to find an input, we have a zero-shuffle which should always
7592 // have already been handled.
7593 // FIXME: Maybe handle this here in case during blending we end up with one?
7597 // If we are offsetting, don't extend if we only match a single input, we
7598 // can always do better by using a basic PSHUF or PUNPCK.
7599 if (Offset != 0 && Matches < 2)
7602 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7603 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7606 // The widest scale possible for extending is to a 64-bit integer.
7607 assert(Bits % 64 == 0 &&
7608 "The number of bits in a vector must be divisible by 64 on x86!");
7609 int NumExtElements = Bits / 64;
7611 // Each iteration, try extending the elements half as much, but into twice as
7613 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7614 assert(NumElements % NumExtElements == 0 &&
7615 "The input vector size must be divisible by the extended size.");
7616 if (SDValue V = Lower(NumElements / NumExtElements))
7620 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7624 // Returns one of the source operands if the shuffle can be reduced to a
7625 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7626 auto CanZExtLowHalf = [&]() {
7627 for (int i = NumElements / 2; i != NumElements; ++i)
7630 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7632 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7637 if (SDValue V = CanZExtLowHalf()) {
7638 V = DAG.getBitcast(MVT::v2i64, V);
7639 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7640 return DAG.getBitcast(VT, V);
7643 // No viable ext lowering found.
7647 /// \brief Try to get a scalar value for a specific element of a vector.
7649 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7650 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7651 SelectionDAG &DAG) {
7652 MVT VT = V.getSimpleValueType();
7653 MVT EltVT = VT.getVectorElementType();
7654 while (V.getOpcode() == ISD::BITCAST)
7655 V = V.getOperand(0);
7656 // If the bitcasts shift the element size, we can't extract an equivalent
7658 MVT NewVT = V.getSimpleValueType();
7659 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7662 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7663 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7664 // Ensure the scalar operand is the same size as the destination.
7665 // FIXME: Add support for scalar truncation where possible.
7666 SDValue S = V.getOperand(Idx);
7667 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7668 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7674 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7676 /// This is particularly important because the set of instructions varies
7677 /// significantly based on whether the operand is a load or not.
7678 static bool isShuffleFoldableLoad(SDValue V) {
7679 while (V.getOpcode() == ISD::BITCAST)
7680 V = V.getOperand(0);
7682 return ISD::isNON_EXTLoad(V.getNode());
7685 /// \brief Try to lower insertion of a single element into a zero vector.
7687 /// This is a common pattern that we have especially efficient patterns to lower
7688 /// across all subtarget feature sets.
7689 static SDValue lowerVectorShuffleAsElementInsertion(
7690 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7691 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7692 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7694 MVT EltVT = VT.getVectorElementType();
7696 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7697 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7699 bool IsV1Zeroable = true;
7700 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7701 if (i != V2Index && !Zeroable[i]) {
7702 IsV1Zeroable = false;
7706 // Check for a single input from a SCALAR_TO_VECTOR node.
7707 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7708 // all the smarts here sunk into that routine. However, the current
7709 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7710 // vector shuffle lowering is dead.
7711 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7713 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7714 // We need to zext the scalar if it is smaller than an i32.
7715 V2S = DAG.getBitcast(EltVT, V2S);
7716 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7717 // Using zext to expand a narrow element won't work for non-zero
7722 // Zero-extend directly to i32.
7724 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7726 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7727 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7728 EltVT == MVT::i16) {
7729 // Either not inserting from the low element of the input or the input
7730 // element size is too small to use VZEXT_MOVL to clear the high bits.
7734 if (!IsV1Zeroable) {
7735 // If V1 can't be treated as a zero vector we have fewer options to lower
7736 // this. We can't support integer vectors or non-zero targets cheaply, and
7737 // the V1 elements can't be permuted in any way.
7738 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7739 if (!VT.isFloatingPoint() || V2Index != 0)
7741 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7742 V1Mask[V2Index] = -1;
7743 if (!isNoopShuffleMask(V1Mask))
7745 // This is essentially a special case blend operation, but if we have
7746 // general purpose blend operations, they are always faster. Bail and let
7747 // the rest of the lowering handle these as blends.
7748 if (Subtarget->hasSSE41())
7751 // Otherwise, use MOVSD or MOVSS.
7752 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7753 "Only two types of floating point element types to handle!");
7754 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7758 // This lowering only works for the low element with floating point vectors.
7759 if (VT.isFloatingPoint() && V2Index != 0)
7762 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7764 V2 = DAG.getBitcast(VT, V2);
7767 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7768 // the desired position. Otherwise it is more efficient to do a vector
7769 // shift left. We know that we can do a vector shift left because all
7770 // the inputs are zero.
7771 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7772 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7773 V2Shuffle[V2Index] = 0;
7774 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7776 V2 = DAG.getBitcast(MVT::v2i64, V2);
7778 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7779 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7780 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7781 DAG.getDataLayout(), VT)));
7782 V2 = DAG.getBitcast(VT, V2);
7788 /// \brief Try to lower broadcast of a single element.
7790 /// For convenience, this code also bundles all of the subtarget feature set
7791 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7792 /// a convenient way to factor it out.
7793 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7795 const X86Subtarget *Subtarget,
7796 SelectionDAG &DAG) {
7797 if (!Subtarget->hasAVX())
7799 if (VT.isInteger() && !Subtarget->hasAVX2())
7802 // Check that the mask is a broadcast.
7803 int BroadcastIdx = -1;
7805 if (M >= 0 && BroadcastIdx == -1)
7807 else if (M >= 0 && M != BroadcastIdx)
7810 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7811 "a sorted mask where the broadcast "
7814 // Go up the chain of (vector) values to find a scalar load that we can
7815 // combine with the broadcast.
7817 switch (V.getOpcode()) {
7818 case ISD::CONCAT_VECTORS: {
7819 int OperandSize = Mask.size() / V.getNumOperands();
7820 V = V.getOperand(BroadcastIdx / OperandSize);
7821 BroadcastIdx %= OperandSize;
7825 case ISD::INSERT_SUBVECTOR: {
7826 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7827 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7831 int BeginIdx = (int)ConstantIdx->getZExtValue();
7833 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7834 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7835 BroadcastIdx -= BeginIdx;
7846 // Check if this is a broadcast of a scalar. We special case lowering
7847 // for scalars so that we can more effectively fold with loads.
7848 // First, look through bitcast: if the original value has a larger element
7849 // type than the shuffle, the broadcast element is in essence truncated.
7850 // Make that explicit to ease folding.
7851 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7852 EVT EltVT = VT.getVectorElementType();
7853 SDValue V0 = V.getOperand(0);
7854 EVT V0VT = V0.getValueType();
7856 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7857 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7858 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7859 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7864 // Also check the simpler case, where we can directly reuse the scalar.
7865 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7866 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7867 V = V.getOperand(BroadcastIdx);
7869 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7870 // Only AVX2 has register broadcasts.
7871 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7873 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7874 // We can't broadcast from a vector register without AVX2, and we can only
7875 // broadcast from the zero-element of a vector register.
7879 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7882 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7883 // INSERTPS when the V1 elements are already in the correct locations
7884 // because otherwise we can just always use two SHUFPS instructions which
7885 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7886 // perform INSERTPS if a single V1 element is out of place and all V2
7887 // elements are zeroable.
7888 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7890 SelectionDAG &DAG) {
7891 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7892 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7893 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7894 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7896 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7899 int V1DstIndex = -1;
7900 int V2DstIndex = -1;
7901 bool V1UsedInPlace = false;
7903 for (int i = 0; i < 4; ++i) {
7904 // Synthesize a zero mask from the zeroable elements (includes undefs).
7910 // Flag if we use any V1 inputs in place.
7912 V1UsedInPlace = true;
7916 // We can only insert a single non-zeroable element.
7917 if (V1DstIndex != -1 || V2DstIndex != -1)
7921 // V1 input out of place for insertion.
7924 // V2 input for insertion.
7929 // Don't bother if we have no (non-zeroable) element for insertion.
7930 if (V1DstIndex == -1 && V2DstIndex == -1)
7933 // Determine element insertion src/dst indices. The src index is from the
7934 // start of the inserted vector, not the start of the concatenated vector.
7935 unsigned V2SrcIndex = 0;
7936 if (V1DstIndex != -1) {
7937 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7938 // and don't use the original V2 at all.
7939 V2SrcIndex = Mask[V1DstIndex];
7940 V2DstIndex = V1DstIndex;
7943 V2SrcIndex = Mask[V2DstIndex] - 4;
7946 // If no V1 inputs are used in place, then the result is created only from
7947 // the zero mask and the V2 insertion - so remove V1 dependency.
7949 V1 = DAG.getUNDEF(MVT::v4f32);
7951 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7952 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7954 // Insert the V2 element into the desired position.
7956 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7957 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7960 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7961 /// UNPCK instruction.
7963 /// This specifically targets cases where we end up with alternating between
7964 /// the two inputs, and so can permute them into something that feeds a single
7965 /// UNPCK instruction. Note that this routine only targets integer vectors
7966 /// because for floating point vectors we have a generalized SHUFPS lowering
7967 /// strategy that handles everything that doesn't *exactly* match an unpack,
7968 /// making this clever lowering unnecessary.
7969 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
7970 SDValue V1, SDValue V2,
7972 SelectionDAG &DAG) {
7973 assert(!VT.isFloatingPoint() &&
7974 "This routine only supports integer vectors.");
7975 assert(!isSingleInputShuffleMask(Mask) &&
7976 "This routine should only be used when blending two inputs.");
7977 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7979 int Size = Mask.size();
7981 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7982 return M >= 0 && M % Size < Size / 2;
7984 int NumHiInputs = std::count_if(
7985 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7987 bool UnpackLo = NumLoInputs >= NumHiInputs;
7989 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7990 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7991 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7993 for (int i = 0; i < Size; ++i) {
7997 // Each element of the unpack contains Scale elements from this mask.
7998 int UnpackIdx = i / Scale;
8000 // We only handle the case where V1 feeds the first slots of the unpack.
8001 // We rely on canonicalization to ensure this is the case.
8002 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8005 // Setup the mask for this input. The indexing is tricky as we have to
8006 // handle the unpack stride.
8007 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8008 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8012 // If we will have to shuffle both inputs to use the unpack, check whether
8013 // we can just unpack first and shuffle the result. If so, skip this unpack.
8014 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8015 !isNoopShuffleMask(V2Mask))
8018 // Shuffle the inputs into place.
8019 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8020 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8022 // Cast the inputs to the type we will use to unpack them.
8023 V1 = DAG.getBitcast(UnpackVT, V1);
8024 V2 = DAG.getBitcast(UnpackVT, V2);
8026 // Unpack the inputs and cast the result back to the desired type.
8027 return DAG.getBitcast(
8028 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8032 // We try each unpack from the largest to the smallest to try and find one
8033 // that fits this mask.
8034 int OrigNumElements = VT.getVectorNumElements();
8035 int OrigScalarSize = VT.getScalarSizeInBits();
8036 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8037 int Scale = ScalarSize / OrigScalarSize;
8038 int NumElements = OrigNumElements / Scale;
8039 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8040 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8044 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8046 if (NumLoInputs == 0 || NumHiInputs == 0) {
8047 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8048 "We have to have *some* inputs!");
8049 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8051 // FIXME: We could consider the total complexity of the permute of each
8052 // possible unpacking. Or at the least we should consider how many
8053 // half-crossings are created.
8054 // FIXME: We could consider commuting the unpacks.
8056 SmallVector<int, 32> PermMask;
8057 PermMask.assign(Size, -1);
8058 for (int i = 0; i < Size; ++i) {
8062 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8065 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8067 return DAG.getVectorShuffle(
8068 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8070 DAG.getUNDEF(VT), PermMask);
8076 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8078 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8079 /// support for floating point shuffles but not integer shuffles. These
8080 /// instructions will incur a domain crossing penalty on some chips though so
8081 /// it is better to avoid lowering through this for integer vectors where
8083 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8084 const X86Subtarget *Subtarget,
8085 SelectionDAG &DAG) {
8087 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8088 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8089 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8090 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8091 ArrayRef<int> Mask = SVOp->getMask();
8092 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8094 if (isSingleInputShuffleMask(Mask)) {
8095 // Use low duplicate instructions for masks that match their pattern.
8096 if (Subtarget->hasSSE3())
8097 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8098 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8100 // Straight shuffle of a single input vector. Simulate this by using the
8101 // single input as both of the "inputs" to this instruction..
8102 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8104 if (Subtarget->hasAVX()) {
8105 // If we have AVX, we can use VPERMILPS which will allow folding a load
8106 // into the shuffle.
8107 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8108 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8111 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8112 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8114 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8115 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8117 // If we have a single input, insert that into V1 if we can do so cheaply.
8118 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8119 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8120 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8122 // Try inverting the insertion since for v2 masks it is easy to do and we
8123 // can't reliably sort the mask one way or the other.
8124 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8125 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8126 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8127 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8131 // Try to use one of the special instruction patterns to handle two common
8132 // blend patterns if a zero-blend above didn't work.
8133 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8134 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8135 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8136 // We can either use a special instruction to load over the low double or
8137 // to move just the low double.
8139 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8141 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8143 if (Subtarget->hasSSE41())
8144 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8148 // Use dedicated unpack instructions for masks that match their pattern.
8149 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8150 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8151 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8152 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8154 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8155 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8156 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8159 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8161 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8162 /// the integer unit to minimize domain crossing penalties. However, for blends
8163 /// it falls back to the floating point shuffle operation with appropriate bit
8165 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8166 const X86Subtarget *Subtarget,
8167 SelectionDAG &DAG) {
8169 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8170 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8171 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8172 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8173 ArrayRef<int> Mask = SVOp->getMask();
8174 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8176 if (isSingleInputShuffleMask(Mask)) {
8177 // Check for being able to broadcast a single element.
8178 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8179 Mask, Subtarget, DAG))
8182 // Straight shuffle of a single input vector. For everything from SSE2
8183 // onward this has a single fast instruction with no scary immediates.
8184 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8185 V1 = DAG.getBitcast(MVT::v4i32, V1);
8186 int WidenedMask[4] = {
8187 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8188 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8189 return DAG.getBitcast(
8191 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8192 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8194 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8195 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8196 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8197 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8199 // If we have a blend of two PACKUS operations an the blend aligns with the
8200 // low and half halves, we can just merge the PACKUS operations. This is
8201 // particularly important as it lets us merge shuffles that this routine itself
8203 auto GetPackNode = [](SDValue V) {
8204 while (V.getOpcode() == ISD::BITCAST)
8205 V = V.getOperand(0);
8207 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8209 if (SDValue V1Pack = GetPackNode(V1))
8210 if (SDValue V2Pack = GetPackNode(V2))
8211 return DAG.getBitcast(MVT::v2i64,
8212 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8213 Mask[0] == 0 ? V1Pack.getOperand(0)
8214 : V1Pack.getOperand(1),
8215 Mask[1] == 2 ? V2Pack.getOperand(0)
8216 : V2Pack.getOperand(1)));
8218 // Try to use shift instructions.
8220 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8223 // When loading a scalar and then shuffling it into a vector we can often do
8224 // the insertion cheaply.
8225 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8226 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8228 // Try inverting the insertion since for v2 masks it is easy to do and we
8229 // can't reliably sort the mask one way or the other.
8230 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8231 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8232 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8235 // We have different paths for blend lowering, but they all must use the
8236 // *exact* same predicate.
8237 bool IsBlendSupported = Subtarget->hasSSE41();
8238 if (IsBlendSupported)
8239 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8243 // Use dedicated unpack instructions for masks that match their pattern.
8244 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8245 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8246 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8247 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8249 // Try to use byte rotation instructions.
8250 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8251 if (Subtarget->hasSSSE3())
8252 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8253 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8256 // If we have direct support for blends, we should lower by decomposing into
8257 // a permute. That will be faster than the domain cross.
8258 if (IsBlendSupported)
8259 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8262 // We implement this with SHUFPD which is pretty lame because it will likely
8263 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8264 // However, all the alternatives are still more cycles and newer chips don't
8265 // have this problem. It would be really nice if x86 had better shuffles here.
8266 V1 = DAG.getBitcast(MVT::v2f64, V1);
8267 V2 = DAG.getBitcast(MVT::v2f64, V2);
8268 return DAG.getBitcast(MVT::v2i64,
8269 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8272 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8274 /// This is used to disable more specialized lowerings when the shufps lowering
8275 /// will happen to be efficient.
8276 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8277 // This routine only handles 128-bit shufps.
8278 assert(Mask.size() == 4 && "Unsupported mask size!");
8280 // To lower with a single SHUFPS we need to have the low half and high half
8281 // each requiring a single input.
8282 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8284 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8290 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8292 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8293 /// It makes no assumptions about whether this is the *best* lowering, it simply
8295 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8296 ArrayRef<int> Mask, SDValue V1,
8297 SDValue V2, SelectionDAG &DAG) {
8298 SDValue LowV = V1, HighV = V2;
8299 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8302 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8304 if (NumV2Elements == 1) {
8306 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8309 // Compute the index adjacent to V2Index and in the same half by toggling
8311 int V2AdjIndex = V2Index ^ 1;
8313 if (Mask[V2AdjIndex] == -1) {
8314 // Handles all the cases where we have a single V2 element and an undef.
8315 // This will only ever happen in the high lanes because we commute the
8316 // vector otherwise.
8318 std::swap(LowV, HighV);
8319 NewMask[V2Index] -= 4;
8321 // Handle the case where the V2 element ends up adjacent to a V1 element.
8322 // To make this work, blend them together as the first step.
8323 int V1Index = V2AdjIndex;
8324 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8325 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8326 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8328 // Now proceed to reconstruct the final blend as we have the necessary
8329 // high or low half formed.
8336 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8337 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8339 } else if (NumV2Elements == 2) {
8340 if (Mask[0] < 4 && Mask[1] < 4) {
8341 // Handle the easy case where we have V1 in the low lanes and V2 in the
8345 } else if (Mask[2] < 4 && Mask[3] < 4) {
8346 // We also handle the reversed case because this utility may get called
8347 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8348 // arrange things in the right direction.
8354 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8355 // trying to place elements directly, just blend them and set up the final
8356 // shuffle to place them.
8358 // The first two blend mask elements are for V1, the second two are for
8360 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8361 Mask[2] < 4 ? Mask[2] : Mask[3],
8362 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8363 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8364 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8365 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8367 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8370 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8371 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8372 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8373 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8376 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8377 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8380 /// \brief Lower 4-lane 32-bit floating point shuffles.
8382 /// Uses instructions exclusively from the floating point unit to minimize
8383 /// domain crossing penalties, as these are sufficient to implement all v4f32
8385 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8386 const X86Subtarget *Subtarget,
8387 SelectionDAG &DAG) {
8389 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8390 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8391 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8392 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8393 ArrayRef<int> Mask = SVOp->getMask();
8394 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8397 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8399 if (NumV2Elements == 0) {
8400 // Check for being able to broadcast a single element.
8401 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8402 Mask, Subtarget, DAG))
8405 // Use even/odd duplicate instructions for masks that match their pattern.
8406 if (Subtarget->hasSSE3()) {
8407 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8408 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8409 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8410 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8413 if (Subtarget->hasAVX()) {
8414 // If we have AVX, we can use VPERMILPS which will allow folding a load
8415 // into the shuffle.
8416 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8417 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8420 // Otherwise, use a straight shuffle of a single input vector. We pass the
8421 // input vector to both operands to simulate this with a SHUFPS.
8422 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8423 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8426 // There are special ways we can lower some single-element blends. However, we
8427 // have custom ways we can lower more complex single-element blends below that
8428 // we defer to if both this and BLENDPS fail to match, so restrict this to
8429 // when the V2 input is targeting element 0 of the mask -- that is the fast
8431 if (NumV2Elements == 1 && Mask[0] >= 4)
8432 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8433 Mask, Subtarget, DAG))
8436 if (Subtarget->hasSSE41()) {
8437 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8441 // Use INSERTPS if we can complete the shuffle efficiently.
8442 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8445 if (!isSingleSHUFPSMask(Mask))
8446 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8447 DL, MVT::v4f32, V1, V2, Mask, DAG))
8451 // Use dedicated unpack instructions for masks that match their pattern.
8452 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8453 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8454 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8455 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8456 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8457 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8458 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8459 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8461 // Otherwise fall back to a SHUFPS lowering strategy.
8462 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8465 /// \brief Lower 4-lane i32 vector shuffles.
8467 /// We try to handle these with integer-domain shuffles where we can, but for
8468 /// blends we use the floating point domain blend instructions.
8469 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8470 const X86Subtarget *Subtarget,
8471 SelectionDAG &DAG) {
8473 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8474 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8475 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8476 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8477 ArrayRef<int> Mask = SVOp->getMask();
8478 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8480 // Whenever we can lower this as a zext, that instruction is strictly faster
8481 // than any alternative. It also allows us to fold memory operands into the
8482 // shuffle in many cases.
8483 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8484 Mask, Subtarget, DAG))
8488 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8490 if (NumV2Elements == 0) {
8491 // Check for being able to broadcast a single element.
8492 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8493 Mask, Subtarget, DAG))
8496 // Straight shuffle of a single input vector. For everything from SSE2
8497 // onward this has a single fast instruction with no scary immediates.
8498 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8499 // but we aren't actually going to use the UNPCK instruction because doing
8500 // so prevents folding a load into this instruction or making a copy.
8501 const int UnpackLoMask[] = {0, 0, 1, 1};
8502 const int UnpackHiMask[] = {2, 2, 3, 3};
8503 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8504 Mask = UnpackLoMask;
8505 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8506 Mask = UnpackHiMask;
8508 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8509 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8512 // Try to use shift instructions.
8514 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8517 // There are special ways we can lower some single-element blends.
8518 if (NumV2Elements == 1)
8519 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8520 Mask, Subtarget, DAG))
8523 // We have different paths for blend lowering, but they all must use the
8524 // *exact* same predicate.
8525 bool IsBlendSupported = Subtarget->hasSSE41();
8526 if (IsBlendSupported)
8527 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8531 if (SDValue Masked =
8532 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8535 // Use dedicated unpack instructions for masks that match their pattern.
8536 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8537 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8538 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8539 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8540 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8541 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8542 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8543 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8545 // Try to use byte rotation instructions.
8546 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8547 if (Subtarget->hasSSSE3())
8548 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8549 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8552 // If we have direct support for blends, we should lower by decomposing into
8553 // a permute. That will be faster than the domain cross.
8554 if (IsBlendSupported)
8555 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8558 // Try to lower by permuting the inputs into an unpack instruction.
8559 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8563 // We implement this with SHUFPS because it can blend from two vectors.
8564 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8565 // up the inputs, bypassing domain shift penalties that we would encur if we
8566 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8568 return DAG.getBitcast(
8570 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8571 DAG.getBitcast(MVT::v4f32, V2), Mask));
8574 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8575 /// shuffle lowering, and the most complex part.
8577 /// The lowering strategy is to try to form pairs of input lanes which are
8578 /// targeted at the same half of the final vector, and then use a dword shuffle
8579 /// to place them onto the right half, and finally unpack the paired lanes into
8580 /// their final position.
8582 /// The exact breakdown of how to form these dword pairs and align them on the
8583 /// correct sides is really tricky. See the comments within the function for
8584 /// more of the details.
8586 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8587 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8588 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8589 /// vector, form the analogous 128-bit 8-element Mask.
8590 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8591 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8592 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8593 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8594 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8596 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8597 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8598 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8600 SmallVector<int, 4> LoInputs;
8601 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8602 [](int M) { return M >= 0; });
8603 std::sort(LoInputs.begin(), LoInputs.end());
8604 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8605 SmallVector<int, 4> HiInputs;
8606 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8607 [](int M) { return M >= 0; });
8608 std::sort(HiInputs.begin(), HiInputs.end());
8609 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8611 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8612 int NumHToL = LoInputs.size() - NumLToL;
8614 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8615 int NumHToH = HiInputs.size() - NumLToH;
8616 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8617 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8618 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8619 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8621 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8622 // such inputs we can swap two of the dwords across the half mark and end up
8623 // with <=2 inputs to each half in each half. Once there, we can fall through
8624 // to the generic code below. For example:
8626 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8627 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8629 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8630 // and an existing 2-into-2 on the other half. In this case we may have to
8631 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8632 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8633 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8634 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8635 // half than the one we target for fixing) will be fixed when we re-enter this
8636 // path. We will also combine away any sequence of PSHUFD instructions that
8637 // result into a single instruction. Here is an example of the tricky case:
8639 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8640 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8642 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8644 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8645 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8647 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8648 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8650 // The result is fine to be handled by the generic logic.
8651 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8652 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8653 int AOffset, int BOffset) {
8654 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8655 "Must call this with A having 3 or 1 inputs from the A half.");
8656 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8657 "Must call this with B having 1 or 3 inputs from the B half.");
8658 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8659 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8661 bool ThreeAInputs = AToAInputs.size() == 3;
8663 // Compute the index of dword with only one word among the three inputs in
8664 // a half by taking the sum of the half with three inputs and subtracting
8665 // the sum of the actual three inputs. The difference is the remaining
8668 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8669 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8670 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8671 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8672 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8673 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8674 int TripleNonInputIdx =
8675 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8676 TripleDWord = TripleNonInputIdx / 2;
8678 // We use xor with one to compute the adjacent DWord to whichever one the
8680 OneInputDWord = (OneInput / 2) ^ 1;
8682 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8683 // and BToA inputs. If there is also such a problem with the BToB and AToB
8684 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8685 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8686 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8687 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8688 // Compute how many inputs will be flipped by swapping these DWords. We
8690 // to balance this to ensure we don't form a 3-1 shuffle in the other
8692 int NumFlippedAToBInputs =
8693 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8694 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8695 int NumFlippedBToBInputs =
8696 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8697 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8698 if ((NumFlippedAToBInputs == 1 &&
8699 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8700 (NumFlippedBToBInputs == 1 &&
8701 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8702 // We choose whether to fix the A half or B half based on whether that
8703 // half has zero flipped inputs. At zero, we may not be able to fix it
8704 // with that half. We also bias towards fixing the B half because that
8705 // will more commonly be the high half, and we have to bias one way.
8706 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8707 ArrayRef<int> Inputs) {
8708 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8709 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8710 PinnedIdx ^ 1) != Inputs.end();
8711 // Determine whether the free index is in the flipped dword or the
8712 // unflipped dword based on where the pinned index is. We use this bit
8713 // in an xor to conditionally select the adjacent dword.
8714 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8715 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8716 FixFreeIdx) != Inputs.end();
8717 if (IsFixIdxInput == IsFixFreeIdxInput)
8719 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8720 FixFreeIdx) != Inputs.end();
8721 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8722 "We need to be changing the number of flipped inputs!");
8723 int PSHUFHalfMask[] = {0, 1, 2, 3};
8724 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8725 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8727 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8730 if (M != -1 && M == FixIdx)
8732 else if (M != -1 && M == FixFreeIdx)
8735 if (NumFlippedBToBInputs != 0) {
8737 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8738 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8740 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8741 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8742 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8747 int PSHUFDMask[] = {0, 1, 2, 3};
8748 PSHUFDMask[ADWord] = BDWord;
8749 PSHUFDMask[BDWord] = ADWord;
8752 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8753 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8755 // Adjust the mask to match the new locations of A and B.
8757 if (M != -1 && M/2 == ADWord)
8758 M = 2 * BDWord + M % 2;
8759 else if (M != -1 && M/2 == BDWord)
8760 M = 2 * ADWord + M % 2;
8762 // Recurse back into this routine to re-compute state now that this isn't
8763 // a 3 and 1 problem.
8764 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8767 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8768 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8769 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8770 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8772 // At this point there are at most two inputs to the low and high halves from
8773 // each half. That means the inputs can always be grouped into dwords and
8774 // those dwords can then be moved to the correct half with a dword shuffle.
8775 // We use at most one low and one high word shuffle to collect these paired
8776 // inputs into dwords, and finally a dword shuffle to place them.
8777 int PSHUFLMask[4] = {-1, -1, -1, -1};
8778 int PSHUFHMask[4] = {-1, -1, -1, -1};
8779 int PSHUFDMask[4] = {-1, -1, -1, -1};
8781 // First fix the masks for all the inputs that are staying in their
8782 // original halves. This will then dictate the targets of the cross-half
8784 auto fixInPlaceInputs =
8785 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8786 MutableArrayRef<int> SourceHalfMask,
8787 MutableArrayRef<int> HalfMask, int HalfOffset) {
8788 if (InPlaceInputs.empty())
8790 if (InPlaceInputs.size() == 1) {
8791 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8792 InPlaceInputs[0] - HalfOffset;
8793 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8796 if (IncomingInputs.empty()) {
8797 // Just fix all of the in place inputs.
8798 for (int Input : InPlaceInputs) {
8799 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8800 PSHUFDMask[Input / 2] = Input / 2;
8805 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8806 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8807 InPlaceInputs[0] - HalfOffset;
8808 // Put the second input next to the first so that they are packed into
8809 // a dword. We find the adjacent index by toggling the low bit.
8810 int AdjIndex = InPlaceInputs[0] ^ 1;
8811 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8812 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8813 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8815 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8816 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8818 // Now gather the cross-half inputs and place them into a free dword of
8819 // their target half.
8820 // FIXME: This operation could almost certainly be simplified dramatically to
8821 // look more like the 3-1 fixing operation.
8822 auto moveInputsToRightHalf = [&PSHUFDMask](
8823 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8824 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8825 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8827 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8828 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8830 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8832 int LowWord = Word & ~1;
8833 int HighWord = Word | 1;
8834 return isWordClobbered(SourceHalfMask, LowWord) ||
8835 isWordClobbered(SourceHalfMask, HighWord);
8838 if (IncomingInputs.empty())
8841 if (ExistingInputs.empty()) {
8842 // Map any dwords with inputs from them into the right half.
8843 for (int Input : IncomingInputs) {
8844 // If the source half mask maps over the inputs, turn those into
8845 // swaps and use the swapped lane.
8846 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8847 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8848 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8849 Input - SourceOffset;
8850 // We have to swap the uses in our half mask in one sweep.
8851 for (int &M : HalfMask)
8852 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8854 else if (M == Input)
8855 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8857 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8858 Input - SourceOffset &&
8859 "Previous placement doesn't match!");
8861 // Note that this correctly re-maps both when we do a swap and when
8862 // we observe the other side of the swap above. We rely on that to
8863 // avoid swapping the members of the input list directly.
8864 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8867 // Map the input's dword into the correct half.
8868 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8869 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8871 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8873 "Previous placement doesn't match!");
8876 // And just directly shift any other-half mask elements to be same-half
8877 // as we will have mirrored the dword containing the element into the
8878 // same position within that half.
8879 for (int &M : HalfMask)
8880 if (M >= SourceOffset && M < SourceOffset + 4) {
8881 M = M - SourceOffset + DestOffset;
8882 assert(M >= 0 && "This should never wrap below zero!");
8887 // Ensure we have the input in a viable dword of its current half. This
8888 // is particularly tricky because the original position may be clobbered
8889 // by inputs being moved and *staying* in that half.
8890 if (IncomingInputs.size() == 1) {
8891 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8892 int InputFixed = std::find(std::begin(SourceHalfMask),
8893 std::end(SourceHalfMask), -1) -
8894 std::begin(SourceHalfMask) + SourceOffset;
8895 SourceHalfMask[InputFixed - SourceOffset] =
8896 IncomingInputs[0] - SourceOffset;
8897 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8899 IncomingInputs[0] = InputFixed;
8901 } else if (IncomingInputs.size() == 2) {
8902 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8903 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8904 // We have two non-adjacent or clobbered inputs we need to extract from
8905 // the source half. To do this, we need to map them into some adjacent
8906 // dword slot in the source mask.
8907 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8908 IncomingInputs[1] - SourceOffset};
8910 // If there is a free slot in the source half mask adjacent to one of
8911 // the inputs, place the other input in it. We use (Index XOR 1) to
8912 // compute an adjacent index.
8913 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8914 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8915 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8916 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8917 InputsFixed[1] = InputsFixed[0] ^ 1;
8918 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8919 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8920 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8921 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8922 InputsFixed[0] = InputsFixed[1] ^ 1;
8923 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8924 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8925 // The two inputs are in the same DWord but it is clobbered and the
8926 // adjacent DWord isn't used at all. Move both inputs to the free
8928 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8929 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8930 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8931 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8933 // The only way we hit this point is if there is no clobbering
8934 // (because there are no off-half inputs to this half) and there is no
8935 // free slot adjacent to one of the inputs. In this case, we have to
8936 // swap an input with a non-input.
8937 for (int i = 0; i < 4; ++i)
8938 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8939 "We can't handle any clobbers here!");
8940 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8941 "Cannot have adjacent inputs here!");
8943 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8944 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8946 // We also have to update the final source mask in this case because
8947 // it may need to undo the above swap.
8948 for (int &M : FinalSourceHalfMask)
8949 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8950 M = InputsFixed[1] + SourceOffset;
8951 else if (M == InputsFixed[1] + SourceOffset)
8952 M = (InputsFixed[0] ^ 1) + SourceOffset;
8954 InputsFixed[1] = InputsFixed[0] ^ 1;
8957 // Point everything at the fixed inputs.
8958 for (int &M : HalfMask)
8959 if (M == IncomingInputs[0])
8960 M = InputsFixed[0] + SourceOffset;
8961 else if (M == IncomingInputs[1])
8962 M = InputsFixed[1] + SourceOffset;
8964 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8965 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8968 llvm_unreachable("Unhandled input size!");
8971 // Now hoist the DWord down to the right half.
8972 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8973 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8974 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8975 for (int &M : HalfMask)
8976 for (int Input : IncomingInputs)
8978 M = FreeDWord * 2 + Input % 2;
8980 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8981 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8982 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8983 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8985 // Now enact all the shuffles we've computed to move the inputs into their
8987 if (!isNoopShuffleMask(PSHUFLMask))
8988 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8989 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8990 if (!isNoopShuffleMask(PSHUFHMask))
8991 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8992 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8993 if (!isNoopShuffleMask(PSHUFDMask))
8996 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8997 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8999 // At this point, each half should contain all its inputs, and we can then
9000 // just shuffle them into their final position.
9001 assert(std::count_if(LoMask.begin(), LoMask.end(),
9002 [](int M) { return M >= 4; }) == 0 &&
9003 "Failed to lift all the high half inputs to the low mask!");
9004 assert(std::count_if(HiMask.begin(), HiMask.end(),
9005 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9006 "Failed to lift all the low half inputs to the high mask!");
9008 // Do a half shuffle for the low mask.
9009 if (!isNoopShuffleMask(LoMask))
9010 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9011 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9013 // Do a half shuffle with the high mask after shifting its values down.
9014 for (int &M : HiMask)
9017 if (!isNoopShuffleMask(HiMask))
9018 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9019 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9024 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9025 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9026 SDValue V2, ArrayRef<int> Mask,
9027 SelectionDAG &DAG, bool &V1InUse,
9029 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9035 int Size = Mask.size();
9036 int Scale = 16 / Size;
9037 for (int i = 0; i < 16; ++i) {
9038 if (Mask[i / Scale] == -1) {
9039 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9041 const int ZeroMask = 0x80;
9042 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9044 int V2Idx = Mask[i / Scale] < Size
9046 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9047 if (Zeroable[i / Scale])
9048 V1Idx = V2Idx = ZeroMask;
9049 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9050 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9051 V1InUse |= (ZeroMask != V1Idx);
9052 V2InUse |= (ZeroMask != V2Idx);
9057 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9058 DAG.getBitcast(MVT::v16i8, V1),
9059 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9061 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9062 DAG.getBitcast(MVT::v16i8, V2),
9063 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9065 // If we need shuffled inputs from both, blend the two.
9067 if (V1InUse && V2InUse)
9068 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9070 V = V1InUse ? V1 : V2;
9072 // Cast the result back to the correct type.
9073 return DAG.getBitcast(VT, V);
9076 /// \brief Generic lowering of 8-lane i16 shuffles.
9078 /// This handles both single-input shuffles and combined shuffle/blends with
9079 /// two inputs. The single input shuffles are immediately delegated to
9080 /// a dedicated lowering routine.
9082 /// The blends are lowered in one of three fundamental ways. If there are few
9083 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9084 /// of the input is significantly cheaper when lowered as an interleaving of
9085 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9086 /// halves of the inputs separately (making them have relatively few inputs)
9087 /// and then concatenate them.
9088 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9089 const X86Subtarget *Subtarget,
9090 SelectionDAG &DAG) {
9092 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9093 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9094 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9095 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9096 ArrayRef<int> OrigMask = SVOp->getMask();
9097 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9098 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9099 MutableArrayRef<int> Mask(MaskStorage);
9101 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9103 // Whenever we can lower this as a zext, that instruction is strictly faster
9104 // than any alternative.
9105 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9106 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9109 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9111 auto isV2 = [](int M) { return M >= 8; };
9113 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9115 if (NumV2Inputs == 0) {
9116 // Check for being able to broadcast a single element.
9117 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9118 Mask, Subtarget, DAG))
9121 // Try to use shift instructions.
9123 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9126 // Use dedicated unpack instructions for masks that match their pattern.
9127 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
9128 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
9129 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
9130 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
9132 // Try to use byte rotation instructions.
9133 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9134 Mask, Subtarget, DAG))
9137 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9141 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9142 "All single-input shuffles should be canonicalized to be V1-input "
9145 // Try to use shift instructions.
9147 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9150 // See if we can use SSE4A Extraction / Insertion.
9151 if (Subtarget->hasSSE4A())
9152 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9155 // There are special ways we can lower some single-element blends.
9156 if (NumV2Inputs == 1)
9157 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9158 Mask, Subtarget, DAG))
9161 // We have different paths for blend lowering, but they all must use the
9162 // *exact* same predicate.
9163 bool IsBlendSupported = Subtarget->hasSSE41();
9164 if (IsBlendSupported)
9165 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9169 if (SDValue Masked =
9170 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9173 // Use dedicated unpack instructions for masks that match their pattern.
9174 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9175 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9176 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9177 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9179 // Try to use byte rotation instructions.
9180 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9181 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9184 if (SDValue BitBlend =
9185 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9188 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9192 // If we can't directly blend but can use PSHUFB, that will be better as it
9193 // can both shuffle and set up the inefficient blend.
9194 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9195 bool V1InUse, V2InUse;
9196 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9200 // We can always bit-blend if we have to so the fallback strategy is to
9201 // decompose into single-input permutes and blends.
9202 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9206 /// \brief Check whether a compaction lowering can be done by dropping even
9207 /// elements and compute how many times even elements must be dropped.
9209 /// This handles shuffles which take every Nth element where N is a power of
9210 /// two. Example shuffle masks:
9212 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9213 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9214 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9215 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9216 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9217 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9219 /// Any of these lanes can of course be undef.
9221 /// This routine only supports N <= 3.
9222 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9225 /// \returns N above, or the number of times even elements must be dropped if
9226 /// there is such a number. Otherwise returns zero.
9227 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9228 // Figure out whether we're looping over two inputs or just one.
9229 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9231 // The modulus for the shuffle vector entries is based on whether this is
9232 // a single input or not.
9233 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9234 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9235 "We should only be called with masks with a power-of-2 size!");
9237 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9239 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9240 // and 2^3 simultaneously. This is because we may have ambiguity with
9241 // partially undef inputs.
9242 bool ViableForN[3] = {true, true, true};
9244 for (int i = 0, e = Mask.size(); i < e; ++i) {
9245 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9250 bool IsAnyViable = false;
9251 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9252 if (ViableForN[j]) {
9255 // The shuffle mask must be equal to (i * 2^N) % M.
9256 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9259 ViableForN[j] = false;
9261 // Early exit if we exhaust the possible powers of two.
9266 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9270 // Return 0 as there is no viable power of two.
9274 /// \brief Generic lowering of v16i8 shuffles.
9276 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9277 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9278 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9279 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9281 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9282 const X86Subtarget *Subtarget,
9283 SelectionDAG &DAG) {
9285 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9286 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9287 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9288 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9289 ArrayRef<int> Mask = SVOp->getMask();
9290 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9292 // Try to use shift instructions.
9294 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9297 // Try to use byte rotation instructions.
9298 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9299 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9302 // Try to use a zext lowering.
9303 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9304 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9307 // See if we can use SSE4A Extraction / Insertion.
9308 if (Subtarget->hasSSE4A())
9309 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9313 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9315 // For single-input shuffles, there are some nicer lowering tricks we can use.
9316 if (NumV2Elements == 0) {
9317 // Check for being able to broadcast a single element.
9318 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9319 Mask, Subtarget, DAG))
9322 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9323 // Notably, this handles splat and partial-splat shuffles more efficiently.
9324 // However, it only makes sense if the pre-duplication shuffle simplifies
9325 // things significantly. Currently, this means we need to be able to
9326 // express the pre-duplication shuffle as an i16 shuffle.
9328 // FIXME: We should check for other patterns which can be widened into an
9329 // i16 shuffle as well.
9330 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9331 for (int i = 0; i < 16; i += 2)
9332 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9337 auto tryToWidenViaDuplication = [&]() -> SDValue {
9338 if (!canWidenViaDuplication(Mask))
9340 SmallVector<int, 4> LoInputs;
9341 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9342 [](int M) { return M >= 0 && M < 8; });
9343 std::sort(LoInputs.begin(), LoInputs.end());
9344 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9346 SmallVector<int, 4> HiInputs;
9347 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9348 [](int M) { return M >= 8; });
9349 std::sort(HiInputs.begin(), HiInputs.end());
9350 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9353 bool TargetLo = LoInputs.size() >= HiInputs.size();
9354 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9355 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9357 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9358 SmallDenseMap<int, int, 8> LaneMap;
9359 for (int I : InPlaceInputs) {
9360 PreDupI16Shuffle[I/2] = I/2;
9363 int j = TargetLo ? 0 : 4, je = j + 4;
9364 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9365 // Check if j is already a shuffle of this input. This happens when
9366 // there are two adjacent bytes after we move the low one.
9367 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9368 // If we haven't yet mapped the input, search for a slot into which
9370 while (j < je && PreDupI16Shuffle[j] != -1)
9374 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9377 // Map this input with the i16 shuffle.
9378 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9381 // Update the lane map based on the mapping we ended up with.
9382 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9384 V1 = DAG.getBitcast(
9386 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9387 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9389 // Unpack the bytes to form the i16s that will be shuffled into place.
9390 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9391 MVT::v16i8, V1, V1);
9393 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9394 for (int i = 0; i < 16; ++i)
9395 if (Mask[i] != -1) {
9396 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9397 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9398 if (PostDupI16Shuffle[i / 2] == -1)
9399 PostDupI16Shuffle[i / 2] = MappedMask;
9401 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9402 "Conflicting entrties in the original shuffle!");
9404 return DAG.getBitcast(
9406 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9407 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9409 if (SDValue V = tryToWidenViaDuplication())
9413 if (SDValue Masked =
9414 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9417 // Use dedicated unpack instructions for masks that match their pattern.
9418 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9419 0, 16, 1, 17, 2, 18, 3, 19,
9421 4, 20, 5, 21, 6, 22, 7, 23}))
9422 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9423 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9424 8, 24, 9, 25, 10, 26, 11, 27,
9426 12, 28, 13, 29, 14, 30, 15, 31}))
9427 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9429 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9430 // with PSHUFB. It is important to do this before we attempt to generate any
9431 // blends but after all of the single-input lowerings. If the single input
9432 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9433 // want to preserve that and we can DAG combine any longer sequences into
9434 // a PSHUFB in the end. But once we start blending from multiple inputs,
9435 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9436 // and there are *very* few patterns that would actually be faster than the
9437 // PSHUFB approach because of its ability to zero lanes.
9439 // FIXME: The only exceptions to the above are blends which are exact
9440 // interleavings with direct instructions supporting them. We currently don't
9441 // handle those well here.
9442 if (Subtarget->hasSSSE3()) {
9443 bool V1InUse = false;
9444 bool V2InUse = false;
9446 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9447 DAG, V1InUse, V2InUse);
9449 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9450 // do so. This avoids using them to handle blends-with-zero which is
9451 // important as a single pshufb is significantly faster for that.
9452 if (V1InUse && V2InUse) {
9453 if (Subtarget->hasSSE41())
9454 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9455 Mask, Subtarget, DAG))
9458 // We can use an unpack to do the blending rather than an or in some
9459 // cases. Even though the or may be (very minorly) more efficient, we
9460 // preference this lowering because there are common cases where part of
9461 // the complexity of the shuffles goes away when we do the final blend as
9463 // FIXME: It might be worth trying to detect if the unpack-feeding
9464 // shuffles will both be pshufb, in which case we shouldn't bother with
9466 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9467 DL, MVT::v16i8, V1, V2, Mask, DAG))
9474 // There are special ways we can lower some single-element blends.
9475 if (NumV2Elements == 1)
9476 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9477 Mask, Subtarget, DAG))
9480 if (SDValue BitBlend =
9481 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9484 // Check whether a compaction lowering can be done. This handles shuffles
9485 // which take every Nth element for some even N. See the helper function for
9488 // We special case these as they can be particularly efficiently handled with
9489 // the PACKUSB instruction on x86 and they show up in common patterns of
9490 // rearranging bytes to truncate wide elements.
9491 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9492 // NumEvenDrops is the power of two stride of the elements. Another way of
9493 // thinking about it is that we need to drop the even elements this many
9494 // times to get the original input.
9495 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9497 // First we need to zero all the dropped bytes.
9498 assert(NumEvenDrops <= 3 &&
9499 "No support for dropping even elements more than 3 times.");
9500 // We use the mask type to pick which bytes are preserved based on how many
9501 // elements are dropped.
9502 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9503 SDValue ByteClearMask = DAG.getBitcast(
9504 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9505 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9507 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9509 // Now pack things back together.
9510 V1 = DAG.getBitcast(MVT::v8i16, V1);
9511 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9512 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9513 for (int i = 1; i < NumEvenDrops; ++i) {
9514 Result = DAG.getBitcast(MVT::v8i16, Result);
9515 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9521 // Handle multi-input cases by blending single-input shuffles.
9522 if (NumV2Elements > 0)
9523 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9526 // The fallback path for single-input shuffles widens this into two v8i16
9527 // vectors with unpacks, shuffles those, and then pulls them back together
9531 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9532 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9533 for (int i = 0; i < 16; ++i)
9535 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9537 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9539 SDValue VLoHalf, VHiHalf;
9540 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9541 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9543 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9544 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9545 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9546 [](int M) { return M >= 0 && M % 2 == 1; })) {
9547 // Use a mask to drop the high bytes.
9548 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9549 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9550 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9552 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9553 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9555 // Squash the masks to point directly into VLoHalf.
9556 for (int &M : LoBlendMask)
9559 for (int &M : HiBlendMask)
9563 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9564 // VHiHalf so that we can blend them as i16s.
9565 VLoHalf = DAG.getBitcast(
9566 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9567 VHiHalf = DAG.getBitcast(
9568 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9571 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9572 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9574 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9577 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9579 /// This routine breaks down the specific type of 128-bit shuffle and
9580 /// dispatches to the lowering routines accordingly.
9581 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9582 MVT VT, const X86Subtarget *Subtarget,
9583 SelectionDAG &DAG) {
9584 switch (VT.SimpleTy) {
9586 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9588 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9590 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9592 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9594 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9596 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9599 llvm_unreachable("Unimplemented!");
9603 /// \brief Helper function to test whether a shuffle mask could be
9604 /// simplified by widening the elements being shuffled.
9606 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9607 /// leaves it in an unspecified state.
9609 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9610 /// shuffle masks. The latter have the special property of a '-2' representing
9611 /// a zero-ed lane of a vector.
9612 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9613 SmallVectorImpl<int> &WidenedMask) {
9614 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9615 // If both elements are undef, its trivial.
9616 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9617 WidenedMask.push_back(SM_SentinelUndef);
9621 // Check for an undef mask and a mask value properly aligned to fit with
9622 // a pair of values. If we find such a case, use the non-undef mask's value.
9623 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9624 WidenedMask.push_back(Mask[i + 1] / 2);
9627 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9628 WidenedMask.push_back(Mask[i] / 2);
9632 // When zeroing, we need to spread the zeroing across both lanes to widen.
9633 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9634 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9635 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9636 WidenedMask.push_back(SM_SentinelZero);
9642 // Finally check if the two mask values are adjacent and aligned with
9644 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9645 WidenedMask.push_back(Mask[i] / 2);
9649 // Otherwise we can't safely widen the elements used in this shuffle.
9652 assert(WidenedMask.size() == Mask.size() / 2 &&
9653 "Incorrect size of mask after widening the elements!");
9658 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9660 /// This routine just extracts two subvectors, shuffles them independently, and
9661 /// then concatenates them back together. This should work effectively with all
9662 /// AVX vector shuffle types.
9663 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9664 SDValue V2, ArrayRef<int> Mask,
9665 SelectionDAG &DAG) {
9666 assert(VT.getSizeInBits() >= 256 &&
9667 "Only for 256-bit or wider vector shuffles!");
9668 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9669 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9671 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9672 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9674 int NumElements = VT.getVectorNumElements();
9675 int SplitNumElements = NumElements / 2;
9676 MVT ScalarVT = VT.getScalarType();
9677 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9679 // Rather than splitting build-vectors, just build two narrower build
9680 // vectors. This helps shuffling with splats and zeros.
9681 auto SplitVector = [&](SDValue V) {
9682 while (V.getOpcode() == ISD::BITCAST)
9683 V = V->getOperand(0);
9685 MVT OrigVT = V.getSimpleValueType();
9686 int OrigNumElements = OrigVT.getVectorNumElements();
9687 int OrigSplitNumElements = OrigNumElements / 2;
9688 MVT OrigScalarVT = OrigVT.getScalarType();
9689 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9693 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9695 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9696 DAG.getIntPtrConstant(0, DL));
9697 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9698 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9701 SmallVector<SDValue, 16> LoOps, HiOps;
9702 for (int i = 0; i < OrigSplitNumElements; ++i) {
9703 LoOps.push_back(BV->getOperand(i));
9704 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9706 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9707 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9709 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9710 DAG.getBitcast(SplitVT, HiV));
9713 SDValue LoV1, HiV1, LoV2, HiV2;
9714 std::tie(LoV1, HiV1) = SplitVector(V1);
9715 std::tie(LoV2, HiV2) = SplitVector(V2);
9717 // Now create two 4-way blends of these half-width vectors.
9718 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9719 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9720 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9721 for (int i = 0; i < SplitNumElements; ++i) {
9722 int M = HalfMask[i];
9723 if (M >= NumElements) {
9724 if (M >= NumElements + SplitNumElements)
9728 V2BlendMask.push_back(M - NumElements);
9729 V1BlendMask.push_back(-1);
9730 BlendMask.push_back(SplitNumElements + i);
9731 } else if (M >= 0) {
9732 if (M >= SplitNumElements)
9736 V2BlendMask.push_back(-1);
9737 V1BlendMask.push_back(M);
9738 BlendMask.push_back(i);
9740 V2BlendMask.push_back(-1);
9741 V1BlendMask.push_back(-1);
9742 BlendMask.push_back(-1);
9746 // Because the lowering happens after all combining takes place, we need to
9747 // manually combine these blend masks as much as possible so that we create
9748 // a minimal number of high-level vector shuffle nodes.
9750 // First try just blending the halves of V1 or V2.
9751 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9752 return DAG.getUNDEF(SplitVT);
9753 if (!UseLoV2 && !UseHiV2)
9754 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9755 if (!UseLoV1 && !UseHiV1)
9756 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9758 SDValue V1Blend, V2Blend;
9759 if (UseLoV1 && UseHiV1) {
9761 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9763 // We only use half of V1 so map the usage down into the final blend mask.
9764 V1Blend = UseLoV1 ? LoV1 : HiV1;
9765 for (int i = 0; i < SplitNumElements; ++i)
9766 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9767 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9769 if (UseLoV2 && UseHiV2) {
9771 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9773 // We only use half of V2 so map the usage down into the final blend mask.
9774 V2Blend = UseLoV2 ? LoV2 : HiV2;
9775 for (int i = 0; i < SplitNumElements; ++i)
9776 if (BlendMask[i] >= SplitNumElements)
9777 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9779 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9781 SDValue Lo = HalfBlend(LoMask);
9782 SDValue Hi = HalfBlend(HiMask);
9783 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9786 /// \brief Either split a vector in halves or decompose the shuffles and the
9789 /// This is provided as a good fallback for many lowerings of non-single-input
9790 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9791 /// between splitting the shuffle into 128-bit components and stitching those
9792 /// back together vs. extracting the single-input shuffles and blending those
9794 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9795 SDValue V2, ArrayRef<int> Mask,
9796 SelectionDAG &DAG) {
9797 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9798 "lower single-input shuffles as it "
9799 "could then recurse on itself.");
9800 int Size = Mask.size();
9802 // If this can be modeled as a broadcast of two elements followed by a blend,
9803 // prefer that lowering. This is especially important because broadcasts can
9804 // often fold with memory operands.
9805 auto DoBothBroadcast = [&] {
9806 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9809 if (V2BroadcastIdx == -1)
9810 V2BroadcastIdx = M - Size;
9811 else if (M - Size != V2BroadcastIdx)
9813 } else if (M >= 0) {
9814 if (V1BroadcastIdx == -1)
9816 else if (M != V1BroadcastIdx)
9821 if (DoBothBroadcast())
9822 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9825 // If the inputs all stem from a single 128-bit lane of each input, then we
9826 // split them rather than blending because the split will decompose to
9827 // unusually few instructions.
9828 int LaneCount = VT.getSizeInBits() / 128;
9829 int LaneSize = Size / LaneCount;
9830 SmallBitVector LaneInputs[2];
9831 LaneInputs[0].resize(LaneCount, false);
9832 LaneInputs[1].resize(LaneCount, false);
9833 for (int i = 0; i < Size; ++i)
9835 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9836 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9837 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9839 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9840 // that the decomposed single-input shuffles don't end up here.
9841 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9844 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9845 /// a permutation and blend of those lanes.
9847 /// This essentially blends the out-of-lane inputs to each lane into the lane
9848 /// from a permuted copy of the vector. This lowering strategy results in four
9849 /// instructions in the worst case for a single-input cross lane shuffle which
9850 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9851 /// of. Special cases for each particular shuffle pattern should be handled
9852 /// prior to trying this lowering.
9853 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9854 SDValue V1, SDValue V2,
9856 SelectionDAG &DAG) {
9857 // FIXME: This should probably be generalized for 512-bit vectors as well.
9858 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9859 int LaneSize = Mask.size() / 2;
9861 // If there are only inputs from one 128-bit lane, splitting will in fact be
9862 // less expensive. The flags track whether the given lane contains an element
9863 // that crosses to another lane.
9864 bool LaneCrossing[2] = {false, false};
9865 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9866 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9867 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9868 if (!LaneCrossing[0] || !LaneCrossing[1])
9869 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9871 if (isSingleInputShuffleMask(Mask)) {
9872 SmallVector<int, 32> FlippedBlendMask;
9873 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9874 FlippedBlendMask.push_back(
9875 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9877 : Mask[i] % LaneSize +
9878 (i / LaneSize) * LaneSize + Size));
9880 // Flip the vector, and blend the results which should now be in-lane. The
9881 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9882 // 5 for the high source. The value 3 selects the high half of source 2 and
9883 // the value 2 selects the low half of source 2. We only use source 2 to
9884 // allow folding it into a memory operand.
9885 unsigned PERMMask = 3 | 2 << 4;
9886 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9887 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9888 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9891 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9892 // will be handled by the above logic and a blend of the results, much like
9893 // other patterns in AVX.
9894 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9897 /// \brief Handle lowering 2-lane 128-bit shuffles.
9898 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9899 SDValue V2, ArrayRef<int> Mask,
9900 const X86Subtarget *Subtarget,
9901 SelectionDAG &DAG) {
9902 // TODO: If minimizing size and one of the inputs is a zero vector and the
9903 // the zero vector has only one use, we could use a VPERM2X128 to save the
9904 // instruction bytes needed to explicitly generate the zero vector.
9906 // Blends are faster and handle all the non-lane-crossing cases.
9907 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9911 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9912 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9914 // If either input operand is a zero vector, use VPERM2X128 because its mask
9915 // allows us to replace the zero input with an implicit zero.
9916 if (!IsV1Zero && !IsV2Zero) {
9917 // Check for patterns which can be matched with a single insert of a 128-bit
9919 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9920 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9921 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9922 VT.getVectorNumElements() / 2);
9923 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9924 DAG.getIntPtrConstant(0, DL));
9925 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9926 OnlyUsesV1 ? V1 : V2,
9927 DAG.getIntPtrConstant(0, DL));
9928 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9932 // Otherwise form a 128-bit permutation. After accounting for undefs,
9933 // convert the 64-bit shuffle mask selection values into 128-bit
9934 // selection bits by dividing the indexes by 2 and shifting into positions
9935 // defined by a vperm2*128 instruction's immediate control byte.
9937 // The immediate permute control byte looks like this:
9938 // [1:0] - select 128 bits from sources for low half of destination
9940 // [3] - zero low half of destination
9941 // [5:4] - select 128 bits from sources for high half of destination
9943 // [7] - zero high half of destination
9945 int MaskLO = Mask[0];
9946 if (MaskLO == SM_SentinelUndef)
9947 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9949 int MaskHI = Mask[2];
9950 if (MaskHI == SM_SentinelUndef)
9951 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9953 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9955 // If either input is a zero vector, replace it with an undef input.
9956 // Shuffle mask values < 4 are selecting elements of V1.
9957 // Shuffle mask values >= 4 are selecting elements of V2.
9958 // Adjust each half of the permute mask by clearing the half that was
9959 // selecting the zero vector and setting the zero mask bit.
9961 V1 = DAG.getUNDEF(VT);
9963 PermMask = (PermMask & 0xf0) | 0x08;
9965 PermMask = (PermMask & 0x0f) | 0x80;
9968 V2 = DAG.getUNDEF(VT);
9970 PermMask = (PermMask & 0xf0) | 0x08;
9972 PermMask = (PermMask & 0x0f) | 0x80;
9975 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9976 DAG.getConstant(PermMask, DL, MVT::i8));
9979 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9980 /// shuffling each lane.
9982 /// This will only succeed when the result of fixing the 128-bit lanes results
9983 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9984 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9985 /// the lane crosses early and then use simpler shuffles within each lane.
9987 /// FIXME: It might be worthwhile at some point to support this without
9988 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9989 /// in x86 only floating point has interesting non-repeating shuffles, and even
9990 /// those are still *marginally* more expensive.
9991 static SDValue lowerVectorShuffleByMerging128BitLanes(
9992 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9993 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9994 assert(!isSingleInputShuffleMask(Mask) &&
9995 "This is only useful with multiple inputs.");
9997 int Size = Mask.size();
9998 int LaneSize = 128 / VT.getScalarSizeInBits();
9999 int NumLanes = Size / LaneSize;
10000 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10002 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10003 // check whether the in-128-bit lane shuffles share a repeating pattern.
10004 SmallVector<int, 4> Lanes;
10005 Lanes.resize(NumLanes, -1);
10006 SmallVector<int, 4> InLaneMask;
10007 InLaneMask.resize(LaneSize, -1);
10008 for (int i = 0; i < Size; ++i) {
10012 int j = i / LaneSize;
10014 if (Lanes[j] < 0) {
10015 // First entry we've seen for this lane.
10016 Lanes[j] = Mask[i] / LaneSize;
10017 } else if (Lanes[j] != Mask[i] / LaneSize) {
10018 // This doesn't match the lane selected previously!
10022 // Check that within each lane we have a consistent shuffle mask.
10023 int k = i % LaneSize;
10024 if (InLaneMask[k] < 0) {
10025 InLaneMask[k] = Mask[i] % LaneSize;
10026 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10027 // This doesn't fit a repeating in-lane mask.
10032 // First shuffle the lanes into place.
10033 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10034 VT.getSizeInBits() / 64);
10035 SmallVector<int, 8> LaneMask;
10036 LaneMask.resize(NumLanes * 2, -1);
10037 for (int i = 0; i < NumLanes; ++i)
10038 if (Lanes[i] >= 0) {
10039 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10040 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10043 V1 = DAG.getBitcast(LaneVT, V1);
10044 V2 = DAG.getBitcast(LaneVT, V2);
10045 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10047 // Cast it back to the type we actually want.
10048 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10050 // Now do a simple shuffle that isn't lane crossing.
10051 SmallVector<int, 8> NewMask;
10052 NewMask.resize(Size, -1);
10053 for (int i = 0; i < Size; ++i)
10055 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10056 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10057 "Must not introduce lane crosses at this point!");
10059 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10062 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10065 /// This returns true if the elements from a particular input are already in the
10066 /// slot required by the given mask and require no permutation.
10067 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10068 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10069 int Size = Mask.size();
10070 for (int i = 0; i < Size; ++i)
10071 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10077 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10078 ArrayRef<int> Mask, SDValue V1,
10079 SDValue V2, SelectionDAG &DAG) {
10081 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10082 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10083 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10084 int NumElts = VT.getVectorNumElements();
10085 bool ShufpdMask = true;
10086 bool CommutableMask = true;
10087 unsigned Immediate = 0;
10088 for (int i = 0; i < NumElts; ++i) {
10091 int Val = (i & 6) + NumElts * (i & 1);
10092 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10093 if (Mask[i] < Val || Mask[i] > Val + 1)
10094 ShufpdMask = false;
10095 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10096 CommutableMask = false;
10097 Immediate |= (Mask[i] % 2) << i;
10100 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10101 DAG.getConstant(Immediate, DL, MVT::i8));
10102 if (CommutableMask)
10103 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10104 DAG.getConstant(Immediate, DL, MVT::i8));
10108 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10110 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10111 /// isn't available.
10112 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10113 const X86Subtarget *Subtarget,
10114 SelectionDAG &DAG) {
10116 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10117 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10118 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10119 ArrayRef<int> Mask = SVOp->getMask();
10120 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10122 SmallVector<int, 4> WidenedMask;
10123 if (canWidenShuffleElements(Mask, WidenedMask))
10124 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10127 if (isSingleInputShuffleMask(Mask)) {
10128 // Check for being able to broadcast a single element.
10129 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10130 Mask, Subtarget, DAG))
10133 // Use low duplicate instructions for masks that match their pattern.
10134 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10135 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10137 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10138 // Non-half-crossing single input shuffles can be lowerid with an
10139 // interleaved permutation.
10140 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10141 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10142 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10143 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10146 // With AVX2 we have direct support for this permutation.
10147 if (Subtarget->hasAVX2())
10148 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10149 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10151 // Otherwise, fall back.
10152 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10156 // X86 has dedicated unpack instructions that can handle specific blend
10157 // operations: UNPCKH and UNPCKL.
10158 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10159 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10160 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10161 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10162 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10163 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10164 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10165 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10167 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10171 // Check if the blend happens to exactly fit that of SHUFPD.
10173 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10176 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10177 // shuffle. However, if we have AVX2 and either inputs are already in place,
10178 // we will be able to shuffle even across lanes the other input in a single
10179 // instruction so skip this pattern.
10180 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10181 isShuffleMaskInputInPlace(1, Mask))))
10182 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10183 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10186 // If we have AVX2 then we always want to lower with a blend because an v4 we
10187 // can fully permute the elements.
10188 if (Subtarget->hasAVX2())
10189 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10192 // Otherwise fall back on generic lowering.
10193 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10196 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10198 /// This routine is only called when we have AVX2 and thus a reasonable
10199 /// instruction set for v4i64 shuffling..
10200 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10201 const X86Subtarget *Subtarget,
10202 SelectionDAG &DAG) {
10204 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10205 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10206 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10207 ArrayRef<int> Mask = SVOp->getMask();
10208 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10209 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10211 SmallVector<int, 4> WidenedMask;
10212 if (canWidenShuffleElements(Mask, WidenedMask))
10213 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10216 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10220 // Check for being able to broadcast a single element.
10221 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10222 Mask, Subtarget, DAG))
10225 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10226 // use lower latency instructions that will operate on both 128-bit lanes.
10227 SmallVector<int, 2> RepeatedMask;
10228 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10229 if (isSingleInputShuffleMask(Mask)) {
10230 int PSHUFDMask[] = {-1, -1, -1, -1};
10231 for (int i = 0; i < 2; ++i)
10232 if (RepeatedMask[i] >= 0) {
10233 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10234 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10236 return DAG.getBitcast(
10238 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10239 DAG.getBitcast(MVT::v8i32, V1),
10240 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10244 // AVX2 provides a direct instruction for permuting a single input across
10246 if (isSingleInputShuffleMask(Mask))
10247 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10248 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10250 // Try to use shift instructions.
10251 if (SDValue Shift =
10252 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10255 // Use dedicated unpack instructions for masks that match their pattern.
10256 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10257 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10258 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10259 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10260 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10261 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10262 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10263 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10265 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10266 // shuffle. However, if we have AVX2 and either inputs are already in place,
10267 // we will be able to shuffle even across lanes the other input in a single
10268 // instruction so skip this pattern.
10269 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10270 isShuffleMaskInputInPlace(1, Mask))))
10271 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10272 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10275 // Otherwise fall back on generic blend lowering.
10276 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10280 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10282 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10283 /// isn't available.
10284 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10285 const X86Subtarget *Subtarget,
10286 SelectionDAG &DAG) {
10288 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10289 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10290 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10291 ArrayRef<int> Mask = SVOp->getMask();
10292 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10294 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10298 // Check for being able to broadcast a single element.
10299 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10300 Mask, Subtarget, DAG))
10303 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10304 // options to efficiently lower the shuffle.
10305 SmallVector<int, 4> RepeatedMask;
10306 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10307 assert(RepeatedMask.size() == 4 &&
10308 "Repeated masks must be half the mask width!");
10310 // Use even/odd duplicate instructions for masks that match their pattern.
10311 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10312 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10313 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10314 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10316 if (isSingleInputShuffleMask(Mask))
10317 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10318 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10320 // Use dedicated unpack instructions for masks that match their pattern.
10321 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10322 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10323 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10324 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10325 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10326 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10327 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10328 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10330 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10331 // have already handled any direct blends. We also need to squash the
10332 // repeated mask into a simulated v4f32 mask.
10333 for (int i = 0; i < 4; ++i)
10334 if (RepeatedMask[i] >= 8)
10335 RepeatedMask[i] -= 4;
10336 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10339 // If we have a single input shuffle with different shuffle patterns in the
10340 // two 128-bit lanes use the variable mask to VPERMILPS.
10341 if (isSingleInputShuffleMask(Mask)) {
10342 SDValue VPermMask[8];
10343 for (int i = 0; i < 8; ++i)
10344 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10345 : DAG.getConstant(Mask[i], DL, MVT::i32);
10346 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10347 return DAG.getNode(
10348 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10349 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10351 if (Subtarget->hasAVX2())
10352 return DAG.getNode(
10353 X86ISD::VPERMV, DL, MVT::v8f32,
10354 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10355 MVT::v8i32, VPermMask)),
10358 // Otherwise, fall back.
10359 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10363 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10365 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10366 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10369 // If we have AVX2 then we always want to lower with a blend because at v8 we
10370 // can fully permute the elements.
10371 if (Subtarget->hasAVX2())
10372 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10375 // Otherwise fall back on generic lowering.
10376 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10379 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10381 /// This routine is only called when we have AVX2 and thus a reasonable
10382 /// instruction set for v8i32 shuffling..
10383 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10384 const X86Subtarget *Subtarget,
10385 SelectionDAG &DAG) {
10387 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10388 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10389 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10390 ArrayRef<int> Mask = SVOp->getMask();
10391 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10392 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10394 // Whenever we can lower this as a zext, that instruction is strictly faster
10395 // than any alternative. It also allows us to fold memory operands into the
10396 // shuffle in many cases.
10397 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10398 Mask, Subtarget, DAG))
10401 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10405 // Check for being able to broadcast a single element.
10406 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10407 Mask, Subtarget, DAG))
10410 // If the shuffle mask is repeated in each 128-bit lane we can use more
10411 // efficient instructions that mirror the shuffles across the two 128-bit
10413 SmallVector<int, 4> RepeatedMask;
10414 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10415 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10416 if (isSingleInputShuffleMask(Mask))
10417 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10418 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10420 // Use dedicated unpack instructions for masks that match their pattern.
10421 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10422 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10423 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10424 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10425 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10426 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10427 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10428 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10431 // Try to use shift instructions.
10432 if (SDValue Shift =
10433 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10436 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10437 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10440 // If the shuffle patterns aren't repeated but it is a single input, directly
10441 // generate a cross-lane VPERMD instruction.
10442 if (isSingleInputShuffleMask(Mask)) {
10443 SDValue VPermMask[8];
10444 for (int i = 0; i < 8; ++i)
10445 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10446 : DAG.getConstant(Mask[i], DL, MVT::i32);
10447 return DAG.getNode(
10448 X86ISD::VPERMV, DL, MVT::v8i32,
10449 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10452 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10454 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10455 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10458 // Otherwise fall back on generic blend lowering.
10459 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10463 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10465 /// This routine is only called when we have AVX2 and thus a reasonable
10466 /// instruction set for v16i16 shuffling..
10467 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10468 const X86Subtarget *Subtarget,
10469 SelectionDAG &DAG) {
10471 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10472 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10473 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10474 ArrayRef<int> Mask = SVOp->getMask();
10475 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10476 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10478 // Whenever we can lower this as a zext, that instruction is strictly faster
10479 // than any alternative. It also allows us to fold memory operands into the
10480 // shuffle in many cases.
10481 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10482 Mask, Subtarget, DAG))
10485 // Check for being able to broadcast a single element.
10486 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10487 Mask, Subtarget, DAG))
10490 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10494 // Use dedicated unpack instructions for masks that match their pattern.
10495 if (isShuffleEquivalent(V1, V2, Mask,
10496 {// First 128-bit lane:
10497 0, 16, 1, 17, 2, 18, 3, 19,
10498 // Second 128-bit lane:
10499 8, 24, 9, 25, 10, 26, 11, 27}))
10500 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10501 if (isShuffleEquivalent(V1, V2, Mask,
10502 {// First 128-bit lane:
10503 4, 20, 5, 21, 6, 22, 7, 23,
10504 // Second 128-bit lane:
10505 12, 28, 13, 29, 14, 30, 15, 31}))
10506 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10508 // Try to use shift instructions.
10509 if (SDValue Shift =
10510 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10513 // Try to use byte rotation instructions.
10514 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10515 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10518 if (isSingleInputShuffleMask(Mask)) {
10519 // There are no generalized cross-lane shuffle operations available on i16
10521 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10522 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10525 SmallVector<int, 8> RepeatedMask;
10526 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10527 // As this is a single-input shuffle, the repeated mask should be
10528 // a strictly valid v8i16 mask that we can pass through to the v8i16
10529 // lowering to handle even the v16 case.
10530 return lowerV8I16GeneralSingleInputVectorShuffle(
10531 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10534 SDValue PSHUFBMask[32];
10535 for (int i = 0; i < 16; ++i) {
10536 if (Mask[i] == -1) {
10537 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10541 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10542 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10543 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10544 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10546 return DAG.getBitcast(MVT::v16i16,
10547 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10548 DAG.getBitcast(MVT::v32i8, V1),
10549 DAG.getNode(ISD::BUILD_VECTOR, DL,
10550 MVT::v32i8, PSHUFBMask)));
10553 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10555 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10556 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10559 // Otherwise fall back on generic lowering.
10560 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10563 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10565 /// This routine is only called when we have AVX2 and thus a reasonable
10566 /// instruction set for v32i8 shuffling..
10567 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10568 const X86Subtarget *Subtarget,
10569 SelectionDAG &DAG) {
10571 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10572 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10573 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10574 ArrayRef<int> Mask = SVOp->getMask();
10575 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10576 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10578 // Whenever we can lower this as a zext, that instruction is strictly faster
10579 // than any alternative. It also allows us to fold memory operands into the
10580 // shuffle in many cases.
10581 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10582 Mask, Subtarget, DAG))
10585 // Check for being able to broadcast a single element.
10586 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10587 Mask, Subtarget, DAG))
10590 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10594 // Use dedicated unpack instructions for masks that match their pattern.
10595 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10597 if (isShuffleEquivalent(
10599 {// First 128-bit lane:
10600 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10601 // Second 128-bit lane:
10602 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10603 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10604 if (isShuffleEquivalent(
10606 {// First 128-bit lane:
10607 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10608 // Second 128-bit lane:
10609 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10610 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10612 // Try to use shift instructions.
10613 if (SDValue Shift =
10614 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10617 // Try to use byte rotation instructions.
10618 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10619 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10622 if (isSingleInputShuffleMask(Mask)) {
10623 // There are no generalized cross-lane shuffle operations available on i8
10625 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10626 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10629 SDValue PSHUFBMask[32];
10630 for (int i = 0; i < 32; ++i)
10633 ? DAG.getUNDEF(MVT::i8)
10634 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10637 return DAG.getNode(
10638 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10639 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10642 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10644 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10645 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10648 // Otherwise fall back on generic lowering.
10649 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10652 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10654 /// This routine either breaks down the specific type of a 256-bit x86 vector
10655 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10656 /// together based on the available instructions.
10657 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10658 MVT VT, const X86Subtarget *Subtarget,
10659 SelectionDAG &DAG) {
10661 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10662 ArrayRef<int> Mask = SVOp->getMask();
10664 // If we have a single input to the zero element, insert that into V1 if we
10665 // can do so cheaply.
10666 int NumElts = VT.getVectorNumElements();
10667 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10668 return M >= NumElts;
10671 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10672 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10673 DL, VT, V1, V2, Mask, Subtarget, DAG))
10676 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10677 // can check for those subtargets here and avoid much of the subtarget
10678 // querying in the per-vector-type lowering routines. With AVX1 we have
10679 // essentially *zero* ability to manipulate a 256-bit vector with integer
10680 // types. Since we'll use floating point types there eventually, just
10681 // immediately cast everything to a float and operate entirely in that domain.
10682 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10683 int ElementBits = VT.getScalarSizeInBits();
10684 if (ElementBits < 32)
10685 // No floating point type available, decompose into 128-bit vectors.
10686 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10688 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10689 VT.getVectorNumElements());
10690 V1 = DAG.getBitcast(FpVT, V1);
10691 V2 = DAG.getBitcast(FpVT, V2);
10692 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10695 switch (VT.SimpleTy) {
10697 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10699 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10701 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10703 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10705 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10707 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10710 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10714 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10715 ArrayRef<int> Mask, SDValue V1,
10716 SDValue V2, SelectionDAG &DAG) {
10718 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10720 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10721 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10723 SmallVector<SDValue, 32> VPermMask;
10724 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
10725 VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
10726 DAG.getConstant(Mask[i], DL, MaskEltVT));
10727 SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
10729 if (isSingleInputShuffleMask(Mask))
10730 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10732 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10735 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10736 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10737 const X86Subtarget *Subtarget,
10738 SelectionDAG &DAG) {
10740 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10741 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10742 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10743 ArrayRef<int> Mask = SVOp->getMask();
10744 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10746 if (SDValue Unpck =
10747 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10750 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10753 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10754 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10755 const X86Subtarget *Subtarget,
10756 SelectionDAG &DAG) {
10758 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10759 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10760 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10761 ArrayRef<int> Mask = SVOp->getMask();
10762 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10764 if (SDValue Unpck =
10765 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10768 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10771 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10772 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10773 const X86Subtarget *Subtarget,
10774 SelectionDAG &DAG) {
10776 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10777 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10778 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10779 ArrayRef<int> Mask = SVOp->getMask();
10780 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10782 if (SDValue Unpck =
10783 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10786 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10789 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10790 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10791 const X86Subtarget *Subtarget,
10792 SelectionDAG &DAG) {
10794 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10795 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10796 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10797 ArrayRef<int> Mask = SVOp->getMask();
10798 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10800 if (SDValue Unpck =
10801 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10804 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10807 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10808 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10809 const X86Subtarget *Subtarget,
10810 SelectionDAG &DAG) {
10812 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10813 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10814 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10815 ArrayRef<int> Mask = SVOp->getMask();
10816 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10817 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10819 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10822 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10823 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10824 const X86Subtarget *Subtarget,
10825 SelectionDAG &DAG) {
10827 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10828 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10829 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10830 ArrayRef<int> Mask = SVOp->getMask();
10831 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10832 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10834 // FIXME: Implement direct support for this type!
10835 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10838 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10840 /// This routine either breaks down the specific type of a 512-bit x86 vector
10841 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10842 /// together based on the available instructions.
10843 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10844 MVT VT, const X86Subtarget *Subtarget,
10845 SelectionDAG &DAG) {
10847 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10848 ArrayRef<int> Mask = SVOp->getMask();
10849 assert(Subtarget->hasAVX512() &&
10850 "Cannot lower 512-bit vectors w/ basic ISA!");
10852 // Check for being able to broadcast a single element.
10853 if (SDValue Broadcast =
10854 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10857 // Dispatch to each element type for lowering. If we don't have supprot for
10858 // specific element type shuffles at 512 bits, immediately split them and
10859 // lower them. Each lowering routine of a given type is allowed to assume that
10860 // the requisite ISA extensions for that element type are available.
10861 switch (VT.SimpleTy) {
10863 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10865 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10867 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10869 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10871 if (Subtarget->hasBWI())
10872 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10875 if (Subtarget->hasBWI())
10876 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10880 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10883 // Otherwise fall back on splitting.
10884 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10887 // Lower vXi1 vector shuffles.
10888 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10889 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10890 // vector, shuffle and then truncate it back.
10891 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10892 MVT VT, const X86Subtarget *Subtarget,
10893 SelectionDAG &DAG) {
10895 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10896 ArrayRef<int> Mask = SVOp->getMask();
10897 assert(Subtarget->hasAVX512() &&
10898 "Cannot lower 512-bit vectors w/o basic ISA!");
10900 switch (VT.SimpleTy) {
10902 assert(false && "Expected a vector of i1 elements");
10905 ExtVT = MVT::v2i64;
10908 ExtVT = MVT::v4i32;
10911 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
10914 ExtVT = MVT::v16i32;
10917 ExtVT = MVT::v32i16;
10920 ExtVT = MVT::v64i8;
10924 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10925 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10926 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
10927 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10929 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
10932 V2 = DAG.getUNDEF(ExtVT);
10933 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
10934 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10935 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
10936 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10938 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
10939 return DAG.getNode(ISD::TRUNCATE, DL, VT,
10940 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
10942 /// \brief Top-level lowering for x86 vector shuffles.
10944 /// This handles decomposition, canonicalization, and lowering of all x86
10945 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10946 /// above in helper routines. The canonicalization attempts to widen shuffles
10947 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10948 /// s.t. only one of the two inputs needs to be tested, etc.
10949 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10950 SelectionDAG &DAG) {
10951 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10952 ArrayRef<int> Mask = SVOp->getMask();
10953 SDValue V1 = Op.getOperand(0);
10954 SDValue V2 = Op.getOperand(1);
10955 MVT VT = Op.getSimpleValueType();
10956 int NumElements = VT.getVectorNumElements();
10958 bool Is1BitVector = (VT.getScalarType() == MVT::i1);
10960 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
10961 "Can't lower MMX shuffles");
10963 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10964 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10965 if (V1IsUndef && V2IsUndef)
10966 return DAG.getUNDEF(VT);
10968 // When we create a shuffle node we put the UNDEF node to second operand,
10969 // but in some cases the first operand may be transformed to UNDEF.
10970 // In this case we should just commute the node.
10972 return DAG.getCommutedVectorShuffle(*SVOp);
10974 // Check for non-undef masks pointing at an undef vector and make the masks
10975 // undef as well. This makes it easier to match the shuffle based solely on
10979 if (M >= NumElements) {
10980 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10981 for (int &M : NewMask)
10982 if (M >= NumElements)
10984 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10987 // We actually see shuffles that are entirely re-arrangements of a set of
10988 // zero inputs. This mostly happens while decomposing complex shuffles into
10989 // simple ones. Directly lower these as a buildvector of zeros.
10990 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10991 if (Zeroable.all())
10992 return getZeroVector(VT, Subtarget, DAG, dl);
10994 // Try to collapse shuffles into using a vector type with fewer elements but
10995 // wider element types. We cap this to not form integers or floating point
10996 // elements wider than 64 bits, but it might be interesting to form i128
10997 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10998 SmallVector<int, 16> WidenedMask;
10999 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11000 canWidenShuffleElements(Mask, WidenedMask)) {
11001 MVT NewEltVT = VT.isFloatingPoint()
11002 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11003 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11004 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11005 // Make sure that the new vector type is legal. For example, v2f64 isn't
11007 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11008 V1 = DAG.getBitcast(NewVT, V1);
11009 V2 = DAG.getBitcast(NewVT, V2);
11010 return DAG.getBitcast(
11011 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11015 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11016 for (int M : SVOp->getMask())
11018 ++NumUndefElements;
11019 else if (M < NumElements)
11024 // Commute the shuffle as needed such that more elements come from V1 than
11025 // V2. This allows us to match the shuffle pattern strictly on how many
11026 // elements come from V1 without handling the symmetric cases.
11027 if (NumV2Elements > NumV1Elements)
11028 return DAG.getCommutedVectorShuffle(*SVOp);
11030 // When the number of V1 and V2 elements are the same, try to minimize the
11031 // number of uses of V2 in the low half of the vector. When that is tied,
11032 // ensure that the sum of indices for V1 is equal to or lower than the sum
11033 // indices for V2. When those are equal, try to ensure that the number of odd
11034 // indices for V1 is lower than the number of odd indices for V2.
11035 if (NumV1Elements == NumV2Elements) {
11036 int LowV1Elements = 0, LowV2Elements = 0;
11037 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11038 if (M >= NumElements)
11042 if (LowV2Elements > LowV1Elements) {
11043 return DAG.getCommutedVectorShuffle(*SVOp);
11044 } else if (LowV2Elements == LowV1Elements) {
11045 int SumV1Indices = 0, SumV2Indices = 0;
11046 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11047 if (SVOp->getMask()[i] >= NumElements)
11049 else if (SVOp->getMask()[i] >= 0)
11051 if (SumV2Indices < SumV1Indices) {
11052 return DAG.getCommutedVectorShuffle(*SVOp);
11053 } else if (SumV2Indices == SumV1Indices) {
11054 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11055 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11056 if (SVOp->getMask()[i] >= NumElements)
11057 NumV2OddIndices += i % 2;
11058 else if (SVOp->getMask()[i] >= 0)
11059 NumV1OddIndices += i % 2;
11060 if (NumV2OddIndices < NumV1OddIndices)
11061 return DAG.getCommutedVectorShuffle(*SVOp);
11066 // For each vector width, delegate to a specialized lowering routine.
11067 if (VT.getSizeInBits() == 128)
11068 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11070 if (VT.getSizeInBits() == 256)
11071 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11073 if (VT.getSizeInBits() == 512)
11074 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11077 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11078 llvm_unreachable("Unimplemented!");
11081 // This function assumes its argument is a BUILD_VECTOR of constants or
11082 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11084 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11085 unsigned &MaskValue) {
11087 unsigned NumElems = BuildVector->getNumOperands();
11088 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11089 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11090 unsigned NumElemsInLane = NumElems / NumLanes;
11092 // Blend for v16i16 should be symmetric for the both lanes.
11093 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11094 SDValue EltCond = BuildVector->getOperand(i);
11095 SDValue SndLaneEltCond =
11096 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11098 int Lane1Cond = -1, Lane2Cond = -1;
11099 if (isa<ConstantSDNode>(EltCond))
11100 Lane1Cond = !isZero(EltCond);
11101 if (isa<ConstantSDNode>(SndLaneEltCond))
11102 Lane2Cond = !isZero(SndLaneEltCond);
11104 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11105 // Lane1Cond != 0, means we want the first argument.
11106 // Lane1Cond == 0, means we want the second argument.
11107 // The encoding of this argument is 0 for the first argument, 1
11108 // for the second. Therefore, invert the condition.
11109 MaskValue |= !Lane1Cond << i;
11110 else if (Lane1Cond < 0)
11111 MaskValue |= !Lane2Cond << i;
11118 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11119 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11120 const X86Subtarget *Subtarget,
11121 SelectionDAG &DAG) {
11122 SDValue Cond = Op.getOperand(0);
11123 SDValue LHS = Op.getOperand(1);
11124 SDValue RHS = Op.getOperand(2);
11126 MVT VT = Op.getSimpleValueType();
11128 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11130 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11132 // Only non-legal VSELECTs reach this lowering, convert those into generic
11133 // shuffles and re-use the shuffle lowering path for blends.
11134 SmallVector<int, 32> Mask;
11135 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11136 SDValue CondElt = CondBV->getOperand(i);
11138 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11140 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11143 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11144 // A vselect where all conditions and data are constants can be optimized into
11145 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11146 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11147 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11148 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11151 // Try to lower this to a blend-style vector shuffle. This can handle all
11152 // constant condition cases.
11153 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11156 // Variable blends are only legal from SSE4.1 onward.
11157 if (!Subtarget->hasSSE41())
11160 // Only some types will be legal on some subtargets. If we can emit a legal
11161 // VSELECT-matching blend, return Op, and but if we need to expand, return
11163 switch (Op.getSimpleValueType().SimpleTy) {
11165 // Most of the vector types have blends past SSE4.1.
11169 // The byte blends for AVX vectors were introduced only in AVX2.
11170 if (Subtarget->hasAVX2())
11177 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11178 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11181 // FIXME: We should custom lower this by fixing the condition and using i8
11187 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11188 MVT VT = Op.getSimpleValueType();
11191 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11194 if (VT.getSizeInBits() == 8) {
11195 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11196 Op.getOperand(0), Op.getOperand(1));
11197 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11198 DAG.getValueType(VT));
11199 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11202 if (VT.getSizeInBits() == 16) {
11203 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11204 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11206 return DAG.getNode(
11207 ISD::TRUNCATE, dl, MVT::i16,
11208 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11209 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11210 Op.getOperand(1)));
11211 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11212 Op.getOperand(0), Op.getOperand(1));
11213 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11214 DAG.getValueType(VT));
11215 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11218 if (VT == MVT::f32) {
11219 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11220 // the result back to FR32 register. It's only worth matching if the
11221 // result has a single use which is a store or a bitcast to i32. And in
11222 // the case of a store, it's not worth it if the index is a constant 0,
11223 // because a MOVSSmr can be used instead, which is smaller and faster.
11224 if (!Op.hasOneUse())
11226 SDNode *User = *Op.getNode()->use_begin();
11227 if ((User->getOpcode() != ISD::STORE ||
11228 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11229 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11230 (User->getOpcode() != ISD::BITCAST ||
11231 User->getValueType(0) != MVT::i32))
11233 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11234 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11236 return DAG.getBitcast(MVT::f32, Extract);
11239 if (VT == MVT::i32 || VT == MVT::i64) {
11240 // ExtractPS/pextrq works with constant index.
11241 if (isa<ConstantSDNode>(Op.getOperand(1)))
11247 /// Extract one bit from mask vector, like v16i1 or v8i1.
11248 /// AVX-512 feature.
11250 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11251 SDValue Vec = Op.getOperand(0);
11253 MVT VecVT = Vec.getSimpleValueType();
11254 SDValue Idx = Op.getOperand(1);
11255 MVT EltVT = Op.getSimpleValueType();
11257 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11258 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11259 "Unexpected vector type in ExtractBitFromMaskVector");
11261 // variable index can't be handled in mask registers,
11262 // extend vector to VR512
11263 if (!isa<ConstantSDNode>(Idx)) {
11264 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11265 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11266 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11267 ExtVT.getVectorElementType(), Ext, Idx);
11268 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11271 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11272 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11273 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11274 rc = getRegClassFor(MVT::v16i1);
11275 unsigned MaxSift = rc->getSize()*8 - 1;
11276 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11277 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11278 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11279 DAG.getConstant(MaxSift, dl, MVT::i8));
11280 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11281 DAG.getIntPtrConstant(0, dl));
11285 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11286 SelectionDAG &DAG) const {
11288 SDValue Vec = Op.getOperand(0);
11289 MVT VecVT = Vec.getSimpleValueType();
11290 SDValue Idx = Op.getOperand(1);
11292 if (Op.getSimpleValueType() == MVT::i1)
11293 return ExtractBitFromMaskVector(Op, DAG);
11295 if (!isa<ConstantSDNode>(Idx)) {
11296 if (VecVT.is512BitVector() ||
11297 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11298 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11301 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11302 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11303 MaskEltVT.getSizeInBits());
11305 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11306 auto PtrVT = getPointerTy(DAG.getDataLayout());
11307 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11308 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11309 DAG.getConstant(0, dl, PtrVT));
11310 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11311 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11312 DAG.getConstant(0, dl, PtrVT));
11317 // If this is a 256-bit vector result, first extract the 128-bit vector and
11318 // then extract the element from the 128-bit vector.
11319 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11321 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11322 // Get the 128-bit vector.
11323 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11324 MVT EltVT = VecVT.getVectorElementType();
11326 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11328 //if (IdxVal >= NumElems/2)
11329 // IdxVal -= NumElems/2;
11330 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11331 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11332 DAG.getConstant(IdxVal, dl, MVT::i32));
11335 assert(VecVT.is128BitVector() && "Unexpected vector length");
11337 if (Subtarget->hasSSE41())
11338 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11341 MVT VT = Op.getSimpleValueType();
11342 // TODO: handle v16i8.
11343 if (VT.getSizeInBits() == 16) {
11344 SDValue Vec = Op.getOperand(0);
11345 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11347 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11348 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11349 DAG.getBitcast(MVT::v4i32, Vec),
11350 Op.getOperand(1)));
11351 // Transform it so it match pextrw which produces a 32-bit result.
11352 MVT EltVT = MVT::i32;
11353 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11354 Op.getOperand(0), Op.getOperand(1));
11355 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11356 DAG.getValueType(VT));
11357 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11360 if (VT.getSizeInBits() == 32) {
11361 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11365 // SHUFPS the element to the lowest double word, then movss.
11366 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11367 MVT VVT = Op.getOperand(0).getSimpleValueType();
11368 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11369 DAG.getUNDEF(VVT), Mask);
11370 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11371 DAG.getIntPtrConstant(0, dl));
11374 if (VT.getSizeInBits() == 64) {
11375 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11376 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11377 // to match extract_elt for f64.
11378 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11382 // UNPCKHPD the element to the lowest double word, then movsd.
11383 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11384 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11385 int Mask[2] = { 1, -1 };
11386 MVT VVT = Op.getOperand(0).getSimpleValueType();
11387 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11388 DAG.getUNDEF(VVT), Mask);
11389 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11390 DAG.getIntPtrConstant(0, dl));
11396 /// Insert one bit to mask vector, like v16i1 or v8i1.
11397 /// AVX-512 feature.
11399 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11401 SDValue Vec = Op.getOperand(0);
11402 SDValue Elt = Op.getOperand(1);
11403 SDValue Idx = Op.getOperand(2);
11404 MVT VecVT = Vec.getSimpleValueType();
11406 if (!isa<ConstantSDNode>(Idx)) {
11407 // Non constant index. Extend source and destination,
11408 // insert element and then truncate the result.
11409 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11410 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11411 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11412 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11413 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11414 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11417 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11418 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11420 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11421 DAG.getConstant(IdxVal, dl, MVT::i8));
11422 if (Vec.getOpcode() == ISD::UNDEF)
11424 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11427 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11428 SelectionDAG &DAG) const {
11429 MVT VT = Op.getSimpleValueType();
11430 MVT EltVT = VT.getVectorElementType();
11432 if (EltVT == MVT::i1)
11433 return InsertBitToMaskVector(Op, DAG);
11436 SDValue N0 = Op.getOperand(0);
11437 SDValue N1 = Op.getOperand(1);
11438 SDValue N2 = Op.getOperand(2);
11439 if (!isa<ConstantSDNode>(N2))
11441 auto *N2C = cast<ConstantSDNode>(N2);
11442 unsigned IdxVal = N2C->getZExtValue();
11444 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11445 // into that, and then insert the subvector back into the result.
11446 if (VT.is256BitVector() || VT.is512BitVector()) {
11447 // With a 256-bit vector, we can insert into the zero element efficiently
11448 // using a blend if we have AVX or AVX2 and the right data type.
11449 if (VT.is256BitVector() && IdxVal == 0) {
11450 // TODO: It is worthwhile to cast integer to floating point and back
11451 // and incur a domain crossing penalty if that's what we'll end up
11452 // doing anyway after extracting to a 128-bit vector.
11453 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11454 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11455 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11456 N2 = DAG.getIntPtrConstant(1, dl);
11457 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11461 // Get the desired 128-bit vector chunk.
11462 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11464 // Insert the element into the desired chunk.
11465 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11466 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11468 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11469 DAG.getConstant(IdxIn128, dl, MVT::i32));
11471 // Insert the changed part back into the bigger vector
11472 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11474 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11476 if (Subtarget->hasSSE41()) {
11477 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11479 if (VT == MVT::v8i16) {
11480 Opc = X86ISD::PINSRW;
11482 assert(VT == MVT::v16i8);
11483 Opc = X86ISD::PINSRB;
11486 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11488 if (N1.getValueType() != MVT::i32)
11489 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11490 if (N2.getValueType() != MVT::i32)
11491 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11492 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11495 if (EltVT == MVT::f32) {
11496 // Bits [7:6] of the constant are the source select. This will always be
11497 // zero here. The DAG Combiner may combine an extract_elt index into
11498 // these bits. For example (insert (extract, 3), 2) could be matched by
11499 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11500 // Bits [5:4] of the constant are the destination select. This is the
11501 // value of the incoming immediate.
11502 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11503 // combine either bitwise AND or insert of float 0.0 to set these bits.
11505 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11506 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11507 // If this is an insertion of 32-bits into the low 32-bits of
11508 // a vector, we prefer to generate a blend with immediate rather
11509 // than an insertps. Blends are simpler operations in hardware and so
11510 // will always have equal or better performance than insertps.
11511 // But if optimizing for size and there's a load folding opportunity,
11512 // generate insertps because blendps does not have a 32-bit memory
11514 N2 = DAG.getIntPtrConstant(1, dl);
11515 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11516 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11518 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11519 // Create this as a scalar to vector..
11520 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11521 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11524 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11525 // PINSR* works with constant index.
11530 if (EltVT == MVT::i8)
11533 if (EltVT.getSizeInBits() == 16) {
11534 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11535 // as its second argument.
11536 if (N1.getValueType() != MVT::i32)
11537 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11538 if (N2.getValueType() != MVT::i32)
11539 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11540 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11545 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11547 MVT OpVT = Op.getSimpleValueType();
11549 // If this is a 256-bit vector result, first insert into a 128-bit
11550 // vector and then insert into the 256-bit vector.
11551 if (!OpVT.is128BitVector()) {
11552 // Insert into a 128-bit vector.
11553 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11554 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11555 OpVT.getVectorNumElements() / SizeFactor);
11557 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11559 // Insert the 128-bit vector.
11560 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11563 if (OpVT == MVT::v1i64 &&
11564 Op.getOperand(0).getValueType() == MVT::i64)
11565 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11567 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11568 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11569 return DAG.getBitcast(
11570 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11573 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11574 // a simple subregister reference or explicit instructions to grab
11575 // upper bits of a vector.
11576 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11577 SelectionDAG &DAG) {
11579 SDValue In = Op.getOperand(0);
11580 SDValue Idx = Op.getOperand(1);
11581 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11582 MVT ResVT = Op.getSimpleValueType();
11583 MVT InVT = In.getSimpleValueType();
11585 if (Subtarget->hasFp256()) {
11586 if (ResVT.is128BitVector() &&
11587 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11588 isa<ConstantSDNode>(Idx)) {
11589 return Extract128BitVector(In, IdxVal, DAG, dl);
11591 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11592 isa<ConstantSDNode>(Idx)) {
11593 return Extract256BitVector(In, IdxVal, DAG, dl);
11599 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11600 // simple superregister reference or explicit instructions to insert
11601 // the upper bits of a vector.
11602 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11603 SelectionDAG &DAG) {
11604 if (!Subtarget->hasAVX())
11608 SDValue Vec = Op.getOperand(0);
11609 SDValue SubVec = Op.getOperand(1);
11610 SDValue Idx = Op.getOperand(2);
11612 if (!isa<ConstantSDNode>(Idx))
11615 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11616 MVT OpVT = Op.getSimpleValueType();
11617 MVT SubVecVT = SubVec.getSimpleValueType();
11619 // Fold two 16-byte subvector loads into one 32-byte load:
11620 // (insert_subvector (insert_subvector undef, (load addr), 0),
11621 // (load addr + 16), Elts/2)
11623 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11624 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11625 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11626 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11627 if (Idx2 && Idx2->getZExtValue() == 0) {
11628 SDValue SubVec2 = Vec.getOperand(1);
11629 // If needed, look through a bitcast to get to the load.
11630 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11631 SubVec2 = SubVec2.getOperand(0);
11633 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11635 unsigned Alignment = FirstLd->getAlignment();
11636 unsigned AS = FirstLd->getAddressSpace();
11637 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11638 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11639 OpVT, AS, Alignment, &Fast) && Fast) {
11640 SDValue Ops[] = { SubVec2, SubVec };
11641 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11648 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11649 SubVecVT.is128BitVector())
11650 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11652 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11653 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11655 if (OpVT.getVectorElementType() == MVT::i1) {
11656 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11658 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11659 SDValue Undef = DAG.getUNDEF(OpVT);
11660 unsigned NumElems = OpVT.getVectorNumElements();
11661 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11663 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11664 // Zero upper bits of the Vec
11665 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11666 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11668 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11670 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11671 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11674 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11676 // Zero upper bits of the Vec2
11677 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11678 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11679 // Zero lower bits of the Vec
11680 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11681 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11682 // Merge them together
11683 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11689 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11690 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11691 // one of the above mentioned nodes. It has to be wrapped because otherwise
11692 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11693 // be used to form addressing mode. These wrapped nodes will be selected
11696 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11697 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11699 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11700 // global base reg.
11701 unsigned char OpFlag = 0;
11702 unsigned WrapperKind = X86ISD::Wrapper;
11703 CodeModel::Model M = DAG.getTarget().getCodeModel();
11705 if (Subtarget->isPICStyleRIPRel() &&
11706 (M == CodeModel::Small || M == CodeModel::Kernel))
11707 WrapperKind = X86ISD::WrapperRIP;
11708 else if (Subtarget->isPICStyleGOT())
11709 OpFlag = X86II::MO_GOTOFF;
11710 else if (Subtarget->isPICStyleStubPIC())
11711 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11713 auto PtrVT = getPointerTy(DAG.getDataLayout());
11714 SDValue Result = DAG.getTargetConstantPool(
11715 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11717 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11718 // With PIC, the address is actually $g + Offset.
11721 DAG.getNode(ISD::ADD, DL, PtrVT,
11722 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11728 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11729 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11731 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11732 // global base reg.
11733 unsigned char OpFlag = 0;
11734 unsigned WrapperKind = X86ISD::Wrapper;
11735 CodeModel::Model M = DAG.getTarget().getCodeModel();
11737 if (Subtarget->isPICStyleRIPRel() &&
11738 (M == CodeModel::Small || M == CodeModel::Kernel))
11739 WrapperKind = X86ISD::WrapperRIP;
11740 else if (Subtarget->isPICStyleGOT())
11741 OpFlag = X86II::MO_GOTOFF;
11742 else if (Subtarget->isPICStyleStubPIC())
11743 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11745 auto PtrVT = getPointerTy(DAG.getDataLayout());
11746 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11748 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11750 // With PIC, the address is actually $g + Offset.
11753 DAG.getNode(ISD::ADD, DL, PtrVT,
11754 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11760 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11761 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11763 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11764 // global base reg.
11765 unsigned char OpFlag = 0;
11766 unsigned WrapperKind = X86ISD::Wrapper;
11767 CodeModel::Model M = DAG.getTarget().getCodeModel();
11769 if (Subtarget->isPICStyleRIPRel() &&
11770 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11771 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11772 OpFlag = X86II::MO_GOTPCREL;
11773 WrapperKind = X86ISD::WrapperRIP;
11774 } else if (Subtarget->isPICStyleGOT()) {
11775 OpFlag = X86II::MO_GOT;
11776 } else if (Subtarget->isPICStyleStubPIC()) {
11777 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11778 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11779 OpFlag = X86II::MO_DARWIN_NONLAZY;
11782 auto PtrVT = getPointerTy(DAG.getDataLayout());
11783 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11786 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11788 // With PIC, the address is actually $g + Offset.
11789 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11790 !Subtarget->is64Bit()) {
11792 DAG.getNode(ISD::ADD, DL, PtrVT,
11793 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11796 // For symbols that require a load from a stub to get the address, emit the
11798 if (isGlobalStubReference(OpFlag))
11799 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11800 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11801 false, false, false, 0);
11807 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11808 // Create the TargetBlockAddressAddress node.
11809 unsigned char OpFlags =
11810 Subtarget->ClassifyBlockAddressReference();
11811 CodeModel::Model M = DAG.getTarget().getCodeModel();
11812 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11813 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11815 auto PtrVT = getPointerTy(DAG.getDataLayout());
11816 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11818 if (Subtarget->isPICStyleRIPRel() &&
11819 (M == CodeModel::Small || M == CodeModel::Kernel))
11820 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11822 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11824 // With PIC, the address is actually $g + Offset.
11825 if (isGlobalRelativeToPICBase(OpFlags)) {
11826 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11827 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11834 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11835 int64_t Offset, SelectionDAG &DAG) const {
11836 // Create the TargetGlobalAddress node, folding in the constant
11837 // offset if it is legal.
11838 unsigned char OpFlags =
11839 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11840 CodeModel::Model M = DAG.getTarget().getCodeModel();
11841 auto PtrVT = getPointerTy(DAG.getDataLayout());
11843 if (OpFlags == X86II::MO_NO_FLAG &&
11844 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11845 // A direct static reference to a global.
11846 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11849 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11852 if (Subtarget->isPICStyleRIPRel() &&
11853 (M == CodeModel::Small || M == CodeModel::Kernel))
11854 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11856 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11858 // With PIC, the address is actually $g + Offset.
11859 if (isGlobalRelativeToPICBase(OpFlags)) {
11860 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11861 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11864 // For globals that require a load from a stub to get the address, emit the
11866 if (isGlobalStubReference(OpFlags))
11867 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11868 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11869 false, false, false, 0);
11871 // If there was a non-zero offset that we didn't fold, create an explicit
11872 // addition for it.
11874 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11875 DAG.getConstant(Offset, dl, PtrVT));
11881 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11882 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11883 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11884 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11888 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11889 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11890 unsigned char OperandFlags, bool LocalDynamic = false) {
11891 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11892 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11894 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11895 GA->getValueType(0),
11899 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11903 SDValue Ops[] = { Chain, TGA, *InFlag };
11904 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11906 SDValue Ops[] = { Chain, TGA };
11907 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11910 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11911 MFI->setAdjustsStack(true);
11912 MFI->setHasCalls(true);
11914 SDValue Flag = Chain.getValue(1);
11915 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11918 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11920 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11923 SDLoc dl(GA); // ? function entry point might be better
11924 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11925 DAG.getNode(X86ISD::GlobalBaseReg,
11926 SDLoc(), PtrVT), InFlag);
11927 InFlag = Chain.getValue(1);
11929 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11932 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11934 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11936 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11937 X86::RAX, X86II::MO_TLSGD);
11940 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11946 // Get the start address of the TLS block for this module.
11947 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11948 .getInfo<X86MachineFunctionInfo>();
11949 MFI->incNumLocalDynamicTLSAccesses();
11953 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11954 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11957 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11958 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11959 InFlag = Chain.getValue(1);
11960 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11961 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11964 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11968 unsigned char OperandFlags = X86II::MO_DTPOFF;
11969 unsigned WrapperKind = X86ISD::Wrapper;
11970 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11971 GA->getValueType(0),
11972 GA->getOffset(), OperandFlags);
11973 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11975 // Add x@dtpoff with the base.
11976 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11979 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11980 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11981 const EVT PtrVT, TLSModel::Model model,
11982 bool is64Bit, bool isPIC) {
11985 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11986 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11987 is64Bit ? 257 : 256));
11989 SDValue ThreadPointer =
11990 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11991 MachinePointerInfo(Ptr), false, false, false, 0);
11993 unsigned char OperandFlags = 0;
11994 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11996 unsigned WrapperKind = X86ISD::Wrapper;
11997 if (model == TLSModel::LocalExec) {
11998 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11999 } else if (model == TLSModel::InitialExec) {
12001 OperandFlags = X86II::MO_GOTTPOFF;
12002 WrapperKind = X86ISD::WrapperRIP;
12004 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12007 llvm_unreachable("Unexpected model");
12010 // emit "addl x@ntpoff,%eax" (local exec)
12011 // or "addl x@indntpoff,%eax" (initial exec)
12012 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12014 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12015 GA->getOffset(), OperandFlags);
12016 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12018 if (model == TLSModel::InitialExec) {
12019 if (isPIC && !is64Bit) {
12020 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12021 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12025 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12026 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12027 false, false, false, 0);
12030 // The address of the thread local variable is the add of the thread
12031 // pointer with the offset of the variable.
12032 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12036 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12038 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12039 const GlobalValue *GV = GA->getGlobal();
12040 auto PtrVT = getPointerTy(DAG.getDataLayout());
12042 if (Subtarget->isTargetELF()) {
12043 if (DAG.getTarget().Options.EmulatedTLS)
12044 return LowerToTLSEmulatedModel(GA, DAG);
12045 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12047 case TLSModel::GeneralDynamic:
12048 if (Subtarget->is64Bit())
12049 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12050 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12051 case TLSModel::LocalDynamic:
12052 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12053 Subtarget->is64Bit());
12054 case TLSModel::InitialExec:
12055 case TLSModel::LocalExec:
12056 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12057 DAG.getTarget().getRelocationModel() ==
12060 llvm_unreachable("Unknown TLS model.");
12063 if (Subtarget->isTargetDarwin()) {
12064 // Darwin only has one model of TLS. Lower to that.
12065 unsigned char OpFlag = 0;
12066 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12067 X86ISD::WrapperRIP : X86ISD::Wrapper;
12069 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12070 // global base reg.
12071 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12072 !Subtarget->is64Bit();
12074 OpFlag = X86II::MO_TLVP_PIC_BASE;
12076 OpFlag = X86II::MO_TLVP;
12078 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12079 GA->getValueType(0),
12080 GA->getOffset(), OpFlag);
12081 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12083 // With PIC32, the address is actually $g + Offset.
12085 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12086 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12089 // Lowering the machine isd will make sure everything is in the right
12091 SDValue Chain = DAG.getEntryNode();
12092 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12093 SDValue Args[] = { Chain, Offset };
12094 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12096 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12097 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12098 MFI->setAdjustsStack(true);
12100 // And our return value (tls address) is in the standard call return value
12102 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12103 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12106 if (Subtarget->isTargetKnownWindowsMSVC() ||
12107 Subtarget->isTargetWindowsGNU()) {
12108 // Just use the implicit TLS architecture
12109 // Need to generate someting similar to:
12110 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12112 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12113 // mov rcx, qword [rdx+rcx*8]
12114 // mov eax, .tls$:tlsvar
12115 // [rax+rcx] contains the address
12116 // Windows 64bit: gs:0x58
12117 // Windows 32bit: fs:__tls_array
12120 SDValue Chain = DAG.getEntryNode();
12122 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12123 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12124 // use its literal value of 0x2C.
12125 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12126 ? Type::getInt8PtrTy(*DAG.getContext(),
12128 : Type::getInt32PtrTy(*DAG.getContext(),
12131 SDValue TlsArray = Subtarget->is64Bit()
12132 ? DAG.getIntPtrConstant(0x58, dl)
12133 : (Subtarget->isTargetWindowsGNU()
12134 ? DAG.getIntPtrConstant(0x2C, dl)
12135 : DAG.getExternalSymbol("_tls_array", PtrVT));
12137 SDValue ThreadPointer =
12138 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12142 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12143 res = ThreadPointer;
12145 // Load the _tls_index variable
12146 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12147 if (Subtarget->is64Bit())
12148 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12149 MachinePointerInfo(), MVT::i32, false, false,
12152 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12155 auto &DL = DAG.getDataLayout();
12157 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12158 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12160 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12163 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12166 // Get the offset of start of .tls section
12167 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12168 GA->getValueType(0),
12169 GA->getOffset(), X86II::MO_SECREL);
12170 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12172 // The address of the thread local variable is the add of the thread
12173 // pointer with the offset of the variable.
12174 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12177 llvm_unreachable("TLS not implemented for this target.");
12180 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12181 /// and take a 2 x i32 value to shift plus a shift amount.
12182 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12183 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12184 MVT VT = Op.getSimpleValueType();
12185 unsigned VTBits = VT.getSizeInBits();
12187 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12188 SDValue ShOpLo = Op.getOperand(0);
12189 SDValue ShOpHi = Op.getOperand(1);
12190 SDValue ShAmt = Op.getOperand(2);
12191 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12192 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12194 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12195 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12196 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12197 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12198 : DAG.getConstant(0, dl, VT);
12200 SDValue Tmp2, Tmp3;
12201 if (Op.getOpcode() == ISD::SHL_PARTS) {
12202 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12203 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12205 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12206 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12209 // If the shift amount is larger or equal than the width of a part we can't
12210 // rely on the results of shld/shrd. Insert a test and select the appropriate
12211 // values for large shift amounts.
12212 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12213 DAG.getConstant(VTBits, dl, MVT::i8));
12214 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12215 AndNode, DAG.getConstant(0, dl, MVT::i8));
12218 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12219 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12220 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12222 if (Op.getOpcode() == ISD::SHL_PARTS) {
12223 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12224 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12226 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12227 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12230 SDValue Ops[2] = { Lo, Hi };
12231 return DAG.getMergeValues(Ops, dl);
12234 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12235 SelectionDAG &DAG) const {
12236 SDValue Src = Op.getOperand(0);
12237 MVT SrcVT = Src.getSimpleValueType();
12238 MVT VT = Op.getSimpleValueType();
12241 if (SrcVT.isVector()) {
12242 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12243 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12244 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12245 DAG.getUNDEF(SrcVT)));
12247 if (SrcVT.getVectorElementType() == MVT::i1) {
12248 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12249 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12250 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12255 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12256 "Unknown SINT_TO_FP to lower!");
12258 // These are really Legal; return the operand so the caller accepts it as
12260 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12262 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12263 Subtarget->is64Bit()) {
12267 unsigned Size = SrcVT.getSizeInBits()/8;
12268 MachineFunction &MF = DAG.getMachineFunction();
12269 auto PtrVT = getPointerTy(MF.getDataLayout());
12270 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12271 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12272 SDValue Chain = DAG.getStore(
12273 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12274 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12276 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12279 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12281 SelectionDAG &DAG) const {
12285 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12287 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12289 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12291 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12293 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12294 MachineMemOperand *MMO;
12296 int SSFI = FI->getIndex();
12297 MMO = DAG.getMachineFunction().getMachineMemOperand(
12298 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12299 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12301 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12302 StackSlot = StackSlot.getOperand(1);
12304 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12305 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12307 Tys, Ops, SrcVT, MMO);
12310 Chain = Result.getValue(1);
12311 SDValue InFlag = Result.getValue(2);
12313 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12314 // shouldn't be necessary except that RFP cannot be live across
12315 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12316 MachineFunction &MF = DAG.getMachineFunction();
12317 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12318 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12319 auto PtrVT = getPointerTy(MF.getDataLayout());
12320 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12321 Tys = DAG.getVTList(MVT::Other);
12323 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12325 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12326 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12327 MachineMemOperand::MOStore, SSFISize, SSFISize);
12329 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12330 Ops, Op.getValueType(), MMO);
12331 Result = DAG.getLoad(
12332 Op.getValueType(), DL, Chain, StackSlot,
12333 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12334 false, false, false, 0);
12340 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12341 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12342 SelectionDAG &DAG) const {
12343 // This algorithm is not obvious. Here it is what we're trying to output:
12346 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12347 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12349 haddpd %xmm0, %xmm0
12351 pshufd $0x4e, %xmm0, %xmm1
12357 LLVMContext *Context = DAG.getContext();
12359 // Build some magic constants.
12360 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12361 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12362 auto PtrVT = getPointerTy(DAG.getDataLayout());
12363 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12365 SmallVector<Constant*,2> CV1;
12367 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12368 APInt(64, 0x4330000000000000ULL))));
12370 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12371 APInt(64, 0x4530000000000000ULL))));
12372 Constant *C1 = ConstantVector::get(CV1);
12373 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12375 // Load the 64-bit value into an XMM register.
12376 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12379 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12380 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12381 false, false, false, 16);
12383 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12386 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12387 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12388 false, false, false, 16);
12389 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12390 // TODO: Are there any fast-math-flags to propagate here?
12391 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12394 if (Subtarget->hasSSE3()) {
12395 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12396 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12398 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12399 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12401 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12402 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12405 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12406 DAG.getIntPtrConstant(0, dl));
12409 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12410 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12411 SelectionDAG &DAG) const {
12413 // FP constant to bias correct the final result.
12414 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12417 // Load the 32-bit value into an XMM register.
12418 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12421 // Zero out the upper parts of the register.
12422 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12424 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12425 DAG.getBitcast(MVT::v2f64, Load),
12426 DAG.getIntPtrConstant(0, dl));
12428 // Or the load with the bias.
12429 SDValue Or = DAG.getNode(
12430 ISD::OR, dl, MVT::v2i64,
12431 DAG.getBitcast(MVT::v2i64,
12432 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12433 DAG.getBitcast(MVT::v2i64,
12434 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12436 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12437 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12439 // Subtract the bias.
12440 // TODO: Are there any fast-math-flags to propagate here?
12441 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12443 // Handle final rounding.
12444 EVT DestVT = Op.getValueType();
12446 if (DestVT.bitsLT(MVT::f64))
12447 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12448 DAG.getIntPtrConstant(0, dl));
12449 if (DestVT.bitsGT(MVT::f64))
12450 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12452 // Handle final rounding.
12456 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12457 const X86Subtarget &Subtarget) {
12458 // The algorithm is the following:
12459 // #ifdef __SSE4_1__
12460 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12461 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12462 // (uint4) 0x53000000, 0xaa);
12464 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12465 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12467 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12468 // return (float4) lo + fhi;
12470 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12471 // reassociate the two FADDs, and if we do that, the algorithm fails
12472 // spectacularly (PR24512).
12473 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12474 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12475 // there's also the MachineCombiner reassociations happening on Machine IR.
12476 if (DAG.getTarget().Options.UnsafeFPMath)
12480 SDValue V = Op->getOperand(0);
12481 EVT VecIntVT = V.getValueType();
12482 bool Is128 = VecIntVT == MVT::v4i32;
12483 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12484 // If we convert to something else than the supported type, e.g., to v4f64,
12486 if (VecFloatVT != Op->getValueType(0))
12489 unsigned NumElts = VecIntVT.getVectorNumElements();
12490 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12491 "Unsupported custom type");
12492 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12494 // In the #idef/#else code, we have in common:
12495 // - The vector of constants:
12501 // Create the splat vector for 0x4b000000.
12502 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12503 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12504 CstLow, CstLow, CstLow, CstLow};
12505 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12506 makeArrayRef(&CstLowArray[0], NumElts));
12507 // Create the splat vector for 0x53000000.
12508 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12509 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12510 CstHigh, CstHigh, CstHigh, CstHigh};
12511 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12512 makeArrayRef(&CstHighArray[0], NumElts));
12514 // Create the right shift.
12515 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12516 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12517 CstShift, CstShift, CstShift, CstShift};
12518 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12519 makeArrayRef(&CstShiftArray[0], NumElts));
12520 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12523 if (Subtarget.hasSSE41()) {
12524 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12525 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12526 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12527 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12528 // Low will be bitcasted right away, so do not bother bitcasting back to its
12530 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12531 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12532 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12533 // (uint4) 0x53000000, 0xaa);
12534 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12535 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12536 // High will be bitcasted right away, so do not bother bitcasting back to
12537 // its original type.
12538 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12539 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12541 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12542 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12543 CstMask, CstMask, CstMask);
12544 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12545 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12546 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12548 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12549 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12552 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12553 SDValue CstFAdd = DAG.getConstantFP(
12554 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12555 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12556 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12557 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12558 makeArrayRef(&CstFAddArray[0], NumElts));
12560 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12561 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12562 // TODO: Are there any fast-math-flags to propagate here?
12564 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12565 // return (float4) lo + fhi;
12566 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12567 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12570 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12571 SelectionDAG &DAG) const {
12572 SDValue N0 = Op.getOperand(0);
12573 MVT SVT = N0.getSimpleValueType();
12576 switch (SVT.SimpleTy) {
12578 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12583 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12584 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12585 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12589 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12592 if (Subtarget->hasAVX512())
12593 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12594 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12596 llvm_unreachable(nullptr);
12599 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12600 SelectionDAG &DAG) const {
12601 SDValue N0 = Op.getOperand(0);
12603 auto PtrVT = getPointerTy(DAG.getDataLayout());
12605 if (Op.getValueType().isVector())
12606 return lowerUINT_TO_FP_vec(Op, DAG);
12608 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12609 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12610 // the optimization here.
12611 if (DAG.SignBitIsZero(N0))
12612 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12614 MVT SrcVT = N0.getSimpleValueType();
12615 MVT DstVT = Op.getSimpleValueType();
12617 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12618 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12619 // Conversions from unsigned i32 to f32/f64 are legal,
12620 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12624 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12625 return LowerUINT_TO_FP_i64(Op, DAG);
12626 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12627 return LowerUINT_TO_FP_i32(Op, DAG);
12628 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12631 // Make a 64-bit buffer, and use it to build an FILD.
12632 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12633 if (SrcVT == MVT::i32) {
12634 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12635 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12636 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12637 StackSlot, MachinePointerInfo(),
12639 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12640 OffsetSlot, MachinePointerInfo(),
12642 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12646 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12647 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12648 StackSlot, MachinePointerInfo(),
12650 // For i64 source, we need to add the appropriate power of 2 if the input
12651 // was negative. This is the same as the optimization in
12652 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12653 // we must be careful to do the computation in x87 extended precision, not
12654 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12655 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12656 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12657 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12658 MachineMemOperand::MOLoad, 8, 8);
12660 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12661 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12662 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12665 APInt FF(32, 0x5F800000ULL);
12667 // Check whether the sign bit is set.
12668 SDValue SignSet = DAG.getSetCC(
12669 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12670 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12672 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12673 SDValue FudgePtr = DAG.getConstantPool(
12674 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12676 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12677 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12678 SDValue Four = DAG.getIntPtrConstant(4, dl);
12679 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12681 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12683 // Load the value out, extending it from f32 to f80.
12684 // FIXME: Avoid the extend by constructing the right constant pool?
12685 SDValue Fudge = DAG.getExtLoad(
12686 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12687 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12688 false, false, false, 4);
12689 // Extend everything to 80 bits to force it to be done on x87.
12690 // TODO: Are there any fast-math-flags to propagate here?
12691 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12692 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12693 DAG.getIntPtrConstant(0, dl));
12696 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12697 // is legal, or has an f16 source (which needs to be promoted to f32),
12698 // just return an <SDValue(), SDValue()> pair.
12699 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12700 // to i16, i32 or i64, and we lower it to a legal sequence.
12701 // If lowered to the final integer result we return a <result, SDValue()> pair.
12702 // Otherwise we lower it to a sequence ending with a FIST, return a
12703 // <FIST, StackSlot> pair, and the caller is responsible for loading
12704 // the final integer result from StackSlot.
12705 std::pair<SDValue,SDValue>
12706 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12707 bool IsSigned, bool IsReplace) const {
12710 EVT DstTy = Op.getValueType();
12711 EVT TheVT = Op.getOperand(0).getValueType();
12712 auto PtrVT = getPointerTy(DAG.getDataLayout());
12714 if (TheVT == MVT::f16)
12715 // We need to promote the f16 to f32 before using the lowering
12716 // in this routine.
12717 return std::make_pair(SDValue(), SDValue());
12719 assert((TheVT == MVT::f32 ||
12720 TheVT == MVT::f64 ||
12721 TheVT == MVT::f80) &&
12722 "Unexpected FP operand type in FP_TO_INTHelper");
12724 // If using FIST to compute an unsigned i64, we'll need some fixup
12725 // to handle values above the maximum signed i64. A FIST is always
12726 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12727 bool UnsignedFixup = !IsSigned &&
12728 DstTy == MVT::i64 &&
12729 (!Subtarget->is64Bit() ||
12730 !isScalarFPTypeInSSEReg(TheVT));
12732 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12733 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12734 // The low 32 bits of the fist result will have the correct uint32 result.
12735 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12739 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12740 DstTy.getSimpleVT() >= MVT::i16 &&
12741 "Unknown FP_TO_INT to lower!");
12743 // These are really Legal.
12744 if (DstTy == MVT::i32 &&
12745 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12746 return std::make_pair(SDValue(), SDValue());
12747 if (Subtarget->is64Bit() &&
12748 DstTy == MVT::i64 &&
12749 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12750 return std::make_pair(SDValue(), SDValue());
12752 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12754 MachineFunction &MF = DAG.getMachineFunction();
12755 unsigned MemSize = DstTy.getSizeInBits()/8;
12756 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12757 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12760 switch (DstTy.getSimpleVT().SimpleTy) {
12761 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12762 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12763 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12764 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12767 SDValue Chain = DAG.getEntryNode();
12768 SDValue Value = Op.getOperand(0);
12769 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12771 if (UnsignedFixup) {
12773 // Conversion to unsigned i64 is implemented with a select,
12774 // depending on whether the source value fits in the range
12775 // of a signed i64. Let Thresh be the FP equivalent of
12776 // 0x8000000000000000ULL.
12778 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12779 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12780 // Fist-to-mem64 FistSrc
12781 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12782 // to XOR'ing the high 32 bits with Adjust.
12784 // Being a power of 2, Thresh is exactly representable in all FP formats.
12785 // For X87 we'd like to use the smallest FP type for this constant, but
12786 // for DAG type consistency we have to match the FP operand type.
12788 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12789 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12790 bool LosesInfo = false;
12791 if (TheVT == MVT::f64)
12792 // The rounding mode is irrelevant as the conversion should be exact.
12793 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12795 else if (TheVT == MVT::f80)
12796 Status = Thresh.convert(APFloat::x87DoubleExtended,
12797 APFloat::rmNearestTiesToEven, &LosesInfo);
12799 assert(Status == APFloat::opOK && !LosesInfo &&
12800 "FP conversion should have been exact");
12802 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12804 SDValue Cmp = DAG.getSetCC(DL,
12805 getSetCCResultType(DAG.getDataLayout(),
12806 *DAG.getContext(), TheVT),
12807 Value, ThreshVal, ISD::SETLT);
12808 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12809 DAG.getConstant(0, DL, MVT::i32),
12810 DAG.getConstant(0x80000000, DL, MVT::i32));
12811 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12812 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12813 *DAG.getContext(), TheVT),
12814 Value, ThreshVal, ISD::SETLT);
12815 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12818 // FIXME This causes a redundant load/store if the SSE-class value is already
12819 // in memory, such as if it is on the callstack.
12820 if (isScalarFPTypeInSSEReg(TheVT)) {
12821 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12822 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12823 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12825 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12827 Chain, StackSlot, DAG.getValueType(TheVT)
12830 MachineMemOperand *MMO =
12831 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12832 MachineMemOperand::MOLoad, MemSize, MemSize);
12833 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12834 Chain = Value.getValue(1);
12835 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12836 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12839 MachineMemOperand *MMO =
12840 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12841 MachineMemOperand::MOStore, MemSize, MemSize);
12843 if (UnsignedFixup) {
12845 // Insert the FIST, load its result as two i32's,
12846 // and XOR the high i32 with Adjust.
12848 SDValue FistOps[] = { Chain, Value, StackSlot };
12849 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12850 FistOps, DstTy, MMO);
12852 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12853 MachinePointerInfo(),
12854 false, false, false, 0);
12855 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12856 DAG.getConstant(4, DL, PtrVT));
12858 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12859 MachinePointerInfo(),
12860 false, false, false, 0);
12861 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12863 if (Subtarget->is64Bit()) {
12864 // Join High32 and Low32 into a 64-bit result.
12865 // (High32 << 32) | Low32
12866 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12867 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12868 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12869 DAG.getConstant(32, DL, MVT::i8));
12870 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12871 return std::make_pair(Result, SDValue());
12874 SDValue ResultOps[] = { Low32, High32 };
12876 SDValue pair = IsReplace
12877 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12878 : DAG.getMergeValues(ResultOps, DL);
12879 return std::make_pair(pair, SDValue());
12881 // Build the FP_TO_INT*_IN_MEM
12882 SDValue Ops[] = { Chain, Value, StackSlot };
12883 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12885 return std::make_pair(FIST, StackSlot);
12889 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12890 const X86Subtarget *Subtarget) {
12891 MVT VT = Op->getSimpleValueType(0);
12892 SDValue In = Op->getOperand(0);
12893 MVT InVT = In.getSimpleValueType();
12896 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12897 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12899 // Optimize vectors in AVX mode:
12902 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12903 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12904 // Concat upper and lower parts.
12907 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12908 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12909 // Concat upper and lower parts.
12912 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12913 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12914 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12917 if (Subtarget->hasInt256())
12918 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12920 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12921 SDValue Undef = DAG.getUNDEF(InVT);
12922 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12923 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12924 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12926 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12927 VT.getVectorNumElements()/2);
12929 OpLo = DAG.getBitcast(HVT, OpLo);
12930 OpHi = DAG.getBitcast(HVT, OpHi);
12932 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12935 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12936 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12937 MVT VT = Op->getSimpleValueType(0);
12938 SDValue In = Op->getOperand(0);
12939 MVT InVT = In.getSimpleValueType();
12941 unsigned int NumElts = VT.getVectorNumElements();
12942 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12945 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12946 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12948 assert(InVT.getVectorElementType() == MVT::i1);
12949 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12951 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12953 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12955 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12956 if (VT.is512BitVector())
12958 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12961 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12962 SelectionDAG &DAG) {
12963 if (Subtarget->hasFp256())
12964 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12970 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12971 SelectionDAG &DAG) {
12973 MVT VT = Op.getSimpleValueType();
12974 SDValue In = Op.getOperand(0);
12975 MVT SVT = In.getSimpleValueType();
12977 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12978 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12980 if (Subtarget->hasFp256())
12981 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12984 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12985 VT.getVectorNumElements() != SVT.getVectorNumElements());
12989 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12991 MVT VT = Op.getSimpleValueType();
12992 SDValue In = Op.getOperand(0);
12993 MVT InVT = In.getSimpleValueType();
12995 if (VT == MVT::i1) {
12996 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12997 "Invalid scalar TRUNCATE operation");
12998 if (InVT.getSizeInBits() >= 32)
13000 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13001 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13003 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13004 "Invalid TRUNCATE operation");
13006 // move vector to mask - truncate solution for SKX
13007 if (VT.getVectorElementType() == MVT::i1) {
13008 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13009 Subtarget->hasBWI())
13010 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13011 if ((InVT.is256BitVector() || InVT.is128BitVector())
13012 && InVT.getScalarSizeInBits() <= 16 &&
13013 Subtarget->hasBWI() && Subtarget->hasVLX())
13014 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13015 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13016 Subtarget->hasDQI())
13017 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13018 if ((InVT.is256BitVector() || InVT.is128BitVector())
13019 && InVT.getScalarSizeInBits() >= 32 &&
13020 Subtarget->hasDQI() && Subtarget->hasVLX())
13021 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13024 if (VT.getVectorElementType() == MVT::i1) {
13025 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13026 unsigned NumElts = InVT.getVectorNumElements();
13027 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13028 if (InVT.getSizeInBits() < 512) {
13029 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13030 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13035 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13036 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13037 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13040 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13041 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
13042 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
13043 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13045 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13046 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13047 if (Subtarget->hasInt256()) {
13048 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13049 In = DAG.getBitcast(MVT::v8i32, In);
13050 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13052 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13053 DAG.getIntPtrConstant(0, DL));
13056 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13057 DAG.getIntPtrConstant(0, DL));
13058 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13059 DAG.getIntPtrConstant(2, DL));
13060 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13061 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13062 static const int ShufMask[] = {0, 2, 4, 6};
13063 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13066 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13067 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13068 if (Subtarget->hasInt256()) {
13069 In = DAG.getBitcast(MVT::v32i8, In);
13071 SmallVector<SDValue,32> pshufbMask;
13072 for (unsigned i = 0; i < 2; ++i) {
13073 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13074 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13075 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13076 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13077 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13078 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13079 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13080 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13081 for (unsigned j = 0; j < 8; ++j)
13082 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13084 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13085 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13086 In = DAG.getBitcast(MVT::v4i64, In);
13088 static const int ShufMask[] = {0, 2, -1, -1};
13089 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13091 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13092 DAG.getIntPtrConstant(0, DL));
13093 return DAG.getBitcast(VT, In);
13096 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13097 DAG.getIntPtrConstant(0, DL));
13099 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13100 DAG.getIntPtrConstant(4, DL));
13102 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13103 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13105 // The PSHUFB mask:
13106 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13107 -1, -1, -1, -1, -1, -1, -1, -1};
13109 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13110 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13111 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13113 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13114 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13116 // The MOVLHPS Mask:
13117 static const int ShufMask2[] = {0, 1, 4, 5};
13118 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13119 return DAG.getBitcast(MVT::v8i16, res);
13122 // Handle truncation of V256 to V128 using shuffles.
13123 if (!VT.is128BitVector() || !InVT.is256BitVector())
13126 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13128 unsigned NumElems = VT.getVectorNumElements();
13129 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13131 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13132 // Prepare truncation shuffle mask
13133 for (unsigned i = 0; i != NumElems; ++i)
13134 MaskVec[i] = i * 2;
13135 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13136 DAG.getUNDEF(NVT), &MaskVec[0]);
13137 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13138 DAG.getIntPtrConstant(0, DL));
13141 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13142 SelectionDAG &DAG) const {
13143 assert(!Op.getSimpleValueType().isVector());
13145 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13146 /*IsSigned=*/ true, /*IsReplace=*/ false);
13147 SDValue FIST = Vals.first, StackSlot = Vals.second;
13148 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13149 if (!FIST.getNode())
13152 if (StackSlot.getNode())
13153 // Load the result.
13154 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13155 FIST, StackSlot, MachinePointerInfo(),
13156 false, false, false, 0);
13158 // The node is the result.
13162 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13163 SelectionDAG &DAG) const {
13164 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13165 /*IsSigned=*/ false, /*IsReplace=*/ false);
13166 SDValue FIST = Vals.first, StackSlot = Vals.second;
13167 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13168 if (!FIST.getNode())
13171 if (StackSlot.getNode())
13172 // Load the result.
13173 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13174 FIST, StackSlot, MachinePointerInfo(),
13175 false, false, false, 0);
13177 // The node is the result.
13181 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13183 MVT VT = Op.getSimpleValueType();
13184 SDValue In = Op.getOperand(0);
13185 MVT SVT = In.getSimpleValueType();
13187 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13189 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13190 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13191 In, DAG.getUNDEF(SVT)));
13194 /// The only differences between FABS and FNEG are the mask and the logic op.
13195 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13196 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13197 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13198 "Wrong opcode for lowering FABS or FNEG.");
13200 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13202 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13203 // into an FNABS. We'll lower the FABS after that if it is still in use.
13205 for (SDNode *User : Op->uses())
13206 if (User->getOpcode() == ISD::FNEG)
13210 MVT VT = Op.getSimpleValueType();
13212 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13213 // decide if we should generate a 16-byte constant mask when we only need 4 or
13214 // 8 bytes for the scalar case.
13220 if (VT.isVector()) {
13222 EltVT = VT.getVectorElementType();
13223 NumElts = VT.getVectorNumElements();
13225 // There are no scalar bitwise logical SSE/AVX instructions, so we
13226 // generate a 16-byte vector constant and logic op even for the scalar case.
13227 // Using a 16-byte mask allows folding the load of the mask with
13228 // the logic op, so it can save (~4 bytes) on code size.
13229 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13231 NumElts = (VT == MVT::f64) ? 2 : 4;
13234 unsigned EltBits = EltVT.getSizeInBits();
13235 LLVMContext *Context = DAG.getContext();
13236 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13238 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13239 Constant *C = ConstantInt::get(*Context, MaskElt);
13240 C = ConstantVector::getSplat(NumElts, C);
13241 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13242 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13243 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13245 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13246 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13247 false, false, false, Alignment);
13249 SDValue Op0 = Op.getOperand(0);
13250 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13252 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13253 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13256 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13258 // For the scalar case extend to a 128-bit vector, perform the logic op,
13259 // and extract the scalar result back out.
13260 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13261 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13262 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13263 DAG.getIntPtrConstant(0, dl));
13266 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13267 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13268 LLVMContext *Context = DAG.getContext();
13269 SDValue Op0 = Op.getOperand(0);
13270 SDValue Op1 = Op.getOperand(1);
13272 MVT VT = Op.getSimpleValueType();
13273 MVT SrcVT = Op1.getSimpleValueType();
13275 // If second operand is smaller, extend it first.
13276 if (SrcVT.bitsLT(VT)) {
13277 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13280 // And if it is bigger, shrink it first.
13281 if (SrcVT.bitsGT(VT)) {
13282 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13286 // At this point the operands and the result should have the same
13287 // type, and that won't be f80 since that is not custom lowered.
13289 const fltSemantics &Sem =
13290 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13291 const unsigned SizeInBits = VT.getSizeInBits();
13293 SmallVector<Constant *, 4> CV(
13294 VT == MVT::f64 ? 2 : 4,
13295 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13297 // First, clear all bits but the sign bit from the second operand (sign).
13298 CV[0] = ConstantFP::get(*Context,
13299 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13300 Constant *C = ConstantVector::get(CV);
13301 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13302 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13304 // Perform all logic operations as 16-byte vectors because there are no
13305 // scalar FP logic instructions in SSE. This allows load folding of the
13306 // constants into the logic instructions.
13307 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13309 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13310 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13311 false, false, false, 16);
13312 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13313 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13315 // Next, clear the sign bit from the first operand (magnitude).
13316 // If it's a constant, we can clear it here.
13317 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13318 APFloat APF = Op0CN->getValueAPF();
13319 // If the magnitude is a positive zero, the sign bit alone is enough.
13320 if (APF.isPosZero())
13321 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13322 DAG.getIntPtrConstant(0, dl));
13324 CV[0] = ConstantFP::get(*Context, APF);
13326 CV[0] = ConstantFP::get(
13328 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13330 C = ConstantVector::get(CV);
13331 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13333 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13334 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13335 false, false, false, 16);
13336 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13337 if (!isa<ConstantFPSDNode>(Op0)) {
13338 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13339 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13341 // OR the magnitude value with the sign bit.
13342 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13343 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13344 DAG.getIntPtrConstant(0, dl));
13347 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13348 SDValue N0 = Op.getOperand(0);
13350 MVT VT = Op.getSimpleValueType();
13352 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13353 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13354 DAG.getConstant(1, dl, VT));
13355 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13358 // Check whether an OR'd tree is PTEST-able.
13359 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13360 SelectionDAG &DAG) {
13361 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13363 if (!Subtarget->hasSSE41())
13366 if (!Op->hasOneUse())
13369 SDNode *N = Op.getNode();
13372 SmallVector<SDValue, 8> Opnds;
13373 DenseMap<SDValue, unsigned> VecInMap;
13374 SmallVector<SDValue, 8> VecIns;
13375 EVT VT = MVT::Other;
13377 // Recognize a special case where a vector is casted into wide integer to
13379 Opnds.push_back(N->getOperand(0));
13380 Opnds.push_back(N->getOperand(1));
13382 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13383 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13384 // BFS traverse all OR'd operands.
13385 if (I->getOpcode() == ISD::OR) {
13386 Opnds.push_back(I->getOperand(0));
13387 Opnds.push_back(I->getOperand(1));
13388 // Re-evaluate the number of nodes to be traversed.
13389 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13393 // Quit if a non-EXTRACT_VECTOR_ELT
13394 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13397 // Quit if without a constant index.
13398 SDValue Idx = I->getOperand(1);
13399 if (!isa<ConstantSDNode>(Idx))
13402 SDValue ExtractedFromVec = I->getOperand(0);
13403 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13404 if (M == VecInMap.end()) {
13405 VT = ExtractedFromVec.getValueType();
13406 // Quit if not 128/256-bit vector.
13407 if (!VT.is128BitVector() && !VT.is256BitVector())
13409 // Quit if not the same type.
13410 if (VecInMap.begin() != VecInMap.end() &&
13411 VT != VecInMap.begin()->first.getValueType())
13413 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13414 VecIns.push_back(ExtractedFromVec);
13416 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13419 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13420 "Not extracted from 128-/256-bit vector.");
13422 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13424 for (DenseMap<SDValue, unsigned>::const_iterator
13425 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13426 // Quit if not all elements are used.
13427 if (I->second != FullMask)
13431 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13433 // Cast all vectors into TestVT for PTEST.
13434 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13435 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13437 // If more than one full vectors are evaluated, OR them first before PTEST.
13438 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13439 // Each iteration will OR 2 nodes and append the result until there is only
13440 // 1 node left, i.e. the final OR'd value of all vectors.
13441 SDValue LHS = VecIns[Slot];
13442 SDValue RHS = VecIns[Slot + 1];
13443 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13446 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13447 VecIns.back(), VecIns.back());
13450 /// \brief return true if \c Op has a use that doesn't just read flags.
13451 static bool hasNonFlagsUse(SDValue Op) {
13452 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13454 SDNode *User = *UI;
13455 unsigned UOpNo = UI.getOperandNo();
13456 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13457 // Look pass truncate.
13458 UOpNo = User->use_begin().getOperandNo();
13459 User = *User->use_begin();
13462 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13463 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13469 /// Emit nodes that will be selected as "test Op0,Op0", or something
13471 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13472 SelectionDAG &DAG) const {
13473 if (Op.getValueType() == MVT::i1) {
13474 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13475 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13476 DAG.getConstant(0, dl, MVT::i8));
13478 // CF and OF aren't always set the way we want. Determine which
13479 // of these we need.
13480 bool NeedCF = false;
13481 bool NeedOF = false;
13484 case X86::COND_A: case X86::COND_AE:
13485 case X86::COND_B: case X86::COND_BE:
13488 case X86::COND_G: case X86::COND_GE:
13489 case X86::COND_L: case X86::COND_LE:
13490 case X86::COND_O: case X86::COND_NO: {
13491 // Check if we really need to set the
13492 // Overflow flag. If NoSignedWrap is present
13493 // that is not actually needed.
13494 switch (Op->getOpcode()) {
13499 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13500 if (BinNode->Flags.hasNoSignedWrap())
13510 // See if we can use the EFLAGS value from the operand instead of
13511 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13512 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13513 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13514 // Emit a CMP with 0, which is the TEST pattern.
13515 //if (Op.getValueType() == MVT::i1)
13516 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13517 // DAG.getConstant(0, MVT::i1));
13518 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13519 DAG.getConstant(0, dl, Op.getValueType()));
13521 unsigned Opcode = 0;
13522 unsigned NumOperands = 0;
13524 // Truncate operations may prevent the merge of the SETCC instruction
13525 // and the arithmetic instruction before it. Attempt to truncate the operands
13526 // of the arithmetic instruction and use a reduced bit-width instruction.
13527 bool NeedTruncation = false;
13528 SDValue ArithOp = Op;
13529 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13530 SDValue Arith = Op->getOperand(0);
13531 // Both the trunc and the arithmetic op need to have one user each.
13532 if (Arith->hasOneUse())
13533 switch (Arith.getOpcode()) {
13540 NeedTruncation = true;
13546 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13547 // which may be the result of a CAST. We use the variable 'Op', which is the
13548 // non-casted variable when we check for possible users.
13549 switch (ArithOp.getOpcode()) {
13551 // Due to an isel shortcoming, be conservative if this add is likely to be
13552 // selected as part of a load-modify-store instruction. When the root node
13553 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13554 // uses of other nodes in the match, such as the ADD in this case. This
13555 // leads to the ADD being left around and reselected, with the result being
13556 // two adds in the output. Alas, even if none our users are stores, that
13557 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13558 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13559 // climbing the DAG back to the root, and it doesn't seem to be worth the
13561 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13562 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13563 if (UI->getOpcode() != ISD::CopyToReg &&
13564 UI->getOpcode() != ISD::SETCC &&
13565 UI->getOpcode() != ISD::STORE)
13568 if (ConstantSDNode *C =
13569 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13570 // An add of one will be selected as an INC.
13571 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13572 Opcode = X86ISD::INC;
13577 // An add of negative one (subtract of one) will be selected as a DEC.
13578 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13579 Opcode = X86ISD::DEC;
13585 // Otherwise use a regular EFLAGS-setting add.
13586 Opcode = X86ISD::ADD;
13591 // If we have a constant logical shift that's only used in a comparison
13592 // against zero turn it into an equivalent AND. This allows turning it into
13593 // a TEST instruction later.
13594 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13595 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13596 EVT VT = Op.getValueType();
13597 unsigned BitWidth = VT.getSizeInBits();
13598 unsigned ShAmt = Op->getConstantOperandVal(1);
13599 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13601 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13602 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13603 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13604 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13606 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13607 DAG.getConstant(Mask, dl, VT));
13608 DAG.ReplaceAllUsesWith(Op, New);
13614 // If the primary and result isn't used, don't bother using X86ISD::AND,
13615 // because a TEST instruction will be better.
13616 if (!hasNonFlagsUse(Op))
13622 // Due to the ISEL shortcoming noted above, be conservative if this op is
13623 // likely to be selected as part of a load-modify-store instruction.
13624 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13625 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13626 if (UI->getOpcode() == ISD::STORE)
13629 // Otherwise use a regular EFLAGS-setting instruction.
13630 switch (ArithOp.getOpcode()) {
13631 default: llvm_unreachable("unexpected operator!");
13632 case ISD::SUB: Opcode = X86ISD::SUB; break;
13633 case ISD::XOR: Opcode = X86ISD::XOR; break;
13634 case ISD::AND: Opcode = X86ISD::AND; break;
13636 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13637 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13638 if (EFLAGS.getNode())
13641 Opcode = X86ISD::OR;
13655 return SDValue(Op.getNode(), 1);
13661 // If we found that truncation is beneficial, perform the truncation and
13663 if (NeedTruncation) {
13664 EVT VT = Op.getValueType();
13665 SDValue WideVal = Op->getOperand(0);
13666 EVT WideVT = WideVal.getValueType();
13667 unsigned ConvertedOp = 0;
13668 // Use a target machine opcode to prevent further DAGCombine
13669 // optimizations that may separate the arithmetic operations
13670 // from the setcc node.
13671 switch (WideVal.getOpcode()) {
13673 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13674 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13675 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13676 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13677 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13682 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13683 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13684 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13685 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13691 // Emit a CMP with 0, which is the TEST pattern.
13692 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13693 DAG.getConstant(0, dl, Op.getValueType()));
13695 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13696 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13698 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13699 DAG.ReplaceAllUsesWith(Op, New);
13700 return SDValue(New.getNode(), 1);
13703 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13705 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13706 SDLoc dl, SelectionDAG &DAG) const {
13707 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13708 if (C->getAPIntValue() == 0)
13709 return EmitTest(Op0, X86CC, dl, DAG);
13711 if (Op0.getValueType() == MVT::i1)
13712 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13715 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13716 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13717 // Do the comparison at i32 if it's smaller, besides the Atom case.
13718 // This avoids subregister aliasing issues. Keep the smaller reference
13719 // if we're optimizing for size, however, as that'll allow better folding
13720 // of memory operations.
13721 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13722 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13723 !Subtarget->isAtom()) {
13724 unsigned ExtendOp =
13725 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13726 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13727 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13729 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13730 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13731 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13733 return SDValue(Sub.getNode(), 1);
13735 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13738 /// Convert a comparison if required by the subtarget.
13739 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13740 SelectionDAG &DAG) const {
13741 // If the subtarget does not support the FUCOMI instruction, floating-point
13742 // comparisons have to be converted.
13743 if (Subtarget->hasCMov() ||
13744 Cmp.getOpcode() != X86ISD::CMP ||
13745 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13746 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13749 // The instruction selector will select an FUCOM instruction instead of
13750 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13751 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13752 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13754 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13755 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13756 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13757 DAG.getConstant(8, dl, MVT::i8));
13758 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13759 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13762 /// The minimum architected relative accuracy is 2^-12. We need one
13763 /// Newton-Raphson step to have a good float result (24 bits of precision).
13764 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13765 DAGCombinerInfo &DCI,
13766 unsigned &RefinementSteps,
13767 bool &UseOneConstNR) const {
13768 EVT VT = Op.getValueType();
13769 const char *RecipOp;
13771 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13772 // TODO: Add support for AVX512 (v16f32).
13773 // It is likely not profitable to do this for f64 because a double-precision
13774 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13775 // instructions: convert to single, rsqrtss, convert back to double, refine
13776 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13777 // along with FMA, this could be a throughput win.
13778 if (VT == MVT::f32 && Subtarget->hasSSE1())
13780 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13781 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13782 RecipOp = "vec-sqrtf";
13786 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13787 if (!Recips.isEnabled(RecipOp))
13790 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13791 UseOneConstNR = false;
13792 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13795 /// The minimum architected relative accuracy is 2^-12. We need one
13796 /// Newton-Raphson step to have a good float result (24 bits of precision).
13797 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13798 DAGCombinerInfo &DCI,
13799 unsigned &RefinementSteps) const {
13800 EVT VT = Op.getValueType();
13801 const char *RecipOp;
13803 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13804 // TODO: Add support for AVX512 (v16f32).
13805 // It is likely not profitable to do this for f64 because a double-precision
13806 // reciprocal estimate with refinement on x86 prior to FMA requires
13807 // 15 instructions: convert to single, rcpss, convert back to double, refine
13808 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13809 // along with FMA, this could be a throughput win.
13810 if (VT == MVT::f32 && Subtarget->hasSSE1())
13812 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13813 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13814 RecipOp = "vec-divf";
13818 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13819 if (!Recips.isEnabled(RecipOp))
13822 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13823 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13826 /// If we have at least two divisions that use the same divisor, convert to
13827 /// multplication by a reciprocal. This may need to be adjusted for a given
13828 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13829 /// This is because we still need one division to calculate the reciprocal and
13830 /// then we need two multiplies by that reciprocal as replacements for the
13831 /// original divisions.
13832 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13836 static bool isAllOnes(SDValue V) {
13837 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13838 return C && C->isAllOnesValue();
13841 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13842 /// if it's possible.
13843 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13844 SDLoc dl, SelectionDAG &DAG) const {
13845 SDValue Op0 = And.getOperand(0);
13846 SDValue Op1 = And.getOperand(1);
13847 if (Op0.getOpcode() == ISD::TRUNCATE)
13848 Op0 = Op0.getOperand(0);
13849 if (Op1.getOpcode() == ISD::TRUNCATE)
13850 Op1 = Op1.getOperand(0);
13853 if (Op1.getOpcode() == ISD::SHL)
13854 std::swap(Op0, Op1);
13855 if (Op0.getOpcode() == ISD::SHL) {
13856 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13857 if (And00C->getZExtValue() == 1) {
13858 // If we looked past a truncate, check that it's only truncating away
13860 unsigned BitWidth = Op0.getValueSizeInBits();
13861 unsigned AndBitWidth = And.getValueSizeInBits();
13862 if (BitWidth > AndBitWidth) {
13864 DAG.computeKnownBits(Op0, Zeros, Ones);
13865 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13869 RHS = Op0.getOperand(1);
13871 } else if (Op1.getOpcode() == ISD::Constant) {
13872 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13873 uint64_t AndRHSVal = AndRHS->getZExtValue();
13874 SDValue AndLHS = Op0;
13876 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13877 LHS = AndLHS.getOperand(0);
13878 RHS = AndLHS.getOperand(1);
13881 // Use BT if the immediate can't be encoded in a TEST instruction.
13882 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13884 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13888 if (LHS.getNode()) {
13889 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13890 // instruction. Since the shift amount is in-range-or-undefined, we know
13891 // that doing a bittest on the i32 value is ok. We extend to i32 because
13892 // the encoding for the i16 version is larger than the i32 version.
13893 // Also promote i16 to i32 for performance / code size reason.
13894 if (LHS.getValueType() == MVT::i8 ||
13895 LHS.getValueType() == MVT::i16)
13896 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13898 // If the operand types disagree, extend the shift amount to match. Since
13899 // BT ignores high bits (like shifts) we can use anyextend.
13900 if (LHS.getValueType() != RHS.getValueType())
13901 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13903 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13904 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13905 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13906 DAG.getConstant(Cond, dl, MVT::i8), BT);
13912 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13914 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13919 // SSE Condition code mapping:
13928 switch (SetCCOpcode) {
13929 default: llvm_unreachable("Unexpected SETCC condition");
13931 case ISD::SETEQ: SSECC = 0; break;
13933 case ISD::SETGT: Swap = true; // Fallthrough
13935 case ISD::SETOLT: SSECC = 1; break;
13937 case ISD::SETGE: Swap = true; // Fallthrough
13939 case ISD::SETOLE: SSECC = 2; break;
13940 case ISD::SETUO: SSECC = 3; break;
13942 case ISD::SETNE: SSECC = 4; break;
13943 case ISD::SETULE: Swap = true; // Fallthrough
13944 case ISD::SETUGE: SSECC = 5; break;
13945 case ISD::SETULT: Swap = true; // Fallthrough
13946 case ISD::SETUGT: SSECC = 6; break;
13947 case ISD::SETO: SSECC = 7; break;
13949 case ISD::SETONE: SSECC = 8; break;
13952 std::swap(Op0, Op1);
13957 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13958 // ones, and then concatenate the result back.
13959 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13960 MVT VT = Op.getSimpleValueType();
13962 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13963 "Unsupported value type for operation");
13965 unsigned NumElems = VT.getVectorNumElements();
13967 SDValue CC = Op.getOperand(2);
13969 // Extract the LHS vectors
13970 SDValue LHS = Op.getOperand(0);
13971 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13972 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13974 // Extract the RHS vectors
13975 SDValue RHS = Op.getOperand(1);
13976 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13977 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13979 // Issue the operation on the smaller types and concatenate the result back
13980 MVT EltVT = VT.getVectorElementType();
13981 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13982 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13983 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13984 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13987 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13988 SDValue Op0 = Op.getOperand(0);
13989 SDValue Op1 = Op.getOperand(1);
13990 SDValue CC = Op.getOperand(2);
13991 MVT VT = Op.getSimpleValueType();
13994 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13995 "Unexpected type for boolean compare operation");
13996 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13997 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13998 DAG.getConstant(-1, dl, VT));
13999 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14000 DAG.getConstant(-1, dl, VT));
14001 switch (SetCCOpcode) {
14002 default: llvm_unreachable("Unexpected SETCC condition");
14004 // (x == y) -> ~(x ^ y)
14005 return DAG.getNode(ISD::XOR, dl, VT,
14006 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14007 DAG.getConstant(-1, dl, VT));
14009 // (x != y) -> (x ^ y)
14010 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14013 // (x > y) -> (x & ~y)
14014 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14017 // (x < y) -> (~x & y)
14018 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14021 // (x <= y) -> (~x | y)
14022 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14025 // (x >=y) -> (x | ~y)
14026 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14030 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14031 const X86Subtarget *Subtarget) {
14032 SDValue Op0 = Op.getOperand(0);
14033 SDValue Op1 = Op.getOperand(1);
14034 SDValue CC = Op.getOperand(2);
14035 MVT VT = Op.getSimpleValueType();
14038 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14039 Op.getValueType().getScalarType() == MVT::i1 &&
14040 "Cannot set masked compare for this operation");
14042 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14044 bool Unsigned = false;
14047 switch (SetCCOpcode) {
14048 default: llvm_unreachable("Unexpected SETCC condition");
14049 case ISD::SETNE: SSECC = 4; break;
14050 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14051 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14052 case ISD::SETLT: Swap = true; //fall-through
14053 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14054 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14055 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14056 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14057 case ISD::SETULE: Unsigned = true; //fall-through
14058 case ISD::SETLE: SSECC = 2; break;
14062 std::swap(Op0, Op1);
14064 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14065 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14066 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14067 DAG.getConstant(SSECC, dl, MVT::i8));
14070 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14071 /// operand \p Op1. If non-trivial (for example because it's not constant)
14072 /// return an empty value.
14073 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14075 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14079 MVT VT = Op1.getSimpleValueType();
14080 MVT EVT = VT.getVectorElementType();
14081 unsigned n = VT.getVectorNumElements();
14082 SmallVector<SDValue, 8> ULTOp1;
14084 for (unsigned i = 0; i < n; ++i) {
14085 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14086 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14089 // Avoid underflow.
14090 APInt Val = Elt->getAPIntValue();
14094 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14097 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14100 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14101 SelectionDAG &DAG) {
14102 SDValue Op0 = Op.getOperand(0);
14103 SDValue Op1 = Op.getOperand(1);
14104 SDValue CC = Op.getOperand(2);
14105 MVT VT = Op.getSimpleValueType();
14106 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14107 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14112 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14113 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14116 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14117 unsigned Opc = X86ISD::CMPP;
14118 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14119 assert(VT.getVectorNumElements() <= 16);
14120 Opc = X86ISD::CMPM;
14122 // In the two special cases we can't handle, emit two comparisons.
14125 unsigned CombineOpc;
14126 if (SetCCOpcode == ISD::SETUEQ) {
14127 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14129 assert(SetCCOpcode == ISD::SETONE);
14130 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14133 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14134 DAG.getConstant(CC0, dl, MVT::i8));
14135 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14136 DAG.getConstant(CC1, dl, MVT::i8));
14137 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14139 // Handle all other FP comparisons here.
14140 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14141 DAG.getConstant(SSECC, dl, MVT::i8));
14144 // Break 256-bit integer vector compare into smaller ones.
14145 if (VT.is256BitVector() && !Subtarget->hasInt256())
14146 return Lower256IntVSETCC(Op, DAG);
14148 EVT OpVT = Op1.getValueType();
14149 if (OpVT.getVectorElementType() == MVT::i1)
14150 return LowerBoolVSETCC_AVX512(Op, DAG);
14152 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14153 if (Subtarget->hasAVX512()) {
14154 if (Op1.getValueType().is512BitVector() ||
14155 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14156 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14157 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14159 // In AVX-512 architecture setcc returns mask with i1 elements,
14160 // But there is no compare instruction for i8 and i16 elements in KNL.
14161 // We are not talking about 512-bit operands in this case, these
14162 // types are illegal.
14164 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14165 OpVT.getVectorElementType().getSizeInBits() >= 8))
14166 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14167 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14170 // We are handling one of the integer comparisons here. Since SSE only has
14171 // GT and EQ comparisons for integer, swapping operands and multiple
14172 // operations may be required for some comparisons.
14174 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14175 bool Subus = false;
14177 switch (SetCCOpcode) {
14178 default: llvm_unreachable("Unexpected SETCC condition");
14179 case ISD::SETNE: Invert = true;
14180 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14181 case ISD::SETLT: Swap = true;
14182 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14183 case ISD::SETGE: Swap = true;
14184 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14185 Invert = true; break;
14186 case ISD::SETULT: Swap = true;
14187 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14188 FlipSigns = true; break;
14189 case ISD::SETUGE: Swap = true;
14190 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14191 FlipSigns = true; Invert = true; break;
14194 // Special case: Use min/max operations for SETULE/SETUGE
14195 MVT VET = VT.getVectorElementType();
14197 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14198 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14201 switch (SetCCOpcode) {
14203 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14204 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14207 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14210 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14211 if (!MinMax && hasSubus) {
14212 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14214 // t = psubus Op0, Op1
14215 // pcmpeq t, <0..0>
14216 switch (SetCCOpcode) {
14218 case ISD::SETULT: {
14219 // If the comparison is against a constant we can turn this into a
14220 // setule. With psubus, setule does not require a swap. This is
14221 // beneficial because the constant in the register is no longer
14222 // destructed as the destination so it can be hoisted out of a loop.
14223 // Only do this pre-AVX since vpcmp* is no longer destructive.
14224 if (Subtarget->hasAVX())
14226 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14227 if (ULEOp1.getNode()) {
14229 Subus = true; Invert = false; Swap = false;
14233 // Psubus is better than flip-sign because it requires no inversion.
14234 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14235 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14239 Opc = X86ISD::SUBUS;
14245 std::swap(Op0, Op1);
14247 // Check that the operation in question is available (most are plain SSE2,
14248 // but PCMPGTQ and PCMPEQQ have different requirements).
14249 if (VT == MVT::v2i64) {
14250 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14251 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14253 // First cast everything to the right type.
14254 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14255 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14257 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14258 // bits of the inputs before performing those operations. The lower
14259 // compare is always unsigned.
14262 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14264 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14265 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14266 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14267 Sign, Zero, Sign, Zero);
14269 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14270 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14272 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14273 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14274 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14276 // Create masks for only the low parts/high parts of the 64 bit integers.
14277 static const int MaskHi[] = { 1, 1, 3, 3 };
14278 static const int MaskLo[] = { 0, 0, 2, 2 };
14279 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14280 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14281 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14283 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14284 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14287 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14289 return DAG.getBitcast(VT, Result);
14292 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14293 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14294 // pcmpeqd + pshufd + pand.
14295 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14297 // First cast everything to the right type.
14298 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14299 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14302 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14304 // Make sure the lower and upper halves are both all-ones.
14305 static const int Mask[] = { 1, 0, 3, 2 };
14306 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14307 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14310 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14312 return DAG.getBitcast(VT, Result);
14316 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14317 // bits of the inputs before performing those operations.
14319 EVT EltVT = VT.getVectorElementType();
14320 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14322 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14323 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14326 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14328 // If the logical-not of the result is required, perform that now.
14330 Result = DAG.getNOT(dl, Result, VT);
14333 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14336 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14337 getZeroVector(VT, Subtarget, DAG, dl));
14342 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14344 MVT VT = Op.getSimpleValueType();
14346 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14348 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14349 && "SetCC type must be 8-bit or 1-bit integer");
14350 SDValue Op0 = Op.getOperand(0);
14351 SDValue Op1 = Op.getOperand(1);
14353 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14355 // Optimize to BT if possible.
14356 // Lower (X & (1 << N)) == 0 to BT(X, N).
14357 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14358 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14359 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14360 Op1.getOpcode() == ISD::Constant &&
14361 cast<ConstantSDNode>(Op1)->isNullValue() &&
14362 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14363 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14364 if (NewSetCC.getNode()) {
14366 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14371 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14373 if (Op1.getOpcode() == ISD::Constant &&
14374 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14375 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14376 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14378 // If the input is a setcc, then reuse the input setcc or use a new one with
14379 // the inverted condition.
14380 if (Op0.getOpcode() == X86ISD::SETCC) {
14381 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14382 bool Invert = (CC == ISD::SETNE) ^
14383 cast<ConstantSDNode>(Op1)->isNullValue();
14387 CCode = X86::GetOppositeBranchCondition(CCode);
14388 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14389 DAG.getConstant(CCode, dl, MVT::i8),
14390 Op0.getOperand(1));
14392 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14396 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14397 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14398 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14400 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14401 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14404 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14405 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14406 if (X86CC == X86::COND_INVALID)
14409 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14410 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14411 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14412 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14414 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14418 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14419 static bool isX86LogicalCmp(SDValue Op) {
14420 unsigned Opc = Op.getNode()->getOpcode();
14421 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14422 Opc == X86ISD::SAHF)
14424 if (Op.getResNo() == 1 &&
14425 (Opc == X86ISD::ADD ||
14426 Opc == X86ISD::SUB ||
14427 Opc == X86ISD::ADC ||
14428 Opc == X86ISD::SBB ||
14429 Opc == X86ISD::SMUL ||
14430 Opc == X86ISD::UMUL ||
14431 Opc == X86ISD::INC ||
14432 Opc == X86ISD::DEC ||
14433 Opc == X86ISD::OR ||
14434 Opc == X86ISD::XOR ||
14435 Opc == X86ISD::AND))
14438 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14444 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14445 if (V.getOpcode() != ISD::TRUNCATE)
14448 SDValue VOp0 = V.getOperand(0);
14449 unsigned InBits = VOp0.getValueSizeInBits();
14450 unsigned Bits = V.getValueSizeInBits();
14451 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14454 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14455 bool addTest = true;
14456 SDValue Cond = Op.getOperand(0);
14457 SDValue Op1 = Op.getOperand(1);
14458 SDValue Op2 = Op.getOperand(2);
14460 EVT VT = Op1.getValueType();
14463 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14464 // are available or VBLENDV if AVX is available.
14465 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14466 if (Cond.getOpcode() == ISD::SETCC &&
14467 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14468 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14469 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14470 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14471 int SSECC = translateX86FSETCC(
14472 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14475 if (Subtarget->hasAVX512()) {
14476 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14477 DAG.getConstant(SSECC, DL, MVT::i8));
14478 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14481 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14482 DAG.getConstant(SSECC, DL, MVT::i8));
14484 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14485 // of 3 logic instructions for size savings and potentially speed.
14486 // Unfortunately, there is no scalar form of VBLENDV.
14488 // If either operand is a constant, don't try this. We can expect to
14489 // optimize away at least one of the logic instructions later in that
14490 // case, so that sequence would be faster than a variable blend.
14492 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14493 // uses XMM0 as the selection register. That may need just as many
14494 // instructions as the AND/ANDN/OR sequence due to register moves, so
14497 if (Subtarget->hasAVX() &&
14498 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14500 // Convert to vectors, do a VSELECT, and convert back to scalar.
14501 // All of the conversions should be optimized away.
14503 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14504 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14505 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14506 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14508 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14509 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14511 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14513 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14514 VSel, DAG.getIntPtrConstant(0, DL));
14516 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14517 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14518 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14522 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14524 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14525 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14526 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14527 Op1Scalar = Op1.getOperand(0);
14529 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14530 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14531 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14532 Op2Scalar = Op2.getOperand(0);
14533 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14534 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14535 Op1Scalar.getValueType(),
14536 Cond, Op1Scalar, Op2Scalar);
14537 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14538 return DAG.getBitcast(VT, newSelect);
14539 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14540 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14541 DAG.getIntPtrConstant(0, DL));
14545 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14546 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14547 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14548 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14549 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14550 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14551 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14553 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14556 if (Cond.getOpcode() == ISD::SETCC) {
14557 SDValue NewCond = LowerSETCC(Cond, DAG);
14558 if (NewCond.getNode())
14562 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14563 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14564 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14565 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14566 if (Cond.getOpcode() == X86ISD::SETCC &&
14567 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14568 isZero(Cond.getOperand(1).getOperand(1))) {
14569 SDValue Cmp = Cond.getOperand(1);
14571 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14573 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14574 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14575 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14577 SDValue CmpOp0 = Cmp.getOperand(0);
14578 // Apply further optimizations for special cases
14579 // (select (x != 0), -1, 0) -> neg & sbb
14580 // (select (x == 0), 0, -1) -> neg & sbb
14581 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14582 if (YC->isNullValue() &&
14583 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14584 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14585 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14586 DAG.getConstant(0, DL,
14587 CmpOp0.getValueType()),
14589 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14590 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14591 SDValue(Neg.getNode(), 1));
14595 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14596 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14597 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14599 SDValue Res = // Res = 0 or -1.
14600 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14601 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14603 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14604 Res = DAG.getNOT(DL, Res, Res.getValueType());
14606 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14607 if (!N2C || !N2C->isNullValue())
14608 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14613 // Look past (and (setcc_carry (cmp ...)), 1).
14614 if (Cond.getOpcode() == ISD::AND &&
14615 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14616 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14617 if (C && C->getAPIntValue() == 1)
14618 Cond = Cond.getOperand(0);
14621 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14622 // setting operand in place of the X86ISD::SETCC.
14623 unsigned CondOpcode = Cond.getOpcode();
14624 if (CondOpcode == X86ISD::SETCC ||
14625 CondOpcode == X86ISD::SETCC_CARRY) {
14626 CC = Cond.getOperand(0);
14628 SDValue Cmp = Cond.getOperand(1);
14629 unsigned Opc = Cmp.getOpcode();
14630 MVT VT = Op.getSimpleValueType();
14632 bool IllegalFPCMov = false;
14633 if (VT.isFloatingPoint() && !VT.isVector() &&
14634 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14635 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14637 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14638 Opc == X86ISD::BT) { // FIXME
14642 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14643 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14644 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14645 Cond.getOperand(0).getValueType() != MVT::i8)) {
14646 SDValue LHS = Cond.getOperand(0);
14647 SDValue RHS = Cond.getOperand(1);
14648 unsigned X86Opcode;
14651 switch (CondOpcode) {
14652 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14653 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14654 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14655 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14656 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14657 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14658 default: llvm_unreachable("unexpected overflowing operator");
14660 if (CondOpcode == ISD::UMULO)
14661 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14664 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14666 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14668 if (CondOpcode == ISD::UMULO)
14669 Cond = X86Op.getValue(2);
14671 Cond = X86Op.getValue(1);
14673 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14678 // Look past the truncate if the high bits are known zero.
14679 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14680 Cond = Cond.getOperand(0);
14682 // We know the result of AND is compared against zero. Try to match
14684 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14685 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14686 if (NewSetCC.getNode()) {
14687 CC = NewSetCC.getOperand(0);
14688 Cond = NewSetCC.getOperand(1);
14695 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14696 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14699 // a < b ? -1 : 0 -> RES = ~setcc_carry
14700 // a < b ? 0 : -1 -> RES = setcc_carry
14701 // a >= b ? -1 : 0 -> RES = setcc_carry
14702 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14703 if (Cond.getOpcode() == X86ISD::SUB) {
14704 Cond = ConvertCmpIfNecessary(Cond, DAG);
14705 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14707 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14708 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14709 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14710 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14712 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14713 return DAG.getNOT(DL, Res, Res.getValueType());
14718 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14719 // widen the cmov and push the truncate through. This avoids introducing a new
14720 // branch during isel and doesn't add any extensions.
14721 if (Op.getValueType() == MVT::i8 &&
14722 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14723 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14724 if (T1.getValueType() == T2.getValueType() &&
14725 // Blacklist CopyFromReg to avoid partial register stalls.
14726 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14727 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14728 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14729 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14733 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14734 // condition is true.
14735 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14736 SDValue Ops[] = { Op2, Op1, CC, Cond };
14737 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14740 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14741 const X86Subtarget *Subtarget,
14742 SelectionDAG &DAG) {
14743 MVT VT = Op->getSimpleValueType(0);
14744 SDValue In = Op->getOperand(0);
14745 MVT InVT = In.getSimpleValueType();
14746 MVT VTElt = VT.getVectorElementType();
14747 MVT InVTElt = InVT.getVectorElementType();
14751 if ((InVTElt == MVT::i1) &&
14752 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14753 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14755 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14756 VTElt.getSizeInBits() <= 16)) ||
14758 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14759 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14761 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14762 VTElt.getSizeInBits() >= 32))))
14763 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14765 unsigned int NumElts = VT.getVectorNumElements();
14767 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14770 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14771 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14772 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14773 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14776 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14777 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14779 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14782 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14784 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14785 if (VT.is512BitVector())
14787 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14790 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14791 const X86Subtarget *Subtarget,
14792 SelectionDAG &DAG) {
14793 SDValue In = Op->getOperand(0);
14794 MVT VT = Op->getSimpleValueType(0);
14795 MVT InVT = In.getSimpleValueType();
14796 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14798 MVT InSVT = InVT.getScalarType();
14799 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14801 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14803 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14808 // SSE41 targets can use the pmovsx* instructions directly.
14809 if (Subtarget->hasSSE41())
14810 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14812 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14816 // As SRAI is only available on i16/i32 types, we expand only up to i32
14817 // and handle i64 separately.
14818 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14819 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14820 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14821 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14822 Curr = DAG.getBitcast(CurrVT, Curr);
14825 SDValue SignExt = Curr;
14826 if (CurrVT != InVT) {
14827 unsigned SignExtShift =
14828 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14829 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14830 DAG.getConstant(SignExtShift, dl, MVT::i8));
14836 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14837 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14838 DAG.getConstant(31, dl, MVT::i8));
14839 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14840 return DAG.getBitcast(VT, Ext);
14846 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14847 SelectionDAG &DAG) {
14848 MVT VT = Op->getSimpleValueType(0);
14849 SDValue In = Op->getOperand(0);
14850 MVT InVT = In.getSimpleValueType();
14853 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14854 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14856 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14857 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14858 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14861 if (Subtarget->hasInt256())
14862 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14864 // Optimize vectors in AVX mode
14865 // Sign extend v8i16 to v8i32 and
14868 // Divide input vector into two parts
14869 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14870 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14871 // concat the vectors to original VT
14873 unsigned NumElems = InVT.getVectorNumElements();
14874 SDValue Undef = DAG.getUNDEF(InVT);
14876 SmallVector<int,8> ShufMask1(NumElems, -1);
14877 for (unsigned i = 0; i != NumElems/2; ++i)
14880 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14882 SmallVector<int,8> ShufMask2(NumElems, -1);
14883 for (unsigned i = 0; i != NumElems/2; ++i)
14884 ShufMask2[i] = i + NumElems/2;
14886 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14888 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14889 VT.getVectorNumElements()/2);
14891 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14892 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14894 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14897 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14898 // may emit an illegal shuffle but the expansion is still better than scalar
14899 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14900 // we'll emit a shuffle and a arithmetic shift.
14901 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14902 // TODO: It is possible to support ZExt by zeroing the undef values during
14903 // the shuffle phase or after the shuffle.
14904 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14905 SelectionDAG &DAG) {
14906 MVT RegVT = Op.getSimpleValueType();
14907 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14908 assert(RegVT.isInteger() &&
14909 "We only custom lower integer vector sext loads.");
14911 // Nothing useful we can do without SSE2 shuffles.
14912 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14914 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14916 EVT MemVT = Ld->getMemoryVT();
14917 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14918 unsigned RegSz = RegVT.getSizeInBits();
14920 ISD::LoadExtType Ext = Ld->getExtensionType();
14922 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14923 && "Only anyext and sext are currently implemented.");
14924 assert(MemVT != RegVT && "Cannot extend to the same type");
14925 assert(MemVT.isVector() && "Must load a vector from memory");
14927 unsigned NumElems = RegVT.getVectorNumElements();
14928 unsigned MemSz = MemVT.getSizeInBits();
14929 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14931 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14932 // The only way in which we have a legal 256-bit vector result but not the
14933 // integer 256-bit operations needed to directly lower a sextload is if we
14934 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14935 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14936 // correctly legalized. We do this late to allow the canonical form of
14937 // sextload to persist throughout the rest of the DAG combiner -- it wants
14938 // to fold together any extensions it can, and so will fuse a sign_extend
14939 // of an sextload into a sextload targeting a wider value.
14941 if (MemSz == 128) {
14942 // Just switch this to a normal load.
14943 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14944 "it must be a legal 128-bit vector "
14946 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14947 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14948 Ld->isInvariant(), Ld->getAlignment());
14950 assert(MemSz < 128 &&
14951 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14952 // Do an sext load to a 128-bit vector type. We want to use the same
14953 // number of elements, but elements half as wide. This will end up being
14954 // recursively lowered by this routine, but will succeed as we definitely
14955 // have all the necessary features if we're using AVX1.
14957 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14958 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14960 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14961 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14962 Ld->isNonTemporal(), Ld->isInvariant(),
14963 Ld->getAlignment());
14966 // Replace chain users with the new chain.
14967 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14968 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14970 // Finally, do a normal sign-extend to the desired register.
14971 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14974 // All sizes must be a power of two.
14975 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14976 "Non-power-of-two elements are not custom lowered!");
14978 // Attempt to load the original value using scalar loads.
14979 // Find the largest scalar type that divides the total loaded size.
14980 MVT SclrLoadTy = MVT::i8;
14981 for (MVT Tp : MVT::integer_valuetypes()) {
14982 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14987 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14988 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14990 SclrLoadTy = MVT::f64;
14992 // Calculate the number of scalar loads that we need to perform
14993 // in order to load our vector from memory.
14994 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14996 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14997 "Can only lower sext loads with a single scalar load!");
14999 unsigned loadRegZize = RegSz;
15000 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15003 // Represent our vector as a sequence of elements which are the
15004 // largest scalar that we can load.
15005 EVT LoadUnitVecVT = EVT::getVectorVT(
15006 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15008 // Represent the data using the same element type that is stored in
15009 // memory. In practice, we ''widen'' MemVT.
15011 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15012 loadRegZize / MemVT.getScalarType().getSizeInBits());
15014 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15015 "Invalid vector type");
15017 // We can't shuffle using an illegal type.
15018 assert(TLI.isTypeLegal(WideVecVT) &&
15019 "We only lower types that form legal widened vector types");
15021 SmallVector<SDValue, 8> Chains;
15022 SDValue Ptr = Ld->getBasePtr();
15023 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15024 TLI.getPointerTy(DAG.getDataLayout()));
15025 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15027 for (unsigned i = 0; i < NumLoads; ++i) {
15028 // Perform a single load.
15029 SDValue ScalarLoad =
15030 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15031 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15032 Ld->getAlignment());
15033 Chains.push_back(ScalarLoad.getValue(1));
15034 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15035 // another round of DAGCombining.
15037 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15039 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15040 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15042 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15045 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15047 // Bitcast the loaded value to a vector of the original element type, in
15048 // the size of the target vector type.
15049 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15050 unsigned SizeRatio = RegSz / MemSz;
15052 if (Ext == ISD::SEXTLOAD) {
15053 // If we have SSE4.1, we can directly emit a VSEXT node.
15054 if (Subtarget->hasSSE41()) {
15055 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15056 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15060 // Otherwise we'll shuffle the small elements in the high bits of the
15061 // larger type and perform an arithmetic shift. If the shift is not legal
15062 // it's better to scalarize.
15063 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15064 "We can't implement a sext load without an arithmetic right shift!");
15066 // Redistribute the loaded elements into the different locations.
15067 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15068 for (unsigned i = 0; i != NumElems; ++i)
15069 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15071 SDValue Shuff = DAG.getVectorShuffle(
15072 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15074 Shuff = DAG.getBitcast(RegVT, Shuff);
15076 // Build the arithmetic shift.
15077 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15078 MemVT.getVectorElementType().getSizeInBits();
15080 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
15081 DAG.getConstant(Amt, dl, RegVT));
15083 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15087 // Redistribute the loaded elements into the different locations.
15088 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15089 for (unsigned i = 0; i != NumElems; ++i)
15090 ShuffleVec[i * SizeRatio] = i;
15092 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15093 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15095 // Bitcast to the requested type.
15096 Shuff = DAG.getBitcast(RegVT, Shuff);
15097 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15101 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15102 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15103 // from the AND / OR.
15104 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15105 Opc = Op.getOpcode();
15106 if (Opc != ISD::OR && Opc != ISD::AND)
15108 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15109 Op.getOperand(0).hasOneUse() &&
15110 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15111 Op.getOperand(1).hasOneUse());
15114 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15115 // 1 and that the SETCC node has a single use.
15116 static bool isXor1OfSetCC(SDValue Op) {
15117 if (Op.getOpcode() != ISD::XOR)
15119 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15120 if (N1C && N1C->getAPIntValue() == 1) {
15121 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15122 Op.getOperand(0).hasOneUse();
15127 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15128 bool addTest = true;
15129 SDValue Chain = Op.getOperand(0);
15130 SDValue Cond = Op.getOperand(1);
15131 SDValue Dest = Op.getOperand(2);
15134 bool Inverted = false;
15136 if (Cond.getOpcode() == ISD::SETCC) {
15137 // Check for setcc([su]{add,sub,mul}o == 0).
15138 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15139 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15140 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15141 Cond.getOperand(0).getResNo() == 1 &&
15142 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15143 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15144 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15145 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15146 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15147 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15149 Cond = Cond.getOperand(0);
15151 SDValue NewCond = LowerSETCC(Cond, DAG);
15152 if (NewCond.getNode())
15157 // FIXME: LowerXALUO doesn't handle these!!
15158 else if (Cond.getOpcode() == X86ISD::ADD ||
15159 Cond.getOpcode() == X86ISD::SUB ||
15160 Cond.getOpcode() == X86ISD::SMUL ||
15161 Cond.getOpcode() == X86ISD::UMUL)
15162 Cond = LowerXALUO(Cond, DAG);
15165 // Look pass (and (setcc_carry (cmp ...)), 1).
15166 if (Cond.getOpcode() == ISD::AND &&
15167 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15168 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15169 if (C && C->getAPIntValue() == 1)
15170 Cond = Cond.getOperand(0);
15173 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15174 // setting operand in place of the X86ISD::SETCC.
15175 unsigned CondOpcode = Cond.getOpcode();
15176 if (CondOpcode == X86ISD::SETCC ||
15177 CondOpcode == X86ISD::SETCC_CARRY) {
15178 CC = Cond.getOperand(0);
15180 SDValue Cmp = Cond.getOperand(1);
15181 unsigned Opc = Cmp.getOpcode();
15182 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15183 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15187 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15191 // These can only come from an arithmetic instruction with overflow,
15192 // e.g. SADDO, UADDO.
15193 Cond = Cond.getNode()->getOperand(1);
15199 CondOpcode = Cond.getOpcode();
15200 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15201 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15202 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15203 Cond.getOperand(0).getValueType() != MVT::i8)) {
15204 SDValue LHS = Cond.getOperand(0);
15205 SDValue RHS = Cond.getOperand(1);
15206 unsigned X86Opcode;
15209 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15210 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15212 switch (CondOpcode) {
15213 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15215 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15217 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15220 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15221 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15223 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15225 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15228 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15229 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15230 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15231 default: llvm_unreachable("unexpected overflowing operator");
15234 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15235 if (CondOpcode == ISD::UMULO)
15236 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15239 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15241 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15243 if (CondOpcode == ISD::UMULO)
15244 Cond = X86Op.getValue(2);
15246 Cond = X86Op.getValue(1);
15248 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15252 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15253 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15254 if (CondOpc == ISD::OR) {
15255 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15256 // two branches instead of an explicit OR instruction with a
15258 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15259 isX86LogicalCmp(Cmp)) {
15260 CC = Cond.getOperand(0).getOperand(0);
15261 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15262 Chain, Dest, CC, Cmp);
15263 CC = Cond.getOperand(1).getOperand(0);
15267 } else { // ISD::AND
15268 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15269 // two branches instead of an explicit AND instruction with a
15270 // separate test. However, we only do this if this block doesn't
15271 // have a fall-through edge, because this requires an explicit
15272 // jmp when the condition is false.
15273 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15274 isX86LogicalCmp(Cmp) &&
15275 Op.getNode()->hasOneUse()) {
15276 X86::CondCode CCode =
15277 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15278 CCode = X86::GetOppositeBranchCondition(CCode);
15279 CC = DAG.getConstant(CCode, dl, MVT::i8);
15280 SDNode *User = *Op.getNode()->use_begin();
15281 // Look for an unconditional branch following this conditional branch.
15282 // We need this because we need to reverse the successors in order
15283 // to implement FCMP_OEQ.
15284 if (User->getOpcode() == ISD::BR) {
15285 SDValue FalseBB = User->getOperand(1);
15287 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15288 assert(NewBR == User);
15292 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15293 Chain, Dest, CC, Cmp);
15294 X86::CondCode CCode =
15295 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15296 CCode = X86::GetOppositeBranchCondition(CCode);
15297 CC = DAG.getConstant(CCode, dl, MVT::i8);
15303 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15304 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15305 // It should be transformed during dag combiner except when the condition
15306 // is set by a arithmetics with overflow node.
15307 X86::CondCode CCode =
15308 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15309 CCode = X86::GetOppositeBranchCondition(CCode);
15310 CC = DAG.getConstant(CCode, dl, MVT::i8);
15311 Cond = Cond.getOperand(0).getOperand(1);
15313 } else if (Cond.getOpcode() == ISD::SETCC &&
15314 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15315 // For FCMP_OEQ, we can emit
15316 // two branches instead of an explicit AND instruction with a
15317 // separate test. However, we only do this if this block doesn't
15318 // have a fall-through edge, because this requires an explicit
15319 // jmp when the condition is false.
15320 if (Op.getNode()->hasOneUse()) {
15321 SDNode *User = *Op.getNode()->use_begin();
15322 // Look for an unconditional branch following this conditional branch.
15323 // We need this because we need to reverse the successors in order
15324 // to implement FCMP_OEQ.
15325 if (User->getOpcode() == ISD::BR) {
15326 SDValue FalseBB = User->getOperand(1);
15328 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15329 assert(NewBR == User);
15333 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15334 Cond.getOperand(0), Cond.getOperand(1));
15335 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15336 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15337 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15338 Chain, Dest, CC, Cmp);
15339 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15344 } else if (Cond.getOpcode() == ISD::SETCC &&
15345 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15346 // For FCMP_UNE, we can emit
15347 // two branches instead of an explicit AND instruction with a
15348 // separate test. However, we only do this if this block doesn't
15349 // have a fall-through edge, because this requires an explicit
15350 // jmp when the condition is false.
15351 if (Op.getNode()->hasOneUse()) {
15352 SDNode *User = *Op.getNode()->use_begin();
15353 // Look for an unconditional branch following this conditional branch.
15354 // We need this because we need to reverse the successors in order
15355 // to implement FCMP_UNE.
15356 if (User->getOpcode() == ISD::BR) {
15357 SDValue FalseBB = User->getOperand(1);
15359 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15360 assert(NewBR == User);
15363 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15364 Cond.getOperand(0), Cond.getOperand(1));
15365 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15366 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15367 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15368 Chain, Dest, CC, Cmp);
15369 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15379 // Look pass the truncate if the high bits are known zero.
15380 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15381 Cond = Cond.getOperand(0);
15383 // We know the result of AND is compared against zero. Try to match
15385 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15386 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15387 if (NewSetCC.getNode()) {
15388 CC = NewSetCC.getOperand(0);
15389 Cond = NewSetCC.getOperand(1);
15396 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15397 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15398 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15400 Cond = ConvertCmpIfNecessary(Cond, DAG);
15401 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15402 Chain, Dest, CC, Cond);
15405 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15406 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15407 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15408 // that the guard pages used by the OS virtual memory manager are allocated in
15409 // correct sequence.
15411 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15412 SelectionDAG &DAG) const {
15413 MachineFunction &MF = DAG.getMachineFunction();
15414 bool SplitStack = MF.shouldSplitStack();
15415 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15420 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15421 SDNode* Node = Op.getNode();
15423 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15424 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15425 " not tell us which reg is the stack pointer!");
15426 EVT VT = Node->getValueType(0);
15427 SDValue Tmp1 = SDValue(Node, 0);
15428 SDValue Tmp2 = SDValue(Node, 1);
15429 SDValue Tmp3 = Node->getOperand(2);
15430 SDValue Chain = Tmp1.getOperand(0);
15432 // Chain the dynamic stack allocation so that it doesn't modify the stack
15433 // pointer when other instructions are using the stack.
15434 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15437 SDValue Size = Tmp2.getOperand(1);
15438 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15439 Chain = SP.getValue(1);
15440 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15441 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15442 unsigned StackAlign = TFI.getStackAlignment();
15443 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15444 if (Align > StackAlign)
15445 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15446 DAG.getConstant(-(uint64_t)Align, dl, VT));
15447 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15449 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15450 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15453 SDValue Ops[2] = { Tmp1, Tmp2 };
15454 return DAG.getMergeValues(Ops, dl);
15458 SDValue Chain = Op.getOperand(0);
15459 SDValue Size = Op.getOperand(1);
15460 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15461 EVT VT = Op.getNode()->getValueType(0);
15463 bool Is64Bit = Subtarget->is64Bit();
15464 MVT SPTy = getPointerTy(DAG.getDataLayout());
15467 MachineRegisterInfo &MRI = MF.getRegInfo();
15470 // The 64 bit implementation of segmented stacks needs to clobber both r10
15471 // r11. This makes it impossible to use it along with nested parameters.
15472 const Function *F = MF.getFunction();
15474 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15476 if (I->hasNestAttr())
15477 report_fatal_error("Cannot use segmented stacks with functions that "
15478 "have nested arguments.");
15481 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15482 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15483 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15484 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15485 DAG.getRegister(Vreg, SPTy));
15486 SDValue Ops1[2] = { Value, Chain };
15487 return DAG.getMergeValues(Ops1, dl);
15490 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15492 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15493 Flag = Chain.getValue(1);
15494 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15496 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15498 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15499 unsigned SPReg = RegInfo->getStackRegister();
15500 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15501 Chain = SP.getValue(1);
15504 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15505 DAG.getConstant(-(uint64_t)Align, dl, VT));
15506 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15509 SDValue Ops1[2] = { SP, Chain };
15510 return DAG.getMergeValues(Ops1, dl);
15514 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15515 MachineFunction &MF = DAG.getMachineFunction();
15516 auto PtrVT = getPointerTy(MF.getDataLayout());
15517 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15519 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15522 if (!Subtarget->is64Bit() ||
15523 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15524 // vastart just stores the address of the VarArgsFrameIndex slot into the
15525 // memory location argument.
15526 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15527 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15528 MachinePointerInfo(SV), false, false, 0);
15532 // gp_offset (0 - 6 * 8)
15533 // fp_offset (48 - 48 + 8 * 16)
15534 // overflow_arg_area (point to parameters coming in memory).
15536 SmallVector<SDValue, 8> MemOps;
15537 SDValue FIN = Op.getOperand(1);
15539 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15540 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15542 FIN, MachinePointerInfo(SV), false, false, 0);
15543 MemOps.push_back(Store);
15546 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15547 Store = DAG.getStore(Op.getOperand(0), DL,
15548 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15550 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15551 MemOps.push_back(Store);
15553 // Store ptr to overflow_arg_area
15554 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15555 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15556 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15557 MachinePointerInfo(SV, 8),
15559 MemOps.push_back(Store);
15561 // Store ptr to reg_save_area.
15562 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15563 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15564 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15565 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15566 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15567 MemOps.push_back(Store);
15568 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15571 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15572 assert(Subtarget->is64Bit() &&
15573 "LowerVAARG only handles 64-bit va_arg!");
15574 assert(Op.getNode()->getNumOperands() == 4);
15576 MachineFunction &MF = DAG.getMachineFunction();
15577 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15578 // The Win64 ABI uses char* instead of a structure.
15579 return DAG.expandVAArg(Op.getNode());
15581 SDValue Chain = Op.getOperand(0);
15582 SDValue SrcPtr = Op.getOperand(1);
15583 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15584 unsigned Align = Op.getConstantOperandVal(3);
15587 EVT ArgVT = Op.getNode()->getValueType(0);
15588 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15589 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15592 // Decide which area this value should be read from.
15593 // TODO: Implement the AMD64 ABI in its entirety. This simple
15594 // selection mechanism works only for the basic types.
15595 if (ArgVT == MVT::f80) {
15596 llvm_unreachable("va_arg for f80 not yet implemented");
15597 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15598 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15599 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15600 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15602 llvm_unreachable("Unhandled argument type in LowerVAARG");
15605 if (ArgMode == 2) {
15606 // Sanity Check: Make sure using fp_offset makes sense.
15607 assert(!Subtarget->useSoftFloat() &&
15608 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15609 Subtarget->hasSSE1());
15612 // Insert VAARG_64 node into the DAG
15613 // VAARG_64 returns two values: Variable Argument Address, Chain
15614 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15615 DAG.getConstant(ArgMode, dl, MVT::i8),
15616 DAG.getConstant(Align, dl, MVT::i32)};
15617 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15618 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15619 VTs, InstOps, MVT::i64,
15620 MachinePointerInfo(SV),
15622 /*Volatile=*/false,
15624 /*WriteMem=*/true);
15625 Chain = VAARG.getValue(1);
15627 // Load the next argument and return it
15628 return DAG.getLoad(ArgVT, dl,
15631 MachinePointerInfo(),
15632 false, false, false, 0);
15635 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15636 SelectionDAG &DAG) {
15637 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15638 // where a va_list is still an i8*.
15639 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15640 if (Subtarget->isCallingConvWin64(
15641 DAG.getMachineFunction().getFunction()->getCallingConv()))
15642 // Probably a Win64 va_copy.
15643 return DAG.expandVACopy(Op.getNode());
15645 SDValue Chain = Op.getOperand(0);
15646 SDValue DstPtr = Op.getOperand(1);
15647 SDValue SrcPtr = Op.getOperand(2);
15648 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15649 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15652 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15653 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15655 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15658 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15659 // amount is a constant. Takes immediate version of shift as input.
15660 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15661 SDValue SrcOp, uint64_t ShiftAmt,
15662 SelectionDAG &DAG) {
15663 MVT ElementType = VT.getVectorElementType();
15665 // Fold this packed shift into its first operand if ShiftAmt is 0.
15669 // Check for ShiftAmt >= element width
15670 if (ShiftAmt >= ElementType.getSizeInBits()) {
15671 if (Opc == X86ISD::VSRAI)
15672 ShiftAmt = ElementType.getSizeInBits() - 1;
15674 return DAG.getConstant(0, dl, VT);
15677 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15678 && "Unknown target vector shift-by-constant node");
15680 // Fold this packed vector shift into a build vector if SrcOp is a
15681 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15682 if (VT == SrcOp.getSimpleValueType() &&
15683 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15684 SmallVector<SDValue, 8> Elts;
15685 unsigned NumElts = SrcOp->getNumOperands();
15686 ConstantSDNode *ND;
15689 default: llvm_unreachable(nullptr);
15690 case X86ISD::VSHLI:
15691 for (unsigned i=0; i!=NumElts; ++i) {
15692 SDValue CurrentOp = SrcOp->getOperand(i);
15693 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15694 Elts.push_back(CurrentOp);
15697 ND = cast<ConstantSDNode>(CurrentOp);
15698 const APInt &C = ND->getAPIntValue();
15699 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15702 case X86ISD::VSRLI:
15703 for (unsigned i=0; i!=NumElts; ++i) {
15704 SDValue CurrentOp = SrcOp->getOperand(i);
15705 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15706 Elts.push_back(CurrentOp);
15709 ND = cast<ConstantSDNode>(CurrentOp);
15710 const APInt &C = ND->getAPIntValue();
15711 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15714 case X86ISD::VSRAI:
15715 for (unsigned i=0; i!=NumElts; ++i) {
15716 SDValue CurrentOp = SrcOp->getOperand(i);
15717 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15718 Elts.push_back(CurrentOp);
15721 ND = cast<ConstantSDNode>(CurrentOp);
15722 const APInt &C = ND->getAPIntValue();
15723 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15728 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15731 return DAG.getNode(Opc, dl, VT, SrcOp,
15732 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15735 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15736 // may or may not be a constant. Takes immediate version of shift as input.
15737 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15738 SDValue SrcOp, SDValue ShAmt,
15739 SelectionDAG &DAG) {
15740 MVT SVT = ShAmt.getSimpleValueType();
15741 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15743 // Catch shift-by-constant.
15744 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15745 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15746 CShAmt->getZExtValue(), DAG);
15748 // Change opcode to non-immediate version
15750 default: llvm_unreachable("Unknown target vector shift node");
15751 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15752 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15753 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15756 const X86Subtarget &Subtarget =
15757 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15758 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15759 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15760 // Let the shuffle legalizer expand this shift amount node.
15761 SDValue Op0 = ShAmt.getOperand(0);
15762 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15763 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15765 // Need to build a vector containing shift amount.
15766 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15767 SmallVector<SDValue, 4> ShOps;
15768 ShOps.push_back(ShAmt);
15769 if (SVT == MVT::i32) {
15770 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15771 ShOps.push_back(DAG.getUNDEF(SVT));
15773 ShOps.push_back(DAG.getUNDEF(SVT));
15775 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15776 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15779 // The return type has to be a 128-bit type with the same element
15780 // type as the input type.
15781 MVT EltVT = VT.getVectorElementType();
15782 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15784 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15785 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15788 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15789 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15790 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15791 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15792 SDValue PreservedSrc,
15793 const X86Subtarget *Subtarget,
15794 SelectionDAG &DAG) {
15795 EVT VT = Op.getValueType();
15796 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15797 MVT::i1, VT.getVectorNumElements());
15798 SDValue VMask = SDValue();
15799 unsigned OpcodeSelect = ISD::VSELECT;
15802 assert(MaskVT.isSimple() && "invalid mask type");
15804 if (isAllOnes(Mask))
15807 if (MaskVT.bitsGT(Mask.getValueType())) {
15808 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15809 MaskVT.getSizeInBits());
15810 VMask = DAG.getBitcast(MaskVT,
15811 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15813 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15814 Mask.getValueType().getSizeInBits());
15815 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15816 // are extracted by EXTRACT_SUBVECTOR.
15817 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15818 DAG.getBitcast(BitcastVT, Mask),
15819 DAG.getIntPtrConstant(0, dl));
15822 switch (Op.getOpcode()) {
15824 case X86ISD::PCMPEQM:
15825 case X86ISD::PCMPGTM:
15827 case X86ISD::CMPMU:
15828 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15829 case X86ISD::VFPCLASS:
15830 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15831 case X86ISD::VTRUNC:
15832 case X86ISD::VTRUNCS:
15833 case X86ISD::VTRUNCUS:
15834 // We can't use ISD::VSELECT here because it is not always "Legal"
15835 // for the destination type. For example vpmovqb require only AVX512
15836 // and vselect that can operate on byte element type require BWI
15837 OpcodeSelect = X86ISD::SELECT;
15840 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15841 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15842 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15845 /// \brief Creates an SDNode for a predicated scalar operation.
15846 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15847 /// The mask is coming as MVT::i8 and it should be truncated
15848 /// to MVT::i1 while lowering masking intrinsics.
15849 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15850 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15851 /// for a scalar instruction.
15852 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15853 SDValue PreservedSrc,
15854 const X86Subtarget *Subtarget,
15855 SelectionDAG &DAG) {
15856 if (isAllOnes(Mask))
15859 EVT VT = Op.getValueType();
15861 // The mask should be of type MVT::i1
15862 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15864 if (Op.getOpcode() == X86ISD::FSETCC)
15865 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
15867 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15868 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15869 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15872 static int getSEHRegistrationNodeSize(const Function *Fn) {
15873 if (!Fn->hasPersonalityFn())
15874 report_fatal_error(
15875 "querying registration node size for function without personality");
15876 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15877 // WinEHStatePass for the full struct definition.
15878 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15879 case EHPersonality::MSVC_X86SEH: return 24;
15880 case EHPersonality::MSVC_CXX: return 16;
15883 report_fatal_error("can only recover FP for MSVC EH personality functions");
15886 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15887 /// function or when returning to a parent frame after catching an exception, we
15888 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15889 /// Here's the math:
15890 /// RegNodeBase = EntryEBP - RegNodeSize
15891 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15892 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15893 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15894 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15895 SDValue EntryEBP) {
15896 MachineFunction &MF = DAG.getMachineFunction();
15899 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15900 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
15902 // It's possible that the parent function no longer has a personality function
15903 // if the exceptional code was optimized away, in which case we just return
15904 // the incoming EBP.
15905 if (!Fn->hasPersonalityFn())
15908 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
15910 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15912 MCSymbol *OffsetSym =
15913 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15914 GlobalValue::getRealLinkageName(Fn->getName()));
15915 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15916 SDValue RegNodeFrameOffset =
15917 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15919 // RegNodeBase = EntryEBP - RegNodeSize
15920 // ParentFP = RegNodeBase - RegNodeFrameOffset
15921 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15922 DAG.getConstant(RegNodeSize, dl, PtrVT));
15923 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15926 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15927 SelectionDAG &DAG) {
15929 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15930 EVT VT = Op.getValueType();
15931 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15933 switch(IntrData->Type) {
15934 case INTR_TYPE_1OP:
15935 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15936 case INTR_TYPE_2OP:
15937 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15939 case INTR_TYPE_2OP_IMM8:
15940 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15941 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
15942 case INTR_TYPE_3OP:
15943 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15944 Op.getOperand(2), Op.getOperand(3));
15945 case INTR_TYPE_4OP:
15946 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15947 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15948 case INTR_TYPE_1OP_MASK_RM: {
15949 SDValue Src = Op.getOperand(1);
15950 SDValue PassThru = Op.getOperand(2);
15951 SDValue Mask = Op.getOperand(3);
15952 SDValue RoundingMode;
15953 // We allways add rounding mode to the Node.
15954 // If the rounding mode is not specified, we add the
15955 // "current direction" mode.
15956 if (Op.getNumOperands() == 4)
15958 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15960 RoundingMode = Op.getOperand(4);
15961 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15962 if (IntrWithRoundingModeOpcode != 0)
15963 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
15964 X86::STATIC_ROUNDING::CUR_DIRECTION)
15965 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15966 dl, Op.getValueType(), Src, RoundingMode),
15967 Mask, PassThru, Subtarget, DAG);
15968 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15970 Mask, PassThru, Subtarget, DAG);
15972 case INTR_TYPE_1OP_MASK: {
15973 SDValue Src = Op.getOperand(1);
15974 SDValue PassThru = Op.getOperand(2);
15975 SDValue Mask = Op.getOperand(3);
15976 // We add rounding mode to the Node when
15977 // - RM Opcode is specified and
15978 // - RM is not "current direction".
15979 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15980 if (IntrWithRoundingModeOpcode != 0) {
15981 SDValue Rnd = Op.getOperand(4);
15982 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15983 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15984 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15985 dl, Op.getValueType(),
15987 Mask, PassThru, Subtarget, DAG);
15990 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15991 Mask, PassThru, Subtarget, DAG);
15993 case INTR_TYPE_SCALAR_MASK: {
15994 SDValue Src1 = Op.getOperand(1);
15995 SDValue Src2 = Op.getOperand(2);
15996 SDValue passThru = Op.getOperand(3);
15997 SDValue Mask = Op.getOperand(4);
15998 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
15999 Mask, passThru, Subtarget, DAG);
16001 case INTR_TYPE_SCALAR_MASK_RM: {
16002 SDValue Src1 = Op.getOperand(1);
16003 SDValue Src2 = Op.getOperand(2);
16004 SDValue Src0 = Op.getOperand(3);
16005 SDValue Mask = Op.getOperand(4);
16006 // There are 2 kinds of intrinsics in this group:
16007 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16008 // (2) With rounding mode and sae - 7 operands.
16009 if (Op.getNumOperands() == 6) {
16010 SDValue Sae = Op.getOperand(5);
16011 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16012 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16014 Mask, Src0, Subtarget, DAG);
16016 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16017 SDValue RoundingMode = Op.getOperand(5);
16018 SDValue Sae = Op.getOperand(6);
16019 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16020 RoundingMode, Sae),
16021 Mask, Src0, Subtarget, DAG);
16023 case INTR_TYPE_2OP_MASK: {
16024 SDValue Src1 = Op.getOperand(1);
16025 SDValue Src2 = Op.getOperand(2);
16026 SDValue PassThru = Op.getOperand(3);
16027 SDValue Mask = Op.getOperand(4);
16028 // We specify 2 possible opcodes for intrinsics with rounding modes.
16029 // First, we check if the intrinsic may have non-default rounding mode,
16030 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16031 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16032 if (IntrWithRoundingModeOpcode != 0) {
16033 SDValue Rnd = Op.getOperand(5);
16034 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16035 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16036 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16037 dl, Op.getValueType(),
16039 Mask, PassThru, Subtarget, DAG);
16042 // TODO: Intrinsics should have fast-math-flags to propagate.
16043 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16044 Mask, PassThru, Subtarget, DAG);
16046 case INTR_TYPE_2OP_MASK_RM: {
16047 SDValue Src1 = Op.getOperand(1);
16048 SDValue Src2 = Op.getOperand(2);
16049 SDValue PassThru = Op.getOperand(3);
16050 SDValue Mask = Op.getOperand(4);
16051 // We specify 2 possible modes for intrinsics, with/without rounding
16053 // First, we check if the intrinsic have rounding mode (6 operands),
16054 // if not, we set rounding mode to "current".
16056 if (Op.getNumOperands() == 6)
16057 Rnd = Op.getOperand(5);
16059 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16060 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16062 Mask, PassThru, Subtarget, DAG);
16064 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16065 SDValue Src1 = Op.getOperand(1);
16066 SDValue Src2 = Op.getOperand(2);
16067 SDValue Src3 = Op.getOperand(3);
16068 SDValue PassThru = Op.getOperand(4);
16069 SDValue Mask = Op.getOperand(5);
16070 SDValue Sae = Op.getOperand(6);
16072 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16074 Mask, PassThru, Subtarget, DAG);
16076 case INTR_TYPE_3OP_MASK_RM: {
16077 SDValue Src1 = Op.getOperand(1);
16078 SDValue Src2 = Op.getOperand(2);
16079 SDValue Imm = Op.getOperand(3);
16080 SDValue PassThru = Op.getOperand(4);
16081 SDValue Mask = Op.getOperand(5);
16082 // We specify 2 possible modes for intrinsics, with/without rounding
16084 // First, we check if the intrinsic have rounding mode (7 operands),
16085 // if not, we set rounding mode to "current".
16087 if (Op.getNumOperands() == 7)
16088 Rnd = Op.getOperand(6);
16090 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16091 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16092 Src1, Src2, Imm, Rnd),
16093 Mask, PassThru, Subtarget, DAG);
16095 case INTR_TYPE_3OP_IMM8_MASK:
16096 case INTR_TYPE_3OP_MASK:
16097 case INSERT_SUBVEC: {
16098 SDValue Src1 = Op.getOperand(1);
16099 SDValue Src2 = Op.getOperand(2);
16100 SDValue Src3 = Op.getOperand(3);
16101 SDValue PassThru = Op.getOperand(4);
16102 SDValue Mask = Op.getOperand(5);
16104 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16105 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16106 else if (IntrData->Type == INSERT_SUBVEC) {
16107 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16108 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16109 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16110 Imm *= Src2.getValueType().getVectorNumElements();
16111 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16114 // We specify 2 possible opcodes for intrinsics with rounding modes.
16115 // First, we check if the intrinsic may have non-default rounding mode,
16116 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16117 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16118 if (IntrWithRoundingModeOpcode != 0) {
16119 SDValue Rnd = Op.getOperand(6);
16120 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16121 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16122 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16123 dl, Op.getValueType(),
16124 Src1, Src2, Src3, Rnd),
16125 Mask, PassThru, Subtarget, DAG);
16128 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16130 Mask, PassThru, Subtarget, DAG);
16132 case VPERM_3OP_MASKZ:
16133 case VPERM_3OP_MASK:
16136 case FMA_OP_MASK: {
16137 SDValue Src1 = Op.getOperand(1);
16138 SDValue Src2 = Op.getOperand(2);
16139 SDValue Src3 = Op.getOperand(3);
16140 SDValue Mask = Op.getOperand(4);
16141 EVT VT = Op.getValueType();
16142 SDValue PassThru = SDValue();
16144 // set PassThru element
16145 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16146 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16147 else if (IntrData->Type == FMA_OP_MASK3)
16152 // We specify 2 possible opcodes for intrinsics with rounding modes.
16153 // First, we check if the intrinsic may have non-default rounding mode,
16154 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16155 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16156 if (IntrWithRoundingModeOpcode != 0) {
16157 SDValue Rnd = Op.getOperand(5);
16158 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16159 X86::STATIC_ROUNDING::CUR_DIRECTION)
16160 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16161 dl, Op.getValueType(),
16162 Src1, Src2, Src3, Rnd),
16163 Mask, PassThru, Subtarget, DAG);
16165 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16166 dl, Op.getValueType(),
16168 Mask, PassThru, Subtarget, DAG);
16171 // FPclass intrinsics with mask
16172 SDValue Src1 = Op.getOperand(1);
16173 EVT VT = Src1.getValueType();
16174 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16175 VT.getVectorNumElements());
16176 SDValue Imm = Op.getOperand(2);
16177 SDValue Mask = Op.getOperand(3);
16178 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16179 Mask.getValueType().getSizeInBits());
16180 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16181 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16182 DAG.getTargetConstant(0, dl, MaskVT),
16184 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16185 DAG.getUNDEF(BitcastVT), FPclassMask,
16186 DAG.getIntPtrConstant(0, dl));
16187 return DAG.getBitcast(Op.getValueType(), Res);
16190 case CMP_MASK_CC: {
16191 // Comparison intrinsics with masks.
16192 // Example of transformation:
16193 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16194 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16196 // (v8i1 (insert_subvector undef,
16197 // (v2i1 (and (PCMPEQM %a, %b),
16198 // (extract_subvector
16199 // (v8i1 (bitcast %mask)), 0))), 0))))
16200 EVT VT = Op.getOperand(1).getValueType();
16201 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16202 VT.getVectorNumElements());
16203 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16204 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16205 Mask.getValueType().getSizeInBits());
16207 if (IntrData->Type == CMP_MASK_CC) {
16208 SDValue CC = Op.getOperand(3);
16209 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16210 // We specify 2 possible opcodes for intrinsics with rounding modes.
16211 // First, we check if the intrinsic may have non-default rounding mode,
16212 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16213 if (IntrData->Opc1 != 0) {
16214 SDValue Rnd = Op.getOperand(5);
16215 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16216 X86::STATIC_ROUNDING::CUR_DIRECTION)
16217 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16218 Op.getOperand(2), CC, Rnd);
16220 //default rounding mode
16222 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16223 Op.getOperand(2), CC);
16226 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16227 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16230 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16231 DAG.getTargetConstant(0, dl,
16234 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16235 DAG.getUNDEF(BitcastVT), CmpMask,
16236 DAG.getIntPtrConstant(0, dl));
16237 return DAG.getBitcast(Op.getValueType(), Res);
16239 case CMP_MASK_SCALAR_CC: {
16240 SDValue Src1 = Op.getOperand(1);
16241 SDValue Src2 = Op.getOperand(2);
16242 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16243 SDValue Mask = Op.getOperand(4);
16246 if (IntrData->Opc1 != 0) {
16247 SDValue Rnd = Op.getOperand(5);
16248 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16249 X86::STATIC_ROUNDING::CUR_DIRECTION)
16250 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16252 //default rounding mode
16254 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16256 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16257 DAG.getTargetConstant(0, dl,
16261 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16262 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16263 DAG.getValueType(MVT::i1));
16265 case COMI: { // Comparison intrinsics
16266 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16267 SDValue LHS = Op.getOperand(1);
16268 SDValue RHS = Op.getOperand(2);
16269 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16270 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16271 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16272 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16273 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16274 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16277 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16278 Op.getOperand(1), Op.getOperand(2), DAG);
16280 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16281 Op.getSimpleValueType(),
16283 Op.getOperand(2), DAG),
16284 Op.getOperand(4), Op.getOperand(3), Subtarget,
16286 case COMPRESS_EXPAND_IN_REG: {
16287 SDValue Mask = Op.getOperand(3);
16288 SDValue DataToCompress = Op.getOperand(1);
16289 SDValue PassThru = Op.getOperand(2);
16290 if (isAllOnes(Mask)) // return data as is
16291 return Op.getOperand(1);
16293 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16295 Mask, PassThru, Subtarget, DAG);
16298 SDValue Mask = Op.getOperand(3);
16299 EVT VT = Op.getValueType();
16300 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16301 VT.getVectorNumElements());
16302 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16303 Mask.getValueType().getSizeInBits());
16305 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16306 DAG.getBitcast(BitcastVT, Mask),
16307 DAG.getIntPtrConstant(0, dl));
16308 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16317 default: return SDValue(); // Don't custom lower most intrinsics.
16319 case Intrinsic::x86_avx2_permd:
16320 case Intrinsic::x86_avx2_permps:
16321 // Operands intentionally swapped. Mask is last operand to intrinsic,
16322 // but second operand for node/instruction.
16323 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16324 Op.getOperand(2), Op.getOperand(1));
16326 // ptest and testp intrinsics. The intrinsic these come from are designed to
16327 // return an integer value, not just an instruction so lower it to the ptest
16328 // or testp pattern and a setcc for the result.
16329 case Intrinsic::x86_sse41_ptestz:
16330 case Intrinsic::x86_sse41_ptestc:
16331 case Intrinsic::x86_sse41_ptestnzc:
16332 case Intrinsic::x86_avx_ptestz_256:
16333 case Intrinsic::x86_avx_ptestc_256:
16334 case Intrinsic::x86_avx_ptestnzc_256:
16335 case Intrinsic::x86_avx_vtestz_ps:
16336 case Intrinsic::x86_avx_vtestc_ps:
16337 case Intrinsic::x86_avx_vtestnzc_ps:
16338 case Intrinsic::x86_avx_vtestz_pd:
16339 case Intrinsic::x86_avx_vtestc_pd:
16340 case Intrinsic::x86_avx_vtestnzc_pd:
16341 case Intrinsic::x86_avx_vtestz_ps_256:
16342 case Intrinsic::x86_avx_vtestc_ps_256:
16343 case Intrinsic::x86_avx_vtestnzc_ps_256:
16344 case Intrinsic::x86_avx_vtestz_pd_256:
16345 case Intrinsic::x86_avx_vtestc_pd_256:
16346 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16347 bool IsTestPacked = false;
16350 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16351 case Intrinsic::x86_avx_vtestz_ps:
16352 case Intrinsic::x86_avx_vtestz_pd:
16353 case Intrinsic::x86_avx_vtestz_ps_256:
16354 case Intrinsic::x86_avx_vtestz_pd_256:
16355 IsTestPacked = true; // Fallthrough
16356 case Intrinsic::x86_sse41_ptestz:
16357 case Intrinsic::x86_avx_ptestz_256:
16359 X86CC = X86::COND_E;
16361 case Intrinsic::x86_avx_vtestc_ps:
16362 case Intrinsic::x86_avx_vtestc_pd:
16363 case Intrinsic::x86_avx_vtestc_ps_256:
16364 case Intrinsic::x86_avx_vtestc_pd_256:
16365 IsTestPacked = true; // Fallthrough
16366 case Intrinsic::x86_sse41_ptestc:
16367 case Intrinsic::x86_avx_ptestc_256:
16369 X86CC = X86::COND_B;
16371 case Intrinsic::x86_avx_vtestnzc_ps:
16372 case Intrinsic::x86_avx_vtestnzc_pd:
16373 case Intrinsic::x86_avx_vtestnzc_ps_256:
16374 case Intrinsic::x86_avx_vtestnzc_pd_256:
16375 IsTestPacked = true; // Fallthrough
16376 case Intrinsic::x86_sse41_ptestnzc:
16377 case Intrinsic::x86_avx_ptestnzc_256:
16379 X86CC = X86::COND_A;
16383 SDValue LHS = Op.getOperand(1);
16384 SDValue RHS = Op.getOperand(2);
16385 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16386 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16387 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16388 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16389 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16391 case Intrinsic::x86_avx512_kortestz_w:
16392 case Intrinsic::x86_avx512_kortestc_w: {
16393 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16394 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16395 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16396 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16397 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16398 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16399 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16402 case Intrinsic::x86_sse42_pcmpistria128:
16403 case Intrinsic::x86_sse42_pcmpestria128:
16404 case Intrinsic::x86_sse42_pcmpistric128:
16405 case Intrinsic::x86_sse42_pcmpestric128:
16406 case Intrinsic::x86_sse42_pcmpistrio128:
16407 case Intrinsic::x86_sse42_pcmpestrio128:
16408 case Intrinsic::x86_sse42_pcmpistris128:
16409 case Intrinsic::x86_sse42_pcmpestris128:
16410 case Intrinsic::x86_sse42_pcmpistriz128:
16411 case Intrinsic::x86_sse42_pcmpestriz128: {
16415 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16416 case Intrinsic::x86_sse42_pcmpistria128:
16417 Opcode = X86ISD::PCMPISTRI;
16418 X86CC = X86::COND_A;
16420 case Intrinsic::x86_sse42_pcmpestria128:
16421 Opcode = X86ISD::PCMPESTRI;
16422 X86CC = X86::COND_A;
16424 case Intrinsic::x86_sse42_pcmpistric128:
16425 Opcode = X86ISD::PCMPISTRI;
16426 X86CC = X86::COND_B;
16428 case Intrinsic::x86_sse42_pcmpestric128:
16429 Opcode = X86ISD::PCMPESTRI;
16430 X86CC = X86::COND_B;
16432 case Intrinsic::x86_sse42_pcmpistrio128:
16433 Opcode = X86ISD::PCMPISTRI;
16434 X86CC = X86::COND_O;
16436 case Intrinsic::x86_sse42_pcmpestrio128:
16437 Opcode = X86ISD::PCMPESTRI;
16438 X86CC = X86::COND_O;
16440 case Intrinsic::x86_sse42_pcmpistris128:
16441 Opcode = X86ISD::PCMPISTRI;
16442 X86CC = X86::COND_S;
16444 case Intrinsic::x86_sse42_pcmpestris128:
16445 Opcode = X86ISD::PCMPESTRI;
16446 X86CC = X86::COND_S;
16448 case Intrinsic::x86_sse42_pcmpistriz128:
16449 Opcode = X86ISD::PCMPISTRI;
16450 X86CC = X86::COND_E;
16452 case Intrinsic::x86_sse42_pcmpestriz128:
16453 Opcode = X86ISD::PCMPESTRI;
16454 X86CC = X86::COND_E;
16457 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16458 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16459 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16460 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16461 DAG.getConstant(X86CC, dl, MVT::i8),
16462 SDValue(PCMP.getNode(), 1));
16463 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16466 case Intrinsic::x86_sse42_pcmpistri128:
16467 case Intrinsic::x86_sse42_pcmpestri128: {
16469 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16470 Opcode = X86ISD::PCMPISTRI;
16472 Opcode = X86ISD::PCMPESTRI;
16474 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16475 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16476 return DAG.getNode(Opcode, dl, VTs, NewOps);
16479 case Intrinsic::x86_seh_lsda: {
16480 // Compute the symbol for the LSDA. We know it'll get emitted later.
16481 MachineFunction &MF = DAG.getMachineFunction();
16482 SDValue Op1 = Op.getOperand(1);
16483 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16484 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16485 GlobalValue::getRealLinkageName(Fn->getName()));
16487 // Generate a simple absolute symbol reference. This intrinsic is only
16488 // supported on 32-bit Windows, which isn't PIC.
16489 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16490 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16493 case Intrinsic::x86_seh_recoverfp: {
16494 SDValue FnOp = Op.getOperand(1);
16495 SDValue IncomingFPOp = Op.getOperand(2);
16496 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16497 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16499 report_fatal_error(
16500 "llvm.x86.seh.recoverfp must take a function as the first argument");
16501 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16504 case Intrinsic::localaddress: {
16505 // Returns one of the stack, base, or frame pointer registers, depending on
16506 // which is used to reference local variables.
16507 MachineFunction &MF = DAG.getMachineFunction();
16508 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16510 if (RegInfo->hasBasePointer(MF))
16511 Reg = RegInfo->getBaseRegister();
16512 else // This function handles the SP or FP case.
16513 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16514 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16519 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16520 SDValue Src, SDValue Mask, SDValue Base,
16521 SDValue Index, SDValue ScaleOp, SDValue Chain,
16522 const X86Subtarget * Subtarget) {
16524 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16526 llvm_unreachable("Invalid scale type");
16527 unsigned ScaleVal = C->getZExtValue();
16528 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16529 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16531 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16532 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16533 Index.getSimpleValueType().getVectorNumElements());
16535 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16537 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16539 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16540 Mask.getValueType().getSizeInBits());
16542 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16543 // are extracted by EXTRACT_SUBVECTOR.
16544 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16545 DAG.getBitcast(BitcastVT, Mask),
16546 DAG.getIntPtrConstant(0, dl));
16548 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16549 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16550 SDValue Segment = DAG.getRegister(0, MVT::i32);
16551 if (Src.getOpcode() == ISD::UNDEF)
16552 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16553 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16554 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16555 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16556 return DAG.getMergeValues(RetOps, dl);
16559 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16560 SDValue Src, SDValue Mask, SDValue Base,
16561 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16563 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16565 llvm_unreachable("Invalid scale type");
16566 unsigned ScaleVal = C->getZExtValue();
16567 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16568 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16570 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16571 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16572 SDValue Segment = DAG.getRegister(0, MVT::i32);
16573 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16574 Index.getSimpleValueType().getVectorNumElements());
16576 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16578 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16580 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16581 Mask.getValueType().getSizeInBits());
16583 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16584 // are extracted by EXTRACT_SUBVECTOR.
16585 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16586 DAG.getBitcast(BitcastVT, Mask),
16587 DAG.getIntPtrConstant(0, dl));
16589 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16590 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16591 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16592 return SDValue(Res, 1);
16595 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16596 SDValue Mask, SDValue Base, SDValue Index,
16597 SDValue ScaleOp, SDValue Chain) {
16599 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16600 assert(C && "Invalid scale type");
16601 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16602 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16603 SDValue Segment = DAG.getRegister(0, MVT::i32);
16605 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16607 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16609 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16611 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16612 //SDVTList VTs = DAG.getVTList(MVT::Other);
16613 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16614 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16615 return SDValue(Res, 0);
16618 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16619 // read performance monitor counters (x86_rdpmc).
16620 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16621 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16622 SmallVectorImpl<SDValue> &Results) {
16623 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16624 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16627 // The ECX register is used to select the index of the performance counter
16629 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16631 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16633 // Reads the content of a 64-bit performance counter and returns it in the
16634 // registers EDX:EAX.
16635 if (Subtarget->is64Bit()) {
16636 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16637 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16640 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16641 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16644 Chain = HI.getValue(1);
16646 if (Subtarget->is64Bit()) {
16647 // The EAX register is loaded with the low-order 32 bits. The EDX register
16648 // is loaded with the supported high-order bits of the counter.
16649 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16650 DAG.getConstant(32, DL, MVT::i8));
16651 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16652 Results.push_back(Chain);
16656 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16657 SDValue Ops[] = { LO, HI };
16658 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16659 Results.push_back(Pair);
16660 Results.push_back(Chain);
16663 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16664 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16665 // also used to custom lower READCYCLECOUNTER nodes.
16666 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16667 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16668 SmallVectorImpl<SDValue> &Results) {
16669 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16670 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16673 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16674 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16675 // and the EAX register is loaded with the low-order 32 bits.
16676 if (Subtarget->is64Bit()) {
16677 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16678 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16681 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16682 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16685 SDValue Chain = HI.getValue(1);
16687 if (Opcode == X86ISD::RDTSCP_DAG) {
16688 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16690 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16691 // the ECX register. Add 'ecx' explicitly to the chain.
16692 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16694 // Explicitly store the content of ECX at the location passed in input
16695 // to the 'rdtscp' intrinsic.
16696 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16697 MachinePointerInfo(), false, false, 0);
16700 if (Subtarget->is64Bit()) {
16701 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16702 // the EAX register is loaded with the low-order 32 bits.
16703 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16704 DAG.getConstant(32, DL, MVT::i8));
16705 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16706 Results.push_back(Chain);
16710 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16711 SDValue Ops[] = { LO, HI };
16712 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16713 Results.push_back(Pair);
16714 Results.push_back(Chain);
16717 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16718 SelectionDAG &DAG) {
16719 SmallVector<SDValue, 2> Results;
16721 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16723 return DAG.getMergeValues(Results, DL);
16726 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16727 SelectionDAG &DAG) {
16728 MachineFunction &MF = DAG.getMachineFunction();
16729 const Function *Fn = MF.getFunction();
16731 SDValue Chain = Op.getOperand(0);
16733 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16734 "using llvm.x86.seh.restoreframe requires a frame pointer");
16736 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16737 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16739 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16740 unsigned FrameReg =
16741 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16742 unsigned SPReg = RegInfo->getStackRegister();
16743 unsigned SlotSize = RegInfo->getSlotSize();
16745 // Get incoming EBP.
16746 SDValue IncomingEBP =
16747 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16749 // SP is saved in the first field of every registration node, so load
16750 // [EBP-RegNodeSize] into SP.
16751 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16752 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16753 DAG.getConstant(-RegNodeSize, dl, VT));
16755 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16756 false, VT.getScalarSizeInBits() / 8);
16757 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16759 if (!RegInfo->needsStackRealignment(MF)) {
16760 // Adjust EBP to point back to the original frame position.
16761 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16762 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16764 assert(RegInfo->hasBasePointer(MF) &&
16765 "functions with Win32 EH must use frame or base pointer register");
16767 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16768 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16769 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16771 // Reload the spilled EBP value, now that the stack and base pointers are
16773 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16774 X86FI->setHasSEHFramePtrSave(true);
16775 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16776 X86FI->setSEHFramePtrSaveIndex(FI);
16777 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16778 MachinePointerInfo(), false, false, false,
16779 VT.getScalarSizeInBits() / 8);
16780 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16786 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16787 /// return truncate Store/MaskedStore Node
16788 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16792 SDValue Mask = Op.getOperand(4);
16793 SDValue DataToTruncate = Op.getOperand(3);
16794 SDValue Addr = Op.getOperand(2);
16795 SDValue Chain = Op.getOperand(0);
16797 EVT VT = DataToTruncate.getValueType();
16798 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16799 ElementType, VT.getVectorNumElements());
16801 if (isAllOnes(Mask)) // return just a truncate store
16802 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16803 MachinePointerInfo(), SVT, false, false,
16804 SVT.getScalarSizeInBits()/8);
16806 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16807 MVT::i1, VT.getVectorNumElements());
16808 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16809 Mask.getValueType().getSizeInBits());
16810 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16811 // are extracted by EXTRACT_SUBVECTOR.
16812 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16813 DAG.getBitcast(BitcastVT, Mask),
16814 DAG.getIntPtrConstant(0, dl));
16816 MachineMemOperand *MMO = DAG.getMachineFunction().
16817 getMachineMemOperand(MachinePointerInfo(),
16818 MachineMemOperand::MOStore, SVT.getStoreSize(),
16819 SVT.getScalarSizeInBits()/8);
16821 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16822 VMask, SVT, MMO, true);
16825 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16826 SelectionDAG &DAG) {
16827 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16829 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16831 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16832 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16837 switch(IntrData->Type) {
16839 llvm_unreachable("Unknown Intrinsic Type");
16843 // Emit the node with the right value type.
16844 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16845 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16847 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16848 // Otherwise return the value from Rand, which is always 0, casted to i32.
16849 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16850 DAG.getConstant(1, dl, Op->getValueType(1)),
16851 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16852 SDValue(Result.getNode(), 1) };
16853 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16854 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16857 // Return { result, isValid, chain }.
16858 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16859 SDValue(Result.getNode(), 2));
16862 //gather(v1, mask, index, base, scale);
16863 SDValue Chain = Op.getOperand(0);
16864 SDValue Src = Op.getOperand(2);
16865 SDValue Base = Op.getOperand(3);
16866 SDValue Index = Op.getOperand(4);
16867 SDValue Mask = Op.getOperand(5);
16868 SDValue Scale = Op.getOperand(6);
16869 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16873 //scatter(base, mask, index, v1, scale);
16874 SDValue Chain = Op.getOperand(0);
16875 SDValue Base = Op.getOperand(2);
16876 SDValue Mask = Op.getOperand(3);
16877 SDValue Index = Op.getOperand(4);
16878 SDValue Src = Op.getOperand(5);
16879 SDValue Scale = Op.getOperand(6);
16880 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16884 SDValue Hint = Op.getOperand(6);
16885 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16886 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16887 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16888 SDValue Chain = Op.getOperand(0);
16889 SDValue Mask = Op.getOperand(2);
16890 SDValue Index = Op.getOperand(3);
16891 SDValue Base = Op.getOperand(4);
16892 SDValue Scale = Op.getOperand(5);
16893 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16895 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16897 SmallVector<SDValue, 2> Results;
16898 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16900 return DAG.getMergeValues(Results, dl);
16902 // Read Performance Monitoring Counters.
16904 SmallVector<SDValue, 2> Results;
16905 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16906 return DAG.getMergeValues(Results, dl);
16908 // XTEST intrinsics.
16910 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16911 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16912 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16913 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16915 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16916 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16917 Ret, SDValue(InTrans.getNode(), 1));
16921 SmallVector<SDValue, 2> Results;
16922 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16923 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16924 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16925 DAG.getConstant(-1, dl, MVT::i8));
16926 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16927 Op.getOperand(4), GenCF.getValue(1));
16928 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16929 Op.getOperand(5), MachinePointerInfo(),
16931 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16932 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16934 Results.push_back(SetCC);
16935 Results.push_back(Store);
16936 return DAG.getMergeValues(Results, dl);
16938 case COMPRESS_TO_MEM: {
16940 SDValue Mask = Op.getOperand(4);
16941 SDValue DataToCompress = Op.getOperand(3);
16942 SDValue Addr = Op.getOperand(2);
16943 SDValue Chain = Op.getOperand(0);
16945 EVT VT = DataToCompress.getValueType();
16946 if (isAllOnes(Mask)) // return just a store
16947 return DAG.getStore(Chain, dl, DataToCompress, Addr,
16948 MachinePointerInfo(), false, false,
16949 VT.getScalarSizeInBits()/8);
16951 SDValue Compressed =
16952 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
16953 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
16954 return DAG.getStore(Chain, dl, Compressed, Addr,
16955 MachinePointerInfo(), false, false,
16956 VT.getScalarSizeInBits()/8);
16958 case TRUNCATE_TO_MEM_VI8:
16959 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
16960 case TRUNCATE_TO_MEM_VI16:
16961 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
16962 case TRUNCATE_TO_MEM_VI32:
16963 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
16964 case EXPAND_FROM_MEM: {
16966 SDValue Mask = Op.getOperand(4);
16967 SDValue PassThru = Op.getOperand(3);
16968 SDValue Addr = Op.getOperand(2);
16969 SDValue Chain = Op.getOperand(0);
16970 EVT VT = Op.getValueType();
16972 if (isAllOnes(Mask)) // return just a load
16973 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
16974 false, VT.getScalarSizeInBits()/8);
16976 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
16977 false, false, false,
16978 VT.getScalarSizeInBits()/8);
16980 SDValue Results[] = {
16981 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
16982 Mask, PassThru, Subtarget, DAG), Chain};
16983 return DAG.getMergeValues(Results, dl);
16988 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16989 SelectionDAG &DAG) const {
16990 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16991 MFI->setReturnAddressIsTaken(true);
16993 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16996 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16998 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17001 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17002 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17003 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17004 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17005 DAG.getNode(ISD::ADD, dl, PtrVT,
17006 FrameAddr, Offset),
17007 MachinePointerInfo(), false, false, false, 0);
17010 // Just load the return address.
17011 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17012 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17013 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17016 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17017 MachineFunction &MF = DAG.getMachineFunction();
17018 MachineFrameInfo *MFI = MF.getFrameInfo();
17019 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17020 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17021 EVT VT = Op.getValueType();
17023 MFI->setFrameAddressIsTaken(true);
17025 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17026 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17027 // is not possible to crawl up the stack without looking at the unwind codes
17029 int FrameAddrIndex = FuncInfo->getFAIndex();
17030 if (!FrameAddrIndex) {
17031 // Set up a frame object for the return address.
17032 unsigned SlotSize = RegInfo->getSlotSize();
17033 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17034 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17035 FuncInfo->setFAIndex(FrameAddrIndex);
17037 return DAG.getFrameIndex(FrameAddrIndex, VT);
17040 unsigned FrameReg =
17041 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17042 SDLoc dl(Op); // FIXME probably not meaningful
17043 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17044 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17045 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17046 "Invalid Frame Register!");
17047 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17049 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17050 MachinePointerInfo(),
17051 false, false, false, 0);
17055 // FIXME? Maybe this could be a TableGen attribute on some registers and
17056 // this table could be generated automatically from RegInfo.
17057 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17058 SelectionDAG &DAG) const {
17059 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17060 const MachineFunction &MF = DAG.getMachineFunction();
17062 unsigned Reg = StringSwitch<unsigned>(RegName)
17063 .Case("esp", X86::ESP)
17064 .Case("rsp", X86::RSP)
17065 .Case("ebp", X86::EBP)
17066 .Case("rbp", X86::RBP)
17069 if (Reg == X86::EBP || Reg == X86::RBP) {
17070 if (!TFI.hasFP(MF))
17071 report_fatal_error("register " + StringRef(RegName) +
17072 " is allocatable: function has no frame pointer");
17075 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17076 unsigned FrameReg =
17077 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17078 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17079 "Invalid Frame Register!");
17087 report_fatal_error("Invalid register name global variable");
17090 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17091 SelectionDAG &DAG) const {
17092 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17093 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17096 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17097 SDValue Chain = Op.getOperand(0);
17098 SDValue Offset = Op.getOperand(1);
17099 SDValue Handler = Op.getOperand(2);
17102 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17103 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17104 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17105 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17106 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17107 "Invalid Frame Register!");
17108 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17109 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17111 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17112 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17114 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17115 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17117 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17119 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17120 DAG.getRegister(StoreAddrReg, PtrVT));
17123 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17124 SelectionDAG &DAG) const {
17126 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17127 DAG.getVTList(MVT::i32, MVT::Other),
17128 Op.getOperand(0), Op.getOperand(1));
17131 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17132 SelectionDAG &DAG) const {
17134 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17135 Op.getOperand(0), Op.getOperand(1));
17138 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17139 return Op.getOperand(0);
17142 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17143 SelectionDAG &DAG) const {
17144 SDValue Root = Op.getOperand(0);
17145 SDValue Trmp = Op.getOperand(1); // trampoline
17146 SDValue FPtr = Op.getOperand(2); // nested function
17147 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17150 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17151 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17153 if (Subtarget->is64Bit()) {
17154 SDValue OutChains[6];
17156 // Large code-model.
17157 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17158 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17160 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17161 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17163 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17165 // Load the pointer to the nested function into R11.
17166 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17167 SDValue Addr = Trmp;
17168 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17169 Addr, MachinePointerInfo(TrmpAddr),
17172 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17173 DAG.getConstant(2, dl, MVT::i64));
17174 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17175 MachinePointerInfo(TrmpAddr, 2),
17178 // Load the 'nest' parameter value into R10.
17179 // R10 is specified in X86CallingConv.td
17180 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17181 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17182 DAG.getConstant(10, dl, MVT::i64));
17183 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17184 Addr, MachinePointerInfo(TrmpAddr, 10),
17187 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17188 DAG.getConstant(12, dl, MVT::i64));
17189 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17190 MachinePointerInfo(TrmpAddr, 12),
17193 // Jump to the nested function.
17194 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17195 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17196 DAG.getConstant(20, dl, MVT::i64));
17197 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17198 Addr, MachinePointerInfo(TrmpAddr, 20),
17201 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17202 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17203 DAG.getConstant(22, dl, MVT::i64));
17204 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17205 Addr, MachinePointerInfo(TrmpAddr, 22),
17208 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17210 const Function *Func =
17211 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17212 CallingConv::ID CC = Func->getCallingConv();
17217 llvm_unreachable("Unsupported calling convention");
17218 case CallingConv::C:
17219 case CallingConv::X86_StdCall: {
17220 // Pass 'nest' parameter in ECX.
17221 // Must be kept in sync with X86CallingConv.td
17222 NestReg = X86::ECX;
17224 // Check that ECX wasn't needed by an 'inreg' parameter.
17225 FunctionType *FTy = Func->getFunctionType();
17226 const AttributeSet &Attrs = Func->getAttributes();
17228 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17229 unsigned InRegCount = 0;
17232 for (FunctionType::param_iterator I = FTy->param_begin(),
17233 E = FTy->param_end(); I != E; ++I, ++Idx)
17234 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17235 auto &DL = DAG.getDataLayout();
17236 // FIXME: should only count parameters that are lowered to integers.
17237 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17240 if (InRegCount > 2) {
17241 report_fatal_error("Nest register in use - reduce number of inreg"
17247 case CallingConv::X86_FastCall:
17248 case CallingConv::X86_ThisCall:
17249 case CallingConv::Fast:
17250 // Pass 'nest' parameter in EAX.
17251 // Must be kept in sync with X86CallingConv.td
17252 NestReg = X86::EAX;
17256 SDValue OutChains[4];
17257 SDValue Addr, Disp;
17259 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17260 DAG.getConstant(10, dl, MVT::i32));
17261 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17263 // This is storing the opcode for MOV32ri.
17264 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17265 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17266 OutChains[0] = DAG.getStore(Root, dl,
17267 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17268 Trmp, MachinePointerInfo(TrmpAddr),
17271 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17272 DAG.getConstant(1, dl, MVT::i32));
17273 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17274 MachinePointerInfo(TrmpAddr, 1),
17277 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17278 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17279 DAG.getConstant(5, dl, MVT::i32));
17280 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17281 Addr, MachinePointerInfo(TrmpAddr, 5),
17284 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17285 DAG.getConstant(6, dl, MVT::i32));
17286 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17287 MachinePointerInfo(TrmpAddr, 6),
17290 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17294 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17295 SelectionDAG &DAG) const {
17297 The rounding mode is in bits 11:10 of FPSR, and has the following
17299 00 Round to nearest
17304 FLT_ROUNDS, on the other hand, expects the following:
17311 To perform the conversion, we do:
17312 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17315 MachineFunction &MF = DAG.getMachineFunction();
17316 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17317 unsigned StackAlignment = TFI.getStackAlignment();
17318 MVT VT = Op.getSimpleValueType();
17321 // Save FP Control Word to stack slot
17322 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17323 SDValue StackSlot =
17324 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17326 MachineMemOperand *MMO =
17327 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17328 MachineMemOperand::MOStore, 2, 2);
17330 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17331 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17332 DAG.getVTList(MVT::Other),
17333 Ops, MVT::i16, MMO);
17335 // Load FP Control Word from stack slot
17336 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17337 MachinePointerInfo(), false, false, false, 0);
17339 // Transform as necessary
17341 DAG.getNode(ISD::SRL, DL, MVT::i16,
17342 DAG.getNode(ISD::AND, DL, MVT::i16,
17343 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17344 DAG.getConstant(11, DL, MVT::i8));
17346 DAG.getNode(ISD::SRL, DL, MVT::i16,
17347 DAG.getNode(ISD::AND, DL, MVT::i16,
17348 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17349 DAG.getConstant(9, DL, MVT::i8));
17352 DAG.getNode(ISD::AND, DL, MVT::i16,
17353 DAG.getNode(ISD::ADD, DL, MVT::i16,
17354 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17355 DAG.getConstant(1, DL, MVT::i16)),
17356 DAG.getConstant(3, DL, MVT::i16));
17358 return DAG.getNode((VT.getSizeInBits() < 16 ?
17359 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17362 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17363 MVT VT = Op.getSimpleValueType();
17365 unsigned NumBits = VT.getSizeInBits();
17368 Op = Op.getOperand(0);
17369 if (VT == MVT::i8) {
17370 // Zero extend to i32 since there is not an i8 bsr.
17372 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17375 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17376 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17377 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17379 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17382 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17383 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17386 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17388 // Finally xor with NumBits-1.
17389 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17390 DAG.getConstant(NumBits - 1, dl, OpVT));
17393 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17397 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17398 MVT VT = Op.getSimpleValueType();
17400 unsigned NumBits = VT.getSizeInBits();
17403 Op = Op.getOperand(0);
17404 if (VT == MVT::i8) {
17405 // Zero extend to i32 since there is not an i8 bsr.
17407 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17410 // Issue a bsr (scan bits in reverse).
17411 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17412 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17414 // And xor with NumBits-1.
17415 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17416 DAG.getConstant(NumBits - 1, dl, OpVT));
17419 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17423 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17424 MVT VT = Op.getSimpleValueType();
17425 unsigned NumBits = VT.getScalarSizeInBits();
17428 if (VT.isVector()) {
17429 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17431 SDValue N0 = Op.getOperand(0);
17432 SDValue Zero = DAG.getConstant(0, dl, VT);
17434 // lsb(x) = (x & -x)
17435 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17436 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17438 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17439 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17440 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17441 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17442 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17443 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17446 // cttz(x) = ctpop(lsb - 1)
17447 SDValue One = DAG.getConstant(1, dl, VT);
17448 return DAG.getNode(ISD::CTPOP, dl, VT,
17449 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17452 assert(Op.getOpcode() == ISD::CTTZ &&
17453 "Only scalar CTTZ requires custom lowering");
17455 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17456 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17457 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17459 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17462 DAG.getConstant(NumBits, dl, VT),
17463 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17466 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17469 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17470 // ones, and then concatenate the result back.
17471 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17472 MVT VT = Op.getSimpleValueType();
17474 assert(VT.is256BitVector() && VT.isInteger() &&
17475 "Unsupported value type for operation");
17477 unsigned NumElems = VT.getVectorNumElements();
17480 // Extract the LHS vectors
17481 SDValue LHS = Op.getOperand(0);
17482 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17483 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17485 // Extract the RHS vectors
17486 SDValue RHS = Op.getOperand(1);
17487 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17488 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17490 MVT EltVT = VT.getVectorElementType();
17491 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17493 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17494 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17495 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17498 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17499 if (Op.getValueType() == MVT::i1)
17500 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17501 Op.getOperand(0), Op.getOperand(1));
17502 assert(Op.getSimpleValueType().is256BitVector() &&
17503 Op.getSimpleValueType().isInteger() &&
17504 "Only handle AVX 256-bit vector integer operation");
17505 return Lower256IntArith(Op, DAG);
17508 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17509 if (Op.getValueType() == MVT::i1)
17510 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17511 Op.getOperand(0), Op.getOperand(1));
17512 assert(Op.getSimpleValueType().is256BitVector() &&
17513 Op.getSimpleValueType().isInteger() &&
17514 "Only handle AVX 256-bit vector integer operation");
17515 return Lower256IntArith(Op, DAG);
17518 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17519 assert(Op.getSimpleValueType().is256BitVector() &&
17520 Op.getSimpleValueType().isInteger() &&
17521 "Only handle AVX 256-bit vector integer operation");
17522 return Lower256IntArith(Op, DAG);
17525 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17526 SelectionDAG &DAG) {
17528 MVT VT = Op.getSimpleValueType();
17531 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17533 // Decompose 256-bit ops into smaller 128-bit ops.
17534 if (VT.is256BitVector() && !Subtarget->hasInt256())
17535 return Lower256IntArith(Op, DAG);
17537 SDValue A = Op.getOperand(0);
17538 SDValue B = Op.getOperand(1);
17540 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17541 // pairs, multiply and truncate.
17542 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17543 if (Subtarget->hasInt256()) {
17544 if (VT == MVT::v32i8) {
17545 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17546 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17547 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17548 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17549 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17550 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17551 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17552 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17553 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17554 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17557 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17558 return DAG.getNode(
17559 ISD::TRUNCATE, dl, VT,
17560 DAG.getNode(ISD::MUL, dl, ExVT,
17561 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17562 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17565 assert(VT == MVT::v16i8 &&
17566 "Pre-AVX2 support only supports v16i8 multiplication");
17567 MVT ExVT = MVT::v8i16;
17569 // Extract the lo parts and sign extend to i16
17571 if (Subtarget->hasSSE41()) {
17572 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17573 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17575 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17576 -1, 4, -1, 5, -1, 6, -1, 7};
17577 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17578 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17579 ALo = DAG.getBitcast(ExVT, ALo);
17580 BLo = DAG.getBitcast(ExVT, BLo);
17581 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17582 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17585 // Extract the hi parts and sign extend to i16
17587 if (Subtarget->hasSSE41()) {
17588 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17589 -1, -1, -1, -1, -1, -1, -1, -1};
17590 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17591 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17592 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17593 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17595 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17596 -1, 12, -1, 13, -1, 14, -1, 15};
17597 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17598 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17599 AHi = DAG.getBitcast(ExVT, AHi);
17600 BHi = DAG.getBitcast(ExVT, BHi);
17601 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17602 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17605 // Multiply, mask the lower 8bits of the lo/hi results and pack
17606 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17607 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17608 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17609 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17610 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17613 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17614 if (VT == MVT::v4i32) {
17615 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17616 "Should not custom lower when pmuldq is available!");
17618 // Extract the odd parts.
17619 static const int UnpackMask[] = { 1, -1, 3, -1 };
17620 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17621 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17623 // Multiply the even parts.
17624 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17625 // Now multiply odd parts.
17626 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17628 Evens = DAG.getBitcast(VT, Evens);
17629 Odds = DAG.getBitcast(VT, Odds);
17631 // Merge the two vectors back together with a shuffle. This expands into 2
17633 static const int ShufMask[] = { 0, 4, 2, 6 };
17634 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17637 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17638 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17640 // Ahi = psrlqi(a, 32);
17641 // Bhi = psrlqi(b, 32);
17643 // AloBlo = pmuludq(a, b);
17644 // AloBhi = pmuludq(a, Bhi);
17645 // AhiBlo = pmuludq(Ahi, b);
17647 // AloBhi = psllqi(AloBhi, 32);
17648 // AhiBlo = psllqi(AhiBlo, 32);
17649 // return AloBlo + AloBhi + AhiBlo;
17651 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17652 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17654 SDValue AhiBlo = Ahi;
17655 SDValue AloBhi = Bhi;
17656 // Bit cast to 32-bit vectors for MULUDQ
17657 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17658 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17659 A = DAG.getBitcast(MulVT, A);
17660 B = DAG.getBitcast(MulVT, B);
17661 Ahi = DAG.getBitcast(MulVT, Ahi);
17662 Bhi = DAG.getBitcast(MulVT, Bhi);
17664 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17665 // After shifting right const values the result may be all-zero.
17666 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17667 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17668 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17670 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17671 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17672 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17675 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17676 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17679 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17680 assert(Subtarget->isTargetWin64() && "Unexpected target");
17681 EVT VT = Op.getValueType();
17682 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17683 "Unexpected return type for lowering");
17687 switch (Op->getOpcode()) {
17688 default: llvm_unreachable("Unexpected request for libcall!");
17689 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17690 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17691 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17692 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17693 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17694 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17698 SDValue InChain = DAG.getEntryNode();
17700 TargetLowering::ArgListTy Args;
17701 TargetLowering::ArgListEntry Entry;
17702 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17703 EVT ArgVT = Op->getOperand(i).getValueType();
17704 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17705 "Unexpected argument type for lowering");
17706 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17707 Entry.Node = StackPtr;
17708 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17710 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17711 Entry.Ty = PointerType::get(ArgTy,0);
17712 Entry.isSExt = false;
17713 Entry.isZExt = false;
17714 Args.push_back(Entry);
17717 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17718 getPointerTy(DAG.getDataLayout()));
17720 TargetLowering::CallLoweringInfo CLI(DAG);
17721 CLI.setDebugLoc(dl).setChain(InChain)
17722 .setCallee(getLibcallCallingConv(LC),
17723 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17724 Callee, std::move(Args), 0)
17725 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17727 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17728 return DAG.getBitcast(VT, CallInfo.first);
17731 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17732 SelectionDAG &DAG) {
17733 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17734 EVT VT = Op0.getValueType();
17737 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17738 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17740 // PMULxD operations multiply each even value (starting at 0) of LHS with
17741 // the related value of RHS and produce a widen result.
17742 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17743 // => <2 x i64> <ae|cg>
17745 // In other word, to have all the results, we need to perform two PMULxD:
17746 // 1. one with the even values.
17747 // 2. one with the odd values.
17748 // To achieve #2, with need to place the odd values at an even position.
17750 // Place the odd value at an even position (basically, shift all values 1
17751 // step to the left):
17752 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17753 // <a|b|c|d> => <b|undef|d|undef>
17754 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17755 // <e|f|g|h> => <f|undef|h|undef>
17756 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17758 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17760 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17761 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17763 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17764 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17765 // => <2 x i64> <ae|cg>
17766 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17767 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17768 // => <2 x i64> <bf|dh>
17769 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17771 // Shuffle it back into the right order.
17772 SDValue Highs, Lows;
17773 if (VT == MVT::v8i32) {
17774 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17775 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17776 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17777 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17779 const int HighMask[] = {1, 5, 3, 7};
17780 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17781 const int LowMask[] = {0, 4, 2, 6};
17782 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17785 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17786 // unsigned multiply.
17787 if (IsSigned && !Subtarget->hasSSE41()) {
17788 SDValue ShAmt = DAG.getConstant(
17790 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17791 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17792 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17793 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17794 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17796 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17797 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17800 // The first result of MUL_LOHI is actually the low value, followed by the
17802 SDValue Ops[] = {Lows, Highs};
17803 return DAG.getMergeValues(Ops, dl);
17806 // Return true if the required (according to Opcode) shift-imm form is natively
17807 // supported by the Subtarget
17808 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
17810 if (VT.getScalarSizeInBits() < 16)
17813 if (VT.is512BitVector() &&
17814 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
17817 bool LShift = VT.is128BitVector() ||
17818 (VT.is256BitVector() && Subtarget->hasInt256());
17820 bool AShift = LShift && (Subtarget->hasVLX() ||
17821 (VT != MVT::v2i64 && VT != MVT::v4i64));
17822 return (Opcode == ISD::SRA) ? AShift : LShift;
17825 // The shift amount is a variable, but it is the same for all vector lanes.
17826 // These instructions are defined together with shift-immediate.
17828 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
17830 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
17833 // Return true if the required (according to Opcode) variable-shift form is
17834 // natively supported by the Subtarget
17835 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
17838 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
17841 // vXi16 supported only on AVX-512, BWI
17842 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
17845 if (VT.is512BitVector() || Subtarget->hasVLX())
17848 bool LShift = VT.is128BitVector() || VT.is256BitVector();
17849 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17850 return (Opcode == ISD::SRA) ? AShift : LShift;
17853 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17854 const X86Subtarget *Subtarget) {
17855 MVT VT = Op.getSimpleValueType();
17857 SDValue R = Op.getOperand(0);
17858 SDValue Amt = Op.getOperand(1);
17860 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17861 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17863 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
17864 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
17865 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
17866 SDValue Ex = DAG.getBitcast(ExVT, R);
17868 if (ShiftAmt >= 32) {
17869 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
17871 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
17872 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17873 ShiftAmt - 32, DAG);
17874 if (VT == MVT::v2i64)
17875 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
17876 if (VT == MVT::v4i64)
17877 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17878 {9, 1, 11, 3, 13, 5, 15, 7});
17880 // SRA upper i32, SHL whole i64 and select lower i32.
17881 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17884 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
17885 Lower = DAG.getBitcast(ExVT, Lower);
17886 if (VT == MVT::v2i64)
17887 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
17888 if (VT == MVT::v4i64)
17889 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17890 {8, 1, 10, 3, 12, 5, 14, 7});
17892 return DAG.getBitcast(VT, Ex);
17895 // Optimize shl/srl/sra with constant shift amount.
17896 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17897 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17898 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17900 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17901 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17903 // i64 SRA needs to be performed as partial shifts.
17904 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17905 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
17906 return ArithmeticShiftRight64(ShiftAmt);
17908 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
17909 unsigned NumElts = VT.getVectorNumElements();
17910 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
17912 // Simple i8 add case
17913 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
17914 return DAG.getNode(ISD::ADD, dl, VT, R, R);
17916 // ashr(R, 7) === cmp_slt(R, 0)
17917 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
17918 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17919 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17922 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
17923 if (VT == MVT::v16i8 && Subtarget->hasXOP())
17926 if (Op.getOpcode() == ISD::SHL) {
17927 // Make a large shift.
17928 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
17930 SHL = DAG.getBitcast(VT, SHL);
17931 // Zero out the rightmost bits.
17932 SmallVector<SDValue, 32> V(
17933 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
17934 return DAG.getNode(ISD::AND, dl, VT, SHL,
17935 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17937 if (Op.getOpcode() == ISD::SRL) {
17938 // Make a large shift.
17939 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
17941 SRL = DAG.getBitcast(VT, SRL);
17942 // Zero out the leftmost bits.
17943 SmallVector<SDValue, 32> V(
17944 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
17945 return DAG.getNode(ISD::AND, dl, VT, SRL,
17946 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17948 if (Op.getOpcode() == ISD::SRA) {
17949 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
17950 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17951 SmallVector<SDValue, 32> V(NumElts,
17952 DAG.getConstant(128 >> ShiftAmt, dl,
17954 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17955 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17956 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17959 llvm_unreachable("Unknown shift opcode.");
17964 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17965 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
17966 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
17968 // Peek through any splat that was introduced for i64 shift vectorization.
17969 int SplatIndex = -1;
17970 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
17971 if (SVN->isSplat()) {
17972 SplatIndex = SVN->getSplatIndex();
17973 Amt = Amt.getOperand(0);
17974 assert(SplatIndex < (int)VT.getVectorNumElements() &&
17975 "Splat shuffle referencing second operand");
17978 if (Amt.getOpcode() != ISD::BITCAST ||
17979 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
17982 Amt = Amt.getOperand(0);
17983 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17984 VT.getVectorNumElements();
17985 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17986 uint64_t ShiftAmt = 0;
17987 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
17988 for (unsigned i = 0; i != Ratio; ++i) {
17989 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
17993 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17996 // Check remaining shift amounts (if not a splat).
17997 if (SplatIndex < 0) {
17998 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17999 uint64_t ShAmt = 0;
18000 for (unsigned j = 0; j != Ratio; ++j) {
18001 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18005 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18007 if (ShAmt != ShiftAmt)
18012 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18013 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18015 if (Op.getOpcode() == ISD::SRA)
18016 return ArithmeticShiftRight64(ShiftAmt);
18022 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18023 const X86Subtarget* Subtarget) {
18024 MVT VT = Op.getSimpleValueType();
18026 SDValue R = Op.getOperand(0);
18027 SDValue Amt = Op.getOperand(1);
18029 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18030 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18032 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18033 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18035 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18037 EVT EltVT = VT.getVectorElementType();
18039 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18040 // Check if this build_vector node is doing a splat.
18041 // If so, then set BaseShAmt equal to the splat value.
18042 BaseShAmt = BV->getSplatValue();
18043 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18044 BaseShAmt = SDValue();
18046 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18047 Amt = Amt.getOperand(0);
18049 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18050 if (SVN && SVN->isSplat()) {
18051 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18052 SDValue InVec = Amt.getOperand(0);
18053 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18054 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18055 "Unexpected shuffle index found!");
18056 BaseShAmt = InVec.getOperand(SplatIdx);
18057 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18058 if (ConstantSDNode *C =
18059 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18060 if (C->getZExtValue() == SplatIdx)
18061 BaseShAmt = InVec.getOperand(1);
18066 // Avoid introducing an extract element from a shuffle.
18067 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18068 DAG.getIntPtrConstant(SplatIdx, dl));
18072 if (BaseShAmt.getNode()) {
18073 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18074 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18075 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18076 else if (EltVT.bitsLT(MVT::i32))
18077 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18079 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18083 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18084 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18085 Amt.getOpcode() == ISD::BITCAST &&
18086 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18087 Amt = Amt.getOperand(0);
18088 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18089 VT.getVectorNumElements();
18090 std::vector<SDValue> Vals(Ratio);
18091 for (unsigned i = 0; i != Ratio; ++i)
18092 Vals[i] = Amt.getOperand(i);
18093 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18094 for (unsigned j = 0; j != Ratio; ++j)
18095 if (Vals[j] != Amt.getOperand(i + j))
18099 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18100 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18105 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18106 SelectionDAG &DAG) {
18107 MVT VT = Op.getSimpleValueType();
18109 SDValue R = Op.getOperand(0);
18110 SDValue Amt = Op.getOperand(1);
18112 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18113 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18115 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18118 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18121 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18124 // XOP has 128-bit variable logical/arithmetic shifts.
18125 // +ve/-ve Amt = shift left/right.
18126 if (Subtarget->hasXOP() &&
18127 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18128 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18129 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18130 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18131 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18133 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18134 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18135 if (Op.getOpcode() == ISD::SRA)
18136 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18139 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18140 // shifts per-lane and then shuffle the partial results back together.
18141 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18142 // Splat the shift amounts so the scalar shifts above will catch it.
18143 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18144 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18145 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18146 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18147 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18150 // i64 vector arithmetic shift can be emulated with the transform:
18151 // M = lshr(SIGN_BIT, Amt)
18152 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18153 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18154 Op.getOpcode() == ISD::SRA) {
18155 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18156 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18157 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18158 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18159 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18163 // If possible, lower this packed shift into a vector multiply instead of
18164 // expanding it into a sequence of scalar shifts.
18165 // Do this only if the vector shift count is a constant build_vector.
18166 if (Op.getOpcode() == ISD::SHL &&
18167 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18168 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18169 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18170 SmallVector<SDValue, 8> Elts;
18171 EVT SVT = VT.getScalarType();
18172 unsigned SVTBits = SVT.getSizeInBits();
18173 const APInt &One = APInt(SVTBits, 1);
18174 unsigned NumElems = VT.getVectorNumElements();
18176 for (unsigned i=0; i !=NumElems; ++i) {
18177 SDValue Op = Amt->getOperand(i);
18178 if (Op->getOpcode() == ISD::UNDEF) {
18179 Elts.push_back(Op);
18183 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18184 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18185 uint64_t ShAmt = C.getZExtValue();
18186 if (ShAmt >= SVTBits) {
18187 Elts.push_back(DAG.getUNDEF(SVT));
18190 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18192 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18193 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18196 // Lower SHL with variable shift amount.
18197 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18198 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18200 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18201 DAG.getConstant(0x3f800000U, dl, VT));
18202 Op = DAG.getBitcast(MVT::v4f32, Op);
18203 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18204 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18207 // If possible, lower this shift as a sequence of two shifts by
18208 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18210 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18212 // Could be rewritten as:
18213 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18215 // The advantage is that the two shifts from the example would be
18216 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18217 // the vector shift into four scalar shifts plus four pairs of vector
18219 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18220 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18221 unsigned TargetOpcode = X86ISD::MOVSS;
18222 bool CanBeSimplified;
18223 // The splat value for the first packed shift (the 'X' from the example).
18224 SDValue Amt1 = Amt->getOperand(0);
18225 // The splat value for the second packed shift (the 'Y' from the example).
18226 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18227 Amt->getOperand(2);
18229 // See if it is possible to replace this node with a sequence of
18230 // two shifts followed by a MOVSS/MOVSD
18231 if (VT == MVT::v4i32) {
18232 // Check if it is legal to use a MOVSS.
18233 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18234 Amt2 == Amt->getOperand(3);
18235 if (!CanBeSimplified) {
18236 // Otherwise, check if we can still simplify this node using a MOVSD.
18237 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18238 Amt->getOperand(2) == Amt->getOperand(3);
18239 TargetOpcode = X86ISD::MOVSD;
18240 Amt2 = Amt->getOperand(2);
18243 // Do similar checks for the case where the machine value type
18245 CanBeSimplified = Amt1 == Amt->getOperand(1);
18246 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18247 CanBeSimplified = Amt2 == Amt->getOperand(i);
18249 if (!CanBeSimplified) {
18250 TargetOpcode = X86ISD::MOVSD;
18251 CanBeSimplified = true;
18252 Amt2 = Amt->getOperand(4);
18253 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18254 CanBeSimplified = Amt1 == Amt->getOperand(i);
18255 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18256 CanBeSimplified = Amt2 == Amt->getOperand(j);
18260 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18261 isa<ConstantSDNode>(Amt2)) {
18262 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18263 EVT CastVT = MVT::v4i32;
18265 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18266 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18268 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18269 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18270 if (TargetOpcode == X86ISD::MOVSD)
18271 CastVT = MVT::v2i64;
18272 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18273 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18274 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18276 return DAG.getBitcast(VT, Result);
18280 // v4i32 Non Uniform Shifts.
18281 // If the shift amount is constant we can shift each lane using the SSE2
18282 // immediate shifts, else we need to zero-extend each lane to the lower i64
18283 // and shift using the SSE2 variable shifts.
18284 // The separate results can then be blended together.
18285 if (VT == MVT::v4i32) {
18286 unsigned Opc = Op.getOpcode();
18287 SDValue Amt0, Amt1, Amt2, Amt3;
18288 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18289 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18290 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18291 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18292 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18294 // ISD::SHL is handled above but we include it here for completeness.
18297 llvm_unreachable("Unknown target vector shift node");
18299 Opc = X86ISD::VSHL;
18302 Opc = X86ISD::VSRL;
18305 Opc = X86ISD::VSRA;
18308 // The SSE2 shifts use the lower i64 as the same shift amount for
18309 // all lanes and the upper i64 is ignored. These shuffle masks
18310 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18311 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18312 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18313 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18314 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18315 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18318 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18319 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18320 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18321 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18322 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18323 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18324 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18327 if (VT == MVT::v16i8 ||
18328 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18329 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18330 unsigned ShiftOpcode = Op->getOpcode();
18332 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18333 // On SSE41 targets we make use of the fact that VSELECT lowers
18334 // to PBLENDVB which selects bytes based just on the sign bit.
18335 if (Subtarget->hasSSE41()) {
18336 V0 = DAG.getBitcast(VT, V0);
18337 V1 = DAG.getBitcast(VT, V1);
18338 Sel = DAG.getBitcast(VT, Sel);
18339 return DAG.getBitcast(SelVT,
18340 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18342 // On pre-SSE41 targets we test for the sign bit by comparing to
18343 // zero - a negative value will set all bits of the lanes to true
18344 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18345 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18346 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18347 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18350 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18351 // We can safely do this using i16 shifts as we're only interested in
18352 // the 3 lower bits of each byte.
18353 Amt = DAG.getBitcast(ExtVT, Amt);
18354 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18355 Amt = DAG.getBitcast(VT, Amt);
18357 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18358 // r = VSELECT(r, shift(r, 4), a);
18360 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18361 R = SignBitSelect(VT, Amt, M, R);
18364 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18366 // r = VSELECT(r, shift(r, 2), a);
18367 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18368 R = SignBitSelect(VT, Amt, M, R);
18371 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18373 // return VSELECT(r, shift(r, 1), a);
18374 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18375 R = SignBitSelect(VT, Amt, M, R);
18379 if (Op->getOpcode() == ISD::SRA) {
18380 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18381 // so we can correctly sign extend. We don't care what happens to the
18383 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18384 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18385 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18386 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18387 ALo = DAG.getBitcast(ExtVT, ALo);
18388 AHi = DAG.getBitcast(ExtVT, AHi);
18389 RLo = DAG.getBitcast(ExtVT, RLo);
18390 RHi = DAG.getBitcast(ExtVT, RHi);
18392 // r = VSELECT(r, shift(r, 4), a);
18393 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18394 DAG.getConstant(4, dl, ExtVT));
18395 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18396 DAG.getConstant(4, dl, ExtVT));
18397 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18398 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18401 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18402 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18404 // r = VSELECT(r, shift(r, 2), a);
18405 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18406 DAG.getConstant(2, dl, ExtVT));
18407 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18408 DAG.getConstant(2, dl, ExtVT));
18409 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18410 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18413 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18414 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18416 // r = VSELECT(r, shift(r, 1), a);
18417 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18418 DAG.getConstant(1, dl, ExtVT));
18419 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18420 DAG.getConstant(1, dl, ExtVT));
18421 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18422 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18424 // Logical shift the result back to the lower byte, leaving a zero upper
18426 // meaning that we can safely pack with PACKUSWB.
18428 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18430 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18431 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18435 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18436 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18437 // solution better.
18438 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18439 MVT ExtVT = MVT::v8i32;
18441 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18442 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18443 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18444 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18445 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18448 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18449 MVT ExtVT = MVT::v8i32;
18450 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18451 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18452 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18453 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18454 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18455 ALo = DAG.getBitcast(ExtVT, ALo);
18456 AHi = DAG.getBitcast(ExtVT, AHi);
18457 RLo = DAG.getBitcast(ExtVT, RLo);
18458 RHi = DAG.getBitcast(ExtVT, RHi);
18459 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18460 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18461 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18462 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18463 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18466 if (VT == MVT::v8i16) {
18467 unsigned ShiftOpcode = Op->getOpcode();
18469 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18470 // On SSE41 targets we make use of the fact that VSELECT lowers
18471 // to PBLENDVB which selects bytes based just on the sign bit.
18472 if (Subtarget->hasSSE41()) {
18473 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18474 V0 = DAG.getBitcast(ExtVT, V0);
18475 V1 = DAG.getBitcast(ExtVT, V1);
18476 Sel = DAG.getBitcast(ExtVT, Sel);
18477 return DAG.getBitcast(
18478 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18480 // On pre-SSE41 targets we splat the sign bit - a negative value will
18481 // set all bits of the lanes to true and VSELECT uses that in
18482 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18484 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18485 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18488 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18489 if (Subtarget->hasSSE41()) {
18490 // On SSE41 targets we need to replicate the shift mask in both
18491 // bytes for PBLENDVB.
18494 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18495 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18497 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18500 // r = VSELECT(r, shift(r, 8), a);
18501 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18502 R = SignBitSelect(Amt, M, R);
18505 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18507 // r = VSELECT(r, shift(r, 4), a);
18508 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18509 R = SignBitSelect(Amt, M, R);
18512 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18514 // r = VSELECT(r, shift(r, 2), a);
18515 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18516 R = SignBitSelect(Amt, M, R);
18519 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18521 // return VSELECT(r, shift(r, 1), a);
18522 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18523 R = SignBitSelect(Amt, M, R);
18527 // Decompose 256-bit shifts into smaller 128-bit shifts.
18528 if (VT.is256BitVector()) {
18529 unsigned NumElems = VT.getVectorNumElements();
18530 MVT EltVT = VT.getVectorElementType();
18531 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18533 // Extract the two vectors
18534 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18535 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18537 // Recreate the shift amount vectors
18538 SDValue Amt1, Amt2;
18539 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18540 // Constant shift amount
18541 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18542 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18543 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18545 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18546 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18548 // Variable shift amount
18549 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18550 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18553 // Issue new vector shifts for the smaller types
18554 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18555 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18557 // Concatenate the result back
18558 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18564 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18565 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18566 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18567 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18568 // has only one use.
18569 SDNode *N = Op.getNode();
18570 SDValue LHS = N->getOperand(0);
18571 SDValue RHS = N->getOperand(1);
18572 unsigned BaseOp = 0;
18575 switch (Op.getOpcode()) {
18576 default: llvm_unreachable("Unknown ovf instruction!");
18578 // A subtract of one will be selected as a INC. Note that INC doesn't
18579 // set CF, so we can't do this for UADDO.
18580 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18582 BaseOp = X86ISD::INC;
18583 Cond = X86::COND_O;
18586 BaseOp = X86ISD::ADD;
18587 Cond = X86::COND_O;
18590 BaseOp = X86ISD::ADD;
18591 Cond = X86::COND_B;
18594 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18595 // set CF, so we can't do this for USUBO.
18596 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18598 BaseOp = X86ISD::DEC;
18599 Cond = X86::COND_O;
18602 BaseOp = X86ISD::SUB;
18603 Cond = X86::COND_O;
18606 BaseOp = X86ISD::SUB;
18607 Cond = X86::COND_B;
18610 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18611 Cond = X86::COND_O;
18613 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18614 if (N->getValueType(0) == MVT::i8) {
18615 BaseOp = X86ISD::UMUL8;
18616 Cond = X86::COND_O;
18619 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18621 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18624 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18625 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18626 SDValue(Sum.getNode(), 2));
18628 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18632 // Also sets EFLAGS.
18633 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18634 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18637 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18638 DAG.getConstant(Cond, DL, MVT::i32),
18639 SDValue(Sum.getNode(), 1));
18641 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18644 /// Returns true if the operand type is exactly twice the native width, and
18645 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18646 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18647 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18648 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18649 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18652 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18653 else if (OpWidth == 128)
18654 return Subtarget->hasCmpxchg16b();
18659 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18660 return needsCmpXchgNb(SI->getValueOperand()->getType());
18663 // Note: this turns large loads into lock cmpxchg8b/16b.
18664 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18665 TargetLowering::AtomicExpansionKind
18666 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18667 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18668 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18669 : AtomicExpansionKind::None;
18672 TargetLowering::AtomicExpansionKind
18673 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18674 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18675 Type *MemType = AI->getType();
18677 // If the operand is too big, we must see if cmpxchg8/16b is available
18678 // and default to library calls otherwise.
18679 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18680 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18681 : AtomicExpansionKind::None;
18684 AtomicRMWInst::BinOp Op = AI->getOperation();
18687 llvm_unreachable("Unknown atomic operation");
18688 case AtomicRMWInst::Xchg:
18689 case AtomicRMWInst::Add:
18690 case AtomicRMWInst::Sub:
18691 // It's better to use xadd, xsub or xchg for these in all cases.
18692 return AtomicExpansionKind::None;
18693 case AtomicRMWInst::Or:
18694 case AtomicRMWInst::And:
18695 case AtomicRMWInst::Xor:
18696 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18697 // prefix to a normal instruction for these operations.
18698 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18699 : AtomicExpansionKind::None;
18700 case AtomicRMWInst::Nand:
18701 case AtomicRMWInst::Max:
18702 case AtomicRMWInst::Min:
18703 case AtomicRMWInst::UMax:
18704 case AtomicRMWInst::UMin:
18705 // These always require a non-trivial set of data operations on x86. We must
18706 // use a cmpxchg loop.
18707 return AtomicExpansionKind::CmpXChg;
18711 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18712 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18713 // no-sse2). There isn't any reason to disable it if the target processor
18715 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18719 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18720 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18721 Type *MemType = AI->getType();
18722 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18723 // there is no benefit in turning such RMWs into loads, and it is actually
18724 // harmful as it introduces a mfence.
18725 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18728 auto Builder = IRBuilder<>(AI);
18729 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18730 auto SynchScope = AI->getSynchScope();
18731 // We must restrict the ordering to avoid generating loads with Release or
18732 // ReleaseAcquire orderings.
18733 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18734 auto Ptr = AI->getPointerOperand();
18736 // Before the load we need a fence. Here is an example lifted from
18737 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18740 // x.store(1, relaxed);
18741 // r1 = y.fetch_add(0, release);
18743 // y.fetch_add(42, acquire);
18744 // r2 = x.load(relaxed);
18745 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18746 // lowered to just a load without a fence. A mfence flushes the store buffer,
18747 // making the optimization clearly correct.
18748 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18749 // otherwise, we might be able to be more aggressive on relaxed idempotent
18750 // rmw. In practice, they do not look useful, so we don't try to be
18751 // especially clever.
18752 if (SynchScope == SingleThread)
18753 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18754 // the IR level, so we must wrap it in an intrinsic.
18757 if (!hasMFENCE(*Subtarget))
18758 // FIXME: it might make sense to use a locked operation here but on a
18759 // different cache-line to prevent cache-line bouncing. In practice it
18760 // is probably a small win, and x86 processors without mfence are rare
18761 // enough that we do not bother.
18765 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
18766 Builder.CreateCall(MFence, {});
18768 // Finally we can emit the atomic load.
18769 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18770 AI->getType()->getPrimitiveSizeInBits());
18771 Loaded->setAtomic(Order, SynchScope);
18772 AI->replaceAllUsesWith(Loaded);
18773 AI->eraseFromParent();
18777 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18778 SelectionDAG &DAG) {
18780 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18781 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18782 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18783 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18785 // The only fence that needs an instruction is a sequentially-consistent
18786 // cross-thread fence.
18787 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18788 if (hasMFENCE(*Subtarget))
18789 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18791 SDValue Chain = Op.getOperand(0);
18792 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
18794 DAG.getRegister(X86::ESP, MVT::i32), // Base
18795 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
18796 DAG.getRegister(0, MVT::i32), // Index
18797 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
18798 DAG.getRegister(0, MVT::i32), // Segment.
18802 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18803 return SDValue(Res, 0);
18806 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18807 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18810 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18811 SelectionDAG &DAG) {
18812 MVT T = Op.getSimpleValueType();
18816 switch(T.SimpleTy) {
18817 default: llvm_unreachable("Invalid value type!");
18818 case MVT::i8: Reg = X86::AL; size = 1; break;
18819 case MVT::i16: Reg = X86::AX; size = 2; break;
18820 case MVT::i32: Reg = X86::EAX; size = 4; break;
18822 assert(Subtarget->is64Bit() && "Node not type legal!");
18823 Reg = X86::RAX; size = 8;
18826 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18827 Op.getOperand(2), SDValue());
18828 SDValue Ops[] = { cpIn.getValue(0),
18831 DAG.getTargetConstant(size, DL, MVT::i8),
18832 cpIn.getValue(1) };
18833 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18834 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18835 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18839 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18840 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18841 MVT::i32, cpOut.getValue(2));
18842 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18843 DAG.getConstant(X86::COND_E, DL, MVT::i8),
18846 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18847 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18848 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18852 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18853 SelectionDAG &DAG) {
18854 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18855 MVT DstVT = Op.getSimpleValueType();
18857 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18858 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18859 if (DstVT != MVT::f64)
18860 // This conversion needs to be expanded.
18863 SDValue InVec = Op->getOperand(0);
18865 unsigned NumElts = SrcVT.getVectorNumElements();
18866 EVT SVT = SrcVT.getVectorElementType();
18868 // Widen the vector in input in the case of MVT::v2i32.
18869 // Example: from MVT::v2i32 to MVT::v4i32.
18870 SmallVector<SDValue, 16> Elts;
18871 for (unsigned i = 0, e = NumElts; i != e; ++i)
18872 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18873 DAG.getIntPtrConstant(i, dl)));
18875 // Explicitly mark the extra elements as Undef.
18876 Elts.append(NumElts, DAG.getUNDEF(SVT));
18878 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18879 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18880 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
18881 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18882 DAG.getIntPtrConstant(0, dl));
18885 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18886 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18887 assert((DstVT == MVT::i64 ||
18888 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18889 "Unexpected custom BITCAST");
18890 // i64 <=> MMX conversions are Legal.
18891 if (SrcVT==MVT::i64 && DstVT.isVector())
18893 if (DstVT==MVT::i64 && SrcVT.isVector())
18895 // MMX <=> MMX conversions are Legal.
18896 if (SrcVT.isVector() && DstVT.isVector())
18898 // All other conversions need to be expanded.
18902 /// Compute the horizontal sum of bytes in V for the elements of VT.
18904 /// Requires V to be a byte vector and VT to be an integer vector type with
18905 /// wider elements than V's type. The width of the elements of VT determines
18906 /// how many bytes of V are summed horizontally to produce each element of the
18908 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
18909 const X86Subtarget *Subtarget,
18910 SelectionDAG &DAG) {
18912 MVT ByteVecVT = V.getSimpleValueType();
18913 MVT EltVT = VT.getVectorElementType();
18914 int NumElts = VT.getVectorNumElements();
18915 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
18916 "Expected value to have byte element type.");
18917 assert(EltVT != MVT::i8 &&
18918 "Horizontal byte sum only makes sense for wider elements!");
18919 unsigned VecSize = VT.getSizeInBits();
18920 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
18922 // PSADBW instruction horizontally add all bytes and leave the result in i64
18923 // chunks, thus directly computes the pop count for v2i64 and v4i64.
18924 if (EltVT == MVT::i64) {
18925 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18926 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
18927 return DAG.getBitcast(VT, V);
18930 if (EltVT == MVT::i32) {
18931 // We unpack the low half and high half into i32s interleaved with zeros so
18932 // that we can use PSADBW to horizontally sum them. The most useful part of
18933 // this is that it lines up the results of two PSADBW instructions to be
18934 // two v2i64 vectors which concatenated are the 4 population counts. We can
18935 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
18936 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
18937 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
18938 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
18940 // Do the horizontal sums into two v2i64s.
18941 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18942 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18943 DAG.getBitcast(ByteVecVT, Low), Zeros);
18944 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18945 DAG.getBitcast(ByteVecVT, High), Zeros);
18947 // Merge them together.
18948 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
18949 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
18950 DAG.getBitcast(ShortVecVT, Low),
18951 DAG.getBitcast(ShortVecVT, High));
18953 return DAG.getBitcast(VT, V);
18956 // The only element type left is i16.
18957 assert(EltVT == MVT::i16 && "Unknown how to handle type");
18959 // To obtain pop count for each i16 element starting from the pop count for
18960 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
18961 // right by 8. It is important to shift as i16s as i8 vector shift isn't
18962 // directly supported.
18963 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
18964 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
18965 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18966 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
18967 DAG.getBitcast(ByteVecVT, V));
18968 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18971 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
18972 const X86Subtarget *Subtarget,
18973 SelectionDAG &DAG) {
18974 MVT VT = Op.getSimpleValueType();
18975 MVT EltVT = VT.getVectorElementType();
18976 unsigned VecSize = VT.getSizeInBits();
18978 // Implement a lookup table in register by using an algorithm based on:
18979 // http://wm.ite.pl/articles/sse-popcount.html
18981 // The general idea is that every lower byte nibble in the input vector is an
18982 // index into a in-register pre-computed pop count table. We then split up the
18983 // input vector in two new ones: (1) a vector with only the shifted-right
18984 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
18985 // masked out higher ones) for each byte. PSHUB is used separately with both
18986 // to index the in-register table. Next, both are added and the result is a
18987 // i8 vector where each element contains the pop count for input byte.
18989 // To obtain the pop count for elements != i8, we follow up with the same
18990 // approach and use additional tricks as described below.
18992 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
18993 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
18994 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
18995 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
18997 int NumByteElts = VecSize / 8;
18998 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
18999 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19000 SmallVector<SDValue, 16> LUTVec;
19001 for (int i = 0; i < NumByteElts; ++i)
19002 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19003 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19004 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19005 DAG.getConstant(0x0F, DL, MVT::i8));
19006 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19009 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19010 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19011 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19014 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19016 // The input vector is used as the shuffle mask that index elements into the
19017 // LUT. After counting low and high nibbles, add the vector to obtain the
19018 // final pop count per i8 element.
19019 SDValue HighPopCnt =
19020 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19021 SDValue LowPopCnt =
19022 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19023 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19025 if (EltVT == MVT::i8)
19028 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19031 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19032 const X86Subtarget *Subtarget,
19033 SelectionDAG &DAG) {
19034 MVT VT = Op.getSimpleValueType();
19035 assert(VT.is128BitVector() &&
19036 "Only 128-bit vector bitmath lowering supported.");
19038 int VecSize = VT.getSizeInBits();
19039 MVT EltVT = VT.getVectorElementType();
19040 int Len = EltVT.getSizeInBits();
19042 // This is the vectorized version of the "best" algorithm from
19043 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19044 // with a minor tweak to use a series of adds + shifts instead of vector
19045 // multiplications. Implemented for all integer vector types. We only use
19046 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19047 // much faster, even faster than using native popcnt instructions.
19049 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19050 MVT VT = V.getSimpleValueType();
19051 SmallVector<SDValue, 32> Shifters(
19052 VT.getVectorNumElements(),
19053 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19054 return DAG.getNode(OpCode, DL, VT, V,
19055 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19057 auto GetMask = [&](SDValue V, APInt Mask) {
19058 MVT VT = V.getSimpleValueType();
19059 SmallVector<SDValue, 32> Masks(
19060 VT.getVectorNumElements(),
19061 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19062 return DAG.getNode(ISD::AND, DL, VT, V,
19063 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19066 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19067 // x86, so set the SRL type to have elements at least i16 wide. This is
19068 // correct because all of our SRLs are followed immediately by a mask anyways
19069 // that handles any bits that sneak into the high bits of the byte elements.
19070 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19074 // v = v - ((v >> 1) & 0x55555555...)
19076 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19077 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19078 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19080 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19081 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19082 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19083 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19084 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19086 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19087 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19088 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19089 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19091 // At this point, V contains the byte-wise population count, and we are
19092 // merely doing a horizontal sum if necessary to get the wider element
19094 if (EltVT == MVT::i8)
19097 return LowerHorizontalByteSum(
19098 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19102 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19103 SelectionDAG &DAG) {
19104 MVT VT = Op.getSimpleValueType();
19105 // FIXME: Need to add AVX-512 support here!
19106 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19107 "Unknown CTPOP type to handle");
19108 SDLoc DL(Op.getNode());
19109 SDValue Op0 = Op.getOperand(0);
19111 if (!Subtarget->hasSSSE3()) {
19112 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19113 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19114 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19117 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19118 unsigned NumElems = VT.getVectorNumElements();
19120 // Extract each 128-bit vector, compute pop count and concat the result.
19121 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19122 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19124 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19125 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19126 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19129 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19132 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19133 SelectionDAG &DAG) {
19134 assert(Op.getValueType().isVector() &&
19135 "We only do custom lowering for vector population count.");
19136 return LowerVectorCTPOP(Op, Subtarget, DAG);
19139 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19140 SDNode *Node = Op.getNode();
19142 EVT T = Node->getValueType(0);
19143 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19144 DAG.getConstant(0, dl, T), Node->getOperand(2));
19145 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19146 cast<AtomicSDNode>(Node)->getMemoryVT(),
19147 Node->getOperand(0),
19148 Node->getOperand(1), negOp,
19149 cast<AtomicSDNode>(Node)->getMemOperand(),
19150 cast<AtomicSDNode>(Node)->getOrdering(),
19151 cast<AtomicSDNode>(Node)->getSynchScope());
19154 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19155 SDNode *Node = Op.getNode();
19157 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19159 // Convert seq_cst store -> xchg
19160 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19161 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19162 // (The only way to get a 16-byte store is cmpxchg16b)
19163 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19164 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19165 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19166 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19167 cast<AtomicSDNode>(Node)->getMemoryVT(),
19168 Node->getOperand(0),
19169 Node->getOperand(1), Node->getOperand(2),
19170 cast<AtomicSDNode>(Node)->getMemOperand(),
19171 cast<AtomicSDNode>(Node)->getOrdering(),
19172 cast<AtomicSDNode>(Node)->getSynchScope());
19173 return Swap.getValue(1);
19175 // Other atomic stores have a simple pattern.
19179 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19180 EVT VT = Op.getNode()->getSimpleValueType(0);
19182 // Let legalize expand this if it isn't a legal type yet.
19183 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19186 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19189 bool ExtraOp = false;
19190 switch (Op.getOpcode()) {
19191 default: llvm_unreachable("Invalid code");
19192 case ISD::ADDC: Opc = X86ISD::ADD; break;
19193 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19194 case ISD::SUBC: Opc = X86ISD::SUB; break;
19195 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19199 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19201 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19202 Op.getOperand(1), Op.getOperand(2));
19205 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19206 SelectionDAG &DAG) {
19207 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19209 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19210 // which returns the values as { float, float } (in XMM0) or
19211 // { double, double } (which is returned in XMM0, XMM1).
19213 SDValue Arg = Op.getOperand(0);
19214 EVT ArgVT = Arg.getValueType();
19215 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19217 TargetLowering::ArgListTy Args;
19218 TargetLowering::ArgListEntry Entry;
19222 Entry.isSExt = false;
19223 Entry.isZExt = false;
19224 Args.push_back(Entry);
19226 bool isF64 = ArgVT == MVT::f64;
19227 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19228 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19229 // the results are returned via SRet in memory.
19230 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19231 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19233 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19235 Type *RetTy = isF64
19236 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19237 : (Type*)VectorType::get(ArgTy, 4);
19239 TargetLowering::CallLoweringInfo CLI(DAG);
19240 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19241 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19243 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19246 // Returned in xmm0 and xmm1.
19247 return CallResult.first;
19249 // Returned in bits 0:31 and 32:64 xmm0.
19250 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19251 CallResult.first, DAG.getIntPtrConstant(0, dl));
19252 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19253 CallResult.first, DAG.getIntPtrConstant(1, dl));
19254 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19255 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19258 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19259 SelectionDAG &DAG) {
19260 assert(Subtarget->hasAVX512() &&
19261 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19263 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19264 EVT VT = N->getValue().getValueType();
19265 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19268 // X86 scatter kills mask register, so its type should be added to
19269 // the list of return values
19270 if (N->getNumValues() == 1) {
19271 SDValue Index = N->getIndex();
19272 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19273 !Index.getValueType().is512BitVector())
19274 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19276 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19277 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19278 N->getOperand(3), Index };
19280 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19281 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19282 return SDValue(NewScatter.getNode(), 0);
19287 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19288 SelectionDAG &DAG) {
19289 assert(Subtarget->hasAVX512() &&
19290 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19292 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19293 EVT VT = Op.getValueType();
19294 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19297 SDValue Index = N->getIndex();
19298 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19299 !Index.getValueType().is512BitVector()) {
19300 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19301 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19302 N->getOperand(3), Index };
19303 DAG.UpdateNodeOperands(N, Ops);
19308 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19309 SelectionDAG &DAG) const {
19310 // TODO: Eventually, the lowering of these nodes should be informed by or
19311 // deferred to the GC strategy for the function in which they appear. For
19312 // now, however, they must be lowered to something. Since they are logically
19313 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19314 // require special handling for these nodes), lower them as literal NOOPs for
19316 SmallVector<SDValue, 2> Ops;
19318 Ops.push_back(Op.getOperand(0));
19319 if (Op->getGluedNode())
19320 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19323 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19324 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19329 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19330 SelectionDAG &DAG) const {
19331 // TODO: Eventually, the lowering of these nodes should be informed by or
19332 // deferred to the GC strategy for the function in which they appear. For
19333 // now, however, they must be lowered to something. Since they are logically
19334 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19335 // require special handling for these nodes), lower them as literal NOOPs for
19337 SmallVector<SDValue, 2> Ops;
19339 Ops.push_back(Op.getOperand(0));
19340 if (Op->getGluedNode())
19341 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19344 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19345 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19350 /// LowerOperation - Provide custom lowering hooks for some operations.
19352 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19353 switch (Op.getOpcode()) {
19354 default: llvm_unreachable("Should not custom lower this!");
19355 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19356 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19357 return LowerCMP_SWAP(Op, Subtarget, DAG);
19358 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19359 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19360 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19361 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19362 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19363 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19364 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19365 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19366 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19367 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19368 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19369 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19370 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19371 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19372 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19373 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19374 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19375 case ISD::SHL_PARTS:
19376 case ISD::SRA_PARTS:
19377 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19378 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19379 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19380 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19381 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19382 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19383 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19384 case ISD::SIGN_EXTEND_VECTOR_INREG:
19385 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19386 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19387 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19388 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19389 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19391 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19392 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19393 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19394 case ISD::SETCC: return LowerSETCC(Op, DAG);
19395 case ISD::SELECT: return LowerSELECT(Op, DAG);
19396 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19397 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19398 case ISD::VASTART: return LowerVASTART(Op, DAG);
19399 case ISD::VAARG: return LowerVAARG(Op, DAG);
19400 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19401 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19402 case ISD::INTRINSIC_VOID:
19403 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19404 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19405 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19406 case ISD::FRAME_TO_ARGS_OFFSET:
19407 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19408 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19409 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19410 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19411 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19412 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19413 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19414 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19415 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19416 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19418 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19419 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19420 case ISD::UMUL_LOHI:
19421 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19424 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19430 case ISD::UMULO: return LowerXALUO(Op, DAG);
19431 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19432 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19436 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19437 case ISD::ADD: return LowerADD(Op, DAG);
19438 case ISD::SUB: return LowerSUB(Op, DAG);
19442 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19443 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19444 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19445 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19446 case ISD::GC_TRANSITION_START:
19447 return LowerGC_TRANSITION_START(Op, DAG);
19448 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19452 /// ReplaceNodeResults - Replace a node with an illegal result type
19453 /// with a new node built out of custom code.
19454 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19455 SmallVectorImpl<SDValue>&Results,
19456 SelectionDAG &DAG) const {
19458 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19459 switch (N->getOpcode()) {
19461 llvm_unreachable("Do not know how to custom type legalize this operation!");
19462 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19463 case X86ISD::FMINC:
19465 case X86ISD::FMAXC:
19466 case X86ISD::FMAX: {
19467 EVT VT = N->getValueType(0);
19468 if (VT != MVT::v2f32)
19469 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19470 SDValue UNDEF = DAG.getUNDEF(VT);
19471 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19472 N->getOperand(0), UNDEF);
19473 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19474 N->getOperand(1), UNDEF);
19475 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19478 case ISD::SIGN_EXTEND_INREG:
19483 // We don't want to expand or promote these.
19490 case ISD::UDIVREM: {
19491 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19492 Results.push_back(V);
19495 case ISD::FP_TO_SINT:
19496 case ISD::FP_TO_UINT: {
19497 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19499 std::pair<SDValue,SDValue> Vals =
19500 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19501 SDValue FIST = Vals.first, StackSlot = Vals.second;
19502 if (FIST.getNode()) {
19503 EVT VT = N->getValueType(0);
19504 // Return a load from the stack slot.
19505 if (StackSlot.getNode())
19506 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19507 MachinePointerInfo(),
19508 false, false, false, 0));
19510 Results.push_back(FIST);
19514 case ISD::UINT_TO_FP: {
19515 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19516 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19517 N->getValueType(0) != MVT::v2f32)
19519 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19521 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19523 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19524 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19525 DAG.getBitcast(MVT::v2i64, VBias));
19526 Or = DAG.getBitcast(MVT::v2f64, Or);
19527 // TODO: Are there any fast-math-flags to propagate here?
19528 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19529 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19532 case ISD::FP_ROUND: {
19533 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19535 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19536 Results.push_back(V);
19539 case ISD::FP_EXTEND: {
19540 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19541 // No other ValueType for FP_EXTEND should reach this point.
19542 assert(N->getValueType(0) == MVT::v2f32 &&
19543 "Do not know how to legalize this Node");
19546 case ISD::INTRINSIC_W_CHAIN: {
19547 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19549 default : llvm_unreachable("Do not know how to custom type "
19550 "legalize this intrinsic operation!");
19551 case Intrinsic::x86_rdtsc:
19552 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19554 case Intrinsic::x86_rdtscp:
19555 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19557 case Intrinsic::x86_rdpmc:
19558 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19561 case ISD::READCYCLECOUNTER: {
19562 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19565 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19566 EVT T = N->getValueType(0);
19567 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19568 bool Regs64bit = T == MVT::i128;
19569 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19570 SDValue cpInL, cpInH;
19571 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19572 DAG.getConstant(0, dl, HalfT));
19573 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19574 DAG.getConstant(1, dl, HalfT));
19575 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19576 Regs64bit ? X86::RAX : X86::EAX,
19578 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19579 Regs64bit ? X86::RDX : X86::EDX,
19580 cpInH, cpInL.getValue(1));
19581 SDValue swapInL, swapInH;
19582 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19583 DAG.getConstant(0, dl, HalfT));
19584 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19585 DAG.getConstant(1, dl, HalfT));
19586 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19587 Regs64bit ? X86::RBX : X86::EBX,
19588 swapInL, cpInH.getValue(1));
19589 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19590 Regs64bit ? X86::RCX : X86::ECX,
19591 swapInH, swapInL.getValue(1));
19592 SDValue Ops[] = { swapInH.getValue(0),
19594 swapInH.getValue(1) };
19595 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19596 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19597 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19598 X86ISD::LCMPXCHG8_DAG;
19599 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19600 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19601 Regs64bit ? X86::RAX : X86::EAX,
19602 HalfT, Result.getValue(1));
19603 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19604 Regs64bit ? X86::RDX : X86::EDX,
19605 HalfT, cpOutL.getValue(2));
19606 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19608 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19609 MVT::i32, cpOutH.getValue(2));
19611 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19612 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19613 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19615 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19616 Results.push_back(Success);
19617 Results.push_back(EFLAGS.getValue(1));
19620 case ISD::ATOMIC_SWAP:
19621 case ISD::ATOMIC_LOAD_ADD:
19622 case ISD::ATOMIC_LOAD_SUB:
19623 case ISD::ATOMIC_LOAD_AND:
19624 case ISD::ATOMIC_LOAD_OR:
19625 case ISD::ATOMIC_LOAD_XOR:
19626 case ISD::ATOMIC_LOAD_NAND:
19627 case ISD::ATOMIC_LOAD_MIN:
19628 case ISD::ATOMIC_LOAD_MAX:
19629 case ISD::ATOMIC_LOAD_UMIN:
19630 case ISD::ATOMIC_LOAD_UMAX:
19631 case ISD::ATOMIC_LOAD: {
19632 // Delegate to generic TypeLegalization. Situations we can really handle
19633 // should have already been dealt with by AtomicExpandPass.cpp.
19636 case ISD::BITCAST: {
19637 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19638 EVT DstVT = N->getValueType(0);
19639 EVT SrcVT = N->getOperand(0)->getValueType(0);
19641 if (SrcVT != MVT::f64 ||
19642 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19645 unsigned NumElts = DstVT.getVectorNumElements();
19646 EVT SVT = DstVT.getVectorElementType();
19647 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19648 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19649 MVT::v2f64, N->getOperand(0));
19650 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19652 if (ExperimentalVectorWideningLegalization) {
19653 // If we are legalizing vectors by widening, we already have the desired
19654 // legal vector type, just return it.
19655 Results.push_back(ToVecInt);
19659 SmallVector<SDValue, 8> Elts;
19660 for (unsigned i = 0, e = NumElts; i != e; ++i)
19661 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19662 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19664 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19669 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19670 switch ((X86ISD::NodeType)Opcode) {
19671 case X86ISD::FIRST_NUMBER: break;
19672 case X86ISD::BSF: return "X86ISD::BSF";
19673 case X86ISD::BSR: return "X86ISD::BSR";
19674 case X86ISD::SHLD: return "X86ISD::SHLD";
19675 case X86ISD::SHRD: return "X86ISD::SHRD";
19676 case X86ISD::FAND: return "X86ISD::FAND";
19677 case X86ISD::FANDN: return "X86ISD::FANDN";
19678 case X86ISD::FOR: return "X86ISD::FOR";
19679 case X86ISD::FXOR: return "X86ISD::FXOR";
19680 case X86ISD::FILD: return "X86ISD::FILD";
19681 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19682 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19683 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19684 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19685 case X86ISD::FLD: return "X86ISD::FLD";
19686 case X86ISD::FST: return "X86ISD::FST";
19687 case X86ISD::CALL: return "X86ISD::CALL";
19688 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19689 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19690 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19691 case X86ISD::BT: return "X86ISD::BT";
19692 case X86ISD::CMP: return "X86ISD::CMP";
19693 case X86ISD::COMI: return "X86ISD::COMI";
19694 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19695 case X86ISD::CMPM: return "X86ISD::CMPM";
19696 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19697 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19698 case X86ISD::SETCC: return "X86ISD::SETCC";
19699 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19700 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19701 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19702 case X86ISD::CMOV: return "X86ISD::CMOV";
19703 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19704 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19705 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19706 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19707 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19708 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19709 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19710 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19711 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19712 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19713 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19714 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19715 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19716 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19717 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19718 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19719 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19720 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19721 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19722 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19723 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19724 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19725 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19726 case X86ISD::HADD: return "X86ISD::HADD";
19727 case X86ISD::HSUB: return "X86ISD::HSUB";
19728 case X86ISD::FHADD: return "X86ISD::FHADD";
19729 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19730 case X86ISD::ABS: return "X86ISD::ABS";
19731 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19732 case X86ISD::FMAX: return "X86ISD::FMAX";
19733 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19734 case X86ISD::FMIN: return "X86ISD::FMIN";
19735 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19736 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19737 case X86ISD::FMINC: return "X86ISD::FMINC";
19738 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19739 case X86ISD::FRCP: return "X86ISD::FRCP";
19740 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19741 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19742 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19743 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19744 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19745 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19746 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19747 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19748 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19749 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19750 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19751 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19752 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19753 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19754 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19755 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19756 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19757 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19758 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19759 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19760 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19761 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19762 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19763 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19764 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
19765 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
19766 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19767 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19768 case X86ISD::VSHL: return "X86ISD::VSHL";
19769 case X86ISD::VSRL: return "X86ISD::VSRL";
19770 case X86ISD::VSRA: return "X86ISD::VSRA";
19771 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19772 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19773 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19774 case X86ISD::CMPP: return "X86ISD::CMPP";
19775 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19776 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19777 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19778 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19779 case X86ISD::ADD: return "X86ISD::ADD";
19780 case X86ISD::SUB: return "X86ISD::SUB";
19781 case X86ISD::ADC: return "X86ISD::ADC";
19782 case X86ISD::SBB: return "X86ISD::SBB";
19783 case X86ISD::SMUL: return "X86ISD::SMUL";
19784 case X86ISD::UMUL: return "X86ISD::UMUL";
19785 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19786 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19787 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19788 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19789 case X86ISD::INC: return "X86ISD::INC";
19790 case X86ISD::DEC: return "X86ISD::DEC";
19791 case X86ISD::OR: return "X86ISD::OR";
19792 case X86ISD::XOR: return "X86ISD::XOR";
19793 case X86ISD::AND: return "X86ISD::AND";
19794 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19795 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19796 case X86ISD::PTEST: return "X86ISD::PTEST";
19797 case X86ISD::TESTP: return "X86ISD::TESTP";
19798 case X86ISD::TESTM: return "X86ISD::TESTM";
19799 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19800 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19801 case X86ISD::KTEST: return "X86ISD::KTEST";
19802 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19803 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19804 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19805 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19806 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19807 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19808 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19809 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19810 case X86ISD::SHUF128: return "X86ISD::SHUF128";
19811 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19812 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19813 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19814 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19815 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19816 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19817 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19818 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19819 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19820 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19821 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19822 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19823 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19824 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
19825 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19826 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
19827 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19828 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19829 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19830 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19831 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19832 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19833 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
19834 case X86ISD::VRANGE: return "X86ISD::VRANGE";
19835 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19836 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19837 case X86ISD::PSADBW: return "X86ISD::PSADBW";
19838 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
19839 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19840 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19841 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19842 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19843 case X86ISD::MFENCE: return "X86ISD::MFENCE";
19844 case X86ISD::SFENCE: return "X86ISD::SFENCE";
19845 case X86ISD::LFENCE: return "X86ISD::LFENCE";
19846 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19847 case X86ISD::SAHF: return "X86ISD::SAHF";
19848 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19849 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19850 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
19851 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
19852 case X86ISD::VPSHA: return "X86ISD::VPSHA";
19853 case X86ISD::VPSHL: return "X86ISD::VPSHL";
19854 case X86ISD::FMADD: return "X86ISD::FMADD";
19855 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19856 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19857 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19858 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19859 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19860 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
19861 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
19862 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
19863 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
19864 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
19865 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
19866 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
19867 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
19868 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
19869 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19870 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19871 case X86ISD::XTEST: return "X86ISD::XTEST";
19872 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19873 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19874 case X86ISD::SELECT: return "X86ISD::SELECT";
19875 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
19876 case X86ISD::RCP28: return "X86ISD::RCP28";
19877 case X86ISD::EXP2: return "X86ISD::EXP2";
19878 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
19879 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
19880 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
19881 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
19882 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
19883 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
19884 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
19885 case X86ISD::SCALEF: return "X86ISD::SCALEF";
19886 case X86ISD::ADDS: return "X86ISD::ADDS";
19887 case X86ISD::SUBS: return "X86ISD::SUBS";
19888 case X86ISD::AVG: return "X86ISD::AVG";
19889 case X86ISD::MULHRS: return "X86ISD::MULHRS";
19890 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
19891 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
19892 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
19893 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
19894 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
19899 // isLegalAddressingMode - Return true if the addressing mode represented
19900 // by AM is legal for this target, for a load/store of the specified type.
19901 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
19902 const AddrMode &AM, Type *Ty,
19903 unsigned AS) const {
19904 // X86 supports extremely general addressing modes.
19905 CodeModel::Model M = getTargetMachine().getCodeModel();
19906 Reloc::Model R = getTargetMachine().getRelocationModel();
19908 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19909 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19914 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19916 // If a reference to this global requires an extra load, we can't fold it.
19917 if (isGlobalStubReference(GVFlags))
19920 // If BaseGV requires a register for the PIC base, we cannot also have a
19921 // BaseReg specified.
19922 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19925 // If lower 4G is not available, then we must use rip-relative addressing.
19926 if ((M != CodeModel::Small || R != Reloc::Static) &&
19927 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19931 switch (AM.Scale) {
19937 // These scales always work.
19942 // These scales are formed with basereg+scalereg. Only accept if there is
19947 default: // Other stuff never works.
19954 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19955 unsigned Bits = Ty->getScalarSizeInBits();
19957 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19958 // particularly cheaper than those without.
19962 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19963 // variable shifts just as cheap as scalar ones.
19964 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19967 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19968 // fully general vector.
19972 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19973 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19975 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19976 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19977 return NumBits1 > NumBits2;
19980 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19981 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19984 if (!isTypeLegal(EVT::getEVT(Ty1)))
19987 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19989 // Assuming the caller doesn't have a zeroext or signext return parameter,
19990 // truncation all the way down to i1 is valid.
19994 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19995 return isInt<32>(Imm);
19998 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19999 // Can also use sub to handle negated immediates.
20000 return isInt<32>(Imm);
20003 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20004 if (!VT1.isInteger() || !VT2.isInteger())
20006 unsigned NumBits1 = VT1.getSizeInBits();
20007 unsigned NumBits2 = VT2.getSizeInBits();
20008 return NumBits1 > NumBits2;
20011 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20012 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20013 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20016 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20017 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20018 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20021 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20022 EVT VT1 = Val.getValueType();
20023 if (isZExtFree(VT1, VT2))
20026 if (Val.getOpcode() != ISD::LOAD)
20029 if (!VT1.isSimple() || !VT1.isInteger() ||
20030 !VT2.isSimple() || !VT2.isInteger())
20033 switch (VT1.getSimpleVT().SimpleTy) {
20038 // X86 has 8, 16, and 32-bit zero-extending loads.
20045 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20048 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20049 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20052 VT = VT.getScalarType();
20054 if (!VT.isSimple())
20057 switch (VT.getSimpleVT().SimpleTy) {
20068 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20069 // i16 instructions are longer (0x66 prefix) and potentially slower.
20070 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20073 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20074 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20075 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20076 /// are assumed to be legal.
20078 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20080 if (!VT.isSimple())
20083 // Not for i1 vectors
20084 if (VT.getScalarType() == MVT::i1)
20087 // Very little shuffling can be done for 64-bit vectors right now.
20088 if (VT.getSizeInBits() == 64)
20091 // We only care that the types being shuffled are legal. The lowering can
20092 // handle any possible shuffle mask that results.
20093 return isTypeLegal(VT.getSimpleVT());
20097 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20099 // Just delegate to the generic legality, clear masks aren't special.
20100 return isShuffleMaskLegal(Mask, VT);
20103 //===----------------------------------------------------------------------===//
20104 // X86 Scheduler Hooks
20105 //===----------------------------------------------------------------------===//
20107 /// Utility function to emit xbegin specifying the start of an RTM region.
20108 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20109 const TargetInstrInfo *TII) {
20110 DebugLoc DL = MI->getDebugLoc();
20112 const BasicBlock *BB = MBB->getBasicBlock();
20113 MachineFunction::iterator I = MBB;
20116 // For the v = xbegin(), we generate
20127 MachineBasicBlock *thisMBB = MBB;
20128 MachineFunction *MF = MBB->getParent();
20129 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20130 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20131 MF->insert(I, mainMBB);
20132 MF->insert(I, sinkMBB);
20134 // Transfer the remainder of BB and its successor edges to sinkMBB.
20135 sinkMBB->splice(sinkMBB->begin(), MBB,
20136 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20137 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20141 // # fallthrough to mainMBB
20142 // # abortion to sinkMBB
20143 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20144 thisMBB->addSuccessor(mainMBB);
20145 thisMBB->addSuccessor(sinkMBB);
20149 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20150 mainMBB->addSuccessor(sinkMBB);
20153 // EAX is live into the sinkMBB
20154 sinkMBB->addLiveIn(X86::EAX);
20155 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20156 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20159 MI->eraseFromParent();
20163 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20164 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20165 // in the .td file.
20166 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20167 const TargetInstrInfo *TII) {
20169 switch (MI->getOpcode()) {
20170 default: llvm_unreachable("illegal opcode!");
20171 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20172 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20173 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20174 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20175 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20176 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20177 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20178 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20181 DebugLoc dl = MI->getDebugLoc();
20182 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20184 unsigned NumArgs = MI->getNumOperands();
20185 for (unsigned i = 1; i < NumArgs; ++i) {
20186 MachineOperand &Op = MI->getOperand(i);
20187 if (!(Op.isReg() && Op.isImplicit()))
20188 MIB.addOperand(Op);
20190 if (MI->hasOneMemOperand())
20191 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20193 BuildMI(*BB, MI, dl,
20194 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20195 .addReg(X86::XMM0);
20197 MI->eraseFromParent();
20201 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20202 // defs in an instruction pattern
20203 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20204 const TargetInstrInfo *TII) {
20206 switch (MI->getOpcode()) {
20207 default: llvm_unreachable("illegal opcode!");
20208 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20209 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20210 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20211 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20212 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20213 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20214 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20215 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20218 DebugLoc dl = MI->getDebugLoc();
20219 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20221 unsigned NumArgs = MI->getNumOperands(); // remove the results
20222 for (unsigned i = 1; i < NumArgs; ++i) {
20223 MachineOperand &Op = MI->getOperand(i);
20224 if (!(Op.isReg() && Op.isImplicit()))
20225 MIB.addOperand(Op);
20227 if (MI->hasOneMemOperand())
20228 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20230 BuildMI(*BB, MI, dl,
20231 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20234 MI->eraseFromParent();
20238 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20239 const X86Subtarget *Subtarget) {
20240 DebugLoc dl = MI->getDebugLoc();
20241 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20242 // Address into RAX/EAX, other two args into ECX, EDX.
20243 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20244 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20245 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20246 for (int i = 0; i < X86::AddrNumOperands; ++i)
20247 MIB.addOperand(MI->getOperand(i));
20249 unsigned ValOps = X86::AddrNumOperands;
20250 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20251 .addReg(MI->getOperand(ValOps).getReg());
20252 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20253 .addReg(MI->getOperand(ValOps+1).getReg());
20255 // The instruction doesn't actually take any operands though.
20256 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20258 MI->eraseFromParent(); // The pseudo is gone now.
20262 MachineBasicBlock *
20263 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20264 MachineBasicBlock *MBB) const {
20265 // Emit va_arg instruction on X86-64.
20267 // Operands to this pseudo-instruction:
20268 // 0 ) Output : destination address (reg)
20269 // 1-5) Input : va_list address (addr, i64mem)
20270 // 6 ) ArgSize : Size (in bytes) of vararg type
20271 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20272 // 8 ) Align : Alignment of type
20273 // 9 ) EFLAGS (implicit-def)
20275 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20276 static_assert(X86::AddrNumOperands == 5,
20277 "VAARG_64 assumes 5 address operands");
20279 unsigned DestReg = MI->getOperand(0).getReg();
20280 MachineOperand &Base = MI->getOperand(1);
20281 MachineOperand &Scale = MI->getOperand(2);
20282 MachineOperand &Index = MI->getOperand(3);
20283 MachineOperand &Disp = MI->getOperand(4);
20284 MachineOperand &Segment = MI->getOperand(5);
20285 unsigned ArgSize = MI->getOperand(6).getImm();
20286 unsigned ArgMode = MI->getOperand(7).getImm();
20287 unsigned Align = MI->getOperand(8).getImm();
20289 // Memory Reference
20290 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20291 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20292 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20294 // Machine Information
20295 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20296 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20297 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20298 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20299 DebugLoc DL = MI->getDebugLoc();
20301 // struct va_list {
20304 // i64 overflow_area (address)
20305 // i64 reg_save_area (address)
20307 // sizeof(va_list) = 24
20308 // alignment(va_list) = 8
20310 unsigned TotalNumIntRegs = 6;
20311 unsigned TotalNumXMMRegs = 8;
20312 bool UseGPOffset = (ArgMode == 1);
20313 bool UseFPOffset = (ArgMode == 2);
20314 unsigned MaxOffset = TotalNumIntRegs * 8 +
20315 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20317 /* Align ArgSize to a multiple of 8 */
20318 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20319 bool NeedsAlign = (Align > 8);
20321 MachineBasicBlock *thisMBB = MBB;
20322 MachineBasicBlock *overflowMBB;
20323 MachineBasicBlock *offsetMBB;
20324 MachineBasicBlock *endMBB;
20326 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20327 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20328 unsigned OffsetReg = 0;
20330 if (!UseGPOffset && !UseFPOffset) {
20331 // If we only pull from the overflow region, we don't create a branch.
20332 // We don't need to alter control flow.
20333 OffsetDestReg = 0; // unused
20334 OverflowDestReg = DestReg;
20336 offsetMBB = nullptr;
20337 overflowMBB = thisMBB;
20340 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20341 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20342 // If not, pull from overflow_area. (branch to overflowMBB)
20347 // offsetMBB overflowMBB
20352 // Registers for the PHI in endMBB
20353 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20354 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20356 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20357 MachineFunction *MF = MBB->getParent();
20358 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20359 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20360 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20362 MachineFunction::iterator MBBIter = MBB;
20365 // Insert the new basic blocks
20366 MF->insert(MBBIter, offsetMBB);
20367 MF->insert(MBBIter, overflowMBB);
20368 MF->insert(MBBIter, endMBB);
20370 // Transfer the remainder of MBB and its successor edges to endMBB.
20371 endMBB->splice(endMBB->begin(), thisMBB,
20372 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20373 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20375 // Make offsetMBB and overflowMBB successors of thisMBB
20376 thisMBB->addSuccessor(offsetMBB);
20377 thisMBB->addSuccessor(overflowMBB);
20379 // endMBB is a successor of both offsetMBB and overflowMBB
20380 offsetMBB->addSuccessor(endMBB);
20381 overflowMBB->addSuccessor(endMBB);
20383 // Load the offset value into a register
20384 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20385 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20389 .addDisp(Disp, UseFPOffset ? 4 : 0)
20390 .addOperand(Segment)
20391 .setMemRefs(MMOBegin, MMOEnd);
20393 // Check if there is enough room left to pull this argument.
20394 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20396 .addImm(MaxOffset + 8 - ArgSizeA8);
20398 // Branch to "overflowMBB" if offset >= max
20399 // Fall through to "offsetMBB" otherwise
20400 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20401 .addMBB(overflowMBB);
20404 // In offsetMBB, emit code to use the reg_save_area.
20406 assert(OffsetReg != 0);
20408 // Read the reg_save_area address.
20409 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20410 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20415 .addOperand(Segment)
20416 .setMemRefs(MMOBegin, MMOEnd);
20418 // Zero-extend the offset
20419 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20420 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20423 .addImm(X86::sub_32bit);
20425 // Add the offset to the reg_save_area to get the final address.
20426 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20427 .addReg(OffsetReg64)
20428 .addReg(RegSaveReg);
20430 // Compute the offset for the next argument
20431 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20432 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20434 .addImm(UseFPOffset ? 16 : 8);
20436 // Store it back into the va_list.
20437 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20441 .addDisp(Disp, UseFPOffset ? 4 : 0)
20442 .addOperand(Segment)
20443 .addReg(NextOffsetReg)
20444 .setMemRefs(MMOBegin, MMOEnd);
20447 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20452 // Emit code to use overflow area
20455 // Load the overflow_area address into a register.
20456 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20457 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20462 .addOperand(Segment)
20463 .setMemRefs(MMOBegin, MMOEnd);
20465 // If we need to align it, do so. Otherwise, just copy the address
20466 // to OverflowDestReg.
20468 // Align the overflow address
20469 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20470 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20472 // aligned_addr = (addr + (align-1)) & ~(align-1)
20473 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20474 .addReg(OverflowAddrReg)
20477 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20479 .addImm(~(uint64_t)(Align-1));
20481 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20482 .addReg(OverflowAddrReg);
20485 // Compute the next overflow address after this argument.
20486 // (the overflow address should be kept 8-byte aligned)
20487 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20488 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20489 .addReg(OverflowDestReg)
20490 .addImm(ArgSizeA8);
20492 // Store the new overflow address.
20493 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20498 .addOperand(Segment)
20499 .addReg(NextAddrReg)
20500 .setMemRefs(MMOBegin, MMOEnd);
20502 // If we branched, emit the PHI to the front of endMBB.
20504 BuildMI(*endMBB, endMBB->begin(), DL,
20505 TII->get(X86::PHI), DestReg)
20506 .addReg(OffsetDestReg).addMBB(offsetMBB)
20507 .addReg(OverflowDestReg).addMBB(overflowMBB);
20510 // Erase the pseudo instruction
20511 MI->eraseFromParent();
20516 MachineBasicBlock *
20517 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20519 MachineBasicBlock *MBB) const {
20520 // Emit code to save XMM registers to the stack. The ABI says that the
20521 // number of registers to save is given in %al, so it's theoretically
20522 // possible to do an indirect jump trick to avoid saving all of them,
20523 // however this code takes a simpler approach and just executes all
20524 // of the stores if %al is non-zero. It's less code, and it's probably
20525 // easier on the hardware branch predictor, and stores aren't all that
20526 // expensive anyway.
20528 // Create the new basic blocks. One block contains all the XMM stores,
20529 // and one block is the final destination regardless of whether any
20530 // stores were performed.
20531 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20532 MachineFunction *F = MBB->getParent();
20533 MachineFunction::iterator MBBIter = MBB;
20535 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20536 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20537 F->insert(MBBIter, XMMSaveMBB);
20538 F->insert(MBBIter, EndMBB);
20540 // Transfer the remainder of MBB and its successor edges to EndMBB.
20541 EndMBB->splice(EndMBB->begin(), MBB,
20542 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20543 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20545 // The original block will now fall through to the XMM save block.
20546 MBB->addSuccessor(XMMSaveMBB);
20547 // The XMMSaveMBB will fall through to the end block.
20548 XMMSaveMBB->addSuccessor(EndMBB);
20550 // Now add the instructions.
20551 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20552 DebugLoc DL = MI->getDebugLoc();
20554 unsigned CountReg = MI->getOperand(0).getReg();
20555 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20556 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20558 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20559 // If %al is 0, branch around the XMM save block.
20560 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20561 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20562 MBB->addSuccessor(EndMBB);
20565 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20566 // that was just emitted, but clearly shouldn't be "saved".
20567 assert((MI->getNumOperands() <= 3 ||
20568 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20569 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20570 && "Expected last argument to be EFLAGS");
20571 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20572 // In the XMM save block, save all the XMM argument registers.
20573 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20574 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20575 MachineMemOperand *MMO = F->getMachineMemOperand(
20576 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20577 MachineMemOperand::MOStore,
20578 /*Size=*/16, /*Align=*/16);
20579 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20580 .addFrameIndex(RegSaveFrameIndex)
20581 .addImm(/*Scale=*/1)
20582 .addReg(/*IndexReg=*/0)
20583 .addImm(/*Disp=*/Offset)
20584 .addReg(/*Segment=*/0)
20585 .addReg(MI->getOperand(i).getReg())
20586 .addMemOperand(MMO);
20589 MI->eraseFromParent(); // The pseudo instruction is gone now.
20594 // The EFLAGS operand of SelectItr might be missing a kill marker
20595 // because there were multiple uses of EFLAGS, and ISel didn't know
20596 // which to mark. Figure out whether SelectItr should have had a
20597 // kill marker, and set it if it should. Returns the correct kill
20599 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20600 MachineBasicBlock* BB,
20601 const TargetRegisterInfo* TRI) {
20602 // Scan forward through BB for a use/def of EFLAGS.
20603 MachineBasicBlock::iterator miI(std::next(SelectItr));
20604 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20605 const MachineInstr& mi = *miI;
20606 if (mi.readsRegister(X86::EFLAGS))
20608 if (mi.definesRegister(X86::EFLAGS))
20609 break; // Should have kill-flag - update below.
20612 // If we hit the end of the block, check whether EFLAGS is live into a
20614 if (miI == BB->end()) {
20615 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20616 sEnd = BB->succ_end();
20617 sItr != sEnd; ++sItr) {
20618 MachineBasicBlock* succ = *sItr;
20619 if (succ->isLiveIn(X86::EFLAGS))
20624 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20625 // out. SelectMI should have a kill flag on EFLAGS.
20626 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20630 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20631 // together with other CMOV pseudo-opcodes into a single basic-block with
20632 // conditional jump around it.
20633 static bool isCMOVPseudo(MachineInstr *MI) {
20634 switch (MI->getOpcode()) {
20635 case X86::CMOV_FR32:
20636 case X86::CMOV_FR64:
20637 case X86::CMOV_GR8:
20638 case X86::CMOV_GR16:
20639 case X86::CMOV_GR32:
20640 case X86::CMOV_RFP32:
20641 case X86::CMOV_RFP64:
20642 case X86::CMOV_RFP80:
20643 case X86::CMOV_V2F64:
20644 case X86::CMOV_V2I64:
20645 case X86::CMOV_V4F32:
20646 case X86::CMOV_V4F64:
20647 case X86::CMOV_V4I64:
20648 case X86::CMOV_V16F32:
20649 case X86::CMOV_V8F32:
20650 case X86::CMOV_V8F64:
20651 case X86::CMOV_V8I64:
20652 case X86::CMOV_V8I1:
20653 case X86::CMOV_V16I1:
20654 case X86::CMOV_V32I1:
20655 case X86::CMOV_V64I1:
20663 MachineBasicBlock *
20664 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20665 MachineBasicBlock *BB) const {
20666 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20667 DebugLoc DL = MI->getDebugLoc();
20669 // To "insert" a SELECT_CC instruction, we actually have to insert the
20670 // diamond control-flow pattern. The incoming instruction knows the
20671 // destination vreg to set, the condition code register to branch on, the
20672 // true/false values to select between, and a branch opcode to use.
20673 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20674 MachineFunction::iterator It = BB;
20680 // cmpTY ccX, r1, r2
20682 // fallthrough --> copy0MBB
20683 MachineBasicBlock *thisMBB = BB;
20684 MachineFunction *F = BB->getParent();
20686 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20687 // as described above, by inserting a BB, and then making a PHI at the join
20688 // point to select the true and false operands of the CMOV in the PHI.
20690 // The code also handles two different cases of multiple CMOV opcodes
20694 // In this case, there are multiple CMOVs in a row, all which are based on
20695 // the same condition setting (or the exact opposite condition setting).
20696 // In this case we can lower all the CMOVs using a single inserted BB, and
20697 // then make a number of PHIs at the join point to model the CMOVs. The only
20698 // trickiness here, is that in a case like:
20700 // t2 = CMOV cond1 t1, f1
20701 // t3 = CMOV cond1 t2, f2
20703 // when rewriting this into PHIs, we have to perform some renaming on the
20704 // temps since you cannot have a PHI operand refer to a PHI result earlier
20705 // in the same block. The "simple" but wrong lowering would be:
20707 // t2 = PHI t1(BB1), f1(BB2)
20708 // t3 = PHI t2(BB1), f2(BB2)
20710 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20711 // renaming is to note that on the path through BB1, t2 is really just a
20712 // copy of t1, and do that renaming, properly generating:
20714 // t2 = PHI t1(BB1), f1(BB2)
20715 // t3 = PHI t1(BB1), f2(BB2)
20717 // Case 2, we lower cascaded CMOVs such as
20719 // (CMOV (CMOV F, T, cc1), T, cc2)
20721 // to two successives branches. For that, we look for another CMOV as the
20722 // following instruction.
20724 // Without this, we would add a PHI between the two jumps, which ends up
20725 // creating a few copies all around. For instance, for
20727 // (sitofp (zext (fcmp une)))
20729 // we would generate:
20731 // ucomiss %xmm1, %xmm0
20732 // movss <1.0f>, %xmm0
20733 // movaps %xmm0, %xmm1
20735 // xorps %xmm1, %xmm1
20738 // movaps %xmm1, %xmm0
20742 // because this custom-inserter would have generated:
20754 // A: X = ...; Y = ...
20756 // C: Z = PHI [X, A], [Y, B]
20758 // E: PHI [X, C], [Z, D]
20760 // If we lower both CMOVs in a single step, we can instead generate:
20772 // A: X = ...; Y = ...
20774 // E: PHI [X, A], [X, C], [Y, D]
20776 // Which, in our sitofp/fcmp example, gives us something like:
20778 // ucomiss %xmm1, %xmm0
20779 // movss <1.0f>, %xmm0
20782 // xorps %xmm0, %xmm0
20786 MachineInstr *CascadedCMOV = nullptr;
20787 MachineInstr *LastCMOV = MI;
20788 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
20789 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
20790 MachineBasicBlock::iterator NextMIIt =
20791 std::next(MachineBasicBlock::iterator(MI));
20793 // Check for case 1, where there are multiple CMOVs with the same condition
20794 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
20795 // number of jumps the most.
20797 if (isCMOVPseudo(MI)) {
20798 // See if we have a string of CMOVS with the same condition.
20799 while (NextMIIt != BB->end() &&
20800 isCMOVPseudo(NextMIIt) &&
20801 (NextMIIt->getOperand(3).getImm() == CC ||
20802 NextMIIt->getOperand(3).getImm() == OppCC)) {
20803 LastCMOV = &*NextMIIt;
20808 // This checks for case 2, but only do this if we didn't already find
20809 // case 1, as indicated by LastCMOV == MI.
20810 if (LastCMOV == MI &&
20811 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
20812 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
20813 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
20814 CascadedCMOV = &*NextMIIt;
20817 MachineBasicBlock *jcc1MBB = nullptr;
20819 // If we have a cascaded CMOV, we lower it to two successive branches to
20820 // the same block. EFLAGS is used by both, so mark it as live in the second.
20821 if (CascadedCMOV) {
20822 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
20823 F->insert(It, jcc1MBB);
20824 jcc1MBB->addLiveIn(X86::EFLAGS);
20827 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20828 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20829 F->insert(It, copy0MBB);
20830 F->insert(It, sinkMBB);
20832 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20833 // live into the sink and copy blocks.
20834 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
20836 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
20837 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
20838 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
20839 copy0MBB->addLiveIn(X86::EFLAGS);
20840 sinkMBB->addLiveIn(X86::EFLAGS);
20843 // Transfer the remainder of BB and its successor edges to sinkMBB.
20844 sinkMBB->splice(sinkMBB->begin(), BB,
20845 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
20846 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20848 // Add the true and fallthrough blocks as its successors.
20849 if (CascadedCMOV) {
20850 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
20851 BB->addSuccessor(jcc1MBB);
20853 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
20854 // jump to the sinkMBB.
20855 jcc1MBB->addSuccessor(copy0MBB);
20856 jcc1MBB->addSuccessor(sinkMBB);
20858 BB->addSuccessor(copy0MBB);
20861 // The true block target of the first (or only) branch is always sinkMBB.
20862 BB->addSuccessor(sinkMBB);
20864 // Create the conditional branch instruction.
20865 unsigned Opc = X86::GetCondBranchFromCond(CC);
20866 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20868 if (CascadedCMOV) {
20869 unsigned Opc2 = X86::GetCondBranchFromCond(
20870 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
20871 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
20875 // %FalseValue = ...
20876 // # fallthrough to sinkMBB
20877 copy0MBB->addSuccessor(sinkMBB);
20880 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20882 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
20883 MachineBasicBlock::iterator MIItEnd =
20884 std::next(MachineBasicBlock::iterator(LastCMOV));
20885 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
20886 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
20887 MachineInstrBuilder MIB;
20889 // As we are creating the PHIs, we have to be careful if there is more than
20890 // one. Later CMOVs may reference the results of earlier CMOVs, but later
20891 // PHIs have to reference the individual true/false inputs from earlier PHIs.
20892 // That also means that PHI construction must work forward from earlier to
20893 // later, and that the code must maintain a mapping from earlier PHI's
20894 // destination registers, and the registers that went into the PHI.
20896 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
20897 unsigned DestReg = MIIt->getOperand(0).getReg();
20898 unsigned Op1Reg = MIIt->getOperand(1).getReg();
20899 unsigned Op2Reg = MIIt->getOperand(2).getReg();
20901 // If this CMOV we are generating is the opposite condition from
20902 // the jump we generated, then we have to swap the operands for the
20903 // PHI that is going to be generated.
20904 if (MIIt->getOperand(3).getImm() == OppCC)
20905 std::swap(Op1Reg, Op2Reg);
20907 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
20908 Op1Reg = RegRewriteTable[Op1Reg].first;
20910 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
20911 Op2Reg = RegRewriteTable[Op2Reg].second;
20913 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
20914 TII->get(X86::PHI), DestReg)
20915 .addReg(Op1Reg).addMBB(copy0MBB)
20916 .addReg(Op2Reg).addMBB(thisMBB);
20918 // Add this PHI to the rewrite table.
20919 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
20922 // If we have a cascaded CMOV, the second Jcc provides the same incoming
20923 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
20924 if (CascadedCMOV) {
20925 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
20926 // Copy the PHI result to the register defined by the second CMOV.
20927 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
20928 DL, TII->get(TargetOpcode::COPY),
20929 CascadedCMOV->getOperand(0).getReg())
20930 .addReg(MI->getOperand(0).getReg());
20931 CascadedCMOV->eraseFromParent();
20934 // Now remove the CMOV(s).
20935 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
20936 (MIIt++)->eraseFromParent();
20941 MachineBasicBlock *
20942 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
20943 MachineBasicBlock *BB) const {
20944 // Combine the following atomic floating-point modification pattern:
20945 // a.store(reg OP a.load(acquire), release)
20946 // Transform them into:
20947 // OPss (%gpr), %xmm
20948 // movss %xmm, (%gpr)
20949 // Or sd equivalent for 64-bit operations.
20951 switch (MI->getOpcode()) {
20952 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
20953 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
20954 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
20956 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20957 DebugLoc DL = MI->getDebugLoc();
20958 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
20959 unsigned MSrc = MI->getOperand(0).getReg();
20960 unsigned VSrc = MI->getOperand(5).getReg();
20961 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
20962 .addReg(/*Base=*/MSrc)
20963 .addImm(/*Scale=*/1)
20964 .addReg(/*Index=*/0)
20967 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
20968 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
20970 .addReg(/*Base=*/MSrc)
20971 .addImm(/*Scale=*/1)
20972 .addReg(/*Index=*/0)
20973 .addImm(/*Disp=*/0)
20974 .addReg(/*Segment=*/0);
20975 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
20976 MI->eraseFromParent(); // The pseudo instruction is gone now.
20980 MachineBasicBlock *
20981 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20982 MachineBasicBlock *BB) const {
20983 MachineFunction *MF = BB->getParent();
20984 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20985 DebugLoc DL = MI->getDebugLoc();
20986 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20988 assert(MF->shouldSplitStack());
20990 const bool Is64Bit = Subtarget->is64Bit();
20991 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20993 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20994 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20997 // ... [Till the alloca]
20998 // If stacklet is not large enough, jump to mallocMBB
21001 // Allocate by subtracting from RSP
21002 // Jump to continueMBB
21005 // Allocate by call to runtime
21009 // [rest of original BB]
21012 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21013 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21014 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21016 MachineRegisterInfo &MRI = MF->getRegInfo();
21017 const TargetRegisterClass *AddrRegClass =
21018 getRegClassFor(getPointerTy(MF->getDataLayout()));
21020 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21021 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21022 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21023 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21024 sizeVReg = MI->getOperand(1).getReg(),
21025 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21027 MachineFunction::iterator MBBIter = BB;
21030 MF->insert(MBBIter, bumpMBB);
21031 MF->insert(MBBIter, mallocMBB);
21032 MF->insert(MBBIter, continueMBB);
21034 continueMBB->splice(continueMBB->begin(), BB,
21035 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21036 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21038 // Add code to the main basic block to check if the stack limit has been hit,
21039 // and if so, jump to mallocMBB otherwise to bumpMBB.
21040 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21041 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21042 .addReg(tmpSPVReg).addReg(sizeVReg);
21043 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21044 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21045 .addReg(SPLimitVReg);
21046 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21048 // bumpMBB simply decreases the stack pointer, since we know the current
21049 // stacklet has enough space.
21050 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21051 .addReg(SPLimitVReg);
21052 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21053 .addReg(SPLimitVReg);
21054 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21056 // Calls into a routine in libgcc to allocate more space from the heap.
21057 const uint32_t *RegMask =
21058 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21060 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21062 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21063 .addExternalSymbol("__morestack_allocate_stack_space")
21064 .addRegMask(RegMask)
21065 .addReg(X86::RDI, RegState::Implicit)
21066 .addReg(X86::RAX, RegState::ImplicitDefine);
21067 } else if (Is64Bit) {
21068 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21070 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21071 .addExternalSymbol("__morestack_allocate_stack_space")
21072 .addRegMask(RegMask)
21073 .addReg(X86::EDI, RegState::Implicit)
21074 .addReg(X86::EAX, RegState::ImplicitDefine);
21076 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21078 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21079 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21080 .addExternalSymbol("__morestack_allocate_stack_space")
21081 .addRegMask(RegMask)
21082 .addReg(X86::EAX, RegState::ImplicitDefine);
21086 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21089 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21090 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21091 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21093 // Set up the CFG correctly.
21094 BB->addSuccessor(bumpMBB);
21095 BB->addSuccessor(mallocMBB);
21096 mallocMBB->addSuccessor(continueMBB);
21097 bumpMBB->addSuccessor(continueMBB);
21099 // Take care of the PHI nodes.
21100 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21101 MI->getOperand(0).getReg())
21102 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21103 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21105 // Delete the original pseudo instruction.
21106 MI->eraseFromParent();
21109 return continueMBB;
21112 MachineBasicBlock *
21113 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21114 MachineBasicBlock *BB) const {
21115 DebugLoc DL = MI->getDebugLoc();
21117 assert(!Subtarget->isTargetMachO());
21119 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21122 MI->eraseFromParent(); // The pseudo instruction is gone now.
21126 MachineBasicBlock *
21127 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21128 MachineBasicBlock *BB) const {
21129 // This is pretty easy. We're taking the value that we received from
21130 // our load from the relocation, sticking it in either RDI (x86-64)
21131 // or EAX and doing an indirect call. The return value will then
21132 // be in the normal return register.
21133 MachineFunction *F = BB->getParent();
21134 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21135 DebugLoc DL = MI->getDebugLoc();
21137 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21138 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21140 // Get a register mask for the lowered call.
21141 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21142 // proper register mask.
21143 const uint32_t *RegMask =
21144 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21145 if (Subtarget->is64Bit()) {
21146 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21147 TII->get(X86::MOV64rm), X86::RDI)
21149 .addImm(0).addReg(0)
21150 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21151 MI->getOperand(3).getTargetFlags())
21153 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21154 addDirectMem(MIB, X86::RDI);
21155 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21156 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21157 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21158 TII->get(X86::MOV32rm), X86::EAX)
21160 .addImm(0).addReg(0)
21161 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21162 MI->getOperand(3).getTargetFlags())
21164 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21165 addDirectMem(MIB, X86::EAX);
21166 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21168 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21169 TII->get(X86::MOV32rm), X86::EAX)
21170 .addReg(TII->getGlobalBaseReg(F))
21171 .addImm(0).addReg(0)
21172 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21173 MI->getOperand(3).getTargetFlags())
21175 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21176 addDirectMem(MIB, X86::EAX);
21177 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21180 MI->eraseFromParent(); // The pseudo instruction is gone now.
21184 MachineBasicBlock *
21185 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21186 MachineBasicBlock *MBB) const {
21187 DebugLoc DL = MI->getDebugLoc();
21188 MachineFunction *MF = MBB->getParent();
21189 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21190 MachineRegisterInfo &MRI = MF->getRegInfo();
21192 const BasicBlock *BB = MBB->getBasicBlock();
21193 MachineFunction::iterator I = MBB;
21196 // Memory Reference
21197 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21198 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21201 unsigned MemOpndSlot = 0;
21203 unsigned CurOp = 0;
21205 DstReg = MI->getOperand(CurOp++).getReg();
21206 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21207 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21208 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21209 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21211 MemOpndSlot = CurOp;
21213 MVT PVT = getPointerTy(MF->getDataLayout());
21214 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21215 "Invalid Pointer Size!");
21217 // For v = setjmp(buf), we generate
21220 // buf[LabelOffset] = restoreMBB
21221 // SjLjSetup restoreMBB
21227 // v = phi(main, restore)
21230 // if base pointer being used, load it from frame
21233 MachineBasicBlock *thisMBB = MBB;
21234 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21235 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21236 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21237 MF->insert(I, mainMBB);
21238 MF->insert(I, sinkMBB);
21239 MF->push_back(restoreMBB);
21241 MachineInstrBuilder MIB;
21243 // Transfer the remainder of BB and its successor edges to sinkMBB.
21244 sinkMBB->splice(sinkMBB->begin(), MBB,
21245 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21246 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21249 unsigned PtrStoreOpc = 0;
21250 unsigned LabelReg = 0;
21251 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21252 Reloc::Model RM = MF->getTarget().getRelocationModel();
21253 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21254 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21256 // Prepare IP either in reg or imm.
21257 if (!UseImmLabel) {
21258 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21259 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21260 LabelReg = MRI.createVirtualRegister(PtrRC);
21261 if (Subtarget->is64Bit()) {
21262 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21266 .addMBB(restoreMBB)
21269 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21270 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21271 .addReg(XII->getGlobalBaseReg(MF))
21274 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21278 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21280 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21281 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21282 if (i == X86::AddrDisp)
21283 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21285 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21288 MIB.addReg(LabelReg);
21290 MIB.addMBB(restoreMBB);
21291 MIB.setMemRefs(MMOBegin, MMOEnd);
21293 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21294 .addMBB(restoreMBB);
21296 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21297 MIB.addRegMask(RegInfo->getNoPreservedMask());
21298 thisMBB->addSuccessor(mainMBB);
21299 thisMBB->addSuccessor(restoreMBB);
21303 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21304 mainMBB->addSuccessor(sinkMBB);
21307 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21308 TII->get(X86::PHI), DstReg)
21309 .addReg(mainDstReg).addMBB(mainMBB)
21310 .addReg(restoreDstReg).addMBB(restoreMBB);
21313 if (RegInfo->hasBasePointer(*MF)) {
21314 const bool Uses64BitFramePtr =
21315 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21316 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21317 X86FI->setRestoreBasePointer(MF);
21318 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21319 unsigned BasePtr = RegInfo->getBaseRegister();
21320 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21321 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21322 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21323 .setMIFlag(MachineInstr::FrameSetup);
21325 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21326 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21327 restoreMBB->addSuccessor(sinkMBB);
21329 MI->eraseFromParent();
21333 MachineBasicBlock *
21334 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21335 MachineBasicBlock *MBB) const {
21336 DebugLoc DL = MI->getDebugLoc();
21337 MachineFunction *MF = MBB->getParent();
21338 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21339 MachineRegisterInfo &MRI = MF->getRegInfo();
21341 // Memory Reference
21342 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21343 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21345 MVT PVT = getPointerTy(MF->getDataLayout());
21346 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21347 "Invalid Pointer Size!");
21349 const TargetRegisterClass *RC =
21350 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21351 unsigned Tmp = MRI.createVirtualRegister(RC);
21352 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21353 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21354 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21355 unsigned SP = RegInfo->getStackRegister();
21357 MachineInstrBuilder MIB;
21359 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21360 const int64_t SPOffset = 2 * PVT.getStoreSize();
21362 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21363 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21366 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21367 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21368 MIB.addOperand(MI->getOperand(i));
21369 MIB.setMemRefs(MMOBegin, MMOEnd);
21371 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21372 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21373 if (i == X86::AddrDisp)
21374 MIB.addDisp(MI->getOperand(i), LabelOffset);
21376 MIB.addOperand(MI->getOperand(i));
21378 MIB.setMemRefs(MMOBegin, MMOEnd);
21380 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21381 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21382 if (i == X86::AddrDisp)
21383 MIB.addDisp(MI->getOperand(i), SPOffset);
21385 MIB.addOperand(MI->getOperand(i));
21387 MIB.setMemRefs(MMOBegin, MMOEnd);
21389 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21391 MI->eraseFromParent();
21395 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21396 // accumulator loops. Writing back to the accumulator allows the coalescer
21397 // to remove extra copies in the loop.
21398 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21399 MachineBasicBlock *
21400 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21401 MachineBasicBlock *MBB) const {
21402 MachineOperand &AddendOp = MI->getOperand(3);
21404 // Bail out early if the addend isn't a register - we can't switch these.
21405 if (!AddendOp.isReg())
21408 MachineFunction &MF = *MBB->getParent();
21409 MachineRegisterInfo &MRI = MF.getRegInfo();
21411 // Check whether the addend is defined by a PHI:
21412 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21413 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21414 if (!AddendDef.isPHI())
21417 // Look for the following pattern:
21419 // %addend = phi [%entry, 0], [%loop, %result]
21421 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21425 // %addend = phi [%entry, 0], [%loop, %result]
21427 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21429 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21430 assert(AddendDef.getOperand(i).isReg());
21431 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21432 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21433 if (&PHISrcInst == MI) {
21434 // Found a matching instruction.
21435 unsigned NewFMAOpc = 0;
21436 switch (MI->getOpcode()) {
21437 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21438 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21439 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21440 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21441 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21442 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21443 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21444 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21445 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21446 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21447 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21448 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21449 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21450 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21451 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21452 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21453 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21454 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21455 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21456 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21458 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21459 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21460 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21461 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21462 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21463 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21464 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21465 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21466 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21467 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21468 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21469 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21470 default: llvm_unreachable("Unrecognized FMA variant.");
21473 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21474 MachineInstrBuilder MIB =
21475 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21476 .addOperand(MI->getOperand(0))
21477 .addOperand(MI->getOperand(3))
21478 .addOperand(MI->getOperand(2))
21479 .addOperand(MI->getOperand(1));
21480 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21481 MI->eraseFromParent();
21488 MachineBasicBlock *
21489 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21490 MachineBasicBlock *BB) const {
21491 switch (MI->getOpcode()) {
21492 default: llvm_unreachable("Unexpected instr type to insert");
21493 case X86::TAILJMPd64:
21494 case X86::TAILJMPr64:
21495 case X86::TAILJMPm64:
21496 case X86::TAILJMPd64_REX:
21497 case X86::TAILJMPr64_REX:
21498 case X86::TAILJMPm64_REX:
21499 llvm_unreachable("TAILJMP64 would not be touched here.");
21500 case X86::TCRETURNdi64:
21501 case X86::TCRETURNri64:
21502 case X86::TCRETURNmi64:
21504 case X86::WIN_ALLOCA:
21505 return EmitLoweredWinAlloca(MI, BB);
21506 case X86::SEG_ALLOCA_32:
21507 case X86::SEG_ALLOCA_64:
21508 return EmitLoweredSegAlloca(MI, BB);
21509 case X86::TLSCall_32:
21510 case X86::TLSCall_64:
21511 return EmitLoweredTLSCall(MI, BB);
21512 case X86::CMOV_FR32:
21513 case X86::CMOV_FR64:
21514 case X86::CMOV_GR8:
21515 case X86::CMOV_GR16:
21516 case X86::CMOV_GR32:
21517 case X86::CMOV_RFP32:
21518 case X86::CMOV_RFP64:
21519 case X86::CMOV_RFP80:
21520 case X86::CMOV_V2F64:
21521 case X86::CMOV_V2I64:
21522 case X86::CMOV_V4F32:
21523 case X86::CMOV_V4F64:
21524 case X86::CMOV_V4I64:
21525 case X86::CMOV_V16F32:
21526 case X86::CMOV_V8F32:
21527 case X86::CMOV_V8F64:
21528 case X86::CMOV_V8I64:
21529 case X86::CMOV_V8I1:
21530 case X86::CMOV_V16I1:
21531 case X86::CMOV_V32I1:
21532 case X86::CMOV_V64I1:
21533 return EmitLoweredSelect(MI, BB);
21535 case X86::RELEASE_FADD32mr:
21536 case X86::RELEASE_FADD64mr:
21537 return EmitLoweredAtomicFP(MI, BB);
21539 case X86::FP32_TO_INT16_IN_MEM:
21540 case X86::FP32_TO_INT32_IN_MEM:
21541 case X86::FP32_TO_INT64_IN_MEM:
21542 case X86::FP64_TO_INT16_IN_MEM:
21543 case X86::FP64_TO_INT32_IN_MEM:
21544 case X86::FP64_TO_INT64_IN_MEM:
21545 case X86::FP80_TO_INT16_IN_MEM:
21546 case X86::FP80_TO_INT32_IN_MEM:
21547 case X86::FP80_TO_INT64_IN_MEM: {
21548 MachineFunction *F = BB->getParent();
21549 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21550 DebugLoc DL = MI->getDebugLoc();
21552 // Change the floating point control register to use "round towards zero"
21553 // mode when truncating to an integer value.
21554 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21555 addFrameReference(BuildMI(*BB, MI, DL,
21556 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21558 // Load the old value of the high byte of the control word...
21560 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21561 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21564 // Set the high part to be round to zero...
21565 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21568 // Reload the modified control word now...
21569 addFrameReference(BuildMI(*BB, MI, DL,
21570 TII->get(X86::FLDCW16m)), CWFrameIdx);
21572 // Restore the memory image of control word to original value
21573 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21576 // Get the X86 opcode to use.
21578 switch (MI->getOpcode()) {
21579 default: llvm_unreachable("illegal opcode!");
21580 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21581 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21582 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21583 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21584 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21585 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21586 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21587 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21588 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21592 MachineOperand &Op = MI->getOperand(0);
21594 AM.BaseType = X86AddressMode::RegBase;
21595 AM.Base.Reg = Op.getReg();
21597 AM.BaseType = X86AddressMode::FrameIndexBase;
21598 AM.Base.FrameIndex = Op.getIndex();
21600 Op = MI->getOperand(1);
21602 AM.Scale = Op.getImm();
21603 Op = MI->getOperand(2);
21605 AM.IndexReg = Op.getImm();
21606 Op = MI->getOperand(3);
21607 if (Op.isGlobal()) {
21608 AM.GV = Op.getGlobal();
21610 AM.Disp = Op.getImm();
21612 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21613 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21615 // Reload the original control word now.
21616 addFrameReference(BuildMI(*BB, MI, DL,
21617 TII->get(X86::FLDCW16m)), CWFrameIdx);
21619 MI->eraseFromParent(); // The pseudo instruction is gone now.
21622 // String/text processing lowering.
21623 case X86::PCMPISTRM128REG:
21624 case X86::VPCMPISTRM128REG:
21625 case X86::PCMPISTRM128MEM:
21626 case X86::VPCMPISTRM128MEM:
21627 case X86::PCMPESTRM128REG:
21628 case X86::VPCMPESTRM128REG:
21629 case X86::PCMPESTRM128MEM:
21630 case X86::VPCMPESTRM128MEM:
21631 assert(Subtarget->hasSSE42() &&
21632 "Target must have SSE4.2 or AVX features enabled");
21633 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21635 // String/text processing lowering.
21636 case X86::PCMPISTRIREG:
21637 case X86::VPCMPISTRIREG:
21638 case X86::PCMPISTRIMEM:
21639 case X86::VPCMPISTRIMEM:
21640 case X86::PCMPESTRIREG:
21641 case X86::VPCMPESTRIREG:
21642 case X86::PCMPESTRIMEM:
21643 case X86::VPCMPESTRIMEM:
21644 assert(Subtarget->hasSSE42() &&
21645 "Target must have SSE4.2 or AVX features enabled");
21646 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21648 // Thread synchronization.
21650 return EmitMonitor(MI, BB, Subtarget);
21654 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21656 case X86::VASTART_SAVE_XMM_REGS:
21657 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21659 case X86::VAARG_64:
21660 return EmitVAARG64WithCustomInserter(MI, BB);
21662 case X86::EH_SjLj_SetJmp32:
21663 case X86::EH_SjLj_SetJmp64:
21664 return emitEHSjLjSetJmp(MI, BB);
21666 case X86::EH_SjLj_LongJmp32:
21667 case X86::EH_SjLj_LongJmp64:
21668 return emitEHSjLjLongJmp(MI, BB);
21670 case TargetOpcode::STATEPOINT:
21671 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21672 // this point in the process. We diverge later.
21673 return emitPatchPoint(MI, BB);
21675 case TargetOpcode::STACKMAP:
21676 case TargetOpcode::PATCHPOINT:
21677 return emitPatchPoint(MI, BB);
21679 case X86::VFMADDPDr213r:
21680 case X86::VFMADDPSr213r:
21681 case X86::VFMADDSDr213r:
21682 case X86::VFMADDSSr213r:
21683 case X86::VFMSUBPDr213r:
21684 case X86::VFMSUBPSr213r:
21685 case X86::VFMSUBSDr213r:
21686 case X86::VFMSUBSSr213r:
21687 case X86::VFNMADDPDr213r:
21688 case X86::VFNMADDPSr213r:
21689 case X86::VFNMADDSDr213r:
21690 case X86::VFNMADDSSr213r:
21691 case X86::VFNMSUBPDr213r:
21692 case X86::VFNMSUBPSr213r:
21693 case X86::VFNMSUBSDr213r:
21694 case X86::VFNMSUBSSr213r:
21695 case X86::VFMADDSUBPDr213r:
21696 case X86::VFMADDSUBPSr213r:
21697 case X86::VFMSUBADDPDr213r:
21698 case X86::VFMSUBADDPSr213r:
21699 case X86::VFMADDPDr213rY:
21700 case X86::VFMADDPSr213rY:
21701 case X86::VFMSUBPDr213rY:
21702 case X86::VFMSUBPSr213rY:
21703 case X86::VFNMADDPDr213rY:
21704 case X86::VFNMADDPSr213rY:
21705 case X86::VFNMSUBPDr213rY:
21706 case X86::VFNMSUBPSr213rY:
21707 case X86::VFMADDSUBPDr213rY:
21708 case X86::VFMADDSUBPSr213rY:
21709 case X86::VFMSUBADDPDr213rY:
21710 case X86::VFMSUBADDPSr213rY:
21711 return emitFMA3Instr(MI, BB);
21715 //===----------------------------------------------------------------------===//
21716 // X86 Optimization Hooks
21717 //===----------------------------------------------------------------------===//
21719 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21722 const SelectionDAG &DAG,
21723 unsigned Depth) const {
21724 unsigned BitWidth = KnownZero.getBitWidth();
21725 unsigned Opc = Op.getOpcode();
21726 assert((Opc >= ISD::BUILTIN_OP_END ||
21727 Opc == ISD::INTRINSIC_WO_CHAIN ||
21728 Opc == ISD::INTRINSIC_W_CHAIN ||
21729 Opc == ISD::INTRINSIC_VOID) &&
21730 "Should use MaskedValueIsZero if you don't know whether Op"
21731 " is a target node!");
21733 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21747 // These nodes' second result is a boolean.
21748 if (Op.getResNo() == 0)
21751 case X86ISD::SETCC:
21752 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21754 case ISD::INTRINSIC_WO_CHAIN: {
21755 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21756 unsigned NumLoBits = 0;
21759 case Intrinsic::x86_sse_movmsk_ps:
21760 case Intrinsic::x86_avx_movmsk_ps_256:
21761 case Intrinsic::x86_sse2_movmsk_pd:
21762 case Intrinsic::x86_avx_movmsk_pd_256:
21763 case Intrinsic::x86_mmx_pmovmskb:
21764 case Intrinsic::x86_sse2_pmovmskb_128:
21765 case Intrinsic::x86_avx2_pmovmskb: {
21766 // High bits of movmskp{s|d}, pmovmskb are known zero.
21768 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21769 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21770 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21771 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21772 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21773 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21774 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21775 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21777 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21786 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21788 const SelectionDAG &,
21789 unsigned Depth) const {
21790 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21791 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21792 return Op.getValueType().getScalarType().getSizeInBits();
21798 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21799 /// node is a GlobalAddress + offset.
21800 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21801 const GlobalValue* &GA,
21802 int64_t &Offset) const {
21803 if (N->getOpcode() == X86ISD::Wrapper) {
21804 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21805 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21806 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21810 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21813 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21814 /// same as extracting the high 128-bit part of 256-bit vector and then
21815 /// inserting the result into the low part of a new 256-bit vector
21816 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21817 EVT VT = SVOp->getValueType(0);
21818 unsigned NumElems = VT.getVectorNumElements();
21820 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21821 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21822 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21823 SVOp->getMaskElt(j) >= 0)
21829 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21830 /// same as extracting the low 128-bit part of 256-bit vector and then
21831 /// inserting the result into the high part of a new 256-bit vector
21832 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21833 EVT VT = SVOp->getValueType(0);
21834 unsigned NumElems = VT.getVectorNumElements();
21836 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21837 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21838 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21839 SVOp->getMaskElt(j) >= 0)
21845 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21846 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21847 TargetLowering::DAGCombinerInfo &DCI,
21848 const X86Subtarget* Subtarget) {
21850 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21851 SDValue V1 = SVOp->getOperand(0);
21852 SDValue V2 = SVOp->getOperand(1);
21853 EVT VT = SVOp->getValueType(0);
21854 unsigned NumElems = VT.getVectorNumElements();
21856 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21857 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21861 // V UNDEF BUILD_VECTOR UNDEF
21863 // CONCAT_VECTOR CONCAT_VECTOR
21866 // RESULT: V + zero extended
21868 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21869 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21870 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21873 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21876 // To match the shuffle mask, the first half of the mask should
21877 // be exactly the first vector, and all the rest a splat with the
21878 // first element of the second one.
21879 for (unsigned i = 0; i != NumElems/2; ++i)
21880 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21881 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21884 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21885 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21886 if (Ld->hasNUsesOfValue(1, 0)) {
21887 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21888 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21890 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21892 Ld->getPointerInfo(),
21893 Ld->getAlignment(),
21894 false/*isVolatile*/, true/*ReadMem*/,
21895 false/*WriteMem*/);
21897 // Make sure the newly-created LOAD is in the same position as Ld in
21898 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21899 // and update uses of Ld's output chain to use the TokenFactor.
21900 if (Ld->hasAnyUseOfValue(1)) {
21901 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21902 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21903 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21904 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21905 SDValue(ResNode.getNode(), 1));
21908 return DAG.getBitcast(VT, ResNode);
21912 // Emit a zeroed vector and insert the desired subvector on its
21914 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21915 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21916 return DCI.CombineTo(N, InsV);
21919 //===--------------------------------------------------------------------===//
21920 // Combine some shuffles into subvector extracts and inserts:
21923 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21924 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21925 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21926 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21927 return DCI.CombineTo(N, InsV);
21930 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21931 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21932 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21933 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21934 return DCI.CombineTo(N, InsV);
21940 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21943 /// This is the leaf of the recursive combinine below. When we have found some
21944 /// chain of single-use x86 shuffle instructions and accumulated the combined
21945 /// shuffle mask represented by them, this will try to pattern match that mask
21946 /// into either a single instruction if there is a special purpose instruction
21947 /// for this operation, or into a PSHUFB instruction which is a fully general
21948 /// instruction but should only be used to replace chains over a certain depth.
21949 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21950 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21951 TargetLowering::DAGCombinerInfo &DCI,
21952 const X86Subtarget *Subtarget) {
21953 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21955 // Find the operand that enters the chain. Note that multiple uses are OK
21956 // here, we're not going to remove the operand we find.
21957 SDValue Input = Op.getOperand(0);
21958 while (Input.getOpcode() == ISD::BITCAST)
21959 Input = Input.getOperand(0);
21961 MVT VT = Input.getSimpleValueType();
21962 MVT RootVT = Root.getSimpleValueType();
21965 // Just remove no-op shuffle masks.
21966 if (Mask.size() == 1) {
21967 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
21972 // Use the float domain if the operand type is a floating point type.
21973 bool FloatDomain = VT.isFloatingPoint();
21975 // For floating point shuffles, we don't have free copies in the shuffle
21976 // instructions or the ability to load as part of the instruction, so
21977 // canonicalize their shuffles to UNPCK or MOV variants.
21979 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21980 // vectors because it can have a load folded into it that UNPCK cannot. This
21981 // doesn't preclude something switching to the shorter encoding post-RA.
21983 // FIXME: Should teach these routines about AVX vector widths.
21984 if (FloatDomain && VT.getSizeInBits() == 128) {
21985 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
21986 bool Lo = Mask.equals({0, 0});
21989 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21990 // is no slower than UNPCKLPD but has the option to fold the input operand
21991 // into even an unaligned memory load.
21992 if (Lo && Subtarget->hasSSE3()) {
21993 Shuffle = X86ISD::MOVDDUP;
21994 ShuffleVT = MVT::v2f64;
21996 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21997 // than the UNPCK variants.
21998 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21999 ShuffleVT = MVT::v4f32;
22001 if (Depth == 1 && Root->getOpcode() == Shuffle)
22002 return false; // Nothing to do!
22003 Op = DAG.getBitcast(ShuffleVT, Input);
22004 DCI.AddToWorklist(Op.getNode());
22005 if (Shuffle == X86ISD::MOVDDUP)
22006 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22008 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22009 DCI.AddToWorklist(Op.getNode());
22010 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22014 if (Subtarget->hasSSE3() &&
22015 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22016 bool Lo = Mask.equals({0, 0, 2, 2});
22017 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22018 MVT ShuffleVT = MVT::v4f32;
22019 if (Depth == 1 && Root->getOpcode() == Shuffle)
22020 return false; // Nothing to do!
22021 Op = DAG.getBitcast(ShuffleVT, Input);
22022 DCI.AddToWorklist(Op.getNode());
22023 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22024 DCI.AddToWorklist(Op.getNode());
22025 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22029 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22030 bool Lo = Mask.equals({0, 0, 1, 1});
22031 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22032 MVT ShuffleVT = MVT::v4f32;
22033 if (Depth == 1 && Root->getOpcode() == Shuffle)
22034 return false; // Nothing to do!
22035 Op = DAG.getBitcast(ShuffleVT, Input);
22036 DCI.AddToWorklist(Op.getNode());
22037 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22038 DCI.AddToWorklist(Op.getNode());
22039 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22045 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22046 // variants as none of these have single-instruction variants that are
22047 // superior to the UNPCK formulation.
22048 if (!FloatDomain && VT.getSizeInBits() == 128 &&
22049 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22050 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22051 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22053 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22054 bool Lo = Mask[0] == 0;
22055 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22056 if (Depth == 1 && Root->getOpcode() == Shuffle)
22057 return false; // Nothing to do!
22059 switch (Mask.size()) {
22061 ShuffleVT = MVT::v8i16;
22064 ShuffleVT = MVT::v16i8;
22067 llvm_unreachable("Impossible mask size!");
22069 Op = DAG.getBitcast(ShuffleVT, Input);
22070 DCI.AddToWorklist(Op.getNode());
22071 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22072 DCI.AddToWorklist(Op.getNode());
22073 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22078 // Don't try to re-form single instruction chains under any circumstances now
22079 // that we've done encoding canonicalization for them.
22083 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22084 // can replace them with a single PSHUFB instruction profitably. Intel's
22085 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22086 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22087 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22088 SmallVector<SDValue, 16> PSHUFBMask;
22089 int NumBytes = VT.getSizeInBits() / 8;
22090 int Ratio = NumBytes / Mask.size();
22091 for (int i = 0; i < NumBytes; ++i) {
22092 if (Mask[i / Ratio] == SM_SentinelUndef) {
22093 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22096 int M = Mask[i / Ratio] != SM_SentinelZero
22097 ? Ratio * Mask[i / Ratio] + i % Ratio
22099 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22101 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22102 Op = DAG.getBitcast(ByteVT, Input);
22103 DCI.AddToWorklist(Op.getNode());
22104 SDValue PSHUFBMaskOp =
22105 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22106 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22107 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22108 DCI.AddToWorklist(Op.getNode());
22109 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22114 // Failed to find any combines.
22118 /// \brief Fully generic combining of x86 shuffle instructions.
22120 /// This should be the last combine run over the x86 shuffle instructions. Once
22121 /// they have been fully optimized, this will recursively consider all chains
22122 /// of single-use shuffle instructions, build a generic model of the cumulative
22123 /// shuffle operation, and check for simpler instructions which implement this
22124 /// operation. We use this primarily for two purposes:
22126 /// 1) Collapse generic shuffles to specialized single instructions when
22127 /// equivalent. In most cases, this is just an encoding size win, but
22128 /// sometimes we will collapse multiple generic shuffles into a single
22129 /// special-purpose shuffle.
22130 /// 2) Look for sequences of shuffle instructions with 3 or more total
22131 /// instructions, and replace them with the slightly more expensive SSSE3
22132 /// PSHUFB instruction if available. We do this as the last combining step
22133 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22134 /// a suitable short sequence of other instructions. The PHUFB will either
22135 /// use a register or have to read from memory and so is slightly (but only
22136 /// slightly) more expensive than the other shuffle instructions.
22138 /// Because this is inherently a quadratic operation (for each shuffle in
22139 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22140 /// This should never be an issue in practice as the shuffle lowering doesn't
22141 /// produce sequences of more than 8 instructions.
22143 /// FIXME: We will currently miss some cases where the redundant shuffling
22144 /// would simplify under the threshold for PSHUFB formation because of
22145 /// combine-ordering. To fix this, we should do the redundant instruction
22146 /// combining in this recursive walk.
22147 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22148 ArrayRef<int> RootMask,
22149 int Depth, bool HasPSHUFB,
22151 TargetLowering::DAGCombinerInfo &DCI,
22152 const X86Subtarget *Subtarget) {
22153 // Bound the depth of our recursive combine because this is ultimately
22154 // quadratic in nature.
22158 // Directly rip through bitcasts to find the underlying operand.
22159 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22160 Op = Op.getOperand(0);
22162 MVT VT = Op.getSimpleValueType();
22163 if (!VT.isVector())
22164 return false; // Bail if we hit a non-vector.
22166 assert(Root.getSimpleValueType().isVector() &&
22167 "Shuffles operate on vector types!");
22168 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22169 "Can only combine shuffles of the same vector register size.");
22171 if (!isTargetShuffle(Op.getOpcode()))
22173 SmallVector<int, 16> OpMask;
22175 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22176 // We only can combine unary shuffles which we can decode the mask for.
22177 if (!HaveMask || !IsUnary)
22180 assert(VT.getVectorNumElements() == OpMask.size() &&
22181 "Different mask size from vector size!");
22182 assert(((RootMask.size() > OpMask.size() &&
22183 RootMask.size() % OpMask.size() == 0) ||
22184 (OpMask.size() > RootMask.size() &&
22185 OpMask.size() % RootMask.size() == 0) ||
22186 OpMask.size() == RootMask.size()) &&
22187 "The smaller number of elements must divide the larger.");
22188 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22189 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22190 assert(((RootRatio == 1 && OpRatio == 1) ||
22191 (RootRatio == 1) != (OpRatio == 1)) &&
22192 "Must not have a ratio for both incoming and op masks!");
22194 SmallVector<int, 16> Mask;
22195 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22197 // Merge this shuffle operation's mask into our accumulated mask. Note that
22198 // this shuffle's mask will be the first applied to the input, followed by the
22199 // root mask to get us all the way to the root value arrangement. The reason
22200 // for this order is that we are recursing up the operation chain.
22201 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22202 int RootIdx = i / RootRatio;
22203 if (RootMask[RootIdx] < 0) {
22204 // This is a zero or undef lane, we're done.
22205 Mask.push_back(RootMask[RootIdx]);
22209 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22210 int OpIdx = RootMaskedIdx / OpRatio;
22211 if (OpMask[OpIdx] < 0) {
22212 // The incoming lanes are zero or undef, it doesn't matter which ones we
22214 Mask.push_back(OpMask[OpIdx]);
22218 // Ok, we have non-zero lanes, map them through.
22219 Mask.push_back(OpMask[OpIdx] * OpRatio +
22220 RootMaskedIdx % OpRatio);
22223 // See if we can recurse into the operand to combine more things.
22224 switch (Op.getOpcode()) {
22225 case X86ISD::PSHUFB:
22227 case X86ISD::PSHUFD:
22228 case X86ISD::PSHUFHW:
22229 case X86ISD::PSHUFLW:
22230 if (Op.getOperand(0).hasOneUse() &&
22231 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22232 HasPSHUFB, DAG, DCI, Subtarget))
22236 case X86ISD::UNPCKL:
22237 case X86ISD::UNPCKH:
22238 assert(Op.getOperand(0) == Op.getOperand(1) &&
22239 "We only combine unary shuffles!");
22240 // We can't check for single use, we have to check that this shuffle is the
22242 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22243 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22244 HasPSHUFB, DAG, DCI, Subtarget))
22249 // Minor canonicalization of the accumulated shuffle mask to make it easier
22250 // to match below. All this does is detect masks with squential pairs of
22251 // elements, and shrink them to the half-width mask. It does this in a loop
22252 // so it will reduce the size of the mask to the minimal width mask which
22253 // performs an equivalent shuffle.
22254 SmallVector<int, 16> WidenedMask;
22255 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22256 Mask = std::move(WidenedMask);
22257 WidenedMask.clear();
22260 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22264 /// \brief Get the PSHUF-style mask from PSHUF node.
22266 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22267 /// PSHUF-style masks that can be reused with such instructions.
22268 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22269 MVT VT = N.getSimpleValueType();
22270 SmallVector<int, 4> Mask;
22272 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22276 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22277 // matter. Check that the upper masks are repeats and remove them.
22278 if (VT.getSizeInBits() > 128) {
22279 int LaneElts = 128 / VT.getScalarSizeInBits();
22281 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22282 for (int j = 0; j < LaneElts; ++j)
22283 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22284 "Mask doesn't repeat in high 128-bit lanes!");
22286 Mask.resize(LaneElts);
22289 switch (N.getOpcode()) {
22290 case X86ISD::PSHUFD:
22292 case X86ISD::PSHUFLW:
22295 case X86ISD::PSHUFHW:
22296 Mask.erase(Mask.begin(), Mask.begin() + 4);
22297 for (int &M : Mask)
22301 llvm_unreachable("No valid shuffle instruction found!");
22305 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22307 /// We walk up the chain and look for a combinable shuffle, skipping over
22308 /// shuffles that we could hoist this shuffle's transformation past without
22309 /// altering anything.
22311 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22313 TargetLowering::DAGCombinerInfo &DCI) {
22314 assert(N.getOpcode() == X86ISD::PSHUFD &&
22315 "Called with something other than an x86 128-bit half shuffle!");
22318 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22319 // of the shuffles in the chain so that we can form a fresh chain to replace
22321 SmallVector<SDValue, 8> Chain;
22322 SDValue V = N.getOperand(0);
22323 for (; V.hasOneUse(); V = V.getOperand(0)) {
22324 switch (V.getOpcode()) {
22326 return SDValue(); // Nothing combined!
22329 // Skip bitcasts as we always know the type for the target specific
22333 case X86ISD::PSHUFD:
22334 // Found another dword shuffle.
22337 case X86ISD::PSHUFLW:
22338 // Check that the low words (being shuffled) are the identity in the
22339 // dword shuffle, and the high words are self-contained.
22340 if (Mask[0] != 0 || Mask[1] != 1 ||
22341 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22344 Chain.push_back(V);
22347 case X86ISD::PSHUFHW:
22348 // Check that the high words (being shuffled) are the identity in the
22349 // dword shuffle, and the low words are self-contained.
22350 if (Mask[2] != 2 || Mask[3] != 3 ||
22351 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22354 Chain.push_back(V);
22357 case X86ISD::UNPCKL:
22358 case X86ISD::UNPCKH:
22359 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22360 // shuffle into a preceding word shuffle.
22361 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22362 V.getSimpleValueType().getScalarType() != MVT::i16)
22365 // Search for a half-shuffle which we can combine with.
22366 unsigned CombineOp =
22367 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22368 if (V.getOperand(0) != V.getOperand(1) ||
22369 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22371 Chain.push_back(V);
22372 V = V.getOperand(0);
22374 switch (V.getOpcode()) {
22376 return SDValue(); // Nothing to combine.
22378 case X86ISD::PSHUFLW:
22379 case X86ISD::PSHUFHW:
22380 if (V.getOpcode() == CombineOp)
22383 Chain.push_back(V);
22387 V = V.getOperand(0);
22391 } while (V.hasOneUse());
22394 // Break out of the loop if we break out of the switch.
22398 if (!V.hasOneUse())
22399 // We fell out of the loop without finding a viable combining instruction.
22402 // Merge this node's mask and our incoming mask.
22403 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22404 for (int &M : Mask)
22406 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22407 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22409 // Rebuild the chain around this new shuffle.
22410 while (!Chain.empty()) {
22411 SDValue W = Chain.pop_back_val();
22413 if (V.getValueType() != W.getOperand(0).getValueType())
22414 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22416 switch (W.getOpcode()) {
22418 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22420 case X86ISD::UNPCKL:
22421 case X86ISD::UNPCKH:
22422 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22425 case X86ISD::PSHUFD:
22426 case X86ISD::PSHUFLW:
22427 case X86ISD::PSHUFHW:
22428 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22432 if (V.getValueType() != N.getValueType())
22433 V = DAG.getBitcast(N.getValueType(), V);
22435 // Return the new chain to replace N.
22439 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22442 /// We walk up the chain, skipping shuffles of the other half and looking
22443 /// through shuffles which switch halves trying to find a shuffle of the same
22444 /// pair of dwords.
22445 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22447 TargetLowering::DAGCombinerInfo &DCI) {
22449 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22450 "Called with something other than an x86 128-bit half shuffle!");
22452 unsigned CombineOpcode = N.getOpcode();
22454 // Walk up a single-use chain looking for a combinable shuffle.
22455 SDValue V = N.getOperand(0);
22456 for (; V.hasOneUse(); V = V.getOperand(0)) {
22457 switch (V.getOpcode()) {
22459 return false; // Nothing combined!
22462 // Skip bitcasts as we always know the type for the target specific
22466 case X86ISD::PSHUFLW:
22467 case X86ISD::PSHUFHW:
22468 if (V.getOpcode() == CombineOpcode)
22471 // Other-half shuffles are no-ops.
22474 // Break out of the loop if we break out of the switch.
22478 if (!V.hasOneUse())
22479 // We fell out of the loop without finding a viable combining instruction.
22482 // Combine away the bottom node as its shuffle will be accumulated into
22483 // a preceding shuffle.
22484 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22486 // Record the old value.
22489 // Merge this node's mask and our incoming mask (adjusted to account for all
22490 // the pshufd instructions encountered).
22491 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22492 for (int &M : Mask)
22494 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22495 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22497 // Check that the shuffles didn't cancel each other out. If not, we need to
22498 // combine to the new one.
22500 // Replace the combinable shuffle with the combined one, updating all users
22501 // so that we re-evaluate the chain here.
22502 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22507 /// \brief Try to combine x86 target specific shuffles.
22508 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22509 TargetLowering::DAGCombinerInfo &DCI,
22510 const X86Subtarget *Subtarget) {
22512 MVT VT = N.getSimpleValueType();
22513 SmallVector<int, 4> Mask;
22515 switch (N.getOpcode()) {
22516 case X86ISD::PSHUFD:
22517 case X86ISD::PSHUFLW:
22518 case X86ISD::PSHUFHW:
22519 Mask = getPSHUFShuffleMask(N);
22520 assert(Mask.size() == 4);
22526 // Nuke no-op shuffles that show up after combining.
22527 if (isNoopShuffleMask(Mask))
22528 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22530 // Look for simplifications involving one or two shuffle instructions.
22531 SDValue V = N.getOperand(0);
22532 switch (N.getOpcode()) {
22535 case X86ISD::PSHUFLW:
22536 case X86ISD::PSHUFHW:
22537 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22539 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22540 return SDValue(); // We combined away this shuffle, so we're done.
22542 // See if this reduces to a PSHUFD which is no more expensive and can
22543 // combine with more operations. Note that it has to at least flip the
22544 // dwords as otherwise it would have been removed as a no-op.
22545 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22546 int DMask[] = {0, 1, 2, 3};
22547 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22548 DMask[DOffset + 0] = DOffset + 1;
22549 DMask[DOffset + 1] = DOffset + 0;
22550 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22551 V = DAG.getBitcast(DVT, V);
22552 DCI.AddToWorklist(V.getNode());
22553 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22554 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22555 DCI.AddToWorklist(V.getNode());
22556 return DAG.getBitcast(VT, V);
22559 // Look for shuffle patterns which can be implemented as a single unpack.
22560 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22561 // only works when we have a PSHUFD followed by two half-shuffles.
22562 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22563 (V.getOpcode() == X86ISD::PSHUFLW ||
22564 V.getOpcode() == X86ISD::PSHUFHW) &&
22565 V.getOpcode() != N.getOpcode() &&
22567 SDValue D = V.getOperand(0);
22568 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22569 D = D.getOperand(0);
22570 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22571 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22572 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22573 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22574 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22576 for (int i = 0; i < 4; ++i) {
22577 WordMask[i + NOffset] = Mask[i] + NOffset;
22578 WordMask[i + VOffset] = VMask[i] + VOffset;
22580 // Map the word mask through the DWord mask.
22582 for (int i = 0; i < 8; ++i)
22583 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22584 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22585 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22586 // We can replace all three shuffles with an unpack.
22587 V = DAG.getBitcast(VT, D.getOperand(0));
22588 DCI.AddToWorklist(V.getNode());
22589 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22598 case X86ISD::PSHUFD:
22599 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22608 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22610 /// We combine this directly on the abstract vector shuffle nodes so it is
22611 /// easier to generically match. We also insert dummy vector shuffle nodes for
22612 /// the operands which explicitly discard the lanes which are unused by this
22613 /// operation to try to flow through the rest of the combiner the fact that
22614 /// they're unused.
22615 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22617 EVT VT = N->getValueType(0);
22619 // We only handle target-independent shuffles.
22620 // FIXME: It would be easy and harmless to use the target shuffle mask
22621 // extraction tool to support more.
22622 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22625 auto *SVN = cast<ShuffleVectorSDNode>(N);
22626 ArrayRef<int> Mask = SVN->getMask();
22627 SDValue V1 = N->getOperand(0);
22628 SDValue V2 = N->getOperand(1);
22630 // We require the first shuffle operand to be the SUB node, and the second to
22631 // be the ADD node.
22632 // FIXME: We should support the commuted patterns.
22633 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22636 // If there are other uses of these operations we can't fold them.
22637 if (!V1->hasOneUse() || !V2->hasOneUse())
22640 // Ensure that both operations have the same operands. Note that we can
22641 // commute the FADD operands.
22642 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22643 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22644 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22647 // We're looking for blends between FADD and FSUB nodes. We insist on these
22648 // nodes being lined up in a specific expected pattern.
22649 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22650 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22651 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22654 // Only specific types are legal at this point, assert so we notice if and
22655 // when these change.
22656 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22657 VT == MVT::v4f64) &&
22658 "Unknown vector type encountered!");
22660 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22663 /// PerformShuffleCombine - Performs several different shuffle combines.
22664 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22665 TargetLowering::DAGCombinerInfo &DCI,
22666 const X86Subtarget *Subtarget) {
22668 SDValue N0 = N->getOperand(0);
22669 SDValue N1 = N->getOperand(1);
22670 EVT VT = N->getValueType(0);
22672 // Don't create instructions with illegal types after legalize types has run.
22673 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22674 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22677 // If we have legalized the vector types, look for blends of FADD and FSUB
22678 // nodes that we can fuse into an ADDSUB node.
22679 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22680 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22683 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22684 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22685 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22686 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22688 // During Type Legalization, when promoting illegal vector types,
22689 // the backend might introduce new shuffle dag nodes and bitcasts.
22691 // This code performs the following transformation:
22692 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22693 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22695 // We do this only if both the bitcast and the BINOP dag nodes have
22696 // one use. Also, perform this transformation only if the new binary
22697 // operation is legal. This is to avoid introducing dag nodes that
22698 // potentially need to be further expanded (or custom lowered) into a
22699 // less optimal sequence of dag nodes.
22700 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22701 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22702 N0.getOpcode() == ISD::BITCAST) {
22703 SDValue BC0 = N0.getOperand(0);
22704 EVT SVT = BC0.getValueType();
22705 unsigned Opcode = BC0.getOpcode();
22706 unsigned NumElts = VT.getVectorNumElements();
22708 if (BC0.hasOneUse() && SVT.isVector() &&
22709 SVT.getVectorNumElements() * 2 == NumElts &&
22710 TLI.isOperationLegal(Opcode, VT)) {
22711 bool CanFold = false;
22723 unsigned SVTNumElts = SVT.getVectorNumElements();
22724 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22725 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22726 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22727 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22728 CanFold = SVOp->getMaskElt(i) < 0;
22731 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22732 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22733 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22734 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22739 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22740 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22741 // consecutive, non-overlapping, and in the right order.
22742 SmallVector<SDValue, 16> Elts;
22743 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22744 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22746 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
22749 if (isTargetShuffle(N->getOpcode())) {
22751 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22752 if (Shuffle.getNode())
22755 // Try recursively combining arbitrary sequences of x86 shuffle
22756 // instructions into higher-order shuffles. We do this after combining
22757 // specific PSHUF instruction sequences into their minimal form so that we
22758 // can evaluate how many specialized shuffle instructions are involved in
22759 // a particular chain.
22760 SmallVector<int, 1> NonceMask; // Just a placeholder.
22761 NonceMask.push_back(0);
22762 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22763 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22765 return SDValue(); // This routine will use CombineTo to replace N.
22771 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22772 /// specific shuffle of a load can be folded into a single element load.
22773 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22774 /// shuffles have been custom lowered so we need to handle those here.
22775 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22776 TargetLowering::DAGCombinerInfo &DCI) {
22777 if (DCI.isBeforeLegalizeOps())
22780 SDValue InVec = N->getOperand(0);
22781 SDValue EltNo = N->getOperand(1);
22783 if (!isa<ConstantSDNode>(EltNo))
22786 EVT OriginalVT = InVec.getValueType();
22788 if (InVec.getOpcode() == ISD::BITCAST) {
22789 // Don't duplicate a load with other uses.
22790 if (!InVec.hasOneUse())
22792 EVT BCVT = InVec.getOperand(0).getValueType();
22793 if (!BCVT.isVector() ||
22794 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22796 InVec = InVec.getOperand(0);
22799 EVT CurrentVT = InVec.getValueType();
22801 if (!isTargetShuffle(InVec.getOpcode()))
22804 // Don't duplicate a load with other uses.
22805 if (!InVec.hasOneUse())
22808 SmallVector<int, 16> ShuffleMask;
22810 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22811 ShuffleMask, UnaryShuffle))
22814 // Select the input vector, guarding against out of range extract vector.
22815 unsigned NumElems = CurrentVT.getVectorNumElements();
22816 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22817 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22818 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22819 : InVec.getOperand(1);
22821 // If inputs to shuffle are the same for both ops, then allow 2 uses
22822 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
22823 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22825 if (LdNode.getOpcode() == ISD::BITCAST) {
22826 // Don't duplicate a load with other uses.
22827 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22830 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22831 LdNode = LdNode.getOperand(0);
22834 if (!ISD::isNormalLoad(LdNode.getNode()))
22837 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22839 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22842 EVT EltVT = N->getValueType(0);
22843 // If there's a bitcast before the shuffle, check if the load type and
22844 // alignment is valid.
22845 unsigned Align = LN0->getAlignment();
22846 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22847 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
22848 EltVT.getTypeForEVT(*DAG.getContext()));
22850 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22853 // All checks match so transform back to vector_shuffle so that DAG combiner
22854 // can finish the job
22857 // Create shuffle node taking into account the case that its a unary shuffle
22858 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22859 : InVec.getOperand(1);
22860 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22861 InVec.getOperand(0), Shuffle,
22863 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
22864 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22868 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
22869 /// special and don't usually play with other vector types, it's better to
22870 /// handle them early to be sure we emit efficient code by avoiding
22871 /// store-load conversions.
22872 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
22873 if (N->getValueType(0) != MVT::x86mmx ||
22874 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
22875 N->getOperand(0)->getValueType(0) != MVT::v2i32)
22878 SDValue V = N->getOperand(0);
22879 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
22880 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
22881 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
22882 N->getValueType(0), V.getOperand(0));
22887 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22888 /// generation and convert it from being a bunch of shuffles and extracts
22889 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22890 /// storing the value and loading scalars back, while for x64 we should
22891 /// use 64-bit extracts and shifts.
22892 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22893 TargetLowering::DAGCombinerInfo &DCI) {
22894 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
22897 SDValue InputVector = N->getOperand(0);
22898 SDLoc dl(InputVector);
22899 // Detect mmx to i32 conversion through a v2i32 elt extract.
22900 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
22901 N->getValueType(0) == MVT::i32 &&
22902 InputVector.getValueType() == MVT::v2i32) {
22904 // The bitcast source is a direct mmx result.
22905 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
22906 if (MMXSrc.getValueType() == MVT::x86mmx)
22907 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22908 N->getValueType(0),
22909 InputVector.getNode()->getOperand(0));
22911 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
22912 SDValue MMXSrcOp = MMXSrc.getOperand(0);
22913 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
22914 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
22915 MMXSrcOp.getOpcode() == ISD::BITCAST &&
22916 MMXSrcOp.getValueType() == MVT::v1i64 &&
22917 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
22918 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22919 N->getValueType(0),
22920 MMXSrcOp.getOperand(0));
22923 EVT VT = N->getValueType(0);
22925 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
22926 InputVector.getOpcode() == ISD::BITCAST &&
22927 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
22928 uint64_t ExtractedElt =
22929 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
22930 uint64_t InputValue =
22931 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
22932 uint64_t Res = (InputValue >> ExtractedElt) & 1;
22933 return DAG.getConstant(Res, dl, MVT::i1);
22935 // Only operate on vectors of 4 elements, where the alternative shuffling
22936 // gets to be more expensive.
22937 if (InputVector.getValueType() != MVT::v4i32)
22940 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22941 // single use which is a sign-extend or zero-extend, and all elements are
22943 SmallVector<SDNode *, 4> Uses;
22944 unsigned ExtractedElements = 0;
22945 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22946 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22947 if (UI.getUse().getResNo() != InputVector.getResNo())
22950 SDNode *Extract = *UI;
22951 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22954 if (Extract->getValueType(0) != MVT::i32)
22956 if (!Extract->hasOneUse())
22958 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22959 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22961 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22964 // Record which element was extracted.
22965 ExtractedElements |=
22966 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22968 Uses.push_back(Extract);
22971 // If not all the elements were used, this may not be worthwhile.
22972 if (ExtractedElements != 15)
22975 // Ok, we've now decided to do the transformation.
22976 // If 64-bit shifts are legal, use the extract-shift sequence,
22977 // otherwise bounce the vector off the cache.
22978 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22981 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22982 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
22983 auto &DL = DAG.getDataLayout();
22984 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
22985 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22986 DAG.getConstant(0, dl, VecIdxTy));
22987 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22988 DAG.getConstant(1, dl, VecIdxTy));
22990 SDValue ShAmt = DAG.getConstant(
22991 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
22992 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22993 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22994 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22995 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22996 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22997 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22999 // Store the value to a temporary stack slot.
23000 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23001 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23002 MachinePointerInfo(), false, false, 0);
23004 EVT ElementType = InputVector.getValueType().getVectorElementType();
23005 unsigned EltSize = ElementType.getSizeInBits() / 8;
23007 // Replace each use (extract) with a load of the appropriate element.
23008 for (unsigned i = 0; i < 4; ++i) {
23009 uint64_t Offset = EltSize * i;
23010 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23011 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23013 SDValue ScalarAddr =
23014 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23016 // Load the scalar.
23017 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23018 ScalarAddr, MachinePointerInfo(),
23019 false, false, false, 0);
23024 // Replace the extracts
23025 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23026 UE = Uses.end(); UI != UE; ++UI) {
23027 SDNode *Extract = *UI;
23029 SDValue Idx = Extract->getOperand(1);
23030 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23031 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23034 // The replacement was made in place; don't return anything.
23039 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23040 const X86Subtarget *Subtarget) {
23042 SDValue Cond = N->getOperand(0);
23043 SDValue LHS = N->getOperand(1);
23044 SDValue RHS = N->getOperand(2);
23046 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23047 SDValue CondSrc = Cond->getOperand(0);
23048 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23049 Cond = CondSrc->getOperand(0);
23052 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23055 // A vselect where all conditions and data are constants can be optimized into
23056 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23057 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23058 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23061 unsigned MaskValue = 0;
23062 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23065 MVT VT = N->getSimpleValueType(0);
23066 unsigned NumElems = VT.getVectorNumElements();
23067 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23068 for (unsigned i = 0; i < NumElems; ++i) {
23069 // Be sure we emit undef where we can.
23070 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23071 ShuffleMask[i] = -1;
23073 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23076 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23077 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23079 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23082 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23084 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23085 TargetLowering::DAGCombinerInfo &DCI,
23086 const X86Subtarget *Subtarget) {
23088 SDValue Cond = N->getOperand(0);
23089 // Get the LHS/RHS of the select.
23090 SDValue LHS = N->getOperand(1);
23091 SDValue RHS = N->getOperand(2);
23092 EVT VT = LHS.getValueType();
23093 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23095 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23096 // instructions match the semantics of the common C idiom x<y?x:y but not
23097 // x<=y?x:y, because of how they handle negative zero (which can be
23098 // ignored in unsafe-math mode).
23099 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23100 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23101 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23102 (Subtarget->hasSSE2() ||
23103 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23104 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23106 unsigned Opcode = 0;
23107 // Check for x CC y ? x : y.
23108 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23109 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23113 // Converting this to a min would handle NaNs incorrectly, and swapping
23114 // the operands would cause it to handle comparisons between positive
23115 // and negative zero incorrectly.
23116 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23117 if (!DAG.getTarget().Options.UnsafeFPMath &&
23118 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23120 std::swap(LHS, RHS);
23122 Opcode = X86ISD::FMIN;
23125 // Converting this to a min would handle comparisons between positive
23126 // and negative zero incorrectly.
23127 if (!DAG.getTarget().Options.UnsafeFPMath &&
23128 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23130 Opcode = X86ISD::FMIN;
23133 // Converting this to a min would handle both negative zeros and NaNs
23134 // incorrectly, but we can swap the operands to fix both.
23135 std::swap(LHS, RHS);
23139 Opcode = X86ISD::FMIN;
23143 // Converting this to a max would handle comparisons between positive
23144 // and negative zero incorrectly.
23145 if (!DAG.getTarget().Options.UnsafeFPMath &&
23146 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23148 Opcode = X86ISD::FMAX;
23151 // Converting this to a max would handle NaNs incorrectly, and swapping
23152 // the operands would cause it to handle comparisons between positive
23153 // and negative zero incorrectly.
23154 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23155 if (!DAG.getTarget().Options.UnsafeFPMath &&
23156 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23158 std::swap(LHS, RHS);
23160 Opcode = X86ISD::FMAX;
23163 // Converting this to a max would handle both negative zeros and NaNs
23164 // incorrectly, but we can swap the operands to fix both.
23165 std::swap(LHS, RHS);
23169 Opcode = X86ISD::FMAX;
23172 // Check for x CC y ? y : x -- a min/max with reversed arms.
23173 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23174 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23178 // Converting this to a min would handle comparisons between positive
23179 // and negative zero incorrectly, and swapping the operands would
23180 // cause it to handle NaNs incorrectly.
23181 if (!DAG.getTarget().Options.UnsafeFPMath &&
23182 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23183 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23185 std::swap(LHS, RHS);
23187 Opcode = X86ISD::FMIN;
23190 // Converting this to a min would handle NaNs incorrectly.
23191 if (!DAG.getTarget().Options.UnsafeFPMath &&
23192 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23194 Opcode = X86ISD::FMIN;
23197 // Converting this to a min would handle both negative zeros and NaNs
23198 // incorrectly, but we can swap the operands to fix both.
23199 std::swap(LHS, RHS);
23203 Opcode = X86ISD::FMIN;
23207 // Converting this to a max would handle NaNs incorrectly.
23208 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23210 Opcode = X86ISD::FMAX;
23213 // Converting this to a max would handle comparisons between positive
23214 // and negative zero incorrectly, and swapping the operands would
23215 // cause it to handle NaNs incorrectly.
23216 if (!DAG.getTarget().Options.UnsafeFPMath &&
23217 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23218 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23220 std::swap(LHS, RHS);
23222 Opcode = X86ISD::FMAX;
23225 // Converting this to a max would handle both negative zeros and NaNs
23226 // incorrectly, but we can swap the operands to fix both.
23227 std::swap(LHS, RHS);
23231 Opcode = X86ISD::FMAX;
23237 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23240 EVT CondVT = Cond.getValueType();
23241 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23242 CondVT.getVectorElementType() == MVT::i1) {
23243 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23244 // lowering on KNL. In this case we convert it to
23245 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23246 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23247 // Since SKX these selects have a proper lowering.
23248 EVT OpVT = LHS.getValueType();
23249 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23250 (OpVT.getVectorElementType() == MVT::i8 ||
23251 OpVT.getVectorElementType() == MVT::i16) &&
23252 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23253 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23254 DCI.AddToWorklist(Cond.getNode());
23255 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23258 // If this is a select between two integer constants, try to do some
23260 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23261 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23262 // Don't do this for crazy integer types.
23263 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23264 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23265 // so that TrueC (the true value) is larger than FalseC.
23266 bool NeedsCondInvert = false;
23268 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23269 // Efficiently invertible.
23270 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23271 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23272 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23273 NeedsCondInvert = true;
23274 std::swap(TrueC, FalseC);
23277 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23278 if (FalseC->getAPIntValue() == 0 &&
23279 TrueC->getAPIntValue().isPowerOf2()) {
23280 if (NeedsCondInvert) // Invert the condition if needed.
23281 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23282 DAG.getConstant(1, DL, Cond.getValueType()));
23284 // Zero extend the condition if needed.
23285 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23287 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23288 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23289 DAG.getConstant(ShAmt, DL, MVT::i8));
23292 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23293 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23294 if (NeedsCondInvert) // Invert the condition if needed.
23295 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23296 DAG.getConstant(1, DL, Cond.getValueType()));
23298 // Zero extend the condition if needed.
23299 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23300 FalseC->getValueType(0), Cond);
23301 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23302 SDValue(FalseC, 0));
23305 // Optimize cases that will turn into an LEA instruction. This requires
23306 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23307 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23308 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23309 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23311 bool isFastMultiplier = false;
23313 switch ((unsigned char)Diff) {
23315 case 1: // result = add base, cond
23316 case 2: // result = lea base( , cond*2)
23317 case 3: // result = lea base(cond, cond*2)
23318 case 4: // result = lea base( , cond*4)
23319 case 5: // result = lea base(cond, cond*4)
23320 case 8: // result = lea base( , cond*8)
23321 case 9: // result = lea base(cond, cond*8)
23322 isFastMultiplier = true;
23327 if (isFastMultiplier) {
23328 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23329 if (NeedsCondInvert) // Invert the condition if needed.
23330 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23331 DAG.getConstant(1, DL, Cond.getValueType()));
23333 // Zero extend the condition if needed.
23334 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23336 // Scale the condition by the difference.
23338 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23339 DAG.getConstant(Diff, DL,
23340 Cond.getValueType()));
23342 // Add the base if non-zero.
23343 if (FalseC->getAPIntValue() != 0)
23344 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23345 SDValue(FalseC, 0));
23352 // Canonicalize max and min:
23353 // (x > y) ? x : y -> (x >= y) ? x : y
23354 // (x < y) ? x : y -> (x <= y) ? x : y
23355 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23356 // the need for an extra compare
23357 // against zero. e.g.
23358 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23360 // testl %edi, %edi
23362 // cmovgl %edi, %eax
23366 // cmovsl %eax, %edi
23367 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23368 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23369 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23370 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23375 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23376 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23377 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23378 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23383 // Early exit check
23384 if (!TLI.isTypeLegal(VT))
23387 // Match VSELECTs into subs with unsigned saturation.
23388 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23389 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23390 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23391 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23392 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23394 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23395 // left side invert the predicate to simplify logic below.
23397 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23399 CC = ISD::getSetCCInverse(CC, true);
23400 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23404 if (Other.getNode() && Other->getNumOperands() == 2 &&
23405 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23406 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23407 SDValue CondRHS = Cond->getOperand(1);
23409 // Look for a general sub with unsigned saturation first.
23410 // x >= y ? x-y : 0 --> subus x, y
23411 // x > y ? x-y : 0 --> subus x, y
23412 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23413 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23414 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23416 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23417 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23418 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23419 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23420 // If the RHS is a constant we have to reverse the const
23421 // canonicalization.
23422 // x > C-1 ? x+-C : 0 --> subus x, C
23423 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23424 CondRHSConst->getAPIntValue() ==
23425 (-OpRHSConst->getAPIntValue() - 1))
23426 return DAG.getNode(
23427 X86ISD::SUBUS, DL, VT, OpLHS,
23428 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23430 // Another special case: If C was a sign bit, the sub has been
23431 // canonicalized into a xor.
23432 // FIXME: Would it be better to use computeKnownBits to determine
23433 // whether it's safe to decanonicalize the xor?
23434 // x s< 0 ? x^C : 0 --> subus x, C
23435 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23436 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23437 OpRHSConst->getAPIntValue().isSignBit())
23438 // Note that we have to rebuild the RHS constant here to ensure we
23439 // don't rely on particular values of undef lanes.
23440 return DAG.getNode(
23441 X86ISD::SUBUS, DL, VT, OpLHS,
23442 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23447 // Simplify vector selection if condition value type matches vselect
23449 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23450 assert(Cond.getValueType().isVector() &&
23451 "vector select expects a vector selector!");
23453 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23454 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23456 // Try invert the condition if true value is not all 1s and false value
23458 if (!TValIsAllOnes && !FValIsAllZeros &&
23459 // Check if the selector will be produced by CMPP*/PCMP*
23460 Cond.getOpcode() == ISD::SETCC &&
23461 // Check if SETCC has already been promoted
23462 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23464 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23465 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23467 if (TValIsAllZeros || FValIsAllOnes) {
23468 SDValue CC = Cond.getOperand(2);
23469 ISD::CondCode NewCC =
23470 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23471 Cond.getOperand(0).getValueType().isInteger());
23472 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23473 std::swap(LHS, RHS);
23474 TValIsAllOnes = FValIsAllOnes;
23475 FValIsAllZeros = TValIsAllZeros;
23479 if (TValIsAllOnes || FValIsAllZeros) {
23482 if (TValIsAllOnes && FValIsAllZeros)
23484 else if (TValIsAllOnes)
23486 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23487 else if (FValIsAllZeros)
23488 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23489 DAG.getBitcast(CondVT, LHS));
23491 return DAG.getBitcast(VT, Ret);
23495 // We should generate an X86ISD::BLENDI from a vselect if its argument
23496 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23497 // constants. This specific pattern gets generated when we split a
23498 // selector for a 512 bit vector in a machine without AVX512 (but with
23499 // 256-bit vectors), during legalization:
23501 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23503 // Iff we find this pattern and the build_vectors are built from
23504 // constants, we translate the vselect into a shuffle_vector that we
23505 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23506 if ((N->getOpcode() == ISD::VSELECT ||
23507 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23508 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23509 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23510 if (Shuffle.getNode())
23514 // If this is a *dynamic* select (non-constant condition) and we can match
23515 // this node with one of the variable blend instructions, restructure the
23516 // condition so that the blends can use the high bit of each element and use
23517 // SimplifyDemandedBits to simplify the condition operand.
23518 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23519 !DCI.isBeforeLegalize() &&
23520 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23521 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23523 // Don't optimize vector selects that map to mask-registers.
23527 // We can only handle the cases where VSELECT is directly legal on the
23528 // subtarget. We custom lower VSELECT nodes with constant conditions and
23529 // this makes it hard to see whether a dynamic VSELECT will correctly
23530 // lower, so we both check the operation's status and explicitly handle the
23531 // cases where a *dynamic* blend will fail even though a constant-condition
23532 // blend could be custom lowered.
23533 // FIXME: We should find a better way to handle this class of problems.
23534 // Potentially, we should combine constant-condition vselect nodes
23535 // pre-legalization into shuffles and not mark as many types as custom
23537 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23539 // FIXME: We don't support i16-element blends currently. We could and
23540 // should support them by making *all* the bits in the condition be set
23541 // rather than just the high bit and using an i8-element blend.
23542 if (VT.getScalarType() == MVT::i16)
23544 // Dynamic blending was only available from SSE4.1 onward.
23545 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23547 // Byte blends are only available in AVX2
23548 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23549 !Subtarget->hasAVX2())
23552 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23553 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23555 APInt KnownZero, KnownOne;
23556 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23557 DCI.isBeforeLegalizeOps());
23558 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23559 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23561 // If we changed the computation somewhere in the DAG, this change
23562 // will affect all users of Cond.
23563 // Make sure it is fine and update all the nodes so that we do not
23564 // use the generic VSELECT anymore. Otherwise, we may perform
23565 // wrong optimizations as we messed up with the actual expectation
23566 // for the vector boolean values.
23567 if (Cond != TLO.Old) {
23568 // Check all uses of that condition operand to check whether it will be
23569 // consumed by non-BLEND instructions, which may depend on all bits are
23571 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23573 if (I->getOpcode() != ISD::VSELECT)
23574 // TODO: Add other opcodes eventually lowered into BLEND.
23577 // Update all the users of the condition, before committing the change,
23578 // so that the VSELECT optimizations that expect the correct vector
23579 // boolean value will not be triggered.
23580 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23582 DAG.ReplaceAllUsesOfValueWith(
23584 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23585 Cond, I->getOperand(1), I->getOperand(2)));
23586 DCI.CommitTargetLoweringOpt(TLO);
23589 // At this point, only Cond is changed. Change the condition
23590 // just for N to keep the opportunity to optimize all other
23591 // users their own way.
23592 DAG.ReplaceAllUsesOfValueWith(
23594 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23595 TLO.New, N->getOperand(1), N->getOperand(2)));
23603 // Check whether a boolean test is testing a boolean value generated by
23604 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23607 // Simplify the following patterns:
23608 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23609 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23610 // to (Op EFLAGS Cond)
23612 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23613 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23614 // to (Op EFLAGS !Cond)
23616 // where Op could be BRCOND or CMOV.
23618 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23619 // Quit if not CMP and SUB with its value result used.
23620 if (Cmp.getOpcode() != X86ISD::CMP &&
23621 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23624 // Quit if not used as a boolean value.
23625 if (CC != X86::COND_E && CC != X86::COND_NE)
23628 // Check CMP operands. One of them should be 0 or 1 and the other should be
23629 // an SetCC or extended from it.
23630 SDValue Op1 = Cmp.getOperand(0);
23631 SDValue Op2 = Cmp.getOperand(1);
23634 const ConstantSDNode* C = nullptr;
23635 bool needOppositeCond = (CC == X86::COND_E);
23636 bool checkAgainstTrue = false; // Is it a comparison against 1?
23638 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23640 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23642 else // Quit if all operands are not constants.
23645 if (C->getZExtValue() == 1) {
23646 needOppositeCond = !needOppositeCond;
23647 checkAgainstTrue = true;
23648 } else if (C->getZExtValue() != 0)
23649 // Quit if the constant is neither 0 or 1.
23652 bool truncatedToBoolWithAnd = false;
23653 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23654 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23655 SetCC.getOpcode() == ISD::TRUNCATE ||
23656 SetCC.getOpcode() == ISD::AND) {
23657 if (SetCC.getOpcode() == ISD::AND) {
23659 ConstantSDNode *CS;
23660 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23661 CS->getZExtValue() == 1)
23663 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23664 CS->getZExtValue() == 1)
23668 SetCC = SetCC.getOperand(OpIdx);
23669 truncatedToBoolWithAnd = true;
23671 SetCC = SetCC.getOperand(0);
23674 switch (SetCC.getOpcode()) {
23675 case X86ISD::SETCC_CARRY:
23676 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23677 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23678 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23679 // truncated to i1 using 'and'.
23680 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23682 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23683 "Invalid use of SETCC_CARRY!");
23685 case X86ISD::SETCC:
23686 // Set the condition code or opposite one if necessary.
23687 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23688 if (needOppositeCond)
23689 CC = X86::GetOppositeBranchCondition(CC);
23690 return SetCC.getOperand(1);
23691 case X86ISD::CMOV: {
23692 // Check whether false/true value has canonical one, i.e. 0 or 1.
23693 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23694 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23695 // Quit if true value is not a constant.
23698 // Quit if false value is not a constant.
23700 SDValue Op = SetCC.getOperand(0);
23701 // Skip 'zext' or 'trunc' node.
23702 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23703 Op.getOpcode() == ISD::TRUNCATE)
23704 Op = Op.getOperand(0);
23705 // A special case for rdrand/rdseed, where 0 is set if false cond is
23707 if ((Op.getOpcode() != X86ISD::RDRAND &&
23708 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23711 // Quit if false value is not the constant 0 or 1.
23712 bool FValIsFalse = true;
23713 if (FVal && FVal->getZExtValue() != 0) {
23714 if (FVal->getZExtValue() != 1)
23716 // If FVal is 1, opposite cond is needed.
23717 needOppositeCond = !needOppositeCond;
23718 FValIsFalse = false;
23720 // Quit if TVal is not the constant opposite of FVal.
23721 if (FValIsFalse && TVal->getZExtValue() != 1)
23723 if (!FValIsFalse && TVal->getZExtValue() != 0)
23725 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23726 if (needOppositeCond)
23727 CC = X86::GetOppositeBranchCondition(CC);
23728 return SetCC.getOperand(3);
23735 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
23737 /// (X86or (X86setcc) (X86setcc))
23738 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
23739 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
23740 X86::CondCode &CC1, SDValue &Flags,
23742 if (Cond->getOpcode() == X86ISD::CMP) {
23743 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
23744 if (!CondOp1C || !CondOp1C->isNullValue())
23747 Cond = Cond->getOperand(0);
23752 SDValue SetCC0, SetCC1;
23753 switch (Cond->getOpcode()) {
23754 default: return false;
23761 SetCC0 = Cond->getOperand(0);
23762 SetCC1 = Cond->getOperand(1);
23766 // Make sure we have SETCC nodes, using the same flags value.
23767 if (SetCC0.getOpcode() != X86ISD::SETCC ||
23768 SetCC1.getOpcode() != X86ISD::SETCC ||
23769 SetCC0->getOperand(1) != SetCC1->getOperand(1))
23772 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
23773 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
23774 Flags = SetCC0->getOperand(1);
23778 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23779 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23780 TargetLowering::DAGCombinerInfo &DCI,
23781 const X86Subtarget *Subtarget) {
23784 // If the flag operand isn't dead, don't touch this CMOV.
23785 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23788 SDValue FalseOp = N->getOperand(0);
23789 SDValue TrueOp = N->getOperand(1);
23790 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23791 SDValue Cond = N->getOperand(3);
23793 if (CC == X86::COND_E || CC == X86::COND_NE) {
23794 switch (Cond.getOpcode()) {
23798 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23799 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23800 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23806 Flags = checkBoolTestSetCCCombine(Cond, CC);
23807 if (Flags.getNode() &&
23808 // Extra check as FCMOV only supports a subset of X86 cond.
23809 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23810 SDValue Ops[] = { FalseOp, TrueOp,
23811 DAG.getConstant(CC, DL, MVT::i8), Flags };
23812 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23815 // If this is a select between two integer constants, try to do some
23816 // optimizations. Note that the operands are ordered the opposite of SELECT
23818 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23819 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23820 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23821 // larger than FalseC (the false value).
23822 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23823 CC = X86::GetOppositeBranchCondition(CC);
23824 std::swap(TrueC, FalseC);
23825 std::swap(TrueOp, FalseOp);
23828 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23829 // This is efficient for any integer data type (including i8/i16) and
23831 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23832 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23833 DAG.getConstant(CC, DL, MVT::i8), Cond);
23835 // Zero extend the condition if needed.
23836 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23838 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23839 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23840 DAG.getConstant(ShAmt, DL, MVT::i8));
23841 if (N->getNumValues() == 2) // Dead flag value?
23842 return DCI.CombineTo(N, Cond, SDValue());
23846 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23847 // for any integer data type, including i8/i16.
23848 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23849 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23850 DAG.getConstant(CC, DL, MVT::i8), Cond);
23852 // Zero extend the condition if needed.
23853 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23854 FalseC->getValueType(0), Cond);
23855 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23856 SDValue(FalseC, 0));
23858 if (N->getNumValues() == 2) // Dead flag value?
23859 return DCI.CombineTo(N, Cond, SDValue());
23863 // Optimize cases that will turn into an LEA instruction. This requires
23864 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23865 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23866 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23867 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23869 bool isFastMultiplier = false;
23871 switch ((unsigned char)Diff) {
23873 case 1: // result = add base, cond
23874 case 2: // result = lea base( , cond*2)
23875 case 3: // result = lea base(cond, cond*2)
23876 case 4: // result = lea base( , cond*4)
23877 case 5: // result = lea base(cond, cond*4)
23878 case 8: // result = lea base( , cond*8)
23879 case 9: // result = lea base(cond, cond*8)
23880 isFastMultiplier = true;
23885 if (isFastMultiplier) {
23886 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23887 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23888 DAG.getConstant(CC, DL, MVT::i8), Cond);
23889 // Zero extend the condition if needed.
23890 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23892 // Scale the condition by the difference.
23894 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23895 DAG.getConstant(Diff, DL, Cond.getValueType()));
23897 // Add the base if non-zero.
23898 if (FalseC->getAPIntValue() != 0)
23899 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23900 SDValue(FalseC, 0));
23901 if (N->getNumValues() == 2) // Dead flag value?
23902 return DCI.CombineTo(N, Cond, SDValue());
23909 // Handle these cases:
23910 // (select (x != c), e, c) -> select (x != c), e, x),
23911 // (select (x == c), c, e) -> select (x == c), x, e)
23912 // where the c is an integer constant, and the "select" is the combination
23913 // of CMOV and CMP.
23915 // The rationale for this change is that the conditional-move from a constant
23916 // needs two instructions, however, conditional-move from a register needs
23917 // only one instruction.
23919 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23920 // some instruction-combining opportunities. This opt needs to be
23921 // postponed as late as possible.
23923 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23924 // the DCI.xxxx conditions are provided to postpone the optimization as
23925 // late as possible.
23927 ConstantSDNode *CmpAgainst = nullptr;
23928 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23929 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23930 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23932 if (CC == X86::COND_NE &&
23933 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23934 CC = X86::GetOppositeBranchCondition(CC);
23935 std::swap(TrueOp, FalseOp);
23938 if (CC == X86::COND_E &&
23939 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23940 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23941 DAG.getConstant(CC, DL, MVT::i8), Cond };
23942 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23947 // Fold and/or of setcc's to double CMOV:
23948 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
23949 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
23951 // This combine lets us generate:
23952 // cmovcc1 (jcc1 if we don't have CMOV)
23958 // cmovne (jne if we don't have CMOV)
23959 // When we can't use the CMOV instruction, it might increase branch
23961 // When we can use CMOV, or when there is no mispredict, this improves
23962 // throughput and reduces register pressure.
23964 if (CC == X86::COND_NE) {
23966 X86::CondCode CC0, CC1;
23968 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
23970 std::swap(FalseOp, TrueOp);
23971 CC0 = X86::GetOppositeBranchCondition(CC0);
23972 CC1 = X86::GetOppositeBranchCondition(CC1);
23975 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
23977 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
23978 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
23979 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23980 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
23988 /// PerformMulCombine - Optimize a single multiply with constant into two
23989 /// in order to implement it with two cheaper instructions, e.g.
23990 /// LEA + SHL, LEA + LEA.
23991 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23992 TargetLowering::DAGCombinerInfo &DCI) {
23993 // An imul is usually smaller than the alternative sequence.
23994 if (DAG.getMachineFunction().getFunction()->optForMinSize())
23997 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24000 EVT VT = N->getValueType(0);
24001 if (VT != MVT::i64 && VT != MVT::i32)
24004 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24007 uint64_t MulAmt = C->getZExtValue();
24008 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24011 uint64_t MulAmt1 = 0;
24012 uint64_t MulAmt2 = 0;
24013 if ((MulAmt % 9) == 0) {
24015 MulAmt2 = MulAmt / 9;
24016 } else if ((MulAmt % 5) == 0) {
24018 MulAmt2 = MulAmt / 5;
24019 } else if ((MulAmt % 3) == 0) {
24021 MulAmt2 = MulAmt / 3;
24024 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24027 if (isPowerOf2_64(MulAmt2) &&
24028 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24029 // If second multiplifer is pow2, issue it first. We want the multiply by
24030 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24032 std::swap(MulAmt1, MulAmt2);
24035 if (isPowerOf2_64(MulAmt1))
24036 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24037 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24039 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24040 DAG.getConstant(MulAmt1, DL, VT));
24042 if (isPowerOf2_64(MulAmt2))
24043 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24044 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24046 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24047 DAG.getConstant(MulAmt2, DL, VT));
24049 // Do not add new nodes to DAG combiner worklist.
24050 DCI.CombineTo(N, NewMul, false);
24055 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24056 SDValue N0 = N->getOperand(0);
24057 SDValue N1 = N->getOperand(1);
24058 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24059 EVT VT = N0.getValueType();
24061 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24062 // since the result of setcc_c is all zero's or all ones.
24063 if (VT.isInteger() && !VT.isVector() &&
24064 N1C && N0.getOpcode() == ISD::AND &&
24065 N0.getOperand(1).getOpcode() == ISD::Constant) {
24066 SDValue N00 = N0.getOperand(0);
24067 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24068 APInt ShAmt = N1C->getAPIntValue();
24069 Mask = Mask.shl(ShAmt);
24070 bool MaskOK = false;
24071 // We can handle cases concerning bit-widening nodes containing setcc_c if
24072 // we carefully interrogate the mask to make sure we are semantics
24074 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24075 // of the underlying setcc_c operation if the setcc_c was zero extended.
24076 // Consider the following example:
24077 // zext(setcc_c) -> i32 0x0000FFFF
24078 // c1 -> i32 0x0000FFFF
24079 // c2 -> i32 0x00000001
24080 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24081 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24082 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24084 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24085 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24087 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24088 N00.getOpcode() == ISD::ANY_EXTEND) &&
24089 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24090 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24092 if (MaskOK && Mask != 0) {
24094 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24098 // Hardware support for vector shifts is sparse which makes us scalarize the
24099 // vector operations in many cases. Also, on sandybridge ADD is faster than
24101 // (shl V, 1) -> add V,V
24102 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24103 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24104 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24105 // We shift all of the values by one. In many cases we do not have
24106 // hardware support for this operation. This is better expressed as an ADD
24108 if (N1SplatC->getAPIntValue() == 1)
24109 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24115 /// \brief Returns a vector of 0s if the node in input is a vector logical
24116 /// shift by a constant amount which is known to be bigger than or equal
24117 /// to the vector element size in bits.
24118 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24119 const X86Subtarget *Subtarget) {
24120 EVT VT = N->getValueType(0);
24122 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24123 (!Subtarget->hasInt256() ||
24124 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24127 SDValue Amt = N->getOperand(1);
24129 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24130 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24131 APInt ShiftAmt = AmtSplat->getAPIntValue();
24132 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24134 // SSE2/AVX2 logical shifts always return a vector of 0s
24135 // if the shift amount is bigger than or equal to
24136 // the element size. The constant shift amount will be
24137 // encoded as a 8-bit immediate.
24138 if (ShiftAmt.trunc(8).uge(MaxAmount))
24139 return getZeroVector(VT, Subtarget, DAG, DL);
24145 /// PerformShiftCombine - Combine shifts.
24146 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24147 TargetLowering::DAGCombinerInfo &DCI,
24148 const X86Subtarget *Subtarget) {
24149 if (N->getOpcode() == ISD::SHL)
24150 if (SDValue V = PerformSHLCombine(N, DAG))
24153 // Try to fold this logical shift into a zero vector.
24154 if (N->getOpcode() != ISD::SRA)
24155 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24161 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24162 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24163 // and friends. Likewise for OR -> CMPNEQSS.
24164 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24165 TargetLowering::DAGCombinerInfo &DCI,
24166 const X86Subtarget *Subtarget) {
24169 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24170 // we're requiring SSE2 for both.
24171 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24172 SDValue N0 = N->getOperand(0);
24173 SDValue N1 = N->getOperand(1);
24174 SDValue CMP0 = N0->getOperand(1);
24175 SDValue CMP1 = N1->getOperand(1);
24178 // The SETCCs should both refer to the same CMP.
24179 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24182 SDValue CMP00 = CMP0->getOperand(0);
24183 SDValue CMP01 = CMP0->getOperand(1);
24184 EVT VT = CMP00.getValueType();
24186 if (VT == MVT::f32 || VT == MVT::f64) {
24187 bool ExpectingFlags = false;
24188 // Check for any users that want flags:
24189 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24190 !ExpectingFlags && UI != UE; ++UI)
24191 switch (UI->getOpcode()) {
24196 ExpectingFlags = true;
24198 case ISD::CopyToReg:
24199 case ISD::SIGN_EXTEND:
24200 case ISD::ZERO_EXTEND:
24201 case ISD::ANY_EXTEND:
24205 if (!ExpectingFlags) {
24206 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24207 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24209 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24210 X86::CondCode tmp = cc0;
24215 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24216 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24217 // FIXME: need symbolic constants for these magic numbers.
24218 // See X86ATTInstPrinter.cpp:printSSECC().
24219 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24220 if (Subtarget->hasAVX512()) {
24221 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24223 DAG.getConstant(x86cc, DL, MVT::i8));
24224 if (N->getValueType(0) != MVT::i1)
24225 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24229 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24230 CMP00.getValueType(), CMP00, CMP01,
24231 DAG.getConstant(x86cc, DL,
24234 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24235 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24237 if (is64BitFP && !Subtarget->is64Bit()) {
24238 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24239 // 64-bit integer, since that's not a legal type. Since
24240 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24241 // bits, but can do this little dance to extract the lowest 32 bits
24242 // and work with those going forward.
24243 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24245 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24246 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24247 Vector32, DAG.getIntPtrConstant(0, DL));
24251 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24252 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24253 DAG.getConstant(1, DL, IntVT));
24254 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24256 return OneBitOfTruth;
24264 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24265 /// so it can be folded inside ANDNP.
24266 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24267 EVT VT = N->getValueType(0);
24269 // Match direct AllOnes for 128 and 256-bit vectors
24270 if (ISD::isBuildVectorAllOnes(N))
24273 // Look through a bit convert.
24274 if (N->getOpcode() == ISD::BITCAST)
24275 N = N->getOperand(0).getNode();
24277 // Sometimes the operand may come from a insert_subvector building a 256-bit
24279 if (VT.is256BitVector() &&
24280 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24281 SDValue V1 = N->getOperand(0);
24282 SDValue V2 = N->getOperand(1);
24284 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24285 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24286 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24287 ISD::isBuildVectorAllOnes(V2.getNode()))
24294 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24295 // register. In most cases we actually compare or select YMM-sized registers
24296 // and mixing the two types creates horrible code. This method optimizes
24297 // some of the transition sequences.
24298 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24299 TargetLowering::DAGCombinerInfo &DCI,
24300 const X86Subtarget *Subtarget) {
24301 EVT VT = N->getValueType(0);
24302 if (!VT.is256BitVector())
24305 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24306 N->getOpcode() == ISD::ZERO_EXTEND ||
24307 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24309 SDValue Narrow = N->getOperand(0);
24310 EVT NarrowVT = Narrow->getValueType(0);
24311 if (!NarrowVT.is128BitVector())
24314 if (Narrow->getOpcode() != ISD::XOR &&
24315 Narrow->getOpcode() != ISD::AND &&
24316 Narrow->getOpcode() != ISD::OR)
24319 SDValue N0 = Narrow->getOperand(0);
24320 SDValue N1 = Narrow->getOperand(1);
24323 // The Left side has to be a trunc.
24324 if (N0.getOpcode() != ISD::TRUNCATE)
24327 // The type of the truncated inputs.
24328 EVT WideVT = N0->getOperand(0)->getValueType(0);
24332 // The right side has to be a 'trunc' or a constant vector.
24333 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24334 ConstantSDNode *RHSConstSplat = nullptr;
24335 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24336 RHSConstSplat = RHSBV->getConstantSplatNode();
24337 if (!RHSTrunc && !RHSConstSplat)
24340 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24342 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24345 // Set N0 and N1 to hold the inputs to the new wide operation.
24346 N0 = N0->getOperand(0);
24347 if (RHSConstSplat) {
24348 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24349 SDValue(RHSConstSplat, 0));
24350 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24351 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24352 } else if (RHSTrunc) {
24353 N1 = N1->getOperand(0);
24356 // Generate the wide operation.
24357 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24358 unsigned Opcode = N->getOpcode();
24360 case ISD::ANY_EXTEND:
24362 case ISD::ZERO_EXTEND: {
24363 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24364 APInt Mask = APInt::getAllOnesValue(InBits);
24365 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24366 return DAG.getNode(ISD::AND, DL, VT,
24367 Op, DAG.getConstant(Mask, DL, VT));
24369 case ISD::SIGN_EXTEND:
24370 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24371 Op, DAG.getValueType(NarrowVT));
24373 llvm_unreachable("Unexpected opcode");
24377 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24378 TargetLowering::DAGCombinerInfo &DCI,
24379 const X86Subtarget *Subtarget) {
24380 SDValue N0 = N->getOperand(0);
24381 SDValue N1 = N->getOperand(1);
24384 // A vector zext_in_reg may be represented as a shuffle,
24385 // feeding into a bitcast (this represents anyext) feeding into
24386 // an and with a mask.
24387 // We'd like to try to combine that into a shuffle with zero
24388 // plus a bitcast, removing the and.
24389 if (N0.getOpcode() != ISD::BITCAST ||
24390 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24393 // The other side of the AND should be a splat of 2^C, where C
24394 // is the number of bits in the source type.
24395 if (N1.getOpcode() == ISD::BITCAST)
24396 N1 = N1.getOperand(0);
24397 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24399 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24401 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24402 EVT SrcType = Shuffle->getValueType(0);
24404 // We expect a single-source shuffle
24405 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24408 unsigned SrcSize = SrcType.getScalarSizeInBits();
24410 APInt SplatValue, SplatUndef;
24411 unsigned SplatBitSize;
24413 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24414 SplatBitSize, HasAnyUndefs))
24417 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24418 // Make sure the splat matches the mask we expect
24419 if (SplatBitSize > ResSize ||
24420 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24423 // Make sure the input and output size make sense
24424 if (SrcSize >= ResSize || ResSize % SrcSize)
24427 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24428 // The number of u's between each two values depends on the ratio between
24429 // the source and dest type.
24430 unsigned ZextRatio = ResSize / SrcSize;
24431 bool IsZext = true;
24432 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24433 if (i % ZextRatio) {
24434 if (Shuffle->getMaskElt(i) > 0) {
24440 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24441 // Expected element number
24451 // Ok, perform the transformation - replace the shuffle with
24452 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24453 // (instead of undef) where the k elements come from the zero vector.
24454 SmallVector<int, 8> Mask;
24455 unsigned NumElems = SrcType.getVectorNumElements();
24456 for (unsigned i = 0; i < NumElems; ++i)
24458 Mask.push_back(NumElems);
24460 Mask.push_back(i / ZextRatio);
24462 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24463 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24464 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24467 /// If both input operands of a logic op are being cast from floating point
24468 /// types, try to convert this into a floating point logic node to avoid
24469 /// unnecessary moves from SSE to integer registers.
24470 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24471 const X86Subtarget *Subtarget) {
24472 unsigned FPOpcode = ISD::DELETED_NODE;
24473 if (N->getOpcode() == ISD::AND)
24474 FPOpcode = X86ISD::FAND;
24475 else if (N->getOpcode() == ISD::OR)
24476 FPOpcode = X86ISD::FOR;
24477 else if (N->getOpcode() == ISD::XOR)
24478 FPOpcode = X86ISD::FXOR;
24480 assert(FPOpcode != ISD::DELETED_NODE &&
24481 "Unexpected input node for FP logic conversion");
24483 EVT VT = N->getValueType(0);
24484 SDValue N0 = N->getOperand(0);
24485 SDValue N1 = N->getOperand(1);
24487 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24488 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24489 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24490 SDValue N00 = N0.getOperand(0);
24491 SDValue N10 = N1.getOperand(0);
24492 EVT N00Type = N00.getValueType();
24493 EVT N10Type = N10.getValueType();
24494 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24495 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24496 return DAG.getBitcast(VT, FPLogic);
24502 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24503 TargetLowering::DAGCombinerInfo &DCI,
24504 const X86Subtarget *Subtarget) {
24505 if (DCI.isBeforeLegalizeOps())
24508 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24511 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24514 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24517 EVT VT = N->getValueType(0);
24518 SDValue N0 = N->getOperand(0);
24519 SDValue N1 = N->getOperand(1);
24522 // Create BEXTR instructions
24523 // BEXTR is ((X >> imm) & (2**size-1))
24524 if (VT == MVT::i32 || VT == MVT::i64) {
24525 // Check for BEXTR.
24526 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24527 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24528 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24529 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24530 if (MaskNode && ShiftNode) {
24531 uint64_t Mask = MaskNode->getZExtValue();
24532 uint64_t Shift = ShiftNode->getZExtValue();
24533 if (isMask_64(Mask)) {
24534 uint64_t MaskSize = countPopulation(Mask);
24535 if (Shift + MaskSize <= VT.getSizeInBits())
24536 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24537 DAG.getConstant(Shift | (MaskSize << 8), DL,
24546 // Want to form ANDNP nodes:
24547 // 1) In the hopes of then easily combining them with OR and AND nodes
24548 // to form PBLEND/PSIGN.
24549 // 2) To match ANDN packed intrinsics
24550 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24553 // Check LHS for vnot
24554 if (N0.getOpcode() == ISD::XOR &&
24555 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24556 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24557 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24559 // Check RHS for vnot
24560 if (N1.getOpcode() == ISD::XOR &&
24561 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24562 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24563 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24568 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24569 TargetLowering::DAGCombinerInfo &DCI,
24570 const X86Subtarget *Subtarget) {
24571 if (DCI.isBeforeLegalizeOps())
24574 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24577 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24580 SDValue N0 = N->getOperand(0);
24581 SDValue N1 = N->getOperand(1);
24582 EVT VT = N->getValueType(0);
24584 // look for psign/blend
24585 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24586 if (!Subtarget->hasSSSE3() ||
24587 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24590 // Canonicalize pandn to RHS
24591 if (N0.getOpcode() == X86ISD::ANDNP)
24593 // or (and (m, y), (pandn m, x))
24594 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24595 SDValue Mask = N1.getOperand(0);
24596 SDValue X = N1.getOperand(1);
24598 if (N0.getOperand(0) == Mask)
24599 Y = N0.getOperand(1);
24600 if (N0.getOperand(1) == Mask)
24601 Y = N0.getOperand(0);
24603 // Check to see if the mask appeared in both the AND and ANDNP and
24607 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24608 // Look through mask bitcast.
24609 if (Mask.getOpcode() == ISD::BITCAST)
24610 Mask = Mask.getOperand(0);
24611 if (X.getOpcode() == ISD::BITCAST)
24612 X = X.getOperand(0);
24613 if (Y.getOpcode() == ISD::BITCAST)
24614 Y = Y.getOperand(0);
24616 EVT MaskVT = Mask.getValueType();
24618 // Validate that the Mask operand is a vector sra node.
24619 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24620 // there is no psrai.b
24621 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24622 unsigned SraAmt = ~0;
24623 if (Mask.getOpcode() == ISD::SRA) {
24624 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24625 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24626 SraAmt = AmtConst->getZExtValue();
24627 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24628 SDValue SraC = Mask.getOperand(1);
24629 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24631 if ((SraAmt + 1) != EltBits)
24636 // Now we know we at least have a plendvb with the mask val. See if
24637 // we can form a psignb/w/d.
24638 // psign = x.type == y.type == mask.type && y = sub(0, x);
24639 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24640 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24641 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24642 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24643 "Unsupported VT for PSIGN");
24644 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24645 return DAG.getBitcast(VT, Mask);
24647 // PBLENDVB only available on SSE 4.1
24648 if (!Subtarget->hasSSE41())
24651 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24653 X = DAG.getBitcast(BlendVT, X);
24654 Y = DAG.getBitcast(BlendVT, Y);
24655 Mask = DAG.getBitcast(BlendVT, Mask);
24656 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24657 return DAG.getBitcast(VT, Mask);
24661 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24664 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24665 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24667 // SHLD/SHRD instructions have lower register pressure, but on some
24668 // platforms they have higher latency than the equivalent
24669 // series of shifts/or that would otherwise be generated.
24670 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24671 // have higher latencies and we are not optimizing for size.
24672 if (!OptForSize && Subtarget->isSHLDSlow())
24675 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24677 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24679 if (!N0.hasOneUse() || !N1.hasOneUse())
24682 SDValue ShAmt0 = N0.getOperand(1);
24683 if (ShAmt0.getValueType() != MVT::i8)
24685 SDValue ShAmt1 = N1.getOperand(1);
24686 if (ShAmt1.getValueType() != MVT::i8)
24688 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24689 ShAmt0 = ShAmt0.getOperand(0);
24690 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24691 ShAmt1 = ShAmt1.getOperand(0);
24694 unsigned Opc = X86ISD::SHLD;
24695 SDValue Op0 = N0.getOperand(0);
24696 SDValue Op1 = N1.getOperand(0);
24697 if (ShAmt0.getOpcode() == ISD::SUB) {
24698 Opc = X86ISD::SHRD;
24699 std::swap(Op0, Op1);
24700 std::swap(ShAmt0, ShAmt1);
24703 unsigned Bits = VT.getSizeInBits();
24704 if (ShAmt1.getOpcode() == ISD::SUB) {
24705 SDValue Sum = ShAmt1.getOperand(0);
24706 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24707 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24708 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24709 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24710 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24711 return DAG.getNode(Opc, DL, VT,
24713 DAG.getNode(ISD::TRUNCATE, DL,
24716 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24717 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24719 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24720 return DAG.getNode(Opc, DL, VT,
24721 N0.getOperand(0), N1.getOperand(0),
24722 DAG.getNode(ISD::TRUNCATE, DL,
24729 // Generate NEG and CMOV for integer abs.
24730 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24731 EVT VT = N->getValueType(0);
24733 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24734 // 8-bit integer abs to NEG and CMOV.
24735 if (VT.isInteger() && VT.getSizeInBits() == 8)
24738 SDValue N0 = N->getOperand(0);
24739 SDValue N1 = N->getOperand(1);
24742 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24743 // and change it to SUB and CMOV.
24744 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24745 N0.getOpcode() == ISD::ADD &&
24746 N0.getOperand(1) == N1 &&
24747 N1.getOpcode() == ISD::SRA &&
24748 N1.getOperand(0) == N0.getOperand(0))
24749 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24750 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24751 // Generate SUB & CMOV.
24752 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24753 DAG.getConstant(0, DL, VT), N0.getOperand(0));
24755 SDValue Ops[] = { N0.getOperand(0), Neg,
24756 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
24757 SDValue(Neg.getNode(), 1) };
24758 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24763 // Try to turn tests against the signbit in the form of:
24764 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
24767 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
24768 // This is only worth doing if the output type is i8.
24769 if (N->getValueType(0) != MVT::i8)
24772 SDValue N0 = N->getOperand(0);
24773 SDValue N1 = N->getOperand(1);
24775 // We should be performing an xor against a truncated shift.
24776 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
24779 // Make sure we are performing an xor against one.
24780 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
24783 // SetCC on x86 zero extends so only act on this if it's a logical shift.
24784 SDValue Shift = N0.getOperand(0);
24785 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
24788 // Make sure we are truncating from one of i16, i32 or i64.
24789 EVT ShiftTy = Shift.getValueType();
24790 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
24793 // Make sure the shift amount extracts the sign bit.
24794 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
24795 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
24798 // Create a greater-than comparison against -1.
24799 // N.B. Using SETGE against 0 works but we want a canonical looking
24800 // comparison, using SETGT matches up with what TranslateX86CC.
24802 SDValue ShiftOp = Shift.getOperand(0);
24803 EVT ShiftOpTy = ShiftOp.getValueType();
24804 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
24805 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
24809 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24810 TargetLowering::DAGCombinerInfo &DCI,
24811 const X86Subtarget *Subtarget) {
24812 if (DCI.isBeforeLegalizeOps())
24815 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
24818 if (Subtarget->hasCMov())
24819 if (SDValue RV = performIntegerAbsCombine(N, DAG))
24822 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24828 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24829 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24830 TargetLowering::DAGCombinerInfo &DCI,
24831 const X86Subtarget *Subtarget) {
24832 LoadSDNode *Ld = cast<LoadSDNode>(N);
24833 EVT RegVT = Ld->getValueType(0);
24834 EVT MemVT = Ld->getMemoryVT();
24836 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24838 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24839 // into two 16-byte operations.
24840 ISD::LoadExtType Ext = Ld->getExtensionType();
24842 unsigned AddressSpace = Ld->getAddressSpace();
24843 unsigned Alignment = Ld->getAlignment();
24844 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
24845 Ext == ISD::NON_EXTLOAD &&
24846 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
24847 AddressSpace, Alignment, &Fast) && !Fast) {
24848 unsigned NumElems = RegVT.getVectorNumElements();
24852 SDValue Ptr = Ld->getBasePtr();
24853 SDValue Increment =
24854 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24856 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24858 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24859 Ld->getPointerInfo(), Ld->isVolatile(),
24860 Ld->isNonTemporal(), Ld->isInvariant(),
24862 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24863 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24864 Ld->getPointerInfo(), Ld->isVolatile(),
24865 Ld->isNonTemporal(), Ld->isInvariant(),
24866 std::min(16U, Alignment));
24867 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24869 Load2.getValue(1));
24871 SDValue NewVec = DAG.getUNDEF(RegVT);
24872 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24873 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24874 return DCI.CombineTo(N, NewVec, TF, true);
24880 /// PerformMLOADCombine - Resolve extending loads
24881 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
24882 TargetLowering::DAGCombinerInfo &DCI,
24883 const X86Subtarget *Subtarget) {
24884 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
24885 if (Mld->getExtensionType() != ISD::SEXTLOAD)
24888 EVT VT = Mld->getValueType(0);
24889 unsigned NumElems = VT.getVectorNumElements();
24890 EVT LdVT = Mld->getMemoryVT();
24893 assert(LdVT != VT && "Cannot extend to the same type");
24894 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
24895 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
24896 // From, To sizes and ElemCount must be pow of two
24897 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24898 "Unexpected size for extending masked load");
24900 unsigned SizeRatio = ToSz / FromSz;
24901 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
24903 // Create a type on which we perform the shuffle
24904 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24905 LdVT.getScalarType(), NumElems*SizeRatio);
24906 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24908 // Convert Src0 value
24909 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
24910 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
24911 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24912 for (unsigned i = 0; i != NumElems; ++i)
24913 ShuffleVec[i] = i * SizeRatio;
24915 // Can't shuffle using an illegal type.
24916 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
24917 "WideVecVT should be legal");
24918 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
24919 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
24921 // Prepare the new mask
24923 SDValue Mask = Mld->getMask();
24924 if (Mask.getValueType() == VT) {
24925 // Mask and original value have the same type
24926 NewMask = DAG.getBitcast(WideVecVT, Mask);
24927 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24928 for (unsigned i = 0; i != NumElems; ++i)
24929 ShuffleVec[i] = i * SizeRatio;
24930 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24931 ShuffleVec[i] = NumElems*SizeRatio;
24932 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24933 DAG.getConstant(0, dl, WideVecVT),
24937 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24938 unsigned WidenNumElts = NumElems*SizeRatio;
24939 unsigned MaskNumElts = VT.getVectorNumElements();
24940 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24943 unsigned NumConcat = WidenNumElts / MaskNumElts;
24944 SmallVector<SDValue, 16> Ops(NumConcat);
24945 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24947 for (unsigned i = 1; i != NumConcat; ++i)
24950 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24953 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
24954 Mld->getBasePtr(), NewMask, WideSrc0,
24955 Mld->getMemoryVT(), Mld->getMemOperand(),
24957 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
24958 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
24960 /// PerformMSTORECombine - Resolve truncating stores
24961 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
24962 const X86Subtarget *Subtarget) {
24963 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
24964 if (!Mst->isTruncatingStore())
24967 EVT VT = Mst->getValue().getValueType();
24968 unsigned NumElems = VT.getVectorNumElements();
24969 EVT StVT = Mst->getMemoryVT();
24972 assert(StVT != VT && "Cannot truncate to the same type");
24973 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24974 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24976 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24978 // The truncating store is legal in some cases. For example
24979 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
24980 // are designated for truncate store.
24981 // In this case we don't need any further transformations.
24982 if (TLI.isTruncStoreLegal(VT, StVT))
24985 // From, To sizes and ElemCount must be pow of two
24986 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24987 "Unexpected size for truncating masked store");
24988 // We are going to use the original vector elt for storing.
24989 // Accumulated smaller vector elements must be a multiple of the store size.
24990 assert (((NumElems * FromSz) % ToSz) == 0 &&
24991 "Unexpected ratio for truncating masked store");
24993 unsigned SizeRatio = FromSz / ToSz;
24994 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24996 // Create a type on which we perform the shuffle
24997 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24998 StVT.getScalarType(), NumElems*SizeRatio);
25000 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25002 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25003 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25004 for (unsigned i = 0; i != NumElems; ++i)
25005 ShuffleVec[i] = i * SizeRatio;
25007 // Can't shuffle using an illegal type.
25008 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25009 "WideVecVT should be legal");
25011 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25012 DAG.getUNDEF(WideVecVT),
25016 SDValue Mask = Mst->getMask();
25017 if (Mask.getValueType() == VT) {
25018 // Mask and original value have the same type
25019 NewMask = DAG.getBitcast(WideVecVT, Mask);
25020 for (unsigned i = 0; i != NumElems; ++i)
25021 ShuffleVec[i] = i * SizeRatio;
25022 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25023 ShuffleVec[i] = NumElems*SizeRatio;
25024 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25025 DAG.getConstant(0, dl, WideVecVT),
25029 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25030 unsigned WidenNumElts = NumElems*SizeRatio;
25031 unsigned MaskNumElts = VT.getVectorNumElements();
25032 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25035 unsigned NumConcat = WidenNumElts / MaskNumElts;
25036 SmallVector<SDValue, 16> Ops(NumConcat);
25037 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25039 for (unsigned i = 1; i != NumConcat; ++i)
25042 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25045 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25046 NewMask, StVT, Mst->getMemOperand(), false);
25048 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25049 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25050 const X86Subtarget *Subtarget) {
25051 StoreSDNode *St = cast<StoreSDNode>(N);
25052 EVT VT = St->getValue().getValueType();
25053 EVT StVT = St->getMemoryVT();
25055 SDValue StoredVal = St->getOperand(1);
25056 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25058 // If we are saving a concatenation of two XMM registers and 32-byte stores
25059 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25061 unsigned AddressSpace = St->getAddressSpace();
25062 unsigned Alignment = St->getAlignment();
25063 if (VT.is256BitVector() && StVT == VT &&
25064 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25065 AddressSpace, Alignment, &Fast) && !Fast) {
25066 unsigned NumElems = VT.getVectorNumElements();
25070 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25071 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25074 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25075 SDValue Ptr0 = St->getBasePtr();
25076 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25078 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25079 St->getPointerInfo(), St->isVolatile(),
25080 St->isNonTemporal(), Alignment);
25081 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25082 St->getPointerInfo(), St->isVolatile(),
25083 St->isNonTemporal(),
25084 std::min(16U, Alignment));
25085 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25088 // Optimize trunc store (of multiple scalars) to shuffle and store.
25089 // First, pack all of the elements in one place. Next, store to memory
25090 // in fewer chunks.
25091 if (St->isTruncatingStore() && VT.isVector()) {
25092 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25093 unsigned NumElems = VT.getVectorNumElements();
25094 assert(StVT != VT && "Cannot truncate to the same type");
25095 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25096 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25098 // The truncating store is legal in some cases. For example
25099 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25100 // are designated for truncate store.
25101 // In this case we don't need any further transformations.
25102 if (TLI.isTruncStoreLegal(VT, StVT))
25105 // From, To sizes and ElemCount must be pow of two
25106 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25107 // We are going to use the original vector elt for storing.
25108 // Accumulated smaller vector elements must be a multiple of the store size.
25109 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25111 unsigned SizeRatio = FromSz / ToSz;
25113 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25115 // Create a type on which we perform the shuffle
25116 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25117 StVT.getScalarType(), NumElems*SizeRatio);
25119 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25121 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25122 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25123 for (unsigned i = 0; i != NumElems; ++i)
25124 ShuffleVec[i] = i * SizeRatio;
25126 // Can't shuffle using an illegal type.
25127 if (!TLI.isTypeLegal(WideVecVT))
25130 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25131 DAG.getUNDEF(WideVecVT),
25133 // At this point all of the data is stored at the bottom of the
25134 // register. We now need to save it to mem.
25136 // Find the largest store unit
25137 MVT StoreType = MVT::i8;
25138 for (MVT Tp : MVT::integer_valuetypes()) {
25139 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25143 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25144 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25145 (64 <= NumElems * ToSz))
25146 StoreType = MVT::f64;
25148 // Bitcast the original vector into a vector of store-size units
25149 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25150 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25151 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25152 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25153 SmallVector<SDValue, 8> Chains;
25154 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25155 TLI.getPointerTy(DAG.getDataLayout()));
25156 SDValue Ptr = St->getBasePtr();
25158 // Perform one or more big stores into memory.
25159 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25160 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25161 StoreType, ShuffWide,
25162 DAG.getIntPtrConstant(i, dl));
25163 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25164 St->getPointerInfo(), St->isVolatile(),
25165 St->isNonTemporal(), St->getAlignment());
25166 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25167 Chains.push_back(Ch);
25170 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25173 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25174 // the FP state in cases where an emms may be missing.
25175 // A preferable solution to the general problem is to figure out the right
25176 // places to insert EMMS. This qualifies as a quick hack.
25178 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25179 if (VT.getSizeInBits() != 64)
25182 const Function *F = DAG.getMachineFunction().getFunction();
25183 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25185 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25186 if ((VT.isVector() ||
25187 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25188 isa<LoadSDNode>(St->getValue()) &&
25189 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25190 St->getChain().hasOneUse() && !St->isVolatile()) {
25191 SDNode* LdVal = St->getValue().getNode();
25192 LoadSDNode *Ld = nullptr;
25193 int TokenFactorIndex = -1;
25194 SmallVector<SDValue, 8> Ops;
25195 SDNode* ChainVal = St->getChain().getNode();
25196 // Must be a store of a load. We currently handle two cases: the load
25197 // is a direct child, and it's under an intervening TokenFactor. It is
25198 // possible to dig deeper under nested TokenFactors.
25199 if (ChainVal == LdVal)
25200 Ld = cast<LoadSDNode>(St->getChain());
25201 else if (St->getValue().hasOneUse() &&
25202 ChainVal->getOpcode() == ISD::TokenFactor) {
25203 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25204 if (ChainVal->getOperand(i).getNode() == LdVal) {
25205 TokenFactorIndex = i;
25206 Ld = cast<LoadSDNode>(St->getValue());
25208 Ops.push_back(ChainVal->getOperand(i));
25212 if (!Ld || !ISD::isNormalLoad(Ld))
25215 // If this is not the MMX case, i.e. we are just turning i64 load/store
25216 // into f64 load/store, avoid the transformation if there are multiple
25217 // uses of the loaded value.
25218 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25223 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25224 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25226 if (Subtarget->is64Bit() || F64IsLegal) {
25227 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25228 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25229 Ld->getPointerInfo(), Ld->isVolatile(),
25230 Ld->isNonTemporal(), Ld->isInvariant(),
25231 Ld->getAlignment());
25232 SDValue NewChain = NewLd.getValue(1);
25233 if (TokenFactorIndex != -1) {
25234 Ops.push_back(NewChain);
25235 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25237 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25238 St->getPointerInfo(),
25239 St->isVolatile(), St->isNonTemporal(),
25240 St->getAlignment());
25243 // Otherwise, lower to two pairs of 32-bit loads / stores.
25244 SDValue LoAddr = Ld->getBasePtr();
25245 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25246 DAG.getConstant(4, LdDL, MVT::i32));
25248 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25249 Ld->getPointerInfo(),
25250 Ld->isVolatile(), Ld->isNonTemporal(),
25251 Ld->isInvariant(), Ld->getAlignment());
25252 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25253 Ld->getPointerInfo().getWithOffset(4),
25254 Ld->isVolatile(), Ld->isNonTemporal(),
25256 MinAlign(Ld->getAlignment(), 4));
25258 SDValue NewChain = LoLd.getValue(1);
25259 if (TokenFactorIndex != -1) {
25260 Ops.push_back(LoLd);
25261 Ops.push_back(HiLd);
25262 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25265 LoAddr = St->getBasePtr();
25266 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25267 DAG.getConstant(4, StDL, MVT::i32));
25269 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25270 St->getPointerInfo(),
25271 St->isVolatile(), St->isNonTemporal(),
25272 St->getAlignment());
25273 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25274 St->getPointerInfo().getWithOffset(4),
25276 St->isNonTemporal(),
25277 MinAlign(St->getAlignment(), 4));
25278 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25281 // This is similar to the above case, but here we handle a scalar 64-bit
25282 // integer store that is extracted from a vector on a 32-bit target.
25283 // If we have SSE2, then we can treat it like a floating-point double
25284 // to get past legalization. The execution dependencies fixup pass will
25285 // choose the optimal machine instruction for the store if this really is
25286 // an integer or v2f32 rather than an f64.
25287 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25288 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25289 SDValue OldExtract = St->getOperand(1);
25290 SDValue ExtOp0 = OldExtract.getOperand(0);
25291 unsigned VecSize = ExtOp0.getValueSizeInBits();
25292 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25293 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25294 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25295 BitCast, OldExtract.getOperand(1));
25296 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25297 St->getPointerInfo(), St->isVolatile(),
25298 St->isNonTemporal(), St->getAlignment());
25304 /// Return 'true' if this vector operation is "horizontal"
25305 /// and return the operands for the horizontal operation in LHS and RHS. A
25306 /// horizontal operation performs the binary operation on successive elements
25307 /// of its first operand, then on successive elements of its second operand,
25308 /// returning the resulting values in a vector. For example, if
25309 /// A = < float a0, float a1, float a2, float a3 >
25311 /// B = < float b0, float b1, float b2, float b3 >
25312 /// then the result of doing a horizontal operation on A and B is
25313 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25314 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25315 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25316 /// set to A, RHS to B, and the routine returns 'true'.
25317 /// Note that the binary operation should have the property that if one of the
25318 /// operands is UNDEF then the result is UNDEF.
25319 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25320 // Look for the following pattern: if
25321 // A = < float a0, float a1, float a2, float a3 >
25322 // B = < float b0, float b1, float b2, float b3 >
25324 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25325 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25326 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25327 // which is A horizontal-op B.
25329 // At least one of the operands should be a vector shuffle.
25330 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25331 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25334 MVT VT = LHS.getSimpleValueType();
25336 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25337 "Unsupported vector type for horizontal add/sub");
25339 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25340 // operate independently on 128-bit lanes.
25341 unsigned NumElts = VT.getVectorNumElements();
25342 unsigned NumLanes = VT.getSizeInBits()/128;
25343 unsigned NumLaneElts = NumElts / NumLanes;
25344 assert((NumLaneElts % 2 == 0) &&
25345 "Vector type should have an even number of elements in each lane");
25346 unsigned HalfLaneElts = NumLaneElts/2;
25348 // View LHS in the form
25349 // LHS = VECTOR_SHUFFLE A, B, LMask
25350 // If LHS is not a shuffle then pretend it is the shuffle
25351 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25352 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25355 SmallVector<int, 16> LMask(NumElts);
25356 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25357 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25358 A = LHS.getOperand(0);
25359 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25360 B = LHS.getOperand(1);
25361 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25362 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25364 if (LHS.getOpcode() != ISD::UNDEF)
25366 for (unsigned i = 0; i != NumElts; ++i)
25370 // Likewise, view RHS in the form
25371 // RHS = VECTOR_SHUFFLE C, D, RMask
25373 SmallVector<int, 16> RMask(NumElts);
25374 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25375 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25376 C = RHS.getOperand(0);
25377 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25378 D = RHS.getOperand(1);
25379 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25380 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25382 if (RHS.getOpcode() != ISD::UNDEF)
25384 for (unsigned i = 0; i != NumElts; ++i)
25388 // Check that the shuffles are both shuffling the same vectors.
25389 if (!(A == C && B == D) && !(A == D && B == C))
25392 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25393 if (!A.getNode() && !B.getNode())
25396 // If A and B occur in reverse order in RHS, then "swap" them (which means
25397 // rewriting the mask).
25399 ShuffleVectorSDNode::commuteMask(RMask);
25401 // At this point LHS and RHS are equivalent to
25402 // LHS = VECTOR_SHUFFLE A, B, LMask
25403 // RHS = VECTOR_SHUFFLE A, B, RMask
25404 // Check that the masks correspond to performing a horizontal operation.
25405 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25406 for (unsigned i = 0; i != NumLaneElts; ++i) {
25407 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25409 // Ignore any UNDEF components.
25410 if (LIdx < 0 || RIdx < 0 ||
25411 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25412 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25415 // Check that successive elements are being operated on. If not, this is
25416 // not a horizontal operation.
25417 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25418 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25419 if (!(LIdx == Index && RIdx == Index + 1) &&
25420 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25425 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25426 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25430 /// Do target-specific dag combines on floating point adds.
25431 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25432 const X86Subtarget *Subtarget) {
25433 EVT VT = N->getValueType(0);
25434 SDValue LHS = N->getOperand(0);
25435 SDValue RHS = N->getOperand(1);
25437 // Try to synthesize horizontal adds from adds of shuffles.
25438 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25439 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25440 isHorizontalBinOp(LHS, RHS, true))
25441 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25445 /// Do target-specific dag combines on floating point subs.
25446 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25447 const X86Subtarget *Subtarget) {
25448 EVT VT = N->getValueType(0);
25449 SDValue LHS = N->getOperand(0);
25450 SDValue RHS = N->getOperand(1);
25452 // Try to synthesize horizontal subs from subs of shuffles.
25453 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25454 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25455 isHorizontalBinOp(LHS, RHS, false))
25456 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25460 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25461 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25462 const X86Subtarget *Subtarget) {
25463 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25465 // F[X]OR(0.0, x) -> x
25466 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25467 if (C->getValueAPF().isPosZero())
25468 return N->getOperand(1);
25470 // F[X]OR(x, 0.0) -> x
25471 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25472 if (C->getValueAPF().isPosZero())
25473 return N->getOperand(0);
25475 EVT VT = N->getValueType(0);
25476 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25478 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25479 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25481 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25482 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25483 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25484 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25485 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25490 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25491 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25492 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25494 // Only perform optimizations if UnsafeMath is used.
25495 if (!DAG.getTarget().Options.UnsafeFPMath)
25498 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25499 // into FMINC and FMAXC, which are Commutative operations.
25500 unsigned NewOp = 0;
25501 switch (N->getOpcode()) {
25502 default: llvm_unreachable("unknown opcode");
25503 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25504 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25507 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25508 N->getOperand(0), N->getOperand(1));
25511 /// Do target-specific dag combines on X86ISD::FAND nodes.
25512 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25513 // FAND(0.0, x) -> 0.0
25514 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25515 if (C->getValueAPF().isPosZero())
25516 return N->getOperand(0);
25518 // FAND(x, 0.0) -> 0.0
25519 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25520 if (C->getValueAPF().isPosZero())
25521 return N->getOperand(1);
25526 /// Do target-specific dag combines on X86ISD::FANDN nodes
25527 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25528 // FANDN(0.0, x) -> x
25529 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25530 if (C->getValueAPF().isPosZero())
25531 return N->getOperand(1);
25533 // FANDN(x, 0.0) -> 0.0
25534 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25535 if (C->getValueAPF().isPosZero())
25536 return N->getOperand(1);
25541 static SDValue PerformBTCombine(SDNode *N,
25543 TargetLowering::DAGCombinerInfo &DCI) {
25544 // BT ignores high bits in the bit index operand.
25545 SDValue Op1 = N->getOperand(1);
25546 if (Op1.hasOneUse()) {
25547 unsigned BitWidth = Op1.getValueSizeInBits();
25548 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25549 APInt KnownZero, KnownOne;
25550 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25551 !DCI.isBeforeLegalizeOps());
25552 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25553 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25554 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25555 DCI.CommitTargetLoweringOpt(TLO);
25560 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25561 SDValue Op = N->getOperand(0);
25562 if (Op.getOpcode() == ISD::BITCAST)
25563 Op = Op.getOperand(0);
25564 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25565 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25566 VT.getVectorElementType().getSizeInBits() ==
25567 OpVT.getVectorElementType().getSizeInBits()) {
25568 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25573 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25574 const X86Subtarget *Subtarget) {
25575 EVT VT = N->getValueType(0);
25576 if (!VT.isVector())
25579 SDValue N0 = N->getOperand(0);
25580 SDValue N1 = N->getOperand(1);
25581 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25584 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25585 // both SSE and AVX2 since there is no sign-extended shift right
25586 // operation on a vector with 64-bit elements.
25587 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25588 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25589 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25590 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25591 SDValue N00 = N0.getOperand(0);
25593 // EXTLOAD has a better solution on AVX2,
25594 // it may be replaced with X86ISD::VSEXT node.
25595 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25596 if (!ISD::isNormalLoad(N00.getNode()))
25599 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25600 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25602 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25608 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25609 TargetLowering::DAGCombinerInfo &DCI,
25610 const X86Subtarget *Subtarget) {
25611 SDValue N0 = N->getOperand(0);
25612 EVT VT = N->getValueType(0);
25613 EVT SVT = VT.getScalarType();
25614 EVT InVT = N0.getValueType();
25615 EVT InSVT = InVT.getScalarType();
25618 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25619 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25620 // This exposes the sext to the sdivrem lowering, so that it directly extends
25621 // from AH (which we otherwise need to do contortions to access).
25622 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25623 InVT == MVT::i8 && VT == MVT::i32) {
25624 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25625 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25626 N0.getOperand(0), N0.getOperand(1));
25627 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25628 return R.getValue(1);
25631 if (!DCI.isBeforeLegalizeOps()) {
25632 if (InVT == MVT::i1) {
25633 SDValue Zero = DAG.getConstant(0, DL, VT);
25635 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25636 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25641 if (VT.isVector() && Subtarget->hasSSE2()) {
25642 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25643 EVT InVT = N.getValueType();
25644 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25645 Size / InVT.getScalarSizeInBits());
25646 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25647 DAG.getUNDEF(InVT));
25649 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25652 // If target-size is less than 128-bits, extend to a type that would extend
25653 // to 128 bits, extend that and extract the original target vector.
25654 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25655 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25656 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25657 unsigned Scale = 128 / VT.getSizeInBits();
25659 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25660 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25661 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25662 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25663 DAG.getIntPtrConstant(0, DL));
25666 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25667 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25668 if (VT.getSizeInBits() == 128 &&
25669 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25670 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25671 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25672 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25675 // On pre-AVX2 targets, split into 128-bit nodes of
25676 // ISD::SIGN_EXTEND_VECTOR_INREG.
25677 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25678 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25679 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25680 unsigned NumVecs = VT.getSizeInBits() / 128;
25681 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25682 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25683 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
25685 SmallVector<SDValue, 8> Opnds;
25686 for (unsigned i = 0, Offset = 0; i != NumVecs;
25687 ++i, Offset += NumSubElts) {
25688 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
25689 DAG.getIntPtrConstant(Offset, DL));
25690 SrcVec = ExtendVecSize(DL, SrcVec, 128);
25691 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
25692 Opnds.push_back(SrcVec);
25694 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
25698 if (!Subtarget->hasFp256())
25701 if (VT.isVector() && VT.getSizeInBits() == 256)
25702 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25708 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25709 const X86Subtarget* Subtarget) {
25711 EVT VT = N->getValueType(0);
25713 // Let legalize expand this if it isn't a legal type yet.
25714 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25717 EVT ScalarVT = VT.getScalarType();
25718 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25719 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
25720 !Subtarget->hasAVX512()))
25723 SDValue A = N->getOperand(0);
25724 SDValue B = N->getOperand(1);
25725 SDValue C = N->getOperand(2);
25727 bool NegA = (A.getOpcode() == ISD::FNEG);
25728 bool NegB = (B.getOpcode() == ISD::FNEG);
25729 bool NegC = (C.getOpcode() == ISD::FNEG);
25731 // Negative multiplication when NegA xor NegB
25732 bool NegMul = (NegA != NegB);
25734 A = A.getOperand(0);
25736 B = B.getOperand(0);
25738 C = C.getOperand(0);
25742 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25744 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25746 return DAG.getNode(Opcode, dl, VT, A, B, C);
25749 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25750 TargetLowering::DAGCombinerInfo &DCI,
25751 const X86Subtarget *Subtarget) {
25752 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25753 // (and (i32 x86isd::setcc_carry), 1)
25754 // This eliminates the zext. This transformation is necessary because
25755 // ISD::SETCC is always legalized to i8.
25757 SDValue N0 = N->getOperand(0);
25758 EVT VT = N->getValueType(0);
25760 if (N0.getOpcode() == ISD::AND &&
25762 N0.getOperand(0).hasOneUse()) {
25763 SDValue N00 = N0.getOperand(0);
25764 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25765 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25766 if (!C || C->getZExtValue() != 1)
25768 return DAG.getNode(ISD::AND, dl, VT,
25769 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25770 N00.getOperand(0), N00.getOperand(1)),
25771 DAG.getConstant(1, dl, VT));
25775 if (N0.getOpcode() == ISD::TRUNCATE &&
25777 N0.getOperand(0).hasOneUse()) {
25778 SDValue N00 = N0.getOperand(0);
25779 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25780 return DAG.getNode(ISD::AND, dl, VT,
25781 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25782 N00.getOperand(0), N00.getOperand(1)),
25783 DAG.getConstant(1, dl, VT));
25787 if (VT.is256BitVector())
25788 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25791 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25792 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25793 // This exposes the zext to the udivrem lowering, so that it directly extends
25794 // from AH (which we otherwise need to do contortions to access).
25795 if (N0.getOpcode() == ISD::UDIVREM &&
25796 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25797 (VT == MVT::i32 || VT == MVT::i64)) {
25798 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25799 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25800 N0.getOperand(0), N0.getOperand(1));
25801 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25802 return R.getValue(1);
25808 // Optimize x == -y --> x+y == 0
25809 // x != -y --> x+y != 0
25810 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25811 const X86Subtarget* Subtarget) {
25812 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25813 SDValue LHS = N->getOperand(0);
25814 SDValue RHS = N->getOperand(1);
25815 EVT VT = N->getValueType(0);
25818 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25819 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25820 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25821 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
25822 LHS.getOperand(1));
25823 return DAG.getSetCC(DL, N->getValueType(0), addV,
25824 DAG.getConstant(0, DL, addV.getValueType()), CC);
25826 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25827 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25828 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25829 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
25830 RHS.getOperand(1));
25831 return DAG.getSetCC(DL, N->getValueType(0), addV,
25832 DAG.getConstant(0, DL, addV.getValueType()), CC);
25835 if (VT.getScalarType() == MVT::i1 &&
25836 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
25838 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25839 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25840 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25842 if (!IsSEXT0 || !IsVZero1) {
25843 // Swap the operands and update the condition code.
25844 std::swap(LHS, RHS);
25845 CC = ISD::getSetCCSwappedOperands(CC);
25847 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25848 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25849 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25852 if (IsSEXT0 && IsVZero1) {
25853 assert(VT == LHS.getOperand(0).getValueType() &&
25854 "Uexpected operand type");
25855 if (CC == ISD::SETGT)
25856 return DAG.getConstant(0, DL, VT);
25857 if (CC == ISD::SETLE)
25858 return DAG.getConstant(1, DL, VT);
25859 if (CC == ISD::SETEQ || CC == ISD::SETGE)
25860 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25862 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
25863 "Unexpected condition code!");
25864 return LHS.getOperand(0);
25871 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
25872 SelectionDAG &DAG) {
25874 MVT VT = Load->getSimpleValueType(0);
25875 MVT EVT = VT.getVectorElementType();
25876 SDValue Addr = Load->getOperand(1);
25877 SDValue NewAddr = DAG.getNode(
25878 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
25879 DAG.getConstant(Index * EVT.getStoreSize(), dl,
25880 Addr.getSimpleValueType()));
25883 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
25884 DAG.getMachineFunction().getMachineMemOperand(
25885 Load->getMemOperand(), 0, EVT.getStoreSize()));
25889 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25890 const X86Subtarget *Subtarget) {
25892 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25893 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25894 "X86insertps is only defined for v4x32");
25896 SDValue Ld = N->getOperand(1);
25897 if (MayFoldLoad(Ld)) {
25898 // Extract the countS bits from the immediate so we can get the proper
25899 // address when narrowing the vector load to a specific element.
25900 // When the second source op is a memory address, insertps doesn't use
25901 // countS and just gets an f32 from that address.
25902 unsigned DestIndex =
25903 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25905 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25907 // Create this as a scalar to vector to match the instruction pattern.
25908 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25909 // countS bits are ignored when loading from memory on insertps, which
25910 // means we don't need to explicitly set them to 0.
25911 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25912 LoadScalarToVector, N->getOperand(2));
25917 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
25918 SDValue V0 = N->getOperand(0);
25919 SDValue V1 = N->getOperand(1);
25921 EVT VT = N->getValueType(0);
25923 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
25924 // operands and changing the mask to 1. This saves us a bunch of
25925 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
25926 // x86InstrInfo knows how to commute this back after instruction selection
25927 // if it would help register allocation.
25929 // TODO: If optimizing for size or a processor that doesn't suffer from
25930 // partial register update stalls, this should be transformed into a MOVSD
25931 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
25933 if (VT == MVT::v2f64)
25934 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
25935 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
25936 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
25937 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
25943 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25944 // as "sbb reg,reg", since it can be extended without zext and produces
25945 // an all-ones bit which is more useful than 0/1 in some cases.
25946 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25949 return DAG.getNode(ISD::AND, DL, VT,
25950 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25951 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25953 DAG.getConstant(1, DL, VT));
25954 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25955 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25956 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25957 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25961 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25962 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25963 TargetLowering::DAGCombinerInfo &DCI,
25964 const X86Subtarget *Subtarget) {
25966 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25967 SDValue EFLAGS = N->getOperand(1);
25969 if (CC == X86::COND_A) {
25970 // Try to convert COND_A into COND_B in an attempt to facilitate
25971 // materializing "setb reg".
25973 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25974 // cannot take an immediate as its first operand.
25976 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25977 EFLAGS.getValueType().isInteger() &&
25978 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25979 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25980 EFLAGS.getNode()->getVTList(),
25981 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25982 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25983 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25987 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25988 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25990 if (CC == X86::COND_B)
25991 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25993 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25994 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25995 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26001 // Optimize branch condition evaluation.
26003 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26004 TargetLowering::DAGCombinerInfo &DCI,
26005 const X86Subtarget *Subtarget) {
26007 SDValue Chain = N->getOperand(0);
26008 SDValue Dest = N->getOperand(1);
26009 SDValue EFLAGS = N->getOperand(3);
26010 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26012 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26013 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26014 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26021 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26022 SelectionDAG &DAG) {
26023 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26024 // optimize away operation when it's from a constant.
26026 // The general transformation is:
26027 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26028 // AND(VECTOR_CMP(x,y), constant2)
26029 // constant2 = UNARYOP(constant)
26031 // Early exit if this isn't a vector operation, the operand of the
26032 // unary operation isn't a bitwise AND, or if the sizes of the operations
26033 // aren't the same.
26034 EVT VT = N->getValueType(0);
26035 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26036 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26037 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26040 // Now check that the other operand of the AND is a constant. We could
26041 // make the transformation for non-constant splats as well, but it's unclear
26042 // that would be a benefit as it would not eliminate any operations, just
26043 // perform one more step in scalar code before moving to the vector unit.
26044 if (BuildVectorSDNode *BV =
26045 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26046 // Bail out if the vector isn't a constant.
26047 if (!BV->isConstant())
26050 // Everything checks out. Build up the new and improved node.
26052 EVT IntVT = BV->getValueType(0);
26053 // Create a new constant of the appropriate type for the transformed
26055 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26056 // The AND node needs bitcasts to/from an integer vector type around it.
26057 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26058 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26059 N->getOperand(0)->getOperand(0), MaskConst);
26060 SDValue Res = DAG.getBitcast(VT, NewAnd);
26067 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26068 const X86Subtarget *Subtarget) {
26069 SDValue Op0 = N->getOperand(0);
26070 EVT VT = N->getValueType(0);
26071 EVT InVT = Op0.getValueType();
26072 EVT InSVT = InVT.getScalarType();
26073 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26075 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26076 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26077 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26079 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26080 InVT.getVectorNumElements());
26081 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26083 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26084 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26086 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26092 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26093 const X86Subtarget *Subtarget) {
26094 // First try to optimize away the conversion entirely when it's
26095 // conditionally from a constant. Vectors only.
26096 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26099 // Now move on to more general possibilities.
26100 SDValue Op0 = N->getOperand(0);
26101 EVT VT = N->getValueType(0);
26102 EVT InVT = Op0.getValueType();
26103 EVT InSVT = InVT.getScalarType();
26105 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26106 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26107 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26109 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26110 InVT.getVectorNumElements());
26111 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26112 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26115 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26116 // a 32-bit target where SSE doesn't support i64->FP operations.
26117 if (Op0.getOpcode() == ISD::LOAD) {
26118 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26119 EVT LdVT = Ld->getValueType(0);
26121 // This transformation is not supported if the result type is f16
26122 if (VT == MVT::f16)
26125 if (!Ld->isVolatile() && !VT.isVector() &&
26126 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26127 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26128 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26129 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26130 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26137 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26138 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26139 X86TargetLowering::DAGCombinerInfo &DCI) {
26140 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26141 // the result is either zero or one (depending on the input carry bit).
26142 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26143 if (X86::isZeroNode(N->getOperand(0)) &&
26144 X86::isZeroNode(N->getOperand(1)) &&
26145 // We don't have a good way to replace an EFLAGS use, so only do this when
26147 SDValue(N, 1).use_empty()) {
26149 EVT VT = N->getValueType(0);
26150 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26151 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26152 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26153 DAG.getConstant(X86::COND_B, DL,
26156 DAG.getConstant(1, DL, VT));
26157 return DCI.CombineTo(N, Res1, CarryOut);
26163 // fold (add Y, (sete X, 0)) -> adc 0, Y
26164 // (add Y, (setne X, 0)) -> sbb -1, Y
26165 // (sub (sete X, 0), Y) -> sbb 0, Y
26166 // (sub (setne X, 0), Y) -> adc -1, Y
26167 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26170 // Look through ZExts.
26171 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26172 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26175 SDValue SetCC = Ext.getOperand(0);
26176 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26179 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26180 if (CC != X86::COND_E && CC != X86::COND_NE)
26183 SDValue Cmp = SetCC.getOperand(1);
26184 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26185 !X86::isZeroNode(Cmp.getOperand(1)) ||
26186 !Cmp.getOperand(0).getValueType().isInteger())
26189 SDValue CmpOp0 = Cmp.getOperand(0);
26190 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26191 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26193 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26194 if (CC == X86::COND_NE)
26195 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26196 DL, OtherVal.getValueType(), OtherVal,
26197 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26199 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26200 DL, OtherVal.getValueType(), OtherVal,
26201 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26204 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26205 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26206 const X86Subtarget *Subtarget) {
26207 EVT VT = N->getValueType(0);
26208 SDValue Op0 = N->getOperand(0);
26209 SDValue Op1 = N->getOperand(1);
26211 // Try to synthesize horizontal adds from adds of shuffles.
26212 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26213 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26214 isHorizontalBinOp(Op0, Op1, true))
26215 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26217 return OptimizeConditionalInDecrement(N, DAG);
26220 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26221 const X86Subtarget *Subtarget) {
26222 SDValue Op0 = N->getOperand(0);
26223 SDValue Op1 = N->getOperand(1);
26225 // X86 can't encode an immediate LHS of a sub. See if we can push the
26226 // negation into a preceding instruction.
26227 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26228 // If the RHS of the sub is a XOR with one use and a constant, invert the
26229 // immediate. Then add one to the LHS of the sub so we can turn
26230 // X-Y -> X+~Y+1, saving one register.
26231 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26232 isa<ConstantSDNode>(Op1.getOperand(1))) {
26233 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26234 EVT VT = Op0.getValueType();
26235 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26237 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26238 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26239 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26243 // Try to synthesize horizontal adds from adds of shuffles.
26244 EVT VT = N->getValueType(0);
26245 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26246 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26247 isHorizontalBinOp(Op0, Op1, true))
26248 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26250 return OptimizeConditionalInDecrement(N, DAG);
26253 /// performVZEXTCombine - Performs build vector combines
26254 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26255 TargetLowering::DAGCombinerInfo &DCI,
26256 const X86Subtarget *Subtarget) {
26258 MVT VT = N->getSimpleValueType(0);
26259 SDValue Op = N->getOperand(0);
26260 MVT OpVT = Op.getSimpleValueType();
26261 MVT OpEltVT = OpVT.getVectorElementType();
26262 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26264 // (vzext (bitcast (vzext (x)) -> (vzext x)
26266 while (V.getOpcode() == ISD::BITCAST)
26267 V = V.getOperand(0);
26269 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26270 MVT InnerVT = V.getSimpleValueType();
26271 MVT InnerEltVT = InnerVT.getVectorElementType();
26273 // If the element sizes match exactly, we can just do one larger vzext. This
26274 // is always an exact type match as vzext operates on integer types.
26275 if (OpEltVT == InnerEltVT) {
26276 assert(OpVT == InnerVT && "Types must match for vzext!");
26277 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26280 // The only other way we can combine them is if only a single element of the
26281 // inner vzext is used in the input to the outer vzext.
26282 if (InnerEltVT.getSizeInBits() < InputBits)
26285 // In this case, the inner vzext is completely dead because we're going to
26286 // only look at bits inside of the low element. Just do the outer vzext on
26287 // a bitcast of the input to the inner.
26288 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26291 // Check if we can bypass extracting and re-inserting an element of an input
26292 // vector. Essentially:
26293 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26294 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26295 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26296 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26297 SDValue ExtractedV = V.getOperand(0);
26298 SDValue OrigV = ExtractedV.getOperand(0);
26299 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26300 if (ExtractIdx->getZExtValue() == 0) {
26301 MVT OrigVT = OrigV.getSimpleValueType();
26302 // Extract a subvector if necessary...
26303 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26304 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26305 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26306 OrigVT.getVectorNumElements() / Ratio);
26307 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26308 DAG.getIntPtrConstant(0, DL));
26310 Op = DAG.getBitcast(OpVT, OrigV);
26311 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26318 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26319 DAGCombinerInfo &DCI) const {
26320 SelectionDAG &DAG = DCI.DAG;
26321 switch (N->getOpcode()) {
26323 case ISD::EXTRACT_VECTOR_ELT:
26324 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26327 case X86ISD::SHRUNKBLEND:
26328 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26329 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
26330 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26331 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26332 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26333 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26334 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26337 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26338 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26339 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26340 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26341 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26342 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26343 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26344 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26345 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26346 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26347 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26348 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26350 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26352 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26353 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26354 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26355 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26356 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26357 case ISD::ANY_EXTEND:
26358 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26359 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26360 case ISD::SIGN_EXTEND_INREG:
26361 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26362 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26363 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26364 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26365 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26366 case X86ISD::SHUFP: // Handle all target specific shuffles
26367 case X86ISD::PALIGNR:
26368 case X86ISD::UNPCKH:
26369 case X86ISD::UNPCKL:
26370 case X86ISD::MOVHLPS:
26371 case X86ISD::MOVLHPS:
26372 case X86ISD::PSHUFB:
26373 case X86ISD::PSHUFD:
26374 case X86ISD::PSHUFHW:
26375 case X86ISD::PSHUFLW:
26376 case X86ISD::MOVSS:
26377 case X86ISD::MOVSD:
26378 case X86ISD::VPERMILPI:
26379 case X86ISD::VPERM2X128:
26380 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26381 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26382 case X86ISD::INSERTPS: {
26383 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26384 return PerformINSERTPSCombine(N, DAG, Subtarget);
26387 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26393 /// isTypeDesirableForOp - Return true if the target has native support for
26394 /// the specified value type and it is 'desirable' to use the type for the
26395 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26396 /// instruction encodings are longer and some i16 instructions are slow.
26397 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26398 if (!isTypeLegal(VT))
26400 if (VT != MVT::i16)
26407 case ISD::SIGN_EXTEND:
26408 case ISD::ZERO_EXTEND:
26409 case ISD::ANY_EXTEND:
26422 /// IsDesirableToPromoteOp - This method query the target whether it is
26423 /// beneficial for dag combiner to promote the specified node. If true, it
26424 /// should return the desired promotion type by reference.
26425 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26426 EVT VT = Op.getValueType();
26427 if (VT != MVT::i16)
26430 bool Promote = false;
26431 bool Commute = false;
26432 switch (Op.getOpcode()) {
26435 LoadSDNode *LD = cast<LoadSDNode>(Op);
26436 // If the non-extending load has a single use and it's not live out, then it
26437 // might be folded.
26438 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26439 Op.hasOneUse()*/) {
26440 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26441 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26442 // The only case where we'd want to promote LOAD (rather then it being
26443 // promoted as an operand is when it's only use is liveout.
26444 if (UI->getOpcode() != ISD::CopyToReg)
26451 case ISD::SIGN_EXTEND:
26452 case ISD::ZERO_EXTEND:
26453 case ISD::ANY_EXTEND:
26458 SDValue N0 = Op.getOperand(0);
26459 // Look out for (store (shl (load), x)).
26460 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26473 SDValue N0 = Op.getOperand(0);
26474 SDValue N1 = Op.getOperand(1);
26475 if (!Commute && MayFoldLoad(N1))
26477 // Avoid disabling potential load folding opportunities.
26478 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26480 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26490 //===----------------------------------------------------------------------===//
26491 // X86 Inline Assembly Support
26492 //===----------------------------------------------------------------------===//
26494 // Helper to match a string separated by whitespace.
26495 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26496 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26498 for (StringRef Piece : Pieces) {
26499 if (!S.startswith(Piece)) // Check if the piece matches.
26502 S = S.substr(Piece.size());
26503 StringRef::size_type Pos = S.find_first_not_of(" \t");
26504 if (Pos == 0) // We matched a prefix.
26513 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26515 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26516 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26517 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26518 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26520 if (AsmPieces.size() == 3)
26522 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26529 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26530 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26532 std::string AsmStr = IA->getAsmString();
26534 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26535 if (!Ty || Ty->getBitWidth() % 16 != 0)
26538 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26539 SmallVector<StringRef, 4> AsmPieces;
26540 SplitString(AsmStr, AsmPieces, ";\n");
26542 switch (AsmPieces.size()) {
26543 default: return false;
26545 // FIXME: this should verify that we are targeting a 486 or better. If not,
26546 // we will turn this bswap into something that will be lowered to logical
26547 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26548 // lower so don't worry about this.
26550 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26551 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26552 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26553 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26554 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26555 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26556 // No need to check constraints, nothing other than the equivalent of
26557 // "=r,0" would be valid here.
26558 return IntrinsicLowering::LowerToByteSwap(CI);
26561 // rorw $$8, ${0:w} --> llvm.bswap.i16
26562 if (CI->getType()->isIntegerTy(16) &&
26563 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26564 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26565 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26567 StringRef ConstraintsStr = IA->getConstraintString();
26568 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26569 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26570 if (clobbersFlagRegisters(AsmPieces))
26571 return IntrinsicLowering::LowerToByteSwap(CI);
26575 if (CI->getType()->isIntegerTy(32) &&
26576 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26577 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26578 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26579 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26581 StringRef ConstraintsStr = IA->getConstraintString();
26582 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26583 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26584 if (clobbersFlagRegisters(AsmPieces))
26585 return IntrinsicLowering::LowerToByteSwap(CI);
26588 if (CI->getType()->isIntegerTy(64)) {
26589 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26590 if (Constraints.size() >= 2 &&
26591 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26592 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26593 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26594 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26595 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26596 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26597 return IntrinsicLowering::LowerToByteSwap(CI);
26605 /// getConstraintType - Given a constraint letter, return the type of
26606 /// constraint it is for this target.
26607 X86TargetLowering::ConstraintType
26608 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26609 if (Constraint.size() == 1) {
26610 switch (Constraint[0]) {
26621 return C_RegisterClass;
26645 return TargetLowering::getConstraintType(Constraint);
26648 /// Examine constraint type and operand type and determine a weight value.
26649 /// This object must already have been set up with the operand type
26650 /// and the current alternative constraint selected.
26651 TargetLowering::ConstraintWeight
26652 X86TargetLowering::getSingleConstraintMatchWeight(
26653 AsmOperandInfo &info, const char *constraint) const {
26654 ConstraintWeight weight = CW_Invalid;
26655 Value *CallOperandVal = info.CallOperandVal;
26656 // If we don't have a value, we can't do a match,
26657 // but allow it at the lowest weight.
26658 if (!CallOperandVal)
26660 Type *type = CallOperandVal->getType();
26661 // Look at the constraint type.
26662 switch (*constraint) {
26664 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26675 if (CallOperandVal->getType()->isIntegerTy())
26676 weight = CW_SpecificReg;
26681 if (type->isFloatingPointTy())
26682 weight = CW_SpecificReg;
26685 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26686 weight = CW_SpecificReg;
26690 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26691 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26692 weight = CW_Register;
26695 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26696 if (C->getZExtValue() <= 31)
26697 weight = CW_Constant;
26701 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26702 if (C->getZExtValue() <= 63)
26703 weight = CW_Constant;
26707 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26708 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26709 weight = CW_Constant;
26713 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26714 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26715 weight = CW_Constant;
26719 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26720 if (C->getZExtValue() <= 3)
26721 weight = CW_Constant;
26725 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26726 if (C->getZExtValue() <= 0xff)
26727 weight = CW_Constant;
26732 if (isa<ConstantFP>(CallOperandVal)) {
26733 weight = CW_Constant;
26737 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26738 if ((C->getSExtValue() >= -0x80000000LL) &&
26739 (C->getSExtValue() <= 0x7fffffffLL))
26740 weight = CW_Constant;
26744 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26745 if (C->getZExtValue() <= 0xffffffff)
26746 weight = CW_Constant;
26753 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26754 /// with another that has more specific requirements based on the type of the
26755 /// corresponding operand.
26756 const char *X86TargetLowering::
26757 LowerXConstraint(EVT ConstraintVT) const {
26758 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26759 // 'f' like normal targets.
26760 if (ConstraintVT.isFloatingPoint()) {
26761 if (Subtarget->hasSSE2())
26763 if (Subtarget->hasSSE1())
26767 return TargetLowering::LowerXConstraint(ConstraintVT);
26770 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26771 /// vector. If it is invalid, don't add anything to Ops.
26772 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26773 std::string &Constraint,
26774 std::vector<SDValue>&Ops,
26775 SelectionDAG &DAG) const {
26778 // Only support length 1 constraints for now.
26779 if (Constraint.length() > 1) return;
26781 char ConstraintLetter = Constraint[0];
26782 switch (ConstraintLetter) {
26785 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26786 if (C->getZExtValue() <= 31) {
26787 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26788 Op.getValueType());
26794 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26795 if (C->getZExtValue() <= 63) {
26796 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26797 Op.getValueType());
26803 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26804 if (isInt<8>(C->getSExtValue())) {
26805 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26806 Op.getValueType());
26812 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26813 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26814 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26815 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
26816 Op.getValueType());
26822 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26823 if (C->getZExtValue() <= 3) {
26824 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26825 Op.getValueType());
26831 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26832 if (C->getZExtValue() <= 255) {
26833 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26834 Op.getValueType());
26840 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26841 if (C->getZExtValue() <= 127) {
26842 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26843 Op.getValueType());
26849 // 32-bit signed value
26850 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26851 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26852 C->getSExtValue())) {
26853 // Widen to 64 bits here to get it sign extended.
26854 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
26857 // FIXME gcc accepts some relocatable values here too, but only in certain
26858 // memory models; it's complicated.
26863 // 32-bit unsigned value
26864 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26865 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26866 C->getZExtValue())) {
26867 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26868 Op.getValueType());
26872 // FIXME gcc accepts some relocatable values here too, but only in certain
26873 // memory models; it's complicated.
26877 // Literal immediates are always ok.
26878 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26879 // Widen to 64 bits here to get it sign extended.
26880 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
26884 // In any sort of PIC mode addresses need to be computed at runtime by
26885 // adding in a register or some sort of table lookup. These can't
26886 // be used as immediates.
26887 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26890 // If we are in non-pic codegen mode, we allow the address of a global (with
26891 // an optional displacement) to be used with 'i'.
26892 GlobalAddressSDNode *GA = nullptr;
26893 int64_t Offset = 0;
26895 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26897 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26898 Offset += GA->getOffset();
26900 } else if (Op.getOpcode() == ISD::ADD) {
26901 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26902 Offset += C->getZExtValue();
26903 Op = Op.getOperand(0);
26906 } else if (Op.getOpcode() == ISD::SUB) {
26907 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26908 Offset += -C->getZExtValue();
26909 Op = Op.getOperand(0);
26914 // Otherwise, this isn't something we can handle, reject it.
26918 const GlobalValue *GV = GA->getGlobal();
26919 // If we require an extra load to get this address, as in PIC mode, we
26920 // can't accept it.
26921 if (isGlobalStubReference(
26922 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26925 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26926 GA->getValueType(0), Offset);
26931 if (Result.getNode()) {
26932 Ops.push_back(Result);
26935 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26938 std::pair<unsigned, const TargetRegisterClass *>
26939 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
26940 StringRef Constraint,
26942 // First, see if this is a constraint that directly corresponds to an LLVM
26944 if (Constraint.size() == 1) {
26945 // GCC Constraint Letters
26946 switch (Constraint[0]) {
26948 // TODO: Slight differences here in allocation order and leaving
26949 // RIP in the class. Do they matter any more here than they do
26950 // in the normal allocation?
26951 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26952 if (Subtarget->is64Bit()) {
26953 if (VT == MVT::i32 || VT == MVT::f32)
26954 return std::make_pair(0U, &X86::GR32RegClass);
26955 if (VT == MVT::i16)
26956 return std::make_pair(0U, &X86::GR16RegClass);
26957 if (VT == MVT::i8 || VT == MVT::i1)
26958 return std::make_pair(0U, &X86::GR8RegClass);
26959 if (VT == MVT::i64 || VT == MVT::f64)
26960 return std::make_pair(0U, &X86::GR64RegClass);
26963 // 32-bit fallthrough
26964 case 'Q': // Q_REGS
26965 if (VT == MVT::i32 || VT == MVT::f32)
26966 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26967 if (VT == MVT::i16)
26968 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26969 if (VT == MVT::i8 || VT == MVT::i1)
26970 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26971 if (VT == MVT::i64)
26972 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26974 case 'r': // GENERAL_REGS
26975 case 'l': // INDEX_REGS
26976 if (VT == MVT::i8 || VT == MVT::i1)
26977 return std::make_pair(0U, &X86::GR8RegClass);
26978 if (VT == MVT::i16)
26979 return std::make_pair(0U, &X86::GR16RegClass);
26980 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26981 return std::make_pair(0U, &X86::GR32RegClass);
26982 return std::make_pair(0U, &X86::GR64RegClass);
26983 case 'R': // LEGACY_REGS
26984 if (VT == MVT::i8 || VT == MVT::i1)
26985 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26986 if (VT == MVT::i16)
26987 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26988 if (VT == MVT::i32 || !Subtarget->is64Bit())
26989 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26990 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26991 case 'f': // FP Stack registers.
26992 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26993 // value to the correct fpstack register class.
26994 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26995 return std::make_pair(0U, &X86::RFP32RegClass);
26996 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26997 return std::make_pair(0U, &X86::RFP64RegClass);
26998 return std::make_pair(0U, &X86::RFP80RegClass);
26999 case 'y': // MMX_REGS if MMX allowed.
27000 if (!Subtarget->hasMMX()) break;
27001 return std::make_pair(0U, &X86::VR64RegClass);
27002 case 'Y': // SSE_REGS if SSE2 allowed
27003 if (!Subtarget->hasSSE2()) break;
27005 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27006 if (!Subtarget->hasSSE1()) break;
27008 switch (VT.SimpleTy) {
27010 // Scalar SSE types.
27013 return std::make_pair(0U, &X86::FR32RegClass);
27016 return std::make_pair(0U, &X86::FR64RegClass);
27024 return std::make_pair(0U, &X86::VR128RegClass);
27032 return std::make_pair(0U, &X86::VR256RegClass);
27037 return std::make_pair(0U, &X86::VR512RegClass);
27043 // Use the default implementation in TargetLowering to convert the register
27044 // constraint into a member of a register class.
27045 std::pair<unsigned, const TargetRegisterClass*> Res;
27046 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27048 // Not found as a standard register?
27050 // Map st(0) -> st(7) -> ST0
27051 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27052 tolower(Constraint[1]) == 's' &&
27053 tolower(Constraint[2]) == 't' &&
27054 Constraint[3] == '(' &&
27055 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27056 Constraint[5] == ')' &&
27057 Constraint[6] == '}') {
27059 Res.first = X86::FP0+Constraint[4]-'0';
27060 Res.second = &X86::RFP80RegClass;
27064 // GCC allows "st(0)" to be called just plain "st".
27065 if (StringRef("{st}").equals_lower(Constraint)) {
27066 Res.first = X86::FP0;
27067 Res.second = &X86::RFP80RegClass;
27072 if (StringRef("{flags}").equals_lower(Constraint)) {
27073 Res.first = X86::EFLAGS;
27074 Res.second = &X86::CCRRegClass;
27078 // 'A' means EAX + EDX.
27079 if (Constraint == "A") {
27080 Res.first = X86::EAX;
27081 Res.second = &X86::GR32_ADRegClass;
27087 // Otherwise, check to see if this is a register class of the wrong value
27088 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27089 // turn into {ax},{dx}.
27090 // MVT::Other is used to specify clobber names.
27091 if (Res.second->hasType(VT) || VT == MVT::Other)
27092 return Res; // Correct type already, nothing to do.
27094 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27095 // return "eax". This should even work for things like getting 64bit integer
27096 // registers when given an f64 type.
27097 const TargetRegisterClass *Class = Res.second;
27098 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27099 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27100 unsigned Size = VT.getSizeInBits();
27101 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27102 : Size == 16 ? MVT::i16
27103 : Size == 32 ? MVT::i32
27104 : Size == 64 ? MVT::i64
27106 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27108 Res.first = DestReg;
27109 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27110 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27111 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27112 : &X86::GR64RegClass;
27113 assert(Res.second->contains(Res.first) && "Register in register class");
27115 // No register found/type mismatch.
27117 Res.second = nullptr;
27119 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27120 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27121 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27122 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27123 Class == &X86::VR512RegClass) {
27124 // Handle references to XMM physical registers that got mapped into the
27125 // wrong class. This can happen with constraints like {xmm0} where the
27126 // target independent register mapper will just pick the first match it can
27127 // find, ignoring the required type.
27129 if (VT == MVT::f32 || VT == MVT::i32)
27130 Res.second = &X86::FR32RegClass;
27131 else if (VT == MVT::f64 || VT == MVT::i64)
27132 Res.second = &X86::FR64RegClass;
27133 else if (X86::VR128RegClass.hasType(VT))
27134 Res.second = &X86::VR128RegClass;
27135 else if (X86::VR256RegClass.hasType(VT))
27136 Res.second = &X86::VR256RegClass;
27137 else if (X86::VR512RegClass.hasType(VT))
27138 Res.second = &X86::VR512RegClass;
27140 // Type mismatch and not a clobber: Return an error;
27142 Res.second = nullptr;
27149 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27150 const AddrMode &AM, Type *Ty,
27151 unsigned AS) const {
27152 // Scaling factors are not free at all.
27153 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27154 // will take 2 allocations in the out of order engine instead of 1
27155 // for plain addressing mode, i.e. inst (reg1).
27157 // vaddps (%rsi,%drx), %ymm0, %ymm1
27158 // Requires two allocations (one for the load, one for the computation)
27160 // vaddps (%rsi), %ymm0, %ymm1
27161 // Requires just 1 allocation, i.e., freeing allocations for other operations
27162 // and having less micro operations to execute.
27164 // For some X86 architectures, this is even worse because for instance for
27165 // stores, the complex addressing mode forces the instruction to use the
27166 // "load" ports instead of the dedicated "store" port.
27167 // E.g., on Haswell:
27168 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27169 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27170 if (isLegalAddressingMode(DL, AM, Ty, AS))
27171 // Scale represents reg2 * scale, thus account for 1
27172 // as soon as we use a second register.
27173 return AM.Scale != 0;
27177 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27178 // Integer division on x86 is expensive. However, when aggressively optimizing
27179 // for code size, we prefer to use a div instruction, as it is usually smaller
27180 // than the alternative sequence.
27181 // The exception to this is vector division. Since x86 doesn't have vector
27182 // integer division, leaving the division as-is is a loss even in terms of
27183 // size, because it will have to be scalarized, while the alternative code
27184 // sequence can be performed in vector form.
27185 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27186 Attribute::MinSize);
27187 return OptSize && !VT.isVector();