1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/StringExtras.h"
41 #include "llvm/Support/CommandLine.h"
45 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
47 // Forward declarations.
48 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl);
50 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
51 : TargetLowering(TM) {
52 Subtarget = &TM.getSubtarget<X86Subtarget>();
53 X86ScalarSSEf64 = Subtarget->hasSSE2();
54 X86ScalarSSEf32 = Subtarget->hasSSE1();
55 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
59 RegInfo = TM.getRegisterInfo();
62 // Set up the TargetLowering object.
64 // X86 is weird, it always uses i8 for shift amounts and setcc results.
65 setShiftAmountType(MVT::i8);
66 setBooleanContents(ZeroOrOneBooleanContent);
67 setSchedulingPreference(SchedulingForRegPressure);
68 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
69 setStackPointerRegisterToSaveRestore(X86StackPtr);
71 if (Subtarget->isTargetDarwin()) {
72 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(false);
74 setUseUnderscoreLongJmp(false);
75 } else if (Subtarget->isTargetMingw()) {
76 // MS runtime is weird: it exports _setjmp, but longjmp!
77 setUseUnderscoreSetJmp(true);
78 setUseUnderscoreLongJmp(false);
80 setUseUnderscoreSetJmp(true);
81 setUseUnderscoreLongJmp(true);
84 // Set up the register classes.
85 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
86 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
87 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
88 if (Subtarget->is64Bit())
89 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 // We don't accept any truncstore of integer registers.
94 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
95 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
96 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
97 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
98 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
99 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
101 // SETOEQ and SETUNE require checking two conditions.
102 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
103 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
104 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
105 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
106 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
107 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
109 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
111 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
112 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
113 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
115 if (Subtarget->is64Bit()) {
116 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
117 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
119 if (!UseSoftFloat && !NoImplicitFloat && X86ScalarSSEf64) {
120 // We have an impenetrably clever algorithm for ui64->double only.
121 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
123 // We have faster algorithm for ui32->single only.
124 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
126 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
130 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
132 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
133 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
135 if (!UseSoftFloat && !NoImplicitFloat) {
136 // SSE has no i16 to fp conversion, only i32
137 if (X86ScalarSSEf32) {
138 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
139 // f32 and f64 cases are Legal, f80 case is not
140 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
142 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
143 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
146 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
147 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
150 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
151 // are Legal, f80 is custom lowered.
152 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
153 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
155 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
157 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
158 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
160 if (X86ScalarSSEf32) {
161 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
162 // f32 and f64 cases are Legal, f80 case is not
163 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
165 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
166 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
169 // Handle FP_TO_UINT by promoting the destination to a larger signed
171 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
172 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
173 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
175 if (Subtarget->is64Bit()) {
176 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
177 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
179 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
180 // Expand FP_TO_UINT into a select.
181 // FIXME: We would like to use a Custom expander here eventually to do
182 // the optimal thing for SSE vs. the default expansion in the legalizer.
183 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
185 // With SSE3 we can use fisttpll to convert to a signed i64.
186 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
189 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
190 if (!X86ScalarSSEf64) {
191 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
192 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
195 // Scalar integer divide and remainder are lowered to use operations that
196 // produce two results, to match the available instructions. This exposes
197 // the two-result form to trivial CSE, which is able to combine x/y and x%y
198 // into a single instruction.
200 // Scalar integer multiply-high is also lowered to use two-result
201 // operations, to match the available instructions. However, plain multiply
202 // (low) operations are left as Legal, as there are single-result
203 // instructions for this in x86. Using the two-result multiply instructions
204 // when both high and low results are needed must be arranged by dagcombine.
205 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
206 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
207 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
208 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
209 setOperationAction(ISD::SREM , MVT::i8 , Expand);
210 setOperationAction(ISD::UREM , MVT::i8 , Expand);
211 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
212 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
213 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
214 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
215 setOperationAction(ISD::SREM , MVT::i16 , Expand);
216 setOperationAction(ISD::UREM , MVT::i16 , Expand);
217 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
218 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
219 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
220 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
221 setOperationAction(ISD::SREM , MVT::i32 , Expand);
222 setOperationAction(ISD::UREM , MVT::i32 , Expand);
223 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
224 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
225 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
226 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
227 setOperationAction(ISD::SREM , MVT::i64 , Expand);
228 setOperationAction(ISD::UREM , MVT::i64 , Expand);
230 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
231 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
232 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
233 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
234 if (Subtarget->is64Bit())
235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
236 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
237 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
238 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
239 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
240 setOperationAction(ISD::FREM , MVT::f32 , Expand);
241 setOperationAction(ISD::FREM , MVT::f64 , Expand);
242 setOperationAction(ISD::FREM , MVT::f80 , Expand);
243 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
245 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
246 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
247 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
248 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
249 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
250 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
251 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
252 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
253 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
254 if (Subtarget->is64Bit()) {
255 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
256 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
257 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
260 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
261 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
263 // These should be promoted to a larger select which is supported.
264 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
265 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
266 // X86 wants to expand cmov itself.
267 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
268 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
269 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
270 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
271 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
272 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
273 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
274 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
275 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
276 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
277 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
278 if (Subtarget->is64Bit()) {
279 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
280 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
282 // X86 ret instruction may pop stack.
283 setOperationAction(ISD::RET , MVT::Other, Custom);
284 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
287 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
288 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
289 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
290 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
291 if (Subtarget->is64Bit())
292 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
293 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
294 if (Subtarget->is64Bit()) {
295 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
296 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
297 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
298 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
300 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
301 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
302 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
303 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
304 if (Subtarget->is64Bit()) {
305 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
306 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
307 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
310 if (Subtarget->hasSSE1())
311 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
313 if (!Subtarget->hasSSE2())
314 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
316 // Expand certain atomics
317 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
318 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
319 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
320 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
322 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
323 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
324 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
325 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
327 if (!Subtarget->is64Bit()) {
328 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
329 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
330 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
331 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
332 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
333 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
334 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
337 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
338 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
339 // FIXME - use subtarget debug flags
340 if (!Subtarget->isTargetDarwin() &&
341 !Subtarget->isTargetELF() &&
342 !Subtarget->isTargetCygMing()) {
343 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
344 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
347 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
348 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
349 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
350 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
351 if (Subtarget->is64Bit()) {
352 setExceptionPointerRegister(X86::RAX);
353 setExceptionSelectorRegister(X86::RDX);
355 setExceptionPointerRegister(X86::EAX);
356 setExceptionSelectorRegister(X86::EDX);
358 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
359 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
361 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
363 setOperationAction(ISD::TRAP, MVT::Other, Legal);
365 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
366 setOperationAction(ISD::VASTART , MVT::Other, Custom);
367 setOperationAction(ISD::VAEND , MVT::Other, Expand);
368 if (Subtarget->is64Bit()) {
369 setOperationAction(ISD::VAARG , MVT::Other, Custom);
370 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
372 setOperationAction(ISD::VAARG , MVT::Other, Expand);
373 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
376 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
377 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
378 if (Subtarget->is64Bit())
379 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
380 if (Subtarget->isTargetCygMing())
381 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
383 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
385 if (!UseSoftFloat && X86ScalarSSEf64) {
386 // f32 and f64 use SSE.
387 // Set up the FP register classes.
388 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
389 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
391 // Use ANDPD to simulate FABS.
392 setOperationAction(ISD::FABS , MVT::f64, Custom);
393 setOperationAction(ISD::FABS , MVT::f32, Custom);
395 // Use XORP to simulate FNEG.
396 setOperationAction(ISD::FNEG , MVT::f64, Custom);
397 setOperationAction(ISD::FNEG , MVT::f32, Custom);
399 // Use ANDPD and ORPD to simulate FCOPYSIGN.
400 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
401 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
403 // We don't support sin/cos/fmod
404 setOperationAction(ISD::FSIN , MVT::f64, Expand);
405 setOperationAction(ISD::FCOS , MVT::f64, Expand);
406 setOperationAction(ISD::FSIN , MVT::f32, Expand);
407 setOperationAction(ISD::FCOS , MVT::f32, Expand);
409 // Expand FP immediates into loads from the stack, except for the special
411 addLegalFPImmediate(APFloat(+0.0)); // xorpd
412 addLegalFPImmediate(APFloat(+0.0f)); // xorps
414 // Floating truncations from f80 and extensions to f80 go through memory.
415 // If optimizing, we lie about this though and handle it in
416 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
418 setConvertAction(MVT::f32, MVT::f80, Expand);
419 setConvertAction(MVT::f64, MVT::f80, Expand);
420 setConvertAction(MVT::f80, MVT::f32, Expand);
421 setConvertAction(MVT::f80, MVT::f64, Expand);
423 } else if (!UseSoftFloat && X86ScalarSSEf32) {
424 // Use SSE for f32, x87 for f64.
425 // Set up the FP register classes.
426 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
427 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
429 // Use ANDPS to simulate FABS.
430 setOperationAction(ISD::FABS , MVT::f32, Custom);
432 // Use XORP to simulate FNEG.
433 setOperationAction(ISD::FNEG , MVT::f32, Custom);
435 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
437 // Use ANDPS and ORPS to simulate FCOPYSIGN.
438 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
439 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
441 // We don't support sin/cos/fmod
442 setOperationAction(ISD::FSIN , MVT::f32, Expand);
443 setOperationAction(ISD::FCOS , MVT::f32, Expand);
445 // Special cases we handle for FP constants.
446 addLegalFPImmediate(APFloat(+0.0f)); // xorps
447 addLegalFPImmediate(APFloat(+0.0)); // FLD0
448 addLegalFPImmediate(APFloat(+1.0)); // FLD1
449 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
450 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
452 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
453 // this though and handle it in InstructionSelectPreprocess so that
454 // dagcombine2 can hack on these.
456 setConvertAction(MVT::f32, MVT::f64, Expand);
457 setConvertAction(MVT::f32, MVT::f80, Expand);
458 setConvertAction(MVT::f80, MVT::f32, Expand);
459 setConvertAction(MVT::f64, MVT::f32, Expand);
460 // And x87->x87 truncations also.
461 setConvertAction(MVT::f80, MVT::f64, Expand);
465 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
466 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
468 } else if (!UseSoftFloat) {
469 // f32 and f64 in x87.
470 // Set up the FP register classes.
471 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
472 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
474 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
475 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
476 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
477 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
479 // Floating truncations go through memory. If optimizing, we lie about
480 // this though and handle it in InstructionSelectPreprocess so that
481 // dagcombine2 can hack on these.
483 setConvertAction(MVT::f80, MVT::f32, Expand);
484 setConvertAction(MVT::f64, MVT::f32, Expand);
485 setConvertAction(MVT::f80, MVT::f64, Expand);
489 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
490 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
492 addLegalFPImmediate(APFloat(+0.0)); // FLD0
493 addLegalFPImmediate(APFloat(+1.0)); // FLD1
494 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
495 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
496 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
497 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
498 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
499 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
502 // Long double always uses X87.
504 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
505 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
506 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
509 APFloat TmpFlt(+0.0);
510 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
512 addLegalFPImmediate(TmpFlt); // FLD0
514 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
515 APFloat TmpFlt2(+1.0);
516 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
518 addLegalFPImmediate(TmpFlt2); // FLD1
519 TmpFlt2.changeSign();
520 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
524 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
525 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
529 // Always use a library call for pow.
530 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
531 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
532 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
534 setOperationAction(ISD::FLOG, MVT::f80, Expand);
535 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
536 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
537 setOperationAction(ISD::FEXP, MVT::f80, Expand);
538 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
540 // First set operation action for all vector types to either promote
541 // (for widening) or expand (for scalarization). Then we will selectively
542 // turn on ones that can be effectively codegen'd.
543 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
544 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
545 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
560 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
590 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
591 // with -msoft-float, disable use of MMX as well.
592 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
593 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
594 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
595 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
596 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
597 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
599 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
600 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
601 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
602 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
604 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
605 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
606 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
607 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
609 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
610 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
612 setOperationAction(ISD::AND, MVT::v8i8, Promote);
613 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
614 setOperationAction(ISD::AND, MVT::v4i16, Promote);
615 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
616 setOperationAction(ISD::AND, MVT::v2i32, Promote);
617 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
618 setOperationAction(ISD::AND, MVT::v1i64, Legal);
620 setOperationAction(ISD::OR, MVT::v8i8, Promote);
621 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
622 setOperationAction(ISD::OR, MVT::v4i16, Promote);
623 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
624 setOperationAction(ISD::OR, MVT::v2i32, Promote);
625 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
626 setOperationAction(ISD::OR, MVT::v1i64, Legal);
628 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
629 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
630 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
631 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
632 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
633 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
634 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
636 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
637 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
638 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
639 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
640 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
641 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
642 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
643 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
644 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
646 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
647 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
648 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
649 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
650 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
652 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
653 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
654 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
655 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
657 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
658 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
659 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
660 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
662 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
664 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
665 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
666 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
667 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
668 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
669 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
672 if (!UseSoftFloat && Subtarget->hasSSE1()) {
673 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
675 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
676 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
677 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
678 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
679 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
680 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
681 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
682 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
683 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
684 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
685 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
686 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
689 if (!UseSoftFloat && Subtarget->hasSSE2()) {
690 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
692 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
693 // registers cannot be used even for integer operations.
694 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
695 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
696 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
697 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
699 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
700 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
701 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
702 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
703 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
704 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
705 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
706 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
707 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
708 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
709 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
710 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
711 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
712 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
713 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
714 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
716 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
717 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
718 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
719 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
721 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
722 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
723 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
724 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
725 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
727 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
728 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
729 MVT VT = (MVT::SimpleValueType)i;
730 // Do not attempt to custom lower non-power-of-2 vectors
731 if (!isPowerOf2_32(VT.getVectorNumElements()))
733 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
734 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
735 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
738 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
739 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
740 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
741 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
742 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
743 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
745 if (Subtarget->is64Bit()) {
746 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
747 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
750 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
751 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
752 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
753 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
754 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
755 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
756 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
757 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
758 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
759 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
760 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
761 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
764 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
766 // Custom lower v2i64 and v2f64 selects.
767 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
768 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
769 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
770 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
774 if (Subtarget->hasSSE41()) {
775 // FIXME: Do we need to handle scalar-to-vector here?
776 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
778 // i8 and i16 vectors are custom , because the source register and source
779 // source memory operand types are not the same width. f32 vectors are
780 // custom since the immediate controlling the insert encodes additional
782 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
783 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
784 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
785 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
787 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
788 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
790 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
792 if (Subtarget->is64Bit()) {
793 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
798 if (Subtarget->hasSSE42()) {
799 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
802 // We want to custom lower some of our intrinsics.
803 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
805 // Add/Sub/Mul with overflow operations are custom lowered.
806 setOperationAction(ISD::SADDO, MVT::i32, Custom);
807 setOperationAction(ISD::SADDO, MVT::i64, Custom);
808 setOperationAction(ISD::UADDO, MVT::i32, Custom);
809 setOperationAction(ISD::UADDO, MVT::i64, Custom);
810 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
811 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
812 setOperationAction(ISD::USUBO, MVT::i32, Custom);
813 setOperationAction(ISD::USUBO, MVT::i64, Custom);
814 setOperationAction(ISD::SMULO, MVT::i32, Custom);
815 setOperationAction(ISD::SMULO, MVT::i64, Custom);
816 setOperationAction(ISD::UMULO, MVT::i32, Custom);
817 setOperationAction(ISD::UMULO, MVT::i64, Custom);
819 // We have target-specific dag combine patterns for the following nodes:
820 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
821 setTargetDAGCombine(ISD::BUILD_VECTOR);
822 setTargetDAGCombine(ISD::SELECT);
823 setTargetDAGCombine(ISD::SHL);
824 setTargetDAGCombine(ISD::SRA);
825 setTargetDAGCombine(ISD::SRL);
826 setTargetDAGCombine(ISD::STORE);
827 if (Subtarget->is64Bit())
828 setTargetDAGCombine(ISD::MUL);
830 computeRegisterProperties();
832 // FIXME: These should be based on subtarget info. Plus, the values should
833 // be smaller when we are in optimizing for size mode.
834 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
835 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
836 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
837 allowUnalignedMemoryAccesses = true; // x86 supports it!
838 setPrefLoopAlignment(16);
842 MVT X86TargetLowering::getSetCCResultType(MVT VT) const {
847 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
848 /// the desired ByVal argument alignment.
849 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
852 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
853 if (VTy->getBitWidth() == 128)
855 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
856 unsigned EltAlign = 0;
857 getMaxByValAlign(ATy->getElementType(), EltAlign);
858 if (EltAlign > MaxAlign)
860 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
861 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
862 unsigned EltAlign = 0;
863 getMaxByValAlign(STy->getElementType(i), EltAlign);
864 if (EltAlign > MaxAlign)
873 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
874 /// function arguments in the caller parameter area. For X86, aggregates
875 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
876 /// are at 4-byte boundaries.
877 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
878 if (Subtarget->is64Bit()) {
879 // Max of 8 and alignment of type.
880 unsigned TyAlign = TD->getABITypeAlignment(Ty);
887 if (Subtarget->hasSSE1())
888 getMaxByValAlign(Ty, Align);
892 /// getOptimalMemOpType - Returns the target specific optimal type for load
893 /// and store operations as a result of memset, memcpy, and memmove
894 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
897 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
898 bool isSrcConst, bool isSrcStr) const {
899 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
900 // linux. This is because the stack realignment code can't handle certain
901 // cases like PR2962. This should be removed when PR2962 is fixed.
902 if (!NoImplicitFloat && Subtarget->getStackAlignment() >= 16) {
903 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
905 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
908 if (Subtarget->is64Bit() && Size >= 8)
913 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
915 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
916 SelectionDAG &DAG) const {
917 if (usesGlobalOffsetTable())
918 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
919 if (!Subtarget->isPICStyleRIPRel())
920 // This doesn't have DebugLoc associated with it, but is not really the
921 // same as a Register.
922 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
927 //===----------------------------------------------------------------------===//
928 // Return Value Calling Convention Implementation
929 //===----------------------------------------------------------------------===//
931 #include "X86GenCallingConv.inc"
933 /// LowerRET - Lower an ISD::RET node.
934 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
935 DebugLoc dl = Op.getDebugLoc();
936 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
938 SmallVector<CCValAssign, 16> RVLocs;
939 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
940 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
941 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
942 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
944 // If this is the first return lowered for this function, add the regs to the
945 // liveout set for the function.
946 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
947 for (unsigned i = 0; i != RVLocs.size(); ++i)
948 if (RVLocs[i].isRegLoc())
949 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
951 SDValue Chain = Op.getOperand(0);
953 // Handle tail call return.
954 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
955 if (Chain.getOpcode() == X86ISD::TAILCALL) {
956 SDValue TailCall = Chain;
957 SDValue TargetAddress = TailCall.getOperand(1);
958 SDValue StackAdjustment = TailCall.getOperand(2);
959 assert(((TargetAddress.getOpcode() == ISD::Register &&
960 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
961 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
962 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
963 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
964 "Expecting an global address, external symbol, or register");
965 assert(StackAdjustment.getOpcode() == ISD::Constant &&
966 "Expecting a const value");
968 SmallVector<SDValue,8> Operands;
969 Operands.push_back(Chain.getOperand(0));
970 Operands.push_back(TargetAddress);
971 Operands.push_back(StackAdjustment);
972 // Copy registers used by the call. Last operand is a flag so it is not
974 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
975 Operands.push_back(Chain.getOperand(i));
977 return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0],
984 SmallVector<SDValue, 6> RetOps;
985 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
986 // Operand #1 = Bytes To Pop
987 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
989 // Copy the result values into the output registers.
990 for (unsigned i = 0; i != RVLocs.size(); ++i) {
991 CCValAssign &VA = RVLocs[i];
992 assert(VA.isRegLoc() && "Can only return in registers!");
993 SDValue ValToCopy = Op.getOperand(i*2+1);
995 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
996 // the RET instruction and handled by the FP Stackifier.
997 if (VA.getLocReg() == X86::ST0 ||
998 VA.getLocReg() == X86::ST1) {
999 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1000 // change the value to the FP stack register class.
1001 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1002 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1003 RetOps.push_back(ValToCopy);
1004 // Don't emit a copytoreg.
1008 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1009 // which is returned in RAX / RDX.
1010 if (Subtarget->is64Bit()) {
1011 MVT ValVT = ValToCopy.getValueType();
1012 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1013 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1014 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1015 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1019 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1020 Flag = Chain.getValue(1);
1023 // The x86-64 ABI for returning structs by value requires that we copy
1024 // the sret argument into %rax for the return. We saved the argument into
1025 // a virtual register in the entry block, so now we copy the value out
1027 if (Subtarget->is64Bit() &&
1028 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1029 MachineFunction &MF = DAG.getMachineFunction();
1030 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1031 unsigned Reg = FuncInfo->getSRetReturnReg();
1033 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1034 FuncInfo->setSRetReturnReg(Reg);
1036 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1038 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1039 Flag = Chain.getValue(1);
1042 RetOps[0] = Chain; // Update chain.
1044 // Add the flag if we have it.
1046 RetOps.push_back(Flag);
1048 return DAG.getNode(X86ISD::RET_FLAG, dl,
1049 MVT::Other, &RetOps[0], RetOps.size());
1053 /// LowerCallResult - Lower the result values of an ISD::CALL into the
1054 /// appropriate copies out of appropriate physical registers. This assumes that
1055 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
1056 /// being lowered. The returns a SDNode with the same number of values as the
1058 SDNode *X86TargetLowering::
1059 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
1060 unsigned CallingConv, SelectionDAG &DAG) {
1062 DebugLoc dl = TheCall->getDebugLoc();
1063 // Assign locations to each value returned by this call.
1064 SmallVector<CCValAssign, 16> RVLocs;
1065 bool isVarArg = TheCall->isVarArg();
1066 bool Is64Bit = Subtarget->is64Bit();
1067 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
1068 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
1070 SmallVector<SDValue, 8> ResultVals;
1072 // Copy all of the result registers out of their specified physreg.
1073 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1074 CCValAssign &VA = RVLocs[i];
1075 MVT CopyVT = VA.getValVT();
1077 // If this is x86-64, and we disabled SSE, we can't return FP values
1078 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1079 ((Is64Bit || TheCall->isInreg()) && !Subtarget->hasSSE1())) {
1080 cerr << "SSE register return with SSE disabled\n";
1084 // If this is a call to a function that returns an fp value on the floating
1085 // point stack, but where we prefer to use the value in xmm registers, copy
1086 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1087 if ((VA.getLocReg() == X86::ST0 ||
1088 VA.getLocReg() == X86::ST1) &&
1089 isScalarFPTypeInSSEReg(VA.getValVT())) {
1094 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1095 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1096 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1097 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1098 MVT::v2i64, InFlag).getValue(1);
1099 Val = Chain.getValue(0);
1100 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1101 Val, DAG.getConstant(0, MVT::i64));
1103 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1104 MVT::i64, InFlag).getValue(1);
1105 Val = Chain.getValue(0);
1107 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1109 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1110 CopyVT, InFlag).getValue(1);
1111 Val = Chain.getValue(0);
1113 InFlag = Chain.getValue(2);
1115 if (CopyVT != VA.getValVT()) {
1116 // Round the F80 the right size, which also moves to the appropriate xmm
1118 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1119 // This truncation won't change the value.
1120 DAG.getIntPtrConstant(1));
1123 ResultVals.push_back(Val);
1126 // Merge everything together with a MERGE_VALUES node.
1127 ResultVals.push_back(Chain);
1128 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
1129 &ResultVals[0], ResultVals.size()).getNode();
1133 //===----------------------------------------------------------------------===//
1134 // C & StdCall & Fast Calling Convention implementation
1135 //===----------------------------------------------------------------------===//
1136 // StdCall calling convention seems to be standard for many Windows' API
1137 // routines and around. It differs from C calling convention just a little:
1138 // callee should clean up the stack, not caller. Symbols should be also
1139 // decorated in some fancy way :) It doesn't support any vector arguments.
1140 // For info on fast calling convention see Fast Calling Convention (tail call)
1141 // implementation LowerX86_32FastCCCallTo.
1143 /// AddLiveIn - This helper function adds the specified physical register to the
1144 /// MachineFunction as a live in value. It also creates a corresponding virtual
1145 /// register for it.
1146 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
1147 const TargetRegisterClass *RC) {
1148 assert(RC->contains(PReg) && "Not the correct regclass!");
1149 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1150 MF.getRegInfo().addLiveIn(PReg, VReg);
1154 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1156 static bool CallIsStructReturn(CallSDNode *TheCall) {
1157 unsigned NumOps = TheCall->getNumArgs();
1161 return TheCall->getArgFlags(0).isSRet();
1164 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1165 /// return semantics.
1166 static bool ArgsAreStructReturn(SDValue Op) {
1167 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1171 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1174 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1175 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1177 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1181 switch (CallingConv) {
1184 case CallingConv::X86_StdCall:
1185 return !Subtarget->is64Bit();
1186 case CallingConv::X86_FastCall:
1187 return !Subtarget->is64Bit();
1188 case CallingConv::Fast:
1189 return PerformTailCallOpt;
1193 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1194 /// given CallingConvention value.
1195 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1196 if (Subtarget->is64Bit()) {
1197 if (Subtarget->isTargetWin64())
1198 return CC_X86_Win64_C;
1199 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1200 return CC_X86_64_TailCall;
1205 if (CC == CallingConv::X86_FastCall)
1206 return CC_X86_32_FastCall;
1207 else if (CC == CallingConv::Fast)
1208 return CC_X86_32_FastCC;
1213 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1214 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1216 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1217 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1218 if (CC == CallingConv::X86_FastCall)
1220 else if (CC == CallingConv::X86_StdCall)
1226 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1227 /// in a register before calling.
1228 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1229 return !IsTailCall && !Is64Bit &&
1230 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1231 Subtarget->isPICStyleGOT();
1234 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1235 /// address to be loaded in a register.
1237 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1238 return !Is64Bit && IsTailCall &&
1239 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1240 Subtarget->isPICStyleGOT();
1243 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1244 /// by "Src" to address "Dst" with size and alignment information specified by
1245 /// the specific parameter attribute. The copy will be passed as a byval
1246 /// function parameter.
1248 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1249 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1251 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1253 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1256 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1257 const CCValAssign &VA,
1258 MachineFrameInfo *MFI,
1260 SDValue Root, unsigned i) {
1261 // Create the nodes corresponding to a load from this parameter slot.
1262 ISD::ArgFlagsTy Flags =
1263 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1264 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1265 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1267 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1268 // changed with more analysis.
1269 // In case of tail call optimization mark all arguments mutable. Since they
1270 // could be overwritten by lowering of arguments in case of a tail call.
1271 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1272 VA.getLocMemOffset(), isImmutable);
1273 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1274 if (Flags.isByVal())
1276 return DAG.getLoad(VA.getValVT(), Op.getDebugLoc(), Root, FIN,
1277 PseudoSourceValue::getFixedStack(FI), 0);
1281 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1282 MachineFunction &MF = DAG.getMachineFunction();
1283 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1284 DebugLoc dl = Op.getDebugLoc();
1286 const Function* Fn = MF.getFunction();
1287 if (Fn->hasExternalLinkage() &&
1288 Subtarget->isTargetCygMing() &&
1289 Fn->getName() == "main")
1290 FuncInfo->setForceFramePointer(true);
1292 // Decorate the function name.
1293 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1295 MachineFrameInfo *MFI = MF.getFrameInfo();
1296 SDValue Root = Op.getOperand(0);
1297 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1298 unsigned CC = MF.getFunction()->getCallingConv();
1299 bool Is64Bit = Subtarget->is64Bit();
1300 bool IsWin64 = Subtarget->isTargetWin64();
1302 assert(!(isVarArg && CC == CallingConv::Fast) &&
1303 "Var args not supported with calling convention fastcc");
1305 // Assign locations to all of the incoming arguments.
1306 SmallVector<CCValAssign, 16> ArgLocs;
1307 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1308 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
1310 SmallVector<SDValue, 8> ArgValues;
1311 unsigned LastVal = ~0U;
1312 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1313 CCValAssign &VA = ArgLocs[i];
1314 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1316 assert(VA.getValNo() != LastVal &&
1317 "Don't support value assigned to multiple locs yet");
1318 LastVal = VA.getValNo();
1320 if (VA.isRegLoc()) {
1321 MVT RegVT = VA.getLocVT();
1322 TargetRegisterClass *RC = NULL;
1323 if (RegVT == MVT::i32)
1324 RC = X86::GR32RegisterClass;
1325 else if (Is64Bit && RegVT == MVT::i64)
1326 RC = X86::GR64RegisterClass;
1327 else if (RegVT == MVT::f32)
1328 RC = X86::FR32RegisterClass;
1329 else if (RegVT == MVT::f64)
1330 RC = X86::FR64RegisterClass;
1331 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1332 RC = X86::VR128RegisterClass;
1333 else if (RegVT.isVector()) {
1334 assert(RegVT.getSizeInBits() == 64);
1336 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1338 // Darwin calling convention passes MMX values in either GPRs or
1339 // XMMs in x86-64. Other targets pass them in memory.
1340 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1341 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1344 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1349 assert(0 && "Unknown argument type!");
1352 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1353 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1355 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1356 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1358 if (VA.getLocInfo() == CCValAssign::SExt)
1359 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1360 DAG.getValueType(VA.getValVT()));
1361 else if (VA.getLocInfo() == CCValAssign::ZExt)
1362 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1363 DAG.getValueType(VA.getValVT()));
1365 if (VA.getLocInfo() != CCValAssign::Full)
1366 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1368 // Handle MMX values passed in GPRs.
1369 if (Is64Bit && RegVT != VA.getLocVT()) {
1370 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1371 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
1372 else if (RC == X86::VR128RegisterClass) {
1373 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1374 ArgValue, DAG.getConstant(0, MVT::i64));
1375 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
1379 ArgValues.push_back(ArgValue);
1381 assert(VA.isMemLoc());
1382 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1386 // The x86-64 ABI for returning structs by value requires that we copy
1387 // the sret argument into %rax for the return. Save the argument into
1388 // a virtual register so that we can access it from the return points.
1389 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1390 MachineFunction &MF = DAG.getMachineFunction();
1391 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1392 unsigned Reg = FuncInfo->getSRetReturnReg();
1394 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1395 FuncInfo->setSRetReturnReg(Reg);
1397 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
1398 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
1401 unsigned StackSize = CCInfo.getNextStackOffset();
1402 // align stack specially for tail calls
1403 if (PerformTailCallOpt && CC == CallingConv::Fast)
1404 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1406 // If the function takes variable number of arguments, make a frame index for
1407 // the start of the first vararg value... for expansion of llvm.va_start.
1409 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1410 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1413 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1415 // FIXME: We should really autogenerate these arrays
1416 static const unsigned GPR64ArgRegsWin64[] = {
1417 X86::RCX, X86::RDX, X86::R8, X86::R9
1419 static const unsigned XMMArgRegsWin64[] = {
1420 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1422 static const unsigned GPR64ArgRegs64Bit[] = {
1423 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1425 static const unsigned XMMArgRegs64Bit[] = {
1426 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1427 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1429 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1432 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1433 GPR64ArgRegs = GPR64ArgRegsWin64;
1434 XMMArgRegs = XMMArgRegsWin64;
1436 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1437 GPR64ArgRegs = GPR64ArgRegs64Bit;
1438 XMMArgRegs = XMMArgRegs64Bit;
1440 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1442 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1445 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1446 "SSE register cannot be used when SSE is disabled!");
1447 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloat) &&
1448 "SSE register cannot be used when SSE is disabled!");
1449 if (UseSoftFloat || NoImplicitFloat || !Subtarget->hasSSE1())
1450 // Kernel mode asks for SSE to be disabled, so don't push them
1452 TotalNumXMMRegs = 0;
1454 // For X86-64, if there are vararg parameters that are passed via
1455 // registers, then we must store them to their spots on the stack so they
1456 // may be loaded by deferencing the result of va_next.
1457 VarArgsGPOffset = NumIntRegs * 8;
1458 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1459 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1460 TotalNumXMMRegs * 16, 16);
1462 // Store the integer parameter registers.
1463 SmallVector<SDValue, 8> MemOps;
1464 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1465 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1466 DAG.getIntPtrConstant(VarArgsGPOffset));
1467 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1468 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1469 X86::GR64RegisterClass);
1470 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
1472 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1473 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1474 MemOps.push_back(Store);
1475 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1476 DAG.getIntPtrConstant(8));
1479 // Now store the XMM (fp + vector) parameter registers.
1480 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1481 DAG.getIntPtrConstant(VarArgsFPOffset));
1482 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1483 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1484 X86::VR128RegisterClass);
1485 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32);
1487 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1488 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1489 MemOps.push_back(Store);
1490 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1491 DAG.getIntPtrConstant(16));
1493 if (!MemOps.empty())
1494 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1495 &MemOps[0], MemOps.size());
1499 ArgValues.push_back(Root);
1501 // Some CCs need callee pop.
1502 if (IsCalleePop(isVarArg, CC)) {
1503 BytesToPopOnReturn = StackSize; // Callee pops everything.
1504 BytesCallerReserves = 0;
1506 BytesToPopOnReturn = 0; // Callee pops nothing.
1507 // If this is an sret function, the return should pop the hidden pointer.
1508 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
1509 BytesToPopOnReturn = 4;
1510 BytesCallerReserves = StackSize;
1514 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1515 if (CC == CallingConv::X86_FastCall)
1516 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1519 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1521 // Return the new list of results.
1522 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1523 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1527 X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
1528 const SDValue &StackPtr,
1529 const CCValAssign &VA,
1531 SDValue Arg, ISD::ArgFlagsTy Flags) {
1532 DebugLoc dl = TheCall->getDebugLoc();
1533 unsigned LocMemOffset = VA.getLocMemOffset();
1534 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1535 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1536 if (Flags.isByVal()) {
1537 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1539 return DAG.getStore(Chain, dl, Arg, PtrOff,
1540 PseudoSourceValue::getStack(), LocMemOffset);
1543 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1544 /// optimization is performed and it is required.
1546 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1547 SDValue &OutRetAddr,
1553 if (!IsTailCall || FPDiff==0) return Chain;
1555 // Adjust the Return address stack slot.
1556 MVT VT = getPointerTy();
1557 OutRetAddr = getReturnAddressFrameIndex(DAG);
1559 // Load the "old" Return address.
1560 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1561 return SDValue(OutRetAddr.getNode(), 1);
1564 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1565 /// optimization is performed and it is required (FPDiff!=0).
1567 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1568 SDValue Chain, SDValue RetAddrFrIdx,
1569 bool Is64Bit, int FPDiff, DebugLoc dl) {
1570 // Store the return address to the appropriate stack slot.
1571 if (!FPDiff) return Chain;
1572 // Calculate the new stack slot for the return address.
1573 int SlotSize = Is64Bit ? 8 : 4;
1574 int NewReturnAddrFI =
1575 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1576 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1577 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1578 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1579 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1583 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1584 MachineFunction &MF = DAG.getMachineFunction();
1585 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1586 SDValue Chain = TheCall->getChain();
1587 unsigned CC = TheCall->getCallingConv();
1588 bool isVarArg = TheCall->isVarArg();
1589 bool IsTailCall = TheCall->isTailCall() &&
1590 CC == CallingConv::Fast && PerformTailCallOpt;
1591 SDValue Callee = TheCall->getCallee();
1592 bool Is64Bit = Subtarget->is64Bit();
1593 bool IsStructRet = CallIsStructReturn(TheCall);
1594 DebugLoc dl = TheCall->getDebugLoc();
1596 assert(!(isVarArg && CC == CallingConv::Fast) &&
1597 "Var args not supported with calling convention fastcc");
1599 // Analyze operands of the call, assigning locations to each operand.
1600 SmallVector<CCValAssign, 16> ArgLocs;
1601 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1602 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
1604 // Get a count of how many bytes are to be pushed on the stack.
1605 unsigned NumBytes = CCInfo.getNextStackOffset();
1606 if (PerformTailCallOpt && CC == CallingConv::Fast)
1607 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1611 // Lower arguments at fp - stackoffset + fpdiff.
1612 unsigned NumBytesCallerPushed =
1613 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1614 FPDiff = NumBytesCallerPushed - NumBytes;
1616 // Set the delta of movement of the returnaddr stackslot.
1617 // But only set if delta is greater than previous delta.
1618 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1619 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1622 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1624 SDValue RetAddrFrIdx;
1625 // Load return adress for tail calls.
1626 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1629 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1630 SmallVector<SDValue, 8> MemOpChains;
1633 // Walk the register/memloc assignments, inserting copies/loads. In the case
1634 // of tail call optimization arguments are handle later.
1635 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1636 CCValAssign &VA = ArgLocs[i];
1637 SDValue Arg = TheCall->getArg(i);
1638 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1639 bool isByVal = Flags.isByVal();
1641 // Promote the value if needed.
1642 switch (VA.getLocInfo()) {
1643 default: assert(0 && "Unknown loc info!");
1644 case CCValAssign::Full: break;
1645 case CCValAssign::SExt:
1646 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1648 case CCValAssign::ZExt:
1649 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1651 case CCValAssign::AExt:
1652 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1656 if (VA.isRegLoc()) {
1658 MVT RegVT = VA.getLocVT();
1659 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1660 switch (VA.getLocReg()) {
1663 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1665 // Special case: passing MMX values in GPR registers.
1666 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1669 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1670 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1671 // Special case: passing MMX values in XMM registers.
1672 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1673 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1674 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64,
1675 DAG.getUNDEF(MVT::v2i64), Arg,
1676 getMOVLMask(2, DAG, dl));
1681 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1683 if (!IsTailCall || (IsTailCall && isByVal)) {
1684 assert(VA.isMemLoc());
1685 if (StackPtr.getNode() == 0)
1686 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1688 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1689 Chain, Arg, Flags));
1694 if (!MemOpChains.empty())
1695 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1696 &MemOpChains[0], MemOpChains.size());
1698 // Build a sequence of copy-to-reg nodes chained together with token chain
1699 // and flag operands which copy the outgoing args into registers.
1701 // Tail call byval lowering might overwrite argument registers so in case of
1702 // tail call optimization the copies to registers are lowered later.
1704 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1705 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1706 RegsToPass[i].second, InFlag);
1707 InFlag = Chain.getValue(1);
1710 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1712 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1713 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1714 DAG.getNode(X86ISD::GlobalBaseReg,
1715 DebugLoc::getUnknownLoc(),
1718 InFlag = Chain.getValue(1);
1720 // If we are tail calling and generating PIC/GOT style code load the address
1721 // of the callee into ecx. The value in ecx is used as target of the tail
1722 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1723 // calls on PIC/GOT architectures. Normally we would just put the address of
1724 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1725 // restored (since ebx is callee saved) before jumping to the target@PLT.
1726 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1727 // Note: The actual moving to ecx is done further down.
1728 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1729 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1730 !G->getGlobal()->hasProtectedVisibility())
1731 Callee = LowerGlobalAddress(Callee, DAG);
1732 else if (isa<ExternalSymbolSDNode>(Callee))
1733 Callee = LowerExternalSymbol(Callee,DAG);
1736 if (Is64Bit && isVarArg) {
1737 // From AMD64 ABI document:
1738 // For calls that may call functions that use varargs or stdargs
1739 // (prototype-less calls or calls to functions containing ellipsis (...) in
1740 // the declaration) %al is used as hidden argument to specify the number
1741 // of SSE registers used. The contents of %al do not need to match exactly
1742 // the number of registers, but must be an ubound on the number of SSE
1743 // registers used and is in the range 0 - 8 inclusive.
1745 // FIXME: Verify this on Win64
1746 // Count the number of XMM registers allocated.
1747 static const unsigned XMMArgRegs[] = {
1748 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1749 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1751 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1752 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1753 && "SSE registers cannot be used when SSE is disabled");
1755 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1756 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1757 InFlag = Chain.getValue(1);
1761 // For tail calls lower the arguments to the 'real' stack slot.
1763 SmallVector<SDValue, 8> MemOpChains2;
1766 // Do not flag preceeding copytoreg stuff together with the following stuff.
1768 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1769 CCValAssign &VA = ArgLocs[i];
1770 if (!VA.isRegLoc()) {
1771 assert(VA.isMemLoc());
1772 SDValue Arg = TheCall->getArg(i);
1773 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1774 // Create frame index.
1775 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1776 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1777 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1778 FIN = DAG.getFrameIndex(FI, getPointerTy());
1780 if (Flags.isByVal()) {
1781 // Copy relative to framepointer.
1782 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1783 if (StackPtr.getNode() == 0)
1784 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1786 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1788 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1791 // Store relative to framepointer.
1792 MemOpChains2.push_back(
1793 DAG.getStore(Chain, dl, Arg, FIN,
1794 PseudoSourceValue::getFixedStack(FI), 0));
1799 if (!MemOpChains2.empty())
1800 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1801 &MemOpChains2[0], MemOpChains2.size());
1803 // Copy arguments to their registers.
1804 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1805 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1806 RegsToPass[i].second, InFlag);
1807 InFlag = Chain.getValue(1);
1811 // Store the return address to the appropriate stack slot.
1812 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1816 // If the callee is a GlobalAddress node (quite common, every direct call is)
1817 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1818 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1819 // We should use extra load for direct calls to dllimported functions in
1821 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1822 getTargetMachine(), true))
1823 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(),
1825 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1826 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1827 } else if (IsTailCall) {
1828 unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
1830 Chain = DAG.getCopyToReg(Chain, dl,
1831 DAG.getRegister(Opc, getPointerTy()),
1833 Callee = DAG.getRegister(Opc, getPointerTy());
1834 // Add register as live out.
1835 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1838 // Returns a chain & a flag for retval copy to use.
1839 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1840 SmallVector<SDValue, 8> Ops;
1843 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1844 DAG.getIntPtrConstant(0, true), InFlag);
1845 InFlag = Chain.getValue(1);
1847 // Returns a chain & a flag for retval copy to use.
1848 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1852 Ops.push_back(Chain);
1853 Ops.push_back(Callee);
1856 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1858 // Add argument registers to the end of the list so that they are known live
1860 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1861 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1862 RegsToPass[i].second.getValueType()));
1864 // Add an implicit use GOT pointer in EBX.
1865 if (!IsTailCall && !Is64Bit &&
1866 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1867 Subtarget->isPICStyleGOT())
1868 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1870 // Add an implicit use of AL for x86 vararg functions.
1871 if (Is64Bit && isVarArg)
1872 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1874 if (InFlag.getNode())
1875 Ops.push_back(InFlag);
1878 assert(InFlag.getNode() &&
1879 "Flag must be set. Depend on flag being set in LowerRET");
1880 Chain = DAG.getNode(X86ISD::TAILCALL, dl,
1881 TheCall->getVTList(), &Ops[0], Ops.size());
1883 return SDValue(Chain.getNode(), Op.getResNo());
1886 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
1887 InFlag = Chain.getValue(1);
1889 // Create the CALLSEQ_END node.
1890 unsigned NumBytesForCalleeToPush;
1891 if (IsCalleePop(isVarArg, CC))
1892 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1893 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
1894 // If this is is a call to a struct-return function, the callee
1895 // pops the hidden struct pointer, so we have to push it back.
1896 // This is common for Darwin/X86, Linux & Mingw32 targets.
1897 NumBytesForCalleeToPush = 4;
1899 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1901 // Returns a flag for retval copy to use.
1902 Chain = DAG.getCALLSEQ_END(Chain,
1903 DAG.getIntPtrConstant(NumBytes, true),
1904 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
1907 InFlag = Chain.getValue(1);
1909 // Handle result values, copying them out of physregs into vregs that we
1911 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
1916 //===----------------------------------------------------------------------===//
1917 // Fast Calling Convention (tail call) implementation
1918 //===----------------------------------------------------------------------===//
1920 // Like std call, callee cleans arguments, convention except that ECX is
1921 // reserved for storing the tail called function address. Only 2 registers are
1922 // free for argument passing (inreg). Tail call optimization is performed
1924 // * tailcallopt is enabled
1925 // * caller/callee are fastcc
1926 // On X86_64 architecture with GOT-style position independent code only local
1927 // (within module) calls are supported at the moment.
1928 // To keep the stack aligned according to platform abi the function
1929 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1930 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1931 // If a tail called function callee has more arguments than the caller the
1932 // caller needs to make sure that there is room to move the RETADDR to. This is
1933 // achieved by reserving an area the size of the argument delta right after the
1934 // original REtADDR, but before the saved framepointer or the spilled registers
1935 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1947 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1948 /// for a 16 byte align requirement.
1949 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1950 SelectionDAG& DAG) {
1951 MachineFunction &MF = DAG.getMachineFunction();
1952 const TargetMachine &TM = MF.getTarget();
1953 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1954 unsigned StackAlignment = TFI.getStackAlignment();
1955 uint64_t AlignMask = StackAlignment - 1;
1956 int64_t Offset = StackSize;
1957 uint64_t SlotSize = TD->getPointerSize();
1958 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1959 // Number smaller than 12 so just add the difference.
1960 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1962 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1963 Offset = ((~AlignMask) & Offset) + StackAlignment +
1964 (StackAlignment-SlotSize);
1969 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1970 /// following the call is a return. A function is eligible if caller/callee
1971 /// calling conventions match, currently only fastcc supports tail calls, and
1972 /// the function CALL is immediatly followed by a RET.
1973 bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1975 SelectionDAG& DAG) const {
1976 if (!PerformTailCallOpt)
1979 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1980 MachineFunction &MF = DAG.getMachineFunction();
1981 unsigned CallerCC = MF.getFunction()->getCallingConv();
1982 unsigned CalleeCC= TheCall->getCallingConv();
1983 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1984 SDValue Callee = TheCall->getCallee();
1985 // On x86/32Bit PIC/GOT tail calls are supported.
1986 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1987 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1990 // Can only do local tail calls (in same module, hidden or protected) on
1991 // x86_64 PIC/GOT at the moment.
1992 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1993 return G->getGlobal()->hasHiddenVisibility()
1994 || G->getGlobal()->hasProtectedVisibility();
2002 X86TargetLowering::createFastISel(MachineFunction &mf,
2003 MachineModuleInfo *mmo,
2005 DenseMap<const Value *, unsigned> &vm,
2006 DenseMap<const BasicBlock *,
2007 MachineBasicBlock *> &bm,
2008 DenseMap<const AllocaInst *, int> &am
2010 , SmallSet<Instruction*, 8> &cil
2013 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2021 //===----------------------------------------------------------------------===//
2022 // Other Lowering Hooks
2023 //===----------------------------------------------------------------------===//
2026 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2027 MachineFunction &MF = DAG.getMachineFunction();
2028 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2029 int ReturnAddrIndex = FuncInfo->getRAIndex();
2031 if (ReturnAddrIndex == 0) {
2032 // Set up a frame object for the return address.
2033 uint64_t SlotSize = TD->getPointerSize();
2034 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
2035 FuncInfo->setRAIndex(ReturnAddrIndex);
2038 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2042 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2043 /// specific condition code, returning the condition code and the LHS/RHS of the
2044 /// comparison to make.
2045 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2046 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2048 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2049 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2050 // X > -1 -> X == 0, jump !sign.
2051 RHS = DAG.getConstant(0, RHS.getValueType());
2052 return X86::COND_NS;
2053 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2054 // X < 0 -> X == 0, jump on sign.
2056 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2058 RHS = DAG.getConstant(0, RHS.getValueType());
2059 return X86::COND_LE;
2063 switch (SetCCOpcode) {
2064 default: assert(0 && "Invalid integer condition!");
2065 case ISD::SETEQ: return X86::COND_E;
2066 case ISD::SETGT: return X86::COND_G;
2067 case ISD::SETGE: return X86::COND_GE;
2068 case ISD::SETLT: return X86::COND_L;
2069 case ISD::SETLE: return X86::COND_LE;
2070 case ISD::SETNE: return X86::COND_NE;
2071 case ISD::SETULT: return X86::COND_B;
2072 case ISD::SETUGT: return X86::COND_A;
2073 case ISD::SETULE: return X86::COND_BE;
2074 case ISD::SETUGE: return X86::COND_AE;
2078 // First determine if it is required or is profitable to flip the operands.
2080 // If LHS is a foldable load, but RHS is not, flip the condition.
2081 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2082 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2083 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2084 std::swap(LHS, RHS);
2087 switch (SetCCOpcode) {
2093 std::swap(LHS, RHS);
2097 // On a floating point condition, the flags are set as follows:
2099 // 0 | 0 | 0 | X > Y
2100 // 0 | 0 | 1 | X < Y
2101 // 1 | 0 | 0 | X == Y
2102 // 1 | 1 | 1 | unordered
2103 switch (SetCCOpcode) {
2104 default: assert(0 && "Condcode should be pre-legalized away");
2106 case ISD::SETEQ: return X86::COND_E;
2107 case ISD::SETOLT: // flipped
2109 case ISD::SETGT: return X86::COND_A;
2110 case ISD::SETOLE: // flipped
2112 case ISD::SETGE: return X86::COND_AE;
2113 case ISD::SETUGT: // flipped
2115 case ISD::SETLT: return X86::COND_B;
2116 case ISD::SETUGE: // flipped
2118 case ISD::SETLE: return X86::COND_BE;
2120 case ISD::SETNE: return X86::COND_NE;
2121 case ISD::SETUO: return X86::COND_P;
2122 case ISD::SETO: return X86::COND_NP;
2126 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2127 /// code. Current x86 isa includes the following FP cmov instructions:
2128 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2129 static bool hasFPCMov(unsigned X86CC) {
2145 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2146 /// true if Op is undef or if its value falls within the specified range (L, H].
2147 static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
2148 if (Op.getOpcode() == ISD::UNDEF)
2151 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue();
2152 return (Val >= Low && Val < Hi);
2155 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2156 /// true if Op is undef or if its value equal to the specified value.
2157 static bool isUndefOrEqual(SDValue Op, unsigned Val) {
2158 if (Op.getOpcode() == ISD::UNDEF)
2160 return cast<ConstantSDNode>(Op)->getZExtValue() == Val;
2163 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2164 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2165 bool X86::isPSHUFDMask(SDNode *N) {
2166 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2168 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2171 // Check if the value doesn't reference the second vector.
2172 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2173 SDValue Arg = N->getOperand(i);
2174 if (Arg.getOpcode() == ISD::UNDEF) continue;
2175 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2176 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e)
2183 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2184 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2185 bool X86::isPSHUFHWMask(SDNode *N) {
2186 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2188 if (N->getNumOperands() != 8)
2191 // Lower quadword copied in order.
2192 for (unsigned i = 0; i != 4; ++i) {
2193 SDValue Arg = N->getOperand(i);
2194 if (Arg.getOpcode() == ISD::UNDEF) continue;
2195 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2196 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i)
2200 // Upper quadword shuffled.
2201 for (unsigned i = 4; i != 8; ++i) {
2202 SDValue Arg = N->getOperand(i);
2203 if (Arg.getOpcode() == ISD::UNDEF) continue;
2204 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2205 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2206 if (Val < 4 || Val > 7)
2213 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2214 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2215 bool X86::isPSHUFLWMask(SDNode *N) {
2216 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2218 if (N->getNumOperands() != 8)
2221 // Upper quadword copied in order.
2222 for (unsigned i = 4; i != 8; ++i)
2223 if (!isUndefOrEqual(N->getOperand(i), i))
2226 // Lower quadword shuffled.
2227 for (unsigned i = 0; i != 4; ++i)
2228 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2234 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2235 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2236 template<class SDOperand>
2237 static bool isSHUFPMask(SDOperand *Elems, unsigned NumElems) {
2238 if (NumElems != 2 && NumElems != 4) return false;
2240 unsigned Half = NumElems / 2;
2241 for (unsigned i = 0; i < Half; ++i)
2242 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2244 for (unsigned i = Half; i < NumElems; ++i)
2245 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2251 bool X86::isSHUFPMask(SDNode *N) {
2252 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2253 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2256 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2257 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2258 /// half elements to come from vector 1 (which would equal the dest.) and
2259 /// the upper half to come from vector 2.
2260 template<class SDOperand>
2261 static bool isCommutedSHUFP(SDOperand *Ops, unsigned NumOps) {
2262 if (NumOps != 2 && NumOps != 4) return false;
2264 unsigned Half = NumOps / 2;
2265 for (unsigned i = 0; i < Half; ++i)
2266 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2268 for (unsigned i = Half; i < NumOps; ++i)
2269 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2274 static bool isCommutedSHUFP(SDNode *N) {
2275 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2276 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2279 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2280 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2281 bool X86::isMOVHLPSMask(SDNode *N) {
2282 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2284 if (N->getNumOperands() != 4)
2287 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2288 return isUndefOrEqual(N->getOperand(0), 6) &&
2289 isUndefOrEqual(N->getOperand(1), 7) &&
2290 isUndefOrEqual(N->getOperand(2), 2) &&
2291 isUndefOrEqual(N->getOperand(3), 3);
2294 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2295 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2297 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2298 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2300 if (N->getNumOperands() != 4)
2303 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2304 return isUndefOrEqual(N->getOperand(0), 2) &&
2305 isUndefOrEqual(N->getOperand(1), 3) &&
2306 isUndefOrEqual(N->getOperand(2), 2) &&
2307 isUndefOrEqual(N->getOperand(3), 3);
2310 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2311 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2312 bool X86::isMOVLPMask(SDNode *N) {
2313 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2315 unsigned NumElems = N->getNumOperands();
2316 if (NumElems != 2 && NumElems != 4)
2319 for (unsigned i = 0; i < NumElems/2; ++i)
2320 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2323 for (unsigned i = NumElems/2; i < NumElems; ++i)
2324 if (!isUndefOrEqual(N->getOperand(i), i))
2330 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2331 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2333 bool X86::isMOVHPMask(SDNode *N) {
2334 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2336 unsigned NumElems = N->getNumOperands();
2337 if (NumElems != 2 && NumElems != 4)
2340 for (unsigned i = 0; i < NumElems/2; ++i)
2341 if (!isUndefOrEqual(N->getOperand(i), i))
2344 for (unsigned i = 0; i < NumElems/2; ++i) {
2345 SDValue Arg = N->getOperand(i + NumElems/2);
2346 if (!isUndefOrEqual(Arg, i + NumElems))
2353 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2354 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2355 template<class SDOperand>
2356 bool static isUNPCKLMask(SDOperand *Elts, unsigned NumElts,
2357 bool V2IsSplat = false) {
2358 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2361 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2362 SDValue BitI = Elts[i];
2363 SDValue BitI1 = Elts[i+1];
2364 if (!isUndefOrEqual(BitI, j))
2367 if (!isUndefOrEqual(BitI1, NumElts))
2370 if (!isUndefOrEqual(BitI1, j + NumElts))
2378 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2379 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2380 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2383 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2384 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2385 template<class SDOperand>
2386 bool static isUNPCKHMask(SDOperand *Elts, unsigned NumElts,
2387 bool V2IsSplat = false) {
2388 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2391 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2392 SDValue BitI = Elts[i];
2393 SDValue BitI1 = Elts[i+1];
2394 if (!isUndefOrEqual(BitI, j + NumElts/2))
2397 if (isUndefOrEqual(BitI1, NumElts))
2400 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2408 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2409 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2410 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2413 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2414 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2416 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2417 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2419 unsigned NumElems = N->getNumOperands();
2420 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2423 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2424 SDValue BitI = N->getOperand(i);
2425 SDValue BitI1 = N->getOperand(i+1);
2427 if (!isUndefOrEqual(BitI, j))
2429 if (!isUndefOrEqual(BitI1, j))
2436 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2437 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2439 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2440 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2442 unsigned NumElems = N->getNumOperands();
2443 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2446 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2447 SDValue BitI = N->getOperand(i);
2448 SDValue BitI1 = N->getOperand(i + 1);
2450 if (!isUndefOrEqual(BitI, j))
2452 if (!isUndefOrEqual(BitI1, j))
2459 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2460 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2461 /// MOVSD, and MOVD, i.e. setting the lowest element.
2462 template<class SDOperand>
2463 static bool isMOVLMask(SDOperand *Elts, unsigned NumElts) {
2464 if (NumElts != 2 && NumElts != 4)
2467 if (!isUndefOrEqual(Elts[0], NumElts))
2470 for (unsigned i = 1; i < NumElts; ++i) {
2471 if (!isUndefOrEqual(Elts[i], i))
2478 bool X86::isMOVLMask(SDNode *N) {
2479 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2480 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2483 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2484 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2485 /// element of vector 2 and the other elements to come from vector 1 in order.
2486 template<class SDOperand>
2487 static bool isCommutedMOVL(SDOperand *Ops, unsigned NumOps,
2488 bool V2IsSplat = false,
2489 bool V2IsUndef = false) {
2490 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2493 if (!isUndefOrEqual(Ops[0], 0))
2496 for (unsigned i = 1; i < NumOps; ++i) {
2497 SDValue Arg = Ops[i];
2498 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2499 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2500 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2507 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2508 bool V2IsUndef = false) {
2509 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2510 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2511 V2IsSplat, V2IsUndef);
2514 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2515 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2516 bool X86::isMOVSHDUPMask(SDNode *N) {
2517 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2519 if (N->getNumOperands() != 4)
2522 // Expect 1, 1, 3, 3
2523 for (unsigned i = 0; i < 2; ++i) {
2524 SDValue Arg = N->getOperand(i);
2525 if (Arg.getOpcode() == ISD::UNDEF) continue;
2526 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2527 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2528 if (Val != 1) return false;
2532 for (unsigned i = 2; i < 4; ++i) {
2533 SDValue Arg = N->getOperand(i);
2534 if (Arg.getOpcode() == ISD::UNDEF) continue;
2535 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2536 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2537 if (Val != 3) return false;
2541 // Don't use movshdup if it can be done with a shufps.
2545 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2546 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2547 bool X86::isMOVSLDUPMask(SDNode *N) {
2548 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2550 if (N->getNumOperands() != 4)
2553 // Expect 0, 0, 2, 2
2554 for (unsigned i = 0; i < 2; ++i) {
2555 SDValue Arg = N->getOperand(i);
2556 if (Arg.getOpcode() == ISD::UNDEF) continue;
2557 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2558 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2559 if (Val != 0) return false;
2563 for (unsigned i = 2; i < 4; ++i) {
2564 SDValue Arg = N->getOperand(i);
2565 if (Arg.getOpcode() == ISD::UNDEF) continue;
2566 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2567 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2568 if (Val != 2) return false;
2572 // Don't use movshdup if it can be done with a shufps.
2576 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2577 /// specifies a identity operation on the LHS or RHS.
2578 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2579 unsigned NumElems = N->getNumOperands();
2580 for (unsigned i = 0; i < NumElems; ++i)
2581 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2586 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2587 /// a splat of a single element.
2588 static bool isSplatMask(SDNode *N) {
2589 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2591 // This is a splat operation if each element of the permute is the same, and
2592 // if the value doesn't reference the second vector.
2593 unsigned NumElems = N->getNumOperands();
2594 SDValue ElementBase;
2596 for (; i != NumElems; ++i) {
2597 SDValue Elt = N->getOperand(i);
2598 if (isa<ConstantSDNode>(Elt)) {
2604 if (!ElementBase.getNode())
2607 for (; i != NumElems; ++i) {
2608 SDValue Arg = N->getOperand(i);
2609 if (Arg.getOpcode() == ISD::UNDEF) continue;
2610 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2611 if (Arg != ElementBase) return false;
2614 // Make sure it is a splat of the first vector operand.
2615 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems;
2618 /// getSplatMaskEltNo - Given a splat mask, return the index to the element
2619 /// we want to splat.
2620 static SDValue getSplatMaskEltNo(SDNode *N) {
2621 assert(isSplatMask(N) && "Not a splat mask");
2622 unsigned NumElems = N->getNumOperands();
2623 SDValue ElementBase;
2625 for (; i != NumElems; ++i) {
2626 SDValue Elt = N->getOperand(i);
2627 if (isa<ConstantSDNode>(Elt))
2630 assert(0 && " No splat value found!");
2635 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2636 /// a splat of a single element and it's a 2 or 4 element mask.
2637 bool X86::isSplatMask(SDNode *N) {
2638 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2640 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2641 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2643 return ::isSplatMask(N);
2646 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2647 /// specifies a splat of zero element.
2648 bool X86::isSplatLoMask(SDNode *N) {
2649 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2651 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2652 if (!isUndefOrEqual(N->getOperand(i), 0))
2657 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2658 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2659 bool X86::isMOVDDUPMask(SDNode *N) {
2660 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2662 unsigned e = N->getNumOperands() / 2;
2663 for (unsigned i = 0; i < e; ++i)
2664 if (!isUndefOrEqual(N->getOperand(i), i))
2666 for (unsigned i = 0; i < e; ++i)
2667 if (!isUndefOrEqual(N->getOperand(e+i), i))
2672 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2673 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2675 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2676 unsigned NumOperands = N->getNumOperands();
2677 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2679 for (unsigned i = 0; i < NumOperands; ++i) {
2681 SDValue Arg = N->getOperand(NumOperands-i-1);
2682 if (Arg.getOpcode() != ISD::UNDEF)
2683 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2684 if (Val >= NumOperands) Val -= NumOperands;
2686 if (i != NumOperands - 1)
2693 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2694 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2696 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2698 // 8 nodes, but we only care about the last 4.
2699 for (unsigned i = 7; i >= 4; --i) {
2701 SDValue Arg = N->getOperand(i);
2702 if (Arg.getOpcode() != ISD::UNDEF) {
2703 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2713 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2714 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2716 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2718 // 8 nodes, but we only care about the first 4.
2719 for (int i = 3; i >= 0; --i) {
2721 SDValue Arg = N->getOperand(i);
2722 if (Arg.getOpcode() != ISD::UNDEF)
2723 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2732 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2733 /// values in ther permute mask.
2734 static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
2735 SDValue &V2, SDValue &Mask,
2736 SelectionDAG &DAG) {
2737 MVT VT = Op.getValueType();
2738 MVT MaskVT = Mask.getValueType();
2739 MVT EltVT = MaskVT.getVectorElementType();
2740 unsigned NumElems = Mask.getNumOperands();
2741 SmallVector<SDValue, 8> MaskVec;
2742 DebugLoc dl = Op.getDebugLoc();
2744 for (unsigned i = 0; i != NumElems; ++i) {
2745 SDValue Arg = Mask.getOperand(i);
2746 if (Arg.getOpcode() == ISD::UNDEF) {
2747 MaskVec.push_back(DAG.getUNDEF(EltVT));
2750 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2751 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2753 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2755 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2759 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems);
2760 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask);
2763 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2764 /// the two vector operands have swapped position.
2766 SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG, DebugLoc dl) {
2767 MVT MaskVT = Mask.getValueType();
2768 MVT EltVT = MaskVT.getVectorElementType();
2769 unsigned NumElems = Mask.getNumOperands();
2770 SmallVector<SDValue, 8> MaskVec;
2771 for (unsigned i = 0; i != NumElems; ++i) {
2772 SDValue Arg = Mask.getOperand(i);
2773 if (Arg.getOpcode() == ISD::UNDEF) {
2774 MaskVec.push_back(DAG.getUNDEF(EltVT));
2777 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2778 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2780 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2782 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2784 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems);
2788 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2789 /// match movhlps. The lower half elements should come from upper half of
2790 /// V1 (and in order), and the upper half elements should come from the upper
2791 /// half of V2 (and in order).
2792 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2793 unsigned NumElems = Mask->getNumOperands();
2796 for (unsigned i = 0, e = 2; i != e; ++i)
2797 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2799 for (unsigned i = 2; i != 4; ++i)
2800 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2805 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2806 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2808 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2809 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2811 N = N->getOperand(0).getNode();
2812 if (!ISD::isNON_EXTLoad(N))
2815 *LD = cast<LoadSDNode>(N);
2819 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2820 /// match movlp{s|d}. The lower half elements should come from lower half of
2821 /// V1 (and in order), and the upper half elements should come from the upper
2822 /// half of V2 (and in order). And since V1 will become the source of the
2823 /// MOVLP, it must be either a vector load or a scalar load to vector.
2824 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2825 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2827 // Is V2 is a vector load, don't do this transformation. We will try to use
2828 // load folding shufps op.
2829 if (ISD::isNON_EXTLoad(V2))
2832 unsigned NumElems = Mask->getNumOperands();
2833 if (NumElems != 2 && NumElems != 4)
2835 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2836 if (!isUndefOrEqual(Mask->getOperand(i), i))
2838 for (unsigned i = NumElems/2; i != NumElems; ++i)
2839 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2844 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2846 static bool isSplatVector(SDNode *N) {
2847 if (N->getOpcode() != ISD::BUILD_VECTOR)
2850 SDValue SplatValue = N->getOperand(0);
2851 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2852 if (N->getOperand(i) != SplatValue)
2857 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2859 static bool isUndefShuffle(SDNode *N) {
2860 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2863 SDValue V1 = N->getOperand(0);
2864 SDValue V2 = N->getOperand(1);
2865 SDValue Mask = N->getOperand(2);
2866 unsigned NumElems = Mask.getNumOperands();
2867 for (unsigned i = 0; i != NumElems; ++i) {
2868 SDValue Arg = Mask.getOperand(i);
2869 if (Arg.getOpcode() != ISD::UNDEF) {
2870 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2871 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2873 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2880 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2882 static inline bool isZeroNode(SDValue Elt) {
2883 return ((isa<ConstantSDNode>(Elt) &&
2884 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2885 (isa<ConstantFPSDNode>(Elt) &&
2886 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2889 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2890 /// to an zero vector.
2891 static bool isZeroShuffle(SDNode *N) {
2892 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2895 SDValue V1 = N->getOperand(0);
2896 SDValue V2 = N->getOperand(1);
2897 SDValue Mask = N->getOperand(2);
2898 unsigned NumElems = Mask.getNumOperands();
2899 for (unsigned i = 0; i != NumElems; ++i) {
2900 SDValue Arg = Mask.getOperand(i);
2901 if (Arg.getOpcode() == ISD::UNDEF)
2904 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2905 if (Idx < NumElems) {
2906 unsigned Opc = V1.getNode()->getOpcode();
2907 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2909 if (Opc != ISD::BUILD_VECTOR ||
2910 !isZeroNode(V1.getNode()->getOperand(Idx)))
2912 } else if (Idx >= NumElems) {
2913 unsigned Opc = V2.getNode()->getOpcode();
2914 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2916 if (Opc != ISD::BUILD_VECTOR ||
2917 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
2924 /// getZeroVector - Returns a vector of specified type with all zero elements.
2926 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG,
2928 assert(VT.isVector() && "Expected a vector type");
2930 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2931 // type. This ensures they get CSE'd.
2933 if (VT.getSizeInBits() == 64) { // MMX
2934 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2935 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2936 } else if (HasSSE2) { // SSE2
2937 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2938 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2940 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2941 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
2943 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2946 /// getOnesVector - Returns a vector of specified type with all bits set.
2948 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
2949 assert(VT.isVector() && "Expected a vector type");
2951 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2952 // type. This ensures they get CSE'd.
2953 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2955 if (VT.getSizeInBits() == 64) // MMX
2956 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2958 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2959 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2963 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2964 /// that point to V2 points to its first element.
2965 static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
2966 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2968 bool Changed = false;
2969 SmallVector<SDValue, 8> MaskVec;
2970 unsigned NumElems = Mask.getNumOperands();
2971 for (unsigned i = 0; i != NumElems; ++i) {
2972 SDValue Arg = Mask.getOperand(i);
2973 if (Arg.getOpcode() != ISD::UNDEF) {
2974 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2975 if (Val > NumElems) {
2976 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2980 MaskVec.push_back(Arg);
2984 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(),
2985 Mask.getValueType(),
2986 &MaskVec[0], MaskVec.size());
2990 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2991 /// operation of specified width.
2992 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl) {
2993 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2994 MVT BaseVT = MaskVT.getVectorElementType();
2996 SmallVector<SDValue, 8> MaskVec;
2997 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2998 for (unsigned i = 1; i != NumElems; ++i)
2999 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3000 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3001 &MaskVec[0], MaskVec.size());
3004 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
3005 /// of specified width.
3006 static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG,
3008 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3009 MVT BaseVT = MaskVT.getVectorElementType();
3010 SmallVector<SDValue, 8> MaskVec;
3011 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3012 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3013 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
3015 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3016 &MaskVec[0], MaskVec.size());
3019 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
3020 /// of specified width.
3021 static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG,
3023 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3024 MVT BaseVT = MaskVT.getVectorElementType();
3025 unsigned Half = NumElems/2;
3026 SmallVector<SDValue, 8> MaskVec;
3027 for (unsigned i = 0; i != Half; ++i) {
3028 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
3029 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
3031 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3032 &MaskVec[0], MaskVec.size());
3035 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
3036 /// element #0 of a vector with the specified index, leaving the rest of the
3037 /// elements in place.
3038 static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
3039 SelectionDAG &DAG, DebugLoc dl) {
3040 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3041 MVT BaseVT = MaskVT.getVectorElementType();
3042 SmallVector<SDValue, 8> MaskVec;
3043 // Element #0 of the result gets the elt we are replacing.
3044 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
3045 for (unsigned i = 1; i != NumElems; ++i)
3046 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
3047 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3048 &MaskVec[0], MaskVec.size());
3051 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3052 static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
3053 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
3054 MVT VT = Op.getValueType();
3057 SDValue V1 = Op.getOperand(0);
3058 SDValue Mask = Op.getOperand(2);
3059 unsigned MaskNumElems = Mask.getNumOperands();
3060 unsigned NumElems = MaskNumElems;
3061 DebugLoc dl = Op.getDebugLoc();
3062 // Special handling of v4f32 -> v4i32.
3063 if (VT != MVT::v4f32) {
3064 // Find which element we want to splat.
3065 SDNode* EltNoNode = getSplatMaskEltNo(Mask.getNode()).getNode();
3066 unsigned EltNo = cast<ConstantSDNode>(EltNoNode)->getZExtValue();
3067 // unpack elements to the correct location
3068 while (NumElems > 4) {
3069 if (EltNo < NumElems/2) {
3070 Mask = getUnpacklMask(MaskNumElems, DAG, dl);
3072 Mask = getUnpackhMask(MaskNumElems, DAG, dl);
3073 EltNo -= NumElems/2;
3075 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1, Mask);
3078 SDValue Cst = DAG.getConstant(EltNo, MVT::i32);
3079 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3082 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3083 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1,
3084 DAG.getUNDEF(PVT), Mask);
3085 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle);
3088 /// isVectorLoad - Returns true if the node is a vector load, a scalar
3089 /// load that's promoted to vector, or a load bitcasted.
3090 static bool isVectorLoad(SDValue Op) {
3091 assert(Op.getValueType().isVector() && "Expected a vector type");
3092 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR ||
3093 Op.getOpcode() == ISD::BIT_CONVERT) {
3094 return isa<LoadSDNode>(Op.getOperand(0));
3096 return isa<LoadSDNode>(Op);
3100 /// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
3102 static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask,
3103 SelectionDAG &DAG, bool HasSSE3) {
3104 // If we have sse3 and shuffle has more than one use or input is a load, then
3105 // use movddup. Otherwise, use movlhps.
3106 bool UseMovddup = HasSSE3 && (!Op.hasOneUse() || isVectorLoad(V1));
3107 MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32;
3108 MVT VT = Op.getValueType();
3111 DebugLoc dl = Op.getDebugLoc();
3112 unsigned NumElems = PVT.getVectorNumElements();
3113 if (NumElems == 2) {
3114 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3115 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3117 assert(NumElems == 4);
3118 SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32);
3119 SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32);
3120 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
3121 Cst0, Cst1, Cst0, Cst1);
3124 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3125 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1,
3126 DAG.getUNDEF(PVT), Mask);
3127 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle);
3130 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3131 /// vector of zero or undef vector. This produces a shuffle where the low
3132 /// element of V2 is swizzled into the zero/undef vector, landing at element
3133 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3134 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3135 bool isZero, bool HasSSE2,
3136 SelectionDAG &DAG) {
3137 DebugLoc dl = V2.getDebugLoc();
3138 MVT VT = V2.getValueType();
3140 ? getZeroVector(VT, HasSSE2, DAG, dl) : DAG.getUNDEF(VT);
3141 unsigned NumElems = V2.getValueType().getVectorNumElements();
3142 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3143 MVT EVT = MaskVT.getVectorElementType();
3144 SmallVector<SDValue, 16> MaskVec;
3145 for (unsigned i = 0; i != NumElems; ++i)
3146 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
3147 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
3149 MaskVec.push_back(DAG.getConstant(i, EVT));
3150 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3151 &MaskVec[0], MaskVec.size());
3152 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask);
3155 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3156 /// a shuffle that is zero.
3158 unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
3159 unsigned NumElems, bool Low,
3160 SelectionDAG &DAG) {
3161 unsigned NumZeros = 0;
3162 for (unsigned i = 0; i < NumElems; ++i) {
3163 unsigned Index = Low ? i : NumElems-i-1;
3164 SDValue Idx = Mask.getOperand(Index);
3165 if (Idx.getOpcode() == ISD::UNDEF) {
3169 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
3170 if (Elt.getNode() && isZeroNode(Elt))
3178 /// isVectorShift - Returns true if the shuffle can be implemented as a
3179 /// logical left or right shift of a vector.
3180 static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
3181 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3182 unsigned NumElems = Mask.getNumOperands();
3185 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
3188 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
3193 bool SeenV1 = false;
3194 bool SeenV2 = false;
3195 for (unsigned i = NumZeros; i < NumElems; ++i) {
3196 unsigned Val = isLeft ? (i - NumZeros) : i;
3197 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
3198 if (Idx.getOpcode() == ISD::UNDEF)
3200 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
3201 if (Index < NumElems)
3210 if (SeenV1 && SeenV2)
3213 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
3219 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3221 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3222 unsigned NumNonZero, unsigned NumZero,
3223 SelectionDAG &DAG, TargetLowering &TLI) {
3227 DebugLoc dl = Op.getDebugLoc();
3230 for (unsigned i = 0; i < 16; ++i) {
3231 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3232 if (ThisIsNonZero && First) {
3234 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3236 V = DAG.getUNDEF(MVT::v8i16);
3241 SDValue ThisElt(0, 0), LastElt(0, 0);
3242 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3243 if (LastIsNonZero) {
3244 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3245 MVT::i16, Op.getOperand(i-1));
3247 if (ThisIsNonZero) {
3248 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3249 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3250 ThisElt, DAG.getConstant(8, MVT::i8));
3252 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3256 if (ThisElt.getNode())
3257 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3258 DAG.getIntPtrConstant(i/2));
3262 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3265 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3267 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3268 unsigned NumNonZero, unsigned NumZero,
3269 SelectionDAG &DAG, TargetLowering &TLI) {
3273 DebugLoc dl = Op.getDebugLoc();
3276 for (unsigned i = 0; i < 8; ++i) {
3277 bool isNonZero = (NonZeros & (1 << i)) != 0;
3281 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3283 V = DAG.getUNDEF(MVT::v8i16);
3286 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3287 MVT::v8i16, V, Op.getOperand(i),
3288 DAG.getIntPtrConstant(i));
3295 /// getVShift - Return a vector logical shift node.
3297 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3298 unsigned NumBits, SelectionDAG &DAG,
3299 const TargetLowering &TLI, DebugLoc dl) {
3300 bool isMMX = VT.getSizeInBits() == 64;
3301 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3302 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3303 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3304 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3305 DAG.getNode(Opc, dl, ShVT, SrcOp,
3306 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3310 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3311 DebugLoc dl = Op.getDebugLoc();
3312 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3313 if (ISD::isBuildVectorAllZeros(Op.getNode())
3314 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3315 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3316 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3317 // eliminated on x86-32 hosts.
3318 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3321 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3322 return getOnesVector(Op.getValueType(), DAG, dl);
3323 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3326 MVT VT = Op.getValueType();
3327 MVT EVT = VT.getVectorElementType();
3328 unsigned EVTBits = EVT.getSizeInBits();
3330 unsigned NumElems = Op.getNumOperands();
3331 unsigned NumZero = 0;
3332 unsigned NumNonZero = 0;
3333 unsigned NonZeros = 0;
3334 bool IsAllConstants = true;
3335 SmallSet<SDValue, 8> Values;
3336 for (unsigned i = 0; i < NumElems; ++i) {
3337 SDValue Elt = Op.getOperand(i);
3338 if (Elt.getOpcode() == ISD::UNDEF)
3341 if (Elt.getOpcode() != ISD::Constant &&
3342 Elt.getOpcode() != ISD::ConstantFP)
3343 IsAllConstants = false;
3344 if (isZeroNode(Elt))
3347 NonZeros |= (1 << i);
3352 if (NumNonZero == 0) {
3353 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3354 return DAG.getUNDEF(VT);
3357 // Special case for single non-zero, non-undef, element.
3358 if (NumNonZero == 1 && NumElems <= 4) {
3359 unsigned Idx = CountTrailingZeros_32(NonZeros);
3360 SDValue Item = Op.getOperand(Idx);
3362 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3363 // the value are obviously zero, truncate the value to i32 and do the
3364 // insertion that way. Only do this if the value is non-constant or if the
3365 // value is a constant being inserted into element 0. It is cheaper to do
3366 // a constant pool load than it is to do a movd + shuffle.
3367 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3368 (!IsAllConstants || Idx == 0)) {
3369 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3370 // Handle MMX and SSE both.
3371 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3372 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3374 // Truncate the value (which may itself be a constant) to i32, and
3375 // convert it to a vector with movd (S2V+shuffle to zero extend).
3376 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3377 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3378 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3379 Subtarget->hasSSE2(), DAG);
3381 // Now we have our 32-bit value zero extended in the low element of
3382 // a vector. If Idx != 0, swizzle it into place.
3385 Item, DAG.getUNDEF(Item.getValueType()),
3386 getSwapEltZeroMask(VecElts, Idx, DAG, dl)
3388 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VecVT, Ops, 3);
3390 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3394 // If we have a constant or non-constant insertion into the low element of
3395 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3396 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3397 // depending on what the source datatype is. Because we can only get here
3398 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3400 // Don't do this for i64 values on x86-32.
3401 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3402 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3403 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3404 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3405 Subtarget->hasSSE2(), DAG);
3408 // Is it a vector logical left shift?
3409 if (NumElems == 2 && Idx == 1 &&
3410 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3411 unsigned NumBits = VT.getSizeInBits();
3412 return getVShift(true, VT,
3413 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3414 VT, Op.getOperand(1)),
3415 NumBits/2, DAG, *this, dl);
3418 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3421 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3422 // is a non-constant being inserted into an element other than the low one,
3423 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3424 // movd/movss) to move this into the low element, then shuffle it into
3426 if (EVTBits == 32) {
3427 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3429 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3430 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3431 Subtarget->hasSSE2(), DAG);
3432 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3433 MVT MaskEVT = MaskVT.getVectorElementType();
3434 SmallVector<SDValue, 8> MaskVec;
3435 for (unsigned i = 0; i < NumElems; i++)
3436 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3437 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3438 &MaskVec[0], MaskVec.size());
3439 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, Item,
3440 DAG.getUNDEF(VT), Mask);
3444 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3445 if (Values.size() == 1)
3448 // A vector full of immediates; various special cases are already
3449 // handled, so this is best done with a single constant-pool load.
3453 // Let legalizer expand 2-wide build_vectors.
3454 if (EVTBits == 64) {
3455 if (NumNonZero == 1) {
3456 // One half is zero or undef.
3457 unsigned Idx = CountTrailingZeros_32(NonZeros);
3458 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3459 Op.getOperand(Idx));
3460 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3461 Subtarget->hasSSE2(), DAG);
3466 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3467 if (EVTBits == 8 && NumElems == 16) {
3468 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3470 if (V.getNode()) return V;
3473 if (EVTBits == 16 && NumElems == 8) {
3474 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3476 if (V.getNode()) return V;
3479 // If element VT is == 32 bits, turn it into a number of shuffles.
3480 SmallVector<SDValue, 8> V;
3482 if (NumElems == 4 && NumZero > 0) {
3483 for (unsigned i = 0; i < 4; ++i) {
3484 bool isZero = !(NonZeros & (1 << i));
3486 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3488 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3491 for (unsigned i = 0; i < 2; ++i) {
3492 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3495 V[i] = V[i*2]; // Must be a zero vector.
3498 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2+1], V[i*2],
3499 getMOVLMask(NumElems, DAG, dl));
3502 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1],
3503 getMOVLMask(NumElems, DAG, dl));
3506 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1],
3507 getUnpacklMask(NumElems, DAG, dl));
3512 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3513 MVT EVT = MaskVT.getVectorElementType();
3514 SmallVector<SDValue, 8> MaskVec;
3515 bool Reverse = (NonZeros & 0x3) == 2;
3516 for (unsigned i = 0; i < 2; ++i)
3518 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3520 MaskVec.push_back(DAG.getConstant(i, EVT));
3521 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3522 for (unsigned i = 0; i < 2; ++i)
3524 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3526 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3527 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3528 &MaskVec[0], MaskVec.size());
3529 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[0], V[1], ShufMask);
3532 if (Values.size() > 2) {
3533 // Expand into a number of unpckl*.
3535 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3536 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3537 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3538 SDValue UnpckMask = getUnpacklMask(NumElems, DAG, dl);
3539 for (unsigned i = 0; i < NumElems; ++i)
3540 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3542 while (NumElems != 0) {
3543 for (unsigned i = 0; i < NumElems; ++i)
3544 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i], V[i + NumElems],
3554 // v8i16 shuffles - Prefer shuffles in the following order:
3555 // 1. [all] pshuflw, pshufhw, optional move
3556 // 2. [ssse3] 1 x pshufb
3557 // 3. [ssse3] 2 x pshufb + 1 x por
3558 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3560 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
3561 SDValue PermMask, SelectionDAG &DAG,
3562 X86TargetLowering &TLI, DebugLoc dl) {
3563 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
3564 PermMask.getNode()->op_end());
3565 SmallVector<int, 8> MaskVals;
3567 // Determine if more than 1 of the words in each of the low and high quadwords
3568 // of the result come from the same quadword of one of the two inputs. Undef
3569 // mask values count as coming from any quadword, for better codegen.
3570 SmallVector<unsigned, 4> LoQuad(4);
3571 SmallVector<unsigned, 4> HiQuad(4);
3572 BitVector InputQuads(4);
3573 for (unsigned i = 0; i < 8; ++i) {
3574 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3575 SDValue Elt = MaskElts[i];
3576 int EltIdx = Elt.getOpcode() == ISD::UNDEF ? -1 :
3577 cast<ConstantSDNode>(Elt)->getZExtValue();
3578 MaskVals.push_back(EltIdx);
3587 InputQuads.set(EltIdx / 4);
3590 int BestLoQuad = -1;
3591 unsigned MaxQuad = 1;
3592 for (unsigned i = 0; i < 4; ++i) {
3593 if (LoQuad[i] > MaxQuad) {
3595 MaxQuad = LoQuad[i];
3599 int BestHiQuad = -1;
3601 for (unsigned i = 0; i < 4; ++i) {
3602 if (HiQuad[i] > MaxQuad) {
3604 MaxQuad = HiQuad[i];
3608 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3609 // of the two input vectors, shuffle them into one input vector so only a
3610 // single pshufb instruction is necessary. If There are more than 2 input
3611 // quads, disable the next transformation since it does not help SSSE3.
3612 bool V1Used = InputQuads[0] || InputQuads[1];
3613 bool V2Used = InputQuads[2] || InputQuads[3];
3614 if (TLI.getSubtarget()->hasSSSE3()) {
3615 if (InputQuads.count() == 2 && V1Used && V2Used) {
3616 BestLoQuad = InputQuads.find_first();
3617 BestHiQuad = InputQuads.find_next(BestLoQuad);
3619 if (InputQuads.count() > 2) {
3625 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3626 // the shuffle mask. If a quad is scored as -1, that means that it contains
3627 // words from all 4 input quadwords.
3629 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3630 SmallVector<SDValue,8> MaskV;
3631 MaskV.push_back(DAG.getConstant(BestLoQuad < 0 ? 0 : BestLoQuad, MVT::i64));
3632 MaskV.push_back(DAG.getConstant(BestHiQuad < 0 ? 1 : BestHiQuad, MVT::i64));
3633 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, &MaskV[0], 2);
3635 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64,
3636 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3637 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), Mask);
3638 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3640 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3641 // source words for the shuffle, to aid later transformations.
3642 bool AllWordsInNewV = true;
3643 bool InOrder[2] = { true, true };
3644 for (unsigned i = 0; i != 8; ++i) {
3645 int idx = MaskVals[i];
3647 InOrder[i/4] = false;
3648 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3650 AllWordsInNewV = false;
3654 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3655 if (AllWordsInNewV) {
3656 for (int i = 0; i != 8; ++i) {
3657 int idx = MaskVals[i];
3660 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3661 if ((idx != i) && idx < 4)
3663 if ((idx != i) && idx > 3)
3672 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3673 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3674 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3676 for (unsigned i = 0; i != 8; ++i)
3677 MaskV.push_back((MaskVals[i] < 0) ? DAG.getUNDEF(MVT::i16)
3678 : DAG.getConstant(MaskVals[i],
3680 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV,
3681 DAG.getUNDEF(MVT::v8i16),
3682 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16,
3687 // If we have SSSE3, and all words of the result are from 1 input vector,
3688 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3689 // is present, fall back to case 4.
3690 if (TLI.getSubtarget()->hasSSSE3()) {
3691 SmallVector<SDValue,16> pshufbMask;
3693 // If we have elements from both input vectors, set the high bit of the
3694 // shuffle mask element to zero out elements that come from V2 in the V1
3695 // mask, and elements that come from V1 in the V2 mask, so that the two
3696 // results can be OR'd together.
3697 bool TwoInputs = V1Used && V2Used;
3698 for (unsigned i = 0; i != 8; ++i) {
3699 int EltIdx = MaskVals[i] * 2;
3700 if (TwoInputs && (EltIdx >= 16)) {
3701 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3702 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3705 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3706 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3708 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3709 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3710 DAG.getNode(ISD::BUILD_VECTOR, dl,
3711 MVT::v16i8, &pshufbMask[0], 16));
3713 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3715 // Calculate the shuffle mask for the second input, shuffle it, and
3716 // OR it with the first shuffled input.
3718 for (unsigned i = 0; i != 8; ++i) {
3719 int EltIdx = MaskVals[i] * 2;
3721 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3722 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3725 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3726 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3728 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3729 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3730 DAG.getNode(ISD::BUILD_VECTOR, dl,
3731 MVT::v16i8, &pshufbMask[0], 16));
3732 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3733 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3736 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3737 // and update MaskVals with new element order.
3738 BitVector InOrder(8);
3739 if (BestLoQuad >= 0) {
3740 SmallVector<SDValue, 8> MaskV;
3741 for (int i = 0; i != 4; ++i) {
3742 int idx = MaskVals[i];
3744 MaskV.push_back(DAG.getUNDEF(MVT::i16));
3746 } else if ((idx / 4) == BestLoQuad) {
3747 MaskV.push_back(DAG.getConstant(idx & 3, MVT::i16));
3750 MaskV.push_back(DAG.getUNDEF(MVT::i16));
3753 for (unsigned i = 4; i != 8; ++i)
3754 MaskV.push_back(DAG.getConstant(i, MVT::i16));
3755 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV,
3756 DAG.getUNDEF(MVT::v8i16),
3757 DAG.getNode(ISD::BUILD_VECTOR, dl,
3758 MVT::v8i16, &MaskV[0], 8));
3761 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3762 // and update MaskVals with the new element order.
3763 if (BestHiQuad >= 0) {
3764 SmallVector<SDValue, 8> MaskV;
3765 for (unsigned i = 0; i != 4; ++i)
3766 MaskV.push_back(DAG.getConstant(i, MVT::i16));
3767 for (unsigned i = 4; i != 8; ++i) {
3768 int idx = MaskVals[i];
3770 MaskV.push_back(DAG.getUNDEF(MVT::i16));
3772 } else if ((idx / 4) == BestHiQuad) {
3773 MaskV.push_back(DAG.getConstant((idx & 3) + 4, MVT::i16));
3776 MaskV.push_back(DAG.getUNDEF(MVT::i16));
3779 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV,
3780 DAG.getUNDEF(MVT::v8i16),
3781 DAG.getNode(ISD::BUILD_VECTOR, dl,
3782 MVT::v8i16, &MaskV[0], 8));
3785 // In case BestHi & BestLo were both -1, which means each quadword has a word
3786 // from each of the four input quadwords, calculate the InOrder bitvector now
3787 // before falling through to the insert/extract cleanup.
3788 if (BestLoQuad == -1 && BestHiQuad == -1) {
3790 for (int i = 0; i != 8; ++i)
3791 if (MaskVals[i] < 0 || MaskVals[i] == i)
3795 // The other elements are put in the right place using pextrw and pinsrw.
3796 for (unsigned i = 0; i != 8; ++i) {
3799 int EltIdx = MaskVals[i];
3802 SDValue ExtOp = (EltIdx < 8)
3803 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3804 DAG.getIntPtrConstant(EltIdx))
3805 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3806 DAG.getIntPtrConstant(EltIdx - 8));
3807 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3808 DAG.getIntPtrConstant(i));
3813 // v16i8 shuffles - Prefer shuffles in the following order:
3814 // 1. [ssse3] 1 x pshufb
3815 // 2. [ssse3] 2 x pshufb + 1 x por
3816 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3818 SDValue LowerVECTOR_SHUFFLEv16i8(SDValue V1, SDValue V2,
3819 SDValue PermMask, SelectionDAG &DAG,
3820 X86TargetLowering &TLI, DebugLoc dl) {
3821 SmallVector<SDValue, 16> MaskElts(PermMask.getNode()->op_begin(),
3822 PermMask.getNode()->op_end());
3823 SmallVector<int, 16> MaskVals;
3825 // If we have SSSE3, case 1 is generated when all result bytes come from
3826 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3827 // present, fall back to case 3.
3828 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3831 for (unsigned i = 0; i < 16; ++i) {
3832 SDValue Elt = MaskElts[i];
3833 int EltIdx = Elt.getOpcode() == ISD::UNDEF ? -1 :
3834 cast<ConstantSDNode>(Elt)->getZExtValue();
3835 MaskVals.push_back(EltIdx);
3844 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3845 if (TLI.getSubtarget()->hasSSSE3()) {
3846 SmallVector<SDValue,16> pshufbMask;
3848 // If all result elements are from one input vector, then only translate
3849 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3851 // Otherwise, we have elements from both input vectors, and must zero out
3852 // elements that come from V2 in the first mask, and V1 in the second mask
3853 // so that we can OR them together.
3854 bool TwoInputs = !(V1Only || V2Only);
3855 for (unsigned i = 0; i != 16; ++i) {
3856 int EltIdx = MaskVals[i];
3857 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3858 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3861 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3863 // If all the elements are from V2, assign it to V1 and return after
3864 // building the first pshufb.
3867 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3868 DAG.getNode(ISD::BUILD_VECTOR, dl,
3869 MVT::v16i8, &pshufbMask[0], 16));
3873 // Calculate the shuffle mask for the second input, shuffle it, and
3874 // OR it with the first shuffled input.
3876 for (unsigned i = 0; i != 16; ++i) {
3877 int EltIdx = MaskVals[i];
3879 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3882 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3884 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3885 DAG.getNode(ISD::BUILD_VECTOR, dl,
3886 MVT::v16i8, &pshufbMask[0], 16));
3887 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3890 // No SSSE3 - Calculate in place words and then fix all out of place words
3891 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
3892 // the 16 different words that comprise the two doublequadword input vectors.
3893 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3894 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
3895 SDValue NewV = V2Only ? V2 : V1;
3896 for (int i = 0; i != 8; ++i) {
3897 int Elt0 = MaskVals[i*2];
3898 int Elt1 = MaskVals[i*2+1];
3900 // This word of the result is all undef, skip it.
3901 if (Elt0 < 0 && Elt1 < 0)
3904 // This word of the result is already in the correct place, skip it.
3905 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
3907 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
3910 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
3911 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
3914 // If Elt0 and Elt1 are defined, are consecutive, and can be load
3915 // using a single extract together, load it and store it.
3916 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
3917 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3918 DAG.getIntPtrConstant(Elt1 / 2));
3919 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3920 DAG.getIntPtrConstant(i));
3924 // If Elt1 is defined, extract it from the appropriate source. If the
3925 // source byte is not also odd, shift the extracted word left 8 bits
3926 // otherwise clear the bottom 8 bits if we need to do an or.
3928 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3929 DAG.getIntPtrConstant(Elt1 / 2));
3930 if ((Elt1 & 1) == 0)
3931 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
3932 DAG.getConstant(8, TLI.getShiftAmountTy()));
3934 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
3935 DAG.getConstant(0xFF00, MVT::i16));
3937 // If Elt0 is defined, extract it from the appropriate source. If the
3938 // source byte is not also even, shift the extracted word right 8 bits. If
3939 // Elt1 was also defined, OR the extracted values together before
3940 // inserting them in the result.
3942 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
3943 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
3944 if ((Elt0 & 1) != 0)
3945 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
3946 DAG.getConstant(8, TLI.getShiftAmountTy()));
3948 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
3949 DAG.getConstant(0x00FF, MVT::i16));
3950 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
3953 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3954 DAG.getIntPtrConstant(i));
3956 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
3959 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3960 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3961 /// done when every pair / quad of shuffle mask elements point to elements in
3962 /// the right sequence. e.g.
3963 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3965 SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
3967 SDValue PermMask, SelectionDAG &DAG,
3968 TargetLowering &TLI, DebugLoc dl) {
3969 unsigned NumElems = PermMask.getNumOperands();
3970 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3971 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3972 MVT MaskEltVT = MaskVT.getVectorElementType();
3974 switch (VT.getSimpleVT()) {
3975 default: assert(false && "Unexpected!");
3976 case MVT::v4f32: NewVT = MVT::v2f64; break;
3977 case MVT::v4i32: NewVT = MVT::v2i64; break;
3978 case MVT::v8i16: NewVT = MVT::v4i32; break;
3979 case MVT::v16i8: NewVT = MVT::v4i32; break;
3982 if (NewWidth == 2) {
3988 unsigned Scale = NumElems / NewWidth;
3989 SmallVector<SDValue, 8> MaskVec;
3990 for (unsigned i = 0; i < NumElems; i += Scale) {
3991 unsigned StartIdx = ~0U;
3992 for (unsigned j = 0; j < Scale; ++j) {
3993 SDValue Elt = PermMask.getOperand(i+j);
3994 if (Elt.getOpcode() == ISD::UNDEF)
3996 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3997 if (StartIdx == ~0U)
3998 StartIdx = EltIdx - (EltIdx % Scale);
3999 if (EltIdx != StartIdx + j)
4002 if (StartIdx == ~0U)
4003 MaskVec.push_back(DAG.getUNDEF(MaskEltVT));
4005 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
4008 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4009 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4010 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, V1, V2,
4011 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4012 &MaskVec[0], MaskVec.size()));
4015 /// getVZextMovL - Return a zero-extending vector move low node.
4017 static SDValue getVZextMovL(MVT VT, MVT OpVT,
4018 SDValue SrcOp, SelectionDAG &DAG,
4019 const X86Subtarget *Subtarget, DebugLoc dl) {
4020 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4021 LoadSDNode *LD = NULL;
4022 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4023 LD = dyn_cast<LoadSDNode>(SrcOp);
4025 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4027 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4028 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
4029 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4030 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4031 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
4033 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4034 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4035 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4036 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4044 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4045 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4046 DAG.getNode(ISD::BIT_CONVERT, dl,
4050 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4053 LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
4054 SDValue PermMask, MVT VT, SelectionDAG &DAG,
4056 MVT MaskVT = PermMask.getValueType();
4057 MVT MaskEVT = MaskVT.getVectorElementType();
4058 SmallVector<std::pair<int, int>, 8> Locs;
4060 SmallVector<SDValue, 8> Mask1(4, DAG.getUNDEF(MaskEVT));
4063 for (unsigned i = 0; i != 4; ++i) {
4064 SDValue Elt = PermMask.getOperand(i);
4065 if (Elt.getOpcode() == ISD::UNDEF) {
4066 Locs[i] = std::make_pair(-1, -1);
4068 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
4069 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
4071 Locs[i] = std::make_pair(0, NumLo);
4075 Locs[i] = std::make_pair(1, NumHi);
4077 Mask1[2+NumHi] = Elt;
4083 if (NumLo <= 2 && NumHi <= 2) {
4084 // If no more than two elements come from either vector. This can be
4085 // implemented with two shuffles. First shuffle gather the elements.
4086 // The second shuffle, which takes the first shuffle as both of its
4087 // vector operands, put the elements into the right order.
4088 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
4089 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4090 &Mask1[0], Mask1.size()));
4092 SmallVector<SDValue, 8> Mask2(4, DAG.getUNDEF(MaskEVT));
4093 for (unsigned i = 0; i != 4; ++i) {
4094 if (Locs[i].first == -1)
4097 unsigned Idx = (i < 2) ? 0 : 4;
4098 Idx += Locs[i].first * 2 + Locs[i].second;
4099 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
4103 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1,
4104 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4105 &Mask2[0], Mask2.size()));
4106 } else if (NumLo == 3 || NumHi == 3) {
4107 // Otherwise, we must have three elements from one vector, call it X, and
4108 // one element from the other, call it Y. First, use a shufps to build an
4109 // intermediate vector with the one element from Y and the element from X
4110 // that will be in the same half in the final destination (the indexes don't
4111 // matter). Then, use a shufps to build the final vector, taking the half
4112 // containing the element from Y from the intermediate, and the other half
4115 // Normalize it so the 3 elements come from V1.
4116 PermMask = CommuteVectorShuffleMask(PermMask, DAG, dl);
4120 // Find the element from V2.
4122 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4123 SDValue Elt = PermMask.getOperand(HiIndex);
4124 if (Elt.getOpcode() == ISD::UNDEF)
4126 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
4131 Mask1[0] = PermMask.getOperand(HiIndex);
4132 Mask1[1] = DAG.getUNDEF(MaskEVT);
4133 Mask1[2] = PermMask.getOperand(HiIndex^1);
4134 Mask1[3] = DAG.getUNDEF(MaskEVT);
4135 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
4136 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &Mask1[0], 4));
4139 Mask1[0] = PermMask.getOperand(0);
4140 Mask1[1] = PermMask.getOperand(1);
4141 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
4142 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
4143 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
4144 DAG.getNode(ISD::BUILD_VECTOR, dl,
4145 MaskVT, &Mask1[0], 4));
4147 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
4148 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
4149 Mask1[2] = PermMask.getOperand(2);
4150 Mask1[3] = PermMask.getOperand(3);
4151 if (Mask1[2].getOpcode() != ISD::UNDEF)
4153 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4,
4155 if (Mask1[3].getOpcode() != ISD::UNDEF)
4157 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
4159 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V2, V1,
4160 DAG.getNode(ISD::BUILD_VECTOR, dl,
4161 MaskVT, &Mask1[0], 4));
4165 // Break it into (shuffle shuffle_hi, shuffle_lo).
4167 SmallVector<SDValue,8> LoMask(4, DAG.getUNDEF(MaskEVT));
4168 SmallVector<SDValue,8> HiMask(4, DAG.getUNDEF(MaskEVT));
4169 SmallVector<SDValue,8> *MaskPtr = &LoMask;
4170 unsigned MaskIdx = 0;
4173 for (unsigned i = 0; i != 4; ++i) {
4180 SDValue Elt = PermMask.getOperand(i);
4181 if (Elt.getOpcode() == ISD::UNDEF) {
4182 Locs[i] = std::make_pair(-1, -1);
4183 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) {
4184 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4185 (*MaskPtr)[LoIdx] = Elt;
4188 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4189 (*MaskPtr)[HiIdx] = Elt;
4194 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
4195 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4196 &LoMask[0], LoMask.size()));
4197 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
4198 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4199 &HiMask[0], HiMask.size()));
4200 SmallVector<SDValue, 8> MaskOps;
4201 for (unsigned i = 0; i != 4; ++i) {
4202 if (Locs[i].first == -1) {
4203 MaskOps.push_back(DAG.getUNDEF(MaskEVT));
4205 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4206 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
4209 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, LoShuffle, HiShuffle,
4210 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4211 &MaskOps[0], MaskOps.size()));
4215 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4216 SDValue V1 = Op.getOperand(0);
4217 SDValue V2 = Op.getOperand(1);
4218 SDValue PermMask = Op.getOperand(2);
4219 MVT VT = Op.getValueType();
4220 DebugLoc dl = Op.getDebugLoc();
4221 unsigned NumElems = PermMask.getNumOperands();
4222 bool isMMX = VT.getSizeInBits() == 64;
4223 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4224 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4225 bool V1IsSplat = false;
4226 bool V2IsSplat = false;
4228 // FIXME: Check for legal shuffle and return?
4230 if (isUndefShuffle(Op.getNode()))
4231 return DAG.getUNDEF(VT);
4233 if (isZeroShuffle(Op.getNode()))
4234 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4236 if (isIdentityMask(PermMask.getNode()))
4238 else if (isIdentityMask(PermMask.getNode(), true))
4241 // Canonicalize movddup shuffles.
4242 if (V2IsUndef && Subtarget->hasSSE2() &&
4243 VT.getSizeInBits() == 128 &&
4244 X86::isMOVDDUPMask(PermMask.getNode()))
4245 return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3());
4247 if (isSplatMask(PermMask.getNode())) {
4248 if (isMMX || NumElems < 4) return Op;
4249 // Promote it to a v4{if}32 splat.
4250 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
4253 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4255 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4256 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG,
4258 if (NewOp.getNode())
4259 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4260 LowerVECTOR_SHUFFLE(NewOp, DAG));
4261 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4262 // FIXME: Figure out a cleaner way to do this.
4263 // Try to make use of movq to zero out the top part.
4264 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4265 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4267 if (NewOp.getNode()) {
4268 SDValue NewV1 = NewOp.getOperand(0);
4269 SDValue NewV2 = NewOp.getOperand(1);
4270 SDValue NewMask = NewOp.getOperand(2);
4271 if (isCommutedMOVL(NewMask.getNode(), true, false)) {
4272 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
4273 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget,
4277 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4278 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4280 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
4281 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4282 DAG, Subtarget, dl);
4286 // Check if this can be converted into a logical shift.
4287 bool isLeft = false;
4290 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
4291 if (isShift && ShVal.hasOneUse()) {
4292 // If the shifted value has multiple uses, it may be cheaper to use
4293 // v_set0 + movlhps or movhlps, etc.
4294 MVT EVT = VT.getVectorElementType();
4295 ShAmt *= EVT.getSizeInBits();
4296 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4299 if (X86::isMOVLMask(PermMask.getNode())) {
4302 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4303 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4308 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
4309 X86::isMOVSLDUPMask(PermMask.getNode()) ||
4310 X86::isMOVHLPSMask(PermMask.getNode()) ||
4311 X86::isMOVHPMask(PermMask.getNode()) ||
4312 X86::isMOVLPMask(PermMask.getNode())))
4315 if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
4316 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
4317 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4320 // No better options. Use a vshl / vsrl.
4321 MVT EVT = VT.getVectorElementType();
4322 ShAmt *= EVT.getSizeInBits();
4323 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4326 bool Commuted = false;
4327 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4328 // 1,1,1,1 -> v8i16 though.
4329 V1IsSplat = isSplatVector(V1.getNode());
4330 V2IsSplat = isSplatVector(V2.getNode());
4332 // Canonicalize the splat or undef, if present, to be on the RHS.
4333 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4334 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4335 std::swap(V1IsSplat, V2IsSplat);
4336 std::swap(V1IsUndef, V2IsUndef);
4340 // FIXME: Figure out a cleaner way to do this.
4341 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
4342 if (V2IsUndef) return V1;
4343 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4345 // V2 is a splat, so the mask may be malformed. That is, it may point
4346 // to any V2 element. The instruction selectior won't like this. Get
4347 // a corrected mask and commute to form a proper MOVS{S|D}.
4348 SDValue NewMask = getMOVLMask(NumElems, DAG, dl);
4349 if (NewMask.getNode() != PermMask.getNode())
4350 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
4355 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4356 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4357 X86::isUNPCKLMask(PermMask.getNode()) ||
4358 X86::isUNPCKHMask(PermMask.getNode()))
4362 // Normalize mask so all entries that point to V2 points to its first
4363 // element then try to match unpck{h|l} again. If match, return a
4364 // new vector_shuffle with the corrected mask.
4365 SDValue NewMask = NormalizeMask(PermMask, DAG);
4366 if (NewMask.getNode() != PermMask.getNode()) {
4367 if (X86::isUNPCKLMask(NewMask.getNode(), true)) {
4368 SDValue NewMask = getUnpacklMask(NumElems, DAG, dl);
4369 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
4370 } else if (X86::isUNPCKHMask(NewMask.getNode(), true)) {
4371 SDValue NewMask = getUnpackhMask(NumElems, DAG, dl);
4372 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
4377 // Normalize the node to match x86 shuffle ops if needed
4378 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
4379 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4382 // Commute is back and try unpck* again.
4383 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4384 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4385 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4386 X86::isUNPCKLMask(PermMask.getNode()) ||
4387 X86::isUNPCKHMask(PermMask.getNode()))
4391 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4392 // Try PSHUF* first, then SHUFP*.
4393 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
4394 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
4395 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
4396 if (V2.getOpcode() != ISD::UNDEF)
4397 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1,
4398 DAG.getUNDEF(VT), PermMask);
4403 if (Subtarget->hasSSE2() &&
4404 (X86::isPSHUFDMask(PermMask.getNode()) ||
4405 X86::isPSHUFHWMask(PermMask.getNode()) ||
4406 X86::isPSHUFLWMask(PermMask.getNode()))) {
4408 if (VT == MVT::v4f32) {
4410 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT,
4411 DAG.getNode(ISD::BIT_CONVERT, dl, RVT, V1),
4412 DAG.getUNDEF(RVT), PermMask);
4413 } else if (V2.getOpcode() != ISD::UNDEF)
4414 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT, V1,
4415 DAG.getUNDEF(RVT), PermMask);
4417 Op = DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op);
4421 // Binary or unary shufps.
4422 if (X86::isSHUFPMask(PermMask.getNode()) ||
4423 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
4427 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4428 if (VT == MVT::v8i16) {
4429 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this, dl);
4430 if (NewOp.getNode())
4434 if (VT == MVT::v16i8) {
4435 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(V1, V2, PermMask, DAG, *this, dl);
4436 if (NewOp.getNode())
4440 // Handle all 4 wide cases with a number of shuffles except for MMX.
4441 if (NumElems == 4 && !isMMX)
4442 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG, dl);
4448 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4449 SelectionDAG &DAG) {
4450 MVT VT = Op.getValueType();
4451 DebugLoc dl = Op.getDebugLoc();
4452 if (VT.getSizeInBits() == 8) {
4453 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4454 Op.getOperand(0), Op.getOperand(1));
4455 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4456 DAG.getValueType(VT));
4457 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4458 } else if (VT.getSizeInBits() == 16) {
4459 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4460 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4462 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4463 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4464 DAG.getNode(ISD::BIT_CONVERT, dl,
4468 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4469 Op.getOperand(0), Op.getOperand(1));
4470 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4471 DAG.getValueType(VT));
4472 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4473 } else if (VT == MVT::f32) {
4474 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4475 // the result back to FR32 register. It's only worth matching if the
4476 // result has a single use which is a store or a bitcast to i32. And in
4477 // the case of a store, it's not worth it if the index is a constant 0,
4478 // because a MOVSSmr can be used instead, which is smaller and faster.
4479 if (!Op.hasOneUse())
4481 SDNode *User = *Op.getNode()->use_begin();
4482 if ((User->getOpcode() != ISD::STORE ||
4483 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4484 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4485 (User->getOpcode() != ISD::BIT_CONVERT ||
4486 User->getValueType(0) != MVT::i32))
4488 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4489 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4492 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4493 } else if (VT == MVT::i32) {
4494 // ExtractPS works with constant index.
4495 if (isa<ConstantSDNode>(Op.getOperand(1)))
4503 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4504 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4507 if (Subtarget->hasSSE41()) {
4508 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4513 MVT VT = Op.getValueType();
4514 DebugLoc dl = Op.getDebugLoc();
4515 // TODO: handle v16i8.
4516 if (VT.getSizeInBits() == 16) {
4517 SDValue Vec = Op.getOperand(0);
4518 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4520 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4521 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4522 DAG.getNode(ISD::BIT_CONVERT, dl,
4525 // Transform it so it match pextrw which produces a 32-bit result.
4526 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4527 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
4528 Op.getOperand(0), Op.getOperand(1));
4529 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
4530 DAG.getValueType(VT));
4531 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4532 } else if (VT.getSizeInBits() == 32) {
4533 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4536 // SHUFPS the element to the lowest double word, then movss.
4537 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4538 SmallVector<SDValue, 8> IdxVec;
4540 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4542 push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
4544 push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
4546 push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
4547 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4548 &IdxVec[0], IdxVec.size());
4549 SDValue Vec = Op.getOperand(0);
4550 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
4551 Vec, DAG.getUNDEF(Vec.getValueType()), Mask);
4552 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4553 DAG.getIntPtrConstant(0));
4554 } else if (VT.getSizeInBits() == 64) {
4555 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4556 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4557 // to match extract_elt for f64.
4558 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4562 // UNPCKHPD the element to the lowest double word, then movsd.
4563 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4564 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4565 MVT MaskVT = MVT::getIntVectorWithNumElements(2);
4566 SmallVector<SDValue, 8> IdxVec;
4567 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4569 push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
4570 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4571 &IdxVec[0], IdxVec.size());
4572 SDValue Vec = Op.getOperand(0);
4573 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
4574 Vec, DAG.getUNDEF(Vec.getValueType()),
4576 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4577 DAG.getIntPtrConstant(0));
4584 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4585 MVT VT = Op.getValueType();
4586 MVT EVT = VT.getVectorElementType();
4587 DebugLoc dl = Op.getDebugLoc();
4589 SDValue N0 = Op.getOperand(0);
4590 SDValue N1 = Op.getOperand(1);
4591 SDValue N2 = Op.getOperand(2);
4593 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4594 isa<ConstantSDNode>(N2)) {
4595 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4597 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4599 if (N1.getValueType() != MVT::i32)
4600 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4601 if (N2.getValueType() != MVT::i32)
4602 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4603 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4604 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4605 // Bits [7:6] of the constant are the source select. This will always be
4606 // zero here. The DAG Combiner may combine an extract_elt index into these
4607 // bits. For example (insert (extract, 3), 2) could be matched by putting
4608 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4609 // Bits [5:4] of the constant are the destination select. This is the
4610 // value of the incoming immediate.
4611 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4612 // combine either bitwise AND or insert of float 0.0 to set these bits.
4613 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4614 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4615 } else if (EVT == MVT::i32) {
4616 // InsertPS works with constant index.
4617 if (isa<ConstantSDNode>(N2))
4624 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4625 MVT VT = Op.getValueType();
4626 MVT EVT = VT.getVectorElementType();
4628 if (Subtarget->hasSSE41())
4629 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4634 DebugLoc dl = Op.getDebugLoc();
4635 SDValue N0 = Op.getOperand(0);
4636 SDValue N1 = Op.getOperand(1);
4637 SDValue N2 = Op.getOperand(2);
4639 if (EVT.getSizeInBits() == 16) {
4640 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4641 // as its second argument.
4642 if (N1.getValueType() != MVT::i32)
4643 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4644 if (N2.getValueType() != MVT::i32)
4645 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4646 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4652 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4653 DebugLoc dl = Op.getDebugLoc();
4654 if (Op.getValueType() == MVT::v2f32)
4655 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4656 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4657 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4658 Op.getOperand(0))));
4660 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4661 MVT VT = MVT::v2i32;
4662 switch (Op.getValueType().getSimpleVT()) {
4669 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4670 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4673 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4674 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4675 // one of the above mentioned nodes. It has to be wrapped because otherwise
4676 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4677 // be used to form addressing mode. These wrapped nodes will be selected
4680 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4681 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4682 // FIXME there isn't really any debug info here, should come from the parent
4683 DebugLoc dl = CP->getDebugLoc();
4684 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4685 CP->getAlignment());
4686 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4687 // With PIC, the address is actually $g + Offset.
4688 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4689 !Subtarget->isPICStyleRIPRel()) {
4690 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4691 DAG.getNode(X86ISD::GlobalBaseReg,
4692 DebugLoc::getUnknownLoc(),
4701 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4703 SelectionDAG &DAG) const {
4704 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
4705 bool ExtraLoadRequired =
4706 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false);
4708 // Create the TargetGlobalAddress node, folding in the constant
4709 // offset if it is legal.
4711 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) {
4712 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4715 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0);
4716 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4718 // With PIC, the address is actually $g + Offset.
4719 if (IsPic && !Subtarget->isPICStyleRIPRel()) {
4720 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4721 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4725 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4726 // load the value at address GV, not the value of GV itself. This means that
4727 // the GlobalAddress must be in the base or index register of the address, not
4728 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4729 // The same applies for external symbols during PIC codegen
4730 if (ExtraLoadRequired)
4731 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4732 PseudoSourceValue::getGOT(), 0);
4734 // If there was a non-zero offset that we didn't fold, create an explicit
4737 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4738 DAG.getConstant(Offset, getPointerTy()));
4744 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4745 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4746 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4747 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4750 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4752 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4755 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4756 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4757 DAG.getNode(X86ISD::GlobalBaseReg,
4758 DebugLoc::getUnknownLoc(),
4760 InFlag = Chain.getValue(1);
4762 // emit leal symbol@TLSGD(,%ebx,1), %eax
4763 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4764 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4765 GA->getValueType(0),
4767 SDValue Ops[] = { Chain, TGA, InFlag };
4768 SDValue Result = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4769 InFlag = Result.getValue(2);
4770 Chain = Result.getValue(1);
4772 // call ___tls_get_addr. This function receives its argument in
4773 // the register EAX.
4774 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Result, InFlag);
4775 InFlag = Chain.getValue(1);
4777 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4778 SDValue Ops1[] = { Chain,
4779 DAG.getTargetExternalSymbol("___tls_get_addr",
4781 DAG.getRegister(X86::EAX, PtrVT),
4782 DAG.getRegister(X86::EBX, PtrVT),
4784 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops1, 5);
4785 InFlag = Chain.getValue(1);
4787 return DAG.getCopyFromReg(Chain, dl, X86::EAX, PtrVT, InFlag);
4790 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4792 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4794 SDValue InFlag, Chain;
4795 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4797 // emit leaq symbol@TLSGD(%rip), %rdi
4798 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4799 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4800 GA->getValueType(0),
4802 SDValue Ops[] = { DAG.getEntryNode(), TGA};
4803 SDValue Result = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4804 Chain = Result.getValue(1);
4805 InFlag = Result.getValue(2);
4807 // call __tls_get_addr. This function receives its argument in
4808 // the register RDI.
4809 Chain = DAG.getCopyToReg(Chain, dl, X86::RDI, Result, InFlag);
4810 InFlag = Chain.getValue(1);
4812 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4813 SDValue Ops1[] = { Chain,
4814 DAG.getTargetExternalSymbol("__tls_get_addr",
4816 DAG.getRegister(X86::RDI, PtrVT),
4818 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops1, 4);
4819 InFlag = Chain.getValue(1);
4821 return DAG.getCopyFromReg(Chain, dl, X86::RAX, PtrVT, InFlag);
4824 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4825 // "local exec" model.
4826 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4827 const MVT PtrVT, TLSModel::Model model) {
4828 DebugLoc dl = GA->getDebugLoc();
4829 // Get the Thread Pointer
4830 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER,
4831 DebugLoc::getUnknownLoc(), PtrVT);
4832 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4834 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4835 GA->getValueType(0),
4837 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
4839 if (model == TLSModel::InitialExec)
4840 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4841 PseudoSourceValue::getGOT(), 0);
4843 // The address of the thread local variable is the add of the thread
4844 // pointer with the offset of the variable.
4845 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
4849 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4850 // TODO: implement the "local dynamic" model
4851 // TODO: implement the "initial exec"model for pic executables
4852 assert(Subtarget->isTargetELF() &&
4853 "TLS not implemented for non-ELF targets");
4854 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4855 GlobalValue *GV = GA->getGlobal();
4856 TLSModel::Model model =
4857 getTLSModel (GV, getTargetMachine().getRelocationModel());
4858 if (Subtarget->is64Bit()) {
4860 case TLSModel::GeneralDynamic:
4861 case TLSModel::LocalDynamic: // not implemented
4862 case TLSModel::InitialExec: // not implemented
4863 case TLSModel::LocalExec: // not implemented
4864 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4866 assert (0 && "Unknown TLS model");
4870 case TLSModel::GeneralDynamic:
4871 case TLSModel::LocalDynamic: // not implemented
4872 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4874 case TLSModel::InitialExec:
4875 case TLSModel::LocalExec:
4876 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model);
4878 assert (0 && "Unknown TLS model");
4884 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4885 // FIXME there isn't really any debug info here
4886 DebugLoc dl = Op.getDebugLoc();
4887 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4888 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4889 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4890 // With PIC, the address is actually $g + Offset.
4891 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4892 !Subtarget->isPICStyleRIPRel()) {
4893 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4894 DAG.getNode(X86ISD::GlobalBaseReg,
4895 DebugLoc::getUnknownLoc(),
4903 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4904 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4905 // FIXME there isn't really any debug into here
4906 DebugLoc dl = JT->getDebugLoc();
4907 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4908 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4909 // With PIC, the address is actually $g + Offset.
4910 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4911 !Subtarget->isPICStyleRIPRel()) {
4912 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4913 DAG.getNode(X86ISD::GlobalBaseReg,
4914 DebugLoc::getUnknownLoc(),
4922 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4923 /// take a 2 x i32 value to shift plus a shift amount.
4924 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4925 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4926 MVT VT = Op.getValueType();
4927 unsigned VTBits = VT.getSizeInBits();
4928 DebugLoc dl = Op.getDebugLoc();
4929 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4930 SDValue ShOpLo = Op.getOperand(0);
4931 SDValue ShOpHi = Op.getOperand(1);
4932 SDValue ShAmt = Op.getOperand(2);
4933 SDValue Tmp1 = isSRA ?
4934 DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
4935 DAG.getConstant(VTBits - 1, MVT::i8)) :
4936 DAG.getConstant(0, VT);
4939 if (Op.getOpcode() == ISD::SHL_PARTS) {
4940 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
4941 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4943 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
4944 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
4947 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
4948 DAG.getConstant(VTBits, MVT::i8));
4949 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
4950 AndNode, DAG.getConstant(0, MVT::i8));
4953 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4954 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4955 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4957 if (Op.getOpcode() == ISD::SHL_PARTS) {
4958 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4959 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4961 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4962 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4965 SDValue Ops[2] = { Lo, Hi };
4966 return DAG.getMergeValues(Ops, 2, dl);
4969 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4970 MVT SrcVT = Op.getOperand(0).getValueType();
4971 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4972 "Unknown SINT_TO_FP to lower!");
4974 // These are really Legal; caller falls through into that case.
4975 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4977 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4978 Subtarget->is64Bit())
4981 DebugLoc dl = Op.getDebugLoc();
4982 unsigned Size = SrcVT.getSizeInBits()/8;
4983 MachineFunction &MF = DAG.getMachineFunction();
4984 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4985 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4986 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
4988 PseudoSourceValue::getFixedStack(SSFI), 0);
4992 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4994 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4996 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4997 SmallVector<SDValue, 8> Ops;
4998 Ops.push_back(Chain);
4999 Ops.push_back(StackSlot);
5000 Ops.push_back(DAG.getValueType(SrcVT));
5001 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5002 Tys, &Ops[0], Ops.size());
5005 Chain = Result.getValue(1);
5006 SDValue InFlag = Result.getValue(2);
5008 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5009 // shouldn't be necessary except that RFP cannot be live across
5010 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5011 MachineFunction &MF = DAG.getMachineFunction();
5012 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
5013 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5014 Tys = DAG.getVTList(MVT::Other);
5015 SmallVector<SDValue, 8> Ops;
5016 Ops.push_back(Chain);
5017 Ops.push_back(Result);
5018 Ops.push_back(StackSlot);
5019 Ops.push_back(DAG.getValueType(Op.getValueType()));
5020 Ops.push_back(InFlag);
5021 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
5022 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5023 PseudoSourceValue::getFixedStack(SSFI), 0);
5029 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5030 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5031 // This algorithm is not obvious. Here it is in C code, more or less:
5033 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5034 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5035 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5037 // Copy ints to xmm registers.
5038 __m128i xh = _mm_cvtsi32_si128( hi );
5039 __m128i xl = _mm_cvtsi32_si128( lo );
5041 // Combine into low half of a single xmm register.
5042 __m128i x = _mm_unpacklo_epi32( xh, xl );
5046 // Merge in appropriate exponents to give the integer bits the right
5048 x = _mm_unpacklo_epi32( x, exp );
5050 // Subtract away the biases to deal with the IEEE-754 double precision
5052 d = _mm_sub_pd( (__m128d) x, bias );
5054 // All conversions up to here are exact. The correctly rounded result is
5055 // calculated using the current rounding mode using the following
5057 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5058 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5059 // store doesn't really need to be here (except
5060 // maybe to zero the other double)
5065 DebugLoc dl = Op.getDebugLoc();
5067 // Build some magic constants.
5068 std::vector<Constant*> CV0;
5069 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000)));
5070 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000)));
5071 CV0.push_back(ConstantInt::get(APInt(32, 0)));
5072 CV0.push_back(ConstantInt::get(APInt(32, 0)));
5073 Constant *C0 = ConstantVector::get(CV0);
5074 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5076 std::vector<Constant*> CV1;
5077 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL))));
5078 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL))));
5079 Constant *C1 = ConstantVector::get(CV1);
5080 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5082 SmallVector<SDValue, 4> MaskVec;
5083 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
5084 MaskVec.push_back(DAG.getConstant(4, MVT::i32));
5085 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
5086 MaskVec.push_back(DAG.getConstant(5, MVT::i32));
5087 SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
5088 &MaskVec[0], MaskVec.size());
5089 SmallVector<SDValue, 4> MaskVec2;
5090 MaskVec2.push_back(DAG.getConstant(1, MVT::i32));
5091 MaskVec2.push_back(DAG.getConstant(0, MVT::i32));
5092 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32,
5093 &MaskVec2[0], MaskVec2.size());
5095 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5096 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5098 DAG.getIntPtrConstant(1)));
5099 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5100 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5102 DAG.getIntPtrConstant(0)));
5103 SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32,
5104 XR1, XR2, UnpcklMask);
5105 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5106 PseudoSourceValue::getConstantPool(), 0,
5108 SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32,
5109 Unpck1, CLod0, UnpcklMask);
5110 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5111 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5112 PseudoSourceValue::getConstantPool(), 0,
5114 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5116 // Add the halves; easiest way is to swap them into another reg first.
5117 SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2f64,
5118 Sub, Sub, ShufMask);
5119 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5120 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5121 DAG.getIntPtrConstant(0));
5124 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5125 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5126 DebugLoc dl = Op.getDebugLoc();
5127 // FP constant to bias correct the final result.
5128 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5131 // Load the 32-bit value into an XMM register.
5132 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5133 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5135 DAG.getIntPtrConstant(0)));
5137 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5138 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5139 DAG.getIntPtrConstant(0));
5141 // Or the load with the bias.
5142 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5143 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5144 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5146 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5147 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5148 MVT::v2f64, Bias)));
5149 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5150 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5151 DAG.getIntPtrConstant(0));
5153 // Subtract the bias.
5154 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5156 // Handle final rounding.
5157 MVT DestVT = Op.getValueType();
5159 if (DestVT.bitsLT(MVT::f64)) {
5160 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5161 DAG.getIntPtrConstant(0));
5162 } else if (DestVT.bitsGT(MVT::f64)) {
5163 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5166 // Handle final rounding.
5170 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5171 SDValue N0 = Op.getOperand(0);
5172 DebugLoc dl = Op.getDebugLoc();
5174 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5175 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5176 // the optimization here.
5177 if (DAG.SignBitIsZero(N0))
5178 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5180 MVT SrcVT = N0.getValueType();
5181 if (SrcVT == MVT::i64) {
5182 // We only handle SSE2 f64 target here; caller can handle the rest.
5183 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5186 return LowerUINT_TO_FP_i64(Op, DAG);
5187 } else if (SrcVT == MVT::i32) {
5188 return LowerUINT_TO_FP_i32(Op, DAG);
5191 assert(0 && "Unknown UINT_TO_FP to lower!");
5195 std::pair<SDValue,SDValue> X86TargetLowering::
5196 FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
5197 DebugLoc dl = Op.getDebugLoc();
5198 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
5199 Op.getValueType().getSimpleVT() >= MVT::i16 &&
5200 "Unknown FP_TO_SINT to lower!");
5202 // These are really Legal.
5203 if (Op.getValueType() == MVT::i32 &&
5204 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5205 return std::make_pair(SDValue(), SDValue());
5206 if (Subtarget->is64Bit() &&
5207 Op.getValueType() == MVT::i64 &&
5208 Op.getOperand(0).getValueType() != MVT::f80)
5209 return std::make_pair(SDValue(), SDValue());
5211 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5213 MachineFunction &MF = DAG.getMachineFunction();
5214 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
5215 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5216 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5218 switch (Op.getValueType().getSimpleVT()) {
5219 default: assert(0 && "Invalid FP_TO_SINT to lower!");
5220 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5221 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5222 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5225 SDValue Chain = DAG.getEntryNode();
5226 SDValue Value = Op.getOperand(0);
5227 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5228 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5229 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5230 PseudoSourceValue::getFixedStack(SSFI), 0);
5231 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5233 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5235 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5236 Chain = Value.getValue(1);
5237 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5238 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5241 // Build the FP_TO_INT*_IN_MEM
5242 SDValue Ops[] = { Chain, Value, StackSlot };
5243 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5245 return std::make_pair(FIST, StackSlot);
5248 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5249 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
5250 SDValue FIST = Vals.first, StackSlot = Vals.second;
5251 if (FIST.getNode() == 0) return SDValue();
5254 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5255 FIST, StackSlot, NULL, 0);
5258 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5259 DebugLoc dl = Op.getDebugLoc();
5260 MVT VT = Op.getValueType();
5263 EltVT = VT.getVectorElementType();
5264 std::vector<Constant*> CV;
5265 if (EltVT == MVT::f64) {
5266 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
5270 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
5276 Constant *C = ConstantVector::get(CV);
5277 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5278 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5279 PseudoSourceValue::getConstantPool(), 0,
5281 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5284 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5285 DebugLoc dl = Op.getDebugLoc();
5286 MVT VT = Op.getValueType();
5288 unsigned EltNum = 1;
5289 if (VT.isVector()) {
5290 EltVT = VT.getVectorElementType();
5291 EltNum = VT.getVectorNumElements();
5293 std::vector<Constant*> CV;
5294 if (EltVT == MVT::f64) {
5295 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
5299 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
5305 Constant *C = ConstantVector::get(CV);
5306 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5307 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5308 PseudoSourceValue::getConstantPool(), 0,
5310 if (VT.isVector()) {
5311 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5312 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5313 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5315 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5317 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5321 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5322 SDValue Op0 = Op.getOperand(0);
5323 SDValue Op1 = Op.getOperand(1);
5324 DebugLoc dl = Op.getDebugLoc();
5325 MVT VT = Op.getValueType();
5326 MVT SrcVT = Op1.getValueType();
5328 // If second operand is smaller, extend it first.
5329 if (SrcVT.bitsLT(VT)) {
5330 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5333 // And if it is bigger, shrink it first.
5334 if (SrcVT.bitsGT(VT)) {
5335 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5339 // At this point the operands and the result should have the same
5340 // type, and that won't be f80 since that is not custom lowered.
5342 // First get the sign bit of second operand.
5343 std::vector<Constant*> CV;
5344 if (SrcVT == MVT::f64) {
5345 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
5346 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
5348 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
5349 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5350 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5351 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5353 Constant *C = ConstantVector::get(CV);
5354 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5355 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5356 PseudoSourceValue::getConstantPool(), 0,
5358 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5360 // Shift sign bit right or left if the two operands have different types.
5361 if (SrcVT.bitsGT(VT)) {
5362 // Op0 is MVT::f32, Op1 is MVT::f64.
5363 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5364 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5365 DAG.getConstant(32, MVT::i32));
5366 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5367 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5368 DAG.getIntPtrConstant(0));
5371 // Clear first operand sign bit.
5373 if (VT == MVT::f64) {
5374 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
5375 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
5377 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
5378 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5379 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5380 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5382 C = ConstantVector::get(CV);
5383 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5384 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5385 PseudoSourceValue::getConstantPool(), 0,
5387 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5389 // Or the value with the sign bit.
5390 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5393 /// Emit nodes that will be selected as "test Op0,Op0", or something
5395 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5396 SelectionDAG &DAG) {
5397 DebugLoc dl = Op.getDebugLoc();
5399 // CF and OF aren't always set the way we want. Determine which
5400 // of these we need.
5401 bool NeedCF = false;
5402 bool NeedOF = false;
5404 case X86::COND_A: case X86::COND_AE:
5405 case X86::COND_B: case X86::COND_BE:
5408 case X86::COND_G: case X86::COND_GE:
5409 case X86::COND_L: case X86::COND_LE:
5410 case X86::COND_O: case X86::COND_NO:
5416 // See if we can use the EFLAGS value from the operand instead of
5417 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5418 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5419 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5420 unsigned Opcode = 0;
5421 unsigned NumOperands = 0;
5422 switch (Op.getNode()->getOpcode()) {
5424 // Due to an isel shortcoming, be conservative if this add is likely to
5425 // be selected as part of a load-modify-store instruction. When the root
5426 // node in a match is a store, isel doesn't know how to remap non-chain
5427 // non-flag uses of other nodes in the match, such as the ADD in this
5428 // case. This leads to the ADD being left around and reselected, with
5429 // the result being two adds in the output.
5430 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5431 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5432 if (UI->getOpcode() == ISD::STORE)
5434 if (ConstantSDNode *C =
5435 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5436 // An add of one will be selected as an INC.
5437 if (C->getAPIntValue() == 1) {
5438 Opcode = X86ISD::INC;
5442 // An add of negative one (subtract of one) will be selected as a DEC.
5443 if (C->getAPIntValue().isAllOnesValue()) {
5444 Opcode = X86ISD::DEC;
5449 // Otherwise use a regular EFLAGS-setting add.
5450 Opcode = X86ISD::ADD;
5454 // Due to the ISEL shortcoming noted above, be conservative if this sub is
5455 // likely to be selected as part of a load-modify-store instruction.
5456 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5457 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5458 if (UI->getOpcode() == ISD::STORE)
5460 // Otherwise use a regular EFLAGS-setting sub.
5461 Opcode = X86ISD::SUB;
5468 return SDValue(Op.getNode(), 1);
5474 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::i32);
5475 SmallVector<SDValue, 4> Ops;
5476 for (unsigned i = 0; i != NumOperands; ++i)
5477 Ops.push_back(Op.getOperand(i));
5478 SDValue New = DAG.getNode(Opcode, dl, VTs, 2, &Ops[0], NumOperands);
5479 DAG.ReplaceAllUsesWith(Op, New);
5480 return SDValue(New.getNode(), 1);
5484 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5485 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5486 DAG.getConstant(0, Op.getValueType()));
5489 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5491 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5492 SelectionDAG &DAG) {
5493 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5494 if (C->getAPIntValue() == 0)
5495 return EmitTest(Op0, X86CC, DAG);
5497 DebugLoc dl = Op0.getDebugLoc();
5498 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5501 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5502 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5503 SDValue Op0 = Op.getOperand(0);
5504 SDValue Op1 = Op.getOperand(1);
5505 DebugLoc dl = Op.getDebugLoc();
5506 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5508 // Lower (X & (1 << N)) == 0 to BT(X, N).
5509 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5510 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5511 if (Op0.getOpcode() == ISD::AND &&
5513 Op1.getOpcode() == ISD::Constant &&
5514 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5515 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5517 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5518 if (ConstantSDNode *Op010C =
5519 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5520 if (Op010C->getZExtValue() == 1) {
5521 LHS = Op0.getOperand(0);
5522 RHS = Op0.getOperand(1).getOperand(1);
5524 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5525 if (ConstantSDNode *Op000C =
5526 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5527 if (Op000C->getZExtValue() == 1) {
5528 LHS = Op0.getOperand(1);
5529 RHS = Op0.getOperand(0).getOperand(1);
5531 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5532 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5533 SDValue AndLHS = Op0.getOperand(0);
5534 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5535 LHS = AndLHS.getOperand(0);
5536 RHS = AndLHS.getOperand(1);
5540 if (LHS.getNode()) {
5541 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5542 // instruction. Since the shift amount is in-range-or-undefined, we know
5543 // that doing a bittest on the i16 value is ok. We extend to i32 because
5544 // the encoding for the i16 version is larger than the i32 version.
5545 if (LHS.getValueType() == MVT::i8)
5546 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5548 // If the operand types disagree, extend the shift amount to match. Since
5549 // BT ignores high bits (like shifts) we can use anyextend.
5550 if (LHS.getValueType() != RHS.getValueType())
5551 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5553 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5554 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5555 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5556 DAG.getConstant(Cond, MVT::i8), BT);
5560 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5561 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5563 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5564 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5565 DAG.getConstant(X86CC, MVT::i8), Cond);
5568 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5570 SDValue Op0 = Op.getOperand(0);
5571 SDValue Op1 = Op.getOperand(1);
5572 SDValue CC = Op.getOperand(2);
5573 MVT VT = Op.getValueType();
5574 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5575 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5576 DebugLoc dl = Op.getDebugLoc();
5580 MVT VT0 = Op0.getValueType();
5581 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5582 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5585 switch (SetCCOpcode) {
5588 case ISD::SETEQ: SSECC = 0; break;
5590 case ISD::SETGT: Swap = true; // Fallthrough
5592 case ISD::SETOLT: SSECC = 1; break;
5594 case ISD::SETGE: Swap = true; // Fallthrough
5596 case ISD::SETOLE: SSECC = 2; break;
5597 case ISD::SETUO: SSECC = 3; break;
5599 case ISD::SETNE: SSECC = 4; break;
5600 case ISD::SETULE: Swap = true;
5601 case ISD::SETUGE: SSECC = 5; break;
5602 case ISD::SETULT: Swap = true;
5603 case ISD::SETUGT: SSECC = 6; break;
5604 case ISD::SETO: SSECC = 7; break;
5607 std::swap(Op0, Op1);
5609 // In the two special cases we can't handle, emit two comparisons.
5611 if (SetCCOpcode == ISD::SETUEQ) {
5613 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5614 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5615 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5617 else if (SetCCOpcode == ISD::SETONE) {
5619 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5620 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5621 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5623 assert(0 && "Illegal FP comparison");
5625 // Handle all other FP comparisons here.
5626 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5629 // We are handling one of the integer comparisons here. Since SSE only has
5630 // GT and EQ comparisons for integer, swapping operands and multiple
5631 // operations may be required for some comparisons.
5632 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5633 bool Swap = false, Invert = false, FlipSigns = false;
5635 switch (VT.getSimpleVT()) {
5637 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5638 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5639 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5640 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5643 switch (SetCCOpcode) {
5645 case ISD::SETNE: Invert = true;
5646 case ISD::SETEQ: Opc = EQOpc; break;
5647 case ISD::SETLT: Swap = true;
5648 case ISD::SETGT: Opc = GTOpc; break;
5649 case ISD::SETGE: Swap = true;
5650 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5651 case ISD::SETULT: Swap = true;
5652 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5653 case ISD::SETUGE: Swap = true;
5654 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5657 std::swap(Op0, Op1);
5659 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5660 // bits of the inputs before performing those operations.
5662 MVT EltVT = VT.getVectorElementType();
5663 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5665 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5666 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5668 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5669 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5672 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5674 // If the logical-not of the result is required, perform that now.
5676 Result = DAG.getNOT(dl, Result, VT);
5681 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5682 static bool isX86LogicalCmp(SDValue Op) {
5683 unsigned Opc = Op.getNode()->getOpcode();
5684 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5686 if (Op.getResNo() == 1 &&
5687 (Opc == X86ISD::ADD ||
5688 Opc == X86ISD::SUB ||
5689 Opc == X86ISD::SMUL ||
5690 Opc == X86ISD::UMUL ||
5691 Opc == X86ISD::INC ||
5692 Opc == X86ISD::DEC))
5698 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5699 bool addTest = true;
5700 SDValue Cond = Op.getOperand(0);
5701 DebugLoc dl = Op.getDebugLoc();
5704 if (Cond.getOpcode() == ISD::SETCC)
5705 Cond = LowerSETCC(Cond, DAG);
5707 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5708 // setting operand in place of the X86ISD::SETCC.
5709 if (Cond.getOpcode() == X86ISD::SETCC) {
5710 CC = Cond.getOperand(0);
5712 SDValue Cmp = Cond.getOperand(1);
5713 unsigned Opc = Cmp.getOpcode();
5714 MVT VT = Op.getValueType();
5716 bool IllegalFPCMov = false;
5717 if (VT.isFloatingPoint() && !VT.isVector() &&
5718 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5719 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5721 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5722 Opc == X86ISD::BT) { // FIXME
5729 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5730 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5733 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
5735 SmallVector<SDValue, 4> Ops;
5736 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5737 // condition is true.
5738 Ops.push_back(Op.getOperand(2));
5739 Ops.push_back(Op.getOperand(1));
5741 Ops.push_back(Cond);
5742 return DAG.getNode(X86ISD::CMOV, dl, VTs, 2, &Ops[0], Ops.size());
5745 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5746 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5747 // from the AND / OR.
5748 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5749 Opc = Op.getOpcode();
5750 if (Opc != ISD::OR && Opc != ISD::AND)
5752 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5753 Op.getOperand(0).hasOneUse() &&
5754 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5755 Op.getOperand(1).hasOneUse());
5758 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5759 // 1 and that the SETCC node has a single use.
5760 static bool isXor1OfSetCC(SDValue Op) {
5761 if (Op.getOpcode() != ISD::XOR)
5763 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5764 if (N1C && N1C->getAPIntValue() == 1) {
5765 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5766 Op.getOperand(0).hasOneUse();
5771 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5772 bool addTest = true;
5773 SDValue Chain = Op.getOperand(0);
5774 SDValue Cond = Op.getOperand(1);
5775 SDValue Dest = Op.getOperand(2);
5776 DebugLoc dl = Op.getDebugLoc();
5779 if (Cond.getOpcode() == ISD::SETCC)
5780 Cond = LowerSETCC(Cond, DAG);
5782 // FIXME: LowerXALUO doesn't handle these!!
5783 else if (Cond.getOpcode() == X86ISD::ADD ||
5784 Cond.getOpcode() == X86ISD::SUB ||
5785 Cond.getOpcode() == X86ISD::SMUL ||
5786 Cond.getOpcode() == X86ISD::UMUL)
5787 Cond = LowerXALUO(Cond, DAG);
5790 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5791 // setting operand in place of the X86ISD::SETCC.
5792 if (Cond.getOpcode() == X86ISD::SETCC) {
5793 CC = Cond.getOperand(0);
5795 SDValue Cmp = Cond.getOperand(1);
5796 unsigned Opc = Cmp.getOpcode();
5797 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5798 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
5802 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5806 // These can only come from an arithmetic instruction with overflow,
5807 // e.g. SADDO, UADDO.
5808 Cond = Cond.getNode()->getOperand(1);
5815 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5816 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5817 if (CondOpc == ISD::OR) {
5818 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5819 // two branches instead of an explicit OR instruction with a
5821 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5822 isX86LogicalCmp(Cmp)) {
5823 CC = Cond.getOperand(0).getOperand(0);
5824 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5825 Chain, Dest, CC, Cmp);
5826 CC = Cond.getOperand(1).getOperand(0);
5830 } else { // ISD::AND
5831 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5832 // two branches instead of an explicit AND instruction with a
5833 // separate test. However, we only do this if this block doesn't
5834 // have a fall-through edge, because this requires an explicit
5835 // jmp when the condition is false.
5836 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5837 isX86LogicalCmp(Cmp) &&
5838 Op.getNode()->hasOneUse()) {
5839 X86::CondCode CCode =
5840 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5841 CCode = X86::GetOppositeBranchCondition(CCode);
5842 CC = DAG.getConstant(CCode, MVT::i8);
5843 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5844 // Look for an unconditional branch following this conditional branch.
5845 // We need this because we need to reverse the successors in order
5846 // to implement FCMP_OEQ.
5847 if (User.getOpcode() == ISD::BR) {
5848 SDValue FalseBB = User.getOperand(1);
5850 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5851 assert(NewBR == User);
5854 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5855 Chain, Dest, CC, Cmp);
5856 X86::CondCode CCode =
5857 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5858 CCode = X86::GetOppositeBranchCondition(CCode);
5859 CC = DAG.getConstant(CCode, MVT::i8);
5865 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5866 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5867 // It should be transformed during dag combiner except when the condition
5868 // is set by a arithmetics with overflow node.
5869 X86::CondCode CCode =
5870 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5871 CCode = X86::GetOppositeBranchCondition(CCode);
5872 CC = DAG.getConstant(CCode, MVT::i8);
5873 Cond = Cond.getOperand(0).getOperand(1);
5879 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5880 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5882 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5883 Chain, Dest, CC, Cond);
5887 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5888 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5889 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5890 // that the guard pages used by the OS virtual memory manager are allocated in
5891 // correct sequence.
5893 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5894 SelectionDAG &DAG) {
5895 assert(Subtarget->isTargetCygMing() &&
5896 "This should be used only on Cygwin/Mingw targets");
5897 DebugLoc dl = Op.getDebugLoc();
5900 SDValue Chain = Op.getOperand(0);
5901 SDValue Size = Op.getOperand(1);
5902 // FIXME: Ensure alignment here
5906 MVT IntPtr = getPointerTy();
5907 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5909 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5911 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
5912 Flag = Chain.getValue(1);
5914 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5915 SDValue Ops[] = { Chain,
5916 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5917 DAG.getRegister(X86::EAX, IntPtr),
5918 DAG.getRegister(X86StackPtr, SPTy),
5920 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
5921 Flag = Chain.getValue(1);
5923 Chain = DAG.getCALLSEQ_END(Chain,
5924 DAG.getIntPtrConstant(0, true),
5925 DAG.getIntPtrConstant(0, true),
5928 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
5930 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5931 return DAG.getMergeValues(Ops1, 2, dl);
5935 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
5937 SDValue Dst, SDValue Src,
5938 SDValue Size, unsigned Align,
5940 uint64_t DstSVOff) {
5941 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5943 // If not DWORD aligned or size is more than the threshold, call the library.
5944 // The libc version is likely to be faster for these cases. It can use the
5945 // address value and run time information about the CPU.
5946 if ((Align & 3) != 0 ||
5948 ConstantSize->getZExtValue() >
5949 getSubtarget()->getMaxInlineSizeThreshold()) {
5950 SDValue InFlag(0, 0);
5952 // Check to see if there is a specialized entry-point for memory zeroing.
5953 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5955 if (const char *bzeroEntry = V &&
5956 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5957 MVT IntPtr = getPointerTy();
5958 const Type *IntPtrTy = TD->getIntPtrType();
5959 TargetLowering::ArgListTy Args;
5960 TargetLowering::ArgListEntry Entry;
5962 Entry.Ty = IntPtrTy;
5963 Args.push_back(Entry);
5965 Args.push_back(Entry);
5966 std::pair<SDValue,SDValue> CallResult =
5967 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
5968 CallingConv::C, false,
5969 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
5970 return CallResult.second;
5973 // Otherwise have the target-independent code call memset.
5977 uint64_t SizeVal = ConstantSize->getZExtValue();
5978 SDValue InFlag(0, 0);
5981 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5982 unsigned BytesLeft = 0;
5983 bool TwoRepStos = false;
5986 uint64_t Val = ValC->getZExtValue() & 255;
5988 // If the value is a constant, then we can potentially use larger sets.
5989 switch (Align & 3) {
5990 case 2: // WORD aligned
5993 Val = (Val << 8) | Val;
5995 case 0: // DWORD aligned
5998 Val = (Val << 8) | Val;
5999 Val = (Val << 16) | Val;
6000 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
6003 Val = (Val << 32) | Val;
6006 default: // Byte aligned
6009 Count = DAG.getIntPtrConstant(SizeVal);
6013 if (AVT.bitsGT(MVT::i8)) {
6014 unsigned UBytes = AVT.getSizeInBits() / 8;
6015 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6016 BytesLeft = SizeVal % UBytes;
6019 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6021 InFlag = Chain.getValue(1);
6024 Count = DAG.getIntPtrConstant(SizeVal);
6025 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6026 InFlag = Chain.getValue(1);
6029 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6032 InFlag = Chain.getValue(1);
6033 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6036 InFlag = Chain.getValue(1);
6038 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6039 SmallVector<SDValue, 8> Ops;
6040 Ops.push_back(Chain);
6041 Ops.push_back(DAG.getValueType(AVT));
6042 Ops.push_back(InFlag);
6043 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6046 InFlag = Chain.getValue(1);
6048 MVT CVT = Count.getValueType();
6049 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6050 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6051 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6054 InFlag = Chain.getValue(1);
6055 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6057 Ops.push_back(Chain);
6058 Ops.push_back(DAG.getValueType(MVT::i8));
6059 Ops.push_back(InFlag);
6060 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6061 } else if (BytesLeft) {
6062 // Handle the last 1 - 7 bytes.
6063 unsigned Offset = SizeVal - BytesLeft;
6064 MVT AddrVT = Dst.getValueType();
6065 MVT SizeVT = Size.getValueType();
6067 Chain = DAG.getMemset(Chain, dl,
6068 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6069 DAG.getConstant(Offset, AddrVT)),
6071 DAG.getConstant(BytesLeft, SizeVT),
6072 Align, DstSV, DstSVOff + Offset);
6075 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6080 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6081 SDValue Chain, SDValue Dst, SDValue Src,
6082 SDValue Size, unsigned Align,
6084 const Value *DstSV, uint64_t DstSVOff,
6085 const Value *SrcSV, uint64_t SrcSVOff) {
6086 // This requires the copy size to be a constant, preferrably
6087 // within a subtarget-specific limit.
6088 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6091 uint64_t SizeVal = ConstantSize->getZExtValue();
6092 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6095 /// If not DWORD aligned, call the library.
6096 if ((Align & 3) != 0)
6101 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6104 unsigned UBytes = AVT.getSizeInBits() / 8;
6105 unsigned CountVal = SizeVal / UBytes;
6106 SDValue Count = DAG.getIntPtrConstant(CountVal);
6107 unsigned BytesLeft = SizeVal % UBytes;
6109 SDValue InFlag(0, 0);
6110 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6113 InFlag = Chain.getValue(1);
6114 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6117 InFlag = Chain.getValue(1);
6118 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6121 InFlag = Chain.getValue(1);
6123 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6124 SmallVector<SDValue, 8> Ops;
6125 Ops.push_back(Chain);
6126 Ops.push_back(DAG.getValueType(AVT));
6127 Ops.push_back(InFlag);
6128 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
6130 SmallVector<SDValue, 4> Results;
6131 Results.push_back(RepMovs);
6133 // Handle the last 1 - 7 bytes.
6134 unsigned Offset = SizeVal - BytesLeft;
6135 MVT DstVT = Dst.getValueType();
6136 MVT SrcVT = Src.getValueType();
6137 MVT SizeVT = Size.getValueType();
6138 Results.push_back(DAG.getMemcpy(Chain, dl,
6139 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6140 DAG.getConstant(Offset, DstVT)),
6141 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6142 DAG.getConstant(Offset, SrcVT)),
6143 DAG.getConstant(BytesLeft, SizeVT),
6144 Align, AlwaysInline,
6145 DstSV, DstSVOff + Offset,
6146 SrcSV, SrcSVOff + Offset));
6149 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6150 &Results[0], Results.size());
6153 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6154 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6155 DebugLoc dl = Op.getDebugLoc();
6157 if (!Subtarget->is64Bit()) {
6158 // vastart just stores the address of the VarArgsFrameIndex slot into the
6159 // memory location argument.
6160 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6161 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6165 // gp_offset (0 - 6 * 8)
6166 // fp_offset (48 - 48 + 8 * 16)
6167 // overflow_arg_area (point to parameters coming in memory).
6169 SmallVector<SDValue, 8> MemOps;
6170 SDValue FIN = Op.getOperand(1);
6172 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6173 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6175 MemOps.push_back(Store);
6178 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6179 FIN, DAG.getIntPtrConstant(4));
6180 Store = DAG.getStore(Op.getOperand(0), dl,
6181 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6183 MemOps.push_back(Store);
6185 // Store ptr to overflow_arg_area
6186 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6187 FIN, DAG.getIntPtrConstant(4));
6188 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6189 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6190 MemOps.push_back(Store);
6192 // Store ptr to reg_save_area.
6193 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6194 FIN, DAG.getIntPtrConstant(8));
6195 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6196 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6197 MemOps.push_back(Store);
6198 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6199 &MemOps[0], MemOps.size());
6202 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6203 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6204 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6205 SDValue Chain = Op.getOperand(0);
6206 SDValue SrcPtr = Op.getOperand(1);
6207 SDValue SrcSV = Op.getOperand(2);
6209 assert(0 && "VAArgInst is not yet implemented for x86-64!");
6214 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6215 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6216 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6217 SDValue Chain = Op.getOperand(0);
6218 SDValue DstPtr = Op.getOperand(1);
6219 SDValue SrcPtr = Op.getOperand(2);
6220 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6221 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6222 DebugLoc dl = Op.getDebugLoc();
6224 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6225 DAG.getIntPtrConstant(24), 8, false,
6226 DstSV, 0, SrcSV, 0);
6230 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6231 DebugLoc dl = Op.getDebugLoc();
6232 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6234 default: return SDValue(); // Don't custom lower most intrinsics.
6235 // Comparison intrinsics.
6236 case Intrinsic::x86_sse_comieq_ss:
6237 case Intrinsic::x86_sse_comilt_ss:
6238 case Intrinsic::x86_sse_comile_ss:
6239 case Intrinsic::x86_sse_comigt_ss:
6240 case Intrinsic::x86_sse_comige_ss:
6241 case Intrinsic::x86_sse_comineq_ss:
6242 case Intrinsic::x86_sse_ucomieq_ss:
6243 case Intrinsic::x86_sse_ucomilt_ss:
6244 case Intrinsic::x86_sse_ucomile_ss:
6245 case Intrinsic::x86_sse_ucomigt_ss:
6246 case Intrinsic::x86_sse_ucomige_ss:
6247 case Intrinsic::x86_sse_ucomineq_ss:
6248 case Intrinsic::x86_sse2_comieq_sd:
6249 case Intrinsic::x86_sse2_comilt_sd:
6250 case Intrinsic::x86_sse2_comile_sd:
6251 case Intrinsic::x86_sse2_comigt_sd:
6252 case Intrinsic::x86_sse2_comige_sd:
6253 case Intrinsic::x86_sse2_comineq_sd:
6254 case Intrinsic::x86_sse2_ucomieq_sd:
6255 case Intrinsic::x86_sse2_ucomilt_sd:
6256 case Intrinsic::x86_sse2_ucomile_sd:
6257 case Intrinsic::x86_sse2_ucomigt_sd:
6258 case Intrinsic::x86_sse2_ucomige_sd:
6259 case Intrinsic::x86_sse2_ucomineq_sd: {
6261 ISD::CondCode CC = ISD::SETCC_INVALID;
6264 case Intrinsic::x86_sse_comieq_ss:
6265 case Intrinsic::x86_sse2_comieq_sd:
6269 case Intrinsic::x86_sse_comilt_ss:
6270 case Intrinsic::x86_sse2_comilt_sd:
6274 case Intrinsic::x86_sse_comile_ss:
6275 case Intrinsic::x86_sse2_comile_sd:
6279 case Intrinsic::x86_sse_comigt_ss:
6280 case Intrinsic::x86_sse2_comigt_sd:
6284 case Intrinsic::x86_sse_comige_ss:
6285 case Intrinsic::x86_sse2_comige_sd:
6289 case Intrinsic::x86_sse_comineq_ss:
6290 case Intrinsic::x86_sse2_comineq_sd:
6294 case Intrinsic::x86_sse_ucomieq_ss:
6295 case Intrinsic::x86_sse2_ucomieq_sd:
6296 Opc = X86ISD::UCOMI;
6299 case Intrinsic::x86_sse_ucomilt_ss:
6300 case Intrinsic::x86_sse2_ucomilt_sd:
6301 Opc = X86ISD::UCOMI;
6304 case Intrinsic::x86_sse_ucomile_ss:
6305 case Intrinsic::x86_sse2_ucomile_sd:
6306 Opc = X86ISD::UCOMI;
6309 case Intrinsic::x86_sse_ucomigt_ss:
6310 case Intrinsic::x86_sse2_ucomigt_sd:
6311 Opc = X86ISD::UCOMI;
6314 case Intrinsic::x86_sse_ucomige_ss:
6315 case Intrinsic::x86_sse2_ucomige_sd:
6316 Opc = X86ISD::UCOMI;
6319 case Intrinsic::x86_sse_ucomineq_ss:
6320 case Intrinsic::x86_sse2_ucomineq_sd:
6321 Opc = X86ISD::UCOMI;
6326 SDValue LHS = Op.getOperand(1);
6327 SDValue RHS = Op.getOperand(2);
6328 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6329 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6330 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6331 DAG.getConstant(X86CC, MVT::i8), Cond);
6332 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6335 // Fix vector shift instructions where the last operand is a non-immediate
6337 case Intrinsic::x86_sse2_pslli_w:
6338 case Intrinsic::x86_sse2_pslli_d:
6339 case Intrinsic::x86_sse2_pslli_q:
6340 case Intrinsic::x86_sse2_psrli_w:
6341 case Intrinsic::x86_sse2_psrli_d:
6342 case Intrinsic::x86_sse2_psrli_q:
6343 case Intrinsic::x86_sse2_psrai_w:
6344 case Intrinsic::x86_sse2_psrai_d:
6345 case Intrinsic::x86_mmx_pslli_w:
6346 case Intrinsic::x86_mmx_pslli_d:
6347 case Intrinsic::x86_mmx_pslli_q:
6348 case Intrinsic::x86_mmx_psrli_w:
6349 case Intrinsic::x86_mmx_psrli_d:
6350 case Intrinsic::x86_mmx_psrli_q:
6351 case Intrinsic::x86_mmx_psrai_w:
6352 case Intrinsic::x86_mmx_psrai_d: {
6353 SDValue ShAmt = Op.getOperand(2);
6354 if (isa<ConstantSDNode>(ShAmt))
6357 unsigned NewIntNo = 0;
6358 MVT ShAmtVT = MVT::v4i32;
6360 case Intrinsic::x86_sse2_pslli_w:
6361 NewIntNo = Intrinsic::x86_sse2_psll_w;
6363 case Intrinsic::x86_sse2_pslli_d:
6364 NewIntNo = Intrinsic::x86_sse2_psll_d;
6366 case Intrinsic::x86_sse2_pslli_q:
6367 NewIntNo = Intrinsic::x86_sse2_psll_q;
6369 case Intrinsic::x86_sse2_psrli_w:
6370 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6372 case Intrinsic::x86_sse2_psrli_d:
6373 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6375 case Intrinsic::x86_sse2_psrli_q:
6376 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6378 case Intrinsic::x86_sse2_psrai_w:
6379 NewIntNo = Intrinsic::x86_sse2_psra_w;
6381 case Intrinsic::x86_sse2_psrai_d:
6382 NewIntNo = Intrinsic::x86_sse2_psra_d;
6385 ShAmtVT = MVT::v2i32;
6387 case Intrinsic::x86_mmx_pslli_w:
6388 NewIntNo = Intrinsic::x86_mmx_psll_w;
6390 case Intrinsic::x86_mmx_pslli_d:
6391 NewIntNo = Intrinsic::x86_mmx_psll_d;
6393 case Intrinsic::x86_mmx_pslli_q:
6394 NewIntNo = Intrinsic::x86_mmx_psll_q;
6396 case Intrinsic::x86_mmx_psrli_w:
6397 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6399 case Intrinsic::x86_mmx_psrli_d:
6400 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6402 case Intrinsic::x86_mmx_psrli_q:
6403 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6405 case Intrinsic::x86_mmx_psrai_w:
6406 NewIntNo = Intrinsic::x86_mmx_psra_w;
6408 case Intrinsic::x86_mmx_psrai_d:
6409 NewIntNo = Intrinsic::x86_mmx_psra_d;
6411 default: abort(); // Can't reach here.
6416 MVT VT = Op.getValueType();
6417 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6418 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
6419 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6420 DAG.getConstant(NewIntNo, MVT::i32),
6421 Op.getOperand(1), ShAmt);
6426 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6427 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6428 DebugLoc dl = Op.getDebugLoc();
6431 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6433 DAG.getConstant(TD->getPointerSize(),
6434 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6435 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6436 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6441 // Just load the return address.
6442 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6443 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6444 RetAddrFI, NULL, 0);
6447 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6448 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6449 MFI->setFrameAddressIsTaken(true);
6450 MVT VT = Op.getValueType();
6451 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6452 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6453 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6454 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6456 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6460 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6461 SelectionDAG &DAG) {
6462 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6465 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6467 MachineFunction &MF = DAG.getMachineFunction();
6468 SDValue Chain = Op.getOperand(0);
6469 SDValue Offset = Op.getOperand(1);
6470 SDValue Handler = Op.getOperand(2);
6471 DebugLoc dl = Op.getDebugLoc();
6473 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6475 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6477 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6478 DAG.getIntPtrConstant(-TD->getPointerSize()));
6479 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6480 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6481 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6482 MF.getRegInfo().addLiveOut(StoreAddrReg);
6484 return DAG.getNode(X86ISD::EH_RETURN, dl,
6486 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6489 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6490 SelectionDAG &DAG) {
6491 SDValue Root = Op.getOperand(0);
6492 SDValue Trmp = Op.getOperand(1); // trampoline
6493 SDValue FPtr = Op.getOperand(2); // nested function
6494 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6495 DebugLoc dl = Op.getDebugLoc();
6497 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6499 const X86InstrInfo *TII =
6500 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6502 if (Subtarget->is64Bit()) {
6503 SDValue OutChains[6];
6505 // Large code-model.
6507 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6508 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6510 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6511 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6513 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6515 // Load the pointer to the nested function into R11.
6516 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6517 SDValue Addr = Trmp;
6518 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6521 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6522 DAG.getConstant(2, MVT::i64));
6523 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6525 // Load the 'nest' parameter value into R10.
6526 // R10 is specified in X86CallingConv.td
6527 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6528 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6529 DAG.getConstant(10, MVT::i64));
6530 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6531 Addr, TrmpAddr, 10);
6533 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6534 DAG.getConstant(12, MVT::i64));
6535 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6537 // Jump to the nested function.
6538 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6539 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6540 DAG.getConstant(20, MVT::i64));
6541 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6542 Addr, TrmpAddr, 20);
6544 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6545 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6546 DAG.getConstant(22, MVT::i64));
6547 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6551 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6552 return DAG.getMergeValues(Ops, 2, dl);
6554 const Function *Func =
6555 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6556 unsigned CC = Func->getCallingConv();
6561 assert(0 && "Unsupported calling convention");
6562 case CallingConv::C:
6563 case CallingConv::X86_StdCall: {
6564 // Pass 'nest' parameter in ECX.
6565 // Must be kept in sync with X86CallingConv.td
6568 // Check that ECX wasn't needed by an 'inreg' parameter.
6569 const FunctionType *FTy = Func->getFunctionType();
6570 const AttrListPtr &Attrs = Func->getAttributes();
6572 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6573 unsigned InRegCount = 0;
6576 for (FunctionType::param_iterator I = FTy->param_begin(),
6577 E = FTy->param_end(); I != E; ++I, ++Idx)
6578 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6579 // FIXME: should only count parameters that are lowered to integers.
6580 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6582 if (InRegCount > 2) {
6583 cerr << "Nest register in use - reduce number of inreg parameters!\n";
6589 case CallingConv::X86_FastCall:
6590 case CallingConv::Fast:
6591 // Pass 'nest' parameter in EAX.
6592 // Must be kept in sync with X86CallingConv.td
6597 SDValue OutChains[4];
6600 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6601 DAG.getConstant(10, MVT::i32));
6602 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6604 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6605 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6606 OutChains[0] = DAG.getStore(Root, dl,
6607 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6610 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6611 DAG.getConstant(1, MVT::i32));
6612 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6614 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6615 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6616 DAG.getConstant(5, MVT::i32));
6617 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6618 TrmpAddr, 5, false, 1);
6620 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6621 DAG.getConstant(6, MVT::i32));
6622 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6625 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6626 return DAG.getMergeValues(Ops, 2, dl);
6630 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6632 The rounding mode is in bits 11:10 of FPSR, and has the following
6639 FLT_ROUNDS, on the other hand, expects the following:
6646 To perform the conversion, we do:
6647 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6650 MachineFunction &MF = DAG.getMachineFunction();
6651 const TargetMachine &TM = MF.getTarget();
6652 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6653 unsigned StackAlignment = TFI.getStackAlignment();
6654 MVT VT = Op.getValueType();
6655 DebugLoc dl = Op.getDebugLoc();
6657 // Save FP Control Word to stack slot
6658 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6659 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6661 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6662 DAG.getEntryNode(), StackSlot);
6664 // Load FP Control Word from stack slot
6665 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6667 // Transform as necessary
6669 DAG.getNode(ISD::SRL, dl, MVT::i16,
6670 DAG.getNode(ISD::AND, dl, MVT::i16,
6671 CWD, DAG.getConstant(0x800, MVT::i16)),
6672 DAG.getConstant(11, MVT::i8));
6674 DAG.getNode(ISD::SRL, dl, MVT::i16,
6675 DAG.getNode(ISD::AND, dl, MVT::i16,
6676 CWD, DAG.getConstant(0x400, MVT::i16)),
6677 DAG.getConstant(9, MVT::i8));
6680 DAG.getNode(ISD::AND, dl, MVT::i16,
6681 DAG.getNode(ISD::ADD, dl, MVT::i16,
6682 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6683 DAG.getConstant(1, MVT::i16)),
6684 DAG.getConstant(3, MVT::i16));
6687 return DAG.getNode((VT.getSizeInBits() < 16 ?
6688 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6691 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6692 MVT VT = Op.getValueType();
6694 unsigned NumBits = VT.getSizeInBits();
6695 DebugLoc dl = Op.getDebugLoc();
6697 Op = Op.getOperand(0);
6698 if (VT == MVT::i8) {
6699 // Zero extend to i32 since there is not an i8 bsr.
6701 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6704 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6705 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6706 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6708 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6709 SmallVector<SDValue, 4> Ops;
6711 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6712 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6713 Ops.push_back(Op.getValue(1));
6714 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6716 // Finally xor with NumBits-1.
6717 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6720 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6724 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6725 MVT VT = Op.getValueType();
6727 unsigned NumBits = VT.getSizeInBits();
6728 DebugLoc dl = Op.getDebugLoc();
6730 Op = Op.getOperand(0);
6731 if (VT == MVT::i8) {
6733 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6736 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6737 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6738 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
6740 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6741 SmallVector<SDValue, 4> Ops;
6743 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6744 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6745 Ops.push_back(Op.getValue(1));
6746 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6749 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6753 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6754 MVT VT = Op.getValueType();
6755 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6756 DebugLoc dl = Op.getDebugLoc();
6758 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6759 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6760 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6761 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6762 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6764 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6765 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6766 // return AloBlo + AloBhi + AhiBlo;
6768 SDValue A = Op.getOperand(0);
6769 SDValue B = Op.getOperand(1);
6771 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6772 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6773 A, DAG.getConstant(32, MVT::i32));
6774 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6775 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6776 B, DAG.getConstant(32, MVT::i32));
6777 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6778 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6780 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6781 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6783 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6784 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6786 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6787 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6788 AloBhi, DAG.getConstant(32, MVT::i32));
6789 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6790 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6791 AhiBlo, DAG.getConstant(32, MVT::i32));
6792 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
6793 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
6798 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6799 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6800 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6801 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6802 // has only one use.
6803 SDNode *N = Op.getNode();
6804 SDValue LHS = N->getOperand(0);
6805 SDValue RHS = N->getOperand(1);
6806 unsigned BaseOp = 0;
6808 DebugLoc dl = Op.getDebugLoc();
6810 switch (Op.getOpcode()) {
6811 default: assert(0 && "Unknown ovf instruction!");
6813 // A subtract of one will be selected as a INC. Note that INC doesn't
6814 // set CF, so we can't do this for UADDO.
6815 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6816 if (C->getAPIntValue() == 1) {
6817 BaseOp = X86ISD::INC;
6821 BaseOp = X86ISD::ADD;
6825 BaseOp = X86ISD::ADD;
6829 // A subtract of one will be selected as a DEC. Note that DEC doesn't
6830 // set CF, so we can't do this for USUBO.
6831 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6832 if (C->getAPIntValue() == 1) {
6833 BaseOp = X86ISD::DEC;
6837 BaseOp = X86ISD::SUB;
6841 BaseOp = X86ISD::SUB;
6845 BaseOp = X86ISD::SMUL;
6849 BaseOp = X86ISD::UMUL;
6854 // Also sets EFLAGS.
6855 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6856 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
6859 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
6860 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6862 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6866 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6867 MVT T = Op.getValueType();
6868 DebugLoc dl = Op.getDebugLoc();
6871 switch(T.getSimpleVT()) {
6873 assert(false && "Invalid value type!");
6874 case MVT::i8: Reg = X86::AL; size = 1; break;
6875 case MVT::i16: Reg = X86::AX; size = 2; break;
6876 case MVT::i32: Reg = X86::EAX; size = 4; break;
6878 assert(Subtarget->is64Bit() && "Node not type legal!");
6879 Reg = X86::RAX; size = 8;
6882 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
6883 Op.getOperand(2), SDValue());
6884 SDValue Ops[] = { cpIn.getValue(0),
6887 DAG.getTargetConstant(size, MVT::i8),
6889 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6890 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
6892 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
6896 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6897 SelectionDAG &DAG) {
6898 assert(Subtarget->is64Bit() && "Result not type legalized?");
6899 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6900 SDValue TheChain = Op.getOperand(0);
6901 DebugLoc dl = Op.getDebugLoc();
6902 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6903 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
6904 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
6906 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
6907 DAG.getConstant(32, MVT::i8));
6909 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
6912 return DAG.getMergeValues(Ops, 2, dl);
6915 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6916 SDNode *Node = Op.getNode();
6917 DebugLoc dl = Node->getDebugLoc();
6918 MVT T = Node->getValueType(0);
6919 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
6920 DAG.getConstant(0, T), Node->getOperand(2));
6921 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
6922 cast<AtomicSDNode>(Node)->getMemoryVT(),
6923 Node->getOperand(0),
6924 Node->getOperand(1), negOp,
6925 cast<AtomicSDNode>(Node)->getSrcValue(),
6926 cast<AtomicSDNode>(Node)->getAlignment());
6929 /// LowerOperation - Provide custom lowering hooks for some operations.
6931 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6932 switch (Op.getOpcode()) {
6933 default: assert(0 && "Should not custom lower this!");
6934 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6935 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
6936 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6937 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6938 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6939 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6940 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6941 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6942 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6943 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6944 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6945 case ISD::SHL_PARTS:
6946 case ISD::SRA_PARTS:
6947 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6948 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6949 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6950 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6951 case ISD::FABS: return LowerFABS(Op, DAG);
6952 case ISD::FNEG: return LowerFNEG(Op, DAG);
6953 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6954 case ISD::SETCC: return LowerSETCC(Op, DAG);
6955 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6956 case ISD::SELECT: return LowerSELECT(Op, DAG);
6957 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6958 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6959 case ISD::CALL: return LowerCALL(Op, DAG);
6960 case ISD::RET: return LowerRET(Op, DAG);
6961 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
6962 case ISD::VASTART: return LowerVASTART(Op, DAG);
6963 case ISD::VAARG: return LowerVAARG(Op, DAG);
6964 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6965 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6966 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6967 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6968 case ISD::FRAME_TO_ARGS_OFFSET:
6969 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6970 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6971 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6972 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6973 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6974 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6975 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6976 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
6982 case ISD::UMULO: return LowerXALUO(Op, DAG);
6983 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6987 void X86TargetLowering::
6988 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6989 SelectionDAG &DAG, unsigned NewOp) {
6990 MVT T = Node->getValueType(0);
6991 DebugLoc dl = Node->getDebugLoc();
6992 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6994 SDValue Chain = Node->getOperand(0);
6995 SDValue In1 = Node->getOperand(1);
6996 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6997 Node->getOperand(2), DAG.getIntPtrConstant(0));
6998 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6999 Node->getOperand(2), DAG.getIntPtrConstant(1));
7000 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
7001 // have a MemOperand. Pass the info through as a normal operand.
7002 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
7003 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
7004 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7005 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
7006 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7007 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7008 Results.push_back(Result.getValue(2));
7011 /// ReplaceNodeResults - Replace a node with an illegal result type
7012 /// with a new node built out of custom code.
7013 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7014 SmallVectorImpl<SDValue>&Results,
7015 SelectionDAG &DAG) {
7016 DebugLoc dl = N->getDebugLoc();
7017 switch (N->getOpcode()) {
7019 assert(false && "Do not know how to custom type legalize this operation!");
7021 case ISD::FP_TO_SINT: {
7022 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
7023 SDValue FIST = Vals.first, StackSlot = Vals.second;
7024 if (FIST.getNode() != 0) {
7025 MVT VT = N->getValueType(0);
7026 // Return a load from the stack slot.
7027 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
7031 case ISD::READCYCLECOUNTER: {
7032 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7033 SDValue TheChain = N->getOperand(0);
7034 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7035 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7037 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7039 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7040 SDValue Ops[] = { eax, edx };
7041 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7042 Results.push_back(edx.getValue(1));
7045 case ISD::ATOMIC_CMP_SWAP: {
7046 MVT T = N->getValueType(0);
7047 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7048 SDValue cpInL, cpInH;
7049 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7050 DAG.getConstant(0, MVT::i32));
7051 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7052 DAG.getConstant(1, MVT::i32));
7053 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7054 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7056 SDValue swapInL, swapInH;
7057 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7058 DAG.getConstant(0, MVT::i32));
7059 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7060 DAG.getConstant(1, MVT::i32));
7061 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7063 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7064 swapInL.getValue(1));
7065 SDValue Ops[] = { swapInH.getValue(0),
7067 swapInH.getValue(1) };
7068 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7069 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7070 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7071 MVT::i32, Result.getValue(1));
7072 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7073 MVT::i32, cpOutL.getValue(2));
7074 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7075 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7076 Results.push_back(cpOutH.getValue(1));
7079 case ISD::ATOMIC_LOAD_ADD:
7080 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7082 case ISD::ATOMIC_LOAD_AND:
7083 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7085 case ISD::ATOMIC_LOAD_NAND:
7086 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7088 case ISD::ATOMIC_LOAD_OR:
7089 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7091 case ISD::ATOMIC_LOAD_SUB:
7092 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7094 case ISD::ATOMIC_LOAD_XOR:
7095 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7097 case ISD::ATOMIC_SWAP:
7098 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7103 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7105 default: return NULL;
7106 case X86ISD::BSF: return "X86ISD::BSF";
7107 case X86ISD::BSR: return "X86ISD::BSR";
7108 case X86ISD::SHLD: return "X86ISD::SHLD";
7109 case X86ISD::SHRD: return "X86ISD::SHRD";
7110 case X86ISD::FAND: return "X86ISD::FAND";
7111 case X86ISD::FOR: return "X86ISD::FOR";
7112 case X86ISD::FXOR: return "X86ISD::FXOR";
7113 case X86ISD::FSRL: return "X86ISD::FSRL";
7114 case X86ISD::FILD: return "X86ISD::FILD";
7115 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7116 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7117 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7118 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7119 case X86ISD::FLD: return "X86ISD::FLD";
7120 case X86ISD::FST: return "X86ISD::FST";
7121 case X86ISD::CALL: return "X86ISD::CALL";
7122 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
7123 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7124 case X86ISD::BT: return "X86ISD::BT";
7125 case X86ISD::CMP: return "X86ISD::CMP";
7126 case X86ISD::COMI: return "X86ISD::COMI";
7127 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7128 case X86ISD::SETCC: return "X86ISD::SETCC";
7129 case X86ISD::CMOV: return "X86ISD::CMOV";
7130 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7131 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7132 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7133 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7134 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7135 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7136 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7137 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7138 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7139 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7140 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7141 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7142 case X86ISD::FMAX: return "X86ISD::FMAX";
7143 case X86ISD::FMIN: return "X86ISD::FMIN";
7144 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7145 case X86ISD::FRCP: return "X86ISD::FRCP";
7146 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7147 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
7148 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7149 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7150 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7151 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7152 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7153 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7154 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7155 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7156 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7157 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7158 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7159 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7160 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7161 case X86ISD::VSHL: return "X86ISD::VSHL";
7162 case X86ISD::VSRL: return "X86ISD::VSRL";
7163 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7164 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7165 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7166 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7167 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7168 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7169 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7170 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7171 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7172 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7173 case X86ISD::ADD: return "X86ISD::ADD";
7174 case X86ISD::SUB: return "X86ISD::SUB";
7175 case X86ISD::SMUL: return "X86ISD::SMUL";
7176 case X86ISD::UMUL: return "X86ISD::UMUL";
7177 case X86ISD::INC: return "X86ISD::INC";
7178 case X86ISD::DEC: return "X86ISD::DEC";
7182 // isLegalAddressingMode - Return true if the addressing mode represented
7183 // by AM is legal for this target, for a load/store of the specified type.
7184 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7185 const Type *Ty) const {
7186 // X86 supports extremely general addressing modes.
7188 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7189 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
7193 // We can only fold this if we don't need an extra load.
7194 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
7196 // If BaseGV requires a register, we cannot also have a BaseReg.
7197 if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) &&
7201 // X86-64 only supports addr of globals in small code model.
7202 if (Subtarget->is64Bit()) {
7203 if (getTargetMachine().getCodeModel() != CodeModel::Small)
7205 // If lower 4G is not available, then we must use rip-relative addressing.
7206 if (AM.BaseOffs || AM.Scale > 1)
7217 // These scales always work.
7222 // These scales are formed with basereg+scalereg. Only accept if there is
7227 default: // Other stuff never works.
7235 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7236 if (!Ty1->isInteger() || !Ty2->isInteger())
7238 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7239 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7240 if (NumBits1 <= NumBits2)
7242 return Subtarget->is64Bit() || NumBits1 < 64;
7245 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
7246 if (!VT1.isInteger() || !VT2.isInteger())
7248 unsigned NumBits1 = VT1.getSizeInBits();
7249 unsigned NumBits2 = VT2.getSizeInBits();
7250 if (NumBits1 <= NumBits2)
7252 return Subtarget->is64Bit() || NumBits1 < 64;
7255 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7256 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7257 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7258 /// are assumed to be legal.
7260 X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
7261 // Only do shuffles on 128-bit vector types for now.
7262 // FIXME: pshufb, blends
7263 if (VT.getSizeInBits() == 64) return false;
7264 return (Mask.getNode()->getNumOperands() <= 4 ||
7265 isIdentityMask(Mask.getNode()) ||
7266 isIdentityMask(Mask.getNode(), true) ||
7267 isSplatMask(Mask.getNode()) ||
7268 X86::isPSHUFHWMask(Mask.getNode()) ||
7269 X86::isPSHUFLWMask(Mask.getNode()) ||
7270 X86::isUNPCKLMask(Mask.getNode()) ||
7271 X86::isUNPCKHMask(Mask.getNode()) ||
7272 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
7273 X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
7277 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
7278 MVT EVT, SelectionDAG &DAG) const {
7279 unsigned NumElts = BVOps.size();
7280 // Only do shuffles on 128-bit vector types for now.
7281 if (EVT.getSizeInBits() * NumElts == 64) return false;
7282 if (NumElts == 2) return true;
7284 return (isMOVLMask(&BVOps[0], 4) ||
7285 isCommutedMOVL(&BVOps[0], 4, true) ||
7286 isSHUFPMask(&BVOps[0], 4) ||
7287 isCommutedSHUFP(&BVOps[0], 4));
7292 //===----------------------------------------------------------------------===//
7293 // X86 Scheduler Hooks
7294 //===----------------------------------------------------------------------===//
7296 // private utility function
7298 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7299 MachineBasicBlock *MBB,
7307 TargetRegisterClass *RC,
7308 bool invSrc) const {
7309 // For the atomic bitwise operator, we generate
7312 // ld t1 = [bitinstr.addr]
7313 // op t2 = t1, [bitinstr.val]
7315 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7317 // fallthrough -->nextMBB
7318 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7319 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7320 MachineFunction::iterator MBBIter = MBB;
7323 /// First build the CFG
7324 MachineFunction *F = MBB->getParent();
7325 MachineBasicBlock *thisMBB = MBB;
7326 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7327 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7328 F->insert(MBBIter, newMBB);
7329 F->insert(MBBIter, nextMBB);
7331 // Move all successors to thisMBB to nextMBB
7332 nextMBB->transferSuccessors(thisMBB);
7334 // Update thisMBB to fall through to newMBB
7335 thisMBB->addSuccessor(newMBB);
7337 // newMBB jumps to itself and fall through to nextMBB
7338 newMBB->addSuccessor(nextMBB);
7339 newMBB->addSuccessor(newMBB);
7341 // Insert instructions into newMBB based on incoming instruction
7342 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7343 "unexpected number of operands");
7344 DebugLoc dl = bInstr->getDebugLoc();
7345 MachineOperand& destOper = bInstr->getOperand(0);
7346 MachineOperand* argOpers[2 + X86AddrNumOperands];
7347 int numArgs = bInstr->getNumOperands() - 1;
7348 for (int i=0; i < numArgs; ++i)
7349 argOpers[i] = &bInstr->getOperand(i+1);
7351 // x86 address has 4 operands: base, index, scale, and displacement
7352 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7353 int valArgIndx = lastAddrIndx + 1;
7355 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7356 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7357 for (int i=0; i <= lastAddrIndx; ++i)
7358 (*MIB).addOperand(*argOpers[i]);
7360 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7362 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7367 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7368 assert((argOpers[valArgIndx]->isReg() ||
7369 argOpers[valArgIndx]->isImm()) &&
7371 if (argOpers[valArgIndx]->isReg())
7372 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7374 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7376 (*MIB).addOperand(*argOpers[valArgIndx]);
7378 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7381 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7382 for (int i=0; i <= lastAddrIndx; ++i)
7383 (*MIB).addOperand(*argOpers[i]);
7385 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7386 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7388 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7392 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7394 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7398 // private utility function: 64 bit atomics on 32 bit host.
7400 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7401 MachineBasicBlock *MBB,
7406 bool invSrc) const {
7407 // For the atomic bitwise operator, we generate
7408 // thisMBB (instructions are in pairs, except cmpxchg8b)
7409 // ld t1,t2 = [bitinstr.addr]
7411 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7412 // op t5, t6 <- out1, out2, [bitinstr.val]
7413 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7414 // mov ECX, EBX <- t5, t6
7415 // mov EAX, EDX <- t1, t2
7416 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7417 // mov t3, t4 <- EAX, EDX
7419 // result in out1, out2
7420 // fallthrough -->nextMBB
7422 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7423 const unsigned LoadOpc = X86::MOV32rm;
7424 const unsigned copyOpc = X86::MOV32rr;
7425 const unsigned NotOpc = X86::NOT32r;
7426 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7427 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7428 MachineFunction::iterator MBBIter = MBB;
7431 /// First build the CFG
7432 MachineFunction *F = MBB->getParent();
7433 MachineBasicBlock *thisMBB = MBB;
7434 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7435 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7436 F->insert(MBBIter, newMBB);
7437 F->insert(MBBIter, nextMBB);
7439 // Move all successors to thisMBB to nextMBB
7440 nextMBB->transferSuccessors(thisMBB);
7442 // Update thisMBB to fall through to newMBB
7443 thisMBB->addSuccessor(newMBB);
7445 // newMBB jumps to itself and fall through to nextMBB
7446 newMBB->addSuccessor(nextMBB);
7447 newMBB->addSuccessor(newMBB);
7449 DebugLoc dl = bInstr->getDebugLoc();
7450 // Insert instructions into newMBB based on incoming instruction
7451 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7452 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7453 "unexpected number of operands");
7454 MachineOperand& dest1Oper = bInstr->getOperand(0);
7455 MachineOperand& dest2Oper = bInstr->getOperand(1);
7456 MachineOperand* argOpers[2 + X86AddrNumOperands];
7457 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7458 argOpers[i] = &bInstr->getOperand(i+2);
7460 // x86 address has 4 operands: base, index, scale, and displacement
7461 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7463 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7464 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7465 for (int i=0; i <= lastAddrIndx; ++i)
7466 (*MIB).addOperand(*argOpers[i]);
7467 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7468 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7469 // add 4 to displacement.
7470 for (int i=0; i <= lastAddrIndx-1; ++i)
7471 (*MIB).addOperand(*argOpers[i]);
7472 MachineOperand newOp3 = *(argOpers[3]);
7474 newOp3.setImm(newOp3.getImm()+4);
7476 newOp3.setOffset(newOp3.getOffset()+4);
7477 (*MIB).addOperand(newOp3);
7479 // t3/4 are defined later, at the bottom of the loop
7480 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7481 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7482 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7483 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7484 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7485 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7487 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7488 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7490 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7491 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7497 int valArgIndx = lastAddrIndx + 1;
7498 assert((argOpers[valArgIndx]->isReg() ||
7499 argOpers[valArgIndx]->isImm()) &&
7501 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7502 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7503 if (argOpers[valArgIndx]->isReg())
7504 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7506 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7507 if (regOpcL != X86::MOV32rr)
7509 (*MIB).addOperand(*argOpers[valArgIndx]);
7510 assert(argOpers[valArgIndx + 1]->isReg() ==
7511 argOpers[valArgIndx]->isReg());
7512 assert(argOpers[valArgIndx + 1]->isImm() ==
7513 argOpers[valArgIndx]->isImm());
7514 if (argOpers[valArgIndx + 1]->isReg())
7515 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7517 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7518 if (regOpcH != X86::MOV32rr)
7520 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7522 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7524 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7527 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7529 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7532 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7533 for (int i=0; i <= lastAddrIndx; ++i)
7534 (*MIB).addOperand(*argOpers[i]);
7536 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7537 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7539 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7540 MIB.addReg(X86::EAX);
7541 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7542 MIB.addReg(X86::EDX);
7545 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7547 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7551 // private utility function
7553 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7554 MachineBasicBlock *MBB,
7555 unsigned cmovOpc) const {
7556 // For the atomic min/max operator, we generate
7559 // ld t1 = [min/max.addr]
7560 // mov t2 = [min/max.val]
7562 // cmov[cond] t2 = t1
7564 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7566 // fallthrough -->nextMBB
7568 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7569 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7570 MachineFunction::iterator MBBIter = MBB;
7573 /// First build the CFG
7574 MachineFunction *F = MBB->getParent();
7575 MachineBasicBlock *thisMBB = MBB;
7576 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7577 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7578 F->insert(MBBIter, newMBB);
7579 F->insert(MBBIter, nextMBB);
7581 // Move all successors to thisMBB to nextMBB
7582 nextMBB->transferSuccessors(thisMBB);
7584 // Update thisMBB to fall through to newMBB
7585 thisMBB->addSuccessor(newMBB);
7587 // newMBB jumps to newMBB and fall through to nextMBB
7588 newMBB->addSuccessor(nextMBB);
7589 newMBB->addSuccessor(newMBB);
7591 DebugLoc dl = mInstr->getDebugLoc();
7592 // Insert instructions into newMBB based on incoming instruction
7593 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7594 "unexpected number of operands");
7595 MachineOperand& destOper = mInstr->getOperand(0);
7596 MachineOperand* argOpers[2 + X86AddrNumOperands];
7597 int numArgs = mInstr->getNumOperands() - 1;
7598 for (int i=0; i < numArgs; ++i)
7599 argOpers[i] = &mInstr->getOperand(i+1);
7601 // x86 address has 4 operands: base, index, scale, and displacement
7602 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7603 int valArgIndx = lastAddrIndx + 1;
7605 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7606 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7607 for (int i=0; i <= lastAddrIndx; ++i)
7608 (*MIB).addOperand(*argOpers[i]);
7610 // We only support register and immediate values
7611 assert((argOpers[valArgIndx]->isReg() ||
7612 argOpers[valArgIndx]->isImm()) &&
7615 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7616 if (argOpers[valArgIndx]->isReg())
7617 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7619 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7620 (*MIB).addOperand(*argOpers[valArgIndx]);
7622 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7625 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7630 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7631 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7635 // Cmp and exchange if none has modified the memory location
7636 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7637 for (int i=0; i <= lastAddrIndx; ++i)
7638 (*MIB).addOperand(*argOpers[i]);
7640 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7641 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
7643 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7644 MIB.addReg(X86::EAX);
7647 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7649 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7655 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7656 MachineBasicBlock *BB) const {
7657 DebugLoc dl = MI->getDebugLoc();
7658 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7659 switch (MI->getOpcode()) {
7660 default: assert(false && "Unexpected instr type to insert");
7661 case X86::CMOV_V1I64:
7662 case X86::CMOV_FR32:
7663 case X86::CMOV_FR64:
7664 case X86::CMOV_V4F32:
7665 case X86::CMOV_V2F64:
7666 case X86::CMOV_V2I64: {
7667 // To "insert" a SELECT_CC instruction, we actually have to insert the
7668 // diamond control-flow pattern. The incoming instruction knows the
7669 // destination vreg to set, the condition code register to branch on, the
7670 // true/false values to select between, and a branch opcode to use.
7671 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7672 MachineFunction::iterator It = BB;
7678 // cmpTY ccX, r1, r2
7680 // fallthrough --> copy0MBB
7681 MachineBasicBlock *thisMBB = BB;
7682 MachineFunction *F = BB->getParent();
7683 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7684 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7686 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7687 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
7688 F->insert(It, copy0MBB);
7689 F->insert(It, sinkMBB);
7690 // Update machine-CFG edges by transferring all successors of the current
7691 // block to the new block which will contain the Phi node for the select.
7692 sinkMBB->transferSuccessors(BB);
7694 // Add the true and fallthrough blocks as its successors.
7695 BB->addSuccessor(copy0MBB);
7696 BB->addSuccessor(sinkMBB);
7699 // %FalseValue = ...
7700 // # fallthrough to sinkMBB
7703 // Update machine-CFG edges
7704 BB->addSuccessor(sinkMBB);
7707 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7710 BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg())
7711 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7712 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7714 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7718 case X86::FP32_TO_INT16_IN_MEM:
7719 case X86::FP32_TO_INT32_IN_MEM:
7720 case X86::FP32_TO_INT64_IN_MEM:
7721 case X86::FP64_TO_INT16_IN_MEM:
7722 case X86::FP64_TO_INT32_IN_MEM:
7723 case X86::FP64_TO_INT64_IN_MEM:
7724 case X86::FP80_TO_INT16_IN_MEM:
7725 case X86::FP80_TO_INT32_IN_MEM:
7726 case X86::FP80_TO_INT64_IN_MEM: {
7727 // Change the floating point control register to use "round towards zero"
7728 // mode when truncating to an integer value.
7729 MachineFunction *F = BB->getParent();
7730 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7731 addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7733 // Load the old value of the high byte of the control word...
7735 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7736 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
7739 // Set the high part to be round to zero...
7740 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx)
7743 // Reload the modified control word now...
7744 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7746 // Restore the memory image of control word to original value
7747 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx)
7750 // Get the X86 opcode to use.
7752 switch (MI->getOpcode()) {
7753 default: assert(0 && "illegal opcode!");
7754 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7755 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7756 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7757 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7758 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7759 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7760 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7761 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7762 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7766 MachineOperand &Op = MI->getOperand(0);
7768 AM.BaseType = X86AddressMode::RegBase;
7769 AM.Base.Reg = Op.getReg();
7771 AM.BaseType = X86AddressMode::FrameIndexBase;
7772 AM.Base.FrameIndex = Op.getIndex();
7774 Op = MI->getOperand(1);
7776 AM.Scale = Op.getImm();
7777 Op = MI->getOperand(2);
7779 AM.IndexReg = Op.getImm();
7780 Op = MI->getOperand(3);
7781 if (Op.isGlobal()) {
7782 AM.GV = Op.getGlobal();
7784 AM.Disp = Op.getImm();
7786 addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
7787 .addReg(MI->getOperand(4).getReg());
7789 // Reload the original control word now.
7790 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7792 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7795 case X86::ATOMAND32:
7796 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7797 X86::AND32ri, X86::MOV32rm,
7798 X86::LCMPXCHG32, X86::MOV32rr,
7799 X86::NOT32r, X86::EAX,
7800 X86::GR32RegisterClass);
7802 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7803 X86::OR32ri, X86::MOV32rm,
7804 X86::LCMPXCHG32, X86::MOV32rr,
7805 X86::NOT32r, X86::EAX,
7806 X86::GR32RegisterClass);
7807 case X86::ATOMXOR32:
7808 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7809 X86::XOR32ri, X86::MOV32rm,
7810 X86::LCMPXCHG32, X86::MOV32rr,
7811 X86::NOT32r, X86::EAX,
7812 X86::GR32RegisterClass);
7813 case X86::ATOMNAND32:
7814 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7815 X86::AND32ri, X86::MOV32rm,
7816 X86::LCMPXCHG32, X86::MOV32rr,
7817 X86::NOT32r, X86::EAX,
7818 X86::GR32RegisterClass, true);
7819 case X86::ATOMMIN32:
7820 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7821 case X86::ATOMMAX32:
7822 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7823 case X86::ATOMUMIN32:
7824 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7825 case X86::ATOMUMAX32:
7826 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7828 case X86::ATOMAND16:
7829 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7830 X86::AND16ri, X86::MOV16rm,
7831 X86::LCMPXCHG16, X86::MOV16rr,
7832 X86::NOT16r, X86::AX,
7833 X86::GR16RegisterClass);
7835 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7836 X86::OR16ri, X86::MOV16rm,
7837 X86::LCMPXCHG16, X86::MOV16rr,
7838 X86::NOT16r, X86::AX,
7839 X86::GR16RegisterClass);
7840 case X86::ATOMXOR16:
7841 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7842 X86::XOR16ri, X86::MOV16rm,
7843 X86::LCMPXCHG16, X86::MOV16rr,
7844 X86::NOT16r, X86::AX,
7845 X86::GR16RegisterClass);
7846 case X86::ATOMNAND16:
7847 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7848 X86::AND16ri, X86::MOV16rm,
7849 X86::LCMPXCHG16, X86::MOV16rr,
7850 X86::NOT16r, X86::AX,
7851 X86::GR16RegisterClass, true);
7852 case X86::ATOMMIN16:
7853 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7854 case X86::ATOMMAX16:
7855 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7856 case X86::ATOMUMIN16:
7857 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7858 case X86::ATOMUMAX16:
7859 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7862 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7863 X86::AND8ri, X86::MOV8rm,
7864 X86::LCMPXCHG8, X86::MOV8rr,
7865 X86::NOT8r, X86::AL,
7866 X86::GR8RegisterClass);
7868 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7869 X86::OR8ri, X86::MOV8rm,
7870 X86::LCMPXCHG8, X86::MOV8rr,
7871 X86::NOT8r, X86::AL,
7872 X86::GR8RegisterClass);
7874 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7875 X86::XOR8ri, X86::MOV8rm,
7876 X86::LCMPXCHG8, X86::MOV8rr,
7877 X86::NOT8r, X86::AL,
7878 X86::GR8RegisterClass);
7879 case X86::ATOMNAND8:
7880 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7881 X86::AND8ri, X86::MOV8rm,
7882 X86::LCMPXCHG8, X86::MOV8rr,
7883 X86::NOT8r, X86::AL,
7884 X86::GR8RegisterClass, true);
7885 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7886 // This group is for 64-bit host.
7887 case X86::ATOMAND64:
7888 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7889 X86::AND64ri32, X86::MOV64rm,
7890 X86::LCMPXCHG64, X86::MOV64rr,
7891 X86::NOT64r, X86::RAX,
7892 X86::GR64RegisterClass);
7894 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7895 X86::OR64ri32, X86::MOV64rm,
7896 X86::LCMPXCHG64, X86::MOV64rr,
7897 X86::NOT64r, X86::RAX,
7898 X86::GR64RegisterClass);
7899 case X86::ATOMXOR64:
7900 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
7901 X86::XOR64ri32, X86::MOV64rm,
7902 X86::LCMPXCHG64, X86::MOV64rr,
7903 X86::NOT64r, X86::RAX,
7904 X86::GR64RegisterClass);
7905 case X86::ATOMNAND64:
7906 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7907 X86::AND64ri32, X86::MOV64rm,
7908 X86::LCMPXCHG64, X86::MOV64rr,
7909 X86::NOT64r, X86::RAX,
7910 X86::GR64RegisterClass, true);
7911 case X86::ATOMMIN64:
7912 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7913 case X86::ATOMMAX64:
7914 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7915 case X86::ATOMUMIN64:
7916 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7917 case X86::ATOMUMAX64:
7918 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
7920 // This group does 64-bit operations on a 32-bit host.
7921 case X86::ATOMAND6432:
7922 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7923 X86::AND32rr, X86::AND32rr,
7924 X86::AND32ri, X86::AND32ri,
7926 case X86::ATOMOR6432:
7927 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7928 X86::OR32rr, X86::OR32rr,
7929 X86::OR32ri, X86::OR32ri,
7931 case X86::ATOMXOR6432:
7932 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7933 X86::XOR32rr, X86::XOR32rr,
7934 X86::XOR32ri, X86::XOR32ri,
7936 case X86::ATOMNAND6432:
7937 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7938 X86::AND32rr, X86::AND32rr,
7939 X86::AND32ri, X86::AND32ri,
7941 case X86::ATOMADD6432:
7942 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7943 X86::ADD32rr, X86::ADC32rr,
7944 X86::ADD32ri, X86::ADC32ri,
7946 case X86::ATOMSUB6432:
7947 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7948 X86::SUB32rr, X86::SBB32rr,
7949 X86::SUB32ri, X86::SBB32ri,
7951 case X86::ATOMSWAP6432:
7952 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7953 X86::MOV32rr, X86::MOV32rr,
7954 X86::MOV32ri, X86::MOV32ri,
7959 //===----------------------------------------------------------------------===//
7960 // X86 Optimization Hooks
7961 //===----------------------------------------------------------------------===//
7963 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7967 const SelectionDAG &DAG,
7968 unsigned Depth) const {
7969 unsigned Opc = Op.getOpcode();
7970 assert((Opc >= ISD::BUILTIN_OP_END ||
7971 Opc == ISD::INTRINSIC_WO_CHAIN ||
7972 Opc == ISD::INTRINSIC_W_CHAIN ||
7973 Opc == ISD::INTRINSIC_VOID) &&
7974 "Should use MaskedValueIsZero if you don't know whether Op"
7975 " is a target node!");
7977 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7986 // These nodes' second result is a boolean.
7987 if (Op.getResNo() == 0)
7991 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7992 Mask.getBitWidth() - 1);
7997 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7998 /// node is a GlobalAddress + offset.
7999 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8000 GlobalValue* &GA, int64_t &Offset) const{
8001 if (N->getOpcode() == X86ISD::Wrapper) {
8002 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8003 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8004 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8008 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8011 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
8012 const TargetLowering &TLI) {
8015 if (TLI.isGAPlusOffset(Base, GV, Offset))
8016 return (GV->getAlignment() >= N && (Offset % N) == 0);
8017 // DAG combine handles the stack object case.
8021 static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
8022 unsigned NumElems, MVT EVT,
8024 SelectionDAG &DAG, MachineFrameInfo *MFI,
8025 const TargetLowering &TLI) {
8027 for (unsigned i = 0; i < NumElems; ++i) {
8028 SDValue Idx = PermMask.getOperand(i);
8029 if (Idx.getOpcode() == ISD::UNDEF) {
8035 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8036 if (!Elt.getNode() ||
8037 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8040 Base = Elt.getNode();
8041 if (Base->getOpcode() == ISD::UNDEF)
8045 if (Elt.getOpcode() == ISD::UNDEF)
8048 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
8049 EVT.getSizeInBits()/8, i, MFI))
8055 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8056 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8057 /// if the load addresses are consecutive, non-overlapping, and in the right
8059 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8060 const TargetLowering &TLI) {
8061 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8062 DebugLoc dl = N->getDebugLoc();
8063 MVT VT = N->getValueType(0);
8064 MVT EVT = VT.getVectorElementType();
8065 SDValue PermMask = N->getOperand(2);
8066 unsigned NumElems = PermMask.getNumOperands();
8067 SDNode *Base = NULL;
8068 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
8072 LoadSDNode *LD = cast<LoadSDNode>(Base);
8073 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
8074 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8075 LD->getSrcValue(), LD->getSrcValueOffset(),
8077 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8078 LD->getSrcValue(), LD->getSrcValueOffset(),
8079 LD->isVolatile(), LD->getAlignment());
8082 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
8083 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
8084 TargetLowering::DAGCombinerInfo &DCI,
8085 const X86Subtarget *Subtarget,
8086 const TargetLowering &TLI) {
8087 unsigned NumOps = N->getNumOperands();
8088 DebugLoc dl = N->getDebugLoc();
8090 // Ignore single operand BUILD_VECTOR.
8094 MVT VT = N->getValueType(0);
8095 MVT EVT = VT.getVectorElementType();
8096 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
8097 // We are looking for load i64 and zero extend. We want to transform
8098 // it before legalizer has a chance to expand it. Also look for i64
8099 // BUILD_PAIR bit casted to f64.
8101 // This must be an insertion into a zero vector.
8102 SDValue HighElt = N->getOperand(1);
8103 if (!isZeroNode(HighElt))
8106 // Value must be a load.
8107 SDNode *Base = N->getOperand(0).getNode();
8108 if (!isa<LoadSDNode>(Base)) {
8109 if (Base->getOpcode() != ISD::BIT_CONVERT)
8111 Base = Base->getOperand(0).getNode();
8112 if (!isa<LoadSDNode>(Base))
8116 // Transform it into VZEXT_LOAD addr.
8117 LoadSDNode *LD = cast<LoadSDNode>(Base);
8119 // Load must not be an extload.
8120 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
8123 // Load type should legal type so we don't have to legalize it.
8124 if (!TLI.isTypeLegal(VT))
8127 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
8128 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8129 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8130 TargetLowering::TargetLoweringOpt TLO(DAG);
8131 TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1));
8132 DCI.CommitTargetLoweringOpt(TLO);
8136 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8137 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8138 const X86Subtarget *Subtarget) {
8139 DebugLoc DL = N->getDebugLoc();
8140 SDValue Cond = N->getOperand(0);
8141 // Get the LHS/RHS of the select.
8142 SDValue LHS = N->getOperand(1);
8143 SDValue RHS = N->getOperand(2);
8145 // If we have SSE[12] support, try to form min/max nodes.
8146 if (Subtarget->hasSSE2() &&
8147 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8148 Cond.getOpcode() == ISD::SETCC) {
8149 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8151 unsigned Opcode = 0;
8152 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8155 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
8158 if (!UnsafeFPMath) break;
8160 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
8162 Opcode = X86ISD::FMIN;
8165 case ISD::SETOGT: // (X > Y) ? X : Y -> max
8168 if (!UnsafeFPMath) break;
8170 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
8172 Opcode = X86ISD::FMAX;
8175 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8178 case ISD::SETOGT: // (X > Y) ? Y : X -> min
8181 if (!UnsafeFPMath) break;
8183 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
8185 Opcode = X86ISD::FMIN;
8188 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
8191 if (!UnsafeFPMath) break;
8193 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
8195 Opcode = X86ISD::FMAX;
8201 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8204 // If this is a select between two integer constants, try to do some
8206 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8207 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8208 // Don't do this for crazy integer types.
8209 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8210 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8211 // so that TrueC (the true value) is larger than FalseC.
8212 bool NeedsCondInvert = false;
8214 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8215 // Efficiently invertible.
8216 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8217 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8218 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8219 NeedsCondInvert = true;
8220 std::swap(TrueC, FalseC);
8223 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8224 if (FalseC->getAPIntValue() == 0 &&
8225 TrueC->getAPIntValue().isPowerOf2()) {
8226 if (NeedsCondInvert) // Invert the condition if needed.
8227 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8228 DAG.getConstant(1, Cond.getValueType()));
8230 // Zero extend the condition if needed.
8231 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8233 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8234 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8235 DAG.getConstant(ShAmt, MVT::i8));
8238 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8239 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8240 if (NeedsCondInvert) // Invert the condition if needed.
8241 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8242 DAG.getConstant(1, Cond.getValueType()));
8244 // Zero extend the condition if needed.
8245 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8246 FalseC->getValueType(0), Cond);
8247 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8248 SDValue(FalseC, 0));
8251 // Optimize cases that will turn into an LEA instruction. This requires
8252 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8253 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8254 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8255 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8257 bool isFastMultiplier = false;
8259 switch ((unsigned char)Diff) {
8261 case 1: // result = add base, cond
8262 case 2: // result = lea base( , cond*2)
8263 case 3: // result = lea base(cond, cond*2)
8264 case 4: // result = lea base( , cond*4)
8265 case 5: // result = lea base(cond, cond*4)
8266 case 8: // result = lea base( , cond*8)
8267 case 9: // result = lea base(cond, cond*8)
8268 isFastMultiplier = true;
8273 if (isFastMultiplier) {
8274 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8275 if (NeedsCondInvert) // Invert the condition if needed.
8276 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8277 DAG.getConstant(1, Cond.getValueType()));
8279 // Zero extend the condition if needed.
8280 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8282 // Scale the condition by the difference.
8284 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8285 DAG.getConstant(Diff, Cond.getValueType()));
8287 // Add the base if non-zero.
8288 if (FalseC->getAPIntValue() != 0)
8289 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8290 SDValue(FalseC, 0));
8300 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8301 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8302 TargetLowering::DAGCombinerInfo &DCI) {
8303 DebugLoc DL = N->getDebugLoc();
8305 // If the flag operand isn't dead, don't touch this CMOV.
8306 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8309 // If this is a select between two integer constants, try to do some
8310 // optimizations. Note that the operands are ordered the opposite of SELECT
8312 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8313 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8314 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8315 // larger than FalseC (the false value).
8316 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8318 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8319 CC = X86::GetOppositeBranchCondition(CC);
8320 std::swap(TrueC, FalseC);
8323 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8324 // This is efficient for any integer data type (including i8/i16) and
8326 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8327 SDValue Cond = N->getOperand(3);
8328 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8329 DAG.getConstant(CC, MVT::i8), Cond);
8331 // Zero extend the condition if needed.
8332 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8334 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8335 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8336 DAG.getConstant(ShAmt, MVT::i8));
8337 if (N->getNumValues() == 2) // Dead flag value?
8338 return DCI.CombineTo(N, Cond, SDValue());
8342 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8343 // for any integer data type, including i8/i16.
8344 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8345 SDValue Cond = N->getOperand(3);
8346 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8347 DAG.getConstant(CC, MVT::i8), Cond);
8349 // Zero extend the condition if needed.
8350 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8351 FalseC->getValueType(0), Cond);
8352 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8353 SDValue(FalseC, 0));
8355 if (N->getNumValues() == 2) // Dead flag value?
8356 return DCI.CombineTo(N, Cond, SDValue());
8360 // Optimize cases that will turn into an LEA instruction. This requires
8361 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8362 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8363 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8364 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8366 bool isFastMultiplier = false;
8368 switch ((unsigned char)Diff) {
8370 case 1: // result = add base, cond
8371 case 2: // result = lea base( , cond*2)
8372 case 3: // result = lea base(cond, cond*2)
8373 case 4: // result = lea base( , cond*4)
8374 case 5: // result = lea base(cond, cond*4)
8375 case 8: // result = lea base( , cond*8)
8376 case 9: // result = lea base(cond, cond*8)
8377 isFastMultiplier = true;
8382 if (isFastMultiplier) {
8383 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8384 SDValue Cond = N->getOperand(3);
8385 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8386 DAG.getConstant(CC, MVT::i8), Cond);
8387 // Zero extend the condition if needed.
8388 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8390 // Scale the condition by the difference.
8392 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8393 DAG.getConstant(Diff, Cond.getValueType()));
8395 // Add the base if non-zero.
8396 if (FalseC->getAPIntValue() != 0)
8397 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8398 SDValue(FalseC, 0));
8399 if (N->getNumValues() == 2) // Dead flag value?
8400 return DCI.CombineTo(N, Cond, SDValue());
8410 /// PerformMulCombine - Optimize a single multiply with constant into two
8411 /// in order to implement it with two cheaper instructions, e.g.
8412 /// LEA + SHL, LEA + LEA.
8413 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8414 TargetLowering::DAGCombinerInfo &DCI) {
8415 if (DAG.getMachineFunction().
8416 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8419 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8422 MVT VT = N->getValueType(0);
8426 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8429 uint64_t MulAmt = C->getZExtValue();
8430 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8433 uint64_t MulAmt1 = 0;
8434 uint64_t MulAmt2 = 0;
8435 if ((MulAmt % 9) == 0) {
8437 MulAmt2 = MulAmt / 9;
8438 } else if ((MulAmt % 5) == 0) {
8440 MulAmt2 = MulAmt / 5;
8441 } else if ((MulAmt % 3) == 0) {
8443 MulAmt2 = MulAmt / 3;
8446 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8447 DebugLoc DL = N->getDebugLoc();
8449 if (isPowerOf2_64(MulAmt2) &&
8450 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8451 // If second multiplifer is pow2, issue it first. We want the multiply by
8452 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8454 std::swap(MulAmt1, MulAmt2);
8457 if (isPowerOf2_64(MulAmt1))
8458 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8459 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8461 NewMul = DAG.getNode(ISD::MUL, DL, VT, N->getOperand(0),
8462 DAG.getConstant(MulAmt1, VT));
8464 if (isPowerOf2_64(MulAmt2))
8465 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8466 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8468 NewMul = DAG.getNode(ISD::MUL, DL, VT, NewMul,
8469 DAG.getConstant(MulAmt2, VT));
8471 // Do not add new nodes to DAG combiner worklist.
8472 DCI.CombineTo(N, NewMul, false);
8478 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
8480 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
8481 const X86Subtarget *Subtarget) {
8482 // On X86 with SSE2 support, we can transform this to a vector shift if
8483 // all elements are shifted by the same amount. We can't do this in legalize
8484 // because the a constant vector is typically transformed to a constant pool
8485 // so we have no knowledge of the shift amount.
8486 if (!Subtarget->hasSSE2())
8489 MVT VT = N->getValueType(0);
8490 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
8493 SDValue ShAmtOp = N->getOperand(1);
8494 MVT EltVT = VT.getVectorElementType();
8495 DebugLoc DL = N->getDebugLoc();
8497 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
8498 unsigned NumElts = VT.getVectorNumElements();
8500 for (; i != NumElts; ++i) {
8501 SDValue Arg = ShAmtOp.getOperand(i);
8502 if (Arg.getOpcode() == ISD::UNDEF) continue;
8506 for (; i != NumElts; ++i) {
8507 SDValue Arg = ShAmtOp.getOperand(i);
8508 if (Arg.getOpcode() == ISD::UNDEF) continue;
8509 if (Arg != BaseShAmt) {
8513 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
8514 isSplatMask(ShAmtOp.getOperand(2).getNode())) {
8515 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
8516 DAG.getIntPtrConstant(0));
8520 if (EltVT.bitsGT(MVT::i32))
8521 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
8522 else if (EltVT.bitsLT(MVT::i32))
8523 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt);
8525 // The shift amount is identical so we can do a vector shift.
8526 SDValue ValOp = N->getOperand(0);
8527 switch (N->getOpcode()) {
8529 assert(0 && "Unknown shift opcode!");
8532 if (VT == MVT::v2i64)
8533 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8534 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8536 if (VT == MVT::v4i32)
8537 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8538 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8540 if (VT == MVT::v8i16)
8541 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8542 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8546 if (VT == MVT::v4i32)
8547 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8548 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
8550 if (VT == MVT::v8i16)
8551 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8552 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
8556 if (VT == MVT::v2i64)
8557 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8558 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8560 if (VT == MVT::v4i32)
8561 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8562 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
8564 if (VT == MVT::v8i16)
8565 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8566 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
8573 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
8574 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
8575 const X86Subtarget *Subtarget) {
8576 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
8577 // the FP state in cases where an emms may be missing.
8578 // A preferable solution to the general problem is to figure out the right
8579 // places to insert EMMS. This qualifies as a quick hack.
8581 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
8582 StoreSDNode *St = cast<StoreSDNode>(N);
8583 MVT VT = St->getValue().getValueType();
8584 if (VT.getSizeInBits() != 64)
8587 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloat && Subtarget->hasSSE2();
8588 if ((VT.isVector() ||
8589 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
8590 isa<LoadSDNode>(St->getValue()) &&
8591 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
8592 St->getChain().hasOneUse() && !St->isVolatile()) {
8593 SDNode* LdVal = St->getValue().getNode();
8595 int TokenFactorIndex = -1;
8596 SmallVector<SDValue, 8> Ops;
8597 SDNode* ChainVal = St->getChain().getNode();
8598 // Must be a store of a load. We currently handle two cases: the load
8599 // is a direct child, and it's under an intervening TokenFactor. It is
8600 // possible to dig deeper under nested TokenFactors.
8601 if (ChainVal == LdVal)
8602 Ld = cast<LoadSDNode>(St->getChain());
8603 else if (St->getValue().hasOneUse() &&
8604 ChainVal->getOpcode() == ISD::TokenFactor) {
8605 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
8606 if (ChainVal->getOperand(i).getNode() == LdVal) {
8607 TokenFactorIndex = i;
8608 Ld = cast<LoadSDNode>(St->getValue());
8610 Ops.push_back(ChainVal->getOperand(i));
8614 if (!Ld || !ISD::isNormalLoad(Ld))
8617 // If this is not the MMX case, i.e. we are just turning i64 load/store
8618 // into f64 load/store, avoid the transformation if there are multiple
8619 // uses of the loaded value.
8620 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
8623 DebugLoc LdDL = Ld->getDebugLoc();
8624 DebugLoc StDL = N->getDebugLoc();
8625 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
8626 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
8628 if (Subtarget->is64Bit() || F64IsLegal) {
8629 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
8630 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
8631 Ld->getBasePtr(), Ld->getSrcValue(),
8632 Ld->getSrcValueOffset(), Ld->isVolatile(),
8633 Ld->getAlignment());
8634 SDValue NewChain = NewLd.getValue(1);
8635 if (TokenFactorIndex != -1) {
8636 Ops.push_back(NewChain);
8637 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8640 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
8641 St->getSrcValue(), St->getSrcValueOffset(),
8642 St->isVolatile(), St->getAlignment());
8645 // Otherwise, lower to two pairs of 32-bit loads / stores.
8646 SDValue LoAddr = Ld->getBasePtr();
8647 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
8648 DAG.getConstant(4, MVT::i32));
8650 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
8651 Ld->getSrcValue(), Ld->getSrcValueOffset(),
8652 Ld->isVolatile(), Ld->getAlignment());
8653 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
8654 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
8656 MinAlign(Ld->getAlignment(), 4));
8658 SDValue NewChain = LoLd.getValue(1);
8659 if (TokenFactorIndex != -1) {
8660 Ops.push_back(LoLd);
8661 Ops.push_back(HiLd);
8662 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8666 LoAddr = St->getBasePtr();
8667 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
8668 DAG.getConstant(4, MVT::i32));
8670 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
8671 St->getSrcValue(), St->getSrcValueOffset(),
8672 St->isVolatile(), St->getAlignment());
8673 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
8675 St->getSrcValueOffset() + 4,
8677 MinAlign(St->getAlignment(), 4));
8678 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
8683 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
8684 /// X86ISD::FXOR nodes.
8685 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
8686 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
8687 // F[X]OR(0.0, x) -> x
8688 // F[X]OR(x, 0.0) -> x
8689 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8690 if (C->getValueAPF().isPosZero())
8691 return N->getOperand(1);
8692 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8693 if (C->getValueAPF().isPosZero())
8694 return N->getOperand(0);
8698 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
8699 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
8700 // FAND(0.0, x) -> 0.0
8701 // FAND(x, 0.0) -> 0.0
8702 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8703 if (C->getValueAPF().isPosZero())
8704 return N->getOperand(0);
8705 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8706 if (C->getValueAPF().isPosZero())
8707 return N->getOperand(1);
8711 static SDValue PerformBTCombine(SDNode *N,
8713 TargetLowering::DAGCombinerInfo &DCI) {
8714 // BT ignores high bits in the bit index operand.
8715 SDValue Op1 = N->getOperand(1);
8716 if (Op1.hasOneUse()) {
8717 unsigned BitWidth = Op1.getValueSizeInBits();
8718 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
8719 APInt KnownZero, KnownOne;
8720 TargetLowering::TargetLoweringOpt TLO(DAG);
8721 TargetLowering &TLI = DAG.getTargetLoweringInfo();
8722 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
8723 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
8724 DCI.CommitTargetLoweringOpt(TLO);
8729 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
8730 DAGCombinerInfo &DCI) const {
8731 SelectionDAG &DAG = DCI.DAG;
8732 switch (N->getOpcode()) {
8734 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
8735 case ISD::BUILD_VECTOR:
8736 return PerformBuildVectorCombine(N, DAG, DCI, Subtarget, *this);
8737 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
8738 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
8739 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
8742 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
8743 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
8745 case X86ISD::FOR: return PerformFORCombine(N, DAG);
8746 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
8747 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
8753 //===----------------------------------------------------------------------===//
8754 // X86 Inline Assembly Support
8755 //===----------------------------------------------------------------------===//
8757 /// getConstraintType - Given a constraint letter, return the type of
8758 /// constraint it is for this target.
8759 X86TargetLowering::ConstraintType
8760 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
8761 if (Constraint.size() == 1) {
8762 switch (Constraint[0]) {
8774 return C_RegisterClass;
8782 return TargetLowering::getConstraintType(Constraint);
8785 /// LowerXConstraint - try to replace an X constraint, which matches anything,
8786 /// with another that has more specific requirements based on the type of the
8787 /// corresponding operand.
8788 const char *X86TargetLowering::
8789 LowerXConstraint(MVT ConstraintVT) const {
8790 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
8791 // 'f' like normal targets.
8792 if (ConstraintVT.isFloatingPoint()) {
8793 if (Subtarget->hasSSE2())
8795 if (Subtarget->hasSSE1())
8799 return TargetLowering::LowerXConstraint(ConstraintVT);
8802 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8803 /// vector. If it is invalid, don't add anything to Ops.
8804 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8807 std::vector<SDValue>&Ops,
8808 SelectionDAG &DAG) const {
8809 SDValue Result(0, 0);
8811 switch (Constraint) {
8814 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8815 if (C->getZExtValue() <= 31) {
8816 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8822 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8823 if (C->getZExtValue() <= 63) {
8824 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8830 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8831 if (C->getZExtValue() <= 255) {
8832 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8838 // 32-bit signed value
8839 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8840 const ConstantInt *CI = C->getConstantIntValue();
8841 if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) {
8842 // Widen to 64 bits here to get it sign extended.
8843 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
8846 // FIXME gcc accepts some relocatable values here too, but only in certain
8847 // memory models; it's complicated.
8852 // 32-bit unsigned value
8853 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8854 const ConstantInt *CI = C->getConstantIntValue();
8855 if (CI->isValueValidForType(Type::Int32Ty, C->getZExtValue())) {
8856 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8860 // FIXME gcc accepts some relocatable values here too, but only in certain
8861 // memory models; it's complicated.
8865 // Literal immediates are always ok.
8866 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
8867 // Widen to 64 bits here to get it sign extended.
8868 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
8872 // If we are in non-pic codegen mode, we allow the address of a global (with
8873 // an optional displacement) to be used with 'i'.
8874 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
8877 // Match either (GA) or (GA+C)
8879 Offset = GA->getOffset();
8880 } else if (Op.getOpcode() == ISD::ADD) {
8881 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8882 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
8884 Offset = GA->getOffset()+C->getZExtValue();
8886 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8887 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
8889 Offset = GA->getOffset()+C->getZExtValue();
8897 Op = LowerGlobalAddress(GA->getGlobal(), Op.getDebugLoc(),
8900 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
8906 // Otherwise, not valid for this mode.
8911 if (Result.getNode()) {
8912 Ops.push_back(Result);
8915 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
8919 std::vector<unsigned> X86TargetLowering::
8920 getRegClassForInlineAsmConstraint(const std::string &Constraint,
8922 if (Constraint.size() == 1) {
8923 // FIXME: not handling fp-stack yet!
8924 switch (Constraint[0]) { // GCC X86 Constraint Letters
8925 default: break; // Unknown constraint letter
8926 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
8929 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
8930 else if (VT == MVT::i16)
8931 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
8932 else if (VT == MVT::i8)
8933 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
8934 else if (VT == MVT::i64)
8935 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
8940 return std::vector<unsigned>();
8943 std::pair<unsigned, const TargetRegisterClass*>
8944 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8946 // First, see if this is a constraint that directly corresponds to an LLVM
8948 if (Constraint.size() == 1) {
8949 // GCC Constraint Letters
8950 switch (Constraint[0]) {
8952 case 'r': // GENERAL_REGS
8953 case 'R': // LEGACY_REGS
8954 case 'l': // INDEX_REGS
8956 return std::make_pair(0U, X86::GR8RegisterClass);
8958 return std::make_pair(0U, X86::GR16RegisterClass);
8959 if (VT == MVT::i32 || !Subtarget->is64Bit())
8960 return std::make_pair(0U, X86::GR32RegisterClass);
8961 return std::make_pair(0U, X86::GR64RegisterClass);
8962 case 'f': // FP Stack registers.
8963 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
8964 // value to the correct fpstack register class.
8965 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
8966 return std::make_pair(0U, X86::RFP32RegisterClass);
8967 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
8968 return std::make_pair(0U, X86::RFP64RegisterClass);
8969 return std::make_pair(0U, X86::RFP80RegisterClass);
8970 case 'y': // MMX_REGS if MMX allowed.
8971 if (!Subtarget->hasMMX()) break;
8972 return std::make_pair(0U, X86::VR64RegisterClass);
8973 case 'Y': // SSE_REGS if SSE2 allowed
8974 if (!Subtarget->hasSSE2()) break;
8976 case 'x': // SSE_REGS if SSE1 allowed
8977 if (!Subtarget->hasSSE1()) break;
8979 switch (VT.getSimpleVT()) {
8981 // Scalar SSE types.
8984 return std::make_pair(0U, X86::FR32RegisterClass);
8987 return std::make_pair(0U, X86::FR64RegisterClass);
8995 return std::make_pair(0U, X86::VR128RegisterClass);
9001 // Use the default implementation in TargetLowering to convert the register
9002 // constraint into a member of a register class.
9003 std::pair<unsigned, const TargetRegisterClass*> Res;
9004 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9006 // Not found as a standard register?
9007 if (Res.second == 0) {
9008 // GCC calls "st(0)" just plain "st".
9009 if (StringsEqualNoCase("{st}", Constraint)) {
9010 Res.first = X86::ST0;
9011 Res.second = X86::RFP80RegisterClass;
9013 // 'A' means EAX + EDX.
9014 if (Constraint == "A") {
9015 Res.first = X86::EAX;
9016 Res.second = X86::GRADRegisterClass;
9021 // Otherwise, check to see if this is a register class of the wrong value
9022 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9023 // turn into {ax},{dx}.
9024 if (Res.second->hasType(VT))
9025 return Res; // Correct type already, nothing to do.
9027 // All of the single-register GCC register classes map their values onto
9028 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
9029 // really want an 8-bit or 32-bit register, map to the appropriate register
9030 // class and return the appropriate register.
9031 if (Res.second == X86::GR16RegisterClass) {
9032 if (VT == MVT::i8) {
9033 unsigned DestReg = 0;
9034 switch (Res.first) {
9036 case X86::AX: DestReg = X86::AL; break;
9037 case X86::DX: DestReg = X86::DL; break;
9038 case X86::CX: DestReg = X86::CL; break;
9039 case X86::BX: DestReg = X86::BL; break;
9042 Res.first = DestReg;
9043 Res.second = Res.second = X86::GR8RegisterClass;
9045 } else if (VT == MVT::i32) {
9046 unsigned DestReg = 0;
9047 switch (Res.first) {
9049 case X86::AX: DestReg = X86::EAX; break;
9050 case X86::DX: DestReg = X86::EDX; break;
9051 case X86::CX: DestReg = X86::ECX; break;
9052 case X86::BX: DestReg = X86::EBX; break;
9053 case X86::SI: DestReg = X86::ESI; break;
9054 case X86::DI: DestReg = X86::EDI; break;
9055 case X86::BP: DestReg = X86::EBP; break;
9056 case X86::SP: DestReg = X86::ESP; break;
9059 Res.first = DestReg;
9060 Res.second = Res.second = X86::GR32RegisterClass;
9062 } else if (VT == MVT::i64) {
9063 unsigned DestReg = 0;
9064 switch (Res.first) {
9066 case X86::AX: DestReg = X86::RAX; break;
9067 case X86::DX: DestReg = X86::RDX; break;
9068 case X86::CX: DestReg = X86::RCX; break;
9069 case X86::BX: DestReg = X86::RBX; break;
9070 case X86::SI: DestReg = X86::RSI; break;
9071 case X86::DI: DestReg = X86::RDI; break;
9072 case X86::BP: DestReg = X86::RBP; break;
9073 case X86::SP: DestReg = X86::RSP; break;
9076 Res.first = DestReg;
9077 Res.second = Res.second = X86::GR64RegisterClass;
9080 } else if (Res.second == X86::FR32RegisterClass ||
9081 Res.second == X86::FR64RegisterClass ||
9082 Res.second == X86::VR128RegisterClass) {
9083 // Handle references to XMM physical registers that got mapped into the
9084 // wrong class. This can happen with constraints like {xmm0} where the
9085 // target independent register mapper will just pick the first match it can
9086 // find, ignoring the required type.
9088 Res.second = X86::FR32RegisterClass;
9089 else if (VT == MVT::f64)
9090 Res.second = X86::FR64RegisterClass;
9091 else if (X86::VR128RegisterClass->hasType(VT))
9092 Res.second = X86::VR128RegisterClass;
9098 //===----------------------------------------------------------------------===//
9099 // X86 Widen vector type
9100 //===----------------------------------------------------------------------===//
9102 /// getWidenVectorType: given a vector type, returns the type to widen
9103 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9104 /// If there is no vector type that we want to widen to, returns MVT::Other
9105 /// When and where to widen is target dependent based on the cost of
9106 /// scalarizing vs using the wider vector type.
9108 MVT X86TargetLowering::getWidenVectorType(MVT VT) const {
9109 assert(VT.isVector());
9110 if (isTypeLegal(VT))
9113 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9114 // type based on element type. This would speed up our search (though
9115 // it may not be worth it since the size of the list is relatively
9117 MVT EltVT = VT.getVectorElementType();
9118 unsigned NElts = VT.getVectorNumElements();
9120 // On X86, it make sense to widen any vector wider than 1
9124 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9125 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9126 MVT SVT = (MVT::SimpleValueType)nVT;
9128 if (isTypeLegal(SVT) &&
9129 SVT.getVectorElementType() == EltVT &&
9130 SVT.getVectorNumElements() > NElts)