1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/ADT/SmallSet.h"
41 #include "llvm/ADT/StringExtras.h"
44 // Forward declarations.
45 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
47 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
48 : TargetLowering(TM) {
49 Subtarget = &TM.getSubtarget<X86Subtarget>();
50 X86ScalarSSEf64 = Subtarget->hasSSE2();
51 X86ScalarSSEf32 = Subtarget->hasSSE1();
52 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
56 RegInfo = TM.getRegisterInfo();
58 // Set up the TargetLowering object.
60 // X86 is weird, it always uses i8 for shift amounts and setcc results.
61 setShiftAmountType(MVT::i8);
62 setSetCCResultContents(ZeroOrOneSetCCResult);
63 setSchedulingPreference(SchedulingForRegPressure);
64 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
65 setStackPointerRegisterToSaveRestore(X86StackPtr);
67 if (Subtarget->isTargetDarwin()) {
68 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(false);
70 setUseUnderscoreLongJmp(false);
71 } else if (Subtarget->isTargetMingw()) {
72 // MS runtime is weird: it exports _setjmp, but longjmp!
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(false);
76 setUseUnderscoreSetJmp(true);
77 setUseUnderscoreLongJmp(true);
80 // Set up the register classes.
81 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
82 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
83 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
84 if (Subtarget->is64Bit())
85 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
87 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
89 // We don't accept any truncstore of integer registers.
90 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
91 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
92 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
93 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
94 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
95 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
97 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
99 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
100 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
101 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
103 if (Subtarget->is64Bit()) {
104 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
105 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
108 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
109 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
111 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
114 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
116 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
117 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
118 // SSE has no i16 to fp conversion, only i32
119 if (X86ScalarSSEf32) {
120 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
121 // f32 and f64 cases are Legal, f80 case is not
122 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
124 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
125 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
128 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
129 // are Legal, f80 is custom lowered.
130 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
131 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
133 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
135 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
136 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
138 if (X86ScalarSSEf32) {
139 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
140 // f32 and f64 cases are Legal, f80 case is not
141 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
143 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
144 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
147 // Handle FP_TO_UINT by promoting the destination to a larger signed
149 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
150 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
151 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
153 if (Subtarget->is64Bit()) {
154 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
155 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
157 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
158 // Expand FP_TO_UINT into a select.
159 // FIXME: We would like to use a Custom expander here eventually to do
160 // the optimal thing for SSE vs. the default expansion in the legalizer.
161 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
163 // With SSE3 we can use fisttpll to convert to a signed i64.
164 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
167 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
168 if (!X86ScalarSSEf64) {
169 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
170 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
173 // Scalar integer divide and remainder are lowered to use operations that
174 // produce two results, to match the available instructions. This exposes
175 // the two-result form to trivial CSE, which is able to combine x/y and x%y
176 // into a single instruction.
178 // Scalar integer multiply-high is also lowered to use two-result
179 // operations, to match the available instructions. However, plain multiply
180 // (low) operations are left as Legal, as there are single-result
181 // instructions for this in x86. Using the two-result multiply instructions
182 // when both high and low results are needed must be arranged by dagcombine.
183 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
184 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
185 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
186 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
187 setOperationAction(ISD::SREM , MVT::i8 , Expand);
188 setOperationAction(ISD::UREM , MVT::i8 , Expand);
189 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
190 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
191 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
192 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
193 setOperationAction(ISD::SREM , MVT::i16 , Expand);
194 setOperationAction(ISD::UREM , MVT::i16 , Expand);
195 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
196 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
197 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
198 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
199 setOperationAction(ISD::SREM , MVT::i32 , Expand);
200 setOperationAction(ISD::UREM , MVT::i32 , Expand);
201 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
202 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
203 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
204 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
205 setOperationAction(ISD::SREM , MVT::i64 , Expand);
206 setOperationAction(ISD::UREM , MVT::i64 , Expand);
208 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
209 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
210 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
211 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
212 if (Subtarget->is64Bit())
213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
215 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
216 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
217 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
218 setOperationAction(ISD::FREM , MVT::f32 , Expand);
219 setOperationAction(ISD::FREM , MVT::f64 , Expand);
220 setOperationAction(ISD::FREM , MVT::f80 , Expand);
221 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
223 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
224 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
225 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
226 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
227 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
228 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
229 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
230 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
231 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
232 if (Subtarget->is64Bit()) {
233 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
234 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
235 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
238 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
239 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
241 // These should be promoted to a larger select which is supported.
242 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
243 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
244 // X86 wants to expand cmov itself.
245 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
246 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
247 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
248 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
249 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
250 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
251 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
252 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
253 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
254 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
255 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
258 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
260 // X86 ret instruction may pop stack.
261 setOperationAction(ISD::RET , MVT::Other, Custom);
262 if (!Subtarget->is64Bit())
263 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
266 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
267 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
268 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
269 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
270 if (Subtarget->is64Bit())
271 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
272 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
273 if (Subtarget->is64Bit()) {
274 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
275 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
276 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
277 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
279 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
280 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
281 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
282 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
283 if (Subtarget->is64Bit()) {
284 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
285 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
286 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
289 if (Subtarget->hasSSE1())
290 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
292 if (!Subtarget->hasSSE2())
293 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
295 // Expand certain atomics
296 setOperationAction(ISD::ATOMIC_LCS , MVT::i8, Custom);
297 setOperationAction(ISD::ATOMIC_LCS , MVT::i16, Custom);
298 setOperationAction(ISD::ATOMIC_LCS , MVT::i32, Custom);
299 setOperationAction(ISD::ATOMIC_LCS , MVT::i64, Custom);
300 setOperationAction(ISD::ATOMIC_LSS , MVT::i32, Expand);
302 // Use the default ISD::LOCATION, ISD::DECLARE expansion.
303 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
304 // FIXME - use subtarget debug flags
305 if (!Subtarget->isTargetDarwin() &&
306 !Subtarget->isTargetELF() &&
307 !Subtarget->isTargetCygMing())
308 setOperationAction(ISD::LABEL, MVT::Other, Expand);
310 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
311 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
312 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
313 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
314 if (Subtarget->is64Bit()) {
316 setExceptionPointerRegister(X86::RAX);
317 setExceptionSelectorRegister(X86::RDX);
319 setExceptionPointerRegister(X86::EAX);
320 setExceptionSelectorRegister(X86::EDX);
322 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
324 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
326 setOperationAction(ISD::TRAP, MVT::Other, Legal);
328 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
329 setOperationAction(ISD::VASTART , MVT::Other, Custom);
330 setOperationAction(ISD::VAEND , MVT::Other, Expand);
331 if (Subtarget->is64Bit()) {
332 setOperationAction(ISD::VAARG , MVT::Other, Custom);
333 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
335 setOperationAction(ISD::VAARG , MVT::Other, Expand);
336 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
339 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
340 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
341 if (Subtarget->is64Bit())
342 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
343 if (Subtarget->isTargetCygMing())
344 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
346 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
348 if (X86ScalarSSEf64) {
349 // f32 and f64 use SSE.
350 // Set up the FP register classes.
351 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
352 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
354 // Use ANDPD to simulate FABS.
355 setOperationAction(ISD::FABS , MVT::f64, Custom);
356 setOperationAction(ISD::FABS , MVT::f32, Custom);
358 // Use XORP to simulate FNEG.
359 setOperationAction(ISD::FNEG , MVT::f64, Custom);
360 setOperationAction(ISD::FNEG , MVT::f32, Custom);
362 // Use ANDPD and ORPD to simulate FCOPYSIGN.
363 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
364 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
366 // We don't support sin/cos/fmod
367 setOperationAction(ISD::FSIN , MVT::f64, Expand);
368 setOperationAction(ISD::FCOS , MVT::f64, Expand);
369 setOperationAction(ISD::FSIN , MVT::f32, Expand);
370 setOperationAction(ISD::FCOS , MVT::f32, Expand);
372 // Expand FP immediates into loads from the stack, except for the special
374 addLegalFPImmediate(APFloat(+0.0)); // xorpd
375 addLegalFPImmediate(APFloat(+0.0f)); // xorps
377 // Floating truncations from f80 and extensions to f80 go through memory.
378 // If optimizing, we lie about this though and handle it in
379 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
381 setConvertAction(MVT::f32, MVT::f80, Expand);
382 setConvertAction(MVT::f64, MVT::f80, Expand);
383 setConvertAction(MVT::f80, MVT::f32, Expand);
384 setConvertAction(MVT::f80, MVT::f64, Expand);
386 } else if (X86ScalarSSEf32) {
387 // Use SSE for f32, x87 for f64.
388 // Set up the FP register classes.
389 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
390 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
392 // Use ANDPS to simulate FABS.
393 setOperationAction(ISD::FABS , MVT::f32, Custom);
395 // Use XORP to simulate FNEG.
396 setOperationAction(ISD::FNEG , MVT::f32, Custom);
398 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
400 // Use ANDPS and ORPS to simulate FCOPYSIGN.
401 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
402 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
404 // We don't support sin/cos/fmod
405 setOperationAction(ISD::FSIN , MVT::f32, Expand);
406 setOperationAction(ISD::FCOS , MVT::f32, Expand);
408 // Special cases we handle for FP constants.
409 addLegalFPImmediate(APFloat(+0.0f)); // xorps
410 addLegalFPImmediate(APFloat(+0.0)); // FLD0
411 addLegalFPImmediate(APFloat(+1.0)); // FLD1
412 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
413 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
415 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
416 // this though and handle it in InstructionSelectPreprocess so that
417 // dagcombine2 can hack on these.
419 setConvertAction(MVT::f32, MVT::f64, Expand);
420 setConvertAction(MVT::f32, MVT::f80, Expand);
421 setConvertAction(MVT::f80, MVT::f32, Expand);
422 setConvertAction(MVT::f64, MVT::f32, Expand);
423 // And x87->x87 truncations also.
424 setConvertAction(MVT::f80, MVT::f64, Expand);
428 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
429 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
432 // f32 and f64 in x87.
433 // Set up the FP register classes.
434 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
435 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
437 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
438 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
439 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
440 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
442 // Floating truncations go through memory. If optimizing, we lie about
443 // this though and handle it in InstructionSelectPreprocess so that
444 // dagcombine2 can hack on these.
446 setConvertAction(MVT::f80, MVT::f32, Expand);
447 setConvertAction(MVT::f64, MVT::f32, Expand);
448 setConvertAction(MVT::f80, MVT::f64, Expand);
452 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
453 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
455 addLegalFPImmediate(APFloat(+0.0)); // FLD0
456 addLegalFPImmediate(APFloat(+1.0)); // FLD1
457 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
458 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
459 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
460 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
461 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
462 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
465 // Long double always uses X87.
466 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
467 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
468 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
470 APFloat TmpFlt(+0.0);
471 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
472 addLegalFPImmediate(TmpFlt); // FLD0
474 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
475 APFloat TmpFlt2(+1.0);
476 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven);
477 addLegalFPImmediate(TmpFlt2); // FLD1
478 TmpFlt2.changeSign();
479 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
483 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
484 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
487 // Always use a library call for pow.
488 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
489 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
490 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
492 // First set operation action for all vector types to expand. Then we
493 // will selectively turn on ones that can be effectively codegen'd.
494 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
495 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
496 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
497 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
498 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
499 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
500 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
501 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
502 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
503 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
504 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
505 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
506 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
507 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
508 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
509 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
510 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::SimpleValueType)VT, Expand);
511 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::SimpleValueType)VT, Expand);
512 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
513 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
514 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
515 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
516 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
517 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
518 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
519 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
520 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
521 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
522 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
523 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
524 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
525 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
526 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
527 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
528 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
529 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
530 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
531 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
532 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
533 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
536 if (Subtarget->hasMMX()) {
537 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
538 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
539 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
540 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
542 // FIXME: add MMX packed arithmetics
544 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
545 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
546 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
547 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
549 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
550 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
551 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
552 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
554 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
555 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
557 setOperationAction(ISD::AND, MVT::v8i8, Promote);
558 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
559 setOperationAction(ISD::AND, MVT::v4i16, Promote);
560 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
561 setOperationAction(ISD::AND, MVT::v2i32, Promote);
562 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
563 setOperationAction(ISD::AND, MVT::v1i64, Legal);
565 setOperationAction(ISD::OR, MVT::v8i8, Promote);
566 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
567 setOperationAction(ISD::OR, MVT::v4i16, Promote);
568 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
569 setOperationAction(ISD::OR, MVT::v2i32, Promote);
570 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
571 setOperationAction(ISD::OR, MVT::v1i64, Legal);
573 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
574 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
575 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
576 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
577 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
578 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
579 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
581 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
582 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
583 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
584 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
585 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
586 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
587 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
589 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
590 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
591 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
592 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
594 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
595 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
596 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
599 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
600 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
601 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
604 if (Subtarget->hasSSE1()) {
605 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
607 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
608 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
609 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
610 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
611 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
612 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
613 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
614 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
615 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
616 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
617 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
618 setOperationAction(ISD::VSETCC, MVT::v4f32, Legal);
621 if (Subtarget->hasSSE2()) {
622 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
623 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
624 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
625 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
626 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
628 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
629 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
630 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
631 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
632 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
633 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
634 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
635 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
636 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
637 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
638 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
639 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
640 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
641 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
642 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
644 setOperationAction(ISD::VSETCC, MVT::v2f64, Legal);
645 setOperationAction(ISD::VSETCC, MVT::v16i8, Legal);
646 setOperationAction(ISD::VSETCC, MVT::v8i16, Legal);
647 setOperationAction(ISD::VSETCC, MVT::v4i32, Legal);
648 setOperationAction(ISD::VSETCC, MVT::v2i64, Legal);
650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
651 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
652 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
653 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
654 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
656 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
657 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
658 MVT VT = (MVT::SimpleValueType)i;
659 // Do not attempt to custom lower non-power-of-2 vectors
660 if (!isPowerOf2_32(VT.getVectorNumElements()))
662 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
663 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
664 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
666 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
667 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
668 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
669 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
670 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
671 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
672 if (Subtarget->is64Bit()) {
673 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
674 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
677 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
678 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
679 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
680 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
681 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
682 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
683 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
684 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
685 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
686 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
687 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
688 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
691 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
693 // Custom lower v2i64 and v2f64 selects.
694 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
695 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
696 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
697 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
701 if (Subtarget->hasSSE41()) {
702 // FIXME: Do we need to handle scalar-to-vector here?
703 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
704 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
706 // i8 and i16 vectors are custom , because the source register and source
707 // source memory operand types are not the same width. f32 vectors are
708 // custom since the immediate controlling the insert encodes additional
710 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
711 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
712 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
713 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
715 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
716 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
717 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
718 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
720 if (Subtarget->is64Bit()) {
721 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
722 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
726 // We want to custom lower some of our intrinsics.
727 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
729 // We have target-specific dag combine patterns for the following nodes:
730 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
731 setTargetDAGCombine(ISD::BUILD_VECTOR);
732 setTargetDAGCombine(ISD::SELECT);
733 setTargetDAGCombine(ISD::STORE);
735 computeRegisterProperties();
737 // FIXME: These should be based on subtarget info. Plus, the values should
738 // be smaller when we are in optimizing for size mode.
739 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
740 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
741 maxStoresPerMemmove = 3; // For %llvm.memmove -> sequence of stores
742 allowUnalignedMemoryAccesses = true; // x86 supports it!
743 setPrefLoopAlignment(16);
747 MVT X86TargetLowering::getSetCCResultType(const SDOperand &) const {
752 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
753 /// the desired ByVal argument alignment.
754 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
757 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
758 if (VTy->getBitWidth() == 128)
760 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
761 unsigned EltAlign = 0;
762 getMaxByValAlign(ATy->getElementType(), EltAlign);
763 if (EltAlign > MaxAlign)
765 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
766 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
767 unsigned EltAlign = 0;
768 getMaxByValAlign(STy->getElementType(i), EltAlign);
769 if (EltAlign > MaxAlign)
778 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
779 /// function arguments in the caller parameter area. For X86, aggregates
780 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
781 /// are at 4-byte boundaries.
782 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
783 if (Subtarget->is64Bit())
784 return getTargetData()->getABITypeAlignment(Ty);
786 if (Subtarget->hasSSE1())
787 getMaxByValAlign(Ty, Align);
791 /// getOptimalMemOpType - Returns the target specific optimal type for load
792 /// and store operations as a result of memset, memcpy, and memmove
793 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
796 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
797 bool isSrcConst, bool isSrcStr) const {
798 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
800 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
802 if (Subtarget->is64Bit() && Size >= 8)
808 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
810 SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
811 SelectionDAG &DAG) const {
812 if (usesGlobalOffsetTable())
813 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
814 if (!Subtarget->isPICStyleRIPRel())
815 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
819 //===----------------------------------------------------------------------===//
820 // Return Value Calling Convention Implementation
821 //===----------------------------------------------------------------------===//
823 #include "X86GenCallingConv.inc"
825 /// LowerRET - Lower an ISD::RET node.
826 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
827 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
829 SmallVector<CCValAssign, 16> RVLocs;
830 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
831 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
832 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
833 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
835 // If this is the first return lowered for this function, add the regs to the
836 // liveout set for the function.
837 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
838 for (unsigned i = 0; i != RVLocs.size(); ++i)
839 if (RVLocs[i].isRegLoc())
840 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
842 SDOperand Chain = Op.getOperand(0);
844 // Handle tail call return.
845 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
846 if (Chain.getOpcode() == X86ISD::TAILCALL) {
847 SDOperand TailCall = Chain;
848 SDOperand TargetAddress = TailCall.getOperand(1);
849 SDOperand StackAdjustment = TailCall.getOperand(2);
850 assert(((TargetAddress.getOpcode() == ISD::Register &&
851 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
852 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
853 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
854 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
855 "Expecting an global address, external symbol, or register");
856 assert(StackAdjustment.getOpcode() == ISD::Constant &&
857 "Expecting a const value");
859 SmallVector<SDOperand,8> Operands;
860 Operands.push_back(Chain.getOperand(0));
861 Operands.push_back(TargetAddress);
862 Operands.push_back(StackAdjustment);
863 // Copy registers used by the call. Last operand is a flag so it is not
865 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
866 Operands.push_back(Chain.getOperand(i));
868 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
875 SmallVector<SDOperand, 6> RetOps;
876 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
877 // Operand #1 = Bytes To Pop
878 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
880 // Copy the result values into the output registers.
881 for (unsigned i = 0; i != RVLocs.size(); ++i) {
882 CCValAssign &VA = RVLocs[i];
883 assert(VA.isRegLoc() && "Can only return in registers!");
884 SDOperand ValToCopy = Op.getOperand(i*2+1);
886 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
887 // the RET instruction and handled by the FP Stackifier.
888 if (RVLocs[i].getLocReg() == X86::ST0 ||
889 RVLocs[i].getLocReg() == X86::ST1) {
890 // If this is a copy from an xmm register to ST(0), use an FPExtend to
891 // change the value to the FP stack register class.
892 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
893 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
894 RetOps.push_back(ValToCopy);
895 // Don't emit a copytoreg.
899 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
900 Flag = Chain.getValue(1);
903 // The x86-64 ABI for returning structs by value requires that we copy
904 // the sret argument into %rax for the return. We saved the argument into
905 // a virtual register in the entry block, so now we copy the value out
907 if (Subtarget->is64Bit() &&
908 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
909 MachineFunction &MF = DAG.getMachineFunction();
910 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
911 unsigned Reg = FuncInfo->getSRetReturnReg();
913 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
914 FuncInfo->setSRetReturnReg(Reg);
916 SDOperand Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
918 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
919 Flag = Chain.getValue(1);
922 RetOps[0] = Chain; // Update chain.
924 // Add the flag if we have it.
926 RetOps.push_back(Flag);
928 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
932 /// LowerCallResult - Lower the result values of an ISD::CALL into the
933 /// appropriate copies out of appropriate physical registers. This assumes that
934 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
935 /// being lowered. The returns a SDNode with the same number of values as the
937 SDNode *X86TargetLowering::
938 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
939 unsigned CallingConv, SelectionDAG &DAG) {
941 // Assign locations to each value returned by this call.
942 SmallVector<CCValAssign, 16> RVLocs;
943 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
944 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
945 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
947 SmallVector<SDOperand, 8> ResultVals;
949 // Copy all of the result registers out of their specified physreg.
950 for (unsigned i = 0; i != RVLocs.size(); ++i) {
951 MVT CopyVT = RVLocs[i].getValVT();
953 // If this is a call to a function that returns an fp value on the floating
954 // point stack, but where we prefer to use the value in xmm registers, copy
955 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
956 if (RVLocs[i].getLocReg() == X86::ST0 &&
957 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
961 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
962 CopyVT, InFlag).getValue(1);
963 SDOperand Val = Chain.getValue(0);
964 InFlag = Chain.getValue(2);
966 if (CopyVT != RVLocs[i].getValVT()) {
967 // Round the F80 the right size, which also moves to the appropriate xmm
969 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
970 // This truncation won't change the value.
971 DAG.getIntPtrConstant(1));
974 ResultVals.push_back(Val);
977 // Merge everything together with a MERGE_VALUES node.
978 ResultVals.push_back(Chain);
979 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
980 &ResultVals[0], ResultVals.size()).Val;
984 //===----------------------------------------------------------------------===//
985 // C & StdCall & Fast Calling Convention implementation
986 //===----------------------------------------------------------------------===//
987 // StdCall calling convention seems to be standard for many Windows' API
988 // routines and around. It differs from C calling convention just a little:
989 // callee should clean up the stack, not caller. Symbols should be also
990 // decorated in some fancy way :) It doesn't support any vector arguments.
991 // For info on fast calling convention see Fast Calling Convention (tail call)
992 // implementation LowerX86_32FastCCCallTo.
994 /// AddLiveIn - This helper function adds the specified physical register to the
995 /// MachineFunction as a live in value. It also creates a corresponding virtual
997 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
998 const TargetRegisterClass *RC) {
999 assert(RC->contains(PReg) && "Not the correct regclass!");
1000 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1001 MF.getRegInfo().addLiveIn(PReg, VReg);
1005 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1007 static bool CallIsStructReturn(SDOperand Op) {
1008 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1012 return cast<ARG_FLAGSSDNode>(Op.getOperand(6))->getArgFlags().isSRet();
1015 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1016 /// return semantics.
1017 static bool ArgsAreStructReturn(SDOperand Op) {
1018 unsigned NumArgs = Op.Val->getNumValues() - 1;
1022 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1025 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1026 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1028 bool X86TargetLowering::IsCalleePop(SDOperand Op) {
1029 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1033 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
1036 case CallingConv::X86_StdCall:
1037 return !Subtarget->is64Bit();
1038 case CallingConv::X86_FastCall:
1039 return !Subtarget->is64Bit();
1040 case CallingConv::Fast:
1041 return PerformTailCallOpt;
1045 /// CCAssignFnForNode - Selects the correct CCAssignFn for a CALL or
1046 /// FORMAL_ARGUMENTS node.
1047 CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
1048 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1050 if (Subtarget->is64Bit()) {
1051 if (Subtarget->isTargetWin64())
1052 return CC_X86_Win64_C;
1054 if (CC == CallingConv::Fast && PerformTailCallOpt)
1055 return CC_X86_64_TailCall;
1061 if (CC == CallingConv::X86_FastCall)
1062 return CC_X86_32_FastCall;
1063 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1064 return CC_X86_32_TailCall;
1069 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1070 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1072 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDOperand Op) {
1073 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1074 if (CC == CallingConv::X86_FastCall)
1076 else if (CC == CallingConv::X86_StdCall)
1082 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1083 /// in a register before calling.
1084 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1085 return !IsTailCall && !Is64Bit &&
1086 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1087 Subtarget->isPICStyleGOT();
1090 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1091 /// address to be loaded in a register.
1093 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1094 return !Is64Bit && IsTailCall &&
1095 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1096 Subtarget->isPICStyleGOT();
1099 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1100 /// by "Src" to address "Dst" with size and alignment information specified by
1101 /// the specific parameter attribute. The copy will be passed as a byval
1102 /// function parameter.
1104 CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
1105 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
1106 SDOperand SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1107 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
1108 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1111 SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
1112 const CCValAssign &VA,
1113 MachineFrameInfo *MFI,
1115 SDOperand Root, unsigned i) {
1116 // Create the nodes corresponding to a load from this parameter slot.
1117 ISD::ArgFlagsTy Flags =
1118 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1119 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1120 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1122 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1123 // changed with more analysis.
1124 // In case of tail call optimization mark all arguments mutable. Since they
1125 // could be overwritten by lowering of arguments in case of a tail call.
1126 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1127 VA.getLocMemOffset(), isImmutable);
1128 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1129 if (Flags.isByVal())
1131 return DAG.getLoad(VA.getValVT(), Root, FIN,
1132 PseudoSourceValue::getFixedStack(), FI);
1136 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
1137 MachineFunction &MF = DAG.getMachineFunction();
1138 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1140 const Function* Fn = MF.getFunction();
1141 if (Fn->hasExternalLinkage() &&
1142 Subtarget->isTargetCygMing() &&
1143 Fn->getName() == "main")
1144 FuncInfo->setForceFramePointer(true);
1146 // Decorate the function name.
1147 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1149 MachineFrameInfo *MFI = MF.getFrameInfo();
1150 SDOperand Root = Op.getOperand(0);
1151 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1152 unsigned CC = MF.getFunction()->getCallingConv();
1153 bool Is64Bit = Subtarget->is64Bit();
1154 bool IsWin64 = Subtarget->isTargetWin64();
1156 assert(!(isVarArg && CC == CallingConv::Fast) &&
1157 "Var args not supported with calling convention fastcc");
1159 // Assign locations to all of the incoming arguments.
1160 SmallVector<CCValAssign, 16> ArgLocs;
1161 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1162 CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
1164 SmallVector<SDOperand, 8> ArgValues;
1165 unsigned LastVal = ~0U;
1166 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1167 CCValAssign &VA = ArgLocs[i];
1168 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1170 assert(VA.getValNo() != LastVal &&
1171 "Don't support value assigned to multiple locs yet");
1172 LastVal = VA.getValNo();
1174 if (VA.isRegLoc()) {
1175 MVT RegVT = VA.getLocVT();
1176 TargetRegisterClass *RC;
1177 if (RegVT == MVT::i32)
1178 RC = X86::GR32RegisterClass;
1179 else if (Is64Bit && RegVT == MVT::i64)
1180 RC = X86::GR64RegisterClass;
1181 else if (RegVT == MVT::f32)
1182 RC = X86::FR32RegisterClass;
1183 else if (RegVT == MVT::f64)
1184 RC = X86::FR64RegisterClass;
1185 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1186 RC = X86::VR128RegisterClass;
1187 else if (RegVT.isVector()) {
1188 assert(RegVT.getSizeInBits() == 64);
1190 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1192 // Darwin calling convention passes MMX values in either GPRs or
1193 // XMMs in x86-64. Other targets pass them in memory.
1194 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1195 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1198 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1203 assert(0 && "Unknown argument type!");
1206 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1207 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1209 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1210 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1212 if (VA.getLocInfo() == CCValAssign::SExt)
1213 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1214 DAG.getValueType(VA.getValVT()));
1215 else if (VA.getLocInfo() == CCValAssign::ZExt)
1216 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1217 DAG.getValueType(VA.getValVT()));
1219 if (VA.getLocInfo() != CCValAssign::Full)
1220 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1222 // Handle MMX values passed in GPRs.
1223 if (Is64Bit && RegVT != VA.getLocVT()) {
1224 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1225 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1226 else if (RC == X86::VR128RegisterClass) {
1227 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
1228 DAG.getConstant(0, MVT::i64));
1229 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1233 ArgValues.push_back(ArgValue);
1235 assert(VA.isMemLoc());
1236 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1240 // The x86-64 ABI for returning structs by value requires that we copy
1241 // the sret argument into %rax for the return. Save the argument into
1242 // a virtual register so that we can access it from the return points.
1243 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1244 MachineFunction &MF = DAG.getMachineFunction();
1245 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1246 unsigned Reg = FuncInfo->getSRetReturnReg();
1248 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1249 FuncInfo->setSRetReturnReg(Reg);
1251 SDOperand Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
1252 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
1255 unsigned StackSize = CCInfo.getNextStackOffset();
1256 // align stack specially for tail calls
1257 if (CC == CallingConv::Fast)
1258 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1260 // If the function takes variable number of arguments, make a frame index for
1261 // the start of the first vararg value... for expansion of llvm.va_start.
1263 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1264 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1267 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1269 // FIXME: We should really autogenerate these arrays
1270 static const unsigned GPR64ArgRegsWin64[] = {
1271 X86::RCX, X86::RDX, X86::R8, X86::R9
1273 static const unsigned XMMArgRegsWin64[] = {
1274 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1276 static const unsigned GPR64ArgRegs64Bit[] = {
1277 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1279 static const unsigned XMMArgRegs64Bit[] = {
1280 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1281 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1283 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1286 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1287 GPR64ArgRegs = GPR64ArgRegsWin64;
1288 XMMArgRegs = XMMArgRegsWin64;
1290 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1291 GPR64ArgRegs = GPR64ArgRegs64Bit;
1292 XMMArgRegs = XMMArgRegs64Bit;
1294 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1296 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1299 // For X86-64, if there are vararg parameters that are passed via
1300 // registers, then we must store them to their spots on the stack so they
1301 // may be loaded by deferencing the result of va_next.
1302 VarArgsGPOffset = NumIntRegs * 8;
1303 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1304 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1305 TotalNumXMMRegs * 16, 16);
1307 // Store the integer parameter registers.
1308 SmallVector<SDOperand, 8> MemOps;
1309 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1310 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1311 DAG.getIntPtrConstant(VarArgsGPOffset));
1312 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1313 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1314 X86::GR64RegisterClass);
1315 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1317 DAG.getStore(Val.getValue(1), Val, FIN,
1318 PseudoSourceValue::getFixedStack(),
1320 MemOps.push_back(Store);
1321 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1322 DAG.getIntPtrConstant(8));
1325 // Now store the XMM (fp + vector) parameter registers.
1326 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1327 DAG.getIntPtrConstant(VarArgsFPOffset));
1328 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1329 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1330 X86::VR128RegisterClass);
1331 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1333 DAG.getStore(Val.getValue(1), Val, FIN,
1334 PseudoSourceValue::getFixedStack(),
1336 MemOps.push_back(Store);
1337 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1338 DAG.getIntPtrConstant(16));
1340 if (!MemOps.empty())
1341 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1342 &MemOps[0], MemOps.size());
1346 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1347 // arguments and the arguments after the retaddr has been pushed are
1349 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1350 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1351 (StackSize & 7) == 0)
1354 ArgValues.push_back(Root);
1356 // Some CCs need callee pop.
1357 if (IsCalleePop(Op)) {
1358 BytesToPopOnReturn = StackSize; // Callee pops everything.
1359 BytesCallerReserves = 0;
1361 BytesToPopOnReturn = 0; // Callee pops nothing.
1362 // If this is an sret function, the return should pop the hidden pointer.
1363 if (!Is64Bit && ArgsAreStructReturn(Op))
1364 BytesToPopOnReturn = 4;
1365 BytesCallerReserves = StackSize;
1369 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1370 if (CC == CallingConv::X86_FastCall)
1371 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1374 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1376 // Return the new list of results.
1377 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1378 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1382 X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
1383 const SDOperand &StackPtr,
1384 const CCValAssign &VA,
1387 unsigned LocMemOffset = VA.getLocMemOffset();
1388 SDOperand PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1389 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1390 ISD::ArgFlagsTy Flags =
1391 cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->getArgFlags();
1392 if (Flags.isByVal()) {
1393 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1395 return DAG.getStore(Chain, Arg, PtrOff,
1396 PseudoSourceValue::getStack(), LocMemOffset);
1399 /// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call
1400 /// optimization is performed and it is required.
1402 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1403 SDOperand &OutRetAddr,
1408 if (!IsTailCall || FPDiff==0) return Chain;
1410 // Adjust the Return address stack slot.
1411 MVT VT = getPointerTy();
1412 OutRetAddr = getReturnAddressFrameIndex(DAG);
1413 // Load the "old" Return address.
1414 OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
1415 return SDOperand(OutRetAddr.Val, 1);
1418 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1419 /// optimization is performed and it is required (FPDiff!=0).
1421 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1422 SDOperand Chain, SDOperand RetAddrFrIdx,
1423 bool Is64Bit, int FPDiff) {
1424 // Store the return address to the appropriate stack slot.
1425 if (!FPDiff) return Chain;
1426 // Calculate the new stack slot for the return address.
1427 int SlotSize = Is64Bit ? 8 : 4;
1428 int NewReturnAddrFI =
1429 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1430 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1431 SDOperand NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1432 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1433 PseudoSourceValue::getFixedStack(), NewReturnAddrFI);
1437 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
1438 MachineFunction &MF = DAG.getMachineFunction();
1439 SDOperand Chain = Op.getOperand(0);
1440 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1441 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1442 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
1443 && CC == CallingConv::Fast && PerformTailCallOpt;
1444 SDOperand Callee = Op.getOperand(4);
1445 bool Is64Bit = Subtarget->is64Bit();
1446 bool IsStructRet = CallIsStructReturn(Op);
1448 assert(!(isVarArg && CC == CallingConv::Fast) &&
1449 "Var args not supported with calling convention fastcc");
1451 // Analyze operands of the call, assigning locations to each operand.
1452 SmallVector<CCValAssign, 16> ArgLocs;
1453 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1454 CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op));
1456 // Get a count of how many bytes are to be pushed on the stack.
1457 unsigned NumBytes = CCInfo.getNextStackOffset();
1458 if (CC == CallingConv::Fast)
1459 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1461 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1462 // arguments and the arguments after the retaddr has been pushed are aligned.
1463 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1464 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1465 (NumBytes & 7) == 0)
1470 // Lower arguments at fp - stackoffset + fpdiff.
1471 unsigned NumBytesCallerPushed =
1472 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1473 FPDiff = NumBytesCallerPushed - NumBytes;
1475 // Set the delta of movement of the returnaddr stackslot.
1476 // But only set if delta is greater than previous delta.
1477 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1478 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1481 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
1483 SDOperand RetAddrFrIdx;
1484 // Load return adress for tail calls.
1485 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1488 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1489 SmallVector<SDOperand, 8> MemOpChains;
1492 // Walk the register/memloc assignments, inserting copies/loads. In the case
1493 // of tail call optimization arguments are handle later.
1494 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1495 CCValAssign &VA = ArgLocs[i];
1496 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1497 bool isByVal = cast<ARG_FLAGSSDNode>(Op.getOperand(6+2*VA.getValNo()))->
1498 getArgFlags().isByVal();
1500 // Promote the value if needed.
1501 switch (VA.getLocInfo()) {
1502 default: assert(0 && "Unknown loc info!");
1503 case CCValAssign::Full: break;
1504 case CCValAssign::SExt:
1505 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1507 case CCValAssign::ZExt:
1508 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1510 case CCValAssign::AExt:
1511 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1515 if (VA.isRegLoc()) {
1517 MVT RegVT = VA.getLocVT();
1518 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1519 switch (VA.getLocReg()) {
1522 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1524 // Special case: passing MMX values in GPR registers.
1525 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1528 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1529 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1530 // Special case: passing MMX values in XMM registers.
1531 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1532 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
1533 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
1534 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
1535 getMOVLMask(2, DAG));
1540 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1542 if (!IsTailCall || (IsTailCall && isByVal)) {
1543 assert(VA.isMemLoc());
1544 if (StackPtr.Val == 0)
1545 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1547 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1553 if (!MemOpChains.empty())
1554 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1555 &MemOpChains[0], MemOpChains.size());
1557 // Build a sequence of copy-to-reg nodes chained together with token chain
1558 // and flag operands which copy the outgoing args into registers.
1560 // Tail call byval lowering might overwrite argument registers so in case of
1561 // tail call optimization the copies to registers are lowered later.
1563 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1564 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1566 InFlag = Chain.getValue(1);
1569 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1571 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1572 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1573 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1575 InFlag = Chain.getValue(1);
1577 // If we are tail calling and generating PIC/GOT style code load the address
1578 // of the callee into ecx. The value in ecx is used as target of the tail
1579 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1580 // calls on PIC/GOT architectures. Normally we would just put the address of
1581 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1582 // restored (since ebx is callee saved) before jumping to the target@PLT.
1583 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1584 // Note: The actual moving to ecx is done further down.
1585 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1586 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1587 !G->getGlobal()->hasProtectedVisibility())
1588 Callee = LowerGlobalAddress(Callee, DAG);
1589 else if (isa<ExternalSymbolSDNode>(Callee))
1590 Callee = LowerExternalSymbol(Callee,DAG);
1593 if (Is64Bit && isVarArg) {
1594 // From AMD64 ABI document:
1595 // For calls that may call functions that use varargs or stdargs
1596 // (prototype-less calls or calls to functions containing ellipsis (...) in
1597 // the declaration) %al is used as hidden argument to specify the number
1598 // of SSE registers used. The contents of %al do not need to match exactly
1599 // the number of registers, but must be an ubound on the number of SSE
1600 // registers used and is in the range 0 - 8 inclusive.
1602 // FIXME: Verify this on Win64
1603 // Count the number of XMM registers allocated.
1604 static const unsigned XMMArgRegs[] = {
1605 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1606 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1608 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1610 Chain = DAG.getCopyToReg(Chain, X86::AL,
1611 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1612 InFlag = Chain.getValue(1);
1616 // For tail calls lower the arguments to the 'real' stack slot.
1618 SmallVector<SDOperand, 8> MemOpChains2;
1621 // Do not flag preceeding copytoreg stuff together with the following stuff.
1622 InFlag = SDOperand();
1623 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1624 CCValAssign &VA = ArgLocs[i];
1625 if (!VA.isRegLoc()) {
1626 assert(VA.isMemLoc());
1627 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1628 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1629 ISD::ArgFlagsTy Flags =
1630 cast<ARG_FLAGSSDNode>(FlagsOp)->getArgFlags();
1631 // Create frame index.
1632 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1633 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1634 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1635 FIN = DAG.getFrameIndex(FI, getPointerTy());
1637 if (Flags.isByVal()) {
1638 // Copy relative to framepointer.
1639 SDOperand Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1640 if (StackPtr.Val == 0)
1641 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1642 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1644 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1647 // Store relative to framepointer.
1648 MemOpChains2.push_back(
1649 DAG.getStore(Chain, Arg, FIN,
1650 PseudoSourceValue::getFixedStack(), FI));
1655 if (!MemOpChains2.empty())
1656 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1657 &MemOpChains2[0], MemOpChains2.size());
1659 // Copy arguments to their registers.
1660 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1661 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1663 InFlag = Chain.getValue(1);
1665 InFlag =SDOperand();
1667 // Store the return address to the appropriate stack slot.
1668 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1672 // If the callee is a GlobalAddress node (quite common, every direct call is)
1673 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1674 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1675 // We should use extra load for direct calls to dllimported functions in
1677 if ((IsTailCall || !Is64Bit ||
1678 getTargetMachine().getCodeModel() != CodeModel::Large)
1679 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1680 getTargetMachine(), true))
1681 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1682 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1683 if (IsTailCall || !Is64Bit ||
1684 getTargetMachine().getCodeModel() != CodeModel::Large)
1685 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1686 } else if (IsTailCall) {
1687 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
1689 Chain = DAG.getCopyToReg(Chain,
1690 DAG.getRegister(Opc, getPointerTy()),
1692 Callee = DAG.getRegister(Opc, getPointerTy());
1693 // Add register as live out.
1694 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1697 // Returns a chain & a flag for retval copy to use.
1698 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1699 SmallVector<SDOperand, 8> Ops;
1702 Ops.push_back(Chain);
1703 Ops.push_back(DAG.getIntPtrConstant(NumBytes));
1704 Ops.push_back(DAG.getIntPtrConstant(0));
1706 Ops.push_back(InFlag);
1707 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1708 InFlag = Chain.getValue(1);
1710 // Returns a chain & a flag for retval copy to use.
1711 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1715 Ops.push_back(Chain);
1716 Ops.push_back(Callee);
1719 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1721 // Add argument registers to the end of the list so that they are known live
1723 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1724 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1725 RegsToPass[i].second.getValueType()));
1727 // Add an implicit use GOT pointer in EBX.
1728 if (!IsTailCall && !Is64Bit &&
1729 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1730 Subtarget->isPICStyleGOT())
1731 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1733 // Add an implicit use of AL for x86 vararg functions.
1734 if (Is64Bit && isVarArg)
1735 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1738 Ops.push_back(InFlag);
1741 assert(InFlag.Val &&
1742 "Flag must be set. Depend on flag being set in LowerRET");
1743 Chain = DAG.getNode(X86ISD::TAILCALL,
1744 Op.Val->getVTList(), &Ops[0], Ops.size());
1746 return SDOperand(Chain.Val, Op.ResNo);
1749 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1750 InFlag = Chain.getValue(1);
1752 // Create the CALLSEQ_END node.
1753 unsigned NumBytesForCalleeToPush;
1754 if (IsCalleePop(Op))
1755 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1756 else if (!Is64Bit && IsStructRet)
1757 // If this is is a call to a struct-return function, the callee
1758 // pops the hidden struct pointer, so we have to push it back.
1759 // This is common for Darwin/X86, Linux & Mingw32 targets.
1760 NumBytesForCalleeToPush = 4;
1762 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1764 // Returns a flag for retval copy to use.
1765 Chain = DAG.getCALLSEQ_END(Chain,
1766 DAG.getIntPtrConstant(NumBytes),
1767 DAG.getIntPtrConstant(NumBytesForCalleeToPush),
1769 InFlag = Chain.getValue(1);
1771 // Handle result values, copying them out of physregs into vregs that we
1773 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1777 //===----------------------------------------------------------------------===//
1778 // Fast Calling Convention (tail call) implementation
1779 //===----------------------------------------------------------------------===//
1781 // Like std call, callee cleans arguments, convention except that ECX is
1782 // reserved for storing the tail called function address. Only 2 registers are
1783 // free for argument passing (inreg). Tail call optimization is performed
1785 // * tailcallopt is enabled
1786 // * caller/callee are fastcc
1787 // On X86_64 architecture with GOT-style position independent code only local
1788 // (within module) calls are supported at the moment.
1789 // To keep the stack aligned according to platform abi the function
1790 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1791 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1792 // If a tail called function callee has more arguments than the caller the
1793 // caller needs to make sure that there is room to move the RETADDR to. This is
1794 // achieved by reserving an area the size of the argument delta right after the
1795 // original REtADDR, but before the saved framepointer or the spilled registers
1796 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1808 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1809 /// for a 16 byte align requirement.
1810 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1811 SelectionDAG& DAG) {
1812 if (PerformTailCallOpt) {
1813 MachineFunction &MF = DAG.getMachineFunction();
1814 const TargetMachine &TM = MF.getTarget();
1815 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1816 unsigned StackAlignment = TFI.getStackAlignment();
1817 uint64_t AlignMask = StackAlignment - 1;
1818 int64_t Offset = StackSize;
1819 unsigned SlotSize = Subtarget->is64Bit() ? 8 : 4;
1820 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1821 // Number smaller than 12 so just add the difference.
1822 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1824 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1825 Offset = ((~AlignMask) & Offset) + StackAlignment +
1826 (StackAlignment-SlotSize);
1833 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1834 /// following the call is a return. A function is eligible if caller/callee
1835 /// calling conventions match, currently only fastcc supports tail calls, and
1836 /// the function CALL is immediatly followed by a RET.
1837 bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
1839 SelectionDAG& DAG) const {
1840 if (!PerformTailCallOpt)
1843 if (CheckTailCallReturnConstraints(Call, Ret)) {
1844 MachineFunction &MF = DAG.getMachineFunction();
1845 unsigned CallerCC = MF.getFunction()->getCallingConv();
1846 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1847 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1848 SDOperand Callee = Call.getOperand(4);
1849 // On x86/32Bit PIC/GOT tail calls are supported.
1850 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1851 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1854 // Can only do local tail calls (in same module, hidden or protected) on
1855 // x86_64 PIC/GOT at the moment.
1856 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1857 return G->getGlobal()->hasHiddenVisibility()
1858 || G->getGlobal()->hasProtectedVisibility();
1865 //===----------------------------------------------------------------------===//
1866 // Other Lowering Hooks
1867 //===----------------------------------------------------------------------===//
1870 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1871 MachineFunction &MF = DAG.getMachineFunction();
1872 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1873 int ReturnAddrIndex = FuncInfo->getRAIndex();
1875 if (ReturnAddrIndex == 0) {
1876 // Set up a frame object for the return address.
1877 if (Subtarget->is64Bit())
1878 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1880 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1882 FuncInfo->setRAIndex(ReturnAddrIndex);
1885 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1890 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1891 /// specific condition code. It returns a false if it cannot do a direct
1892 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1894 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1895 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1896 SelectionDAG &DAG) {
1897 X86CC = X86::COND_INVALID;
1899 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1900 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1901 // X > -1 -> X == 0, jump !sign.
1902 RHS = DAG.getConstant(0, RHS.getValueType());
1903 X86CC = X86::COND_NS;
1905 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1906 // X < 0 -> X == 0, jump on sign.
1907 X86CC = X86::COND_S;
1909 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) {
1911 RHS = DAG.getConstant(0, RHS.getValueType());
1912 X86CC = X86::COND_LE;
1917 switch (SetCCOpcode) {
1919 case ISD::SETEQ: X86CC = X86::COND_E; break;
1920 case ISD::SETGT: X86CC = X86::COND_G; break;
1921 case ISD::SETGE: X86CC = X86::COND_GE; break;
1922 case ISD::SETLT: X86CC = X86::COND_L; break;
1923 case ISD::SETLE: X86CC = X86::COND_LE; break;
1924 case ISD::SETNE: X86CC = X86::COND_NE; break;
1925 case ISD::SETULT: X86CC = X86::COND_B; break;
1926 case ISD::SETUGT: X86CC = X86::COND_A; break;
1927 case ISD::SETULE: X86CC = X86::COND_BE; break;
1928 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1931 // On a floating point condition, the flags are set as follows:
1933 // 0 | 0 | 0 | X > Y
1934 // 0 | 0 | 1 | X < Y
1935 // 1 | 0 | 0 | X == Y
1936 // 1 | 1 | 1 | unordered
1938 switch (SetCCOpcode) {
1941 case ISD::SETEQ: X86CC = X86::COND_E; break;
1942 case ISD::SETOLT: Flip = true; // Fallthrough
1944 case ISD::SETGT: X86CC = X86::COND_A; break;
1945 case ISD::SETOLE: Flip = true; // Fallthrough
1947 case ISD::SETGE: X86CC = X86::COND_AE; break;
1948 case ISD::SETUGT: Flip = true; // Fallthrough
1950 case ISD::SETLT: X86CC = X86::COND_B; break;
1951 case ISD::SETUGE: Flip = true; // Fallthrough
1953 case ISD::SETLE: X86CC = X86::COND_BE; break;
1955 case ISD::SETNE: X86CC = X86::COND_NE; break;
1956 case ISD::SETUO: X86CC = X86::COND_P; break;
1957 case ISD::SETO: X86CC = X86::COND_NP; break;
1960 std::swap(LHS, RHS);
1963 return X86CC != X86::COND_INVALID;
1966 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1967 /// code. Current x86 isa includes the following FP cmov instructions:
1968 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1969 static bool hasFPCMov(unsigned X86CC) {
1985 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1986 /// true if Op is undef or if its value falls within the specified range (L, H].
1987 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1988 if (Op.getOpcode() == ISD::UNDEF)
1991 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1992 return (Val >= Low && Val < Hi);
1995 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1996 /// true if Op is undef or if its value equal to the specified value.
1997 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1998 if (Op.getOpcode() == ISD::UNDEF)
2000 return cast<ConstantSDNode>(Op)->getValue() == Val;
2003 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2004 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2005 bool X86::isPSHUFDMask(SDNode *N) {
2006 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2008 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2011 // Check if the value doesn't reference the second vector.
2012 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2013 SDOperand Arg = N->getOperand(i);
2014 if (Arg.getOpcode() == ISD::UNDEF) continue;
2015 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2016 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
2023 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2024 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2025 bool X86::isPSHUFHWMask(SDNode *N) {
2026 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2028 if (N->getNumOperands() != 8)
2031 // Lower quadword copied in order.
2032 for (unsigned i = 0; i != 4; ++i) {
2033 SDOperand Arg = N->getOperand(i);
2034 if (Arg.getOpcode() == ISD::UNDEF) continue;
2035 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2036 if (cast<ConstantSDNode>(Arg)->getValue() != i)
2040 // Upper quadword shuffled.
2041 for (unsigned i = 4; i != 8; ++i) {
2042 SDOperand Arg = N->getOperand(i);
2043 if (Arg.getOpcode() == ISD::UNDEF) continue;
2044 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2045 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2046 if (Val < 4 || Val > 7)
2053 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2054 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2055 bool X86::isPSHUFLWMask(SDNode *N) {
2056 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2058 if (N->getNumOperands() != 8)
2061 // Upper quadword copied in order.
2062 for (unsigned i = 4; i != 8; ++i)
2063 if (!isUndefOrEqual(N->getOperand(i), i))
2066 // Lower quadword shuffled.
2067 for (unsigned i = 0; i != 4; ++i)
2068 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2074 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2075 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2076 static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) {
2077 if (NumElems != 2 && NumElems != 4) return false;
2079 unsigned Half = NumElems / 2;
2080 for (unsigned i = 0; i < Half; ++i)
2081 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2083 for (unsigned i = Half; i < NumElems; ++i)
2084 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2090 bool X86::isSHUFPMask(SDNode *N) {
2091 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2092 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2095 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2096 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2097 /// half elements to come from vector 1 (which would equal the dest.) and
2098 /// the upper half to come from vector 2.
2099 static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) {
2100 if (NumOps != 2 && NumOps != 4) return false;
2102 unsigned Half = NumOps / 2;
2103 for (unsigned i = 0; i < Half; ++i)
2104 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2106 for (unsigned i = Half; i < NumOps; ++i)
2107 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2112 static bool isCommutedSHUFP(SDNode *N) {
2113 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2114 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2117 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2118 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2119 bool X86::isMOVHLPSMask(SDNode *N) {
2120 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2122 if (N->getNumOperands() != 4)
2125 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2126 return isUndefOrEqual(N->getOperand(0), 6) &&
2127 isUndefOrEqual(N->getOperand(1), 7) &&
2128 isUndefOrEqual(N->getOperand(2), 2) &&
2129 isUndefOrEqual(N->getOperand(3), 3);
2132 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2133 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2135 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2136 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2138 if (N->getNumOperands() != 4)
2141 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2142 return isUndefOrEqual(N->getOperand(0), 2) &&
2143 isUndefOrEqual(N->getOperand(1), 3) &&
2144 isUndefOrEqual(N->getOperand(2), 2) &&
2145 isUndefOrEqual(N->getOperand(3), 3);
2148 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2149 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2150 bool X86::isMOVLPMask(SDNode *N) {
2151 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2153 unsigned NumElems = N->getNumOperands();
2154 if (NumElems != 2 && NumElems != 4)
2157 for (unsigned i = 0; i < NumElems/2; ++i)
2158 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2161 for (unsigned i = NumElems/2; i < NumElems; ++i)
2162 if (!isUndefOrEqual(N->getOperand(i), i))
2168 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2169 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2171 bool X86::isMOVHPMask(SDNode *N) {
2172 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2174 unsigned NumElems = N->getNumOperands();
2175 if (NumElems != 2 && NumElems != 4)
2178 for (unsigned i = 0; i < NumElems/2; ++i)
2179 if (!isUndefOrEqual(N->getOperand(i), i))
2182 for (unsigned i = 0; i < NumElems/2; ++i) {
2183 SDOperand Arg = N->getOperand(i + NumElems/2);
2184 if (!isUndefOrEqual(Arg, i + NumElems))
2191 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2192 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2193 bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts,
2194 bool V2IsSplat = false) {
2195 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2198 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2199 SDOperand BitI = Elts[i];
2200 SDOperand BitI1 = Elts[i+1];
2201 if (!isUndefOrEqual(BitI, j))
2204 if (isUndefOrEqual(BitI1, NumElts))
2207 if (!isUndefOrEqual(BitI1, j + NumElts))
2215 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2216 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2217 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2220 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2221 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2222 bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts,
2223 bool V2IsSplat = false) {
2224 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2227 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2228 SDOperand BitI = Elts[i];
2229 SDOperand BitI1 = Elts[i+1];
2230 if (!isUndefOrEqual(BitI, j + NumElts/2))
2233 if (isUndefOrEqual(BitI1, NumElts))
2236 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2244 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2245 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2246 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2249 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2250 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2252 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2253 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2255 unsigned NumElems = N->getNumOperands();
2256 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2259 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2260 SDOperand BitI = N->getOperand(i);
2261 SDOperand BitI1 = N->getOperand(i+1);
2263 if (!isUndefOrEqual(BitI, j))
2265 if (!isUndefOrEqual(BitI1, j))
2272 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2273 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2275 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2276 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2278 unsigned NumElems = N->getNumOperands();
2279 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2282 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2283 SDOperand BitI = N->getOperand(i);
2284 SDOperand BitI1 = N->getOperand(i + 1);
2286 if (!isUndefOrEqual(BitI, j))
2288 if (!isUndefOrEqual(BitI1, j))
2295 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2296 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2297 /// MOVSD, and MOVD, i.e. setting the lowest element.
2298 static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) {
2299 if (NumElts != 2 && NumElts != 4)
2302 if (!isUndefOrEqual(Elts[0], NumElts))
2305 for (unsigned i = 1; i < NumElts; ++i) {
2306 if (!isUndefOrEqual(Elts[i], i))
2313 bool X86::isMOVLMask(SDNode *N) {
2314 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2315 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2318 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2319 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2320 /// element of vector 2 and the other elements to come from vector 1 in order.
2321 static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps,
2322 bool V2IsSplat = false,
2323 bool V2IsUndef = false) {
2324 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2327 if (!isUndefOrEqual(Ops[0], 0))
2330 for (unsigned i = 1; i < NumOps; ++i) {
2331 SDOperand Arg = Ops[i];
2332 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2333 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2334 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2341 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2342 bool V2IsUndef = false) {
2343 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2344 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2345 V2IsSplat, V2IsUndef);
2348 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2349 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2350 bool X86::isMOVSHDUPMask(SDNode *N) {
2351 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2353 if (N->getNumOperands() != 4)
2356 // Expect 1, 1, 3, 3
2357 for (unsigned i = 0; i < 2; ++i) {
2358 SDOperand Arg = N->getOperand(i);
2359 if (Arg.getOpcode() == ISD::UNDEF) continue;
2360 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2361 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2362 if (Val != 1) return false;
2366 for (unsigned i = 2; i < 4; ++i) {
2367 SDOperand Arg = N->getOperand(i);
2368 if (Arg.getOpcode() == ISD::UNDEF) continue;
2369 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2370 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2371 if (Val != 3) return false;
2375 // Don't use movshdup if it can be done with a shufps.
2379 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2380 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2381 bool X86::isMOVSLDUPMask(SDNode *N) {
2382 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2384 if (N->getNumOperands() != 4)
2387 // Expect 0, 0, 2, 2
2388 for (unsigned i = 0; i < 2; ++i) {
2389 SDOperand Arg = N->getOperand(i);
2390 if (Arg.getOpcode() == ISD::UNDEF) continue;
2391 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2392 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2393 if (Val != 0) return false;
2397 for (unsigned i = 2; i < 4; ++i) {
2398 SDOperand Arg = N->getOperand(i);
2399 if (Arg.getOpcode() == ISD::UNDEF) continue;
2400 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2401 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2402 if (Val != 2) return false;
2406 // Don't use movshdup if it can be done with a shufps.
2410 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2411 /// specifies a identity operation on the LHS or RHS.
2412 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2413 unsigned NumElems = N->getNumOperands();
2414 for (unsigned i = 0; i < NumElems; ++i)
2415 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2420 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2421 /// a splat of a single element.
2422 static bool isSplatMask(SDNode *N) {
2423 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2425 // This is a splat operation if each element of the permute is the same, and
2426 // if the value doesn't reference the second vector.
2427 unsigned NumElems = N->getNumOperands();
2428 SDOperand ElementBase;
2430 for (; i != NumElems; ++i) {
2431 SDOperand Elt = N->getOperand(i);
2432 if (isa<ConstantSDNode>(Elt)) {
2438 if (!ElementBase.Val)
2441 for (; i != NumElems; ++i) {
2442 SDOperand Arg = N->getOperand(i);
2443 if (Arg.getOpcode() == ISD::UNDEF) continue;
2444 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2445 if (Arg != ElementBase) return false;
2448 // Make sure it is a splat of the first vector operand.
2449 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2452 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2453 /// a splat of a single element and it's a 2 or 4 element mask.
2454 bool X86::isSplatMask(SDNode *N) {
2455 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2457 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2458 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2460 return ::isSplatMask(N);
2463 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2464 /// specifies a splat of zero element.
2465 bool X86::isSplatLoMask(SDNode *N) {
2466 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2468 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2469 if (!isUndefOrEqual(N->getOperand(i), 0))
2474 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2475 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2477 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2478 unsigned NumOperands = N->getNumOperands();
2479 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2481 for (unsigned i = 0; i < NumOperands; ++i) {
2483 SDOperand Arg = N->getOperand(NumOperands-i-1);
2484 if (Arg.getOpcode() != ISD::UNDEF)
2485 Val = cast<ConstantSDNode>(Arg)->getValue();
2486 if (Val >= NumOperands) Val -= NumOperands;
2488 if (i != NumOperands - 1)
2495 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2496 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2498 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2500 // 8 nodes, but we only care about the last 4.
2501 for (unsigned i = 7; i >= 4; --i) {
2503 SDOperand Arg = N->getOperand(i);
2504 if (Arg.getOpcode() != ISD::UNDEF)
2505 Val = cast<ConstantSDNode>(Arg)->getValue();
2514 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2515 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2517 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2519 // 8 nodes, but we only care about the first 4.
2520 for (int i = 3; i >= 0; --i) {
2522 SDOperand Arg = N->getOperand(i);
2523 if (Arg.getOpcode() != ISD::UNDEF)
2524 Val = cast<ConstantSDNode>(Arg)->getValue();
2533 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2534 /// specifies a 8 element shuffle that can be broken into a pair of
2535 /// PSHUFHW and PSHUFLW.
2536 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2537 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2539 if (N->getNumOperands() != 8)
2542 // Lower quadword shuffled.
2543 for (unsigned i = 0; i != 4; ++i) {
2544 SDOperand Arg = N->getOperand(i);
2545 if (Arg.getOpcode() == ISD::UNDEF) continue;
2546 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2547 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2552 // Upper quadword shuffled.
2553 for (unsigned i = 4; i != 8; ++i) {
2554 SDOperand Arg = N->getOperand(i);
2555 if (Arg.getOpcode() == ISD::UNDEF) continue;
2556 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2557 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2558 if (Val < 4 || Val > 7)
2565 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2566 /// values in ther permute mask.
2567 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2568 SDOperand &V2, SDOperand &Mask,
2569 SelectionDAG &DAG) {
2570 MVT VT = Op.getValueType();
2571 MVT MaskVT = Mask.getValueType();
2572 MVT EltVT = MaskVT.getVectorElementType();
2573 unsigned NumElems = Mask.getNumOperands();
2574 SmallVector<SDOperand, 8> MaskVec;
2576 for (unsigned i = 0; i != NumElems; ++i) {
2577 SDOperand Arg = Mask.getOperand(i);
2578 if (Arg.getOpcode() == ISD::UNDEF) {
2579 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2582 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2583 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2585 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2587 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2591 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2592 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2595 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2596 /// the two vector operands have swapped position.
2598 SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) {
2599 MVT MaskVT = Mask.getValueType();
2600 MVT EltVT = MaskVT.getVectorElementType();
2601 unsigned NumElems = Mask.getNumOperands();
2602 SmallVector<SDOperand, 8> MaskVec;
2603 for (unsigned i = 0; i != NumElems; ++i) {
2604 SDOperand Arg = Mask.getOperand(i);
2605 if (Arg.getOpcode() == ISD::UNDEF) {
2606 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2609 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2610 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2612 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2614 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2616 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2620 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2621 /// match movhlps. The lower half elements should come from upper half of
2622 /// V1 (and in order), and the upper half elements should come from the upper
2623 /// half of V2 (and in order).
2624 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2625 unsigned NumElems = Mask->getNumOperands();
2628 for (unsigned i = 0, e = 2; i != e; ++i)
2629 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2631 for (unsigned i = 2; i != 4; ++i)
2632 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2637 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2638 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2640 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2641 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2642 N = N->getOperand(0).Val;
2643 if (ISD::isNON_EXTLoad(N)) {
2645 *LD = cast<LoadSDNode>(N);
2652 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2653 /// match movlp{s|d}. The lower half elements should come from lower half of
2654 /// V1 (and in order), and the upper half elements should come from the upper
2655 /// half of V2 (and in order). And since V1 will become the source of the
2656 /// MOVLP, it must be either a vector load or a scalar load to vector.
2657 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2658 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2660 // Is V2 is a vector load, don't do this transformation. We will try to use
2661 // load folding shufps op.
2662 if (ISD::isNON_EXTLoad(V2))
2665 unsigned NumElems = Mask->getNumOperands();
2666 if (NumElems != 2 && NumElems != 4)
2668 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2669 if (!isUndefOrEqual(Mask->getOperand(i), i))
2671 for (unsigned i = NumElems/2; i != NumElems; ++i)
2672 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2677 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2679 static bool isSplatVector(SDNode *N) {
2680 if (N->getOpcode() != ISD::BUILD_VECTOR)
2683 SDOperand SplatValue = N->getOperand(0);
2684 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2685 if (N->getOperand(i) != SplatValue)
2690 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2692 static bool isUndefShuffle(SDNode *N) {
2693 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2696 SDOperand V1 = N->getOperand(0);
2697 SDOperand V2 = N->getOperand(1);
2698 SDOperand Mask = N->getOperand(2);
2699 unsigned NumElems = Mask.getNumOperands();
2700 for (unsigned i = 0; i != NumElems; ++i) {
2701 SDOperand Arg = Mask.getOperand(i);
2702 if (Arg.getOpcode() != ISD::UNDEF) {
2703 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2704 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2706 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2713 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2715 static inline bool isZeroNode(SDOperand Elt) {
2716 return ((isa<ConstantSDNode>(Elt) &&
2717 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2718 (isa<ConstantFPSDNode>(Elt) &&
2719 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2722 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2723 /// to an zero vector.
2724 static bool isZeroShuffle(SDNode *N) {
2725 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2728 SDOperand V1 = N->getOperand(0);
2729 SDOperand V2 = N->getOperand(1);
2730 SDOperand Mask = N->getOperand(2);
2731 unsigned NumElems = Mask.getNumOperands();
2732 for (unsigned i = 0; i != NumElems; ++i) {
2733 SDOperand Arg = Mask.getOperand(i);
2734 if (Arg.getOpcode() == ISD::UNDEF)
2737 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2738 if (Idx < NumElems) {
2739 unsigned Opc = V1.Val->getOpcode();
2740 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val))
2742 if (Opc != ISD::BUILD_VECTOR ||
2743 !isZeroNode(V1.Val->getOperand(Idx)))
2745 } else if (Idx >= NumElems) {
2746 unsigned Opc = V2.Val->getOpcode();
2747 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val))
2749 if (Opc != ISD::BUILD_VECTOR ||
2750 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2757 /// getZeroVector - Returns a vector of specified type with all zero elements.
2759 static SDOperand getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
2760 assert(VT.isVector() && "Expected a vector type");
2762 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2763 // type. This ensures they get CSE'd.
2765 if (VT.getSizeInBits() == 64) { // MMX
2766 SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
2767 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2768 } else if (HasSSE2) { // SSE2
2769 SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
2770 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2772 SDOperand Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2773 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
2775 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2778 /// getOnesVector - Returns a vector of specified type with all bits set.
2780 static SDOperand getOnesVector(MVT VT, SelectionDAG &DAG) {
2781 assert(VT.isVector() && "Expected a vector type");
2783 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2784 // type. This ensures they get CSE'd.
2785 SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32);
2787 if (VT.getSizeInBits() == 64) // MMX
2788 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2790 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2791 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2795 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2796 /// that point to V2 points to its first element.
2797 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2798 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2800 bool Changed = false;
2801 SmallVector<SDOperand, 8> MaskVec;
2802 unsigned NumElems = Mask.getNumOperands();
2803 for (unsigned i = 0; i != NumElems; ++i) {
2804 SDOperand Arg = Mask.getOperand(i);
2805 if (Arg.getOpcode() != ISD::UNDEF) {
2806 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2807 if (Val > NumElems) {
2808 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2812 MaskVec.push_back(Arg);
2816 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2817 &MaskVec[0], MaskVec.size());
2821 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2822 /// operation of specified width.
2823 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2824 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2825 MVT BaseVT = MaskVT.getVectorElementType();
2827 SmallVector<SDOperand, 8> MaskVec;
2828 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2829 for (unsigned i = 1; i != NumElems; ++i)
2830 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2831 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2834 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2835 /// of specified width.
2836 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2837 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2838 MVT BaseVT = MaskVT.getVectorElementType();
2839 SmallVector<SDOperand, 8> MaskVec;
2840 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2841 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2842 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2844 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2847 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2848 /// of specified width.
2849 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2850 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2851 MVT BaseVT = MaskVT.getVectorElementType();
2852 unsigned Half = NumElems/2;
2853 SmallVector<SDOperand, 8> MaskVec;
2854 for (unsigned i = 0; i != Half; ++i) {
2855 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2856 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2858 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2861 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2862 /// element #0 of a vector with the specified index, leaving the rest of the
2863 /// elements in place.
2864 static SDOperand getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2865 SelectionDAG &DAG) {
2866 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2867 MVT BaseVT = MaskVT.getVectorElementType();
2868 SmallVector<SDOperand, 8> MaskVec;
2869 // Element #0 of the result gets the elt we are replacing.
2870 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2871 for (unsigned i = 1; i != NumElems; ++i)
2872 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2873 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2876 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2877 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG, bool HasSSE2) {
2878 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
2879 MVT VT = Op.getValueType();
2882 SDOperand V1 = Op.getOperand(0);
2883 SDOperand Mask = Op.getOperand(2);
2884 unsigned NumElems = Mask.getNumOperands();
2885 // Special handling of v4f32 -> v4i32.
2886 if (VT != MVT::v4f32) {
2887 Mask = getUnpacklMask(NumElems, DAG);
2888 while (NumElems > 4) {
2889 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2892 Mask = getZeroVector(MVT::v4i32, true, DAG);
2895 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
2896 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
2897 DAG.getNode(ISD::UNDEF, PVT), Mask);
2898 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2901 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2902 /// vector of zero or undef vector. This produces a shuffle where the low
2903 /// element of V2 is swizzled into the zero/undef vector, landing at element
2904 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
2905 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, unsigned Idx,
2906 bool isZero, bool HasSSE2,
2907 SelectionDAG &DAG) {
2908 MVT VT = V2.getValueType();
2909 SDOperand V1 = isZero
2910 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
2911 unsigned NumElems = V2.getValueType().getVectorNumElements();
2912 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2913 MVT EVT = MaskVT.getVectorElementType();
2914 SmallVector<SDOperand, 16> MaskVec;
2915 for (unsigned i = 0; i != NumElems; ++i)
2916 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
2917 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
2919 MaskVec.push_back(DAG.getConstant(i, EVT));
2920 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2921 &MaskVec[0], MaskVec.size());
2922 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2925 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
2926 /// a shuffle that is zero.
2928 unsigned getNumOfConsecutiveZeros(SDOperand Op, SDOperand Mask,
2929 unsigned NumElems, bool Low,
2930 SelectionDAG &DAG) {
2931 unsigned NumZeros = 0;
2932 for (unsigned i = 0; i < NumElems; ++i) {
2933 SDOperand Idx = Mask.getOperand(Low ? i : NumElems-i-1);
2934 if (Idx.getOpcode() == ISD::UNDEF) {
2938 unsigned Index = cast<ConstantSDNode>(Idx)->getValue();
2939 SDOperand Elt = DAG.getShuffleScalarElt(Op.Val, Index);
2940 if (Elt.Val && isZeroNode(Elt))
2948 /// isVectorShift - Returns true if the shuffle can be implemented as a
2949 /// logical left or right shift of a vector.
2950 static bool isVectorShift(SDOperand Op, SDOperand Mask, SelectionDAG &DAG,
2951 bool &isLeft, SDOperand &ShVal, unsigned &ShAmt) {
2952 unsigned NumElems = Mask.getNumOperands();
2955 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
2958 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
2963 bool SeenV1 = false;
2964 bool SeenV2 = false;
2965 for (unsigned i = NumZeros; i < NumElems; ++i) {
2966 unsigned Val = isLeft ? (i - NumZeros) : i;
2967 SDOperand Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
2968 if (Idx.getOpcode() == ISD::UNDEF)
2970 unsigned Index = cast<ConstantSDNode>(Idx)->getValue();
2971 if (Index < NumElems)
2980 if (SeenV1 && SeenV2)
2983 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
2989 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2991 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2992 unsigned NumNonZero, unsigned NumZero,
2993 SelectionDAG &DAG, TargetLowering &TLI) {
2999 for (unsigned i = 0; i < 16; ++i) {
3000 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3001 if (ThisIsNonZero && First) {
3003 V = getZeroVector(MVT::v8i16, true, DAG);
3005 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3010 SDOperand ThisElt(0, 0), LastElt(0, 0);
3011 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3012 if (LastIsNonZero) {
3013 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
3015 if (ThisIsNonZero) {
3016 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
3017 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
3018 ThisElt, DAG.getConstant(8, MVT::i8));
3020 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
3025 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
3026 DAG.getIntPtrConstant(i/2));
3030 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
3033 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3035 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
3036 unsigned NumNonZero, unsigned NumZero,
3037 SelectionDAG &DAG, TargetLowering &TLI) {
3043 for (unsigned i = 0; i < 8; ++i) {
3044 bool isNonZero = (NonZeros & (1 << i)) != 0;
3048 V = getZeroVector(MVT::v8i16, true, DAG);
3050 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3053 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
3054 DAG.getIntPtrConstant(i));
3061 /// getVShift - Return a vector logical shift node.
3063 static SDOperand getVShift(bool isLeft, MVT VT, SDOperand SrcOp,
3064 unsigned NumBits, SelectionDAG &DAG,
3065 const TargetLowering &TLI) {
3066 bool isMMX = VT.getSizeInBits() == 64;
3067 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3068 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3069 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
3070 return DAG.getNode(ISD::BIT_CONVERT, VT,
3071 DAG.getNode(Opc, ShVT, SrcOp,
3072 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3076 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3077 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3078 if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) {
3079 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3080 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3081 // eliminated on x86-32 hosts.
3082 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3085 if (ISD::isBuildVectorAllOnes(Op.Val))
3086 return getOnesVector(Op.getValueType(), DAG);
3087 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
3090 MVT VT = Op.getValueType();
3091 MVT EVT = VT.getVectorElementType();
3092 unsigned EVTBits = EVT.getSizeInBits();
3094 unsigned NumElems = Op.getNumOperands();
3095 unsigned NumZero = 0;
3096 unsigned NumNonZero = 0;
3097 unsigned NonZeros = 0;
3098 bool IsAllConstants = true;
3099 SmallSet<SDOperand, 8> Values;
3100 for (unsigned i = 0; i < NumElems; ++i) {
3101 SDOperand Elt = Op.getOperand(i);
3102 if (Elt.getOpcode() == ISD::UNDEF)
3105 if (Elt.getOpcode() != ISD::Constant &&
3106 Elt.getOpcode() != ISD::ConstantFP)
3107 IsAllConstants = false;
3108 if (isZeroNode(Elt))
3111 NonZeros |= (1 << i);
3116 if (NumNonZero == 0) {
3117 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3118 return DAG.getNode(ISD::UNDEF, VT);
3121 // Special case for single non-zero, non-undef, element.
3122 if (NumNonZero == 1 && NumElems <= 4) {
3123 unsigned Idx = CountTrailingZeros_32(NonZeros);
3124 SDOperand Item = Op.getOperand(Idx);
3126 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3127 // the value are obviously zero, truncate the value to i32 and do the
3128 // insertion that way. Only do this if the value is non-constant or if the
3129 // value is a constant being inserted into element 0. It is cheaper to do
3130 // a constant pool load than it is to do a movd + shuffle.
3131 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3132 (!IsAllConstants || Idx == 0)) {
3133 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3134 // Handle MMX and SSE both.
3135 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3136 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3138 // Truncate the value (which may itself be a constant) to i32, and
3139 // convert it to a vector with movd (S2V+shuffle to zero extend).
3140 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3141 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
3142 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3143 Subtarget->hasSSE2(), DAG);
3145 // Now we have our 32-bit value zero extended in the low element of
3146 // a vector. If Idx != 0, swizzle it into place.
3149 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3150 getSwapEltZeroMask(VecElts, Idx, DAG)
3152 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3154 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3158 // If we have a constant or non-constant insertion into the low element of
3159 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3160 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3161 // depending on what the source datatype is. Because we can only get here
3162 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3164 // Don't do this for i64 values on x86-32.
3165 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3166 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3167 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3168 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3169 Subtarget->hasSSE2(), DAG);
3172 // Is it a vector logical left shift?
3173 if (NumElems == 2 && Idx == 1 &&
3174 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3175 unsigned NumBits = VT.getSizeInBits();
3176 return getVShift(true, VT,
3177 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
3178 NumBits/2, DAG, *this);
3181 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3184 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3185 // is a non-constant being inserted into an element other than the low one,
3186 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3187 // movd/movss) to move this into the low element, then shuffle it into
3189 if (EVTBits == 32) {
3190 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3192 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3193 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3194 Subtarget->hasSSE2(), DAG);
3195 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3196 MVT MaskEVT = MaskVT.getVectorElementType();
3197 SmallVector<SDOperand, 8> MaskVec;
3198 for (unsigned i = 0; i < NumElems; i++)
3199 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3200 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3201 &MaskVec[0], MaskVec.size());
3202 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3203 DAG.getNode(ISD::UNDEF, VT), Mask);
3207 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3208 if (Values.size() == 1)
3211 // A vector full of immediates; various special cases are already
3212 // handled, so this is best done with a single constant-pool load.
3216 // Let legalizer expand 2-wide build_vectors.
3217 if (EVTBits == 64) {
3218 if (NumNonZero == 1) {
3219 // One half is zero or undef.
3220 unsigned Idx = CountTrailingZeros_32(NonZeros);
3221 SDOperand V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
3222 Op.getOperand(Idx));
3223 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3224 Subtarget->hasSSE2(), DAG);
3229 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3230 if (EVTBits == 8 && NumElems == 16) {
3231 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3233 if (V.Val) return V;
3236 if (EVTBits == 16 && NumElems == 8) {
3237 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3239 if (V.Val) return V;
3242 // If element VT is == 32 bits, turn it into a number of shuffles.
3243 SmallVector<SDOperand, 8> V;
3245 if (NumElems == 4 && NumZero > 0) {
3246 for (unsigned i = 0; i < 4; ++i) {
3247 bool isZero = !(NonZeros & (1 << i));
3249 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3251 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3254 for (unsigned i = 0; i < 2; ++i) {
3255 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3258 V[i] = V[i*2]; // Must be a zero vector.
3261 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3262 getMOVLMask(NumElems, DAG));
3265 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3266 getMOVLMask(NumElems, DAG));
3269 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3270 getUnpacklMask(NumElems, DAG));
3275 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3276 MVT EVT = MaskVT.getVectorElementType();
3277 SmallVector<SDOperand, 8> MaskVec;
3278 bool Reverse = (NonZeros & 0x3) == 2;
3279 for (unsigned i = 0; i < 2; ++i)
3281 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3283 MaskVec.push_back(DAG.getConstant(i, EVT));
3284 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3285 for (unsigned i = 0; i < 2; ++i)
3287 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3289 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3290 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3291 &MaskVec[0], MaskVec.size());
3292 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3295 if (Values.size() > 2) {
3296 // Expand into a number of unpckl*.
3298 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3299 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3300 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3301 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
3302 for (unsigned i = 0; i < NumElems; ++i)
3303 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3305 while (NumElems != 0) {
3306 for (unsigned i = 0; i < NumElems; ++i)
3307 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3318 SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
3319 SDOperand PermMask, SelectionDAG &DAG,
3320 TargetLowering &TLI) {
3322 MVT MaskVT = MVT::getIntVectorWithNumElements(8);
3323 MVT MaskEVT = MaskVT.getVectorElementType();
3324 MVT PtrVT = TLI.getPointerTy();
3325 SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(),
3326 PermMask.Val->op_end());
3328 // First record which half of which vector the low elements come from.
3329 SmallVector<unsigned, 4> LowQuad(4);
3330 for (unsigned i = 0; i < 4; ++i) {
3331 SDOperand Elt = MaskElts[i];
3332 if (Elt.getOpcode() == ISD::UNDEF)
3334 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3335 int QuadIdx = EltIdx / 4;
3338 int BestLowQuad = -1;
3339 unsigned MaxQuad = 1;
3340 for (unsigned i = 0; i < 4; ++i) {
3341 if (LowQuad[i] > MaxQuad) {
3343 MaxQuad = LowQuad[i];
3347 // Record which half of which vector the high elements come from.
3348 SmallVector<unsigned, 4> HighQuad(4);
3349 for (unsigned i = 4; i < 8; ++i) {
3350 SDOperand Elt = MaskElts[i];
3351 if (Elt.getOpcode() == ISD::UNDEF)
3353 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3354 int QuadIdx = EltIdx / 4;
3355 ++HighQuad[QuadIdx];
3357 int BestHighQuad = -1;
3359 for (unsigned i = 0; i < 4; ++i) {
3360 if (HighQuad[i] > MaxQuad) {
3362 MaxQuad = HighQuad[i];
3366 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3367 if (BestLowQuad != -1 || BestHighQuad != -1) {
3368 // First sort the 4 chunks in order using shufpd.
3369 SmallVector<SDOperand, 8> MaskVec;
3370 if (BestLowQuad != -1)
3371 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3373 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3374 if (BestHighQuad != -1)
3375 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3377 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3378 SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3379 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3380 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3381 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3382 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3384 // Now sort high and low parts separately.
3385 BitVector InOrder(8);
3386 if (BestLowQuad != -1) {
3387 // Sort lower half in order using PSHUFLW.
3389 bool AnyOutOrder = false;
3390 for (unsigned i = 0; i != 4; ++i) {
3391 SDOperand Elt = MaskElts[i];
3392 if (Elt.getOpcode() == ISD::UNDEF) {
3393 MaskVec.push_back(Elt);
3396 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3399 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3400 // If this element is in the right place after this shuffle, then
3402 if ((int)(EltIdx / 4) == BestLowQuad)
3407 for (unsigned i = 4; i != 8; ++i)
3408 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3409 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3410 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3414 if (BestHighQuad != -1) {
3415 // Sort high half in order using PSHUFHW if possible.
3417 for (unsigned i = 0; i != 4; ++i)
3418 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3419 bool AnyOutOrder = false;
3420 for (unsigned i = 4; i != 8; ++i) {
3421 SDOperand Elt = MaskElts[i];
3422 if (Elt.getOpcode() == ISD::UNDEF) {
3423 MaskVec.push_back(Elt);
3426 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3429 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3430 // If this element is in the right place after this shuffle, then
3432 if ((int)(EltIdx / 4) == BestHighQuad)
3437 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3438 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3442 // The other elements are put in the right place using pextrw and pinsrw.
3443 for (unsigned i = 0; i != 8; ++i) {
3446 SDOperand Elt = MaskElts[i];
3447 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3448 SDOperand ExtOp = (EltIdx < 8)
3449 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3450 DAG.getConstant(EltIdx, PtrVT))
3451 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3452 DAG.getConstant(EltIdx - 8, PtrVT));
3453 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3454 DAG.getConstant(i, PtrVT));
3459 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use
3460 ///as few as possible.
3461 // First, let's find out how many elements are already in the right order.
3462 unsigned V1InOrder = 0;
3463 unsigned V1FromV1 = 0;
3464 unsigned V2InOrder = 0;
3465 unsigned V2FromV2 = 0;
3466 SmallVector<SDOperand, 8> V1Elts;
3467 SmallVector<SDOperand, 8> V2Elts;
3468 for (unsigned i = 0; i < 8; ++i) {
3469 SDOperand Elt = MaskElts[i];
3470 if (Elt.getOpcode() == ISD::UNDEF) {
3471 V1Elts.push_back(Elt);
3472 V2Elts.push_back(Elt);
3477 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3479 V1Elts.push_back(Elt);
3480 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3482 } else if (EltIdx == i+8) {
3483 V1Elts.push_back(Elt);
3484 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3486 } else if (EltIdx < 8) {
3487 V1Elts.push_back(Elt);
3490 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3495 if (V2InOrder > V1InOrder) {
3496 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3498 std::swap(V1Elts, V2Elts);
3499 std::swap(V1FromV1, V2FromV2);
3502 if ((V1FromV1 + V1InOrder) != 8) {
3503 // Some elements are from V2.
3505 // If there are elements that are from V1 but out of place,
3506 // then first sort them in place
3507 SmallVector<SDOperand, 8> MaskVec;
3508 for (unsigned i = 0; i < 8; ++i) {
3509 SDOperand Elt = V1Elts[i];
3510 if (Elt.getOpcode() == ISD::UNDEF) {
3511 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3514 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3516 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3518 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3520 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3521 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3525 for (unsigned i = 0; i < 8; ++i) {
3526 SDOperand Elt = V1Elts[i];
3527 if (Elt.getOpcode() == ISD::UNDEF)
3529 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3532 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3533 DAG.getConstant(EltIdx - 8, PtrVT));
3534 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3535 DAG.getConstant(i, PtrVT));
3539 // All elements are from V1.
3541 for (unsigned i = 0; i < 8; ++i) {
3542 SDOperand Elt = V1Elts[i];
3543 if (Elt.getOpcode() == ISD::UNDEF)
3545 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3546 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3547 DAG.getConstant(EltIdx, PtrVT));
3548 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3549 DAG.getConstant(i, PtrVT));
3555 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3556 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3557 /// done when every pair / quad of shuffle mask elements point to elements in
3558 /// the right sequence. e.g.
3559 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3561 SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
3563 SDOperand PermMask, SelectionDAG &DAG,
3564 TargetLowering &TLI) {
3565 unsigned NumElems = PermMask.getNumOperands();
3566 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3567 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3569 switch (VT.getSimpleVT()) {
3570 default: assert(false && "Unexpected!");
3571 case MVT::v4f32: NewVT = MVT::v2f64; break;
3572 case MVT::v4i32: NewVT = MVT::v2i64; break;
3573 case MVT::v8i16: NewVT = MVT::v4i32; break;
3574 case MVT::v16i8: NewVT = MVT::v4i32; break;
3577 if (NewWidth == 2) {
3583 unsigned Scale = NumElems / NewWidth;
3584 SmallVector<SDOperand, 8> MaskVec;
3585 for (unsigned i = 0; i < NumElems; i += Scale) {
3586 unsigned StartIdx = ~0U;
3587 for (unsigned j = 0; j < Scale; ++j) {
3588 SDOperand Elt = PermMask.getOperand(i+j);
3589 if (Elt.getOpcode() == ISD::UNDEF)
3591 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3592 if (StartIdx == ~0U)
3593 StartIdx = EltIdx - (EltIdx % Scale);
3594 if (EltIdx != StartIdx + j)
3597 if (StartIdx == ~0U)
3598 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
3600 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MVT::i32));
3603 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3604 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3605 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3606 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3607 &MaskVec[0], MaskVec.size()));
3610 /// getVZextMovL - Return a zero-extending vector move low node.
3612 static SDOperand getVZextMovL(MVT VT, MVT OpVT,
3613 SDOperand SrcOp, SelectionDAG &DAG,
3614 const X86Subtarget *Subtarget) {
3615 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3616 LoadSDNode *LD = NULL;
3617 if (!isScalarLoadToVector(SrcOp.Val, &LD))
3618 LD = dyn_cast<LoadSDNode>(SrcOp);
3620 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3622 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3623 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3624 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3625 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3626 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3628 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3629 return DAG.getNode(ISD::BIT_CONVERT, VT,
3630 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3631 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
3632 SrcOp.getOperand(0).getOperand(0))));
3637 return DAG.getNode(ISD::BIT_CONVERT, VT,
3638 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3639 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
3643 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
3644 SDOperand V1 = Op.getOperand(0);
3645 SDOperand V2 = Op.getOperand(1);
3646 SDOperand PermMask = Op.getOperand(2);
3647 MVT VT = Op.getValueType();
3648 unsigned NumElems = PermMask.getNumOperands();
3649 bool isMMX = VT.getSizeInBits() == 64;
3650 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3651 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3652 bool V1IsSplat = false;
3653 bool V2IsSplat = false;
3655 if (isUndefShuffle(Op.Val))
3656 return DAG.getNode(ISD::UNDEF, VT);
3658 if (isZeroShuffle(Op.Val))
3659 return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3661 if (isIdentityMask(PermMask.Val))
3663 else if (isIdentityMask(PermMask.Val, true))
3666 if (isSplatMask(PermMask.Val)) {
3667 if (isMMX || NumElems < 4) return Op;
3668 // Promote it to a v4{if}32 splat.
3669 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
3672 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3674 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3675 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3677 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3678 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3679 // FIXME: Figure out a cleaner way to do this.
3680 // Try to make use of movq to zero out the top part.
3681 if (ISD::isBuildVectorAllZeros(V2.Val)) {
3682 SDOperand NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
3685 SDOperand NewV1 = NewOp.getOperand(0);
3686 SDOperand NewV2 = NewOp.getOperand(1);
3687 SDOperand NewMask = NewOp.getOperand(2);
3688 if (isCommutedMOVL(NewMask.Val, true, false)) {
3689 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
3690 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
3693 } else if (ISD::isBuildVectorAllZeros(V1.Val)) {
3694 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
3696 if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
3697 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
3702 // Check if this can be converted into a logical shift.
3703 bool isLeft = false;
3706 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
3707 if (isShift && ShVal.hasOneUse()) {
3708 // If the shifted value has multiple uses, it may be cheaper to use
3709 // v_set0 + movlhps or movhlps, etc.
3710 MVT EVT = VT.getVectorElementType();
3711 ShAmt *= EVT.getSizeInBits();
3712 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
3715 if (X86::isMOVLMask(PermMask.Val)) {
3718 if (ISD::isBuildVectorAllZeros(V1.Val))
3719 return getVZextMovL(VT, VT, V2, DAG, Subtarget);
3723 if (X86::isMOVSHDUPMask(PermMask.Val) ||
3724 X86::isMOVSLDUPMask(PermMask.Val) ||
3725 X86::isMOVHLPSMask(PermMask.Val) ||
3726 X86::isMOVHPMask(PermMask.Val) ||
3727 X86::isMOVLPMask(PermMask.Val))
3730 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3731 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
3732 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3735 // No better options. Use a vshl / vsrl.
3736 MVT EVT = VT.getVectorElementType();
3737 ShAmt *= EVT.getSizeInBits();
3738 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
3741 bool Commuted = false;
3742 // FIXME: This should also accept a bitcast of a splat? Be careful, not
3743 // 1,1,1,1 -> v8i16 though.
3744 V1IsSplat = isSplatVector(V1.Val);
3745 V2IsSplat = isSplatVector(V2.Val);
3747 // Canonicalize the splat or undef, if present, to be on the RHS.
3748 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3749 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3750 std::swap(V1IsSplat, V2IsSplat);
3751 std::swap(V1IsUndef, V2IsUndef);
3755 // FIXME: Figure out a cleaner way to do this.
3756 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3757 if (V2IsUndef) return V1;
3758 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3760 // V2 is a splat, so the mask may be malformed. That is, it may point
3761 // to any V2 element. The instruction selectior won't like this. Get
3762 // a corrected mask and commute to form a proper MOVS{S|D}.
3763 SDOperand NewMask = getMOVLMask(NumElems, DAG);
3764 if (NewMask.Val != PermMask.Val)
3765 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3770 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3771 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3772 X86::isUNPCKLMask(PermMask.Val) ||
3773 X86::isUNPCKHMask(PermMask.Val))
3777 // Normalize mask so all entries that point to V2 points to its first
3778 // element then try to match unpck{h|l} again. If match, return a
3779 // new vector_shuffle with the corrected mask.
3780 SDOperand NewMask = NormalizeMask(PermMask, DAG);
3781 if (NewMask.Val != PermMask.Val) {
3782 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3783 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
3784 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3785 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3786 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
3787 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3792 // Normalize the node to match x86 shuffle ops if needed
3793 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3794 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3797 // Commute is back and try unpck* again.
3798 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3799 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3800 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3801 X86::isUNPCKLMask(PermMask.Val) ||
3802 X86::isUNPCKHMask(PermMask.Val))
3806 // Try PSHUF* first, then SHUFP*.
3807 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
3808 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
3809 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.Val)) {
3810 if (V2.getOpcode() != ISD::UNDEF)
3811 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3812 DAG.getNode(ISD::UNDEF, VT), PermMask);
3817 if (Subtarget->hasSSE2() &&
3818 (X86::isPSHUFDMask(PermMask.Val) ||
3819 X86::isPSHUFHWMask(PermMask.Val) ||
3820 X86::isPSHUFLWMask(PermMask.Val))) {
3822 if (VT == MVT::v4f32) {
3824 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
3825 DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
3826 DAG.getNode(ISD::UNDEF, RVT), PermMask);
3827 } else if (V2.getOpcode() != ISD::UNDEF)
3828 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
3829 DAG.getNode(ISD::UNDEF, RVT), PermMask);
3831 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
3835 // Binary or unary shufps.
3836 if (X86::isSHUFPMask(PermMask.Val) ||
3837 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.Val)))
3841 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
3842 if (VT == MVT::v8i16) {
3843 SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
3848 // Handle all 4 wide cases with a number of shuffles.
3849 if (NumElems == 4 && !isMMX) {
3850 // Don't do this for MMX.
3851 MVT MaskVT = PermMask.getValueType();
3852 MVT MaskEVT = MaskVT.getVectorElementType();
3853 SmallVector<std::pair<int, int>, 8> Locs;
3854 Locs.reserve(NumElems);
3855 SmallVector<SDOperand, 8> Mask1(NumElems,
3856 DAG.getNode(ISD::UNDEF, MaskEVT));
3857 SmallVector<SDOperand, 8> Mask2(NumElems,
3858 DAG.getNode(ISD::UNDEF, MaskEVT));
3861 // If no more than two elements come from either vector. This can be
3862 // implemented with two shuffles. First shuffle gather the elements.
3863 // The second shuffle, which takes the first shuffle as both of its
3864 // vector operands, put the elements into the right order.
3865 for (unsigned i = 0; i != NumElems; ++i) {
3866 SDOperand Elt = PermMask.getOperand(i);
3867 if (Elt.getOpcode() == ISD::UNDEF) {
3868 Locs[i] = std::make_pair(-1, -1);
3870 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3871 if (Val < NumElems) {
3872 Locs[i] = std::make_pair(0, NumLo);
3876 Locs[i] = std::make_pair(1, NumHi);
3877 if (2+NumHi < NumElems)
3878 Mask1[2+NumHi] = Elt;
3883 if (NumLo <= 2 && NumHi <= 2) {
3884 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3885 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3886 &Mask1[0], Mask1.size()));
3887 for (unsigned i = 0; i != NumElems; ++i) {
3888 if (Locs[i].first == -1)
3891 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3892 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3893 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3897 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3898 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3899 &Mask2[0], Mask2.size()));
3902 // Break it into (shuffle shuffle_hi, shuffle_lo).
3904 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3905 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3906 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
3907 unsigned MaskIdx = 0;
3909 unsigned HiIdx = NumElems/2;
3910 for (unsigned i = 0; i != NumElems; ++i) {
3911 if (i == NumElems/2) {
3917 SDOperand Elt = PermMask.getOperand(i);
3918 if (Elt.getOpcode() == ISD::UNDEF) {
3919 Locs[i] = std::make_pair(-1, -1);
3920 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3921 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3922 (*MaskPtr)[LoIdx] = Elt;
3925 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3926 (*MaskPtr)[HiIdx] = Elt;
3931 SDOperand LoShuffle =
3932 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3933 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3934 &LoMask[0], LoMask.size()));
3935 SDOperand HiShuffle =
3936 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3937 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3938 &HiMask[0], HiMask.size()));
3939 SmallVector<SDOperand, 8> MaskOps;
3940 for (unsigned i = 0; i != NumElems; ++i) {
3941 if (Locs[i].first == -1) {
3942 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3944 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3945 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3948 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3949 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3950 &MaskOps[0], MaskOps.size()));
3957 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDOperand Op,
3958 SelectionDAG &DAG) {
3959 MVT VT = Op.getValueType();
3960 if (VT.getSizeInBits() == 8) {
3961 SDOperand Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
3962 Op.getOperand(0), Op.getOperand(1));
3963 SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
3964 DAG.getValueType(VT));
3965 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3966 } else if (VT.getSizeInBits() == 16) {
3967 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
3968 Op.getOperand(0), Op.getOperand(1));
3969 SDOperand Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
3970 DAG.getValueType(VT));
3971 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3972 } else if (VT == MVT::f32) {
3973 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
3974 // the result back to FR32 register. It's only worth matching if the
3975 // result has a single use which is a store or a bitcast to i32.
3976 if (!Op.hasOneUse())
3978 SDNode *User = Op.Val->use_begin()->getUser();
3979 if (User->getOpcode() != ISD::STORE &&
3980 (User->getOpcode() != ISD::BIT_CONVERT ||
3981 User->getValueType(0) != MVT::i32))
3983 SDOperand Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
3984 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
3986 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
3993 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3994 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3997 if (Subtarget->hasSSE41()) {
3998 SDOperand Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4003 MVT VT = Op.getValueType();
4004 // TODO: handle v16i8.
4005 if (VT.getSizeInBits() == 16) {
4006 SDOperand Vec = Op.getOperand(0);
4007 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4009 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4010 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4011 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
4013 // Transform it so it match pextrw which produces a 32-bit result.
4014 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4015 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
4016 Op.getOperand(0), Op.getOperand(1));
4017 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
4018 DAG.getValueType(VT));
4019 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4020 } else if (VT.getSizeInBits() == 32) {
4021 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4024 // SHUFPS the element to the lowest double word, then movss.
4025 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4026 SmallVector<SDOperand, 8> IdxVec;
4028 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4030 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4032 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4034 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4035 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4036 &IdxVec[0], IdxVec.size());
4037 SDOperand Vec = Op.getOperand(0);
4038 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4039 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4040 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4041 DAG.getIntPtrConstant(0));
4042 } else if (VT.getSizeInBits() == 64) {
4043 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4044 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4045 // to match extract_elt for f64.
4046 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
4050 // UNPCKHPD the element to the lowest double word, then movsd.
4051 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4052 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4053 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4054 SmallVector<SDOperand, 8> IdxVec;
4055 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4057 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4058 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4059 &IdxVec[0], IdxVec.size());
4060 SDOperand Vec = Op.getOperand(0);
4061 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4062 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4063 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4064 DAG.getIntPtrConstant(0));
4071 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDOperand Op, SelectionDAG &DAG){
4072 MVT VT = Op.getValueType();
4073 MVT EVT = VT.getVectorElementType();
4075 SDOperand N0 = Op.getOperand(0);
4076 SDOperand N1 = Op.getOperand(1);
4077 SDOperand N2 = Op.getOperand(2);
4079 if ((EVT.getSizeInBits() == 8) || (EVT.getSizeInBits() == 16)) {
4080 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4082 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4084 if (N1.getValueType() != MVT::i32)
4085 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4086 if (N2.getValueType() != MVT::i32)
4087 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
4088 return DAG.getNode(Opc, VT, N0, N1, N2);
4089 } else if (EVT == MVT::f32) {
4090 // Bits [7:6] of the constant are the source select. This will always be
4091 // zero here. The DAG Combiner may combine an extract_elt index into these
4092 // bits. For example (insert (extract, 3), 2) could be matched by putting
4093 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4094 // Bits [5:4] of the constant are the destination select. This is the
4095 // value of the incoming immediate.
4096 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4097 // combine either bitwise AND or insert of float 0.0 to set these bits.
4098 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue() << 4);
4099 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
4105 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
4106 MVT VT = Op.getValueType();
4107 MVT EVT = VT.getVectorElementType();
4109 if (Subtarget->hasSSE41())
4110 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4115 SDOperand N0 = Op.getOperand(0);
4116 SDOperand N1 = Op.getOperand(1);
4117 SDOperand N2 = Op.getOperand(2);
4119 if (EVT.getSizeInBits() == 16) {
4120 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4121 // as its second argument.
4122 if (N1.getValueType() != MVT::i32)
4123 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4124 if (N2.getValueType() != MVT::i32)
4125 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
4126 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
4132 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
4133 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
4134 MVT VT = MVT::v2i32;
4135 switch (Op.getValueType().getSimpleVT()) {
4142 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
4143 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
4146 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4147 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4148 // one of the above mentioned nodes. It has to be wrapped because otherwise
4149 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4150 // be used to form addressing mode. These wrapped nodes will be selected
4153 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
4154 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4155 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
4157 CP->getAlignment());
4158 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4159 // With PIC, the address is actually $g + Offset.
4160 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4161 !Subtarget->isPICStyleRIPRel()) {
4162 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4163 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4171 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
4172 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4173 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
4174 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4175 // With PIC, the address is actually $g + Offset.
4176 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4177 !Subtarget->isPICStyleRIPRel()) {
4178 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4179 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4183 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4184 // load the value at address GV, not the value of GV itself. This means that
4185 // the GlobalAddress must be in the base or index register of the address, not
4186 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4187 // The same applies for external symbols during PIC codegen
4188 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
4189 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
4190 PseudoSourceValue::getGOT(), 0);
4195 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4197 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4200 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
4201 DAG.getNode(X86ISD::GlobalBaseReg,
4203 InFlag = Chain.getValue(1);
4205 // emit leal symbol@TLSGD(,%ebx,1), %eax
4206 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4207 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4208 GA->getValueType(0),
4210 SDOperand Ops[] = { Chain, TGA, InFlag };
4211 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
4212 InFlag = Result.getValue(2);
4213 Chain = Result.getValue(1);
4215 // call ___tls_get_addr. This function receives its argument in
4216 // the register EAX.
4217 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4218 InFlag = Chain.getValue(1);
4220 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4221 SDOperand Ops1[] = { Chain,
4222 DAG.getTargetExternalSymbol("___tls_get_addr",
4224 DAG.getRegister(X86::EAX, PtrVT),
4225 DAG.getRegister(X86::EBX, PtrVT),
4227 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4228 InFlag = Chain.getValue(1);
4230 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4233 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4235 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4237 SDOperand InFlag, Chain;
4239 // emit leaq symbol@TLSGD(%rip), %rdi
4240 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4241 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4242 GA->getValueType(0),
4244 SDOperand Ops[] = { DAG.getEntryNode(), TGA};
4245 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
4246 Chain = Result.getValue(1);
4247 InFlag = Result.getValue(2);
4249 // call ___tls_get_addr. This function receives its argument in
4250 // the register RDI.
4251 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
4252 InFlag = Chain.getValue(1);
4254 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4255 SDOperand Ops1[] = { Chain,
4256 DAG.getTargetExternalSymbol("___tls_get_addr",
4258 DAG.getRegister(X86::RDI, PtrVT),
4260 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
4261 InFlag = Chain.getValue(1);
4263 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
4266 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4267 // "local exec" model.
4268 static SDOperand LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4270 // Get the Thread Pointer
4271 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
4272 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4274 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4275 GA->getValueType(0),
4277 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
4279 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
4280 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
4281 PseudoSourceValue::getGOT(), 0);
4283 // The address of the thread local variable is the add of the thread
4284 // pointer with the offset of the variable.
4285 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4289 X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
4290 // TODO: implement the "local dynamic" model
4291 // TODO: implement the "initial exec"model for pic executables
4292 assert(Subtarget->isTargetELF() &&
4293 "TLS not implemented for non-ELF targets");
4294 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4295 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4296 // otherwise use the "Local Exec"TLS Model
4297 if (Subtarget->is64Bit()) {
4298 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4300 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4301 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4303 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4308 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
4309 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4310 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4311 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4312 // With PIC, the address is actually $g + Offset.
4313 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4314 !Subtarget->isPICStyleRIPRel()) {
4315 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4316 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4323 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
4324 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4325 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4326 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4327 // With PIC, the address is actually $g + Offset.
4328 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4329 !Subtarget->isPICStyleRIPRel()) {
4330 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4331 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4338 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4339 /// take a 2 x i32 value to shift plus a shift amount.
4340 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
4341 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4342 MVT VT = Op.getValueType();
4343 unsigned VTBits = VT.getSizeInBits();
4344 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4345 SDOperand ShOpLo = Op.getOperand(0);
4346 SDOperand ShOpHi = Op.getOperand(1);
4347 SDOperand ShAmt = Op.getOperand(2);
4348 SDOperand Tmp1 = isSRA ?
4349 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4350 DAG.getConstant(0, VT);
4352 SDOperand Tmp2, Tmp3;
4353 if (Op.getOpcode() == ISD::SHL_PARTS) {
4354 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4355 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
4357 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4358 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
4361 const MVT *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4362 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
4363 DAG.getConstant(VTBits, MVT::i8));
4364 SDOperand Cond = DAG.getNode(X86ISD::CMP, VT,
4365 AndNode, DAG.getConstant(0, MVT::i8));
4368 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4369 VTs = DAG.getNodeValueTypes(VT, MVT::Flag);
4370 SmallVector<SDOperand, 4> Ops;
4371 if (Op.getOpcode() == ISD::SHL_PARTS) {
4372 Ops.push_back(Tmp2);
4373 Ops.push_back(Tmp3);
4375 Ops.push_back(Cond);
4376 Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
4379 Ops.push_back(Tmp3);
4380 Ops.push_back(Tmp1);
4382 Ops.push_back(Cond);
4383 Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
4385 Ops.push_back(Tmp2);
4386 Ops.push_back(Tmp3);
4388 Ops.push_back(Cond);
4389 Lo = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
4392 Ops.push_back(Tmp3);
4393 Ops.push_back(Tmp1);
4395 Ops.push_back(Cond);
4396 Hi = DAG.getNode(X86ISD::CMOV, VT, &Ops[0], Ops.size());
4399 VTs = DAG.getNodeValueTypes(VT, VT);
4403 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
4406 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
4407 MVT SrcVT = Op.getOperand(0).getValueType();
4408 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4409 "Unknown SINT_TO_FP to lower!");
4411 // These are really Legal; caller falls through into that case.
4412 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4414 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4415 Subtarget->is64Bit())
4418 unsigned Size = SrcVT.getSizeInBits()/8;
4419 MachineFunction &MF = DAG.getMachineFunction();
4420 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4421 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4422 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
4424 PseudoSourceValue::getFixedStack(),
4429 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4431 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4433 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4434 SmallVector<SDOperand, 8> Ops;
4435 Ops.push_back(Chain);
4436 Ops.push_back(StackSlot);
4437 Ops.push_back(DAG.getValueType(SrcVT));
4438 SDOperand Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4439 Tys, &Ops[0], Ops.size());
4442 Chain = Result.getValue(1);
4443 SDOperand InFlag = Result.getValue(2);
4445 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4446 // shouldn't be necessary except that RFP cannot be live across
4447 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4448 MachineFunction &MF = DAG.getMachineFunction();
4449 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4450 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4451 Tys = DAG.getVTList(MVT::Other);
4452 SmallVector<SDOperand, 8> Ops;
4453 Ops.push_back(Chain);
4454 Ops.push_back(Result);
4455 Ops.push_back(StackSlot);
4456 Ops.push_back(DAG.getValueType(Op.getValueType()));
4457 Ops.push_back(InFlag);
4458 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4459 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
4460 PseudoSourceValue::getFixedStack(), SSFI);
4466 std::pair<SDOperand,SDOperand> X86TargetLowering::
4467 FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
4468 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
4469 Op.getValueType().getSimpleVT() >= MVT::i16 &&
4470 "Unknown FP_TO_SINT to lower!");
4472 // These are really Legal.
4473 if (Op.getValueType() == MVT::i32 &&
4474 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
4475 return std::make_pair(SDOperand(), SDOperand());
4476 if (Subtarget->is64Bit() &&
4477 Op.getValueType() == MVT::i64 &&
4478 Op.getOperand(0).getValueType() != MVT::f80)
4479 return std::make_pair(SDOperand(), SDOperand());
4481 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4483 MachineFunction &MF = DAG.getMachineFunction();
4484 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
4485 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4486 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4488 switch (Op.getValueType().getSimpleVT()) {
4489 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4490 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4491 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4492 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4495 SDOperand Chain = DAG.getEntryNode();
4496 SDOperand Value = Op.getOperand(0);
4497 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
4498 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4499 Chain = DAG.getStore(Chain, Value, StackSlot,
4500 PseudoSourceValue::getFixedStack(), SSFI);
4501 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
4503 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4505 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
4506 Chain = Value.getValue(1);
4507 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4508 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4511 // Build the FP_TO_INT*_IN_MEM
4512 SDOperand Ops[] = { Chain, Value, StackSlot };
4513 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
4515 return std::make_pair(FIST, StackSlot);
4518 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
4519 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(Op, DAG);
4520 SDOperand FIST = Vals.first, StackSlot = Vals.second;
4521 if (FIST.Val == 0) return SDOperand();
4524 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4527 SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
4528 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG);
4529 SDOperand FIST = Vals.first, StackSlot = Vals.second;
4530 if (FIST.Val == 0) return 0;
4532 // Return an i64 load from the stack slot.
4533 SDOperand Res = DAG.getLoad(MVT::i64, FIST, StackSlot, NULL, 0);
4535 // Use a MERGE_VALUES node to drop the chain result value.
4536 return DAG.getNode(ISD::MERGE_VALUES, MVT::i64, Res).Val;
4539 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
4540 MVT VT = Op.getValueType();
4543 EltVT = VT.getVectorElementType();
4544 std::vector<Constant*> CV;
4545 if (EltVT == MVT::f64) {
4546 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
4550 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
4556 Constant *C = ConstantVector::get(CV);
4557 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4558 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4559 PseudoSourceValue::getConstantPool(), 0,
4561 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4564 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
4565 MVT VT = Op.getValueType();
4567 unsigned EltNum = 1;
4568 if (VT.isVector()) {
4569 EltVT = VT.getVectorElementType();
4570 EltNum = VT.getVectorNumElements();
4572 std::vector<Constant*> CV;
4573 if (EltVT == MVT::f64) {
4574 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
4578 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
4584 Constant *C = ConstantVector::get(CV);
4585 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4586 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4587 PseudoSourceValue::getConstantPool(), 0,
4589 if (VT.isVector()) {
4590 return DAG.getNode(ISD::BIT_CONVERT, VT,
4591 DAG.getNode(ISD::XOR, MVT::v2i64,
4592 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4593 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4595 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4599 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
4600 SDOperand Op0 = Op.getOperand(0);
4601 SDOperand Op1 = Op.getOperand(1);
4602 MVT VT = Op.getValueType();
4603 MVT SrcVT = Op1.getValueType();
4605 // If second operand is smaller, extend it first.
4606 if (SrcVT.bitsLT(VT)) {
4607 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4610 // And if it is bigger, shrink it first.
4611 if (SrcVT.bitsGT(VT)) {
4612 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
4616 // At this point the operands and the result should have the same
4617 // type, and that won't be f80 since that is not custom lowered.
4619 // First get the sign bit of second operand.
4620 std::vector<Constant*> CV;
4621 if (SrcVT == MVT::f64) {
4622 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
4623 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4625 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
4626 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4627 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4628 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4630 Constant *C = ConstantVector::get(CV);
4631 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4632 SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
4633 PseudoSourceValue::getConstantPool(), 0,
4635 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4637 // Shift sign bit right or left if the two operands have different types.
4638 if (SrcVT.bitsGT(VT)) {
4639 // Op0 is MVT::f32, Op1 is MVT::f64.
4640 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4641 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4642 DAG.getConstant(32, MVT::i32));
4643 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4644 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4645 DAG.getIntPtrConstant(0));
4648 // Clear first operand sign bit.
4650 if (VT == MVT::f64) {
4651 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
4652 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4654 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
4655 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4656 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4657 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4659 C = ConstantVector::get(CV);
4660 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4661 SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4662 PseudoSourceValue::getConstantPool(), 0,
4664 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
4666 // Or the value with the sign bit.
4667 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
4670 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
4671 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
4673 SDOperand Op0 = Op.getOperand(0);
4674 SDOperand Op1 = Op.getOperand(1);
4675 SDOperand CC = Op.getOperand(2);
4676 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4677 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
4680 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
4682 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4683 return DAG.getNode(X86ISD::SETCC, MVT::i8,
4684 DAG.getConstant(X86CC, MVT::i8), Cond);
4687 assert(isFP && "Illegal integer SetCC!");
4689 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4690 switch (SetCCOpcode) {
4691 default: assert(false && "Illegal floating point SetCC!");
4692 case ISD::SETOEQ: { // !PF & ZF
4693 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4694 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
4695 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4696 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
4697 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4699 case ISD::SETUNE: { // PF | !ZF
4700 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4701 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
4702 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4703 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
4704 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4710 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
4711 bool addTest = true;
4712 SDOperand Cond = Op.getOperand(0);
4715 if (Cond.getOpcode() == ISD::SETCC)
4716 Cond = LowerSETCC(Cond, DAG);
4718 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4719 // setting operand in place of the X86ISD::SETCC.
4720 if (Cond.getOpcode() == X86ISD::SETCC) {
4721 CC = Cond.getOperand(0);
4723 SDOperand Cmp = Cond.getOperand(1);
4724 unsigned Opc = Cmp.getOpcode();
4725 MVT VT = Op.getValueType();
4727 bool IllegalFPCMov = false;
4728 if (VT.isFloatingPoint() && !VT.isVector() &&
4729 !isScalarFPTypeInSSEReg(VT)) // FPStack?
4730 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4732 if ((Opc == X86ISD::CMP ||
4733 Opc == X86ISD::COMI ||
4734 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
4741 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4742 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4745 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
4747 SmallVector<SDOperand, 4> Ops;
4748 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4749 // condition is true.
4750 Ops.push_back(Op.getOperand(2));
4751 Ops.push_back(Op.getOperand(1));
4753 Ops.push_back(Cond);
4754 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
4757 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
4758 bool addTest = true;
4759 SDOperand Chain = Op.getOperand(0);
4760 SDOperand Cond = Op.getOperand(1);
4761 SDOperand Dest = Op.getOperand(2);
4764 if (Cond.getOpcode() == ISD::SETCC)
4765 Cond = LowerSETCC(Cond, DAG);
4767 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4768 // setting operand in place of the X86ISD::SETCC.
4769 if (Cond.getOpcode() == X86ISD::SETCC) {
4770 CC = Cond.getOperand(0);
4772 SDOperand Cmp = Cond.getOperand(1);
4773 unsigned Opc = Cmp.getOpcode();
4774 if (Opc == X86ISD::CMP ||
4775 Opc == X86ISD::COMI ||
4776 Opc == X86ISD::UCOMI) {
4783 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4784 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4786 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
4787 Chain, Op.getOperand(2), CC, Cond);
4791 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
4792 // Calls to _alloca is needed to probe the stack when allocating more than 4k
4793 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
4794 // that the guard pages used by the OS virtual memory manager are allocated in
4795 // correct sequence.
4797 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
4798 SelectionDAG &DAG) {
4799 assert(Subtarget->isTargetCygMing() &&
4800 "This should be used only on Cygwin/Mingw targets");
4803 SDOperand Chain = Op.getOperand(0);
4804 SDOperand Size = Op.getOperand(1);
4805 // FIXME: Ensure alignment here
4809 MVT IntPtr = getPointerTy();
4810 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
4812 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0));
4814 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
4815 Flag = Chain.getValue(1);
4817 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4818 SDOperand Ops[] = { Chain,
4819 DAG.getTargetExternalSymbol("_alloca", IntPtr),
4820 DAG.getRegister(X86::EAX, IntPtr),
4821 DAG.getRegister(X86StackPtr, SPTy),
4823 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5);
4824 Flag = Chain.getValue(1);
4826 Chain = DAG.getCALLSEQ_END(Chain,
4827 DAG.getIntPtrConstant(0),
4828 DAG.getIntPtrConstant(0),
4831 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
4833 std::vector<MVT> Tys;
4834 Tys.push_back(SPTy);
4835 Tys.push_back(MVT::Other);
4836 SDOperand Ops1[2] = { Chain.getValue(0), Chain };
4837 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2);
4841 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
4843 SDOperand Dst, SDOperand Src,
4844 SDOperand Size, unsigned Align,
4845 const Value *DstSV, uint64_t DstSVOff) {
4846 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
4848 /// If not DWORD aligned or size is more than the threshold, call the library.
4849 /// The libc version is likely to be faster for these cases. It can use the
4850 /// address value and run time information about the CPU.
4851 if ((Align & 3) == 0 ||
4853 ConstantSize->getValue() > getSubtarget()->getMaxInlineSizeThreshold()) {
4854 SDOperand InFlag(0, 0);
4856 // Check to see if there is a specialized entry-point for memory zeroing.
4857 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
4858 if (const char *bzeroEntry =
4859 V && V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
4860 MVT IntPtr = getPointerTy();
4861 const Type *IntPtrTy = getTargetData()->getIntPtrType();
4862 TargetLowering::ArgListTy Args;
4863 TargetLowering::ArgListEntry Entry;
4865 Entry.Ty = IntPtrTy;
4866 Args.push_back(Entry);
4868 Args.push_back(Entry);
4869 std::pair<SDOperand,SDOperand> CallResult =
4870 LowerCallTo(Chain, Type::VoidTy, false, false, false, CallingConv::C,
4871 false, DAG.getExternalSymbol(bzeroEntry, IntPtr),
4873 return CallResult.second;
4876 // Otherwise have the target-independent code call memset.
4880 uint64_t SizeVal = ConstantSize->getValue();
4881 SDOperand InFlag(0, 0);
4884 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
4885 unsigned BytesLeft = 0;
4886 bool TwoRepStos = false;
4889 uint64_t Val = ValC->getValue() & 255;
4891 // If the value is a constant, then we can potentially use larger sets.
4892 switch (Align & 3) {
4893 case 2: // WORD aligned
4896 Val = (Val << 8) | Val;
4898 case 0: // DWORD aligned
4901 Val = (Val << 8) | Val;
4902 Val = (Val << 16) | Val;
4903 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
4906 Val = (Val << 32) | Val;
4909 default: // Byte aligned
4912 Count = DAG.getIntPtrConstant(SizeVal);
4916 if (AVT.bitsGT(MVT::i8)) {
4917 unsigned UBytes = AVT.getSizeInBits() / 8;
4918 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
4919 BytesLeft = SizeVal % UBytes;
4922 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
4924 InFlag = Chain.getValue(1);
4927 Count = DAG.getIntPtrConstant(SizeVal);
4928 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
4929 InFlag = Chain.getValue(1);
4932 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4934 InFlag = Chain.getValue(1);
4935 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4937 InFlag = Chain.getValue(1);
4939 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4940 SmallVector<SDOperand, 8> Ops;
4941 Ops.push_back(Chain);
4942 Ops.push_back(DAG.getValueType(AVT));
4943 Ops.push_back(InFlag);
4944 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4947 InFlag = Chain.getValue(1);
4949 MVT CVT = Count.getValueType();
4950 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4951 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4952 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4954 InFlag = Chain.getValue(1);
4955 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4957 Ops.push_back(Chain);
4958 Ops.push_back(DAG.getValueType(MVT::i8));
4959 Ops.push_back(InFlag);
4960 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4961 } else if (BytesLeft) {
4962 // Handle the last 1 - 7 bytes.
4963 unsigned Offset = SizeVal - BytesLeft;
4964 MVT AddrVT = Dst.getValueType();
4965 MVT SizeVT = Size.getValueType();
4967 Chain = DAG.getMemset(Chain,
4968 DAG.getNode(ISD::ADD, AddrVT, Dst,
4969 DAG.getConstant(Offset, AddrVT)),
4971 DAG.getConstant(BytesLeft, SizeVT),
4972 Align, DstSV, DstSVOff + Offset);
4975 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
4980 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
4982 SDOperand Dst, SDOperand Src,
4983 SDOperand Size, unsigned Align,
4985 const Value *DstSV, uint64_t DstSVOff,
4986 const Value *SrcSV, uint64_t SrcSVOff){
4988 // This requires the copy size to be a constant, preferrably
4989 // within a subtarget-specific limit.
4990 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
4993 uint64_t SizeVal = ConstantSize->getValue();
4994 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
4998 unsigned BytesLeft = 0;
4999 if (Align >= 8 && Subtarget->is64Bit())
5001 else if (Align >= 4)
5003 else if (Align >= 2)
5008 unsigned UBytes = AVT.getSizeInBits() / 8;
5009 unsigned CountVal = SizeVal / UBytes;
5010 SDOperand Count = DAG.getIntPtrConstant(CountVal);
5011 BytesLeft = SizeVal % UBytes;
5013 SDOperand InFlag(0, 0);
5014 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5016 InFlag = Chain.getValue(1);
5017 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5019 InFlag = Chain.getValue(1);
5020 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
5022 InFlag = Chain.getValue(1);
5024 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5025 SmallVector<SDOperand, 8> Ops;
5026 Ops.push_back(Chain);
5027 Ops.push_back(DAG.getValueType(AVT));
5028 Ops.push_back(InFlag);
5029 SDOperand RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
5031 SmallVector<SDOperand, 4> Results;
5032 Results.push_back(RepMovs);
5034 // Handle the last 1 - 7 bytes.
5035 unsigned Offset = SizeVal - BytesLeft;
5036 MVT DstVT = Dst.getValueType();
5037 MVT SrcVT = Src.getValueType();
5038 MVT SizeVT = Size.getValueType();
5039 Results.push_back(DAG.getMemcpy(Chain,
5040 DAG.getNode(ISD::ADD, DstVT, Dst,
5041 DAG.getConstant(Offset, DstVT)),
5042 DAG.getNode(ISD::ADD, SrcVT, Src,
5043 DAG.getConstant(Offset, SrcVT)),
5044 DAG.getConstant(BytesLeft, SizeVT),
5045 Align, AlwaysInline,
5046 DstSV, DstSVOff + Offset,
5047 SrcSV, SrcSVOff + Offset));
5050 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
5053 /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
5054 SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
5055 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5056 SDOperand TheChain = N->getOperand(0);
5057 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
5058 if (Subtarget->is64Bit()) {
5059 SDOperand rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
5060 SDOperand rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
5061 MVT::i64, rax.getValue(2));
5062 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
5063 DAG.getConstant(32, MVT::i8));
5065 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
5068 Tys = DAG.getVTList(MVT::i64, MVT::Other);
5069 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
5072 SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
5073 SDOperand edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
5074 MVT::i32, eax.getValue(2));
5075 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
5076 SDOperand Ops[] = { eax, edx };
5077 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
5079 // Use a MERGE_VALUES to return the value and chain.
5080 Ops[1] = edx.getValue(1);
5081 Tys = DAG.getVTList(MVT::i64, MVT::Other);
5082 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
5085 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
5086 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
5088 if (!Subtarget->is64Bit()) {
5089 // vastart just stores the address of the VarArgsFrameIndex slot into the
5090 // memory location argument.
5091 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5092 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
5096 // gp_offset (0 - 6 * 8)
5097 // fp_offset (48 - 48 + 8 * 16)
5098 // overflow_arg_area (point to parameters coming in memory).
5100 SmallVector<SDOperand, 8> MemOps;
5101 SDOperand FIN = Op.getOperand(1);
5103 SDOperand Store = DAG.getStore(Op.getOperand(0),
5104 DAG.getConstant(VarArgsGPOffset, MVT::i32),
5106 MemOps.push_back(Store);
5109 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5110 Store = DAG.getStore(Op.getOperand(0),
5111 DAG.getConstant(VarArgsFPOffset, MVT::i32),
5113 MemOps.push_back(Store);
5115 // Store ptr to overflow_arg_area
5116 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5117 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5118 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
5119 MemOps.push_back(Store);
5121 // Store ptr to reg_save_area.
5122 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
5123 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
5124 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
5125 MemOps.push_back(Store);
5126 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
5129 SDOperand X86TargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG) {
5130 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5131 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
5132 SDOperand Chain = Op.getOperand(0);
5133 SDOperand SrcPtr = Op.getOperand(1);
5134 SDOperand SrcSV = Op.getOperand(2);
5136 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5141 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
5142 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5143 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
5144 SDOperand Chain = Op.getOperand(0);
5145 SDOperand DstPtr = Op.getOperand(1);
5146 SDOperand SrcPtr = Op.getOperand(2);
5147 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5148 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5150 return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
5151 DAG.getIntPtrConstant(24), 8, false,
5152 DstSV, 0, SrcSV, 0);
5156 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
5157 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
5159 default: return SDOperand(); // Don't custom lower most intrinsics.
5160 // Comparison intrinsics.
5161 case Intrinsic::x86_sse_comieq_ss:
5162 case Intrinsic::x86_sse_comilt_ss:
5163 case Intrinsic::x86_sse_comile_ss:
5164 case Intrinsic::x86_sse_comigt_ss:
5165 case Intrinsic::x86_sse_comige_ss:
5166 case Intrinsic::x86_sse_comineq_ss:
5167 case Intrinsic::x86_sse_ucomieq_ss:
5168 case Intrinsic::x86_sse_ucomilt_ss:
5169 case Intrinsic::x86_sse_ucomile_ss:
5170 case Intrinsic::x86_sse_ucomigt_ss:
5171 case Intrinsic::x86_sse_ucomige_ss:
5172 case Intrinsic::x86_sse_ucomineq_ss:
5173 case Intrinsic::x86_sse2_comieq_sd:
5174 case Intrinsic::x86_sse2_comilt_sd:
5175 case Intrinsic::x86_sse2_comile_sd:
5176 case Intrinsic::x86_sse2_comigt_sd:
5177 case Intrinsic::x86_sse2_comige_sd:
5178 case Intrinsic::x86_sse2_comineq_sd:
5179 case Intrinsic::x86_sse2_ucomieq_sd:
5180 case Intrinsic::x86_sse2_ucomilt_sd:
5181 case Intrinsic::x86_sse2_ucomile_sd:
5182 case Intrinsic::x86_sse2_ucomigt_sd:
5183 case Intrinsic::x86_sse2_ucomige_sd:
5184 case Intrinsic::x86_sse2_ucomineq_sd: {
5186 ISD::CondCode CC = ISD::SETCC_INVALID;
5189 case Intrinsic::x86_sse_comieq_ss:
5190 case Intrinsic::x86_sse2_comieq_sd:
5194 case Intrinsic::x86_sse_comilt_ss:
5195 case Intrinsic::x86_sse2_comilt_sd:
5199 case Intrinsic::x86_sse_comile_ss:
5200 case Intrinsic::x86_sse2_comile_sd:
5204 case Intrinsic::x86_sse_comigt_ss:
5205 case Intrinsic::x86_sse2_comigt_sd:
5209 case Intrinsic::x86_sse_comige_ss:
5210 case Intrinsic::x86_sse2_comige_sd:
5214 case Intrinsic::x86_sse_comineq_ss:
5215 case Intrinsic::x86_sse2_comineq_sd:
5219 case Intrinsic::x86_sse_ucomieq_ss:
5220 case Intrinsic::x86_sse2_ucomieq_sd:
5221 Opc = X86ISD::UCOMI;
5224 case Intrinsic::x86_sse_ucomilt_ss:
5225 case Intrinsic::x86_sse2_ucomilt_sd:
5226 Opc = X86ISD::UCOMI;
5229 case Intrinsic::x86_sse_ucomile_ss:
5230 case Intrinsic::x86_sse2_ucomile_sd:
5231 Opc = X86ISD::UCOMI;
5234 case Intrinsic::x86_sse_ucomigt_ss:
5235 case Intrinsic::x86_sse2_ucomigt_sd:
5236 Opc = X86ISD::UCOMI;
5239 case Intrinsic::x86_sse_ucomige_ss:
5240 case Intrinsic::x86_sse2_ucomige_sd:
5241 Opc = X86ISD::UCOMI;
5244 case Intrinsic::x86_sse_ucomineq_ss:
5245 case Intrinsic::x86_sse2_ucomineq_sd:
5246 Opc = X86ISD::UCOMI;
5252 SDOperand LHS = Op.getOperand(1);
5253 SDOperand RHS = Op.getOperand(2);
5254 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
5256 SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5257 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
5258 DAG.getConstant(X86CC, MVT::i8), Cond);
5259 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
5262 // Fix vector shift instructions where the last operand is a non-immediate
5264 case Intrinsic::x86_sse2_pslli_w:
5265 case Intrinsic::x86_sse2_pslli_d:
5266 case Intrinsic::x86_sse2_pslli_q:
5267 case Intrinsic::x86_sse2_psrli_w:
5268 case Intrinsic::x86_sse2_psrli_d:
5269 case Intrinsic::x86_sse2_psrli_q:
5270 case Intrinsic::x86_sse2_psrai_w:
5271 case Intrinsic::x86_sse2_psrai_d:
5272 case Intrinsic::x86_mmx_pslli_w:
5273 case Intrinsic::x86_mmx_pslli_d:
5274 case Intrinsic::x86_mmx_pslli_q:
5275 case Intrinsic::x86_mmx_psrli_w:
5276 case Intrinsic::x86_mmx_psrli_d:
5277 case Intrinsic::x86_mmx_psrli_q:
5278 case Intrinsic::x86_mmx_psrai_w:
5279 case Intrinsic::x86_mmx_psrai_d: {
5280 SDOperand ShAmt = Op.getOperand(2);
5281 if (isa<ConstantSDNode>(ShAmt))
5284 unsigned NewIntNo = 0;
5285 MVT ShAmtVT = MVT::v4i32;
5287 case Intrinsic::x86_sse2_pslli_w:
5288 NewIntNo = Intrinsic::x86_sse2_psll_w;
5290 case Intrinsic::x86_sse2_pslli_d:
5291 NewIntNo = Intrinsic::x86_sse2_psll_d;
5293 case Intrinsic::x86_sse2_pslli_q:
5294 NewIntNo = Intrinsic::x86_sse2_psll_q;
5296 case Intrinsic::x86_sse2_psrli_w:
5297 NewIntNo = Intrinsic::x86_sse2_psrl_w;
5299 case Intrinsic::x86_sse2_psrli_d:
5300 NewIntNo = Intrinsic::x86_sse2_psrl_d;
5302 case Intrinsic::x86_sse2_psrli_q:
5303 NewIntNo = Intrinsic::x86_sse2_psrl_q;
5305 case Intrinsic::x86_sse2_psrai_w:
5306 NewIntNo = Intrinsic::x86_sse2_psra_w;
5308 case Intrinsic::x86_sse2_psrai_d:
5309 NewIntNo = Intrinsic::x86_sse2_psra_d;
5312 ShAmtVT = MVT::v2i32;
5314 case Intrinsic::x86_mmx_pslli_w:
5315 NewIntNo = Intrinsic::x86_mmx_psll_w;
5317 case Intrinsic::x86_mmx_pslli_d:
5318 NewIntNo = Intrinsic::x86_mmx_psll_d;
5320 case Intrinsic::x86_mmx_pslli_q:
5321 NewIntNo = Intrinsic::x86_mmx_psll_q;
5323 case Intrinsic::x86_mmx_psrli_w:
5324 NewIntNo = Intrinsic::x86_mmx_psrl_w;
5326 case Intrinsic::x86_mmx_psrli_d:
5327 NewIntNo = Intrinsic::x86_mmx_psrl_d;
5329 case Intrinsic::x86_mmx_psrli_q:
5330 NewIntNo = Intrinsic::x86_mmx_psrl_q;
5332 case Intrinsic::x86_mmx_psrai_w:
5333 NewIntNo = Intrinsic::x86_mmx_psra_w;
5335 case Intrinsic::x86_mmx_psrai_d:
5336 NewIntNo = Intrinsic::x86_mmx_psra_d;
5338 default: abort(); // Can't reach here.
5343 MVT VT = Op.getValueType();
5344 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
5345 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
5346 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
5347 DAG.getConstant(NewIntNo, MVT::i32),
5348 Op.getOperand(1), ShAmt);
5353 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
5354 // Depths > 0 not supported yet!
5355 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5358 // Just load the return address
5359 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
5360 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5363 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
5364 // Depths > 0 not supported yet!
5365 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
5368 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
5369 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
5370 DAG.getIntPtrConstant(4));
5373 SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
5374 SelectionDAG &DAG) {
5375 // Is not yet supported on x86-64
5376 if (Subtarget->is64Bit())
5379 return DAG.getIntPtrConstant(8);
5382 SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
5384 assert(!Subtarget->is64Bit() &&
5385 "Lowering of eh_return builtin is not supported yet on x86-64");
5387 MachineFunction &MF = DAG.getMachineFunction();
5388 SDOperand Chain = Op.getOperand(0);
5389 SDOperand Offset = Op.getOperand(1);
5390 SDOperand Handler = Op.getOperand(2);
5392 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
5395 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
5396 DAG.getIntPtrConstant(-4UL));
5397 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
5398 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
5399 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
5400 MF.getRegInfo().addLiveOut(X86::ECX);
5402 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
5403 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
5406 SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
5407 SelectionDAG &DAG) {
5408 SDOperand Root = Op.getOperand(0);
5409 SDOperand Trmp = Op.getOperand(1); // trampoline
5410 SDOperand FPtr = Op.getOperand(2); // nested function
5411 SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
5413 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5415 const X86InstrInfo *TII =
5416 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
5418 if (Subtarget->is64Bit()) {
5419 SDOperand OutChains[6];
5421 // Large code-model.
5423 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
5424 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
5426 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
5427 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
5429 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
5431 // Load the pointer to the nested function into R11.
5432 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
5433 SDOperand Addr = Trmp;
5434 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5437 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
5438 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
5440 // Load the 'nest' parameter value into R10.
5441 // R10 is specified in X86CallingConv.td
5442 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
5443 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
5444 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5447 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
5448 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
5450 // Jump to the nested function.
5451 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
5452 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
5453 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5456 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
5457 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
5458 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
5462 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
5463 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
5465 const Function *Func =
5466 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
5467 unsigned CC = Func->getCallingConv();
5472 assert(0 && "Unsupported calling convention");
5473 case CallingConv::C:
5474 case CallingConv::X86_StdCall: {
5475 // Pass 'nest' parameter in ECX.
5476 // Must be kept in sync with X86CallingConv.td
5479 // Check that ECX wasn't needed by an 'inreg' parameter.
5480 const FunctionType *FTy = Func->getFunctionType();
5481 const PAListPtr &Attrs = Func->getParamAttrs();
5483 if (!Attrs.isEmpty() && !Func->isVarArg()) {
5484 unsigned InRegCount = 0;
5487 for (FunctionType::param_iterator I = FTy->param_begin(),
5488 E = FTy->param_end(); I != E; ++I, ++Idx)
5489 if (Attrs.paramHasAttr(Idx, ParamAttr::InReg))
5490 // FIXME: should only count parameters that are lowered to integers.
5491 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
5493 if (InRegCount > 2) {
5494 cerr << "Nest register in use - reduce number of inreg parameters!\n";
5500 case CallingConv::X86_FastCall:
5501 // Pass 'nest' parameter in EAX.
5502 // Must be kept in sync with X86CallingConv.td
5507 SDOperand OutChains[4];
5508 SDOperand Addr, Disp;
5510 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
5511 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
5513 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
5514 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
5515 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
5518 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
5519 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
5521 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
5522 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
5523 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
5524 TrmpAddr, 5, false, 1);
5526 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
5527 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
5530 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
5531 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
5535 SDOperand X86TargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
5537 The rounding mode is in bits 11:10 of FPSR, and has the following
5544 FLT_ROUNDS, on the other hand, expects the following:
5551 To perform the conversion, we do:
5552 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
5555 MachineFunction &MF = DAG.getMachineFunction();
5556 const TargetMachine &TM = MF.getTarget();
5557 const TargetFrameInfo &TFI = *TM.getFrameInfo();
5558 unsigned StackAlignment = TFI.getStackAlignment();
5559 MVT VT = Op.getValueType();
5561 // Save FP Control Word to stack slot
5562 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
5563 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5565 SDOperand Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
5566 DAG.getEntryNode(), StackSlot);
5568 // Load FP Control Word from stack slot
5569 SDOperand CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
5571 // Transform as necessary
5573 DAG.getNode(ISD::SRL, MVT::i16,
5574 DAG.getNode(ISD::AND, MVT::i16,
5575 CWD, DAG.getConstant(0x800, MVT::i16)),
5576 DAG.getConstant(11, MVT::i8));
5578 DAG.getNode(ISD::SRL, MVT::i16,
5579 DAG.getNode(ISD::AND, MVT::i16,
5580 CWD, DAG.getConstant(0x400, MVT::i16)),
5581 DAG.getConstant(9, MVT::i8));
5584 DAG.getNode(ISD::AND, MVT::i16,
5585 DAG.getNode(ISD::ADD, MVT::i16,
5586 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
5587 DAG.getConstant(1, MVT::i16)),
5588 DAG.getConstant(3, MVT::i16));
5591 return DAG.getNode((VT.getSizeInBits() < 16 ?
5592 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
5595 SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) {
5596 MVT VT = Op.getValueType();
5598 unsigned NumBits = VT.getSizeInBits();
5600 Op = Op.getOperand(0);
5601 if (VT == MVT::i8) {
5602 // Zero extend to i32 since there is not an i8 bsr.
5604 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5607 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
5608 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5609 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
5611 // If src is zero (i.e. bsr sets ZF), returns NumBits.
5612 SmallVector<SDOperand, 4> Ops;
5614 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
5615 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5616 Ops.push_back(Op.getValue(1));
5617 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5619 // Finally xor with NumBits-1.
5620 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
5623 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5627 SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) {
5628 MVT VT = Op.getValueType();
5630 unsigned NumBits = VT.getSizeInBits();
5632 Op = Op.getOperand(0);
5633 if (VT == MVT::i8) {
5635 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5638 // Issue a bsf (scan bits forward) which also sets EFLAGS.
5639 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5640 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
5642 // If src is zero (i.e. bsf sets ZF), returns NumBits.
5643 SmallVector<SDOperand, 4> Ops;
5645 Ops.push_back(DAG.getConstant(NumBits, OpVT));
5646 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5647 Ops.push_back(Op.getValue(1));
5648 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5651 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5655 SDOperand X86TargetLowering::LowerLCS(SDOperand Op, SelectionDAG &DAG) {
5656 MVT T = cast<AtomicSDNode>(Op.Val)->getVT();
5659 switch(T.getSimpleVT()) {
5661 assert(false && "Invalid value type!");
5662 case MVT::i8: Reg = X86::AL; size = 1; break;
5663 case MVT::i16: Reg = X86::AX; size = 2; break;
5664 case MVT::i32: Reg = X86::EAX; size = 4; break;
5666 if (Subtarget->is64Bit()) {
5667 Reg = X86::RAX; size = 8;
5668 } else //Should go away when LowerType stuff lands
5669 return SDOperand(ExpandATOMIC_LCS(Op.Val, DAG), 0);
5672 SDOperand cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
5673 Op.getOperand(3), SDOperand());
5674 SDOperand Ops[] = { cpIn.getValue(0),
5677 DAG.getTargetConstant(size, MVT::i8),
5679 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5680 SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
5682 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
5686 SDNode* X86TargetLowering::ExpandATOMIC_LCS(SDNode* Op, SelectionDAG &DAG) {
5687 MVT T = cast<AtomicSDNode>(Op)->getVT();
5688 assert (T == MVT::i64 && "Only know how to expand i64 CAS");
5689 SDOperand cpInL, cpInH;
5690 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5691 DAG.getConstant(0, MVT::i32));
5692 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
5693 DAG.getConstant(1, MVT::i32));
5694 cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX,
5695 cpInL, SDOperand());
5696 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX,
5697 cpInH, cpInL.getValue(1));
5698 SDOperand swapInL, swapInH;
5699 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5700 DAG.getConstant(0, MVT::i32));
5701 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
5702 DAG.getConstant(1, MVT::i32));
5703 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX,
5704 swapInL, cpInH.getValue(1));
5705 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX,
5706 swapInH, swapInL.getValue(1));
5707 SDOperand Ops[] = { swapInH.getValue(0),
5709 swapInH.getValue(1)};
5710 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5711 SDOperand Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
5712 SDOperand cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
5713 Result.getValue(1));
5714 SDOperand cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
5715 cpOutL.getValue(2));
5716 SDOperand OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
5717 SDOperand ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
5718 Tys = DAG.getVTList(MVT::i64, MVT::Other);
5719 return DAG.getNode(ISD::MERGE_VALUES, Tys, ResultVal, cpOutH.getValue(1)).Val;
5722 SDNode* X86TargetLowering::ExpandATOMIC_LSS(SDNode* Op, SelectionDAG &DAG) {
5723 MVT T = cast<AtomicSDNode>(Op)->getVT();
5724 assert (T == MVT::i32 && "Only know how to expand i32 LSS");
5725 SDOperand negOp = DAG.getNode(ISD::SUB, T,
5726 DAG.getConstant(0, T), Op->getOperand(2));
5727 return DAG.getAtomic(ISD::ATOMIC_LAS, Op->getOperand(0),
5728 Op->getOperand(1), negOp, T).Val;
5731 /// LowerOperation - Provide custom lowering hooks for some operations.
5733 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
5734 switch (Op.getOpcode()) {
5735 default: assert(0 && "Should not custom lower this!");
5736 case ISD::ATOMIC_LCS: return LowerLCS(Op,DAG);
5737 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5738 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5739 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5740 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5741 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5742 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5743 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5744 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5745 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
5746 case ISD::SHL_PARTS:
5747 case ISD::SRA_PARTS:
5748 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
5749 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5750 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
5751 case ISD::FABS: return LowerFABS(Op, DAG);
5752 case ISD::FNEG: return LowerFNEG(Op, DAG);
5753 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5754 case ISD::SETCC: return LowerSETCC(Op, DAG);
5755 case ISD::SELECT: return LowerSELECT(Op, DAG);
5756 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
5757 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5758 case ISD::CALL: return LowerCALL(Op, DAG);
5759 case ISD::RET: return LowerRET(Op, DAG);
5760 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
5761 case ISD::VASTART: return LowerVASTART(Op, DAG);
5762 case ISD::VAARG: return LowerVAARG(Op, DAG);
5763 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
5764 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5765 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5766 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5767 case ISD::FRAME_TO_ARGS_OFFSET:
5768 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
5769 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
5770 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
5771 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
5772 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5773 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
5774 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
5776 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
5777 case ISD::READCYCLECOUNTER:
5778 return SDOperand(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
5782 /// ExpandOperation - Provide custom lowering hooks for expanding operations.
5783 SDNode *X86TargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
5784 switch (N->getOpcode()) {
5785 default: assert(0 && "Should not custom lower this!");
5786 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
5787 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
5788 case ISD::ATOMIC_LCS: return ExpandATOMIC_LCS(N, DAG);
5789 case ISD::ATOMIC_LSS: return ExpandATOMIC_LSS(N,DAG);
5793 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
5795 default: return NULL;
5796 case X86ISD::BSF: return "X86ISD::BSF";
5797 case X86ISD::BSR: return "X86ISD::BSR";
5798 case X86ISD::SHLD: return "X86ISD::SHLD";
5799 case X86ISD::SHRD: return "X86ISD::SHRD";
5800 case X86ISD::FAND: return "X86ISD::FAND";
5801 case X86ISD::FOR: return "X86ISD::FOR";
5802 case X86ISD::FXOR: return "X86ISD::FXOR";
5803 case X86ISD::FSRL: return "X86ISD::FSRL";
5804 case X86ISD::FILD: return "X86ISD::FILD";
5805 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
5806 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
5807 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
5808 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
5809 case X86ISD::FLD: return "X86ISD::FLD";
5810 case X86ISD::FST: return "X86ISD::FST";
5811 case X86ISD::CALL: return "X86ISD::CALL";
5812 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
5813 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
5814 case X86ISD::CMP: return "X86ISD::CMP";
5815 case X86ISD::COMI: return "X86ISD::COMI";
5816 case X86ISD::UCOMI: return "X86ISD::UCOMI";
5817 case X86ISD::SETCC: return "X86ISD::SETCC";
5818 case X86ISD::CMOV: return "X86ISD::CMOV";
5819 case X86ISD::BRCOND: return "X86ISD::BRCOND";
5820 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
5821 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
5822 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
5823 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
5824 case X86ISD::Wrapper: return "X86ISD::Wrapper";
5825 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
5826 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
5827 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
5828 case X86ISD::PINSRB: return "X86ISD::PINSRB";
5829 case X86ISD::PINSRW: return "X86ISD::PINSRW";
5830 case X86ISD::FMAX: return "X86ISD::FMAX";
5831 case X86ISD::FMIN: return "X86ISD::FMIN";
5832 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
5833 case X86ISD::FRCP: return "X86ISD::FRCP";
5834 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
5835 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
5836 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
5837 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
5838 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
5839 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
5840 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
5841 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
5842 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
5843 case X86ISD::VSHL: return "X86ISD::VSHL";
5844 case X86ISD::VSRL: return "X86ISD::VSRL";
5848 // isLegalAddressingMode - Return true if the addressing mode represented
5849 // by AM is legal for this target, for a load/store of the specified type.
5850 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
5851 const Type *Ty) const {
5852 // X86 supports extremely general addressing modes.
5854 // X86 allows a sign-extended 32-bit immediate field as a displacement.
5855 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
5859 // We can only fold this if we don't need an extra load.
5860 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
5863 // X86-64 only supports addr of globals in small code model.
5864 if (Subtarget->is64Bit()) {
5865 if (getTargetMachine().getCodeModel() != CodeModel::Small)
5867 // If lower 4G is not available, then we must use rip-relative addressing.
5868 if (AM.BaseOffs || AM.Scale > 1)
5879 // These scales always work.
5884 // These scales are formed with basereg+scalereg. Only accept if there is
5889 default: // Other stuff never works.
5897 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
5898 if (!Ty1->isInteger() || !Ty2->isInteger())
5900 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
5901 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
5902 if (NumBits1 <= NumBits2)
5904 return Subtarget->is64Bit() || NumBits1 < 64;
5907 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
5908 if (!VT1.isInteger() || !VT2.isInteger())
5910 unsigned NumBits1 = VT1.getSizeInBits();
5911 unsigned NumBits2 = VT2.getSizeInBits();
5912 if (NumBits1 <= NumBits2)
5914 return Subtarget->is64Bit() || NumBits1 < 64;
5917 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5918 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5919 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5920 /// are assumed to be legal.
5922 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT VT) const {
5923 // Only do shuffles on 128-bit vector types for now.
5924 if (VT.getSizeInBits() == 64) return false;
5925 return (Mask.Val->getNumOperands() <= 4 ||
5926 isIdentityMask(Mask.Val) ||
5927 isIdentityMask(Mask.Val, true) ||
5928 isSplatMask(Mask.Val) ||
5929 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
5930 X86::isUNPCKLMask(Mask.Val) ||
5931 X86::isUNPCKHMask(Mask.Val) ||
5932 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
5933 X86::isUNPCKH_v_undef_Mask(Mask.Val));
5937 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
5938 MVT EVT, SelectionDAG &DAG) const {
5939 unsigned NumElts = BVOps.size();
5940 // Only do shuffles on 128-bit vector types for now.
5941 if (EVT.getSizeInBits() * NumElts == 64) return false;
5942 if (NumElts == 2) return true;
5944 return (isMOVLMask(&BVOps[0], 4) ||
5945 isCommutedMOVL(&BVOps[0], 4, true) ||
5946 isSHUFPMask(&BVOps[0], 4) ||
5947 isCommutedSHUFP(&BVOps[0], 4));
5952 //===----------------------------------------------------------------------===//
5953 // X86 Scheduler Hooks
5954 //===----------------------------------------------------------------------===//
5956 // private utility function
5958 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
5959 MachineBasicBlock *MBB,
5963 // For the atomic bitwise operator, we generate
5966 // ld t1 = [bitinstr.addr]
5967 // op t2 = t1, [bitinstr.val]
5969 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
5971 // fallthrough -->nextMBB
5972 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5973 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
5974 ilist<MachineBasicBlock>::iterator MBBIter = MBB;
5977 /// First build the CFG
5978 MachineFunction *F = MBB->getParent();
5979 MachineBasicBlock *thisMBB = MBB;
5980 MachineBasicBlock *newMBB = new MachineBasicBlock(LLVM_BB);
5981 MachineBasicBlock *nextMBB = new MachineBasicBlock(LLVM_BB);
5982 F->getBasicBlockList().insert(MBBIter, newMBB);
5983 F->getBasicBlockList().insert(MBBIter, nextMBB);
5985 // Move all successors to thisMBB to nextMBB
5986 nextMBB->transferSuccessors(thisMBB);
5988 // Update thisMBB to fall through to newMBB
5989 thisMBB->addSuccessor(newMBB);
5991 // newMBB jumps to itself and fall through to nextMBB
5992 newMBB->addSuccessor(nextMBB);
5993 newMBB->addSuccessor(newMBB);
5995 // Insert instructions into newMBB based on incoming instruction
5996 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
5997 MachineOperand& destOper = bInstr->getOperand(0);
5998 MachineOperand* argOpers[6];
5999 int numArgs = bInstr->getNumOperands() - 1;
6000 for (int i=0; i < numArgs; ++i)
6001 argOpers[i] = &bInstr->getOperand(i+1);
6003 // x86 address has 4 operands: base, index, scale, and displacement
6004 int lastAddrIndx = 3; // [0,3]
6007 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6008 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
6009 for (int i=0; i <= lastAddrIndx; ++i)
6010 (*MIB).addOperand(*argOpers[i]);
6012 unsigned tt = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6014 MIB = BuildMI(newMBB, TII->get(X86::NOT32r), tt).addReg(t1);
6019 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6020 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
6021 && "invalid operand");
6022 if (argOpers[valArgIndx]->isReg())
6023 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
6025 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
6027 (*MIB).addOperand(*argOpers[valArgIndx]);
6029 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
6032 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
6033 for (int i=0; i <= lastAddrIndx; ++i)
6034 (*MIB).addOperand(*argOpers[i]);
6037 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
6038 MIB.addReg(X86::EAX);
6041 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6043 delete bInstr; // The pseudo instruction is gone now.
6047 // private utility function
6049 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
6050 MachineBasicBlock *MBB,
6052 // For the atomic min/max operator, we generate
6055 // ld t1 = [min/max.addr]
6056 // mov t2 = [min/max.val]
6058 // cmov[cond] t2 = t1
6060 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6062 // fallthrough -->nextMBB
6064 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6065 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6066 ilist<MachineBasicBlock>::iterator MBBIter = MBB;
6069 /// First build the CFG
6070 MachineFunction *F = MBB->getParent();
6071 MachineBasicBlock *thisMBB = MBB;
6072 MachineBasicBlock *newMBB = new MachineBasicBlock(LLVM_BB);
6073 MachineBasicBlock *nextMBB = new MachineBasicBlock(LLVM_BB);
6074 F->getBasicBlockList().insert(MBBIter, newMBB);
6075 F->getBasicBlockList().insert(MBBIter, nextMBB);
6077 // Move all successors to thisMBB to nextMBB
6078 nextMBB->transferSuccessors(thisMBB);
6080 // Update thisMBB to fall through to newMBB
6081 thisMBB->addSuccessor(newMBB);
6083 // newMBB jumps to newMBB and fall through to nextMBB
6084 newMBB->addSuccessor(nextMBB);
6085 newMBB->addSuccessor(newMBB);
6087 // Insert instructions into newMBB based on incoming instruction
6088 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
6089 MachineOperand& destOper = mInstr->getOperand(0);
6090 MachineOperand* argOpers[6];
6091 int numArgs = mInstr->getNumOperands() - 1;
6092 for (int i=0; i < numArgs; ++i)
6093 argOpers[i] = &mInstr->getOperand(i+1);
6095 // x86 address has 4 operands: base, index, scale, and displacement
6096 int lastAddrIndx = 3; // [0,3]
6099 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6100 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
6101 for (int i=0; i <= lastAddrIndx; ++i)
6102 (*MIB).addOperand(*argOpers[i]);
6104 // We only support register and immediate values
6105 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
6106 && "invalid operand");
6108 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6109 if (argOpers[valArgIndx]->isReg())
6110 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6112 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6113 (*MIB).addOperand(*argOpers[valArgIndx]);
6115 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
6118 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
6123 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6124 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
6128 // Cmp and exchange if none has modified the memory location
6129 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
6130 for (int i=0; i <= lastAddrIndx; ++i)
6131 (*MIB).addOperand(*argOpers[i]);
6134 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
6135 MIB.addReg(X86::EAX);
6138 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6140 delete mInstr; // The pseudo instruction is gone now.
6146 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6147 MachineBasicBlock *BB) {
6148 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6149 switch (MI->getOpcode()) {
6150 default: assert(false && "Unexpected instr type to insert");
6151 case X86::CMOV_FR32:
6152 case X86::CMOV_FR64:
6153 case X86::CMOV_V4F32:
6154 case X86::CMOV_V2F64:
6155 case X86::CMOV_V2I64: {
6156 // To "insert" a SELECT_CC instruction, we actually have to insert the
6157 // diamond control-flow pattern. The incoming instruction knows the
6158 // destination vreg to set, the condition code register to branch on, the
6159 // true/false values to select between, and a branch opcode to use.
6160 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6161 ilist<MachineBasicBlock>::iterator It = BB;
6167 // cmpTY ccX, r1, r2
6169 // fallthrough --> copy0MBB
6170 MachineBasicBlock *thisMBB = BB;
6171 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
6172 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
6174 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
6175 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
6176 MachineFunction *F = BB->getParent();
6177 F->getBasicBlockList().insert(It, copy0MBB);
6178 F->getBasicBlockList().insert(It, sinkMBB);
6179 // Update machine-CFG edges by transferring all successors of the current
6180 // block to the new block which will contain the Phi node for the select.
6181 sinkMBB->transferSuccessors(BB);
6183 // Add the true and fallthrough blocks as its successors.
6184 BB->addSuccessor(copy0MBB);
6185 BB->addSuccessor(sinkMBB);
6188 // %FalseValue = ...
6189 // # fallthrough to sinkMBB
6192 // Update machine-CFG edges
6193 BB->addSuccessor(sinkMBB);
6196 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6199 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
6200 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6201 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6203 delete MI; // The pseudo instruction is gone now.
6207 case X86::FP32_TO_INT16_IN_MEM:
6208 case X86::FP32_TO_INT32_IN_MEM:
6209 case X86::FP32_TO_INT64_IN_MEM:
6210 case X86::FP64_TO_INT16_IN_MEM:
6211 case X86::FP64_TO_INT32_IN_MEM:
6212 case X86::FP64_TO_INT64_IN_MEM:
6213 case X86::FP80_TO_INT16_IN_MEM:
6214 case X86::FP80_TO_INT32_IN_MEM:
6215 case X86::FP80_TO_INT64_IN_MEM: {
6216 // Change the floating point control register to use "round towards zero"
6217 // mode when truncating to an integer value.
6218 MachineFunction *F = BB->getParent();
6219 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
6220 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
6222 // Load the old value of the high byte of the control word...
6224 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
6225 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
6227 // Set the high part to be round to zero...
6228 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
6231 // Reload the modified control word now...
6232 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6234 // Restore the memory image of control word to original value
6235 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
6238 // Get the X86 opcode to use.
6240 switch (MI->getOpcode()) {
6241 default: assert(0 && "illegal opcode!");
6242 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
6243 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
6244 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
6245 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
6246 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
6247 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
6248 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
6249 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
6250 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
6254 MachineOperand &Op = MI->getOperand(0);
6255 if (Op.isRegister()) {
6256 AM.BaseType = X86AddressMode::RegBase;
6257 AM.Base.Reg = Op.getReg();
6259 AM.BaseType = X86AddressMode::FrameIndexBase;
6260 AM.Base.FrameIndex = Op.getIndex();
6262 Op = MI->getOperand(1);
6263 if (Op.isImmediate())
6264 AM.Scale = Op.getImm();
6265 Op = MI->getOperand(2);
6266 if (Op.isImmediate())
6267 AM.IndexReg = Op.getImm();
6268 Op = MI->getOperand(3);
6269 if (Op.isGlobalAddress()) {
6270 AM.GV = Op.getGlobal();
6272 AM.Disp = Op.getImm();
6274 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
6275 .addReg(MI->getOperand(4).getReg());
6277 // Reload the original control word now.
6278 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6280 delete MI; // The pseudo instruction is gone now.
6283 case X86::ATOMAND32:
6284 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
6287 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
6289 case X86::ATOMXOR32:
6290 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
6292 case X86::ATOMNAND32:
6293 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
6294 X86::AND32ri, true);
6295 case X86::ATOMMIN32:
6296 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
6297 case X86::ATOMMAX32:
6298 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
6299 case X86::ATOMUMIN32:
6300 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
6301 case X86::ATOMUMAX32:
6302 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
6306 //===----------------------------------------------------------------------===//
6307 // X86 Optimization Hooks
6308 //===----------------------------------------------------------------------===//
6310 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
6314 const SelectionDAG &DAG,
6315 unsigned Depth) const {
6316 unsigned Opc = Op.getOpcode();
6317 assert((Opc >= ISD::BUILTIN_OP_END ||
6318 Opc == ISD::INTRINSIC_WO_CHAIN ||
6319 Opc == ISD::INTRINSIC_W_CHAIN ||
6320 Opc == ISD::INTRINSIC_VOID) &&
6321 "Should use MaskedValueIsZero if you don't know whether Op"
6322 " is a target node!");
6324 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
6328 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
6329 Mask.getBitWidth() - 1);
6334 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
6335 /// node is a GlobalAddress + offset.
6336 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
6337 GlobalValue* &GA, int64_t &Offset) const{
6338 if (N->getOpcode() == X86ISD::Wrapper) {
6339 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
6340 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
6344 return TargetLowering::isGAPlusOffset(N, GA, Offset);
6347 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
6348 const TargetLowering &TLI) {
6351 if (TLI.isGAPlusOffset(Base, GV, Offset))
6352 return (GV->getAlignment() >= N && (Offset % N) == 0);
6353 // DAG combine handles the stack object case.
6357 static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask,
6358 unsigned NumElems, MVT EVT,
6360 SelectionDAG &DAG, MachineFrameInfo *MFI,
6361 const TargetLowering &TLI) {
6363 for (unsigned i = 0; i < NumElems; ++i) {
6364 SDOperand Idx = PermMask.getOperand(i);
6365 if (Idx.getOpcode() == ISD::UNDEF) {
6371 unsigned Index = cast<ConstantSDNode>(Idx)->getValue();
6372 SDOperand Elt = DAG.getShuffleScalarElt(N, Index);
6374 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.Val)))
6378 if (Base->getOpcode() == ISD::UNDEF)
6382 if (Elt.getOpcode() == ISD::UNDEF)
6385 if (!TLI.isConsecutiveLoad(Elt.Val, Base,
6386 EVT.getSizeInBits()/8, i, MFI))
6392 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
6393 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
6394 /// if the load addresses are consecutive, non-overlapping, and in the right
6396 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
6397 const TargetLowering &TLI) {
6398 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6399 MVT VT = N->getValueType(0);
6400 MVT EVT = VT.getVectorElementType();
6401 SDOperand PermMask = N->getOperand(2);
6402 unsigned NumElems = PermMask.getNumOperands();
6403 SDNode *Base = NULL;
6404 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
6408 LoadSDNode *LD = cast<LoadSDNode>(Base);
6409 if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, TLI))
6410 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6411 LD->getSrcValueOffset(), LD->isVolatile());
6412 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
6413 LD->getSrcValueOffset(), LD->isVolatile(),
6414 LD->getAlignment());
6417 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
6418 static SDOperand PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
6419 const X86Subtarget *Subtarget,
6420 const TargetLowering &TLI) {
6421 unsigned NumOps = N->getNumOperands();
6423 // Ignore single operand BUILD_VECTOR.
6427 MVT VT = N->getValueType(0);
6428 MVT EVT = VT.getVectorElementType();
6429 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
6430 // We are looking for load i64 and zero extend. We want to transform
6431 // it before legalizer has a chance to expand it. Also look for i64
6432 // BUILD_PAIR bit casted to f64.
6434 // This must be an insertion into a zero vector.
6435 SDOperand HighElt = N->getOperand(1);
6436 if (!isZeroNode(HighElt))
6439 // Value must be a load.
6440 SDNode *Base = N->getOperand(0).Val;
6441 if (!isa<LoadSDNode>(Base)) {
6442 if (Base->getOpcode() != ISD::BIT_CONVERT)
6444 Base = Base->getOperand(0).Val;
6445 if (!isa<LoadSDNode>(Base))
6449 // Transform it into VZEXT_LOAD addr.
6450 LoadSDNode *LD = cast<LoadSDNode>(Base);
6452 // Load must not be an extload.
6453 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
6456 return DAG.getNode(X86ISD::VZEXT_LOAD, VT, LD->getChain(), LD->getBasePtr());
6459 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
6460 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
6461 const X86Subtarget *Subtarget) {
6462 SDOperand Cond = N->getOperand(0);
6464 // If we have SSE[12] support, try to form min/max nodes.
6465 if (Subtarget->hasSSE2() &&
6466 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
6467 if (Cond.getOpcode() == ISD::SETCC) {
6468 // Get the LHS/RHS of the select.
6469 SDOperand LHS = N->getOperand(1);
6470 SDOperand RHS = N->getOperand(2);
6471 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
6473 unsigned Opcode = 0;
6474 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
6477 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
6480 if (!UnsafeFPMath) break;
6482 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
6484 Opcode = X86ISD::FMIN;
6487 case ISD::SETOGT: // (X > Y) ? X : Y -> max
6490 if (!UnsafeFPMath) break;
6492 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
6494 Opcode = X86ISD::FMAX;
6497 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
6500 case ISD::SETOGT: // (X > Y) ? Y : X -> min
6503 if (!UnsafeFPMath) break;
6505 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
6507 Opcode = X86ISD::FMIN;
6510 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
6513 if (!UnsafeFPMath) break;
6515 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
6517 Opcode = X86ISD::FMAX;
6523 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
6531 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
6532 static SDOperand PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
6533 const X86Subtarget *Subtarget) {
6534 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
6535 // the FP state in cases where an emms may be missing.
6536 // A preferable solution to the general problem is to figure out the right
6537 // places to insert EMMS. This qualifies as a quick hack.
6538 StoreSDNode *St = cast<StoreSDNode>(N);
6539 if (St->getValue().getValueType().isVector() &&
6540 St->getValue().getValueType().getSizeInBits() == 64 &&
6541 isa<LoadSDNode>(St->getValue()) &&
6542 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
6543 St->getChain().hasOneUse() && !St->isVolatile()) {
6544 SDNode* LdVal = St->getValue().Val;
6546 int TokenFactorIndex = -1;
6547 SmallVector<SDOperand, 8> Ops;
6548 SDNode* ChainVal = St->getChain().Val;
6549 // Must be a store of a load. We currently handle two cases: the load
6550 // is a direct child, and it's under an intervening TokenFactor. It is
6551 // possible to dig deeper under nested TokenFactors.
6552 if (ChainVal == LdVal)
6553 Ld = cast<LoadSDNode>(St->getChain());
6554 else if (St->getValue().hasOneUse() &&
6555 ChainVal->getOpcode() == ISD::TokenFactor) {
6556 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
6557 if (ChainVal->getOperand(i).Val == LdVal) {
6558 TokenFactorIndex = i;
6559 Ld = cast<LoadSDNode>(St->getValue());
6561 Ops.push_back(ChainVal->getOperand(i));
6565 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
6566 if (Subtarget->is64Bit()) {
6567 SDOperand NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
6568 Ld->getBasePtr(), Ld->getSrcValue(),
6569 Ld->getSrcValueOffset(), Ld->isVolatile(),
6570 Ld->getAlignment());
6571 SDOperand NewChain = NewLd.getValue(1);
6572 if (TokenFactorIndex != -1) {
6573 Ops.push_back(NewChain);
6574 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6577 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
6578 St->getSrcValue(), St->getSrcValueOffset(),
6579 St->isVolatile(), St->getAlignment());
6582 // Otherwise, lower to two 32-bit copies.
6583 SDOperand LoAddr = Ld->getBasePtr();
6584 SDOperand HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6585 DAG.getConstant(4, MVT::i32));
6587 SDOperand LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
6588 Ld->getSrcValue(), Ld->getSrcValueOffset(),
6589 Ld->isVolatile(), Ld->getAlignment());
6590 SDOperand HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
6591 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
6593 MinAlign(Ld->getAlignment(), 4));
6595 SDOperand NewChain = LoLd.getValue(1);
6596 if (TokenFactorIndex != -1) {
6597 Ops.push_back(LoLd);
6598 Ops.push_back(HiLd);
6599 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
6603 LoAddr = St->getBasePtr();
6604 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
6605 DAG.getConstant(4, MVT::i32));
6607 SDOperand LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
6608 St->getSrcValue(), St->getSrcValueOffset(),
6609 St->isVolatile(), St->getAlignment());
6610 SDOperand HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
6611 St->getSrcValue(), St->getSrcValueOffset()+4,
6613 MinAlign(St->getAlignment(), 4));
6614 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
6620 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
6621 /// X86ISD::FXOR nodes.
6622 static SDOperand PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
6623 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
6624 // F[X]OR(0.0, x) -> x
6625 // F[X]OR(x, 0.0) -> x
6626 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6627 if (C->getValueAPF().isPosZero())
6628 return N->getOperand(1);
6629 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6630 if (C->getValueAPF().isPosZero())
6631 return N->getOperand(0);
6635 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
6636 static SDOperand PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
6637 // FAND(0.0, x) -> 0.0
6638 // FAND(x, 0.0) -> 0.0
6639 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
6640 if (C->getValueAPF().isPosZero())
6641 return N->getOperand(0);
6642 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
6643 if (C->getValueAPF().isPosZero())
6644 return N->getOperand(1);
6649 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
6650 DAGCombinerInfo &DCI) const {
6651 SelectionDAG &DAG = DCI.DAG;
6652 switch (N->getOpcode()) {
6654 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
6655 case ISD::BUILD_VECTOR:
6656 return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
6657 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
6658 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
6660 case X86ISD::FOR: return PerformFORCombine(N, DAG);
6661 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
6667 //===----------------------------------------------------------------------===//
6668 // X86 Inline Assembly Support
6669 //===----------------------------------------------------------------------===//
6671 /// getConstraintType - Given a constraint letter, return the type of
6672 /// constraint it is for this target.
6673 X86TargetLowering::ConstraintType
6674 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
6675 if (Constraint.size() == 1) {
6676 switch (Constraint[0]) {
6687 return C_RegisterClass;
6692 return TargetLowering::getConstraintType(Constraint);
6695 /// LowerXConstraint - try to replace an X constraint, which matches anything,
6696 /// with another that has more specific requirements based on the type of the
6697 /// corresponding operand.
6698 const char *X86TargetLowering::
6699 LowerXConstraint(MVT ConstraintVT) const {
6700 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
6701 // 'f' like normal targets.
6702 if (ConstraintVT.isFloatingPoint()) {
6703 if (Subtarget->hasSSE2())
6705 if (Subtarget->hasSSE1())
6709 return TargetLowering::LowerXConstraint(ConstraintVT);
6712 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
6713 /// vector. If it is invalid, don't add anything to Ops.
6714 void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
6716 std::vector<SDOperand>&Ops,
6717 SelectionDAG &DAG) const {
6718 SDOperand Result(0, 0);
6720 switch (Constraint) {
6723 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
6724 if (C->getValue() <= 31) {
6725 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
6731 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
6732 if (C->getValue() <= 255) {
6733 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
6739 // Literal immediates are always ok.
6740 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
6741 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
6745 // If we are in non-pic codegen mode, we allow the address of a global (with
6746 // an optional displacement) to be used with 'i'.
6747 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
6750 // Match either (GA) or (GA+C)
6752 Offset = GA->getOffset();
6753 } else if (Op.getOpcode() == ISD::ADD) {
6754 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6755 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
6757 Offset = GA->getOffset()+C->getValue();
6759 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6760 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
6762 Offset = GA->getOffset()+C->getValue();
6769 // If addressing this global requires a load (e.g. in PIC mode), we can't
6771 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
6775 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
6781 // Otherwise, not valid for this mode.
6787 Ops.push_back(Result);
6790 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
6793 std::vector<unsigned> X86TargetLowering::
6794 getRegClassForInlineAsmConstraint(const std::string &Constraint,
6796 if (Constraint.size() == 1) {
6797 // FIXME: not handling fp-stack yet!
6798 switch (Constraint[0]) { // GCC X86 Constraint Letters
6799 default: break; // Unknown constraint letter
6800 case 'A': // EAX/EDX
6801 if (VT == MVT::i32 || VT == MVT::i64)
6802 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
6804 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
6807 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
6808 else if (VT == MVT::i16)
6809 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
6810 else if (VT == MVT::i8)
6811 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
6812 else if (VT == MVT::i64)
6813 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
6818 return std::vector<unsigned>();
6821 std::pair<unsigned, const TargetRegisterClass*>
6822 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6824 // First, see if this is a constraint that directly corresponds to an LLVM
6826 if (Constraint.size() == 1) {
6827 // GCC Constraint Letters
6828 switch (Constraint[0]) {
6830 case 'r': // GENERAL_REGS
6831 case 'R': // LEGACY_REGS
6832 case 'l': // INDEX_REGS
6833 if (VT == MVT::i64 && Subtarget->is64Bit())
6834 return std::make_pair(0U, X86::GR64RegisterClass);
6836 return std::make_pair(0U, X86::GR32RegisterClass);
6837 else if (VT == MVT::i16)
6838 return std::make_pair(0U, X86::GR16RegisterClass);
6839 else if (VT == MVT::i8)
6840 return std::make_pair(0U, X86::GR8RegisterClass);
6842 case 'f': // FP Stack registers.
6843 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
6844 // value to the correct fpstack register class.
6845 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
6846 return std::make_pair(0U, X86::RFP32RegisterClass);
6847 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
6848 return std::make_pair(0U, X86::RFP64RegisterClass);
6849 return std::make_pair(0U, X86::RFP80RegisterClass);
6850 case 'y': // MMX_REGS if MMX allowed.
6851 if (!Subtarget->hasMMX()) break;
6852 return std::make_pair(0U, X86::VR64RegisterClass);
6854 case 'Y': // SSE_REGS if SSE2 allowed
6855 if (!Subtarget->hasSSE2()) break;
6857 case 'x': // SSE_REGS if SSE1 allowed
6858 if (!Subtarget->hasSSE1()) break;
6860 switch (VT.getSimpleVT()) {
6862 // Scalar SSE types.
6865 return std::make_pair(0U, X86::FR32RegisterClass);
6868 return std::make_pair(0U, X86::FR64RegisterClass);
6876 return std::make_pair(0U, X86::VR128RegisterClass);
6882 // Use the default implementation in TargetLowering to convert the register
6883 // constraint into a member of a register class.
6884 std::pair<unsigned, const TargetRegisterClass*> Res;
6885 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
6887 // Not found as a standard register?
6888 if (Res.second == 0) {
6889 // GCC calls "st(0)" just plain "st".
6890 if (StringsEqualNoCase("{st}", Constraint)) {
6891 Res.first = X86::ST0;
6892 Res.second = X86::RFP80RegisterClass;
6898 // Otherwise, check to see if this is a register class of the wrong value
6899 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
6900 // turn into {ax},{dx}.
6901 if (Res.second->hasType(VT))
6902 return Res; // Correct type already, nothing to do.
6904 // All of the single-register GCC register classes map their values onto
6905 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
6906 // really want an 8-bit or 32-bit register, map to the appropriate register
6907 // class and return the appropriate register.
6908 if (Res.second != X86::GR16RegisterClass)
6911 if (VT == MVT::i8) {
6912 unsigned DestReg = 0;
6913 switch (Res.first) {
6915 case X86::AX: DestReg = X86::AL; break;
6916 case X86::DX: DestReg = X86::DL; break;
6917 case X86::CX: DestReg = X86::CL; break;
6918 case X86::BX: DestReg = X86::BL; break;
6921 Res.first = DestReg;
6922 Res.second = Res.second = X86::GR8RegisterClass;
6924 } else if (VT == MVT::i32) {
6925 unsigned DestReg = 0;
6926 switch (Res.first) {
6928 case X86::AX: DestReg = X86::EAX; break;
6929 case X86::DX: DestReg = X86::EDX; break;
6930 case X86::CX: DestReg = X86::ECX; break;
6931 case X86::BX: DestReg = X86::EBX; break;
6932 case X86::SI: DestReg = X86::ESI; break;
6933 case X86::DI: DestReg = X86::EDI; break;
6934 case X86::BP: DestReg = X86::EBP; break;
6935 case X86::SP: DestReg = X86::ESP; break;
6938 Res.first = DestReg;
6939 Res.second = Res.second = X86::GR32RegisterClass;
6941 } else if (VT == MVT::i64) {
6942 unsigned DestReg = 0;
6943 switch (Res.first) {
6945 case X86::AX: DestReg = X86::RAX; break;
6946 case X86::DX: DestReg = X86::RDX; break;
6947 case X86::CX: DestReg = X86::RCX; break;
6948 case X86::BX: DestReg = X86::RBX; break;
6949 case X86::SI: DestReg = X86::RSI; break;
6950 case X86::DI: DestReg = X86::RDI; break;
6951 case X86::BP: DestReg = X86::RBP; break;
6952 case X86::SP: DestReg = X86::RSP; break;
6955 Res.first = DestReg;
6956 Res.second = Res.second = X86::GR64RegisterClass;