1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86MCTargetExpr.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
53 STATISTIC(NumTailCalls, "Number of tail calls");
56 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
58 // Disable16Bit - 16-bit operations typically have a larger encoding than
59 // corresponding 32-bit instructions, and 16-bit code is slow on some
60 // processors. This is an experimental flag to disable 16-bit operations
61 // (which forces them to be Legalized to 32-bit operations).
63 Disable16Bit("disable-16bit", cl::Hidden,
64 cl::desc("Disable use of 16-bit instructions"));
66 // Forward declarations.
67 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
70 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
71 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
72 default: llvm_unreachable("unknown subtarget type");
73 case X86Subtarget::isDarwin:
74 if (TM.getSubtarget<X86Subtarget>().is64Bit())
75 return new X8664_MachoTargetObjectFile();
76 return new X8632_MachoTargetObjectFile();
77 case X86Subtarget::isELF:
78 if (TM.getSubtarget<X86Subtarget>().is64Bit())
79 return new X8664_ELFTargetObjectFile(TM);
80 return new X8632_ELFTargetObjectFile(TM);
81 case X86Subtarget::isMingw:
82 case X86Subtarget::isCygwin:
83 case X86Subtarget::isWindows:
84 return new TargetLoweringObjectFileCOFF();
88 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
89 : TargetLowering(TM, createTLOF(TM)) {
90 Subtarget = &TM.getSubtarget<X86Subtarget>();
91 X86ScalarSSEf64 = Subtarget->hasSSE2();
92 X86ScalarSSEf32 = Subtarget->hasSSE1();
93 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
95 RegInfo = TM.getRegisterInfo();
98 // Set up the TargetLowering object.
100 // X86 is weird, it always uses i8 for shift amounts and setcc results.
101 setShiftAmountType(MVT::i8);
102 setBooleanContents(ZeroOrOneBooleanContent);
103 setSchedulingPreference(SchedulingForRegPressure);
104 setStackPointerRegisterToSaveRestore(X86StackPtr);
106 if (Subtarget->isTargetDarwin()) {
107 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
108 setUseUnderscoreSetJmp(false);
109 setUseUnderscoreLongJmp(false);
110 } else if (Subtarget->isTargetMingw()) {
111 // MS runtime is weird: it exports _setjmp, but longjmp!
112 setUseUnderscoreSetJmp(true);
113 setUseUnderscoreLongJmp(false);
115 setUseUnderscoreSetJmp(true);
116 setUseUnderscoreLongJmp(true);
119 // Set up the register classes.
120 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
122 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
123 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
124 if (Subtarget->is64Bit())
125 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
127 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
129 // We don't accept any truncstore of integer registers.
130 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
132 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
133 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
135 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
136 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
137 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
139 // SETOEQ and SETUNE require checking two conditions.
140 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
141 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
142 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
143 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
144 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
145 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
147 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
149 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
150 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
151 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
153 if (Subtarget->is64Bit()) {
154 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
155 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
156 } else if (!UseSoftFloat) {
157 if (X86ScalarSSEf64) {
158 // We have an impenetrably clever algorithm for ui64->double only.
159 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
161 // We have an algorithm for SSE2, and we turn this into a 64-bit
162 // FILD for other targets.
163 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
166 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
168 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
169 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
172 // SSE has no i16 to fp conversion, only i32
173 if (X86ScalarSSEf32) {
174 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
175 // f32 and f64 cases are Legal, f80 case is not
176 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
178 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
179 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
182 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
183 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
186 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
187 // are Legal, f80 is custom lowered.
188 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
189 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
191 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
193 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
194 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
196 if (X86ScalarSSEf32) {
197 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
198 // f32 and f64 cases are Legal, f80 case is not
199 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
201 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
202 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
205 // Handle FP_TO_UINT by promoting the destination to a larger signed
207 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
208 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
209 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
211 if (Subtarget->is64Bit()) {
212 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
213 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
214 } else if (!UseSoftFloat) {
215 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
216 // Expand FP_TO_UINT into a select.
217 // FIXME: We would like to use a Custom expander here eventually to do
218 // the optimal thing for SSE vs. the default expansion in the legalizer.
219 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
221 // With SSE3 we can use fisttpll to convert to a signed i64; without
222 // SSE, we're stuck with a fistpll.
223 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
226 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
227 if (!X86ScalarSSEf64) {
228 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
229 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
232 // Scalar integer divide and remainder are lowered to use operations that
233 // produce two results, to match the available instructions. This exposes
234 // the two-result form to trivial CSE, which is able to combine x/y and x%y
235 // into a single instruction.
237 // Scalar integer multiply-high is also lowered to use two-result
238 // operations, to match the available instructions. However, plain multiply
239 // (low) operations are left as Legal, as there are single-result
240 // instructions for this in x86. Using the two-result multiply instructions
241 // when both high and low results are needed must be arranged by dagcombine.
242 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
243 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
244 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
245 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
246 setOperationAction(ISD::SREM , MVT::i8 , Expand);
247 setOperationAction(ISD::UREM , MVT::i8 , Expand);
248 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
249 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
250 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
251 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
252 setOperationAction(ISD::SREM , MVT::i16 , Expand);
253 setOperationAction(ISD::UREM , MVT::i16 , Expand);
254 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
255 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
256 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
257 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
258 setOperationAction(ISD::SREM , MVT::i32 , Expand);
259 setOperationAction(ISD::UREM , MVT::i32 , Expand);
260 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
261 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
262 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
263 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
264 setOperationAction(ISD::SREM , MVT::i64 , Expand);
265 setOperationAction(ISD::UREM , MVT::i64 , Expand);
267 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
268 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
269 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
270 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
271 if (Subtarget->is64Bit())
272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
273 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
275 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
276 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
277 setOperationAction(ISD::FREM , MVT::f32 , Expand);
278 setOperationAction(ISD::FREM , MVT::f64 , Expand);
279 setOperationAction(ISD::FREM , MVT::f80 , Expand);
280 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
282 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
283 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
284 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
285 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
287 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
288 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
290 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
291 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
293 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
294 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
295 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
296 if (Subtarget->is64Bit()) {
297 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
298 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
299 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
302 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
303 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
305 // These should be promoted to a larger select which is supported.
306 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
307 // X86 wants to expand cmov itself.
308 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
310 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
312 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
313 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
314 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
315 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
316 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
317 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
319 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
321 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
322 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
323 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
324 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
325 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
326 if (Subtarget->is64Bit()) {
327 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
328 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
330 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
333 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
334 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
335 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
336 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
337 if (Subtarget->is64Bit())
338 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
339 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
340 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
341 if (Subtarget->is64Bit()) {
342 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
343 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
344 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
345 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
346 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
348 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
349 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
350 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
351 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
352 if (Subtarget->is64Bit()) {
353 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
354 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
355 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
358 if (Subtarget->hasSSE1())
359 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
361 if (!Subtarget->hasSSE2())
362 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
364 // Expand certain atomics
365 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
366 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
368 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
375 if (!Subtarget->is64Bit()) {
376 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
377 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
378 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
379 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
380 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
381 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
382 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
385 // FIXME - use subtarget debug flags
386 if (!Subtarget->isTargetDarwin() &&
387 !Subtarget->isTargetELF() &&
388 !Subtarget->isTargetCygMing()) {
389 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
392 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
393 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
394 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
395 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
396 if (Subtarget->is64Bit()) {
397 setExceptionPointerRegister(X86::RAX);
398 setExceptionSelectorRegister(X86::RDX);
400 setExceptionPointerRegister(X86::EAX);
401 setExceptionSelectorRegister(X86::EDX);
403 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
404 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
406 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
408 setOperationAction(ISD::TRAP, MVT::Other, Legal);
410 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
411 setOperationAction(ISD::VASTART , MVT::Other, Custom);
412 setOperationAction(ISD::VAEND , MVT::Other, Expand);
413 if (Subtarget->is64Bit()) {
414 setOperationAction(ISD::VAARG , MVT::Other, Custom);
415 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
417 setOperationAction(ISD::VAARG , MVT::Other, Expand);
418 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
421 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
422 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
423 if (Subtarget->is64Bit())
424 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
425 if (Subtarget->isTargetCygMing())
426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
428 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
430 if (!UseSoftFloat && X86ScalarSSEf64) {
431 // f32 and f64 use SSE.
432 // Set up the FP register classes.
433 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
434 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
436 // Use ANDPD to simulate FABS.
437 setOperationAction(ISD::FABS , MVT::f64, Custom);
438 setOperationAction(ISD::FABS , MVT::f32, Custom);
440 // Use XORP to simulate FNEG.
441 setOperationAction(ISD::FNEG , MVT::f64, Custom);
442 setOperationAction(ISD::FNEG , MVT::f32, Custom);
444 // Use ANDPD and ORPD to simulate FCOPYSIGN.
445 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
446 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
448 // We don't support sin/cos/fmod
449 setOperationAction(ISD::FSIN , MVT::f64, Expand);
450 setOperationAction(ISD::FCOS , MVT::f64, Expand);
451 setOperationAction(ISD::FSIN , MVT::f32, Expand);
452 setOperationAction(ISD::FCOS , MVT::f32, Expand);
454 // Expand FP immediates into loads from the stack, except for the special
456 addLegalFPImmediate(APFloat(+0.0)); // xorpd
457 addLegalFPImmediate(APFloat(+0.0f)); // xorps
458 } else if (!UseSoftFloat && X86ScalarSSEf32) {
459 // Use SSE for f32, x87 for f64.
460 // Set up the FP register classes.
461 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
462 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
464 // Use ANDPS to simulate FABS.
465 setOperationAction(ISD::FABS , MVT::f32, Custom);
467 // Use XORP to simulate FNEG.
468 setOperationAction(ISD::FNEG , MVT::f32, Custom);
470 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
472 // Use ANDPS and ORPS to simulate FCOPYSIGN.
473 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
474 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
476 // We don't support sin/cos/fmod
477 setOperationAction(ISD::FSIN , MVT::f32, Expand);
478 setOperationAction(ISD::FCOS , MVT::f32, Expand);
480 // Special cases we handle for FP constants.
481 addLegalFPImmediate(APFloat(+0.0f)); // xorps
482 addLegalFPImmediate(APFloat(+0.0)); // FLD0
483 addLegalFPImmediate(APFloat(+1.0)); // FLD1
484 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
485 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
488 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
489 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
491 } else if (!UseSoftFloat) {
492 // f32 and f64 in x87.
493 // Set up the FP register classes.
494 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
495 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
497 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
498 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
499 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
500 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
503 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
504 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
506 addLegalFPImmediate(APFloat(+0.0)); // FLD0
507 addLegalFPImmediate(APFloat(+1.0)); // FLD1
508 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
509 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
510 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
511 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
512 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
513 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
516 // Long double always uses X87.
518 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
519 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
520 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
523 APFloat TmpFlt(+0.0);
524 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
526 addLegalFPImmediate(TmpFlt); // FLD0
528 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
529 APFloat TmpFlt2(+1.0);
530 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
532 addLegalFPImmediate(TmpFlt2); // FLD1
533 TmpFlt2.changeSign();
534 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
538 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
539 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
543 // Always use a library call for pow.
544 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
545 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
546 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
548 setOperationAction(ISD::FLOG, MVT::f80, Expand);
549 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
550 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
551 setOperationAction(ISD::FEXP, MVT::f80, Expand);
552 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
554 // First set operation action for all vector types to either promote
555 // (for widening) or expand (for scalarization). Then we will selectively
556 // turn on ones that can be effectively codegen'd.
557 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
558 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
559 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
574 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
575 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
605 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
606 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
608 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
609 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
610 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
611 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
612 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
613 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
614 setTruncStoreAction((MVT::SimpleValueType)VT,
615 (MVT::SimpleValueType)InnerVT, Expand);
616 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
617 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
618 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
621 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
622 // with -msoft-float, disable use of MMX as well.
623 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
624 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
625 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
626 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
627 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
628 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
630 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
631 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
632 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
633 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
635 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
636 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
637 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
638 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
640 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
641 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
643 setOperationAction(ISD::AND, MVT::v8i8, Promote);
644 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
645 setOperationAction(ISD::AND, MVT::v4i16, Promote);
646 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
647 setOperationAction(ISD::AND, MVT::v2i32, Promote);
648 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
649 setOperationAction(ISD::AND, MVT::v1i64, Legal);
651 setOperationAction(ISD::OR, MVT::v8i8, Promote);
652 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
653 setOperationAction(ISD::OR, MVT::v4i16, Promote);
654 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
655 setOperationAction(ISD::OR, MVT::v2i32, Promote);
656 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
657 setOperationAction(ISD::OR, MVT::v1i64, Legal);
659 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
660 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
661 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
662 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
663 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
664 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
665 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
667 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
668 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
669 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
670 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
671 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
672 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
673 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
674 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
675 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
677 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
678 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
679 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
680 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
681 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
683 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
684 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
685 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
686 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
688 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
689 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
690 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
691 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
693 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
695 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
696 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
697 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
698 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
699 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
700 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
701 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
704 if (!UseSoftFloat && Subtarget->hasSSE1()) {
705 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
707 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
708 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
709 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
710 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
711 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
712 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
713 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
714 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
715 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
716 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
717 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
718 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
721 if (!UseSoftFloat && Subtarget->hasSSE2()) {
722 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
724 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
725 // registers cannot be used even for integer operations.
726 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
727 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
728 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
729 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
731 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
732 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
733 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
734 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
735 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
736 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
737 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
738 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
739 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
740 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
741 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
742 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
743 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
744 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
745 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
746 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
748 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
749 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
750 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
751 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
753 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
754 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
755 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
756 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
757 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
759 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
760 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
763 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
765 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
766 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
767 EVT VT = (MVT::SimpleValueType)i;
768 // Do not attempt to custom lower non-power-of-2 vectors
769 if (!isPowerOf2_32(VT.getVectorNumElements()))
771 // Do not attempt to custom lower non-128-bit vectors
772 if (!VT.is128BitVector())
774 setOperationAction(ISD::BUILD_VECTOR,
775 VT.getSimpleVT().SimpleTy, Custom);
776 setOperationAction(ISD::VECTOR_SHUFFLE,
777 VT.getSimpleVT().SimpleTy, Custom);
778 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
779 VT.getSimpleVT().SimpleTy, Custom);
782 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
783 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
785 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
786 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
787 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
789 if (Subtarget->is64Bit()) {
790 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
791 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
794 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
795 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
796 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
799 // Do not attempt to promote non-128-bit vectors
800 if (!VT.is128BitVector()) {
803 setOperationAction(ISD::AND, SVT, Promote);
804 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
805 setOperationAction(ISD::OR, SVT, Promote);
806 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
807 setOperationAction(ISD::XOR, SVT, Promote);
808 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
809 setOperationAction(ISD::LOAD, SVT, Promote);
810 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
811 setOperationAction(ISD::SELECT, SVT, Promote);
812 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
815 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
817 // Custom lower v2i64 and v2f64 selects.
818 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
819 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
820 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
821 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
823 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
824 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
825 if (!DisableMMX && Subtarget->hasMMX()) {
826 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
827 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
831 if (Subtarget->hasSSE41()) {
832 // FIXME: Do we need to handle scalar-to-vector here?
833 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
835 // i8 and i16 vectors are custom , because the source register and source
836 // source memory operand types are not the same width. f32 vectors are
837 // custom since the immediate controlling the insert encodes additional
839 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
844 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
845 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
849 if (Subtarget->is64Bit()) {
850 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
851 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
855 if (Subtarget->hasSSE42()) {
856 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
859 if (!UseSoftFloat && Subtarget->hasAVX()) {
860 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
861 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
862 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
863 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
865 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
866 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
867 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
868 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
869 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
870 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
871 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
872 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
873 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
874 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
875 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
876 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
877 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
878 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
879 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
881 // Operations to consider commented out -v16i16 v32i8
882 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
883 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
884 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
885 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
886 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
887 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
888 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
889 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
890 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
891 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
892 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
893 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
894 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
895 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
897 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
898 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
899 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
900 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
902 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
903 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
904 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
905 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
906 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
908 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
909 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
910 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
911 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
913 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
916 // Not sure we want to do this since there are no 256-bit integer
919 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
920 // This includes 256-bit vectors
921 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
922 EVT VT = (MVT::SimpleValueType)i;
924 // Do not attempt to custom lower non-power-of-2 vectors
925 if (!isPowerOf2_32(VT.getVectorNumElements()))
928 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
929 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
930 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
933 if (Subtarget->is64Bit()) {
934 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
935 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
940 // Not sure we want to do this since there are no 256-bit integer
943 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
944 // Including 256-bit vectors
945 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
946 EVT VT = (MVT::SimpleValueType)i;
948 if (!VT.is256BitVector()) {
951 setOperationAction(ISD::AND, VT, Promote);
952 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
953 setOperationAction(ISD::OR, VT, Promote);
954 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
955 setOperationAction(ISD::XOR, VT, Promote);
956 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
957 setOperationAction(ISD::LOAD, VT, Promote);
958 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
959 setOperationAction(ISD::SELECT, VT, Promote);
960 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
963 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
967 // We want to custom lower some of our intrinsics.
968 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
970 // Add/Sub/Mul with overflow operations are custom lowered.
971 setOperationAction(ISD::SADDO, MVT::i32, Custom);
972 setOperationAction(ISD::SADDO, MVT::i64, Custom);
973 setOperationAction(ISD::UADDO, MVT::i32, Custom);
974 setOperationAction(ISD::UADDO, MVT::i64, Custom);
975 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
976 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
977 setOperationAction(ISD::USUBO, MVT::i32, Custom);
978 setOperationAction(ISD::USUBO, MVT::i64, Custom);
979 setOperationAction(ISD::SMULO, MVT::i32, Custom);
980 setOperationAction(ISD::SMULO, MVT::i64, Custom);
982 if (!Subtarget->is64Bit()) {
983 // These libcalls are not available in 32-bit.
984 setLibcallName(RTLIB::SHL_I128, 0);
985 setLibcallName(RTLIB::SRL_I128, 0);
986 setLibcallName(RTLIB::SRA_I128, 0);
989 // We have target-specific dag combine patterns for the following nodes:
990 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
991 setTargetDAGCombine(ISD::BUILD_VECTOR);
992 setTargetDAGCombine(ISD::SELECT);
993 setTargetDAGCombine(ISD::AND);
994 setTargetDAGCombine(ISD::SHL);
995 setTargetDAGCombine(ISD::SRA);
996 setTargetDAGCombine(ISD::SRL);
997 setTargetDAGCombine(ISD::OR);
998 setTargetDAGCombine(ISD::STORE);
999 setTargetDAGCombine(ISD::MEMBARRIER);
1000 setTargetDAGCombine(ISD::ZERO_EXTEND);
1001 if (Subtarget->is64Bit())
1002 setTargetDAGCombine(ISD::MUL);
1004 computeRegisterProperties();
1006 // FIXME: These should be based on subtarget info. Plus, the values should
1007 // be smaller when we are in optimizing for size mode.
1008 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1009 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
1010 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1011 setPrefLoopAlignment(16);
1012 benefitFromCodePlacementOpt = true;
1016 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1021 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1022 /// the desired ByVal argument alignment.
1023 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1026 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1027 if (VTy->getBitWidth() == 128)
1029 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1030 unsigned EltAlign = 0;
1031 getMaxByValAlign(ATy->getElementType(), EltAlign);
1032 if (EltAlign > MaxAlign)
1033 MaxAlign = EltAlign;
1034 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1035 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1036 unsigned EltAlign = 0;
1037 getMaxByValAlign(STy->getElementType(i), EltAlign);
1038 if (EltAlign > MaxAlign)
1039 MaxAlign = EltAlign;
1047 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1048 /// function arguments in the caller parameter area. For X86, aggregates
1049 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1050 /// are at 4-byte boundaries.
1051 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1052 if (Subtarget->is64Bit()) {
1053 // Max of 8 and alignment of type.
1054 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1061 if (Subtarget->hasSSE1())
1062 getMaxByValAlign(Ty, Align);
1066 /// getOptimalMemOpType - Returns the target specific optimal type for load
1067 /// and store operations as a result of memset, memcpy, and memmove
1068 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1071 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1072 bool isSrcConst, bool isSrcStr,
1073 SelectionDAG &DAG) const {
1074 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1075 // linux. This is because the stack realignment code can't handle certain
1076 // cases like PR2962. This should be removed when PR2962 is fixed.
1077 const Function *F = DAG.getMachineFunction().getFunction();
1078 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1079 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1080 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1082 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1085 if (Subtarget->is64Bit() && Size >= 8)
1090 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1091 /// current function. The returned value is a member of the
1092 /// MachineJumpTableInfo::JTEntryKind enum.
1093 unsigned X86TargetLowering::getJumpTableEncoding() const {
1094 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1096 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1097 Subtarget->isPICStyleGOT())
1098 return MachineJumpTableInfo::EK_Custom32;
1100 // Otherwise, use the normal jump table encoding heuristics.
1101 return TargetLowering::getJumpTableEncoding();
1104 /// getPICBaseSymbol - Return the X86-32 PIC base.
1106 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1107 MCContext &Ctx) const {
1108 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1109 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1110 Twine(MF->getFunctionNumber())+"$pb");
1115 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1116 const MachineBasicBlock *MBB,
1117 unsigned uid,MCContext &Ctx) const{
1118 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1119 Subtarget->isPICStyleGOT());
1120 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1122 return X86MCTargetExpr::Create(MBB->getSymbol(Ctx),
1123 X86MCTargetExpr::GOTOFF, Ctx);
1126 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1128 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1129 SelectionDAG &DAG) const {
1130 if (!Subtarget->is64Bit())
1131 // This doesn't have DebugLoc associated with it, but is not really the
1132 // same as a Register.
1133 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1138 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1139 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1141 const MCExpr *X86TargetLowering::
1142 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1143 MCContext &Ctx) const {
1144 // X86-64 uses RIP relative addressing based on the jump table label.
1145 if (Subtarget->isPICStyleRIPRel())
1146 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1148 // Otherwise, the reference is relative to the PIC base.
1149 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1152 /// getFunctionAlignment - Return the Log2 alignment of this function.
1153 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1154 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1157 //===----------------------------------------------------------------------===//
1158 // Return Value Calling Convention Implementation
1159 //===----------------------------------------------------------------------===//
1161 #include "X86GenCallingConv.inc"
1164 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1165 const SmallVectorImpl<EVT> &OutTys,
1166 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1167 SelectionDAG &DAG) {
1168 SmallVector<CCValAssign, 16> RVLocs;
1169 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1170 RVLocs, *DAG.getContext());
1171 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1175 X86TargetLowering::LowerReturn(SDValue Chain,
1176 CallingConv::ID CallConv, bool isVarArg,
1177 const SmallVectorImpl<ISD::OutputArg> &Outs,
1178 DebugLoc dl, SelectionDAG &DAG) {
1180 SmallVector<CCValAssign, 16> RVLocs;
1181 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1182 RVLocs, *DAG.getContext());
1183 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1185 // Add the regs to the liveout set for the function.
1186 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1187 for (unsigned i = 0; i != RVLocs.size(); ++i)
1188 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1189 MRI.addLiveOut(RVLocs[i].getLocReg());
1193 SmallVector<SDValue, 6> RetOps;
1194 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1195 // Operand #1 = Bytes To Pop
1196 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1198 // Copy the result values into the output registers.
1199 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1200 CCValAssign &VA = RVLocs[i];
1201 assert(VA.isRegLoc() && "Can only return in registers!");
1202 SDValue ValToCopy = Outs[i].Val;
1204 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1205 // the RET instruction and handled by the FP Stackifier.
1206 if (VA.getLocReg() == X86::ST0 ||
1207 VA.getLocReg() == X86::ST1) {
1208 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1209 // change the value to the FP stack register class.
1210 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1211 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1212 RetOps.push_back(ValToCopy);
1213 // Don't emit a copytoreg.
1217 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1218 // which is returned in RAX / RDX.
1219 if (Subtarget->is64Bit()) {
1220 EVT ValVT = ValToCopy.getValueType();
1221 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1222 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1223 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1224 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1228 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1229 Flag = Chain.getValue(1);
1232 // The x86-64 ABI for returning structs by value requires that we copy
1233 // the sret argument into %rax for the return. We saved the argument into
1234 // a virtual register in the entry block, so now we copy the value out
1236 if (Subtarget->is64Bit() &&
1237 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1238 MachineFunction &MF = DAG.getMachineFunction();
1239 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1240 unsigned Reg = FuncInfo->getSRetReturnReg();
1242 Reg = MRI.createVirtualRegister(getRegClassFor(MVT::i64));
1243 FuncInfo->setSRetReturnReg(Reg);
1245 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1247 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1248 Flag = Chain.getValue(1);
1250 // RAX now acts like a return value.
1251 MRI.addLiveOut(X86::RAX);
1254 RetOps[0] = Chain; // Update chain.
1256 // Add the flag if we have it.
1258 RetOps.push_back(Flag);
1260 return DAG.getNode(X86ISD::RET_FLAG, dl,
1261 MVT::Other, &RetOps[0], RetOps.size());
1264 /// LowerCallResult - Lower the result values of a call into the
1265 /// appropriate copies out of appropriate physical registers.
1268 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1269 CallingConv::ID CallConv, bool isVarArg,
1270 const SmallVectorImpl<ISD::InputArg> &Ins,
1271 DebugLoc dl, SelectionDAG &DAG,
1272 SmallVectorImpl<SDValue> &InVals) {
1274 // Assign locations to each value returned by this call.
1275 SmallVector<CCValAssign, 16> RVLocs;
1276 bool Is64Bit = Subtarget->is64Bit();
1277 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1278 RVLocs, *DAG.getContext());
1279 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1281 // Copy all of the result registers out of their specified physreg.
1282 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1283 CCValAssign &VA = RVLocs[i];
1284 EVT CopyVT = VA.getValVT();
1286 // If this is x86-64, and we disabled SSE, we can't return FP values
1287 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1288 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1289 llvm_report_error("SSE register return with SSE disabled");
1292 // If this is a call to a function that returns an fp value on the floating
1293 // point stack, but where we prefer to use the value in xmm registers, copy
1294 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1295 if ((VA.getLocReg() == X86::ST0 ||
1296 VA.getLocReg() == X86::ST1) &&
1297 isScalarFPTypeInSSEReg(VA.getValVT())) {
1302 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1303 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1304 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1305 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1306 MVT::v2i64, InFlag).getValue(1);
1307 Val = Chain.getValue(0);
1308 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1309 Val, DAG.getConstant(0, MVT::i64));
1311 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1312 MVT::i64, InFlag).getValue(1);
1313 Val = Chain.getValue(0);
1315 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1317 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1318 CopyVT, InFlag).getValue(1);
1319 Val = Chain.getValue(0);
1321 InFlag = Chain.getValue(2);
1323 if (CopyVT != VA.getValVT()) {
1324 // Round the F80 the right size, which also moves to the appropriate xmm
1326 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1327 // This truncation won't change the value.
1328 DAG.getIntPtrConstant(1));
1331 InVals.push_back(Val);
1338 //===----------------------------------------------------------------------===//
1339 // C & StdCall & Fast Calling Convention implementation
1340 //===----------------------------------------------------------------------===//
1341 // StdCall calling convention seems to be standard for many Windows' API
1342 // routines and around. It differs from C calling convention just a little:
1343 // callee should clean up the stack, not caller. Symbols should be also
1344 // decorated in some fancy way :) It doesn't support any vector arguments.
1345 // For info on fast calling convention see Fast Calling Convention (tail call)
1346 // implementation LowerX86_32FastCCCallTo.
1348 /// CallIsStructReturn - Determines whether a call uses struct return
1350 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1354 return Outs[0].Flags.isSRet();
1357 /// ArgsAreStructReturn - Determines whether a function uses struct
1358 /// return semantics.
1360 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1364 return Ins[0].Flags.isSRet();
1367 /// IsCalleePop - Determines whether the callee is required to pop its
1368 /// own arguments. Callee pop is necessary to support tail calls.
1369 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1373 switch (CallingConv) {
1376 case CallingConv::X86_StdCall:
1377 return !Subtarget->is64Bit();
1378 case CallingConv::X86_FastCall:
1379 return !Subtarget->is64Bit();
1380 case CallingConv::Fast:
1381 return GuaranteedTailCallOpt;
1385 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1386 /// given CallingConvention value.
1387 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1388 if (Subtarget->is64Bit()) {
1389 if (Subtarget->isTargetWin64())
1390 return CC_X86_Win64_C;
1395 if (CC == CallingConv::X86_FastCall)
1396 return CC_X86_32_FastCall;
1397 else if (CC == CallingConv::Fast)
1398 return CC_X86_32_FastCC;
1403 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1404 /// by "Src" to address "Dst" with size and alignment information specified by
1405 /// the specific parameter attribute. The copy will be passed as a byval
1406 /// function parameter.
1408 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1409 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1411 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1412 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1413 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1416 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1417 /// a tailcall target by changing its ABI.
1418 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1419 return GuaranteedTailCallOpt && CC == CallingConv::Fast;
1423 X86TargetLowering::LowerMemArgument(SDValue Chain,
1424 CallingConv::ID CallConv,
1425 const SmallVectorImpl<ISD::InputArg> &Ins,
1426 DebugLoc dl, SelectionDAG &DAG,
1427 const CCValAssign &VA,
1428 MachineFrameInfo *MFI,
1430 // Create the nodes corresponding to a load from this parameter slot.
1431 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1432 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1433 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1436 // If value is passed by pointer we have address passed instead of the value
1438 if (VA.getLocInfo() == CCValAssign::Indirect)
1439 ValVT = VA.getLocVT();
1441 ValVT = VA.getValVT();
1443 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1444 // changed with more analysis.
1445 // In case of tail call optimization mark all arguments mutable. Since they
1446 // could be overwritten by lowering of arguments in case of a tail call.
1447 if (Flags.isByVal()) {
1448 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1449 VA.getLocMemOffset(), isImmutable, false);
1450 return DAG.getFrameIndex(FI, getPointerTy());
1452 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1453 VA.getLocMemOffset(), isImmutable, false);
1454 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1455 return DAG.getLoad(ValVT, dl, Chain, FIN,
1456 PseudoSourceValue::getFixedStack(FI), 0,
1462 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1463 CallingConv::ID CallConv,
1465 const SmallVectorImpl<ISD::InputArg> &Ins,
1468 SmallVectorImpl<SDValue> &InVals) {
1470 MachineFunction &MF = DAG.getMachineFunction();
1471 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1473 const Function* Fn = MF.getFunction();
1474 if (Fn->hasExternalLinkage() &&
1475 Subtarget->isTargetCygMing() &&
1476 Fn->getName() == "main")
1477 FuncInfo->setForceFramePointer(true);
1479 MachineFrameInfo *MFI = MF.getFrameInfo();
1480 bool Is64Bit = Subtarget->is64Bit();
1481 bool IsWin64 = Subtarget->isTargetWin64();
1483 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1484 "Var args not supported with calling convention fastcc");
1486 // Assign locations to all of the incoming arguments.
1487 SmallVector<CCValAssign, 16> ArgLocs;
1488 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1489 ArgLocs, *DAG.getContext());
1490 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1492 unsigned LastVal = ~0U;
1494 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1495 CCValAssign &VA = ArgLocs[i];
1496 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1498 assert(VA.getValNo() != LastVal &&
1499 "Don't support value assigned to multiple locs yet");
1500 LastVal = VA.getValNo();
1502 if (VA.isRegLoc()) {
1503 EVT RegVT = VA.getLocVT();
1504 TargetRegisterClass *RC = NULL;
1505 if (RegVT == MVT::i32)
1506 RC = X86::GR32RegisterClass;
1507 else if (Is64Bit && RegVT == MVT::i64)
1508 RC = X86::GR64RegisterClass;
1509 else if (RegVT == MVT::f32)
1510 RC = X86::FR32RegisterClass;
1511 else if (RegVT == MVT::f64)
1512 RC = X86::FR64RegisterClass;
1513 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1514 RC = X86::VR128RegisterClass;
1515 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1516 RC = X86::VR64RegisterClass;
1518 llvm_unreachable("Unknown argument type!");
1520 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1521 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1523 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1524 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1526 if (VA.getLocInfo() == CCValAssign::SExt)
1527 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1528 DAG.getValueType(VA.getValVT()));
1529 else if (VA.getLocInfo() == CCValAssign::ZExt)
1530 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1531 DAG.getValueType(VA.getValVT()));
1532 else if (VA.getLocInfo() == CCValAssign::BCvt)
1533 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1535 if (VA.isExtInLoc()) {
1536 // Handle MMX values passed in XMM regs.
1537 if (RegVT.isVector()) {
1538 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1539 ArgValue, DAG.getConstant(0, MVT::i64));
1540 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1542 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1545 assert(VA.isMemLoc());
1546 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1549 // If value is passed via pointer - do a load.
1550 if (VA.getLocInfo() == CCValAssign::Indirect)
1551 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
1554 InVals.push_back(ArgValue);
1557 // The x86-64 ABI for returning structs by value requires that we copy
1558 // the sret argument into %rax for the return. Save the argument into
1559 // a virtual register so that we can access it from the return points.
1560 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1561 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1562 unsigned Reg = FuncInfo->getSRetReturnReg();
1564 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1565 FuncInfo->setSRetReturnReg(Reg);
1567 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1568 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1571 unsigned StackSize = CCInfo.getNextStackOffset();
1572 // Align stack specially for tail calls.
1573 if (FuncIsMadeTailCallSafe(CallConv))
1574 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1576 // If the function takes variable number of arguments, make a frame index for
1577 // the start of the first vararg value... for expansion of llvm.va_start.
1579 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1580 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false);
1583 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1585 // FIXME: We should really autogenerate these arrays
1586 static const unsigned GPR64ArgRegsWin64[] = {
1587 X86::RCX, X86::RDX, X86::R8, X86::R9
1589 static const unsigned XMMArgRegsWin64[] = {
1590 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1592 static const unsigned GPR64ArgRegs64Bit[] = {
1593 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1595 static const unsigned XMMArgRegs64Bit[] = {
1596 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1597 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1599 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1602 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1603 GPR64ArgRegs = GPR64ArgRegsWin64;
1604 XMMArgRegs = XMMArgRegsWin64;
1606 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1607 GPR64ArgRegs = GPR64ArgRegs64Bit;
1608 XMMArgRegs = XMMArgRegs64Bit;
1610 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1612 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1615 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1616 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1617 "SSE register cannot be used when SSE is disabled!");
1618 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1619 "SSE register cannot be used when SSE is disabled!");
1620 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1621 // Kernel mode asks for SSE to be disabled, so don't push them
1623 TotalNumXMMRegs = 0;
1625 // For X86-64, if there are vararg parameters that are passed via
1626 // registers, then we must store them to their spots on the stack so they
1627 // may be loaded by deferencing the result of va_next.
1628 VarArgsGPOffset = NumIntRegs * 8;
1629 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1630 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1631 TotalNumXMMRegs * 16, 16,
1634 // Store the integer parameter registers.
1635 SmallVector<SDValue, 8> MemOps;
1636 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1637 unsigned Offset = VarArgsGPOffset;
1638 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1639 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1640 DAG.getIntPtrConstant(Offset));
1641 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1642 X86::GR64RegisterClass);
1643 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1645 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1646 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1647 Offset, false, false, 0);
1648 MemOps.push_back(Store);
1652 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1653 // Now store the XMM (fp + vector) parameter registers.
1654 SmallVector<SDValue, 11> SaveXMMOps;
1655 SaveXMMOps.push_back(Chain);
1657 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1658 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1659 SaveXMMOps.push_back(ALVal);
1661 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1662 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1664 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1665 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1666 X86::VR128RegisterClass);
1667 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1668 SaveXMMOps.push_back(Val);
1670 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1672 &SaveXMMOps[0], SaveXMMOps.size()));
1675 if (!MemOps.empty())
1676 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1677 &MemOps[0], MemOps.size());
1681 // Some CCs need callee pop.
1682 if (IsCalleePop(isVarArg, CallConv)) {
1683 BytesToPopOnReturn = StackSize; // Callee pops everything.
1685 BytesToPopOnReturn = 0; // Callee pops nothing.
1686 // If this is an sret function, the return should pop the hidden pointer.
1687 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1688 BytesToPopOnReturn = 4;
1692 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1693 if (CallConv == CallingConv::X86_FastCall)
1694 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1697 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1703 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1704 SDValue StackPtr, SDValue Arg,
1705 DebugLoc dl, SelectionDAG &DAG,
1706 const CCValAssign &VA,
1707 ISD::ArgFlagsTy Flags) {
1708 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1709 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1710 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1711 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1712 if (Flags.isByVal()) {
1713 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1715 return DAG.getStore(Chain, dl, Arg, PtrOff,
1716 PseudoSourceValue::getStack(), LocMemOffset,
1720 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1721 /// optimization is performed and it is required.
1723 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1724 SDValue &OutRetAddr, SDValue Chain,
1725 bool IsTailCall, bool Is64Bit,
1726 int FPDiff, DebugLoc dl) {
1727 // Adjust the Return address stack slot.
1728 EVT VT = getPointerTy();
1729 OutRetAddr = getReturnAddressFrameIndex(DAG);
1731 // Load the "old" Return address.
1732 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
1733 return SDValue(OutRetAddr.getNode(), 1);
1736 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1737 /// optimization is performed and it is required (FPDiff!=0).
1739 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1740 SDValue Chain, SDValue RetAddrFrIdx,
1741 bool Is64Bit, int FPDiff, DebugLoc dl) {
1742 // Store the return address to the appropriate stack slot.
1743 if (!FPDiff) return Chain;
1744 // Calculate the new stack slot for the return address.
1745 int SlotSize = Is64Bit ? 8 : 4;
1746 int NewReturnAddrFI =
1747 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, true,false);
1748 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1749 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1750 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1751 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
1757 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1758 CallingConv::ID CallConv, bool isVarArg,
1760 const SmallVectorImpl<ISD::OutputArg> &Outs,
1761 const SmallVectorImpl<ISD::InputArg> &Ins,
1762 DebugLoc dl, SelectionDAG &DAG,
1763 SmallVectorImpl<SDValue> &InVals) {
1764 MachineFunction &MF = DAG.getMachineFunction();
1765 bool Is64Bit = Subtarget->is64Bit();
1766 bool IsStructRet = CallIsStructReturn(Outs);
1767 bool IsSibcall = false;
1770 // Check if it's really possible to do a tail call.
1771 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
1774 // Sibcalls are automatically detected tailcalls which do not require
1776 if (!GuaranteedTailCallOpt && isTailCall)
1783 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1784 "Var args not supported with calling convention fastcc");
1786 // Analyze operands of the call, assigning locations to each operand.
1787 SmallVector<CCValAssign, 16> ArgLocs;
1788 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1789 ArgLocs, *DAG.getContext());
1790 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1792 // Get a count of how many bytes are to be pushed on the stack.
1793 unsigned NumBytes = CCInfo.getNextStackOffset();
1795 // This is a sibcall. The memory operands are available in caller's
1796 // own caller's stack.
1798 else if (GuaranteedTailCallOpt && CallConv == CallingConv::Fast)
1799 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1802 if (isTailCall && !IsSibcall) {
1803 // Lower arguments at fp - stackoffset + fpdiff.
1804 unsigned NumBytesCallerPushed =
1805 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1806 FPDiff = NumBytesCallerPushed - NumBytes;
1808 // Set the delta of movement of the returnaddr stackslot.
1809 // But only set if delta is greater than previous delta.
1810 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1811 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1815 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1817 SDValue RetAddrFrIdx;
1818 // Load return adress for tail calls.
1819 if (isTailCall && FPDiff)
1820 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1821 Is64Bit, FPDiff, dl);
1823 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1824 SmallVector<SDValue, 8> MemOpChains;
1827 // Walk the register/memloc assignments, inserting copies/loads. In the case
1828 // of tail call optimization arguments are handle later.
1829 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1830 CCValAssign &VA = ArgLocs[i];
1831 EVT RegVT = VA.getLocVT();
1832 SDValue Arg = Outs[i].Val;
1833 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1834 bool isByVal = Flags.isByVal();
1836 // Promote the value if needed.
1837 switch (VA.getLocInfo()) {
1838 default: llvm_unreachable("Unknown loc info!");
1839 case CCValAssign::Full: break;
1840 case CCValAssign::SExt:
1841 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1843 case CCValAssign::ZExt:
1844 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1846 case CCValAssign::AExt:
1847 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1848 // Special case: passing MMX values in XMM registers.
1849 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1850 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1851 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1853 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1855 case CCValAssign::BCvt:
1856 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1858 case CCValAssign::Indirect: {
1859 // Store the argument.
1860 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1861 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1862 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1863 PseudoSourceValue::getFixedStack(FI), 0,
1870 if (VA.isRegLoc()) {
1871 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1872 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1873 assert(VA.isMemLoc());
1874 if (StackPtr.getNode() == 0)
1875 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1876 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1877 dl, DAG, VA, Flags));
1881 if (!MemOpChains.empty())
1882 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1883 &MemOpChains[0], MemOpChains.size());
1885 // Build a sequence of copy-to-reg nodes chained together with token chain
1886 // and flag operands which copy the outgoing args into registers.
1888 // Tail call byval lowering might overwrite argument registers so in case of
1889 // tail call optimization the copies to registers are lowered later.
1891 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1892 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1893 RegsToPass[i].second, InFlag);
1894 InFlag = Chain.getValue(1);
1897 if (Subtarget->isPICStyleGOT()) {
1898 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1901 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1902 DAG.getNode(X86ISD::GlobalBaseReg,
1903 DebugLoc::getUnknownLoc(),
1906 InFlag = Chain.getValue(1);
1908 // If we are tail calling and generating PIC/GOT style code load the
1909 // address of the callee into ECX. The value in ecx is used as target of
1910 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1911 // for tail calls on PIC/GOT architectures. Normally we would just put the
1912 // address of GOT into ebx and then call target@PLT. But for tail calls
1913 // ebx would be restored (since ebx is callee saved) before jumping to the
1916 // Note: The actual moving to ECX is done further down.
1917 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1918 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1919 !G->getGlobal()->hasProtectedVisibility())
1920 Callee = LowerGlobalAddress(Callee, DAG);
1921 else if (isa<ExternalSymbolSDNode>(Callee))
1922 Callee = LowerExternalSymbol(Callee, DAG);
1926 if (Is64Bit && isVarArg) {
1927 // From AMD64 ABI document:
1928 // For calls that may call functions that use varargs or stdargs
1929 // (prototype-less calls or calls to functions containing ellipsis (...) in
1930 // the declaration) %al is used as hidden argument to specify the number
1931 // of SSE registers used. The contents of %al do not need to match exactly
1932 // the number of registers, but must be an ubound on the number of SSE
1933 // registers used and is in the range 0 - 8 inclusive.
1935 // FIXME: Verify this on Win64
1936 // Count the number of XMM registers allocated.
1937 static const unsigned XMMArgRegs[] = {
1938 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1939 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1941 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1942 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1943 && "SSE registers cannot be used when SSE is disabled");
1945 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1946 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1947 InFlag = Chain.getValue(1);
1951 // For tail calls lower the arguments to the 'real' stack slot.
1953 // Force all the incoming stack arguments to be loaded from the stack
1954 // before any new outgoing arguments are stored to the stack, because the
1955 // outgoing stack slots may alias the incoming argument stack slots, and
1956 // the alias isn't otherwise explicit. This is slightly more conservative
1957 // than necessary, because it means that each store effectively depends
1958 // on every argument instead of just those arguments it would clobber.
1959 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1961 SmallVector<SDValue, 8> MemOpChains2;
1964 // Do not flag preceeding copytoreg stuff together with the following stuff.
1966 if (GuaranteedTailCallOpt) {
1967 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1968 CCValAssign &VA = ArgLocs[i];
1971 assert(VA.isMemLoc());
1972 SDValue Arg = Outs[i].Val;
1973 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1974 // Create frame index.
1975 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1976 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1977 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
1978 FIN = DAG.getFrameIndex(FI, getPointerTy());
1980 if (Flags.isByVal()) {
1981 // Copy relative to framepointer.
1982 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1983 if (StackPtr.getNode() == 0)
1984 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1986 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1988 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
1992 // Store relative to framepointer.
1993 MemOpChains2.push_back(
1994 DAG.getStore(ArgChain, dl, Arg, FIN,
1995 PseudoSourceValue::getFixedStack(FI), 0,
2001 if (!MemOpChains2.empty())
2002 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2003 &MemOpChains2[0], MemOpChains2.size());
2005 // Copy arguments to their registers.
2006 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2007 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2008 RegsToPass[i].second, InFlag);
2009 InFlag = Chain.getValue(1);
2013 // Store the return address to the appropriate stack slot.
2014 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2018 bool WasGlobalOrExternal = false;
2019 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2020 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2021 // In the 64-bit large code model, we have to make all calls
2022 // through a register, since the call instruction's 32-bit
2023 // pc-relative offset may not be large enough to hold the whole
2025 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2026 WasGlobalOrExternal = true;
2027 // If the callee is a GlobalAddress node (quite common, every direct call
2028 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2031 // We should use extra load for direct calls to dllimported functions in
2033 GlobalValue *GV = G->getGlobal();
2034 if (!GV->hasDLLImportLinkage()) {
2035 unsigned char OpFlags = 0;
2037 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2038 // external symbols most go through the PLT in PIC mode. If the symbol
2039 // has hidden or protected visibility, or if it is static or local, then
2040 // we don't need to use the PLT - we can directly call it.
2041 if (Subtarget->isTargetELF() &&
2042 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2043 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2044 OpFlags = X86II::MO_PLT;
2045 } else if (Subtarget->isPICStyleStubAny() &&
2046 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2047 Subtarget->getDarwinVers() < 9) {
2048 // PC-relative references to external symbols should go through $stub,
2049 // unless we're building with the leopard linker or later, which
2050 // automatically synthesizes these stubs.
2051 OpFlags = X86II::MO_DARWIN_STUB;
2054 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
2055 G->getOffset(), OpFlags);
2057 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2058 WasGlobalOrExternal = true;
2059 unsigned char OpFlags = 0;
2061 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2062 // symbols should go through the PLT.
2063 if (Subtarget->isTargetELF() &&
2064 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2065 OpFlags = X86II::MO_PLT;
2066 } else if (Subtarget->isPICStyleStubAny() &&
2067 Subtarget->getDarwinVers() < 9) {
2068 // PC-relative references to external symbols should go through $stub,
2069 // unless we're building with the leopard linker or later, which
2070 // automatically synthesizes these stubs.
2071 OpFlags = X86II::MO_DARWIN_STUB;
2074 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2078 if (isTailCall && !WasGlobalOrExternal) {
2079 // Force the address into a (call preserved) caller-saved register since
2080 // tailcall must happen after callee-saved registers are poped.
2081 // FIXME: Give it a special register class that contains caller-saved
2082 // register instead?
2083 unsigned TCReg = Is64Bit ? X86::R11 : X86::EAX;
2084 Chain = DAG.getCopyToReg(Chain, dl,
2085 DAG.getRegister(TCReg, getPointerTy()),
2087 Callee = DAG.getRegister(TCReg, getPointerTy());
2090 // Returns a chain & a flag for retval copy to use.
2091 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2092 SmallVector<SDValue, 8> Ops;
2094 if (!IsSibcall && isTailCall) {
2095 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2096 DAG.getIntPtrConstant(0, true), InFlag);
2097 InFlag = Chain.getValue(1);
2100 Ops.push_back(Chain);
2101 Ops.push_back(Callee);
2104 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2106 // Add argument registers to the end of the list so that they are known live
2108 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2109 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2110 RegsToPass[i].second.getValueType()));
2112 // Add an implicit use GOT pointer in EBX.
2113 if (!isTailCall && Subtarget->isPICStyleGOT())
2114 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2116 // Add an implicit use of AL for x86 vararg functions.
2117 if (Is64Bit && isVarArg)
2118 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2120 if (InFlag.getNode())
2121 Ops.push_back(InFlag);
2124 // If this is the first return lowered for this function, add the regs
2125 // to the liveout set for the function.
2126 if (MF.getRegInfo().liveout_empty()) {
2127 SmallVector<CCValAssign, 16> RVLocs;
2128 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2130 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2131 for (unsigned i = 0; i != RVLocs.size(); ++i)
2132 if (RVLocs[i].isRegLoc())
2133 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2136 assert(((Callee.getOpcode() == ISD::Register &&
2137 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2138 cast<RegisterSDNode>(Callee)->getReg() == X86::R11)) ||
2139 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2140 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2141 "Expecting a global address, external symbol, or scratch register");
2143 return DAG.getNode(X86ISD::TC_RETURN, dl,
2144 NodeTys, &Ops[0], Ops.size());
2147 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2148 InFlag = Chain.getValue(1);
2150 // Create the CALLSEQ_END node.
2151 unsigned NumBytesForCalleeToPush;
2152 if (IsCalleePop(isVarArg, CallConv))
2153 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2154 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2155 // If this is a call to a struct-return function, the callee
2156 // pops the hidden struct pointer, so we have to push it back.
2157 // This is common for Darwin/X86, Linux & Mingw32 targets.
2158 NumBytesForCalleeToPush = 4;
2160 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2162 // Returns a flag for retval copy to use.
2164 Chain = DAG.getCALLSEQ_END(Chain,
2165 DAG.getIntPtrConstant(NumBytes, true),
2166 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2169 InFlag = Chain.getValue(1);
2172 // Handle result values, copying them out of physregs into vregs that we
2174 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2175 Ins, dl, DAG, InVals);
2179 //===----------------------------------------------------------------------===//
2180 // Fast Calling Convention (tail call) implementation
2181 //===----------------------------------------------------------------------===//
2183 // Like std call, callee cleans arguments, convention except that ECX is
2184 // reserved for storing the tail called function address. Only 2 registers are
2185 // free for argument passing (inreg). Tail call optimization is performed
2187 // * tailcallopt is enabled
2188 // * caller/callee are fastcc
2189 // On X86_64 architecture with GOT-style position independent code only local
2190 // (within module) calls are supported at the moment.
2191 // To keep the stack aligned according to platform abi the function
2192 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2193 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2194 // If a tail called function callee has more arguments than the caller the
2195 // caller needs to make sure that there is room to move the RETADDR to. This is
2196 // achieved by reserving an area the size of the argument delta right after the
2197 // original REtADDR, but before the saved framepointer or the spilled registers
2198 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2210 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2211 /// for a 16 byte align requirement.
2212 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2213 SelectionDAG& DAG) {
2214 MachineFunction &MF = DAG.getMachineFunction();
2215 const TargetMachine &TM = MF.getTarget();
2216 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2217 unsigned StackAlignment = TFI.getStackAlignment();
2218 uint64_t AlignMask = StackAlignment - 1;
2219 int64_t Offset = StackSize;
2220 uint64_t SlotSize = TD->getPointerSize();
2221 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2222 // Number smaller than 12 so just add the difference.
2223 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2225 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2226 Offset = ((~AlignMask) & Offset) + StackAlignment +
2227 (StackAlignment-SlotSize);
2232 /// MatchingStackOffset - Return true if the given stack call argument is
2233 /// already available in the same position (relatively) of the caller's
2234 /// incoming argument stack.
2236 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2237 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2238 const X86InstrInfo *TII) {
2240 if (Arg.getOpcode() == ISD::CopyFromReg) {
2241 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2242 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2244 MachineInstr *Def = MRI->getVRegDef(VR);
2247 if (!Flags.isByVal()) {
2248 if (!TII->isLoadFromStackSlot(Def, FI))
2251 unsigned Opcode = Def->getOpcode();
2252 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2253 Def->getOperand(1).isFI()) {
2254 FI = Def->getOperand(1).getIndex();
2255 if (MFI->getObjectSize(FI) != Flags.getByValSize())
2261 LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg);
2264 SDValue Ptr = Ld->getBasePtr();
2265 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2268 FI = FINode->getIndex();
2271 if (!MFI->isFixedObjectIndex(FI))
2273 return Offset == MFI->getObjectOffset(FI);
2276 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2277 /// for tail call optimization. Targets which want to do tail call
2278 /// optimization should implement this function.
2280 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2281 CallingConv::ID CalleeCC,
2283 const SmallVectorImpl<ISD::OutputArg> &Outs,
2284 const SmallVectorImpl<ISD::InputArg> &Ins,
2285 SelectionDAG& DAG) const {
2286 if (CalleeCC != CallingConv::Fast &&
2287 CalleeCC != CallingConv::C)
2290 // If -tailcallopt is specified, make fastcc functions tail-callable.
2291 const Function *CallerF = DAG.getMachineFunction().getFunction();
2292 if (GuaranteedTailCallOpt) {
2293 if (CalleeCC == CallingConv::Fast &&
2294 CallerF->getCallingConv() == CalleeCC)
2299 // Look for obvious safe cases to perform tail call optimization that does not
2300 // requite ABI changes. This is what gcc calls sibcall.
2302 // Do not tail call optimize vararg calls for now.
2306 // If the callee takes no arguments then go on to check the results of the
2308 if (!Outs.empty()) {
2309 // Check if stack adjustment is needed. For now, do not do this if any
2310 // argument is passed on the stack.
2311 SmallVector<CCValAssign, 16> ArgLocs;
2312 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2313 ArgLocs, *DAG.getContext());
2314 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2315 if (CCInfo.getNextStackOffset()) {
2316 MachineFunction &MF = DAG.getMachineFunction();
2317 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2319 if (Subtarget->isTargetWin64())
2320 // Win64 ABI has additional complications.
2323 // Check if the arguments are already laid out in the right way as
2324 // the caller's fixed stack objects.
2325 MachineFrameInfo *MFI = MF.getFrameInfo();
2326 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2327 const X86InstrInfo *TII =
2328 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2329 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2330 CCValAssign &VA = ArgLocs[i];
2331 EVT RegVT = VA.getLocVT();
2332 SDValue Arg = Outs[i].Val;
2333 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2334 if (VA.getLocInfo() == CCValAssign::Indirect)
2336 if (!VA.isRegLoc()) {
2337 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2349 X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo,
2351 DenseMap<const Value *, unsigned> &vm,
2352 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm,
2353 DenseMap<const AllocaInst *, int> &am
2355 , SmallSet<Instruction*, 8> &cil
2358 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2366 //===----------------------------------------------------------------------===//
2367 // Other Lowering Hooks
2368 //===----------------------------------------------------------------------===//
2371 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2372 MachineFunction &MF = DAG.getMachineFunction();
2373 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2374 int ReturnAddrIndex = FuncInfo->getRAIndex();
2376 if (ReturnAddrIndex == 0) {
2377 // Set up a frame object for the return address.
2378 uint64_t SlotSize = TD->getPointerSize();
2379 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2381 FuncInfo->setRAIndex(ReturnAddrIndex);
2384 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2388 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2389 bool hasSymbolicDisplacement) {
2390 // Offset should fit into 32 bit immediate field.
2391 if (!isInt32(Offset))
2394 // If we don't have a symbolic displacement - we don't have any extra
2396 if (!hasSymbolicDisplacement)
2399 // FIXME: Some tweaks might be needed for medium code model.
2400 if (M != CodeModel::Small && M != CodeModel::Kernel)
2403 // For small code model we assume that latest object is 16MB before end of 31
2404 // bits boundary. We may also accept pretty large negative constants knowing
2405 // that all objects are in the positive half of address space.
2406 if (M == CodeModel::Small && Offset < 16*1024*1024)
2409 // For kernel code model we know that all object resist in the negative half
2410 // of 32bits address space. We may not accept negative offsets, since they may
2411 // be just off and we may accept pretty large positive ones.
2412 if (M == CodeModel::Kernel && Offset > 0)
2418 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2419 /// specific condition code, returning the condition code and the LHS/RHS of the
2420 /// comparison to make.
2421 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2422 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2424 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2425 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2426 // X > -1 -> X == 0, jump !sign.
2427 RHS = DAG.getConstant(0, RHS.getValueType());
2428 return X86::COND_NS;
2429 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2430 // X < 0 -> X == 0, jump on sign.
2432 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2434 RHS = DAG.getConstant(0, RHS.getValueType());
2435 return X86::COND_LE;
2439 switch (SetCCOpcode) {
2440 default: llvm_unreachable("Invalid integer condition!");
2441 case ISD::SETEQ: return X86::COND_E;
2442 case ISD::SETGT: return X86::COND_G;
2443 case ISD::SETGE: return X86::COND_GE;
2444 case ISD::SETLT: return X86::COND_L;
2445 case ISD::SETLE: return X86::COND_LE;
2446 case ISD::SETNE: return X86::COND_NE;
2447 case ISD::SETULT: return X86::COND_B;
2448 case ISD::SETUGT: return X86::COND_A;
2449 case ISD::SETULE: return X86::COND_BE;
2450 case ISD::SETUGE: return X86::COND_AE;
2454 // First determine if it is required or is profitable to flip the operands.
2456 // If LHS is a foldable load, but RHS is not, flip the condition.
2457 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2458 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2459 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2460 std::swap(LHS, RHS);
2463 switch (SetCCOpcode) {
2469 std::swap(LHS, RHS);
2473 // On a floating point condition, the flags are set as follows:
2475 // 0 | 0 | 0 | X > Y
2476 // 0 | 0 | 1 | X < Y
2477 // 1 | 0 | 0 | X == Y
2478 // 1 | 1 | 1 | unordered
2479 switch (SetCCOpcode) {
2480 default: llvm_unreachable("Condcode should be pre-legalized away");
2482 case ISD::SETEQ: return X86::COND_E;
2483 case ISD::SETOLT: // flipped
2485 case ISD::SETGT: return X86::COND_A;
2486 case ISD::SETOLE: // flipped
2488 case ISD::SETGE: return X86::COND_AE;
2489 case ISD::SETUGT: // flipped
2491 case ISD::SETLT: return X86::COND_B;
2492 case ISD::SETUGE: // flipped
2494 case ISD::SETLE: return X86::COND_BE;
2496 case ISD::SETNE: return X86::COND_NE;
2497 case ISD::SETUO: return X86::COND_P;
2498 case ISD::SETO: return X86::COND_NP;
2500 case ISD::SETUNE: return X86::COND_INVALID;
2504 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2505 /// code. Current x86 isa includes the following FP cmov instructions:
2506 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2507 static bool hasFPCMov(unsigned X86CC) {
2523 /// isFPImmLegal - Returns true if the target can instruction select the
2524 /// specified FP immediate natively. If false, the legalizer will
2525 /// materialize the FP immediate as a load from a constant pool.
2526 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2527 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2528 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2534 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2535 /// the specified range (L, H].
2536 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2537 return (Val < 0) || (Val >= Low && Val < Hi);
2540 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2541 /// specified value.
2542 static bool isUndefOrEqual(int Val, int CmpVal) {
2543 if (Val < 0 || Val == CmpVal)
2548 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2549 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2550 /// the second operand.
2551 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2552 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2553 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2554 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2555 return (Mask[0] < 2 && Mask[1] < 2);
2559 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2560 SmallVector<int, 8> M;
2562 return ::isPSHUFDMask(M, N->getValueType(0));
2565 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2566 /// is suitable for input to PSHUFHW.
2567 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2568 if (VT != MVT::v8i16)
2571 // Lower quadword copied in order or undef.
2572 for (int i = 0; i != 4; ++i)
2573 if (Mask[i] >= 0 && Mask[i] != i)
2576 // Upper quadword shuffled.
2577 for (int i = 4; i != 8; ++i)
2578 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2584 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2585 SmallVector<int, 8> M;
2587 return ::isPSHUFHWMask(M, N->getValueType(0));
2590 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2591 /// is suitable for input to PSHUFLW.
2592 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2593 if (VT != MVT::v8i16)
2596 // Upper quadword copied in order.
2597 for (int i = 4; i != 8; ++i)
2598 if (Mask[i] >= 0 && Mask[i] != i)
2601 // Lower quadword shuffled.
2602 for (int i = 0; i != 4; ++i)
2609 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2610 SmallVector<int, 8> M;
2612 return ::isPSHUFLWMask(M, N->getValueType(0));
2615 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2616 /// is suitable for input to PALIGNR.
2617 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2619 int i, e = VT.getVectorNumElements();
2621 // Do not handle v2i64 / v2f64 shuffles with palignr.
2622 if (e < 4 || !hasSSSE3)
2625 for (i = 0; i != e; ++i)
2629 // All undef, not a palignr.
2633 // Determine if it's ok to perform a palignr with only the LHS, since we
2634 // don't have access to the actual shuffle elements to see if RHS is undef.
2635 bool Unary = Mask[i] < (int)e;
2636 bool NeedsUnary = false;
2638 int s = Mask[i] - i;
2640 // Check the rest of the elements to see if they are consecutive.
2641 for (++i; i != e; ++i) {
2646 Unary = Unary && (m < (int)e);
2647 NeedsUnary = NeedsUnary || (m < s);
2649 if (NeedsUnary && !Unary)
2651 if (Unary && m != ((s+i) & (e-1)))
2653 if (!Unary && m != (s+i))
2659 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2660 SmallVector<int, 8> M;
2662 return ::isPALIGNRMask(M, N->getValueType(0), true);
2665 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2666 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2667 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2668 int NumElems = VT.getVectorNumElements();
2669 if (NumElems != 2 && NumElems != 4)
2672 int Half = NumElems / 2;
2673 for (int i = 0; i < Half; ++i)
2674 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2676 for (int i = Half; i < NumElems; ++i)
2677 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2683 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2684 SmallVector<int, 8> M;
2686 return ::isSHUFPMask(M, N->getValueType(0));
2689 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2690 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2691 /// half elements to come from vector 1 (which would equal the dest.) and
2692 /// the upper half to come from vector 2.
2693 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2694 int NumElems = VT.getVectorNumElements();
2696 if (NumElems != 2 && NumElems != 4)
2699 int Half = NumElems / 2;
2700 for (int i = 0; i < Half; ++i)
2701 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2703 for (int i = Half; i < NumElems; ++i)
2704 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2709 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2710 SmallVector<int, 8> M;
2712 return isCommutedSHUFPMask(M, N->getValueType(0));
2715 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2716 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2717 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2718 if (N->getValueType(0).getVectorNumElements() != 4)
2721 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2722 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2723 isUndefOrEqual(N->getMaskElt(1), 7) &&
2724 isUndefOrEqual(N->getMaskElt(2), 2) &&
2725 isUndefOrEqual(N->getMaskElt(3), 3);
2728 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2729 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2731 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2732 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2737 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2738 isUndefOrEqual(N->getMaskElt(1), 3) &&
2739 isUndefOrEqual(N->getMaskElt(2), 2) &&
2740 isUndefOrEqual(N->getMaskElt(3), 3);
2743 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2744 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2745 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2746 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2748 if (NumElems != 2 && NumElems != 4)
2751 for (unsigned i = 0; i < NumElems/2; ++i)
2752 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2755 for (unsigned i = NumElems/2; i < NumElems; ++i)
2756 if (!isUndefOrEqual(N->getMaskElt(i), i))
2762 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2763 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2764 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2765 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2767 if (NumElems != 2 && NumElems != 4)
2770 for (unsigned i = 0; i < NumElems/2; ++i)
2771 if (!isUndefOrEqual(N->getMaskElt(i), i))
2774 for (unsigned i = 0; i < NumElems/2; ++i)
2775 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2781 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2782 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2783 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2784 bool V2IsSplat = false) {
2785 int NumElts = VT.getVectorNumElements();
2786 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2789 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2791 int BitI1 = Mask[i+1];
2792 if (!isUndefOrEqual(BitI, j))
2795 if (!isUndefOrEqual(BitI1, NumElts))
2798 if (!isUndefOrEqual(BitI1, j + NumElts))
2805 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2806 SmallVector<int, 8> M;
2808 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2811 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2812 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2813 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2814 bool V2IsSplat = false) {
2815 int NumElts = VT.getVectorNumElements();
2816 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2819 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2821 int BitI1 = Mask[i+1];
2822 if (!isUndefOrEqual(BitI, j + NumElts/2))
2825 if (isUndefOrEqual(BitI1, NumElts))
2828 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2835 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2836 SmallVector<int, 8> M;
2838 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2841 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2842 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2844 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2845 int NumElems = VT.getVectorNumElements();
2846 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2849 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2851 int BitI1 = Mask[i+1];
2852 if (!isUndefOrEqual(BitI, j))
2854 if (!isUndefOrEqual(BitI1, j))
2860 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2861 SmallVector<int, 8> M;
2863 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2866 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2867 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2869 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2870 int NumElems = VT.getVectorNumElements();
2871 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2874 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2876 int BitI1 = Mask[i+1];
2877 if (!isUndefOrEqual(BitI, j))
2879 if (!isUndefOrEqual(BitI1, j))
2885 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2886 SmallVector<int, 8> M;
2888 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2891 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2892 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2893 /// MOVSD, and MOVD, i.e. setting the lowest element.
2894 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2895 if (VT.getVectorElementType().getSizeInBits() < 32)
2898 int NumElts = VT.getVectorNumElements();
2900 if (!isUndefOrEqual(Mask[0], NumElts))
2903 for (int i = 1; i < NumElts; ++i)
2904 if (!isUndefOrEqual(Mask[i], i))
2910 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2911 SmallVector<int, 8> M;
2913 return ::isMOVLMask(M, N->getValueType(0));
2916 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2917 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2918 /// element of vector 2 and the other elements to come from vector 1 in order.
2919 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2920 bool V2IsSplat = false, bool V2IsUndef = false) {
2921 int NumOps = VT.getVectorNumElements();
2922 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2925 if (!isUndefOrEqual(Mask[0], 0))
2928 for (int i = 1; i < NumOps; ++i)
2929 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2930 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2931 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2937 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2938 bool V2IsUndef = false) {
2939 SmallVector<int, 8> M;
2941 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2944 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2945 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2946 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2947 if (N->getValueType(0).getVectorNumElements() != 4)
2950 // Expect 1, 1, 3, 3
2951 for (unsigned i = 0; i < 2; ++i) {
2952 int Elt = N->getMaskElt(i);
2953 if (Elt >= 0 && Elt != 1)
2958 for (unsigned i = 2; i < 4; ++i) {
2959 int Elt = N->getMaskElt(i);
2960 if (Elt >= 0 && Elt != 3)
2965 // Don't use movshdup if it can be done with a shufps.
2966 // FIXME: verify that matching u, u, 3, 3 is what we want.
2970 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2971 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2972 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2973 if (N->getValueType(0).getVectorNumElements() != 4)
2976 // Expect 0, 0, 2, 2
2977 for (unsigned i = 0; i < 2; ++i)
2978 if (N->getMaskElt(i) > 0)
2982 for (unsigned i = 2; i < 4; ++i) {
2983 int Elt = N->getMaskElt(i);
2984 if (Elt >= 0 && Elt != 2)
2989 // Don't use movsldup if it can be done with a shufps.
2993 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2994 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2995 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2996 int e = N->getValueType(0).getVectorNumElements() / 2;
2998 for (int i = 0; i < e; ++i)
2999 if (!isUndefOrEqual(N->getMaskElt(i), i))
3001 for (int i = 0; i < e; ++i)
3002 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3007 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3008 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3009 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3010 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3011 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3013 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3015 for (int i = 0; i < NumOperands; ++i) {
3016 int Val = SVOp->getMaskElt(NumOperands-i-1);
3017 if (Val < 0) Val = 0;
3018 if (Val >= NumOperands) Val -= NumOperands;
3020 if (i != NumOperands - 1)
3026 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3027 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3028 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3029 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3031 // 8 nodes, but we only care about the last 4.
3032 for (unsigned i = 7; i >= 4; --i) {
3033 int Val = SVOp->getMaskElt(i);
3042 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3043 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3044 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3045 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3047 // 8 nodes, but we only care about the first 4.
3048 for (int i = 3; i >= 0; --i) {
3049 int Val = SVOp->getMaskElt(i);
3058 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3059 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3060 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3061 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3062 EVT VVT = N->getValueType(0);
3063 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3067 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3068 Val = SVOp->getMaskElt(i);
3072 return (Val - i) * EltSize;
3075 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3077 bool X86::isZeroNode(SDValue Elt) {
3078 return ((isa<ConstantSDNode>(Elt) &&
3079 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
3080 (isa<ConstantFPSDNode>(Elt) &&
3081 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3084 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3085 /// their permute mask.
3086 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3087 SelectionDAG &DAG) {
3088 EVT VT = SVOp->getValueType(0);
3089 unsigned NumElems = VT.getVectorNumElements();
3090 SmallVector<int, 8> MaskVec;
3092 for (unsigned i = 0; i != NumElems; ++i) {
3093 int idx = SVOp->getMaskElt(i);
3095 MaskVec.push_back(idx);
3096 else if (idx < (int)NumElems)
3097 MaskVec.push_back(idx + NumElems);
3099 MaskVec.push_back(idx - NumElems);
3101 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3102 SVOp->getOperand(0), &MaskVec[0]);
3105 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3106 /// the two vector operands have swapped position.
3107 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3108 unsigned NumElems = VT.getVectorNumElements();
3109 for (unsigned i = 0; i != NumElems; ++i) {
3113 else if (idx < (int)NumElems)
3114 Mask[i] = idx + NumElems;
3116 Mask[i] = idx - NumElems;
3120 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3121 /// match movhlps. The lower half elements should come from upper half of
3122 /// V1 (and in order), and the upper half elements should come from the upper
3123 /// half of V2 (and in order).
3124 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3125 if (Op->getValueType(0).getVectorNumElements() != 4)
3127 for (unsigned i = 0, e = 2; i != e; ++i)
3128 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3130 for (unsigned i = 2; i != 4; ++i)
3131 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3136 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3137 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3139 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3140 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3142 N = N->getOperand(0).getNode();
3143 if (!ISD::isNON_EXTLoad(N))
3146 *LD = cast<LoadSDNode>(N);
3150 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3151 /// match movlp{s|d}. The lower half elements should come from lower half of
3152 /// V1 (and in order), and the upper half elements should come from the upper
3153 /// half of V2 (and in order). And since V1 will become the source of the
3154 /// MOVLP, it must be either a vector load or a scalar load to vector.
3155 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3156 ShuffleVectorSDNode *Op) {
3157 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3159 // Is V2 is a vector load, don't do this transformation. We will try to use
3160 // load folding shufps op.
3161 if (ISD::isNON_EXTLoad(V2))
3164 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3166 if (NumElems != 2 && NumElems != 4)
3168 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3169 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3171 for (unsigned i = NumElems/2; i != NumElems; ++i)
3172 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3177 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3179 static bool isSplatVector(SDNode *N) {
3180 if (N->getOpcode() != ISD::BUILD_VECTOR)
3183 SDValue SplatValue = N->getOperand(0);
3184 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3185 if (N->getOperand(i) != SplatValue)
3190 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3191 /// to an zero vector.
3192 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3193 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3194 SDValue V1 = N->getOperand(0);
3195 SDValue V2 = N->getOperand(1);
3196 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3197 for (unsigned i = 0; i != NumElems; ++i) {
3198 int Idx = N->getMaskElt(i);
3199 if (Idx >= (int)NumElems) {
3200 unsigned Opc = V2.getOpcode();
3201 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3203 if (Opc != ISD::BUILD_VECTOR ||
3204 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3206 } else if (Idx >= 0) {
3207 unsigned Opc = V1.getOpcode();
3208 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3210 if (Opc != ISD::BUILD_VECTOR ||
3211 !X86::isZeroNode(V1.getOperand(Idx)))
3218 /// getZeroVector - Returns a vector of specified type with all zero elements.
3220 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3222 assert(VT.isVector() && "Expected a vector type");
3224 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3225 // type. This ensures they get CSE'd.
3227 if (VT.getSizeInBits() == 64) { // MMX
3228 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3229 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3230 } else if (HasSSE2) { // SSE2
3231 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3232 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3234 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3235 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3237 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3240 /// getOnesVector - Returns a vector of specified type with all bits set.
3242 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3243 assert(VT.isVector() && "Expected a vector type");
3245 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3246 // type. This ensures they get CSE'd.
3247 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3249 if (VT.getSizeInBits() == 64) // MMX
3250 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3252 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3253 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3257 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3258 /// that point to V2 points to its first element.
3259 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3260 EVT VT = SVOp->getValueType(0);
3261 unsigned NumElems = VT.getVectorNumElements();
3263 bool Changed = false;
3264 SmallVector<int, 8> MaskVec;
3265 SVOp->getMask(MaskVec);
3267 for (unsigned i = 0; i != NumElems; ++i) {
3268 if (MaskVec[i] > (int)NumElems) {
3269 MaskVec[i] = NumElems;
3274 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3275 SVOp->getOperand(1), &MaskVec[0]);
3276 return SDValue(SVOp, 0);
3279 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3280 /// operation of specified width.
3281 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3283 unsigned NumElems = VT.getVectorNumElements();
3284 SmallVector<int, 8> Mask;
3285 Mask.push_back(NumElems);
3286 for (unsigned i = 1; i != NumElems; ++i)
3288 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3291 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3292 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3294 unsigned NumElems = VT.getVectorNumElements();
3295 SmallVector<int, 8> Mask;
3296 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3298 Mask.push_back(i + NumElems);
3300 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3303 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3304 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3306 unsigned NumElems = VT.getVectorNumElements();
3307 unsigned Half = NumElems/2;
3308 SmallVector<int, 8> Mask;
3309 for (unsigned i = 0; i != Half; ++i) {
3310 Mask.push_back(i + Half);
3311 Mask.push_back(i + NumElems + Half);
3313 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3316 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3317 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3319 if (SV->getValueType(0).getVectorNumElements() <= 4)
3320 return SDValue(SV, 0);
3322 EVT PVT = MVT::v4f32;
3323 EVT VT = SV->getValueType(0);
3324 DebugLoc dl = SV->getDebugLoc();
3325 SDValue V1 = SV->getOperand(0);
3326 int NumElems = VT.getVectorNumElements();
3327 int EltNo = SV->getSplatIndex();
3329 // unpack elements to the correct location
3330 while (NumElems > 4) {
3331 if (EltNo < NumElems/2) {
3332 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3334 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3335 EltNo -= NumElems/2;
3340 // Perform the splat.
3341 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3342 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3343 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3344 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3347 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3348 /// vector of zero or undef vector. This produces a shuffle where the low
3349 /// element of V2 is swizzled into the zero/undef vector, landing at element
3350 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3351 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3352 bool isZero, bool HasSSE2,
3353 SelectionDAG &DAG) {
3354 EVT VT = V2.getValueType();
3356 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3357 unsigned NumElems = VT.getVectorNumElements();
3358 SmallVector<int, 16> MaskVec;
3359 for (unsigned i = 0; i != NumElems; ++i)
3360 // If this is the insertion idx, put the low elt of V2 here.
3361 MaskVec.push_back(i == Idx ? NumElems : i);
3362 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3365 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3366 /// a shuffle that is zero.
3368 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3369 bool Low, SelectionDAG &DAG) {
3370 unsigned NumZeros = 0;
3371 for (int i = 0; i < NumElems; ++i) {
3372 unsigned Index = Low ? i : NumElems-i-1;
3373 int Idx = SVOp->getMaskElt(Index);
3378 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3379 if (Elt.getNode() && X86::isZeroNode(Elt))
3387 /// isVectorShift - Returns true if the shuffle can be implemented as a
3388 /// logical left or right shift of a vector.
3389 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3390 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3391 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3392 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3395 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3398 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3402 bool SeenV1 = false;
3403 bool SeenV2 = false;
3404 for (int i = NumZeros; i < NumElems; ++i) {
3405 int Val = isLeft ? (i - NumZeros) : i;
3406 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3418 if (SeenV1 && SeenV2)
3421 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3427 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3429 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3430 unsigned NumNonZero, unsigned NumZero,
3431 SelectionDAG &DAG, TargetLowering &TLI) {
3435 DebugLoc dl = Op.getDebugLoc();
3438 for (unsigned i = 0; i < 16; ++i) {
3439 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3440 if (ThisIsNonZero && First) {
3442 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3444 V = DAG.getUNDEF(MVT::v8i16);
3449 SDValue ThisElt(0, 0), LastElt(0, 0);
3450 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3451 if (LastIsNonZero) {
3452 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3453 MVT::i16, Op.getOperand(i-1));
3455 if (ThisIsNonZero) {
3456 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3457 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3458 ThisElt, DAG.getConstant(8, MVT::i8));
3460 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3464 if (ThisElt.getNode())
3465 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3466 DAG.getIntPtrConstant(i/2));
3470 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3473 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3475 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3476 unsigned NumNonZero, unsigned NumZero,
3477 SelectionDAG &DAG, TargetLowering &TLI) {
3481 DebugLoc dl = Op.getDebugLoc();
3484 for (unsigned i = 0; i < 8; ++i) {
3485 bool isNonZero = (NonZeros & (1 << i)) != 0;
3489 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3491 V = DAG.getUNDEF(MVT::v8i16);
3494 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3495 MVT::v8i16, V, Op.getOperand(i),
3496 DAG.getIntPtrConstant(i));
3503 /// getVShift - Return a vector logical shift node.
3505 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3506 unsigned NumBits, SelectionDAG &DAG,
3507 const TargetLowering &TLI, DebugLoc dl) {
3508 bool isMMX = VT.getSizeInBits() == 64;
3509 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3510 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3511 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3512 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3513 DAG.getNode(Opc, dl, ShVT, SrcOp,
3514 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3518 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3519 SelectionDAG &DAG) {
3521 // Check if the scalar load can be widened into a vector load. And if
3522 // the address is "base + cst" see if the cst can be "absorbed" into
3523 // the shuffle mask.
3524 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3525 SDValue Ptr = LD->getBasePtr();
3526 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3528 EVT PVT = LD->getValueType(0);
3529 if (PVT != MVT::i32 && PVT != MVT::f32)
3534 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3535 FI = FINode->getIndex();
3537 } else if (Ptr.getOpcode() == ISD::ADD &&
3538 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3539 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3540 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3541 Offset = Ptr.getConstantOperandVal(1);
3542 Ptr = Ptr.getOperand(0);
3547 SDValue Chain = LD->getChain();
3548 // Make sure the stack object alignment is at least 16.
3549 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3550 if (DAG.InferPtrAlignment(Ptr) < 16) {
3551 if (MFI->isFixedObjectIndex(FI)) {
3552 // Can't change the alignment. FIXME: It's possible to compute
3553 // the exact stack offset and reference FI + adjust offset instead.
3554 // If someone *really* cares about this. That's the way to implement it.
3557 MFI->setObjectAlignment(FI, 16);
3561 // (Offset % 16) must be multiple of 4. Then address is then
3562 // Ptr + (Offset & ~15).
3565 if ((Offset % 16) & 3)
3567 int64_t StartOffset = Offset & ~15;
3569 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3570 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3572 int EltNo = (Offset - StartOffset) >> 2;
3573 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3574 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3575 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
3577 // Canonicalize it to a v4i32 shuffle.
3578 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3579 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3580 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3581 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3588 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3589 DebugLoc dl = Op.getDebugLoc();
3590 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3591 if (ISD::isBuildVectorAllZeros(Op.getNode())
3592 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3593 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3594 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3595 // eliminated on x86-32 hosts.
3596 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3599 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3600 return getOnesVector(Op.getValueType(), DAG, dl);
3601 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3604 EVT VT = Op.getValueType();
3605 EVT ExtVT = VT.getVectorElementType();
3606 unsigned EVTBits = ExtVT.getSizeInBits();
3608 unsigned NumElems = Op.getNumOperands();
3609 unsigned NumZero = 0;
3610 unsigned NumNonZero = 0;
3611 unsigned NonZeros = 0;
3612 bool IsAllConstants = true;
3613 SmallSet<SDValue, 8> Values;
3614 for (unsigned i = 0; i < NumElems; ++i) {
3615 SDValue Elt = Op.getOperand(i);
3616 if (Elt.getOpcode() == ISD::UNDEF)
3619 if (Elt.getOpcode() != ISD::Constant &&
3620 Elt.getOpcode() != ISD::ConstantFP)
3621 IsAllConstants = false;
3622 if (X86::isZeroNode(Elt))
3625 NonZeros |= (1 << i);
3630 if (NumNonZero == 0) {
3631 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3632 return DAG.getUNDEF(VT);
3635 // Special case for single non-zero, non-undef, element.
3636 if (NumNonZero == 1) {
3637 unsigned Idx = CountTrailingZeros_32(NonZeros);
3638 SDValue Item = Op.getOperand(Idx);
3640 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3641 // the value are obviously zero, truncate the value to i32 and do the
3642 // insertion that way. Only do this if the value is non-constant or if the
3643 // value is a constant being inserted into element 0. It is cheaper to do
3644 // a constant pool load than it is to do a movd + shuffle.
3645 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3646 (!IsAllConstants || Idx == 0)) {
3647 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3648 // Handle MMX and SSE both.
3649 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3650 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3652 // Truncate the value (which may itself be a constant) to i32, and
3653 // convert it to a vector with movd (S2V+shuffle to zero extend).
3654 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3655 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3656 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3657 Subtarget->hasSSE2(), DAG);
3659 // Now we have our 32-bit value zero extended in the low element of
3660 // a vector. If Idx != 0, swizzle it into place.
3662 SmallVector<int, 4> Mask;
3663 Mask.push_back(Idx);
3664 for (unsigned i = 1; i != VecElts; ++i)
3666 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3667 DAG.getUNDEF(Item.getValueType()),
3670 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3674 // If we have a constant or non-constant insertion into the low element of
3675 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3676 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3677 // depending on what the source datatype is.
3680 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3681 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3682 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3683 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3684 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3685 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3687 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3688 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3689 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3690 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3691 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3692 Subtarget->hasSSE2(), DAG);
3693 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3697 // Is it a vector logical left shift?
3698 if (NumElems == 2 && Idx == 1 &&
3699 X86::isZeroNode(Op.getOperand(0)) &&
3700 !X86::isZeroNode(Op.getOperand(1))) {
3701 unsigned NumBits = VT.getSizeInBits();
3702 return getVShift(true, VT,
3703 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3704 VT, Op.getOperand(1)),
3705 NumBits/2, DAG, *this, dl);
3708 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3711 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3712 // is a non-constant being inserted into an element other than the low one,
3713 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3714 // movd/movss) to move this into the low element, then shuffle it into
3716 if (EVTBits == 32) {
3717 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3719 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3720 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3721 Subtarget->hasSSE2(), DAG);
3722 SmallVector<int, 8> MaskVec;
3723 for (unsigned i = 0; i < NumElems; i++)
3724 MaskVec.push_back(i == Idx ? 0 : 1);
3725 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3729 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3730 if (Values.size() == 1) {
3731 if (EVTBits == 32) {
3732 // Instead of a shuffle like this:
3733 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3734 // Check if it's possible to issue this instead.
3735 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3736 unsigned Idx = CountTrailingZeros_32(NonZeros);
3737 SDValue Item = Op.getOperand(Idx);
3738 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3739 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3744 // A vector full of immediates; various special cases are already
3745 // handled, so this is best done with a single constant-pool load.
3749 // Let legalizer expand 2-wide build_vectors.
3750 if (EVTBits == 64) {
3751 if (NumNonZero == 1) {
3752 // One half is zero or undef.
3753 unsigned Idx = CountTrailingZeros_32(NonZeros);
3754 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3755 Op.getOperand(Idx));
3756 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3757 Subtarget->hasSSE2(), DAG);
3762 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3763 if (EVTBits == 8 && NumElems == 16) {
3764 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3766 if (V.getNode()) return V;
3769 if (EVTBits == 16 && NumElems == 8) {
3770 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3772 if (V.getNode()) return V;
3775 // If element VT is == 32 bits, turn it into a number of shuffles.
3776 SmallVector<SDValue, 8> V;
3778 if (NumElems == 4 && NumZero > 0) {
3779 for (unsigned i = 0; i < 4; ++i) {
3780 bool isZero = !(NonZeros & (1 << i));
3782 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3784 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3787 for (unsigned i = 0; i < 2; ++i) {
3788 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3791 V[i] = V[i*2]; // Must be a zero vector.
3794 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3797 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3800 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3805 SmallVector<int, 8> MaskVec;
3806 bool Reverse = (NonZeros & 0x3) == 2;
3807 for (unsigned i = 0; i < 2; ++i)
3808 MaskVec.push_back(Reverse ? 1-i : i);
3809 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3810 for (unsigned i = 0; i < 2; ++i)
3811 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3812 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3815 if (Values.size() > 2) {
3816 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3817 // values to be inserted is equal to the number of elements, in which case
3818 // use the unpack code below in the hopes of matching the consecutive elts
3819 // load merge pattern for shuffles.
3820 // FIXME: We could probably just check that here directly.
3821 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3822 getSubtarget()->hasSSE41()) {
3823 V[0] = DAG.getUNDEF(VT);
3824 for (unsigned i = 0; i < NumElems; ++i)
3825 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3826 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3827 Op.getOperand(i), DAG.getIntPtrConstant(i));
3830 // Expand into a number of unpckl*.
3832 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3833 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3834 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3835 for (unsigned i = 0; i < NumElems; ++i)
3836 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3838 while (NumElems != 0) {
3839 for (unsigned i = 0; i < NumElems; ++i)
3840 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3850 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3851 // We support concatenate two MMX registers and place them in a MMX
3852 // register. This is better than doing a stack convert.
3853 DebugLoc dl = Op.getDebugLoc();
3854 EVT ResVT = Op.getValueType();
3855 assert(Op.getNumOperands() == 2);
3856 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
3857 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
3859 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
3860 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3861 InVec = Op.getOperand(1);
3862 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3863 unsigned NumElts = ResVT.getVectorNumElements();
3864 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3865 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
3866 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
3868 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
3869 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3870 Mask[0] = 0; Mask[1] = 2;
3871 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
3873 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3876 // v8i16 shuffles - Prefer shuffles in the following order:
3877 // 1. [all] pshuflw, pshufhw, optional move
3878 // 2. [ssse3] 1 x pshufb
3879 // 3. [ssse3] 2 x pshufb + 1 x por
3880 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3882 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3883 SelectionDAG &DAG, X86TargetLowering &TLI) {
3884 SDValue V1 = SVOp->getOperand(0);
3885 SDValue V2 = SVOp->getOperand(1);
3886 DebugLoc dl = SVOp->getDebugLoc();
3887 SmallVector<int, 8> MaskVals;
3889 // Determine if more than 1 of the words in each of the low and high quadwords
3890 // of the result come from the same quadword of one of the two inputs. Undef
3891 // mask values count as coming from any quadword, for better codegen.
3892 SmallVector<unsigned, 4> LoQuad(4);
3893 SmallVector<unsigned, 4> HiQuad(4);
3894 BitVector InputQuads(4);
3895 for (unsigned i = 0; i < 8; ++i) {
3896 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3897 int EltIdx = SVOp->getMaskElt(i);
3898 MaskVals.push_back(EltIdx);
3907 InputQuads.set(EltIdx / 4);
3910 int BestLoQuad = -1;
3911 unsigned MaxQuad = 1;
3912 for (unsigned i = 0; i < 4; ++i) {
3913 if (LoQuad[i] > MaxQuad) {
3915 MaxQuad = LoQuad[i];
3919 int BestHiQuad = -1;
3921 for (unsigned i = 0; i < 4; ++i) {
3922 if (HiQuad[i] > MaxQuad) {
3924 MaxQuad = HiQuad[i];
3928 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3929 // of the two input vectors, shuffle them into one input vector so only a
3930 // single pshufb instruction is necessary. If There are more than 2 input
3931 // quads, disable the next transformation since it does not help SSSE3.
3932 bool V1Used = InputQuads[0] || InputQuads[1];
3933 bool V2Used = InputQuads[2] || InputQuads[3];
3934 if (TLI.getSubtarget()->hasSSSE3()) {
3935 if (InputQuads.count() == 2 && V1Used && V2Used) {
3936 BestLoQuad = InputQuads.find_first();
3937 BestHiQuad = InputQuads.find_next(BestLoQuad);
3939 if (InputQuads.count() > 2) {
3945 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3946 // the shuffle mask. If a quad is scored as -1, that means that it contains
3947 // words from all 4 input quadwords.
3949 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3950 SmallVector<int, 8> MaskV;
3951 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3952 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3953 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3954 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3955 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3956 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3958 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3959 // source words for the shuffle, to aid later transformations.
3960 bool AllWordsInNewV = true;
3961 bool InOrder[2] = { true, true };
3962 for (unsigned i = 0; i != 8; ++i) {
3963 int idx = MaskVals[i];
3965 InOrder[i/4] = false;
3966 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3968 AllWordsInNewV = false;
3972 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3973 if (AllWordsInNewV) {
3974 for (int i = 0; i != 8; ++i) {
3975 int idx = MaskVals[i];
3978 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3979 if ((idx != i) && idx < 4)
3981 if ((idx != i) && idx > 3)
3990 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3991 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3992 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3993 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3994 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3998 // If we have SSSE3, and all words of the result are from 1 input vector,
3999 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4000 // is present, fall back to case 4.
4001 if (TLI.getSubtarget()->hasSSSE3()) {
4002 SmallVector<SDValue,16> pshufbMask;
4004 // If we have elements from both input vectors, set the high bit of the
4005 // shuffle mask element to zero out elements that come from V2 in the V1
4006 // mask, and elements that come from V1 in the V2 mask, so that the two
4007 // results can be OR'd together.
4008 bool TwoInputs = V1Used && V2Used;
4009 for (unsigned i = 0; i != 8; ++i) {
4010 int EltIdx = MaskVals[i] * 2;
4011 if (TwoInputs && (EltIdx >= 16)) {
4012 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4013 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4016 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4017 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4019 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4020 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4021 DAG.getNode(ISD::BUILD_VECTOR, dl,
4022 MVT::v16i8, &pshufbMask[0], 16));
4024 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4026 // Calculate the shuffle mask for the second input, shuffle it, and
4027 // OR it with the first shuffled input.
4029 for (unsigned i = 0; i != 8; ++i) {
4030 int EltIdx = MaskVals[i] * 2;
4032 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4033 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4036 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4037 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4039 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4040 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4041 DAG.getNode(ISD::BUILD_VECTOR, dl,
4042 MVT::v16i8, &pshufbMask[0], 16));
4043 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4044 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4047 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4048 // and update MaskVals with new element order.
4049 BitVector InOrder(8);
4050 if (BestLoQuad >= 0) {
4051 SmallVector<int, 8> MaskV;
4052 for (int i = 0; i != 4; ++i) {
4053 int idx = MaskVals[i];
4055 MaskV.push_back(-1);
4057 } else if ((idx / 4) == BestLoQuad) {
4058 MaskV.push_back(idx & 3);
4061 MaskV.push_back(-1);
4064 for (unsigned i = 4; i != 8; ++i)
4066 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4070 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4071 // and update MaskVals with the new element order.
4072 if (BestHiQuad >= 0) {
4073 SmallVector<int, 8> MaskV;
4074 for (unsigned i = 0; i != 4; ++i)
4076 for (unsigned i = 4; i != 8; ++i) {
4077 int idx = MaskVals[i];
4079 MaskV.push_back(-1);
4081 } else if ((idx / 4) == BestHiQuad) {
4082 MaskV.push_back((idx & 3) + 4);
4085 MaskV.push_back(-1);
4088 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4092 // In case BestHi & BestLo were both -1, which means each quadword has a word
4093 // from each of the four input quadwords, calculate the InOrder bitvector now
4094 // before falling through to the insert/extract cleanup.
4095 if (BestLoQuad == -1 && BestHiQuad == -1) {
4097 for (int i = 0; i != 8; ++i)
4098 if (MaskVals[i] < 0 || MaskVals[i] == i)
4102 // The other elements are put in the right place using pextrw and pinsrw.
4103 for (unsigned i = 0; i != 8; ++i) {
4106 int EltIdx = MaskVals[i];
4109 SDValue ExtOp = (EltIdx < 8)
4110 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4111 DAG.getIntPtrConstant(EltIdx))
4112 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4113 DAG.getIntPtrConstant(EltIdx - 8));
4114 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4115 DAG.getIntPtrConstant(i));
4120 // v16i8 shuffles - Prefer shuffles in the following order:
4121 // 1. [ssse3] 1 x pshufb
4122 // 2. [ssse3] 2 x pshufb + 1 x por
4123 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4125 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4126 SelectionDAG &DAG, X86TargetLowering &TLI) {
4127 SDValue V1 = SVOp->getOperand(0);
4128 SDValue V2 = SVOp->getOperand(1);
4129 DebugLoc dl = SVOp->getDebugLoc();
4130 SmallVector<int, 16> MaskVals;
4131 SVOp->getMask(MaskVals);
4133 // If we have SSSE3, case 1 is generated when all result bytes come from
4134 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4135 // present, fall back to case 3.
4136 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4139 for (unsigned i = 0; i < 16; ++i) {
4140 int EltIdx = MaskVals[i];
4149 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4150 if (TLI.getSubtarget()->hasSSSE3()) {
4151 SmallVector<SDValue,16> pshufbMask;
4153 // If all result elements are from one input vector, then only translate
4154 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4156 // Otherwise, we have elements from both input vectors, and must zero out
4157 // elements that come from V2 in the first mask, and V1 in the second mask
4158 // so that we can OR them together.
4159 bool TwoInputs = !(V1Only || V2Only);
4160 for (unsigned i = 0; i != 16; ++i) {
4161 int EltIdx = MaskVals[i];
4162 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4163 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4166 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4168 // If all the elements are from V2, assign it to V1 and return after
4169 // building the first pshufb.
4172 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4173 DAG.getNode(ISD::BUILD_VECTOR, dl,
4174 MVT::v16i8, &pshufbMask[0], 16));
4178 // Calculate the shuffle mask for the second input, shuffle it, and
4179 // OR it with the first shuffled input.
4181 for (unsigned i = 0; i != 16; ++i) {
4182 int EltIdx = MaskVals[i];
4184 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4187 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4189 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4190 DAG.getNode(ISD::BUILD_VECTOR, dl,
4191 MVT::v16i8, &pshufbMask[0], 16));
4192 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4195 // No SSSE3 - Calculate in place words and then fix all out of place words
4196 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4197 // the 16 different words that comprise the two doublequadword input vectors.
4198 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4199 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4200 SDValue NewV = V2Only ? V2 : V1;
4201 for (int i = 0; i != 8; ++i) {
4202 int Elt0 = MaskVals[i*2];
4203 int Elt1 = MaskVals[i*2+1];
4205 // This word of the result is all undef, skip it.
4206 if (Elt0 < 0 && Elt1 < 0)
4209 // This word of the result is already in the correct place, skip it.
4210 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4212 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4215 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4216 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4219 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4220 // using a single extract together, load it and store it.
4221 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4222 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4223 DAG.getIntPtrConstant(Elt1 / 2));
4224 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4225 DAG.getIntPtrConstant(i));
4229 // If Elt1 is defined, extract it from the appropriate source. If the
4230 // source byte is not also odd, shift the extracted word left 8 bits
4231 // otherwise clear the bottom 8 bits if we need to do an or.
4233 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4234 DAG.getIntPtrConstant(Elt1 / 2));
4235 if ((Elt1 & 1) == 0)
4236 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4237 DAG.getConstant(8, TLI.getShiftAmountTy()));
4239 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4240 DAG.getConstant(0xFF00, MVT::i16));
4242 // If Elt0 is defined, extract it from the appropriate source. If the
4243 // source byte is not also even, shift the extracted word right 8 bits. If
4244 // Elt1 was also defined, OR the extracted values together before
4245 // inserting them in the result.
4247 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4248 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4249 if ((Elt0 & 1) != 0)
4250 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4251 DAG.getConstant(8, TLI.getShiftAmountTy()));
4253 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4254 DAG.getConstant(0x00FF, MVT::i16));
4255 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4258 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4259 DAG.getIntPtrConstant(i));
4261 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4264 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4265 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4266 /// done when every pair / quad of shuffle mask elements point to elements in
4267 /// the right sequence. e.g.
4268 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4270 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4272 TargetLowering &TLI, DebugLoc dl) {
4273 EVT VT = SVOp->getValueType(0);
4274 SDValue V1 = SVOp->getOperand(0);
4275 SDValue V2 = SVOp->getOperand(1);
4276 unsigned NumElems = VT.getVectorNumElements();
4277 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4278 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4279 EVT MaskEltVT = MaskVT.getVectorElementType();
4281 switch (VT.getSimpleVT().SimpleTy) {
4282 default: assert(false && "Unexpected!");
4283 case MVT::v4f32: NewVT = MVT::v2f64; break;
4284 case MVT::v4i32: NewVT = MVT::v2i64; break;
4285 case MVT::v8i16: NewVT = MVT::v4i32; break;
4286 case MVT::v16i8: NewVT = MVT::v4i32; break;
4289 if (NewWidth == 2) {
4295 int Scale = NumElems / NewWidth;
4296 SmallVector<int, 8> MaskVec;
4297 for (unsigned i = 0; i < NumElems; i += Scale) {
4299 for (int j = 0; j < Scale; ++j) {
4300 int EltIdx = SVOp->getMaskElt(i+j);
4304 StartIdx = EltIdx - (EltIdx % Scale);
4305 if (EltIdx != StartIdx + j)
4309 MaskVec.push_back(-1);
4311 MaskVec.push_back(StartIdx / Scale);
4314 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4315 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4316 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4319 /// getVZextMovL - Return a zero-extending vector move low node.
4321 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4322 SDValue SrcOp, SelectionDAG &DAG,
4323 const X86Subtarget *Subtarget, DebugLoc dl) {
4324 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4325 LoadSDNode *LD = NULL;
4326 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4327 LD = dyn_cast<LoadSDNode>(SrcOp);
4329 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4331 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4332 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4333 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4334 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4335 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4337 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4338 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4339 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4340 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4348 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4349 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4350 DAG.getNode(ISD::BIT_CONVERT, dl,
4354 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4357 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4358 SDValue V1 = SVOp->getOperand(0);
4359 SDValue V2 = SVOp->getOperand(1);
4360 DebugLoc dl = SVOp->getDebugLoc();
4361 EVT VT = SVOp->getValueType(0);
4363 SmallVector<std::pair<int, int>, 8> Locs;
4365 SmallVector<int, 8> Mask1(4U, -1);
4366 SmallVector<int, 8> PermMask;
4367 SVOp->getMask(PermMask);
4371 for (unsigned i = 0; i != 4; ++i) {
4372 int Idx = PermMask[i];
4374 Locs[i] = std::make_pair(-1, -1);
4376 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4378 Locs[i] = std::make_pair(0, NumLo);
4382 Locs[i] = std::make_pair(1, NumHi);
4384 Mask1[2+NumHi] = Idx;
4390 if (NumLo <= 2 && NumHi <= 2) {
4391 // If no more than two elements come from either vector. This can be
4392 // implemented with two shuffles. First shuffle gather the elements.
4393 // The second shuffle, which takes the first shuffle as both of its
4394 // vector operands, put the elements into the right order.
4395 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4397 SmallVector<int, 8> Mask2(4U, -1);
4399 for (unsigned i = 0; i != 4; ++i) {
4400 if (Locs[i].first == -1)
4403 unsigned Idx = (i < 2) ? 0 : 4;
4404 Idx += Locs[i].first * 2 + Locs[i].second;
4409 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4410 } else if (NumLo == 3 || NumHi == 3) {
4411 // Otherwise, we must have three elements from one vector, call it X, and
4412 // one element from the other, call it Y. First, use a shufps to build an
4413 // intermediate vector with the one element from Y and the element from X
4414 // that will be in the same half in the final destination (the indexes don't
4415 // matter). Then, use a shufps to build the final vector, taking the half
4416 // containing the element from Y from the intermediate, and the other half
4419 // Normalize it so the 3 elements come from V1.
4420 CommuteVectorShuffleMask(PermMask, VT);
4424 // Find the element from V2.
4426 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4427 int Val = PermMask[HiIndex];
4434 Mask1[0] = PermMask[HiIndex];
4436 Mask1[2] = PermMask[HiIndex^1];
4438 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4441 Mask1[0] = PermMask[0];
4442 Mask1[1] = PermMask[1];
4443 Mask1[2] = HiIndex & 1 ? 6 : 4;
4444 Mask1[3] = HiIndex & 1 ? 4 : 6;
4445 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4447 Mask1[0] = HiIndex & 1 ? 2 : 0;
4448 Mask1[1] = HiIndex & 1 ? 0 : 2;
4449 Mask1[2] = PermMask[2];
4450 Mask1[3] = PermMask[3];
4455 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4459 // Break it into (shuffle shuffle_hi, shuffle_lo).
4461 SmallVector<int,8> LoMask(4U, -1);
4462 SmallVector<int,8> HiMask(4U, -1);
4464 SmallVector<int,8> *MaskPtr = &LoMask;
4465 unsigned MaskIdx = 0;
4468 for (unsigned i = 0; i != 4; ++i) {
4475 int Idx = PermMask[i];
4477 Locs[i] = std::make_pair(-1, -1);
4478 } else if (Idx < 4) {
4479 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4480 (*MaskPtr)[LoIdx] = Idx;
4483 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4484 (*MaskPtr)[HiIdx] = Idx;
4489 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4490 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4491 SmallVector<int, 8> MaskOps;
4492 for (unsigned i = 0; i != 4; ++i) {
4493 if (Locs[i].first == -1) {
4494 MaskOps.push_back(-1);
4496 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4497 MaskOps.push_back(Idx);
4500 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4504 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4505 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4506 SDValue V1 = Op.getOperand(0);
4507 SDValue V2 = Op.getOperand(1);
4508 EVT VT = Op.getValueType();
4509 DebugLoc dl = Op.getDebugLoc();
4510 unsigned NumElems = VT.getVectorNumElements();
4511 bool isMMX = VT.getSizeInBits() == 64;
4512 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4513 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4514 bool V1IsSplat = false;
4515 bool V2IsSplat = false;
4517 if (isZeroShuffle(SVOp))
4518 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4520 // Promote splats to v4f32.
4521 if (SVOp->isSplat()) {
4522 if (isMMX || NumElems < 4)
4524 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4527 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4529 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4530 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4531 if (NewOp.getNode())
4532 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4533 LowerVECTOR_SHUFFLE(NewOp, DAG));
4534 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4535 // FIXME: Figure out a cleaner way to do this.
4536 // Try to make use of movq to zero out the top part.
4537 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4538 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4539 if (NewOp.getNode()) {
4540 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4541 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4542 DAG, Subtarget, dl);
4544 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4545 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4546 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4547 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4548 DAG, Subtarget, dl);
4552 if (X86::isPSHUFDMask(SVOp))
4555 // Check if this can be converted into a logical shift.
4556 bool isLeft = false;
4559 bool isShift = getSubtarget()->hasSSE2() &&
4560 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4561 if (isShift && ShVal.hasOneUse()) {
4562 // If the shifted value has multiple uses, it may be cheaper to use
4563 // v_set0 + movlhps or movhlps, etc.
4564 EVT EltVT = VT.getVectorElementType();
4565 ShAmt *= EltVT.getSizeInBits();
4566 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4569 if (X86::isMOVLMask(SVOp)) {
4572 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4573 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4578 // FIXME: fold these into legal mask.
4579 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4580 X86::isMOVSLDUPMask(SVOp) ||
4581 X86::isMOVHLPSMask(SVOp) ||
4582 X86::isMOVLHPSMask(SVOp) ||
4583 X86::isMOVLPMask(SVOp)))
4586 if (ShouldXformToMOVHLPS(SVOp) ||
4587 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4588 return CommuteVectorShuffle(SVOp, DAG);
4591 // No better options. Use a vshl / vsrl.
4592 EVT EltVT = VT.getVectorElementType();
4593 ShAmt *= EltVT.getSizeInBits();
4594 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4597 bool Commuted = false;
4598 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4599 // 1,1,1,1 -> v8i16 though.
4600 V1IsSplat = isSplatVector(V1.getNode());
4601 V2IsSplat = isSplatVector(V2.getNode());
4603 // Canonicalize the splat or undef, if present, to be on the RHS.
4604 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4605 Op = CommuteVectorShuffle(SVOp, DAG);
4606 SVOp = cast<ShuffleVectorSDNode>(Op);
4607 V1 = SVOp->getOperand(0);
4608 V2 = SVOp->getOperand(1);
4609 std::swap(V1IsSplat, V2IsSplat);
4610 std::swap(V1IsUndef, V2IsUndef);
4614 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4615 // Shuffling low element of v1 into undef, just return v1.
4618 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4619 // the instruction selector will not match, so get a canonical MOVL with
4620 // swapped operands to undo the commute.
4621 return getMOVL(DAG, dl, VT, V2, V1);
4624 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4625 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4626 X86::isUNPCKLMask(SVOp) ||
4627 X86::isUNPCKHMask(SVOp))
4631 // Normalize mask so all entries that point to V2 points to its first
4632 // element then try to match unpck{h|l} again. If match, return a
4633 // new vector_shuffle with the corrected mask.
4634 SDValue NewMask = NormalizeMask(SVOp, DAG);
4635 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4636 if (NSVOp != SVOp) {
4637 if (X86::isUNPCKLMask(NSVOp, true)) {
4639 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4646 // Commute is back and try unpck* again.
4647 // FIXME: this seems wrong.
4648 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4649 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4650 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4651 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4652 X86::isUNPCKLMask(NewSVOp) ||
4653 X86::isUNPCKHMask(NewSVOp))
4657 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4659 // Normalize the node to match x86 shuffle ops if needed
4660 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4661 return CommuteVectorShuffle(SVOp, DAG);
4663 // Check for legal shuffle and return?
4664 SmallVector<int, 16> PermMask;
4665 SVOp->getMask(PermMask);
4666 if (isShuffleMaskLegal(PermMask, VT))
4669 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4670 if (VT == MVT::v8i16) {
4671 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4672 if (NewOp.getNode())
4676 if (VT == MVT::v16i8) {
4677 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4678 if (NewOp.getNode())
4682 // Handle all 4 wide cases with a number of shuffles except for MMX.
4683 if (NumElems == 4 && !isMMX)
4684 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4690 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4691 SelectionDAG &DAG) {
4692 EVT VT = Op.getValueType();
4693 DebugLoc dl = Op.getDebugLoc();
4694 if (VT.getSizeInBits() == 8) {
4695 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4696 Op.getOperand(0), Op.getOperand(1));
4697 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4698 DAG.getValueType(VT));
4699 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4700 } else if (VT.getSizeInBits() == 16) {
4701 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4702 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4704 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4705 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4706 DAG.getNode(ISD::BIT_CONVERT, dl,
4710 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4711 Op.getOperand(0), Op.getOperand(1));
4712 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4713 DAG.getValueType(VT));
4714 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4715 } else if (VT == MVT::f32) {
4716 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4717 // the result back to FR32 register. It's only worth matching if the
4718 // result has a single use which is a store or a bitcast to i32. And in
4719 // the case of a store, it's not worth it if the index is a constant 0,
4720 // because a MOVSSmr can be used instead, which is smaller and faster.
4721 if (!Op.hasOneUse())
4723 SDNode *User = *Op.getNode()->use_begin();
4724 if ((User->getOpcode() != ISD::STORE ||
4725 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4726 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4727 (User->getOpcode() != ISD::BIT_CONVERT ||
4728 User->getValueType(0) != MVT::i32))
4730 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4731 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4734 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4735 } else if (VT == MVT::i32) {
4736 // ExtractPS works with constant index.
4737 if (isa<ConstantSDNode>(Op.getOperand(1)))
4745 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4746 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4749 if (Subtarget->hasSSE41()) {
4750 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4755 EVT VT = Op.getValueType();
4756 DebugLoc dl = Op.getDebugLoc();
4757 // TODO: handle v16i8.
4758 if (VT.getSizeInBits() == 16) {
4759 SDValue Vec = Op.getOperand(0);
4760 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4762 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4763 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4764 DAG.getNode(ISD::BIT_CONVERT, dl,
4767 // Transform it so it match pextrw which produces a 32-bit result.
4768 EVT EltVT = MVT::i32;
4769 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4770 Op.getOperand(0), Op.getOperand(1));
4771 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4772 DAG.getValueType(VT));
4773 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4774 } else if (VT.getSizeInBits() == 32) {
4775 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4779 // SHUFPS the element to the lowest double word, then movss.
4780 int Mask[4] = { Idx, -1, -1, -1 };
4781 EVT VVT = Op.getOperand(0).getValueType();
4782 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4783 DAG.getUNDEF(VVT), Mask);
4784 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4785 DAG.getIntPtrConstant(0));
4786 } else if (VT.getSizeInBits() == 64) {
4787 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4788 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4789 // to match extract_elt for f64.
4790 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4794 // UNPCKHPD the element to the lowest double word, then movsd.
4795 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4796 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4797 int Mask[2] = { 1, -1 };
4798 EVT VVT = Op.getOperand(0).getValueType();
4799 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4800 DAG.getUNDEF(VVT), Mask);
4801 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4802 DAG.getIntPtrConstant(0));
4809 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4810 EVT VT = Op.getValueType();
4811 EVT EltVT = VT.getVectorElementType();
4812 DebugLoc dl = Op.getDebugLoc();
4814 SDValue N0 = Op.getOperand(0);
4815 SDValue N1 = Op.getOperand(1);
4816 SDValue N2 = Op.getOperand(2);
4818 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4819 isa<ConstantSDNode>(N2)) {
4820 unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4822 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4824 if (N1.getValueType() != MVT::i32)
4825 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4826 if (N2.getValueType() != MVT::i32)
4827 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4828 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4829 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4830 // Bits [7:6] of the constant are the source select. This will always be
4831 // zero here. The DAG Combiner may combine an extract_elt index into these
4832 // bits. For example (insert (extract, 3), 2) could be matched by putting
4833 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4834 // Bits [5:4] of the constant are the destination select. This is the
4835 // value of the incoming immediate.
4836 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4837 // combine either bitwise AND or insert of float 0.0 to set these bits.
4838 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4839 // Create this as a scalar to vector..
4840 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4841 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4842 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4843 // PINSR* works with constant index.
4850 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4851 EVT VT = Op.getValueType();
4852 EVT EltVT = VT.getVectorElementType();
4854 if (Subtarget->hasSSE41())
4855 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4857 if (EltVT == MVT::i8)
4860 DebugLoc dl = Op.getDebugLoc();
4861 SDValue N0 = Op.getOperand(0);
4862 SDValue N1 = Op.getOperand(1);
4863 SDValue N2 = Op.getOperand(2);
4865 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4866 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4867 // as its second argument.
4868 if (N1.getValueType() != MVT::i32)
4869 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4870 if (N2.getValueType() != MVT::i32)
4871 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4872 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4878 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4879 DebugLoc dl = Op.getDebugLoc();
4880 if (Op.getValueType() == MVT::v2f32)
4881 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4882 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4883 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4884 Op.getOperand(0))));
4886 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4887 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4889 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4890 EVT VT = MVT::v2i32;
4891 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4898 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4899 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4902 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4903 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4904 // one of the above mentioned nodes. It has to be wrapped because otherwise
4905 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4906 // be used to form addressing mode. These wrapped nodes will be selected
4909 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4910 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4912 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4914 unsigned char OpFlag = 0;
4915 unsigned WrapperKind = X86ISD::Wrapper;
4916 CodeModel::Model M = getTargetMachine().getCodeModel();
4918 if (Subtarget->isPICStyleRIPRel() &&
4919 (M == CodeModel::Small || M == CodeModel::Kernel))
4920 WrapperKind = X86ISD::WrapperRIP;
4921 else if (Subtarget->isPICStyleGOT())
4922 OpFlag = X86II::MO_GOTOFF;
4923 else if (Subtarget->isPICStyleStubPIC())
4924 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4926 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4928 CP->getOffset(), OpFlag);
4929 DebugLoc DL = CP->getDebugLoc();
4930 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4931 // With PIC, the address is actually $g + Offset.
4933 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4934 DAG.getNode(X86ISD::GlobalBaseReg,
4935 DebugLoc::getUnknownLoc(), getPointerTy()),
4942 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4943 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4945 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4947 unsigned char OpFlag = 0;
4948 unsigned WrapperKind = X86ISD::Wrapper;
4949 CodeModel::Model M = getTargetMachine().getCodeModel();
4951 if (Subtarget->isPICStyleRIPRel() &&
4952 (M == CodeModel::Small || M == CodeModel::Kernel))
4953 WrapperKind = X86ISD::WrapperRIP;
4954 else if (Subtarget->isPICStyleGOT())
4955 OpFlag = X86II::MO_GOTOFF;
4956 else if (Subtarget->isPICStyleStubPIC())
4957 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4959 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4961 DebugLoc DL = JT->getDebugLoc();
4962 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4964 // With PIC, the address is actually $g + Offset.
4966 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4967 DAG.getNode(X86ISD::GlobalBaseReg,
4968 DebugLoc::getUnknownLoc(), getPointerTy()),
4976 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4977 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4979 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4981 unsigned char OpFlag = 0;
4982 unsigned WrapperKind = X86ISD::Wrapper;
4983 CodeModel::Model M = getTargetMachine().getCodeModel();
4985 if (Subtarget->isPICStyleRIPRel() &&
4986 (M == CodeModel::Small || M == CodeModel::Kernel))
4987 WrapperKind = X86ISD::WrapperRIP;
4988 else if (Subtarget->isPICStyleGOT())
4989 OpFlag = X86II::MO_GOTOFF;
4990 else if (Subtarget->isPICStyleStubPIC())
4991 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4993 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4995 DebugLoc DL = Op.getDebugLoc();
4996 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4999 // With PIC, the address is actually $g + Offset.
5000 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5001 !Subtarget->is64Bit()) {
5002 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5003 DAG.getNode(X86ISD::GlobalBaseReg,
5004 DebugLoc::getUnknownLoc(),
5013 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
5014 // Create the TargetBlockAddressAddress node.
5015 unsigned char OpFlags =
5016 Subtarget->ClassifyBlockAddressReference();
5017 CodeModel::Model M = getTargetMachine().getCodeModel();
5018 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5019 DebugLoc dl = Op.getDebugLoc();
5020 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5021 /*isTarget=*/true, OpFlags);
5023 if (Subtarget->isPICStyleRIPRel() &&
5024 (M == CodeModel::Small || M == CodeModel::Kernel))
5025 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5027 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5029 // With PIC, the address is actually $g + Offset.
5030 if (isGlobalRelativeToPICBase(OpFlags)) {
5031 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5032 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5040 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5042 SelectionDAG &DAG) const {
5043 // Create the TargetGlobalAddress node, folding in the constant
5044 // offset if it is legal.
5045 unsigned char OpFlags =
5046 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5047 CodeModel::Model M = getTargetMachine().getCodeModel();
5049 if (OpFlags == X86II::MO_NO_FLAG &&
5050 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5051 // A direct static reference to a global.
5052 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
5055 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
5058 if (Subtarget->isPICStyleRIPRel() &&
5059 (M == CodeModel::Small || M == CodeModel::Kernel))
5060 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5062 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5064 // With PIC, the address is actually $g + Offset.
5065 if (isGlobalRelativeToPICBase(OpFlags)) {
5066 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5067 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5071 // For globals that require a load from a stub to get the address, emit the
5073 if (isGlobalStubReference(OpFlags))
5074 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5075 PseudoSourceValue::getGOT(), 0, false, false, 0);
5077 // If there was a non-zero offset that we didn't fold, create an explicit
5080 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5081 DAG.getConstant(Offset, getPointerTy()));
5087 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
5088 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5089 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5090 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5094 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5095 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5096 unsigned char OperandFlags) {
5097 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5098 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5099 DebugLoc dl = GA->getDebugLoc();
5100 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
5101 GA->getValueType(0),
5105 SDValue Ops[] = { Chain, TGA, *InFlag };
5106 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5108 SDValue Ops[] = { Chain, TGA };
5109 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5112 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5113 MFI->setHasCalls(true);
5115 SDValue Flag = Chain.getValue(1);
5116 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5119 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5121 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5124 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5125 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5126 DAG.getNode(X86ISD::GlobalBaseReg,
5127 DebugLoc::getUnknownLoc(),
5129 InFlag = Chain.getValue(1);
5131 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5134 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5136 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5138 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5139 X86::RAX, X86II::MO_TLSGD);
5142 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5143 // "local exec" model.
5144 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5145 const EVT PtrVT, TLSModel::Model model,
5147 DebugLoc dl = GA->getDebugLoc();
5148 // Get the Thread Pointer
5149 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5150 DebugLoc::getUnknownLoc(), PtrVT,
5151 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5154 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5155 NULL, 0, false, false, 0);
5157 unsigned char OperandFlags = 0;
5158 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5160 unsigned WrapperKind = X86ISD::Wrapper;
5161 if (model == TLSModel::LocalExec) {
5162 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5163 } else if (is64Bit) {
5164 assert(model == TLSModel::InitialExec);
5165 OperandFlags = X86II::MO_GOTTPOFF;
5166 WrapperKind = X86ISD::WrapperRIP;
5168 assert(model == TLSModel::InitialExec);
5169 OperandFlags = X86II::MO_INDNTPOFF;
5172 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5174 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5175 GA->getOffset(), OperandFlags);
5176 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5178 if (model == TLSModel::InitialExec)
5179 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5180 PseudoSourceValue::getGOT(), 0, false, false, 0);
5182 // The address of the thread local variable is the add of the thread
5183 // pointer with the offset of the variable.
5184 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5188 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
5189 // TODO: implement the "local dynamic" model
5190 // TODO: implement the "initial exec"model for pic executables
5191 assert(Subtarget->isTargetELF() &&
5192 "TLS not implemented for non-ELF targets");
5193 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5194 const GlobalValue *GV = GA->getGlobal();
5196 // If GV is an alias then use the aliasee for determining
5197 // thread-localness.
5198 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5199 GV = GA->resolveAliasedGlobal(false);
5201 TLSModel::Model model = getTLSModel(GV,
5202 getTargetMachine().getRelocationModel());
5205 case TLSModel::GeneralDynamic:
5206 case TLSModel::LocalDynamic: // not implemented
5207 if (Subtarget->is64Bit())
5208 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5209 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5211 case TLSModel::InitialExec:
5212 case TLSModel::LocalExec:
5213 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5214 Subtarget->is64Bit());
5217 llvm_unreachable("Unreachable");
5222 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5223 /// take a 2 x i32 value to shift plus a shift amount.
5224 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
5225 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5226 EVT VT = Op.getValueType();
5227 unsigned VTBits = VT.getSizeInBits();
5228 DebugLoc dl = Op.getDebugLoc();
5229 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5230 SDValue ShOpLo = Op.getOperand(0);
5231 SDValue ShOpHi = Op.getOperand(1);
5232 SDValue ShAmt = Op.getOperand(2);
5233 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5234 DAG.getConstant(VTBits - 1, MVT::i8))
5235 : DAG.getConstant(0, VT);
5238 if (Op.getOpcode() == ISD::SHL_PARTS) {
5239 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5240 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5242 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5243 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5246 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5247 DAG.getConstant(VTBits, MVT::i8));
5248 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
5249 AndNode, DAG.getConstant(0, MVT::i8));
5252 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5253 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5254 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5256 if (Op.getOpcode() == ISD::SHL_PARTS) {
5257 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5258 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5260 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5261 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5264 SDValue Ops[2] = { Lo, Hi };
5265 return DAG.getMergeValues(Ops, 2, dl);
5268 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5269 EVT SrcVT = Op.getOperand(0).getValueType();
5271 if (SrcVT.isVector()) {
5272 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5278 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5279 "Unknown SINT_TO_FP to lower!");
5281 // These are really Legal; return the operand so the caller accepts it as
5283 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5285 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5286 Subtarget->is64Bit()) {
5290 DebugLoc dl = Op.getDebugLoc();
5291 unsigned Size = SrcVT.getSizeInBits()/8;
5292 MachineFunction &MF = DAG.getMachineFunction();
5293 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5294 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5295 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5297 PseudoSourceValue::getFixedStack(SSFI), 0,
5299 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5302 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5304 SelectionDAG &DAG) {
5306 DebugLoc dl = Op.getDebugLoc();
5308 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5310 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5312 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5313 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5314 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5315 Tys, Ops, array_lengthof(Ops));
5318 Chain = Result.getValue(1);
5319 SDValue InFlag = Result.getValue(2);
5321 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5322 // shouldn't be necessary except that RFP cannot be live across
5323 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5324 MachineFunction &MF = DAG.getMachineFunction();
5325 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5326 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5327 Tys = DAG.getVTList(MVT::Other);
5329 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5331 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5332 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5333 PseudoSourceValue::getFixedStack(SSFI), 0,
5340 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5341 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5342 // This algorithm is not obvious. Here it is in C code, more or less:
5344 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5345 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5346 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5348 // Copy ints to xmm registers.
5349 __m128i xh = _mm_cvtsi32_si128( hi );
5350 __m128i xl = _mm_cvtsi32_si128( lo );
5352 // Combine into low half of a single xmm register.
5353 __m128i x = _mm_unpacklo_epi32( xh, xl );
5357 // Merge in appropriate exponents to give the integer bits the right
5359 x = _mm_unpacklo_epi32( x, exp );
5361 // Subtract away the biases to deal with the IEEE-754 double precision
5363 d = _mm_sub_pd( (__m128d) x, bias );
5365 // All conversions up to here are exact. The correctly rounded result is
5366 // calculated using the current rounding mode using the following
5368 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5369 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5370 // store doesn't really need to be here (except
5371 // maybe to zero the other double)
5376 DebugLoc dl = Op.getDebugLoc();
5377 LLVMContext *Context = DAG.getContext();
5379 // Build some magic constants.
5380 std::vector<Constant*> CV0;
5381 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5382 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5383 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5384 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5385 Constant *C0 = ConstantVector::get(CV0);
5386 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5388 std::vector<Constant*> CV1;
5390 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5392 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5393 Constant *C1 = ConstantVector::get(CV1);
5394 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5396 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5397 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5399 DAG.getIntPtrConstant(1)));
5400 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5401 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5403 DAG.getIntPtrConstant(0)));
5404 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5405 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5406 PseudoSourceValue::getConstantPool(), 0,
5408 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5409 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5410 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5411 PseudoSourceValue::getConstantPool(), 0,
5413 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5415 // Add the halves; easiest way is to swap them into another reg first.
5416 int ShufMask[2] = { 1, -1 };
5417 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5418 DAG.getUNDEF(MVT::v2f64), ShufMask);
5419 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5420 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5421 DAG.getIntPtrConstant(0));
5424 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5425 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5426 DebugLoc dl = Op.getDebugLoc();
5427 // FP constant to bias correct the final result.
5428 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5431 // Load the 32-bit value into an XMM register.
5432 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5433 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5435 DAG.getIntPtrConstant(0)));
5437 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5438 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5439 DAG.getIntPtrConstant(0));
5441 // Or the load with the bias.
5442 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5443 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5444 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5446 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5447 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5448 MVT::v2f64, Bias)));
5449 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5450 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5451 DAG.getIntPtrConstant(0));
5453 // Subtract the bias.
5454 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5456 // Handle final rounding.
5457 EVT DestVT = Op.getValueType();
5459 if (DestVT.bitsLT(MVT::f64)) {
5460 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5461 DAG.getIntPtrConstant(0));
5462 } else if (DestVT.bitsGT(MVT::f64)) {
5463 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5466 // Handle final rounding.
5470 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5471 SDValue N0 = Op.getOperand(0);
5472 DebugLoc dl = Op.getDebugLoc();
5474 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5475 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5476 // the optimization here.
5477 if (DAG.SignBitIsZero(N0))
5478 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5480 EVT SrcVT = N0.getValueType();
5481 if (SrcVT == MVT::i64) {
5482 // We only handle SSE2 f64 target here; caller can expand the rest.
5483 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5486 return LowerUINT_TO_FP_i64(Op, DAG);
5487 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5488 return LowerUINT_TO_FP_i32(Op, DAG);
5491 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5493 // Make a 64-bit buffer, and use it to build an FILD.
5494 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5495 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5496 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5497 getPointerTy(), StackSlot, WordOff);
5498 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5499 StackSlot, NULL, 0, false, false, 0);
5500 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5501 OffsetSlot, NULL, 0, false, false, 0);
5502 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5505 std::pair<SDValue,SDValue> X86TargetLowering::
5506 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5507 DebugLoc dl = Op.getDebugLoc();
5509 EVT DstTy = Op.getValueType();
5512 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5516 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5517 DstTy.getSimpleVT() >= MVT::i16 &&
5518 "Unknown FP_TO_SINT to lower!");
5520 // These are really Legal.
5521 if (DstTy == MVT::i32 &&
5522 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5523 return std::make_pair(SDValue(), SDValue());
5524 if (Subtarget->is64Bit() &&
5525 DstTy == MVT::i64 &&
5526 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5527 return std::make_pair(SDValue(), SDValue());
5529 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5531 MachineFunction &MF = DAG.getMachineFunction();
5532 unsigned MemSize = DstTy.getSizeInBits()/8;
5533 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5534 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5537 switch (DstTy.getSimpleVT().SimpleTy) {
5538 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5539 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5540 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5541 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5544 SDValue Chain = DAG.getEntryNode();
5545 SDValue Value = Op.getOperand(0);
5546 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5547 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5548 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5549 PseudoSourceValue::getFixedStack(SSFI), 0,
5551 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5553 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5555 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5556 Chain = Value.getValue(1);
5557 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5558 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5561 // Build the FP_TO_INT*_IN_MEM
5562 SDValue Ops[] = { Chain, Value, StackSlot };
5563 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5565 return std::make_pair(FIST, StackSlot);
5568 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5569 if (Op.getValueType().isVector()) {
5570 if (Op.getValueType() == MVT::v2i32 &&
5571 Op.getOperand(0).getValueType() == MVT::v2f64) {
5577 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5578 SDValue FIST = Vals.first, StackSlot = Vals.second;
5579 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5580 if (FIST.getNode() == 0) return Op;
5583 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5584 FIST, StackSlot, NULL, 0, false, false, 0);
5587 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5588 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5589 SDValue FIST = Vals.first, StackSlot = Vals.second;
5590 assert(FIST.getNode() && "Unexpected failure");
5593 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5594 FIST, StackSlot, NULL, 0, false, false, 0);
5597 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5598 LLVMContext *Context = DAG.getContext();
5599 DebugLoc dl = Op.getDebugLoc();
5600 EVT VT = Op.getValueType();
5603 EltVT = VT.getVectorElementType();
5604 std::vector<Constant*> CV;
5605 if (EltVT == MVT::f64) {
5606 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5610 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5616 Constant *C = ConstantVector::get(CV);
5617 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5618 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5619 PseudoSourceValue::getConstantPool(), 0,
5621 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5624 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5625 LLVMContext *Context = DAG.getContext();
5626 DebugLoc dl = Op.getDebugLoc();
5627 EVT VT = Op.getValueType();
5630 EltVT = VT.getVectorElementType();
5631 std::vector<Constant*> CV;
5632 if (EltVT == MVT::f64) {
5633 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5637 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5643 Constant *C = ConstantVector::get(CV);
5644 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5645 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5646 PseudoSourceValue::getConstantPool(), 0,
5648 if (VT.isVector()) {
5649 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5650 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5651 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5653 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5655 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5659 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5660 LLVMContext *Context = DAG.getContext();
5661 SDValue Op0 = Op.getOperand(0);
5662 SDValue Op1 = Op.getOperand(1);
5663 DebugLoc dl = Op.getDebugLoc();
5664 EVT VT = Op.getValueType();
5665 EVT SrcVT = Op1.getValueType();
5667 // If second operand is smaller, extend it first.
5668 if (SrcVT.bitsLT(VT)) {
5669 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5672 // And if it is bigger, shrink it first.
5673 if (SrcVT.bitsGT(VT)) {
5674 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5678 // At this point the operands and the result should have the same
5679 // type, and that won't be f80 since that is not custom lowered.
5681 // First get the sign bit of second operand.
5682 std::vector<Constant*> CV;
5683 if (SrcVT == MVT::f64) {
5684 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5685 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5687 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5688 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5689 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5690 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5692 Constant *C = ConstantVector::get(CV);
5693 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5694 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5695 PseudoSourceValue::getConstantPool(), 0,
5697 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5699 // Shift sign bit right or left if the two operands have different types.
5700 if (SrcVT.bitsGT(VT)) {
5701 // Op0 is MVT::f32, Op1 is MVT::f64.
5702 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5703 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5704 DAG.getConstant(32, MVT::i32));
5705 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5706 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5707 DAG.getIntPtrConstant(0));
5710 // Clear first operand sign bit.
5712 if (VT == MVT::f64) {
5713 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5714 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5716 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5717 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5718 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5719 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5721 C = ConstantVector::get(CV);
5722 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5723 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5724 PseudoSourceValue::getConstantPool(), 0,
5726 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5728 // Or the value with the sign bit.
5729 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5732 /// Emit nodes that will be selected as "test Op0,Op0", or something
5734 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5735 SelectionDAG &DAG) {
5736 DebugLoc dl = Op.getDebugLoc();
5738 // CF and OF aren't always set the way we want. Determine which
5739 // of these we need.
5740 bool NeedCF = false;
5741 bool NeedOF = false;
5743 case X86::COND_A: case X86::COND_AE:
5744 case X86::COND_B: case X86::COND_BE:
5747 case X86::COND_G: case X86::COND_GE:
5748 case X86::COND_L: case X86::COND_LE:
5749 case X86::COND_O: case X86::COND_NO:
5755 // See if we can use the EFLAGS value from the operand instead of
5756 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5757 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5758 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5759 unsigned Opcode = 0;
5760 unsigned NumOperands = 0;
5761 switch (Op.getNode()->getOpcode()) {
5763 // Due to an isel shortcoming, be conservative if this add is likely to
5764 // be selected as part of a load-modify-store instruction. When the root
5765 // node in a match is a store, isel doesn't know how to remap non-chain
5766 // non-flag uses of other nodes in the match, such as the ADD in this
5767 // case. This leads to the ADD being left around and reselected, with
5768 // the result being two adds in the output.
5769 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5770 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5771 if (UI->getOpcode() == ISD::STORE)
5773 if (ConstantSDNode *C =
5774 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5775 // An add of one will be selected as an INC.
5776 if (C->getAPIntValue() == 1) {
5777 Opcode = X86ISD::INC;
5781 // An add of negative one (subtract of one) will be selected as a DEC.
5782 if (C->getAPIntValue().isAllOnesValue()) {
5783 Opcode = X86ISD::DEC;
5788 // Otherwise use a regular EFLAGS-setting add.
5789 Opcode = X86ISD::ADD;
5793 // If the primary and result isn't used, don't bother using X86ISD::AND,
5794 // because a TEST instruction will be better.
5795 bool NonFlagUse = false;
5796 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5797 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
5799 unsigned UOpNo = UI.getOperandNo();
5800 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
5801 // Look pass truncate.
5802 UOpNo = User->use_begin().getOperandNo();
5803 User = *User->use_begin();
5805 if (User->getOpcode() != ISD::BRCOND &&
5806 User->getOpcode() != ISD::SETCC &&
5807 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
5819 // Due to the ISEL shortcoming noted above, be conservative if this op is
5820 // likely to be selected as part of a load-modify-store instruction.
5821 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5822 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5823 if (UI->getOpcode() == ISD::STORE)
5825 // Otherwise use a regular EFLAGS-setting instruction.
5826 switch (Op.getNode()->getOpcode()) {
5827 case ISD::SUB: Opcode = X86ISD::SUB; break;
5828 case ISD::OR: Opcode = X86ISD::OR; break;
5829 case ISD::XOR: Opcode = X86ISD::XOR; break;
5830 case ISD::AND: Opcode = X86ISD::AND; break;
5831 default: llvm_unreachable("unexpected operator!");
5842 return SDValue(Op.getNode(), 1);
5848 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5849 SmallVector<SDValue, 4> Ops;
5850 for (unsigned i = 0; i != NumOperands; ++i)
5851 Ops.push_back(Op.getOperand(i));
5852 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5853 DAG.ReplaceAllUsesWith(Op, New);
5854 return SDValue(New.getNode(), 1);
5858 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5859 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5860 DAG.getConstant(0, Op.getValueType()));
5863 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5865 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5866 SelectionDAG &DAG) {
5867 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5868 if (C->getAPIntValue() == 0)
5869 return EmitTest(Op0, X86CC, DAG);
5871 DebugLoc dl = Op0.getDebugLoc();
5872 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5875 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
5876 /// if it's possible.
5877 static SDValue LowerToBT(SDValue And, ISD::CondCode CC,
5878 DebugLoc dl, SelectionDAG &DAG) {
5879 SDValue Op0 = And.getOperand(0);
5880 SDValue Op1 = And.getOperand(1);
5881 if (Op0.getOpcode() == ISD::TRUNCATE)
5882 Op0 = Op0.getOperand(0);
5883 if (Op1.getOpcode() == ISD::TRUNCATE)
5884 Op1 = Op1.getOperand(0);
5887 if (Op1.getOpcode() == ISD::SHL) {
5888 if (ConstantSDNode *And10C = dyn_cast<ConstantSDNode>(Op1.getOperand(0)))
5889 if (And10C->getZExtValue() == 1) {
5891 RHS = Op1.getOperand(1);
5893 } else if (Op0.getOpcode() == ISD::SHL) {
5894 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
5895 if (And00C->getZExtValue() == 1) {
5897 RHS = Op0.getOperand(1);
5899 } else if (Op1.getOpcode() == ISD::Constant) {
5900 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
5901 SDValue AndLHS = Op0;
5902 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5903 LHS = AndLHS.getOperand(0);
5904 RHS = AndLHS.getOperand(1);
5908 if (LHS.getNode()) {
5909 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5910 // instruction. Since the shift amount is in-range-or-undefined, we know
5911 // that doing a bittest on the i16 value is ok. We extend to i32 because
5912 // the encoding for the i16 version is larger than the i32 version.
5913 if (LHS.getValueType() == MVT::i8)
5914 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5916 // If the operand types disagree, extend the shift amount to match. Since
5917 // BT ignores high bits (like shifts) we can use anyextend.
5918 if (LHS.getValueType() != RHS.getValueType())
5919 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5921 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5922 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5923 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5924 DAG.getConstant(Cond, MVT::i8), BT);
5930 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5931 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5932 SDValue Op0 = Op.getOperand(0);
5933 SDValue Op1 = Op.getOperand(1);
5934 DebugLoc dl = Op.getDebugLoc();
5935 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5937 // Optimize to BT if possible.
5938 // Lower (X & (1 << N)) == 0 to BT(X, N).
5939 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5940 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5941 if (Op0.getOpcode() == ISD::AND &&
5943 Op1.getOpcode() == ISD::Constant &&
5944 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5945 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5946 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
5947 if (NewSetCC.getNode())
5951 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
5952 if (Op0.getOpcode() == X86ISD::SETCC &&
5953 Op1.getOpcode() == ISD::Constant &&
5954 cast<ConstantSDNode>(Op1)->getZExtValue() == 1 &&
5955 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5956 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
5957 CCode = X86::GetOppositeBranchCondition(CCode);
5958 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5959 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
5962 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5963 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5964 if (X86CC == X86::COND_INVALID)
5967 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5969 // Use sbb x, x to materialize carry bit into a GPR.
5970 if (X86CC == X86::COND_B)
5971 return DAG.getNode(ISD::AND, dl, MVT::i8,
5972 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
5973 DAG.getConstant(X86CC, MVT::i8), Cond),
5974 DAG.getConstant(1, MVT::i8));
5976 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5977 DAG.getConstant(X86CC, MVT::i8), Cond);
5980 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5982 SDValue Op0 = Op.getOperand(0);
5983 SDValue Op1 = Op.getOperand(1);
5984 SDValue CC = Op.getOperand(2);
5985 EVT VT = Op.getValueType();
5986 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5987 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5988 DebugLoc dl = Op.getDebugLoc();
5992 EVT VT0 = Op0.getValueType();
5993 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5994 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5997 switch (SetCCOpcode) {
6000 case ISD::SETEQ: SSECC = 0; break;
6002 case ISD::SETGT: Swap = true; // Fallthrough
6004 case ISD::SETOLT: SSECC = 1; break;
6006 case ISD::SETGE: Swap = true; // Fallthrough
6008 case ISD::SETOLE: SSECC = 2; break;
6009 case ISD::SETUO: SSECC = 3; break;
6011 case ISD::SETNE: SSECC = 4; break;
6012 case ISD::SETULE: Swap = true;
6013 case ISD::SETUGE: SSECC = 5; break;
6014 case ISD::SETULT: Swap = true;
6015 case ISD::SETUGT: SSECC = 6; break;
6016 case ISD::SETO: SSECC = 7; break;
6019 std::swap(Op0, Op1);
6021 // In the two special cases we can't handle, emit two comparisons.
6023 if (SetCCOpcode == ISD::SETUEQ) {
6025 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
6026 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6027 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6029 else if (SetCCOpcode == ISD::SETONE) {
6031 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6032 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6033 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6035 llvm_unreachable("Illegal FP comparison");
6037 // Handle all other FP comparisons here.
6038 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6041 // We are handling one of the integer comparisons here. Since SSE only has
6042 // GT and EQ comparisons for integer, swapping operands and multiple
6043 // operations may be required for some comparisons.
6044 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6045 bool Swap = false, Invert = false, FlipSigns = false;
6047 switch (VT.getSimpleVT().SimpleTy) {
6050 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6052 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6054 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6055 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6058 switch (SetCCOpcode) {
6060 case ISD::SETNE: Invert = true;
6061 case ISD::SETEQ: Opc = EQOpc; break;
6062 case ISD::SETLT: Swap = true;
6063 case ISD::SETGT: Opc = GTOpc; break;
6064 case ISD::SETGE: Swap = true;
6065 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
6066 case ISD::SETULT: Swap = true;
6067 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6068 case ISD::SETUGE: Swap = true;
6069 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6072 std::swap(Op0, Op1);
6074 // Since SSE has no unsigned integer comparisons, we need to flip the sign
6075 // bits of the inputs before performing those operations.
6077 EVT EltVT = VT.getVectorElementType();
6078 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6080 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6081 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6083 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6084 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6087 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6089 // If the logical-not of the result is required, perform that now.
6091 Result = DAG.getNOT(dl, Result, VT);
6096 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6097 static bool isX86LogicalCmp(SDValue Op) {
6098 unsigned Opc = Op.getNode()->getOpcode();
6099 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6101 if (Op.getResNo() == 1 &&
6102 (Opc == X86ISD::ADD ||
6103 Opc == X86ISD::SUB ||
6104 Opc == X86ISD::SMUL ||
6105 Opc == X86ISD::UMUL ||
6106 Opc == X86ISD::INC ||
6107 Opc == X86ISD::DEC ||
6108 Opc == X86ISD::OR ||
6109 Opc == X86ISD::XOR ||
6110 Opc == X86ISD::AND))
6116 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
6117 bool addTest = true;
6118 SDValue Cond = Op.getOperand(0);
6119 DebugLoc dl = Op.getDebugLoc();
6122 if (Cond.getOpcode() == ISD::SETCC) {
6123 SDValue NewCond = LowerSETCC(Cond, DAG);
6124 if (NewCond.getNode())
6128 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6129 SDValue Op1 = Op.getOperand(1);
6130 SDValue Op2 = Op.getOperand(2);
6131 if (Cond.getOpcode() == X86ISD::SETCC &&
6132 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6133 SDValue Cmp = Cond.getOperand(1);
6134 if (Cmp.getOpcode() == X86ISD::CMP) {
6135 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6136 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6137 ConstantSDNode *RHSC =
6138 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6139 if (N1C && N1C->isAllOnesValue() &&
6140 N2C && N2C->isNullValue() &&
6141 RHSC && RHSC->isNullValue()) {
6142 SDValue CmpOp0 = Cmp.getOperand(0);
6143 Cmp = DAG.getNode(X86ISD::CMP, dl, CmpOp0.getValueType(),
6144 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6145 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6146 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6151 // Look pass (and (setcc_carry (cmp ...)), 1).
6152 if (Cond.getOpcode() == ISD::AND &&
6153 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6154 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6155 if (C && C->getAPIntValue() == 1)
6156 Cond = Cond.getOperand(0);
6159 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6160 // setting operand in place of the X86ISD::SETCC.
6161 if (Cond.getOpcode() == X86ISD::SETCC ||
6162 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6163 CC = Cond.getOperand(0);
6165 SDValue Cmp = Cond.getOperand(1);
6166 unsigned Opc = Cmp.getOpcode();
6167 EVT VT = Op.getValueType();
6169 bool IllegalFPCMov = false;
6170 if (VT.isFloatingPoint() && !VT.isVector() &&
6171 !isScalarFPTypeInSSEReg(VT)) // FPStack?
6172 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6174 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6175 Opc == X86ISD::BT) { // FIXME
6182 // Look pass the truncate.
6183 if (Cond.getOpcode() == ISD::TRUNCATE)
6184 Cond = Cond.getOperand(0);
6186 // We know the result of AND is compared against zero. Try to match
6188 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6189 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6190 if (NewSetCC.getNode()) {
6191 CC = NewSetCC.getOperand(0);
6192 Cond = NewSetCC.getOperand(1);
6199 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6200 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6203 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6204 // condition is true.
6205 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6206 SDValue Ops[] = { Op2, Op1, CC, Cond };
6207 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6210 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6211 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6212 // from the AND / OR.
6213 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6214 Opc = Op.getOpcode();
6215 if (Opc != ISD::OR && Opc != ISD::AND)
6217 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6218 Op.getOperand(0).hasOneUse() &&
6219 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6220 Op.getOperand(1).hasOneUse());
6223 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6224 // 1 and that the SETCC node has a single use.
6225 static bool isXor1OfSetCC(SDValue Op) {
6226 if (Op.getOpcode() != ISD::XOR)
6228 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6229 if (N1C && N1C->getAPIntValue() == 1) {
6230 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6231 Op.getOperand(0).hasOneUse();
6236 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
6237 bool addTest = true;
6238 SDValue Chain = Op.getOperand(0);
6239 SDValue Cond = Op.getOperand(1);
6240 SDValue Dest = Op.getOperand(2);
6241 DebugLoc dl = Op.getDebugLoc();
6244 if (Cond.getOpcode() == ISD::SETCC) {
6245 SDValue NewCond = LowerSETCC(Cond, DAG);
6246 if (NewCond.getNode())
6250 // FIXME: LowerXALUO doesn't handle these!!
6251 else if (Cond.getOpcode() == X86ISD::ADD ||
6252 Cond.getOpcode() == X86ISD::SUB ||
6253 Cond.getOpcode() == X86ISD::SMUL ||
6254 Cond.getOpcode() == X86ISD::UMUL)
6255 Cond = LowerXALUO(Cond, DAG);
6258 // Look pass (and (setcc_carry (cmp ...)), 1).
6259 if (Cond.getOpcode() == ISD::AND &&
6260 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6261 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6262 if (C && C->getAPIntValue() == 1)
6263 Cond = Cond.getOperand(0);
6266 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6267 // setting operand in place of the X86ISD::SETCC.
6268 if (Cond.getOpcode() == X86ISD::SETCC ||
6269 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6270 CC = Cond.getOperand(0);
6272 SDValue Cmp = Cond.getOperand(1);
6273 unsigned Opc = Cmp.getOpcode();
6274 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6275 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6279 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6283 // These can only come from an arithmetic instruction with overflow,
6284 // e.g. SADDO, UADDO.
6285 Cond = Cond.getNode()->getOperand(1);
6292 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6293 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6294 if (CondOpc == ISD::OR) {
6295 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6296 // two branches instead of an explicit OR instruction with a
6298 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6299 isX86LogicalCmp(Cmp)) {
6300 CC = Cond.getOperand(0).getOperand(0);
6301 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6302 Chain, Dest, CC, Cmp);
6303 CC = Cond.getOperand(1).getOperand(0);
6307 } else { // ISD::AND
6308 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6309 // two branches instead of an explicit AND instruction with a
6310 // separate test. However, we only do this if this block doesn't
6311 // have a fall-through edge, because this requires an explicit
6312 // jmp when the condition is false.
6313 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6314 isX86LogicalCmp(Cmp) &&
6315 Op.getNode()->hasOneUse()) {
6316 X86::CondCode CCode =
6317 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6318 CCode = X86::GetOppositeBranchCondition(CCode);
6319 CC = DAG.getConstant(CCode, MVT::i8);
6320 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
6321 // Look for an unconditional branch following this conditional branch.
6322 // We need this because we need to reverse the successors in order
6323 // to implement FCMP_OEQ.
6324 if (User.getOpcode() == ISD::BR) {
6325 SDValue FalseBB = User.getOperand(1);
6327 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
6328 assert(NewBR == User);
6331 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6332 Chain, Dest, CC, Cmp);
6333 X86::CondCode CCode =
6334 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6335 CCode = X86::GetOppositeBranchCondition(CCode);
6336 CC = DAG.getConstant(CCode, MVT::i8);
6342 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6343 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6344 // It should be transformed during dag combiner except when the condition
6345 // is set by a arithmetics with overflow node.
6346 X86::CondCode CCode =
6347 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6348 CCode = X86::GetOppositeBranchCondition(CCode);
6349 CC = DAG.getConstant(CCode, MVT::i8);
6350 Cond = Cond.getOperand(0).getOperand(1);
6356 // Look pass the truncate.
6357 if (Cond.getOpcode() == ISD::TRUNCATE)
6358 Cond = Cond.getOperand(0);
6360 // We know the result of AND is compared against zero. Try to match
6362 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6363 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6364 if (NewSetCC.getNode()) {
6365 CC = NewSetCC.getOperand(0);
6366 Cond = NewSetCC.getOperand(1);
6373 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6374 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6376 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6377 Chain, Dest, CC, Cond);
6381 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6382 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6383 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6384 // that the guard pages used by the OS virtual memory manager are allocated in
6385 // correct sequence.
6387 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6388 SelectionDAG &DAG) {
6389 assert(Subtarget->isTargetCygMing() &&
6390 "This should be used only on Cygwin/Mingw targets");
6391 DebugLoc dl = Op.getDebugLoc();
6394 SDValue Chain = Op.getOperand(0);
6395 SDValue Size = Op.getOperand(1);
6396 // FIXME: Ensure alignment here
6400 EVT IntPtr = getPointerTy();
6401 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6403 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
6405 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6406 Flag = Chain.getValue(1);
6408 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6409 SDValue Ops[] = { Chain,
6410 DAG.getTargetExternalSymbol("_alloca", IntPtr),
6411 DAG.getRegister(X86::EAX, IntPtr),
6412 DAG.getRegister(X86StackPtr, SPTy),
6414 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
6415 Flag = Chain.getValue(1);
6417 Chain = DAG.getCALLSEQ_END(Chain,
6418 DAG.getIntPtrConstant(0, true),
6419 DAG.getIntPtrConstant(0, true),
6422 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6424 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6425 return DAG.getMergeValues(Ops1, 2, dl);
6429 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
6431 SDValue Dst, SDValue Src,
6432 SDValue Size, unsigned Align,
6434 uint64_t DstSVOff) {
6435 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6437 // If not DWORD aligned or size is more than the threshold, call the library.
6438 // The libc version is likely to be faster for these cases. It can use the
6439 // address value and run time information about the CPU.
6440 if ((Align & 3) != 0 ||
6442 ConstantSize->getZExtValue() >
6443 getSubtarget()->getMaxInlineSizeThreshold()) {
6444 SDValue InFlag(0, 0);
6446 // Check to see if there is a specialized entry-point for memory zeroing.
6447 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6449 if (const char *bzeroEntry = V &&
6450 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6451 EVT IntPtr = getPointerTy();
6452 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6453 TargetLowering::ArgListTy Args;
6454 TargetLowering::ArgListEntry Entry;
6456 Entry.Ty = IntPtrTy;
6457 Args.push_back(Entry);
6459 Args.push_back(Entry);
6460 std::pair<SDValue,SDValue> CallResult =
6461 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6462 false, false, false, false,
6463 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6464 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl,
6465 DAG.GetOrdering(Chain.getNode()));
6466 return CallResult.second;
6469 // Otherwise have the target-independent code call memset.
6473 uint64_t SizeVal = ConstantSize->getZExtValue();
6474 SDValue InFlag(0, 0);
6477 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6478 unsigned BytesLeft = 0;
6479 bool TwoRepStos = false;
6482 uint64_t Val = ValC->getZExtValue() & 255;
6484 // If the value is a constant, then we can potentially use larger sets.
6485 switch (Align & 3) {
6486 case 2: // WORD aligned
6489 Val = (Val << 8) | Val;
6491 case 0: // DWORD aligned
6494 Val = (Val << 8) | Val;
6495 Val = (Val << 16) | Val;
6496 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
6499 Val = (Val << 32) | Val;
6502 default: // Byte aligned
6505 Count = DAG.getIntPtrConstant(SizeVal);
6509 if (AVT.bitsGT(MVT::i8)) {
6510 unsigned UBytes = AVT.getSizeInBits() / 8;
6511 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6512 BytesLeft = SizeVal % UBytes;
6515 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6517 InFlag = Chain.getValue(1);
6520 Count = DAG.getIntPtrConstant(SizeVal);
6521 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6522 InFlag = Chain.getValue(1);
6525 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6528 InFlag = Chain.getValue(1);
6529 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6532 InFlag = Chain.getValue(1);
6534 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6535 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6536 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6539 InFlag = Chain.getValue(1);
6541 EVT CVT = Count.getValueType();
6542 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6543 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6544 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6547 InFlag = Chain.getValue(1);
6548 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6549 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
6550 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6551 } else if (BytesLeft) {
6552 // Handle the last 1 - 7 bytes.
6553 unsigned Offset = SizeVal - BytesLeft;
6554 EVT AddrVT = Dst.getValueType();
6555 EVT SizeVT = Size.getValueType();
6557 Chain = DAG.getMemset(Chain, dl,
6558 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6559 DAG.getConstant(Offset, AddrVT)),
6561 DAG.getConstant(BytesLeft, SizeVT),
6562 Align, DstSV, DstSVOff + Offset);
6565 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6570 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6571 SDValue Chain, SDValue Dst, SDValue Src,
6572 SDValue Size, unsigned Align,
6574 const Value *DstSV, uint64_t DstSVOff,
6575 const Value *SrcSV, uint64_t SrcSVOff) {
6576 // This requires the copy size to be a constant, preferrably
6577 // within a subtarget-specific limit.
6578 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6581 uint64_t SizeVal = ConstantSize->getZExtValue();
6582 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6585 /// If not DWORD aligned, call the library.
6586 if ((Align & 3) != 0)
6591 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6594 unsigned UBytes = AVT.getSizeInBits() / 8;
6595 unsigned CountVal = SizeVal / UBytes;
6596 SDValue Count = DAG.getIntPtrConstant(CountVal);
6597 unsigned BytesLeft = SizeVal % UBytes;
6599 SDValue InFlag(0, 0);
6600 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6603 InFlag = Chain.getValue(1);
6604 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6607 InFlag = Chain.getValue(1);
6608 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6611 InFlag = Chain.getValue(1);
6613 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6614 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6615 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops,
6616 array_lengthof(Ops));
6618 SmallVector<SDValue, 4> Results;
6619 Results.push_back(RepMovs);
6621 // Handle the last 1 - 7 bytes.
6622 unsigned Offset = SizeVal - BytesLeft;
6623 EVT DstVT = Dst.getValueType();
6624 EVT SrcVT = Src.getValueType();
6625 EVT SizeVT = Size.getValueType();
6626 Results.push_back(DAG.getMemcpy(Chain, dl,
6627 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6628 DAG.getConstant(Offset, DstVT)),
6629 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6630 DAG.getConstant(Offset, SrcVT)),
6631 DAG.getConstant(BytesLeft, SizeVT),
6632 Align, AlwaysInline,
6633 DstSV, DstSVOff + Offset,
6634 SrcSV, SrcSVOff + Offset));
6637 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6638 &Results[0], Results.size());
6641 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6642 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6643 DebugLoc dl = Op.getDebugLoc();
6645 if (!Subtarget->is64Bit()) {
6646 // vastart just stores the address of the VarArgsFrameIndex slot into the
6647 // memory location argument.
6648 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6649 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
6654 // gp_offset (0 - 6 * 8)
6655 // fp_offset (48 - 48 + 8 * 16)
6656 // overflow_arg_area (point to parameters coming in memory).
6658 SmallVector<SDValue, 8> MemOps;
6659 SDValue FIN = Op.getOperand(1);
6661 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6662 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6663 FIN, SV, 0, false, false, 0);
6664 MemOps.push_back(Store);
6667 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6668 FIN, DAG.getIntPtrConstant(4));
6669 Store = DAG.getStore(Op.getOperand(0), dl,
6670 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6671 FIN, SV, 0, false, false, 0);
6672 MemOps.push_back(Store);
6674 // Store ptr to overflow_arg_area
6675 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6676 FIN, DAG.getIntPtrConstant(4));
6677 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6678 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0,
6680 MemOps.push_back(Store);
6682 // Store ptr to reg_save_area.
6683 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6684 FIN, DAG.getIntPtrConstant(8));
6685 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6686 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0,
6688 MemOps.push_back(Store);
6689 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6690 &MemOps[0], MemOps.size());
6693 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6694 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6695 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6696 SDValue Chain = Op.getOperand(0);
6697 SDValue SrcPtr = Op.getOperand(1);
6698 SDValue SrcSV = Op.getOperand(2);
6700 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6704 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6705 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6706 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6707 SDValue Chain = Op.getOperand(0);
6708 SDValue DstPtr = Op.getOperand(1);
6709 SDValue SrcPtr = Op.getOperand(2);
6710 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6711 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6712 DebugLoc dl = Op.getDebugLoc();
6714 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6715 DAG.getIntPtrConstant(24), 8, false,
6716 DstSV, 0, SrcSV, 0);
6720 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6721 DebugLoc dl = Op.getDebugLoc();
6722 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6724 default: return SDValue(); // Don't custom lower most intrinsics.
6725 // Comparison intrinsics.
6726 case Intrinsic::x86_sse_comieq_ss:
6727 case Intrinsic::x86_sse_comilt_ss:
6728 case Intrinsic::x86_sse_comile_ss:
6729 case Intrinsic::x86_sse_comigt_ss:
6730 case Intrinsic::x86_sse_comige_ss:
6731 case Intrinsic::x86_sse_comineq_ss:
6732 case Intrinsic::x86_sse_ucomieq_ss:
6733 case Intrinsic::x86_sse_ucomilt_ss:
6734 case Intrinsic::x86_sse_ucomile_ss:
6735 case Intrinsic::x86_sse_ucomigt_ss:
6736 case Intrinsic::x86_sse_ucomige_ss:
6737 case Intrinsic::x86_sse_ucomineq_ss:
6738 case Intrinsic::x86_sse2_comieq_sd:
6739 case Intrinsic::x86_sse2_comilt_sd:
6740 case Intrinsic::x86_sse2_comile_sd:
6741 case Intrinsic::x86_sse2_comigt_sd:
6742 case Intrinsic::x86_sse2_comige_sd:
6743 case Intrinsic::x86_sse2_comineq_sd:
6744 case Intrinsic::x86_sse2_ucomieq_sd:
6745 case Intrinsic::x86_sse2_ucomilt_sd:
6746 case Intrinsic::x86_sse2_ucomile_sd:
6747 case Intrinsic::x86_sse2_ucomigt_sd:
6748 case Intrinsic::x86_sse2_ucomige_sd:
6749 case Intrinsic::x86_sse2_ucomineq_sd: {
6751 ISD::CondCode CC = ISD::SETCC_INVALID;
6754 case Intrinsic::x86_sse_comieq_ss:
6755 case Intrinsic::x86_sse2_comieq_sd:
6759 case Intrinsic::x86_sse_comilt_ss:
6760 case Intrinsic::x86_sse2_comilt_sd:
6764 case Intrinsic::x86_sse_comile_ss:
6765 case Intrinsic::x86_sse2_comile_sd:
6769 case Intrinsic::x86_sse_comigt_ss:
6770 case Intrinsic::x86_sse2_comigt_sd:
6774 case Intrinsic::x86_sse_comige_ss:
6775 case Intrinsic::x86_sse2_comige_sd:
6779 case Intrinsic::x86_sse_comineq_ss:
6780 case Intrinsic::x86_sse2_comineq_sd:
6784 case Intrinsic::x86_sse_ucomieq_ss:
6785 case Intrinsic::x86_sse2_ucomieq_sd:
6786 Opc = X86ISD::UCOMI;
6789 case Intrinsic::x86_sse_ucomilt_ss:
6790 case Intrinsic::x86_sse2_ucomilt_sd:
6791 Opc = X86ISD::UCOMI;
6794 case Intrinsic::x86_sse_ucomile_ss:
6795 case Intrinsic::x86_sse2_ucomile_sd:
6796 Opc = X86ISD::UCOMI;
6799 case Intrinsic::x86_sse_ucomigt_ss:
6800 case Intrinsic::x86_sse2_ucomigt_sd:
6801 Opc = X86ISD::UCOMI;
6804 case Intrinsic::x86_sse_ucomige_ss:
6805 case Intrinsic::x86_sse2_ucomige_sd:
6806 Opc = X86ISD::UCOMI;
6809 case Intrinsic::x86_sse_ucomineq_ss:
6810 case Intrinsic::x86_sse2_ucomineq_sd:
6811 Opc = X86ISD::UCOMI;
6816 SDValue LHS = Op.getOperand(1);
6817 SDValue RHS = Op.getOperand(2);
6818 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6819 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6820 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6821 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6822 DAG.getConstant(X86CC, MVT::i8), Cond);
6823 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6825 // ptest intrinsics. The intrinsic these come from are designed to return
6826 // an integer value, not just an instruction so lower it to the ptest
6827 // pattern and a setcc for the result.
6828 case Intrinsic::x86_sse41_ptestz:
6829 case Intrinsic::x86_sse41_ptestc:
6830 case Intrinsic::x86_sse41_ptestnzc:{
6833 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6834 case Intrinsic::x86_sse41_ptestz:
6836 X86CC = X86::COND_E;
6838 case Intrinsic::x86_sse41_ptestc:
6840 X86CC = X86::COND_B;
6842 case Intrinsic::x86_sse41_ptestnzc:
6844 X86CC = X86::COND_A;
6848 SDValue LHS = Op.getOperand(1);
6849 SDValue RHS = Op.getOperand(2);
6850 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6851 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6852 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6853 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6856 // Fix vector shift instructions where the last operand is a non-immediate
6858 case Intrinsic::x86_sse2_pslli_w:
6859 case Intrinsic::x86_sse2_pslli_d:
6860 case Intrinsic::x86_sse2_pslli_q:
6861 case Intrinsic::x86_sse2_psrli_w:
6862 case Intrinsic::x86_sse2_psrli_d:
6863 case Intrinsic::x86_sse2_psrli_q:
6864 case Intrinsic::x86_sse2_psrai_w:
6865 case Intrinsic::x86_sse2_psrai_d:
6866 case Intrinsic::x86_mmx_pslli_w:
6867 case Intrinsic::x86_mmx_pslli_d:
6868 case Intrinsic::x86_mmx_pslli_q:
6869 case Intrinsic::x86_mmx_psrli_w:
6870 case Intrinsic::x86_mmx_psrli_d:
6871 case Intrinsic::x86_mmx_psrli_q:
6872 case Intrinsic::x86_mmx_psrai_w:
6873 case Intrinsic::x86_mmx_psrai_d: {
6874 SDValue ShAmt = Op.getOperand(2);
6875 if (isa<ConstantSDNode>(ShAmt))
6878 unsigned NewIntNo = 0;
6879 EVT ShAmtVT = MVT::v4i32;
6881 case Intrinsic::x86_sse2_pslli_w:
6882 NewIntNo = Intrinsic::x86_sse2_psll_w;
6884 case Intrinsic::x86_sse2_pslli_d:
6885 NewIntNo = Intrinsic::x86_sse2_psll_d;
6887 case Intrinsic::x86_sse2_pslli_q:
6888 NewIntNo = Intrinsic::x86_sse2_psll_q;
6890 case Intrinsic::x86_sse2_psrli_w:
6891 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6893 case Intrinsic::x86_sse2_psrli_d:
6894 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6896 case Intrinsic::x86_sse2_psrli_q:
6897 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6899 case Intrinsic::x86_sse2_psrai_w:
6900 NewIntNo = Intrinsic::x86_sse2_psra_w;
6902 case Intrinsic::x86_sse2_psrai_d:
6903 NewIntNo = Intrinsic::x86_sse2_psra_d;
6906 ShAmtVT = MVT::v2i32;
6908 case Intrinsic::x86_mmx_pslli_w:
6909 NewIntNo = Intrinsic::x86_mmx_psll_w;
6911 case Intrinsic::x86_mmx_pslli_d:
6912 NewIntNo = Intrinsic::x86_mmx_psll_d;
6914 case Intrinsic::x86_mmx_pslli_q:
6915 NewIntNo = Intrinsic::x86_mmx_psll_q;
6917 case Intrinsic::x86_mmx_psrli_w:
6918 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6920 case Intrinsic::x86_mmx_psrli_d:
6921 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6923 case Intrinsic::x86_mmx_psrli_q:
6924 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6926 case Intrinsic::x86_mmx_psrai_w:
6927 NewIntNo = Intrinsic::x86_mmx_psra_w;
6929 case Intrinsic::x86_mmx_psrai_d:
6930 NewIntNo = Intrinsic::x86_mmx_psra_d;
6932 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6938 // The vector shift intrinsics with scalars uses 32b shift amounts but
6939 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6943 ShOps[1] = DAG.getConstant(0, MVT::i32);
6944 if (ShAmtVT == MVT::v4i32) {
6945 ShOps[2] = DAG.getUNDEF(MVT::i32);
6946 ShOps[3] = DAG.getUNDEF(MVT::i32);
6947 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6949 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6952 EVT VT = Op.getValueType();
6953 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6954 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6955 DAG.getConstant(NewIntNo, MVT::i32),
6956 Op.getOperand(1), ShAmt);
6961 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6962 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6963 DebugLoc dl = Op.getDebugLoc();
6966 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6968 DAG.getConstant(TD->getPointerSize(),
6969 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6970 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6971 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6973 NULL, 0, false, false, 0);
6976 // Just load the return address.
6977 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6978 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6979 RetAddrFI, NULL, 0, false, false, 0);
6982 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6983 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6984 MFI->setFrameAddressIsTaken(true);
6985 EVT VT = Op.getValueType();
6986 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6987 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6988 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6989 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6991 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
6996 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6997 SelectionDAG &DAG) {
6998 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7001 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
7003 MachineFunction &MF = DAG.getMachineFunction();
7004 SDValue Chain = Op.getOperand(0);
7005 SDValue Offset = Op.getOperand(1);
7006 SDValue Handler = Op.getOperand(2);
7007 DebugLoc dl = Op.getDebugLoc();
7009 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7011 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7013 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
7014 DAG.getIntPtrConstant(-TD->getPointerSize()));
7015 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7016 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
7017 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7018 MF.getRegInfo().addLiveOut(StoreAddrReg);
7020 return DAG.getNode(X86ISD::EH_RETURN, dl,
7022 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7025 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7026 SelectionDAG &DAG) {
7027 SDValue Root = Op.getOperand(0);
7028 SDValue Trmp = Op.getOperand(1); // trampoline
7029 SDValue FPtr = Op.getOperand(2); // nested function
7030 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7031 DebugLoc dl = Op.getDebugLoc();
7033 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7035 if (Subtarget->is64Bit()) {
7036 SDValue OutChains[6];
7038 // Large code-model.
7039 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7040 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7042 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7043 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7045 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7047 // Load the pointer to the nested function into R11.
7048 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7049 SDValue Addr = Trmp;
7050 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7051 Addr, TrmpAddr, 0, false, false, 0);
7053 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7054 DAG.getConstant(2, MVT::i64));
7055 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
7058 // Load the 'nest' parameter value into R10.
7059 // R10 is specified in X86CallingConv.td
7060 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7061 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7062 DAG.getConstant(10, MVT::i64));
7063 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7064 Addr, TrmpAddr, 10, false, false, 0);
7066 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7067 DAG.getConstant(12, MVT::i64));
7068 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
7071 // Jump to the nested function.
7072 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7073 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7074 DAG.getConstant(20, MVT::i64));
7075 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7076 Addr, TrmpAddr, 20, false, false, 0);
7078 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7079 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7080 DAG.getConstant(22, MVT::i64));
7081 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7082 TrmpAddr, 22, false, false, 0);
7085 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7086 return DAG.getMergeValues(Ops, 2, dl);
7088 const Function *Func =
7089 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7090 CallingConv::ID CC = Func->getCallingConv();
7095 llvm_unreachable("Unsupported calling convention");
7096 case CallingConv::C:
7097 case CallingConv::X86_StdCall: {
7098 // Pass 'nest' parameter in ECX.
7099 // Must be kept in sync with X86CallingConv.td
7102 // Check that ECX wasn't needed by an 'inreg' parameter.
7103 const FunctionType *FTy = Func->getFunctionType();
7104 const AttrListPtr &Attrs = Func->getAttributes();
7106 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7107 unsigned InRegCount = 0;
7110 for (FunctionType::param_iterator I = FTy->param_begin(),
7111 E = FTy->param_end(); I != E; ++I, ++Idx)
7112 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7113 // FIXME: should only count parameters that are lowered to integers.
7114 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7116 if (InRegCount > 2) {
7117 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
7122 case CallingConv::X86_FastCall:
7123 case CallingConv::Fast:
7124 // Pass 'nest' parameter in EAX.
7125 // Must be kept in sync with X86CallingConv.td
7130 SDValue OutChains[4];
7133 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7134 DAG.getConstant(10, MVT::i32));
7135 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7137 // This is storing the opcode for MOV32ri.
7138 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7139 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7140 OutChains[0] = DAG.getStore(Root, dl,
7141 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7142 Trmp, TrmpAddr, 0, false, false, 0);
7144 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7145 DAG.getConstant(1, MVT::i32));
7146 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
7149 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7150 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7151 DAG.getConstant(5, MVT::i32));
7152 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7153 TrmpAddr, 5, false, false, 1);
7155 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7156 DAG.getConstant(6, MVT::i32));
7157 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
7161 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7162 return DAG.getMergeValues(Ops, 2, dl);
7166 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
7168 The rounding mode is in bits 11:10 of FPSR, and has the following
7175 FLT_ROUNDS, on the other hand, expects the following:
7182 To perform the conversion, we do:
7183 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7186 MachineFunction &MF = DAG.getMachineFunction();
7187 const TargetMachine &TM = MF.getTarget();
7188 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7189 unsigned StackAlignment = TFI.getStackAlignment();
7190 EVT VT = Op.getValueType();
7191 DebugLoc dl = Op.getDebugLoc();
7193 // Save FP Control Word to stack slot
7194 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7195 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7197 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7198 DAG.getEntryNode(), StackSlot);
7200 // Load FP Control Word from stack slot
7201 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
7204 // Transform as necessary
7206 DAG.getNode(ISD::SRL, dl, MVT::i16,
7207 DAG.getNode(ISD::AND, dl, MVT::i16,
7208 CWD, DAG.getConstant(0x800, MVT::i16)),
7209 DAG.getConstant(11, MVT::i8));
7211 DAG.getNode(ISD::SRL, dl, MVT::i16,
7212 DAG.getNode(ISD::AND, dl, MVT::i16,
7213 CWD, DAG.getConstant(0x400, MVT::i16)),
7214 DAG.getConstant(9, MVT::i8));
7217 DAG.getNode(ISD::AND, dl, MVT::i16,
7218 DAG.getNode(ISD::ADD, dl, MVT::i16,
7219 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7220 DAG.getConstant(1, MVT::i16)),
7221 DAG.getConstant(3, MVT::i16));
7224 return DAG.getNode((VT.getSizeInBits() < 16 ?
7225 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7228 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
7229 EVT VT = Op.getValueType();
7231 unsigned NumBits = VT.getSizeInBits();
7232 DebugLoc dl = Op.getDebugLoc();
7234 Op = Op.getOperand(0);
7235 if (VT == MVT::i8) {
7236 // Zero extend to i32 since there is not an i8 bsr.
7238 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7241 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7242 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7243 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7245 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7248 DAG.getConstant(NumBits+NumBits-1, OpVT),
7249 DAG.getConstant(X86::COND_E, MVT::i8),
7252 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7254 // Finally xor with NumBits-1.
7255 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7258 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7262 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
7263 EVT VT = Op.getValueType();
7265 unsigned NumBits = VT.getSizeInBits();
7266 DebugLoc dl = Op.getDebugLoc();
7268 Op = Op.getOperand(0);
7269 if (VT == MVT::i8) {
7271 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7274 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7275 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7276 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7278 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7281 DAG.getConstant(NumBits, OpVT),
7282 DAG.getConstant(X86::COND_E, MVT::i8),
7285 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7288 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7292 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
7293 EVT VT = Op.getValueType();
7294 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7295 DebugLoc dl = Op.getDebugLoc();
7297 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7298 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7299 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7300 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7301 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7303 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7304 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7305 // return AloBlo + AloBhi + AhiBlo;
7307 SDValue A = Op.getOperand(0);
7308 SDValue B = Op.getOperand(1);
7310 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7311 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7312 A, DAG.getConstant(32, MVT::i32));
7313 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7314 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7315 B, DAG.getConstant(32, MVT::i32));
7316 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7317 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7319 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7320 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7322 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7323 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7325 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7326 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7327 AloBhi, DAG.getConstant(32, MVT::i32));
7328 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7329 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7330 AhiBlo, DAG.getConstant(32, MVT::i32));
7331 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7332 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7337 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
7338 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7339 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7340 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7341 // has only one use.
7342 SDNode *N = Op.getNode();
7343 SDValue LHS = N->getOperand(0);
7344 SDValue RHS = N->getOperand(1);
7345 unsigned BaseOp = 0;
7347 DebugLoc dl = Op.getDebugLoc();
7349 switch (Op.getOpcode()) {
7350 default: llvm_unreachable("Unknown ovf instruction!");
7352 // A subtract of one will be selected as a INC. Note that INC doesn't
7353 // set CF, so we can't do this for UADDO.
7354 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7355 if (C->getAPIntValue() == 1) {
7356 BaseOp = X86ISD::INC;
7360 BaseOp = X86ISD::ADD;
7364 BaseOp = X86ISD::ADD;
7368 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7369 // set CF, so we can't do this for USUBO.
7370 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7371 if (C->getAPIntValue() == 1) {
7372 BaseOp = X86ISD::DEC;
7376 BaseOp = X86ISD::SUB;
7380 BaseOp = X86ISD::SUB;
7384 BaseOp = X86ISD::SMUL;
7388 BaseOp = X86ISD::UMUL;
7393 // Also sets EFLAGS.
7394 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7395 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7398 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7399 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7401 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7405 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
7406 EVT T = Op.getValueType();
7407 DebugLoc dl = Op.getDebugLoc();
7410 switch(T.getSimpleVT().SimpleTy) {
7412 assert(false && "Invalid value type!");
7413 case MVT::i8: Reg = X86::AL; size = 1; break;
7414 case MVT::i16: Reg = X86::AX; size = 2; break;
7415 case MVT::i32: Reg = X86::EAX; size = 4; break;
7417 assert(Subtarget->is64Bit() && "Node not type legal!");
7418 Reg = X86::RAX; size = 8;
7421 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7422 Op.getOperand(2), SDValue());
7423 SDValue Ops[] = { cpIn.getValue(0),
7426 DAG.getTargetConstant(size, MVT::i8),
7428 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7429 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7431 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7435 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7436 SelectionDAG &DAG) {
7437 assert(Subtarget->is64Bit() && "Result not type legalized?");
7438 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7439 SDValue TheChain = Op.getOperand(0);
7440 DebugLoc dl = Op.getDebugLoc();
7441 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7442 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7443 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7445 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7446 DAG.getConstant(32, MVT::i8));
7448 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7451 return DAG.getMergeValues(Ops, 2, dl);
7454 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7455 SDNode *Node = Op.getNode();
7456 DebugLoc dl = Node->getDebugLoc();
7457 EVT T = Node->getValueType(0);
7458 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7459 DAG.getConstant(0, T), Node->getOperand(2));
7460 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7461 cast<AtomicSDNode>(Node)->getMemoryVT(),
7462 Node->getOperand(0),
7463 Node->getOperand(1), negOp,
7464 cast<AtomicSDNode>(Node)->getSrcValue(),
7465 cast<AtomicSDNode>(Node)->getAlignment());
7468 /// LowerOperation - Provide custom lowering hooks for some operations.
7470 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7471 switch (Op.getOpcode()) {
7472 default: llvm_unreachable("Should not custom lower this!");
7473 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7474 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7475 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7476 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7477 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7478 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7479 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7480 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7481 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7482 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7483 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7484 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7485 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7486 case ISD::SHL_PARTS:
7487 case ISD::SRA_PARTS:
7488 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7489 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7490 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7491 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7492 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7493 case ISD::FABS: return LowerFABS(Op, DAG);
7494 case ISD::FNEG: return LowerFNEG(Op, DAG);
7495 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7496 case ISD::SETCC: return LowerSETCC(Op, DAG);
7497 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7498 case ISD::SELECT: return LowerSELECT(Op, DAG);
7499 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7500 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7501 case ISD::VASTART: return LowerVASTART(Op, DAG);
7502 case ISD::VAARG: return LowerVAARG(Op, DAG);
7503 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7504 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7505 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7506 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7507 case ISD::FRAME_TO_ARGS_OFFSET:
7508 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7509 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7510 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7511 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7512 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7513 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7514 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7515 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7521 case ISD::UMULO: return LowerXALUO(Op, DAG);
7522 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7526 void X86TargetLowering::
7527 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7528 SelectionDAG &DAG, unsigned NewOp) {
7529 EVT T = Node->getValueType(0);
7530 DebugLoc dl = Node->getDebugLoc();
7531 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7533 SDValue Chain = Node->getOperand(0);
7534 SDValue In1 = Node->getOperand(1);
7535 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7536 Node->getOperand(2), DAG.getIntPtrConstant(0));
7537 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7538 Node->getOperand(2), DAG.getIntPtrConstant(1));
7539 SDValue Ops[] = { Chain, In1, In2L, In2H };
7540 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7542 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7543 cast<MemSDNode>(Node)->getMemOperand());
7544 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7545 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7546 Results.push_back(Result.getValue(2));
7549 /// ReplaceNodeResults - Replace a node with an illegal result type
7550 /// with a new node built out of custom code.
7551 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7552 SmallVectorImpl<SDValue>&Results,
7553 SelectionDAG &DAG) {
7554 DebugLoc dl = N->getDebugLoc();
7555 switch (N->getOpcode()) {
7557 assert(false && "Do not know how to custom type legalize this operation!");
7559 case ISD::FP_TO_SINT: {
7560 std::pair<SDValue,SDValue> Vals =
7561 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7562 SDValue FIST = Vals.first, StackSlot = Vals.second;
7563 if (FIST.getNode() != 0) {
7564 EVT VT = N->getValueType(0);
7565 // Return a load from the stack slot.
7566 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
7571 case ISD::READCYCLECOUNTER: {
7572 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7573 SDValue TheChain = N->getOperand(0);
7574 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7575 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7577 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7579 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7580 SDValue Ops[] = { eax, edx };
7581 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7582 Results.push_back(edx.getValue(1));
7585 case ISD::ATOMIC_CMP_SWAP: {
7586 EVT T = N->getValueType(0);
7587 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7588 SDValue cpInL, cpInH;
7589 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7590 DAG.getConstant(0, MVT::i32));
7591 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7592 DAG.getConstant(1, MVT::i32));
7593 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7594 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7596 SDValue swapInL, swapInH;
7597 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7598 DAG.getConstant(0, MVT::i32));
7599 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7600 DAG.getConstant(1, MVT::i32));
7601 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7603 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7604 swapInL.getValue(1));
7605 SDValue Ops[] = { swapInH.getValue(0),
7607 swapInH.getValue(1) };
7608 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7609 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7610 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7611 MVT::i32, Result.getValue(1));
7612 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7613 MVT::i32, cpOutL.getValue(2));
7614 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7615 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7616 Results.push_back(cpOutH.getValue(1));
7619 case ISD::ATOMIC_LOAD_ADD:
7620 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7622 case ISD::ATOMIC_LOAD_AND:
7623 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7625 case ISD::ATOMIC_LOAD_NAND:
7626 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7628 case ISD::ATOMIC_LOAD_OR:
7629 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7631 case ISD::ATOMIC_LOAD_SUB:
7632 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7634 case ISD::ATOMIC_LOAD_XOR:
7635 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7637 case ISD::ATOMIC_SWAP:
7638 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7643 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7645 default: return NULL;
7646 case X86ISD::BSF: return "X86ISD::BSF";
7647 case X86ISD::BSR: return "X86ISD::BSR";
7648 case X86ISD::SHLD: return "X86ISD::SHLD";
7649 case X86ISD::SHRD: return "X86ISD::SHRD";
7650 case X86ISD::FAND: return "X86ISD::FAND";
7651 case X86ISD::FOR: return "X86ISD::FOR";
7652 case X86ISD::FXOR: return "X86ISD::FXOR";
7653 case X86ISD::FSRL: return "X86ISD::FSRL";
7654 case X86ISD::FILD: return "X86ISD::FILD";
7655 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7656 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7657 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7658 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7659 case X86ISD::FLD: return "X86ISD::FLD";
7660 case X86ISD::FST: return "X86ISD::FST";
7661 case X86ISD::CALL: return "X86ISD::CALL";
7662 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7663 case X86ISD::BT: return "X86ISD::BT";
7664 case X86ISD::CMP: return "X86ISD::CMP";
7665 case X86ISD::COMI: return "X86ISD::COMI";
7666 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7667 case X86ISD::SETCC: return "X86ISD::SETCC";
7668 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7669 case X86ISD::CMOV: return "X86ISD::CMOV";
7670 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7671 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7672 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7673 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7674 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7675 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7676 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7677 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7678 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7679 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7680 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7681 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7682 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7683 case X86ISD::FMAX: return "X86ISD::FMAX";
7684 case X86ISD::FMIN: return "X86ISD::FMIN";
7685 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7686 case X86ISD::FRCP: return "X86ISD::FRCP";
7687 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7688 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7689 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7690 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7691 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7692 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7693 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7694 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7695 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7696 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7697 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7698 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7699 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7700 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7701 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7702 case X86ISD::VSHL: return "X86ISD::VSHL";
7703 case X86ISD::VSRL: return "X86ISD::VSRL";
7704 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7705 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7706 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7707 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7708 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7709 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7710 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7711 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7712 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7713 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7714 case X86ISD::ADD: return "X86ISD::ADD";
7715 case X86ISD::SUB: return "X86ISD::SUB";
7716 case X86ISD::SMUL: return "X86ISD::SMUL";
7717 case X86ISD::UMUL: return "X86ISD::UMUL";
7718 case X86ISD::INC: return "X86ISD::INC";
7719 case X86ISD::DEC: return "X86ISD::DEC";
7720 case X86ISD::OR: return "X86ISD::OR";
7721 case X86ISD::XOR: return "X86ISD::XOR";
7722 case X86ISD::AND: return "X86ISD::AND";
7723 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7724 case X86ISD::PTEST: return "X86ISD::PTEST";
7725 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7729 // isLegalAddressingMode - Return true if the addressing mode represented
7730 // by AM is legal for this target, for a load/store of the specified type.
7731 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7732 const Type *Ty) const {
7733 // X86 supports extremely general addressing modes.
7734 CodeModel::Model M = getTargetMachine().getCodeModel();
7736 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7737 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7742 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7744 // If a reference to this global requires an extra load, we can't fold it.
7745 if (isGlobalStubReference(GVFlags))
7748 // If BaseGV requires a register for the PIC base, we cannot also have a
7749 // BaseReg specified.
7750 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7753 // If lower 4G is not available, then we must use rip-relative addressing.
7754 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7764 // These scales always work.
7769 // These scales are formed with basereg+scalereg. Only accept if there is
7774 default: // Other stuff never works.
7782 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7783 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
7785 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7786 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7787 if (NumBits1 <= NumBits2)
7789 return Subtarget->is64Bit() || NumBits1 < 64;
7792 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7793 if (!VT1.isInteger() || !VT2.isInteger())
7795 unsigned NumBits1 = VT1.getSizeInBits();
7796 unsigned NumBits2 = VT2.getSizeInBits();
7797 if (NumBits1 <= NumBits2)
7799 return Subtarget->is64Bit() || NumBits1 < 64;
7802 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7803 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7804 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
7807 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7808 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7809 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7812 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7813 // i16 instructions are longer (0x66 prefix) and potentially slower.
7814 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7817 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7818 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7819 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7820 /// are assumed to be legal.
7822 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7824 // Only do shuffles on 128-bit vector types for now.
7825 if (VT.getSizeInBits() == 64)
7828 // FIXME: pshufb, blends, shifts.
7829 return (VT.getVectorNumElements() == 2 ||
7830 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7831 isMOVLMask(M, VT) ||
7832 isSHUFPMask(M, VT) ||
7833 isPSHUFDMask(M, VT) ||
7834 isPSHUFHWMask(M, VT) ||
7835 isPSHUFLWMask(M, VT) ||
7836 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7837 isUNPCKLMask(M, VT) ||
7838 isUNPCKHMask(M, VT) ||
7839 isUNPCKL_v_undef_Mask(M, VT) ||
7840 isUNPCKH_v_undef_Mask(M, VT));
7844 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7846 unsigned NumElts = VT.getVectorNumElements();
7847 // FIXME: This collection of masks seems suspect.
7850 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7851 return (isMOVLMask(Mask, VT) ||
7852 isCommutedMOVLMask(Mask, VT, true) ||
7853 isSHUFPMask(Mask, VT) ||
7854 isCommutedSHUFPMask(Mask, VT));
7859 //===----------------------------------------------------------------------===//
7860 // X86 Scheduler Hooks
7861 //===----------------------------------------------------------------------===//
7863 // private utility function
7865 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7866 MachineBasicBlock *MBB,
7874 TargetRegisterClass *RC,
7875 bool invSrc) const {
7876 // For the atomic bitwise operator, we generate
7879 // ld t1 = [bitinstr.addr]
7880 // op t2 = t1, [bitinstr.val]
7882 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7884 // fallthrough -->nextMBB
7885 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7886 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7887 MachineFunction::iterator MBBIter = MBB;
7890 /// First build the CFG
7891 MachineFunction *F = MBB->getParent();
7892 MachineBasicBlock *thisMBB = MBB;
7893 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7894 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7895 F->insert(MBBIter, newMBB);
7896 F->insert(MBBIter, nextMBB);
7898 // Move all successors to thisMBB to nextMBB
7899 nextMBB->transferSuccessors(thisMBB);
7901 // Update thisMBB to fall through to newMBB
7902 thisMBB->addSuccessor(newMBB);
7904 // newMBB jumps to itself and fall through to nextMBB
7905 newMBB->addSuccessor(nextMBB);
7906 newMBB->addSuccessor(newMBB);
7908 // Insert instructions into newMBB based on incoming instruction
7909 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7910 "unexpected number of operands");
7911 DebugLoc dl = bInstr->getDebugLoc();
7912 MachineOperand& destOper = bInstr->getOperand(0);
7913 MachineOperand* argOpers[2 + X86AddrNumOperands];
7914 int numArgs = bInstr->getNumOperands() - 1;
7915 for (int i=0; i < numArgs; ++i)
7916 argOpers[i] = &bInstr->getOperand(i+1);
7918 // x86 address has 4 operands: base, index, scale, and displacement
7919 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7920 int valArgIndx = lastAddrIndx + 1;
7922 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7923 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7924 for (int i=0; i <= lastAddrIndx; ++i)
7925 (*MIB).addOperand(*argOpers[i]);
7927 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7929 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7934 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7935 assert((argOpers[valArgIndx]->isReg() ||
7936 argOpers[valArgIndx]->isImm()) &&
7938 if (argOpers[valArgIndx]->isReg())
7939 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7941 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7943 (*MIB).addOperand(*argOpers[valArgIndx]);
7945 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7948 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7949 for (int i=0; i <= lastAddrIndx; ++i)
7950 (*MIB).addOperand(*argOpers[i]);
7952 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7953 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7954 bInstr->memoperands_end());
7956 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7960 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
7962 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7966 // private utility function: 64 bit atomics on 32 bit host.
7968 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7969 MachineBasicBlock *MBB,
7974 bool invSrc) const {
7975 // For the atomic bitwise operator, we generate
7976 // thisMBB (instructions are in pairs, except cmpxchg8b)
7977 // ld t1,t2 = [bitinstr.addr]
7979 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7980 // op t5, t6 <- out1, out2, [bitinstr.val]
7981 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7982 // mov ECX, EBX <- t5, t6
7983 // mov EAX, EDX <- t1, t2
7984 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7985 // mov t3, t4 <- EAX, EDX
7987 // result in out1, out2
7988 // fallthrough -->nextMBB
7990 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7991 const unsigned LoadOpc = X86::MOV32rm;
7992 const unsigned copyOpc = X86::MOV32rr;
7993 const unsigned NotOpc = X86::NOT32r;
7994 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7995 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7996 MachineFunction::iterator MBBIter = MBB;
7999 /// First build the CFG
8000 MachineFunction *F = MBB->getParent();
8001 MachineBasicBlock *thisMBB = MBB;
8002 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8003 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8004 F->insert(MBBIter, newMBB);
8005 F->insert(MBBIter, nextMBB);
8007 // Move all successors to thisMBB to nextMBB
8008 nextMBB->transferSuccessors(thisMBB);
8010 // Update thisMBB to fall through to newMBB
8011 thisMBB->addSuccessor(newMBB);
8013 // newMBB jumps to itself and fall through to nextMBB
8014 newMBB->addSuccessor(nextMBB);
8015 newMBB->addSuccessor(newMBB);
8017 DebugLoc dl = bInstr->getDebugLoc();
8018 // Insert instructions into newMBB based on incoming instruction
8019 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
8020 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
8021 "unexpected number of operands");
8022 MachineOperand& dest1Oper = bInstr->getOperand(0);
8023 MachineOperand& dest2Oper = bInstr->getOperand(1);
8024 MachineOperand* argOpers[2 + X86AddrNumOperands];
8025 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
8026 argOpers[i] = &bInstr->getOperand(i+2);
8028 // x86 address has 5 operands: base, index, scale, displacement, and segment.
8029 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8031 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8032 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8033 for (int i=0; i <= lastAddrIndx; ++i)
8034 (*MIB).addOperand(*argOpers[i]);
8035 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8036 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
8037 // add 4 to displacement.
8038 for (int i=0; i <= lastAddrIndx-2; ++i)
8039 (*MIB).addOperand(*argOpers[i]);
8040 MachineOperand newOp3 = *(argOpers[3]);
8042 newOp3.setImm(newOp3.getImm()+4);
8044 newOp3.setOffset(newOp3.getOffset()+4);
8045 (*MIB).addOperand(newOp3);
8046 (*MIB).addOperand(*argOpers[lastAddrIndx]);
8048 // t3/4 are defined later, at the bottom of the loop
8049 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8050 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8051 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8052 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8053 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8054 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8056 // The subsequent operations should be using the destination registers of
8057 //the PHI instructions.
8059 t1 = F->getRegInfo().createVirtualRegister(RC);
8060 t2 = F->getRegInfo().createVirtualRegister(RC);
8061 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8062 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8064 t1 = dest1Oper.getReg();
8065 t2 = dest2Oper.getReg();
8068 int valArgIndx = lastAddrIndx + 1;
8069 assert((argOpers[valArgIndx]->isReg() ||
8070 argOpers[valArgIndx]->isImm()) &&
8072 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8073 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8074 if (argOpers[valArgIndx]->isReg())
8075 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8077 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8078 if (regOpcL != X86::MOV32rr)
8080 (*MIB).addOperand(*argOpers[valArgIndx]);
8081 assert(argOpers[valArgIndx + 1]->isReg() ==
8082 argOpers[valArgIndx]->isReg());
8083 assert(argOpers[valArgIndx + 1]->isImm() ==
8084 argOpers[valArgIndx]->isImm());
8085 if (argOpers[valArgIndx + 1]->isReg())
8086 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8088 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8089 if (regOpcH != X86::MOV32rr)
8091 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8093 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
8095 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
8098 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
8100 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
8103 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8104 for (int i=0; i <= lastAddrIndx; ++i)
8105 (*MIB).addOperand(*argOpers[i]);
8107 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8108 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8109 bInstr->memoperands_end());
8111 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
8112 MIB.addReg(X86::EAX);
8113 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
8114 MIB.addReg(X86::EDX);
8117 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8119 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
8123 // private utility function
8125 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8126 MachineBasicBlock *MBB,
8127 unsigned cmovOpc) const {
8128 // For the atomic min/max operator, we generate
8131 // ld t1 = [min/max.addr]
8132 // mov t2 = [min/max.val]
8134 // cmov[cond] t2 = t1
8136 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8138 // fallthrough -->nextMBB
8140 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8141 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8142 MachineFunction::iterator MBBIter = MBB;
8145 /// First build the CFG
8146 MachineFunction *F = MBB->getParent();
8147 MachineBasicBlock *thisMBB = MBB;
8148 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8149 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8150 F->insert(MBBIter, newMBB);
8151 F->insert(MBBIter, nextMBB);
8153 // Move all successors of thisMBB to nextMBB
8154 nextMBB->transferSuccessors(thisMBB);
8156 // Update thisMBB to fall through to newMBB
8157 thisMBB->addSuccessor(newMBB);
8159 // newMBB jumps to newMBB and fall through to nextMBB
8160 newMBB->addSuccessor(nextMBB);
8161 newMBB->addSuccessor(newMBB);
8163 DebugLoc dl = mInstr->getDebugLoc();
8164 // Insert instructions into newMBB based on incoming instruction
8165 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
8166 "unexpected number of operands");
8167 MachineOperand& destOper = mInstr->getOperand(0);
8168 MachineOperand* argOpers[2 + X86AddrNumOperands];
8169 int numArgs = mInstr->getNumOperands() - 1;
8170 for (int i=0; i < numArgs; ++i)
8171 argOpers[i] = &mInstr->getOperand(i+1);
8173 // x86 address has 4 operands: base, index, scale, and displacement
8174 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8175 int valArgIndx = lastAddrIndx + 1;
8177 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8178 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8179 for (int i=0; i <= lastAddrIndx; ++i)
8180 (*MIB).addOperand(*argOpers[i]);
8182 // We only support register and immediate values
8183 assert((argOpers[valArgIndx]->isReg() ||
8184 argOpers[valArgIndx]->isImm()) &&
8187 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8188 if (argOpers[valArgIndx]->isReg())
8189 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8191 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8192 (*MIB).addOperand(*argOpers[valArgIndx]);
8194 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
8197 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8202 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8203 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8207 // Cmp and exchange if none has modified the memory location
8208 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8209 for (int i=0; i <= lastAddrIndx; ++i)
8210 (*MIB).addOperand(*argOpers[i]);
8212 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8213 (*MIB).setMemRefs(mInstr->memoperands_begin(),
8214 mInstr->memoperands_end());
8216 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
8217 MIB.addReg(X86::EAX);
8220 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8222 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
8226 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8227 // all of this code can be replaced with that in the .td file.
8229 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8230 unsigned numArgs, bool memArg) const {
8232 MachineFunction *F = BB->getParent();
8233 DebugLoc dl = MI->getDebugLoc();
8234 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8238 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8240 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8242 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8244 for (unsigned i = 0; i < numArgs; ++i) {
8245 MachineOperand &Op = MI->getOperand(i+1);
8247 if (!(Op.isReg() && Op.isImplicit()))
8251 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8254 F->DeleteMachineInstr(MI);
8260 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8262 MachineBasicBlock *MBB) const {
8263 // Emit code to save XMM registers to the stack. The ABI says that the
8264 // number of registers to save is given in %al, so it's theoretically
8265 // possible to do an indirect jump trick to avoid saving all of them,
8266 // however this code takes a simpler approach and just executes all
8267 // of the stores if %al is non-zero. It's less code, and it's probably
8268 // easier on the hardware branch predictor, and stores aren't all that
8269 // expensive anyway.
8271 // Create the new basic blocks. One block contains all the XMM stores,
8272 // and one block is the final destination regardless of whether any
8273 // stores were performed.
8274 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8275 MachineFunction *F = MBB->getParent();
8276 MachineFunction::iterator MBBIter = MBB;
8278 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8279 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8280 F->insert(MBBIter, XMMSaveMBB);
8281 F->insert(MBBIter, EndMBB);
8284 // Move any original successors of MBB to the end block.
8285 EndMBB->transferSuccessors(MBB);
8286 // The original block will now fall through to the XMM save block.
8287 MBB->addSuccessor(XMMSaveMBB);
8288 // The XMMSaveMBB will fall through to the end block.
8289 XMMSaveMBB->addSuccessor(EndMBB);
8291 // Now add the instructions.
8292 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8293 DebugLoc DL = MI->getDebugLoc();
8295 unsigned CountReg = MI->getOperand(0).getReg();
8296 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8297 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8299 if (!Subtarget->isTargetWin64()) {
8300 // If %al is 0, branch around the XMM save block.
8301 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8302 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
8303 MBB->addSuccessor(EndMBB);
8306 // In the XMM save block, save all the XMM argument registers.
8307 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8308 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8309 MachineMemOperand *MMO =
8310 F->getMachineMemOperand(
8311 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8312 MachineMemOperand::MOStore, Offset,
8313 /*Size=*/16, /*Align=*/16);
8314 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8315 .addFrameIndex(RegSaveFrameIndex)
8316 .addImm(/*Scale=*/1)
8317 .addReg(/*IndexReg=*/0)
8318 .addImm(/*Disp=*/Offset)
8319 .addReg(/*Segment=*/0)
8320 .addReg(MI->getOperand(i).getReg())
8321 .addMemOperand(MMO);
8324 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8330 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8331 MachineBasicBlock *BB,
8332 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8333 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8334 DebugLoc DL = MI->getDebugLoc();
8336 // To "insert" a SELECT_CC instruction, we actually have to insert the
8337 // diamond control-flow pattern. The incoming instruction knows the
8338 // destination vreg to set, the condition code register to branch on, the
8339 // true/false values to select between, and a branch opcode to use.
8340 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8341 MachineFunction::iterator It = BB;
8347 // cmpTY ccX, r1, r2
8349 // fallthrough --> copy0MBB
8350 MachineBasicBlock *thisMBB = BB;
8351 MachineFunction *F = BB->getParent();
8352 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8353 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8355 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8356 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8357 F->insert(It, copy0MBB);
8358 F->insert(It, sinkMBB);
8359 // Update machine-CFG edges by first adding all successors of the current
8360 // block to the new block which will contain the Phi node for the select.
8361 // Also inform sdisel of the edge changes.
8362 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8363 E = BB->succ_end(); I != E; ++I) {
8364 EM->insert(std::make_pair(*I, sinkMBB));
8365 sinkMBB->addSuccessor(*I);
8367 // Next, remove all successors of the current block, and add the true
8368 // and fallthrough blocks as its successors.
8369 while (!BB->succ_empty())
8370 BB->removeSuccessor(BB->succ_begin());
8371 // Add the true and fallthrough blocks as its successors.
8372 BB->addSuccessor(copy0MBB);
8373 BB->addSuccessor(sinkMBB);
8376 // %FalseValue = ...
8377 // # fallthrough to sinkMBB
8380 // Update machine-CFG edges
8381 BB->addSuccessor(sinkMBB);
8384 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8387 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8388 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8389 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8391 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8397 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8398 MachineBasicBlock *BB,
8399 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8400 switch (MI->getOpcode()) {
8401 default: assert(false && "Unexpected instr type to insert");
8403 case X86::CMOV_V1I64:
8404 case X86::CMOV_FR32:
8405 case X86::CMOV_FR64:
8406 case X86::CMOV_V4F32:
8407 case X86::CMOV_V2F64:
8408 case X86::CMOV_V2I64:
8409 return EmitLoweredSelect(MI, BB, EM);
8411 case X86::FP32_TO_INT16_IN_MEM:
8412 case X86::FP32_TO_INT32_IN_MEM:
8413 case X86::FP32_TO_INT64_IN_MEM:
8414 case X86::FP64_TO_INT16_IN_MEM:
8415 case X86::FP64_TO_INT32_IN_MEM:
8416 case X86::FP64_TO_INT64_IN_MEM:
8417 case X86::FP80_TO_INT16_IN_MEM:
8418 case X86::FP80_TO_INT32_IN_MEM:
8419 case X86::FP80_TO_INT64_IN_MEM: {
8420 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8421 DebugLoc DL = MI->getDebugLoc();
8423 // Change the floating point control register to use "round towards zero"
8424 // mode when truncating to an integer value.
8425 MachineFunction *F = BB->getParent();
8426 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8427 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8429 // Load the old value of the high byte of the control word...
8431 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8432 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8435 // Set the high part to be round to zero...
8436 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8439 // Reload the modified control word now...
8440 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8442 // Restore the memory image of control word to original value
8443 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8446 // Get the X86 opcode to use.
8448 switch (MI->getOpcode()) {
8449 default: llvm_unreachable("illegal opcode!");
8450 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8451 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8452 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8453 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8454 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8455 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8456 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8457 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8458 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8462 MachineOperand &Op = MI->getOperand(0);
8464 AM.BaseType = X86AddressMode::RegBase;
8465 AM.Base.Reg = Op.getReg();
8467 AM.BaseType = X86AddressMode::FrameIndexBase;
8468 AM.Base.FrameIndex = Op.getIndex();
8470 Op = MI->getOperand(1);
8472 AM.Scale = Op.getImm();
8473 Op = MI->getOperand(2);
8475 AM.IndexReg = Op.getImm();
8476 Op = MI->getOperand(3);
8477 if (Op.isGlobal()) {
8478 AM.GV = Op.getGlobal();
8480 AM.Disp = Op.getImm();
8482 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8483 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8485 // Reload the original control word now.
8486 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8488 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8491 // String/text processing lowering.
8492 case X86::PCMPISTRM128REG:
8493 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8494 case X86::PCMPISTRM128MEM:
8495 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8496 case X86::PCMPESTRM128REG:
8497 return EmitPCMP(MI, BB, 5, false /* in mem */);
8498 case X86::PCMPESTRM128MEM:
8499 return EmitPCMP(MI, BB, 5, true /* in mem */);
8502 case X86::ATOMAND32:
8503 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8504 X86::AND32ri, X86::MOV32rm,
8505 X86::LCMPXCHG32, X86::MOV32rr,
8506 X86::NOT32r, X86::EAX,
8507 X86::GR32RegisterClass);
8509 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8510 X86::OR32ri, X86::MOV32rm,
8511 X86::LCMPXCHG32, X86::MOV32rr,
8512 X86::NOT32r, X86::EAX,
8513 X86::GR32RegisterClass);
8514 case X86::ATOMXOR32:
8515 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8516 X86::XOR32ri, X86::MOV32rm,
8517 X86::LCMPXCHG32, X86::MOV32rr,
8518 X86::NOT32r, X86::EAX,
8519 X86::GR32RegisterClass);
8520 case X86::ATOMNAND32:
8521 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8522 X86::AND32ri, X86::MOV32rm,
8523 X86::LCMPXCHG32, X86::MOV32rr,
8524 X86::NOT32r, X86::EAX,
8525 X86::GR32RegisterClass, true);
8526 case X86::ATOMMIN32:
8527 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8528 case X86::ATOMMAX32:
8529 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8530 case X86::ATOMUMIN32:
8531 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8532 case X86::ATOMUMAX32:
8533 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8535 case X86::ATOMAND16:
8536 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8537 X86::AND16ri, X86::MOV16rm,
8538 X86::LCMPXCHG16, X86::MOV16rr,
8539 X86::NOT16r, X86::AX,
8540 X86::GR16RegisterClass);
8542 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8543 X86::OR16ri, X86::MOV16rm,
8544 X86::LCMPXCHG16, X86::MOV16rr,
8545 X86::NOT16r, X86::AX,
8546 X86::GR16RegisterClass);
8547 case X86::ATOMXOR16:
8548 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8549 X86::XOR16ri, X86::MOV16rm,
8550 X86::LCMPXCHG16, X86::MOV16rr,
8551 X86::NOT16r, X86::AX,
8552 X86::GR16RegisterClass);
8553 case X86::ATOMNAND16:
8554 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8555 X86::AND16ri, X86::MOV16rm,
8556 X86::LCMPXCHG16, X86::MOV16rr,
8557 X86::NOT16r, X86::AX,
8558 X86::GR16RegisterClass, true);
8559 case X86::ATOMMIN16:
8560 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8561 case X86::ATOMMAX16:
8562 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8563 case X86::ATOMUMIN16:
8564 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8565 case X86::ATOMUMAX16:
8566 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8569 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8570 X86::AND8ri, X86::MOV8rm,
8571 X86::LCMPXCHG8, X86::MOV8rr,
8572 X86::NOT8r, X86::AL,
8573 X86::GR8RegisterClass);
8575 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8576 X86::OR8ri, X86::MOV8rm,
8577 X86::LCMPXCHG8, X86::MOV8rr,
8578 X86::NOT8r, X86::AL,
8579 X86::GR8RegisterClass);
8581 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8582 X86::XOR8ri, X86::MOV8rm,
8583 X86::LCMPXCHG8, X86::MOV8rr,
8584 X86::NOT8r, X86::AL,
8585 X86::GR8RegisterClass);
8586 case X86::ATOMNAND8:
8587 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8588 X86::AND8ri, X86::MOV8rm,
8589 X86::LCMPXCHG8, X86::MOV8rr,
8590 X86::NOT8r, X86::AL,
8591 X86::GR8RegisterClass, true);
8592 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8593 // This group is for 64-bit host.
8594 case X86::ATOMAND64:
8595 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8596 X86::AND64ri32, X86::MOV64rm,
8597 X86::LCMPXCHG64, X86::MOV64rr,
8598 X86::NOT64r, X86::RAX,
8599 X86::GR64RegisterClass);
8601 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8602 X86::OR64ri32, X86::MOV64rm,
8603 X86::LCMPXCHG64, X86::MOV64rr,
8604 X86::NOT64r, X86::RAX,
8605 X86::GR64RegisterClass);
8606 case X86::ATOMXOR64:
8607 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8608 X86::XOR64ri32, X86::MOV64rm,
8609 X86::LCMPXCHG64, X86::MOV64rr,
8610 X86::NOT64r, X86::RAX,
8611 X86::GR64RegisterClass);
8612 case X86::ATOMNAND64:
8613 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8614 X86::AND64ri32, X86::MOV64rm,
8615 X86::LCMPXCHG64, X86::MOV64rr,
8616 X86::NOT64r, X86::RAX,
8617 X86::GR64RegisterClass, true);
8618 case X86::ATOMMIN64:
8619 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8620 case X86::ATOMMAX64:
8621 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8622 case X86::ATOMUMIN64:
8623 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8624 case X86::ATOMUMAX64:
8625 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8627 // This group does 64-bit operations on a 32-bit host.
8628 case X86::ATOMAND6432:
8629 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8630 X86::AND32rr, X86::AND32rr,
8631 X86::AND32ri, X86::AND32ri,
8633 case X86::ATOMOR6432:
8634 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8635 X86::OR32rr, X86::OR32rr,
8636 X86::OR32ri, X86::OR32ri,
8638 case X86::ATOMXOR6432:
8639 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8640 X86::XOR32rr, X86::XOR32rr,
8641 X86::XOR32ri, X86::XOR32ri,
8643 case X86::ATOMNAND6432:
8644 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8645 X86::AND32rr, X86::AND32rr,
8646 X86::AND32ri, X86::AND32ri,
8648 case X86::ATOMADD6432:
8649 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8650 X86::ADD32rr, X86::ADC32rr,
8651 X86::ADD32ri, X86::ADC32ri,
8653 case X86::ATOMSUB6432:
8654 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8655 X86::SUB32rr, X86::SBB32rr,
8656 X86::SUB32ri, X86::SBB32ri,
8658 case X86::ATOMSWAP6432:
8659 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8660 X86::MOV32rr, X86::MOV32rr,
8661 X86::MOV32ri, X86::MOV32ri,
8663 case X86::VASTART_SAVE_XMM_REGS:
8664 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8668 //===----------------------------------------------------------------------===//
8669 // X86 Optimization Hooks
8670 //===----------------------------------------------------------------------===//
8672 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8676 const SelectionDAG &DAG,
8677 unsigned Depth) const {
8678 unsigned Opc = Op.getOpcode();
8679 assert((Opc >= ISD::BUILTIN_OP_END ||
8680 Opc == ISD::INTRINSIC_WO_CHAIN ||
8681 Opc == ISD::INTRINSIC_W_CHAIN ||
8682 Opc == ISD::INTRINSIC_VOID) &&
8683 "Should use MaskedValueIsZero if you don't know whether Op"
8684 " is a target node!");
8686 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8698 // These nodes' second result is a boolean.
8699 if (Op.getResNo() == 0)
8703 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8704 Mask.getBitWidth() - 1);
8709 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8710 /// node is a GlobalAddress + offset.
8711 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8712 GlobalValue* &GA, int64_t &Offset) const{
8713 if (N->getOpcode() == X86ISD::Wrapper) {
8714 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8715 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8716 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8720 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8723 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8724 EVT EltVT, LoadSDNode *&LDBase,
8725 unsigned &LastLoadedElt,
8726 SelectionDAG &DAG, MachineFrameInfo *MFI,
8727 const TargetLowering &TLI) {
8729 LastLoadedElt = -1U;
8730 for (unsigned i = 0; i < NumElems; ++i) {
8731 if (N->getMaskElt(i) < 0) {
8737 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8738 if (!Elt.getNode() ||
8739 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8742 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8744 LDBase = cast<LoadSDNode>(Elt.getNode());
8748 if (Elt.getOpcode() == ISD::UNDEF)
8751 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8752 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
8759 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8760 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8761 /// if the load addresses are consecutive, non-overlapping, and in the right
8762 /// order. In the case of v2i64, it will see if it can rewrite the
8763 /// shuffle to be an appropriate build vector so it can take advantage of
8764 // performBuildVectorCombine.
8765 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8766 const TargetLowering &TLI) {
8767 DebugLoc dl = N->getDebugLoc();
8768 EVT VT = N->getValueType(0);
8769 EVT EltVT = VT.getVectorElementType();
8770 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8771 unsigned NumElems = VT.getVectorNumElements();
8773 if (VT.getSizeInBits() != 128)
8776 // Try to combine a vector_shuffle into a 128-bit load.
8777 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8778 LoadSDNode *LD = NULL;
8779 unsigned LastLoadedElt;
8780 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8784 if (LastLoadedElt == NumElems - 1) {
8785 if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
8786 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8787 LD->getSrcValue(), LD->getSrcValueOffset(),
8788 LD->isVolatile(), LD->isNonTemporal(), 0);
8789 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8790 LD->getSrcValue(), LD->getSrcValueOffset(),
8791 LD->isVolatile(), LD->isNonTemporal(),
8792 LD->getAlignment());
8793 } else if (NumElems == 4 && LastLoadedElt == 1) {
8794 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8795 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8796 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8797 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8802 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8803 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8804 const X86Subtarget *Subtarget) {
8805 DebugLoc DL = N->getDebugLoc();
8806 SDValue Cond = N->getOperand(0);
8807 // Get the LHS/RHS of the select.
8808 SDValue LHS = N->getOperand(1);
8809 SDValue RHS = N->getOperand(2);
8811 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8812 // instructions have the peculiarity that if either operand is a NaN,
8813 // they chose what we call the RHS operand (and as such are not symmetric).
8814 // It happens that this matches the semantics of the common C idiom
8815 // x<y?x:y and related forms, so we can recognize these cases.
8816 if (Subtarget->hasSSE2() &&
8817 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8818 Cond.getOpcode() == ISD::SETCC) {
8819 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8821 unsigned Opcode = 0;
8822 // Check for x CC y ? x : y.
8823 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8827 // This can be a min if we can prove that at least one of the operands
8829 if (!FiniteOnlyFPMath()) {
8830 if (DAG.isKnownNeverNaN(RHS)) {
8831 // Put the potential NaN in the RHS so that SSE will preserve it.
8832 std::swap(LHS, RHS);
8833 } else if (!DAG.isKnownNeverNaN(LHS))
8836 Opcode = X86ISD::FMIN;
8839 // This can be a min if we can prove that at least one of the operands
8841 if (!FiniteOnlyFPMath()) {
8842 if (DAG.isKnownNeverNaN(LHS)) {
8843 // Put the potential NaN in the RHS so that SSE will preserve it.
8844 std::swap(LHS, RHS);
8845 } else if (!DAG.isKnownNeverNaN(RHS))
8848 Opcode = X86ISD::FMIN;
8851 // This can be a min, but if either operand is a NaN we need it to
8852 // preserve the original LHS.
8853 std::swap(LHS, RHS);
8857 Opcode = X86ISD::FMIN;
8861 // This can be a max if we can prove that at least one of the operands
8863 if (!FiniteOnlyFPMath()) {
8864 if (DAG.isKnownNeverNaN(LHS)) {
8865 // Put the potential NaN in the RHS so that SSE will preserve it.
8866 std::swap(LHS, RHS);
8867 } else if (!DAG.isKnownNeverNaN(RHS))
8870 Opcode = X86ISD::FMAX;
8873 // This can be a max if we can prove that at least one of the operands
8875 if (!FiniteOnlyFPMath()) {
8876 if (DAG.isKnownNeverNaN(RHS)) {
8877 // Put the potential NaN in the RHS so that SSE will preserve it.
8878 std::swap(LHS, RHS);
8879 } else if (!DAG.isKnownNeverNaN(LHS))
8882 Opcode = X86ISD::FMAX;
8885 // This can be a max, but if either operand is a NaN we need it to
8886 // preserve the original LHS.
8887 std::swap(LHS, RHS);
8891 Opcode = X86ISD::FMAX;
8894 // Check for x CC y ? y : x -- a min/max with reversed arms.
8895 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8899 // This can be a min if we can prove that at least one of the operands
8901 if (!FiniteOnlyFPMath()) {
8902 if (DAG.isKnownNeverNaN(RHS)) {
8903 // Put the potential NaN in the RHS so that SSE will preserve it.
8904 std::swap(LHS, RHS);
8905 } else if (!DAG.isKnownNeverNaN(LHS))
8908 Opcode = X86ISD::FMIN;
8911 // This can be a min if we can prove that at least one of the operands
8913 if (!FiniteOnlyFPMath()) {
8914 if (DAG.isKnownNeverNaN(LHS)) {
8915 // Put the potential NaN in the RHS so that SSE will preserve it.
8916 std::swap(LHS, RHS);
8917 } else if (!DAG.isKnownNeverNaN(RHS))
8920 Opcode = X86ISD::FMIN;
8923 // This can be a min, but if either operand is a NaN we need it to
8924 // preserve the original LHS.
8925 std::swap(LHS, RHS);
8929 Opcode = X86ISD::FMIN;
8933 // This can be a max if we can prove that at least one of the operands
8935 if (!FiniteOnlyFPMath()) {
8936 if (DAG.isKnownNeverNaN(LHS)) {
8937 // Put the potential NaN in the RHS so that SSE will preserve it.
8938 std::swap(LHS, RHS);
8939 } else if (!DAG.isKnownNeverNaN(RHS))
8942 Opcode = X86ISD::FMAX;
8945 // This can be a max if we can prove that at least one of the operands
8947 if (!FiniteOnlyFPMath()) {
8948 if (DAG.isKnownNeverNaN(RHS)) {
8949 // Put the potential NaN in the RHS so that SSE will preserve it.
8950 std::swap(LHS, RHS);
8951 } else if (!DAG.isKnownNeverNaN(LHS))
8954 Opcode = X86ISD::FMAX;
8957 // This can be a max, but if either operand is a NaN we need it to
8958 // preserve the original LHS.
8959 std::swap(LHS, RHS);
8963 Opcode = X86ISD::FMAX;
8969 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8972 // If this is a select between two integer constants, try to do some
8974 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8975 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8976 // Don't do this for crazy integer types.
8977 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8978 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8979 // so that TrueC (the true value) is larger than FalseC.
8980 bool NeedsCondInvert = false;
8982 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8983 // Efficiently invertible.
8984 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8985 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8986 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8987 NeedsCondInvert = true;
8988 std::swap(TrueC, FalseC);
8991 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8992 if (FalseC->getAPIntValue() == 0 &&
8993 TrueC->getAPIntValue().isPowerOf2()) {
8994 if (NeedsCondInvert) // Invert the condition if needed.
8995 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8996 DAG.getConstant(1, Cond.getValueType()));
8998 // Zero extend the condition if needed.
8999 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
9001 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9002 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
9003 DAG.getConstant(ShAmt, MVT::i8));
9006 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
9007 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9008 if (NeedsCondInvert) // Invert the condition if needed.
9009 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9010 DAG.getConstant(1, Cond.getValueType()));
9012 // Zero extend the condition if needed.
9013 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9014 FalseC->getValueType(0), Cond);
9015 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9016 SDValue(FalseC, 0));
9019 // Optimize cases that will turn into an LEA instruction. This requires
9020 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9021 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9022 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9023 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9025 bool isFastMultiplier = false;
9027 switch ((unsigned char)Diff) {
9029 case 1: // result = add base, cond
9030 case 2: // result = lea base( , cond*2)
9031 case 3: // result = lea base(cond, cond*2)
9032 case 4: // result = lea base( , cond*4)
9033 case 5: // result = lea base(cond, cond*4)
9034 case 8: // result = lea base( , cond*8)
9035 case 9: // result = lea base(cond, cond*8)
9036 isFastMultiplier = true;
9041 if (isFastMultiplier) {
9042 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9043 if (NeedsCondInvert) // Invert the condition if needed.
9044 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9045 DAG.getConstant(1, Cond.getValueType()));
9047 // Zero extend the condition if needed.
9048 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9050 // Scale the condition by the difference.
9052 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9053 DAG.getConstant(Diff, Cond.getValueType()));
9055 // Add the base if non-zero.
9056 if (FalseC->getAPIntValue() != 0)
9057 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9058 SDValue(FalseC, 0));
9068 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9069 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9070 TargetLowering::DAGCombinerInfo &DCI) {
9071 DebugLoc DL = N->getDebugLoc();
9073 // If the flag operand isn't dead, don't touch this CMOV.
9074 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9077 // If this is a select between two integer constants, try to do some
9078 // optimizations. Note that the operands are ordered the opposite of SELECT
9080 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9081 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9082 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9083 // larger than FalseC (the false value).
9084 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9086 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9087 CC = X86::GetOppositeBranchCondition(CC);
9088 std::swap(TrueC, FalseC);
9091 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
9092 // This is efficient for any integer data type (including i8/i16) and
9094 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9095 SDValue Cond = N->getOperand(3);
9096 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9097 DAG.getConstant(CC, MVT::i8), Cond);
9099 // Zero extend the condition if needed.
9100 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9102 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9103 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9104 DAG.getConstant(ShAmt, MVT::i8));
9105 if (N->getNumValues() == 2) // Dead flag value?
9106 return DCI.CombineTo(N, Cond, SDValue());
9110 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
9111 // for any integer data type, including i8/i16.
9112 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9113 SDValue Cond = N->getOperand(3);
9114 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9115 DAG.getConstant(CC, MVT::i8), Cond);
9117 // Zero extend the condition if needed.
9118 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9119 FalseC->getValueType(0), Cond);
9120 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9121 SDValue(FalseC, 0));
9123 if (N->getNumValues() == 2) // Dead flag value?
9124 return DCI.CombineTo(N, Cond, SDValue());
9128 // Optimize cases that will turn into an LEA instruction. This requires
9129 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9130 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9131 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9132 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9134 bool isFastMultiplier = false;
9136 switch ((unsigned char)Diff) {
9138 case 1: // result = add base, cond
9139 case 2: // result = lea base( , cond*2)
9140 case 3: // result = lea base(cond, cond*2)
9141 case 4: // result = lea base( , cond*4)
9142 case 5: // result = lea base(cond, cond*4)
9143 case 8: // result = lea base( , cond*8)
9144 case 9: // result = lea base(cond, cond*8)
9145 isFastMultiplier = true;
9150 if (isFastMultiplier) {
9151 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9152 SDValue Cond = N->getOperand(3);
9153 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9154 DAG.getConstant(CC, MVT::i8), Cond);
9155 // Zero extend the condition if needed.
9156 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9158 // Scale the condition by the difference.
9160 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9161 DAG.getConstant(Diff, Cond.getValueType()));
9163 // Add the base if non-zero.
9164 if (FalseC->getAPIntValue() != 0)
9165 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9166 SDValue(FalseC, 0));
9167 if (N->getNumValues() == 2) // Dead flag value?
9168 return DCI.CombineTo(N, Cond, SDValue());
9177 /// PerformANDCombine - Look for SSE and instructions of this form:
9178 /// (and x, (build_vector c1,c2,c3,c4)). If there exists a use of a build_vector
9179 /// that's the bitwise complement of the mask, then transform the node to
9180 /// (and (xor x, (build_vector -1,-1,-1,-1)), (build_vector ~c1,~c2,~c3,~c4)).
9181 static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG,
9182 TargetLowering::DAGCombinerInfo &DCI) {
9183 EVT VT = N->getValueType(0);
9184 if (!VT.isVector() || !VT.isInteger())
9187 SDValue N0 = N->getOperand(0);
9188 SDValue N1 = N->getOperand(1);
9189 if (N0.getOpcode() == ISD::XOR || !N1.hasOneUse())
9192 if (N1.getOpcode() == ISD::BUILD_VECTOR) {
9193 unsigned NumElts = VT.getVectorNumElements();
9194 EVT EltVT = VT.getVectorElementType();
9195 SmallVector<SDValue, 8> Mask;
9196 Mask.reserve(NumElts);
9197 for (unsigned i = 0; i != NumElts; ++i) {
9198 SDValue Arg = N1.getOperand(i);
9199 if (Arg.getOpcode() == ISD::UNDEF) {
9200 Mask.push_back(Arg);
9203 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Arg);
9204 if (!C) return SDValue();
9205 Mask.push_back(DAG.getConstant(~C->getAPIntValue(), EltVT));
9207 N1 = DAG.getNode(ISD::BUILD_VECTOR, N1.getDebugLoc(), VT,
9209 if (!N1.use_empty()) {
9210 unsigned Bits = EltVT.getSizeInBits();
9212 for (unsigned i = 0; i != NumElts; ++i)
9213 Mask.push_back(DAG.getConstant(APInt::getAllOnesValue(Bits), EltVT));
9214 SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
9215 VT, &Mask[0], NumElts);
9216 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9217 DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
9225 /// PerformMulCombine - Optimize a single multiply with constant into two
9226 /// in order to implement it with two cheaper instructions, e.g.
9227 /// LEA + SHL, LEA + LEA.
9228 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9229 TargetLowering::DAGCombinerInfo &DCI) {
9230 if (DAG.getMachineFunction().
9231 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
9234 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9237 EVT VT = N->getValueType(0);
9241 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9244 uint64_t MulAmt = C->getZExtValue();
9245 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9248 uint64_t MulAmt1 = 0;
9249 uint64_t MulAmt2 = 0;
9250 if ((MulAmt % 9) == 0) {
9252 MulAmt2 = MulAmt / 9;
9253 } else if ((MulAmt % 5) == 0) {
9255 MulAmt2 = MulAmt / 5;
9256 } else if ((MulAmt % 3) == 0) {
9258 MulAmt2 = MulAmt / 3;
9261 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9262 DebugLoc DL = N->getDebugLoc();
9264 if (isPowerOf2_64(MulAmt2) &&
9265 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9266 // If second multiplifer is pow2, issue it first. We want the multiply by
9267 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9269 std::swap(MulAmt1, MulAmt2);
9272 if (isPowerOf2_64(MulAmt1))
9273 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9274 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9276 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9277 DAG.getConstant(MulAmt1, VT));
9279 if (isPowerOf2_64(MulAmt2))
9280 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9281 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9283 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9284 DAG.getConstant(MulAmt2, VT));
9286 // Do not add new nodes to DAG combiner worklist.
9287 DCI.CombineTo(N, NewMul, false);
9292 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9293 SDValue N0 = N->getOperand(0);
9294 SDValue N1 = N->getOperand(1);
9295 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9296 EVT VT = N0.getValueType();
9298 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9299 // since the result of setcc_c is all zero's or all ones.
9300 if (N1C && N0.getOpcode() == ISD::AND &&
9301 N0.getOperand(1).getOpcode() == ISD::Constant) {
9302 SDValue N00 = N0.getOperand(0);
9303 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9304 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9305 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9306 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9307 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9308 APInt ShAmt = N1C->getAPIntValue();
9309 Mask = Mask.shl(ShAmt);
9311 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9312 N00, DAG.getConstant(Mask, VT));
9319 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9321 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9322 const X86Subtarget *Subtarget) {
9323 EVT VT = N->getValueType(0);
9324 if (!VT.isVector() && VT.isInteger() &&
9325 N->getOpcode() == ISD::SHL)
9326 return PerformSHLCombine(N, DAG);
9328 // On X86 with SSE2 support, we can transform this to a vector shift if
9329 // all elements are shifted by the same amount. We can't do this in legalize
9330 // because the a constant vector is typically transformed to a constant pool
9331 // so we have no knowledge of the shift amount.
9332 if (!Subtarget->hasSSE2())
9335 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9338 SDValue ShAmtOp = N->getOperand(1);
9339 EVT EltVT = VT.getVectorElementType();
9340 DebugLoc DL = N->getDebugLoc();
9341 SDValue BaseShAmt = SDValue();
9342 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9343 unsigned NumElts = VT.getVectorNumElements();
9345 for (; i != NumElts; ++i) {
9346 SDValue Arg = ShAmtOp.getOperand(i);
9347 if (Arg.getOpcode() == ISD::UNDEF) continue;
9351 for (; i != NumElts; ++i) {
9352 SDValue Arg = ShAmtOp.getOperand(i);
9353 if (Arg.getOpcode() == ISD::UNDEF) continue;
9354 if (Arg != BaseShAmt) {
9358 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9359 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9360 SDValue InVec = ShAmtOp.getOperand(0);
9361 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9362 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9364 for (; i != NumElts; ++i) {
9365 SDValue Arg = InVec.getOperand(i);
9366 if (Arg.getOpcode() == ISD::UNDEF) continue;
9370 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9371 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9372 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9373 if (C->getZExtValue() == SplatIdx)
9374 BaseShAmt = InVec.getOperand(1);
9377 if (BaseShAmt.getNode() == 0)
9378 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9379 DAG.getIntPtrConstant(0));
9383 // The shift amount is an i32.
9384 if (EltVT.bitsGT(MVT::i32))
9385 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9386 else if (EltVT.bitsLT(MVT::i32))
9387 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9389 // The shift amount is identical so we can do a vector shift.
9390 SDValue ValOp = N->getOperand(0);
9391 switch (N->getOpcode()) {
9393 llvm_unreachable("Unknown shift opcode!");
9396 if (VT == MVT::v2i64)
9397 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9398 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9400 if (VT == MVT::v4i32)
9401 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9402 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9404 if (VT == MVT::v8i16)
9405 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9406 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9410 if (VT == MVT::v4i32)
9411 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9412 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9414 if (VT == MVT::v8i16)
9415 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9416 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9420 if (VT == MVT::v2i64)
9421 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9422 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9424 if (VT == MVT::v4i32)
9425 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9426 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9428 if (VT == MVT::v8i16)
9429 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9430 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9437 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9438 const X86Subtarget *Subtarget) {
9439 EVT VT = N->getValueType(0);
9440 if (VT != MVT::i64 || !Subtarget->is64Bit())
9443 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9444 SDValue N0 = N->getOperand(0);
9445 SDValue N1 = N->getOperand(1);
9446 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9448 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9451 SDValue ShAmt0 = N0.getOperand(1);
9452 if (ShAmt0.getValueType() != MVT::i8)
9454 SDValue ShAmt1 = N1.getOperand(1);
9455 if (ShAmt1.getValueType() != MVT::i8)
9457 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9458 ShAmt0 = ShAmt0.getOperand(0);
9459 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9460 ShAmt1 = ShAmt1.getOperand(0);
9462 DebugLoc DL = N->getDebugLoc();
9463 unsigned Opc = X86ISD::SHLD;
9464 SDValue Op0 = N0.getOperand(0);
9465 SDValue Op1 = N1.getOperand(0);
9466 if (ShAmt0.getOpcode() == ISD::SUB) {
9468 std::swap(Op0, Op1);
9469 std::swap(ShAmt0, ShAmt1);
9472 if (ShAmt1.getOpcode() == ISD::SUB) {
9473 SDValue Sum = ShAmt1.getOperand(0);
9474 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9475 if (SumC->getSExtValue() == 64 &&
9476 ShAmt1.getOperand(1) == ShAmt0)
9477 return DAG.getNode(Opc, DL, VT,
9479 DAG.getNode(ISD::TRUNCATE, DL,
9482 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9483 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9485 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64)
9486 return DAG.getNode(Opc, DL, VT,
9487 N0.getOperand(0), N1.getOperand(0),
9488 DAG.getNode(ISD::TRUNCATE, DL,
9495 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9496 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9497 const X86Subtarget *Subtarget) {
9498 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9499 // the FP state in cases where an emms may be missing.
9500 // A preferable solution to the general problem is to figure out the right
9501 // places to insert EMMS. This qualifies as a quick hack.
9503 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9504 StoreSDNode *St = cast<StoreSDNode>(N);
9505 EVT VT = St->getValue().getValueType();
9506 if (VT.getSizeInBits() != 64)
9509 const Function *F = DAG.getMachineFunction().getFunction();
9510 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9511 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9512 && Subtarget->hasSSE2();
9513 if ((VT.isVector() ||
9514 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9515 isa<LoadSDNode>(St->getValue()) &&
9516 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9517 St->getChain().hasOneUse() && !St->isVolatile()) {
9518 SDNode* LdVal = St->getValue().getNode();
9520 int TokenFactorIndex = -1;
9521 SmallVector<SDValue, 8> Ops;
9522 SDNode* ChainVal = St->getChain().getNode();
9523 // Must be a store of a load. We currently handle two cases: the load
9524 // is a direct child, and it's under an intervening TokenFactor. It is
9525 // possible to dig deeper under nested TokenFactors.
9526 if (ChainVal == LdVal)
9527 Ld = cast<LoadSDNode>(St->getChain());
9528 else if (St->getValue().hasOneUse() &&
9529 ChainVal->getOpcode() == ISD::TokenFactor) {
9530 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9531 if (ChainVal->getOperand(i).getNode() == LdVal) {
9532 TokenFactorIndex = i;
9533 Ld = cast<LoadSDNode>(St->getValue());
9535 Ops.push_back(ChainVal->getOperand(i));
9539 if (!Ld || !ISD::isNormalLoad(Ld))
9542 // If this is not the MMX case, i.e. we are just turning i64 load/store
9543 // into f64 load/store, avoid the transformation if there are multiple
9544 // uses of the loaded value.
9545 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9548 DebugLoc LdDL = Ld->getDebugLoc();
9549 DebugLoc StDL = N->getDebugLoc();
9550 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9551 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9553 if (Subtarget->is64Bit() || F64IsLegal) {
9554 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9555 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9556 Ld->getBasePtr(), Ld->getSrcValue(),
9557 Ld->getSrcValueOffset(), Ld->isVolatile(),
9558 Ld->isNonTemporal(), Ld->getAlignment());
9559 SDValue NewChain = NewLd.getValue(1);
9560 if (TokenFactorIndex != -1) {
9561 Ops.push_back(NewChain);
9562 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9565 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9566 St->getSrcValue(), St->getSrcValueOffset(),
9567 St->isVolatile(), St->isNonTemporal(),
9568 St->getAlignment());
9571 // Otherwise, lower to two pairs of 32-bit loads / stores.
9572 SDValue LoAddr = Ld->getBasePtr();
9573 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9574 DAG.getConstant(4, MVT::i32));
9576 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9577 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9578 Ld->isVolatile(), Ld->isNonTemporal(),
9579 Ld->getAlignment());
9580 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9581 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9582 Ld->isVolatile(), Ld->isNonTemporal(),
9583 MinAlign(Ld->getAlignment(), 4));
9585 SDValue NewChain = LoLd.getValue(1);
9586 if (TokenFactorIndex != -1) {
9587 Ops.push_back(LoLd);
9588 Ops.push_back(HiLd);
9589 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9593 LoAddr = St->getBasePtr();
9594 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9595 DAG.getConstant(4, MVT::i32));
9597 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9598 St->getSrcValue(), St->getSrcValueOffset(),
9599 St->isVolatile(), St->isNonTemporal(),
9600 St->getAlignment());
9601 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9603 St->getSrcValueOffset() + 4,
9605 St->isNonTemporal(),
9606 MinAlign(St->getAlignment(), 4));
9607 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9612 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9613 /// X86ISD::FXOR nodes.
9614 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9615 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9616 // F[X]OR(0.0, x) -> x
9617 // F[X]OR(x, 0.0) -> x
9618 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9619 if (C->getValueAPF().isPosZero())
9620 return N->getOperand(1);
9621 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9622 if (C->getValueAPF().isPosZero())
9623 return N->getOperand(0);
9627 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9628 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9629 // FAND(0.0, x) -> 0.0
9630 // FAND(x, 0.0) -> 0.0
9631 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9632 if (C->getValueAPF().isPosZero())
9633 return N->getOperand(0);
9634 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9635 if (C->getValueAPF().isPosZero())
9636 return N->getOperand(1);
9640 static SDValue PerformBTCombine(SDNode *N,
9642 TargetLowering::DAGCombinerInfo &DCI) {
9643 // BT ignores high bits in the bit index operand.
9644 SDValue Op1 = N->getOperand(1);
9645 if (Op1.hasOneUse()) {
9646 unsigned BitWidth = Op1.getValueSizeInBits();
9647 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9648 APInt KnownZero, KnownOne;
9649 TargetLowering::TargetLoweringOpt TLO(DAG);
9650 TargetLowering &TLI = DAG.getTargetLoweringInfo();
9651 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9652 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9653 DCI.CommitTargetLoweringOpt(TLO);
9658 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9659 SDValue Op = N->getOperand(0);
9660 if (Op.getOpcode() == ISD::BIT_CONVERT)
9661 Op = Op.getOperand(0);
9662 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9663 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9664 VT.getVectorElementType().getSizeInBits() ==
9665 OpVT.getVectorElementType().getSizeInBits()) {
9666 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9671 // On X86 and X86-64, atomic operations are lowered to locked instructions.
9672 // Locked instructions, in turn, have implicit fence semantics (all memory
9673 // operations are flushed before issuing the locked instruction, and the
9674 // are not buffered), so we can fold away the common pattern of
9675 // fence-atomic-fence.
9676 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9677 SDValue atomic = N->getOperand(0);
9678 switch (atomic.getOpcode()) {
9679 case ISD::ATOMIC_CMP_SWAP:
9680 case ISD::ATOMIC_SWAP:
9681 case ISD::ATOMIC_LOAD_ADD:
9682 case ISD::ATOMIC_LOAD_SUB:
9683 case ISD::ATOMIC_LOAD_AND:
9684 case ISD::ATOMIC_LOAD_OR:
9685 case ISD::ATOMIC_LOAD_XOR:
9686 case ISD::ATOMIC_LOAD_NAND:
9687 case ISD::ATOMIC_LOAD_MIN:
9688 case ISD::ATOMIC_LOAD_MAX:
9689 case ISD::ATOMIC_LOAD_UMIN:
9690 case ISD::ATOMIC_LOAD_UMAX:
9696 SDValue fence = atomic.getOperand(0);
9697 if (fence.getOpcode() != ISD::MEMBARRIER)
9700 switch (atomic.getOpcode()) {
9701 case ISD::ATOMIC_CMP_SWAP:
9702 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9703 atomic.getOperand(1), atomic.getOperand(2),
9704 atomic.getOperand(3));
9705 case ISD::ATOMIC_SWAP:
9706 case ISD::ATOMIC_LOAD_ADD:
9707 case ISD::ATOMIC_LOAD_SUB:
9708 case ISD::ATOMIC_LOAD_AND:
9709 case ISD::ATOMIC_LOAD_OR:
9710 case ISD::ATOMIC_LOAD_XOR:
9711 case ISD::ATOMIC_LOAD_NAND:
9712 case ISD::ATOMIC_LOAD_MIN:
9713 case ISD::ATOMIC_LOAD_MAX:
9714 case ISD::ATOMIC_LOAD_UMIN:
9715 case ISD::ATOMIC_LOAD_UMAX:
9716 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9717 atomic.getOperand(1), atomic.getOperand(2));
9723 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9724 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9725 // (and (i32 x86isd::setcc_carry), 1)
9726 // This eliminates the zext. This transformation is necessary because
9727 // ISD::SETCC is always legalized to i8.
9728 DebugLoc dl = N->getDebugLoc();
9729 SDValue N0 = N->getOperand(0);
9730 EVT VT = N->getValueType(0);
9731 if (N0.getOpcode() == ISD::AND &&
9733 N0.getOperand(0).hasOneUse()) {
9734 SDValue N00 = N0.getOperand(0);
9735 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9737 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9738 if (!C || C->getZExtValue() != 1)
9740 return DAG.getNode(ISD::AND, dl, VT,
9741 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9742 N00.getOperand(0), N00.getOperand(1)),
9743 DAG.getConstant(1, VT));
9749 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9750 DAGCombinerInfo &DCI) const {
9751 SelectionDAG &DAG = DCI.DAG;
9752 switch (N->getOpcode()) {
9754 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9755 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9756 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9757 case ISD::AND: return PerformANDCombine(N, DAG, DCI);
9758 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9761 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9762 case ISD::OR: return PerformOrCombine(N, DAG, Subtarget);
9763 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9765 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9766 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9767 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9768 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9769 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9770 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9776 //===----------------------------------------------------------------------===//
9777 // X86 Inline Assembly Support
9778 //===----------------------------------------------------------------------===//
9780 static bool LowerToBSwap(CallInst *CI) {
9781 // FIXME: this should verify that we are targetting a 486 or better. If not,
9782 // we will turn this bswap into something that will be lowered to logical ops
9783 // instead of emitting the bswap asm. For now, we don't support 486 or lower
9784 // so don't worry about this.
9786 // Verify this is a simple bswap.
9787 if (CI->getNumOperands() != 2 ||
9788 CI->getType() != CI->getOperand(1)->getType() ||
9789 !CI->getType()->isIntegerTy())
9792 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9793 if (!Ty || Ty->getBitWidth() % 16 != 0)
9796 // Okay, we can do this xform, do so now.
9797 const Type *Tys[] = { Ty };
9798 Module *M = CI->getParent()->getParent()->getParent();
9799 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9801 Value *Op = CI->getOperand(1);
9802 Op = CallInst::Create(Int, Op, CI->getName(), CI);
9804 CI->replaceAllUsesWith(Op);
9805 CI->eraseFromParent();
9809 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9810 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9811 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9813 std::string AsmStr = IA->getAsmString();
9815 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9816 SmallVector<StringRef, 4> AsmPieces;
9817 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9819 switch (AsmPieces.size()) {
9820 default: return false;
9822 AsmStr = AsmPieces[0];
9824 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9827 if (AsmPieces.size() == 2 &&
9828 (AsmPieces[0] == "bswap" ||
9829 AsmPieces[0] == "bswapq" ||
9830 AsmPieces[0] == "bswapl") &&
9831 (AsmPieces[1] == "$0" ||
9832 AsmPieces[1] == "${0:q}")) {
9833 // No need to check constraints, nothing other than the equivalent of
9834 // "=r,0" would be valid here.
9835 return LowerToBSwap(CI);
9837 // rorw $$8, ${0:w} --> llvm.bswap.i16
9838 if (CI->getType()->isIntegerTy(16) &&
9839 AsmPieces.size() == 3 &&
9840 AsmPieces[0] == "rorw" &&
9841 AsmPieces[1] == "$$8," &&
9842 AsmPieces[2] == "${0:w}" &&
9843 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
9844 return LowerToBSwap(CI);
9848 if (CI->getType()->isIntegerTy(64) &&
9849 Constraints.size() >= 2 &&
9850 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9851 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9852 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9853 SmallVector<StringRef, 4> Words;
9854 SplitString(AsmPieces[0], Words, " \t");
9855 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9857 SplitString(AsmPieces[1], Words, " \t");
9858 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9860 SplitString(AsmPieces[2], Words, " \t,");
9861 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9862 Words[2] == "%edx") {
9863 return LowerToBSwap(CI);
9875 /// getConstraintType - Given a constraint letter, return the type of
9876 /// constraint it is for this target.
9877 X86TargetLowering::ConstraintType
9878 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9879 if (Constraint.size() == 1) {
9880 switch (Constraint[0]) {
9892 return C_RegisterClass;
9900 return TargetLowering::getConstraintType(Constraint);
9903 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9904 /// with another that has more specific requirements based on the type of the
9905 /// corresponding operand.
9906 const char *X86TargetLowering::
9907 LowerXConstraint(EVT ConstraintVT) const {
9908 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9909 // 'f' like normal targets.
9910 if (ConstraintVT.isFloatingPoint()) {
9911 if (Subtarget->hasSSE2())
9913 if (Subtarget->hasSSE1())
9917 return TargetLowering::LowerXConstraint(ConstraintVT);
9920 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9921 /// vector. If it is invalid, don't add anything to Ops.
9922 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9925 std::vector<SDValue>&Ops,
9926 SelectionDAG &DAG) const {
9927 SDValue Result(0, 0);
9929 switch (Constraint) {
9932 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9933 if (C->getZExtValue() <= 31) {
9934 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9940 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9941 if (C->getZExtValue() <= 63) {
9942 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9948 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9949 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9950 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9956 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9957 if (C->getZExtValue() <= 255) {
9958 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9964 // 32-bit signed value
9965 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9966 const ConstantInt *CI = C->getConstantIntValue();
9967 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9968 C->getSExtValue())) {
9969 // Widen to 64 bits here to get it sign extended.
9970 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9973 // FIXME gcc accepts some relocatable values here too, but only in certain
9974 // memory models; it's complicated.
9979 // 32-bit unsigned value
9980 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9981 const ConstantInt *CI = C->getConstantIntValue();
9982 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9983 C->getZExtValue())) {
9984 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9988 // FIXME gcc accepts some relocatable values here too, but only in certain
9989 // memory models; it's complicated.
9993 // Literal immediates are always ok.
9994 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9995 // Widen to 64 bits here to get it sign extended.
9996 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
10000 // If we are in non-pic codegen mode, we allow the address of a global (with
10001 // an optional displacement) to be used with 'i'.
10002 GlobalAddressSDNode *GA = 0;
10003 int64_t Offset = 0;
10005 // Match either (GA), (GA+C), (GA+C1+C2), etc.
10007 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
10008 Offset += GA->getOffset();
10010 } else if (Op.getOpcode() == ISD::ADD) {
10011 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10012 Offset += C->getZExtValue();
10013 Op = Op.getOperand(0);
10016 } else if (Op.getOpcode() == ISD::SUB) {
10017 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
10018 Offset += -C->getZExtValue();
10019 Op = Op.getOperand(0);
10024 // Otherwise, this isn't something we can handle, reject it.
10028 GlobalValue *GV = GA->getGlobal();
10029 // If we require an extra load to get this address, as in PIC mode, we
10030 // can't accept it.
10031 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
10032 getTargetMachine())))
10036 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
10038 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
10044 if (Result.getNode()) {
10045 Ops.push_back(Result);
10048 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
10052 std::vector<unsigned> X86TargetLowering::
10053 getRegClassForInlineAsmConstraint(const std::string &Constraint,
10055 if (Constraint.size() == 1) {
10056 // FIXME: not handling fp-stack yet!
10057 switch (Constraint[0]) { // GCC X86 Constraint Letters
10058 default: break; // Unknown constraint letter
10059 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
10060 if (Subtarget->is64Bit()) {
10061 if (VT == MVT::i32)
10062 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
10063 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
10064 X86::R10D,X86::R11D,X86::R12D,
10065 X86::R13D,X86::R14D,X86::R15D,
10066 X86::EBP, X86::ESP, 0);
10067 else if (VT == MVT::i16)
10068 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
10069 X86::SI, X86::DI, X86::R8W,X86::R9W,
10070 X86::R10W,X86::R11W,X86::R12W,
10071 X86::R13W,X86::R14W,X86::R15W,
10072 X86::BP, X86::SP, 0);
10073 else if (VT == MVT::i8)
10074 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
10075 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
10076 X86::R10B,X86::R11B,X86::R12B,
10077 X86::R13B,X86::R14B,X86::R15B,
10078 X86::BPL, X86::SPL, 0);
10080 else if (VT == MVT::i64)
10081 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
10082 X86::RSI, X86::RDI, X86::R8, X86::R9,
10083 X86::R10, X86::R11, X86::R12,
10084 X86::R13, X86::R14, X86::R15,
10085 X86::RBP, X86::RSP, 0);
10089 // 32-bit fallthrough
10090 case 'Q': // Q_REGS
10091 if (VT == MVT::i32)
10092 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10093 else if (VT == MVT::i16)
10094 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10095 else if (VT == MVT::i8)
10096 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10097 else if (VT == MVT::i64)
10098 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10103 return std::vector<unsigned>();
10106 std::pair<unsigned, const TargetRegisterClass*>
10107 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10109 // First, see if this is a constraint that directly corresponds to an LLVM
10111 if (Constraint.size() == 1) {
10112 // GCC Constraint Letters
10113 switch (Constraint[0]) {
10115 case 'r': // GENERAL_REGS
10116 case 'l': // INDEX_REGS
10118 return std::make_pair(0U, X86::GR8RegisterClass);
10119 if (VT == MVT::i16)
10120 return std::make_pair(0U, X86::GR16RegisterClass);
10121 if (VT == MVT::i32 || !Subtarget->is64Bit())
10122 return std::make_pair(0U, X86::GR32RegisterClass);
10123 return std::make_pair(0U, X86::GR64RegisterClass);
10124 case 'R': // LEGACY_REGS
10126 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10127 if (VT == MVT::i16)
10128 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10129 if (VT == MVT::i32 || !Subtarget->is64Bit())
10130 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10131 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10132 case 'f': // FP Stack registers.
10133 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10134 // value to the correct fpstack register class.
10135 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10136 return std::make_pair(0U, X86::RFP32RegisterClass);
10137 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10138 return std::make_pair(0U, X86::RFP64RegisterClass);
10139 return std::make_pair(0U, X86::RFP80RegisterClass);
10140 case 'y': // MMX_REGS if MMX allowed.
10141 if (!Subtarget->hasMMX()) break;
10142 return std::make_pair(0U, X86::VR64RegisterClass);
10143 case 'Y': // SSE_REGS if SSE2 allowed
10144 if (!Subtarget->hasSSE2()) break;
10146 case 'x': // SSE_REGS if SSE1 allowed
10147 if (!Subtarget->hasSSE1()) break;
10149 switch (VT.getSimpleVT().SimpleTy) {
10151 // Scalar SSE types.
10154 return std::make_pair(0U, X86::FR32RegisterClass);
10157 return std::make_pair(0U, X86::FR64RegisterClass);
10165 return std::make_pair(0U, X86::VR128RegisterClass);
10171 // Use the default implementation in TargetLowering to convert the register
10172 // constraint into a member of a register class.
10173 std::pair<unsigned, const TargetRegisterClass*> Res;
10174 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10176 // Not found as a standard register?
10177 if (Res.second == 0) {
10178 // Map st(0) -> st(7) -> ST0
10179 if (Constraint.size() == 7 && Constraint[0] == '{' &&
10180 tolower(Constraint[1]) == 's' &&
10181 tolower(Constraint[2]) == 't' &&
10182 Constraint[3] == '(' &&
10183 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10184 Constraint[5] == ')' &&
10185 Constraint[6] == '}') {
10187 Res.first = X86::ST0+Constraint[4]-'0';
10188 Res.second = X86::RFP80RegisterClass;
10192 // GCC allows "st(0)" to be called just plain "st".
10193 if (StringRef("{st}").equals_lower(Constraint)) {
10194 Res.first = X86::ST0;
10195 Res.second = X86::RFP80RegisterClass;
10200 if (StringRef("{flags}").equals_lower(Constraint)) {
10201 Res.first = X86::EFLAGS;
10202 Res.second = X86::CCRRegisterClass;
10206 // 'A' means EAX + EDX.
10207 if (Constraint == "A") {
10208 Res.first = X86::EAX;
10209 Res.second = X86::GR32_ADRegisterClass;
10215 // Otherwise, check to see if this is a register class of the wrong value
10216 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10217 // turn into {ax},{dx}.
10218 if (Res.second->hasType(VT))
10219 return Res; // Correct type already, nothing to do.
10221 // All of the single-register GCC register classes map their values onto
10222 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
10223 // really want an 8-bit or 32-bit register, map to the appropriate register
10224 // class and return the appropriate register.
10225 if (Res.second == X86::GR16RegisterClass) {
10226 if (VT == MVT::i8) {
10227 unsigned DestReg = 0;
10228 switch (Res.first) {
10230 case X86::AX: DestReg = X86::AL; break;
10231 case X86::DX: DestReg = X86::DL; break;
10232 case X86::CX: DestReg = X86::CL; break;
10233 case X86::BX: DestReg = X86::BL; break;
10236 Res.first = DestReg;
10237 Res.second = X86::GR8RegisterClass;
10239 } else if (VT == MVT::i32) {
10240 unsigned DestReg = 0;
10241 switch (Res.first) {
10243 case X86::AX: DestReg = X86::EAX; break;
10244 case X86::DX: DestReg = X86::EDX; break;
10245 case X86::CX: DestReg = X86::ECX; break;
10246 case X86::BX: DestReg = X86::EBX; break;
10247 case X86::SI: DestReg = X86::ESI; break;
10248 case X86::DI: DestReg = X86::EDI; break;
10249 case X86::BP: DestReg = X86::EBP; break;
10250 case X86::SP: DestReg = X86::ESP; break;
10253 Res.first = DestReg;
10254 Res.second = X86::GR32RegisterClass;
10256 } else if (VT == MVT::i64) {
10257 unsigned DestReg = 0;
10258 switch (Res.first) {
10260 case X86::AX: DestReg = X86::RAX; break;
10261 case X86::DX: DestReg = X86::RDX; break;
10262 case X86::CX: DestReg = X86::RCX; break;
10263 case X86::BX: DestReg = X86::RBX; break;
10264 case X86::SI: DestReg = X86::RSI; break;
10265 case X86::DI: DestReg = X86::RDI; break;
10266 case X86::BP: DestReg = X86::RBP; break;
10267 case X86::SP: DestReg = X86::RSP; break;
10270 Res.first = DestReg;
10271 Res.second = X86::GR64RegisterClass;
10274 } else if (Res.second == X86::FR32RegisterClass ||
10275 Res.second == X86::FR64RegisterClass ||
10276 Res.second == X86::VR128RegisterClass) {
10277 // Handle references to XMM physical registers that got mapped into the
10278 // wrong class. This can happen with constraints like {xmm0} where the
10279 // target independent register mapper will just pick the first match it can
10280 // find, ignoring the required type.
10281 if (VT == MVT::f32)
10282 Res.second = X86::FR32RegisterClass;
10283 else if (VT == MVT::f64)
10284 Res.second = X86::FR64RegisterClass;
10285 else if (X86::VR128RegisterClass->hasType(VT))
10286 Res.second = X86::VR128RegisterClass;
10292 //===----------------------------------------------------------------------===//
10293 // X86 Widen vector type
10294 //===----------------------------------------------------------------------===//
10296 /// getWidenVectorType: given a vector type, returns the type to widen
10297 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
10298 /// If there is no vector type that we want to widen to, returns MVT::Other
10299 /// When and where to widen is target dependent based on the cost of
10300 /// scalarizing vs using the wider vector type.
10302 EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
10303 assert(VT.isVector());
10304 if (isTypeLegal(VT))
10307 // TODO: In computeRegisterProperty, we can compute the list of legal vector
10308 // type based on element type. This would speed up our search (though
10309 // it may not be worth it since the size of the list is relatively
10311 EVT EltVT = VT.getVectorElementType();
10312 unsigned NElts = VT.getVectorNumElements();
10314 // On X86, it make sense to widen any vector wider than 1
10318 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
10319 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
10320 EVT SVT = (MVT::SimpleValueType)nVT;
10322 if (isTypeLegal(SVT) &&
10323 SVT.getVectorElementType() == EltVT &&
10324 SVT.getVectorNumElements() > NElts)