1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/ADT/VectorExtras.h"
33 #include "llvm/Support/CommandLine.h"
34 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
35 cl::desc("Enable fastcc on X86"));
37 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
38 : TargetLowering(TM) {
39 Subtarget = &TM.getSubtarget<X86Subtarget>();
40 X86ScalarSSE = Subtarget->hasSSE2();
42 // Set up the TargetLowering object.
44 // X86 is weird, it always uses i8 for shift amounts and setcc results.
45 setShiftAmountType(MVT::i8);
46 setSetCCResultType(MVT::i8);
47 setSetCCResultContents(ZeroOrOneSetCCResult);
48 setSchedulingPreference(SchedulingForRegPressure);
49 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
50 setStackPointerRegisterToSaveRestore(X86::ESP);
52 // Set up the register classes.
53 addRegisterClass(MVT::i8, X86::R8RegisterClass);
54 addRegisterClass(MVT::i16, X86::R16RegisterClass);
55 addRegisterClass(MVT::i32, X86::R32RegisterClass);
57 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
59 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
60 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
61 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
64 // No SSE i64 SINT_TO_FP, so expand i32 UINT_TO_FP instead.
65 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
67 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
69 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
71 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
72 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
73 // SSE has no i16 to fp conversion, only i32
75 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
77 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
78 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
81 // We can handle SINT_TO_FP and FP_TO_SINT from/to i64 even though i64
83 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
84 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
86 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
88 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
89 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
92 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
94 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
95 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
98 // Handle FP_TO_UINT by promoting the destination to a larger signed
100 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
101 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
102 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
104 if (X86ScalarSSE && !Subtarget->hasSSE3())
105 // Expand FP_TO_UINT into a select.
106 // FIXME: We would like to use a Custom expander here eventually to do
107 // the optimal thing for SSE vs. the default expansion in the legalizer.
108 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
110 // With SSE3 we can use fisttpll to convert to a signed i64.
111 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
113 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
114 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
116 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
117 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
118 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
119 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
120 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
121 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
125 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
126 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
127 setOperationAction(ISD::FREM , MVT::f64 , Expand);
128 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
129 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
130 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
131 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
132 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
133 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
134 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
135 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
136 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
137 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
138 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
140 setOperationAction(ISD::READIO , MVT::i1 , Expand);
141 setOperationAction(ISD::READIO , MVT::i8 , Expand);
142 setOperationAction(ISD::READIO , MVT::i16 , Expand);
143 setOperationAction(ISD::READIO , MVT::i32 , Expand);
144 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
145 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
146 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
147 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
149 // These should be promoted to a larger select which is supported.
150 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
151 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
153 // X86 wants to expand cmov itself.
154 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
155 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
156 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
157 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
158 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
159 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
160 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
161 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
162 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
163 // X86 ret instruction may pop stack.
164 setOperationAction(ISD::RET , MVT::Other, Custom);
166 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
167 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
168 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
169 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
170 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
171 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
172 // X86 wants to expand memset / memcpy itself.
173 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
174 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
176 // We don't have line number support yet.
177 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
178 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
179 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
181 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
182 setOperationAction(ISD::VASTART , MVT::Other, Custom);
184 // Use the default implementation.
185 setOperationAction(ISD::VAARG , MVT::Other, Expand);
186 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
187 setOperationAction(ISD::VAEND , MVT::Other, Expand);
188 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
189 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
190 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
193 // Set up the FP register classes.
194 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
195 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
197 // SSE has no load+extend ops
198 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
199 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
201 // Use ANDPD to simulate FABS.
202 setOperationAction(ISD::FABS , MVT::f64, Custom);
203 setOperationAction(ISD::FABS , MVT::f32, Custom);
205 // Use XORP to simulate FNEG.
206 setOperationAction(ISD::FNEG , MVT::f64, Custom);
207 setOperationAction(ISD::FNEG , MVT::f32, Custom);
209 // We don't support sin/cos/fmod
210 setOperationAction(ISD::FSIN , MVT::f64, Expand);
211 setOperationAction(ISD::FCOS , MVT::f64, Expand);
212 setOperationAction(ISD::FREM , MVT::f64, Expand);
213 setOperationAction(ISD::FSIN , MVT::f32, Expand);
214 setOperationAction(ISD::FCOS , MVT::f32, Expand);
215 setOperationAction(ISD::FREM , MVT::f32, Expand);
217 // Expand FP immediates into loads from the stack, except for the special
219 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
220 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
221 addLegalFPImmediate(+0.0); // xorps / xorpd
223 // Set up the FP register classes.
224 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
226 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
229 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
230 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
233 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
234 addLegalFPImmediate(+0.0); // FLD0
235 addLegalFPImmediate(+1.0); // FLD1
236 addLegalFPImmediate(-0.0); // FLD0/FCHS
237 addLegalFPImmediate(-1.0); // FLD1/FCHS
239 computeRegisterProperties();
241 // FIXME: These should be based on subtarget info. Plus, the values should
242 // be smaller when we are in optimizing for size mode.
243 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
244 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
245 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
246 allowUnalignedMemoryAccesses = true; // x86 supports it!
249 std::vector<SDOperand>
250 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
251 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
252 return LowerFastCCArguments(F, DAG);
253 return LowerCCCArguments(F, DAG);
256 std::pair<SDOperand, SDOperand>
257 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
258 bool isVarArg, unsigned CallingConv,
260 SDOperand Callee, ArgListTy &Args,
262 assert((!isVarArg || CallingConv == CallingConv::C) &&
263 "Only C takes varargs!");
265 // If the callee is a GlobalAddress node (quite common, every direct call is)
266 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
267 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
268 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
269 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
270 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
272 if (CallingConv == CallingConv::Fast && EnableFastCC)
273 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
274 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
277 //===----------------------------------------------------------------------===//
278 // C Calling Convention implementation
279 //===----------------------------------------------------------------------===//
281 std::vector<SDOperand>
282 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
283 std::vector<SDOperand> ArgValues;
285 MachineFunction &MF = DAG.getMachineFunction();
286 MachineFrameInfo *MFI = MF.getFrameInfo();
288 // Add DAG nodes to load the arguments... On entry to a function on the X86,
289 // the stack frame looks like this:
291 // [ESP] -- return address
292 // [ESP + 4] -- first argument (leftmost lexically)
293 // [ESP + 8] -- second argument, if first argument is four bytes in size
296 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
297 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
298 MVT::ValueType ObjectVT = getValueType(I->getType());
299 unsigned ArgIncrement = 4;
302 default: assert(0 && "Unhandled argument type!");
304 case MVT::i8: ObjSize = 1; break;
305 case MVT::i16: ObjSize = 2; break;
306 case MVT::i32: ObjSize = 4; break;
307 case MVT::i64: ObjSize = ArgIncrement = 8; break;
308 case MVT::f32: ObjSize = 4; break;
309 case MVT::f64: ObjSize = ArgIncrement = 8; break;
311 // Create the frame index object for this incoming parameter...
312 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
314 // Create the SelectionDAG nodes corresponding to a load from this parameter
315 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
317 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
321 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
322 DAG.getSrcValue(NULL));
324 if (MVT::isInteger(ObjectVT))
325 ArgValue = DAG.getConstant(0, ObjectVT);
327 ArgValue = DAG.getConstantFP(0, ObjectVT);
329 ArgValues.push_back(ArgValue);
331 ArgOffset += ArgIncrement; // Move on to the next argument...
334 // If the function takes variable number of arguments, make a frame index for
335 // the start of the first vararg value... for expansion of llvm.va_start.
337 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
338 ReturnAddrIndex = 0; // No return address slot generated yet.
339 BytesToPopOnReturn = 0; // Callee pops nothing.
340 BytesCallerReserves = ArgOffset;
342 // Finally, inform the code generator which regs we return values in.
343 switch (getValueType(F.getReturnType())) {
344 default: assert(0 && "Unknown type!");
345 case MVT::isVoid: break;
350 MF.addLiveOut(X86::EAX);
353 MF.addLiveOut(X86::EAX);
354 MF.addLiveOut(X86::EDX);
358 MF.addLiveOut(X86::ST0);
364 std::pair<SDOperand, SDOperand>
365 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
366 bool isVarArg, bool isTailCall,
367 SDOperand Callee, ArgListTy &Args,
369 // Count how many bytes are to be pushed on the stack.
370 unsigned NumBytes = 0;
374 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(0, getPointerTy()));
376 for (unsigned i = 0, e = Args.size(); i != e; ++i)
377 switch (getValueType(Args[i].second)) {
378 default: assert(0 && "Unknown value type!");
392 Chain = DAG.getCALLSEQ_START(Chain,
393 DAG.getConstant(NumBytes, getPointerTy()));
395 // Arguments go on the stack in reverse order, as specified by the ABI.
396 unsigned ArgOffset = 0;
397 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
398 std::vector<SDOperand> Stores;
400 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
401 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
402 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
404 switch (getValueType(Args[i].second)) {
405 default: assert(0 && "Unexpected ValueType for argument!");
409 // Promote the integer to 32 bits. If the input type is signed use a
410 // sign extend, otherwise use a zero extend.
411 if (Args[i].second->isSigned())
412 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
414 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
419 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
420 Args[i].first, PtrOff,
421 DAG.getSrcValue(NULL)));
426 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
427 Args[i].first, PtrOff,
428 DAG.getSrcValue(NULL)));
433 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
436 std::vector<MVT::ValueType> RetVals;
437 MVT::ValueType RetTyVT = getValueType(RetTy);
438 RetVals.push_back(MVT::Other);
440 // The result values produced have to be legal. Promote the result.
442 case MVT::isVoid: break;
444 RetVals.push_back(RetTyVT);
449 RetVals.push_back(MVT::i32);
453 RetVals.push_back(MVT::f32);
455 RetVals.push_back(MVT::f64);
458 RetVals.push_back(MVT::i32);
459 RetVals.push_back(MVT::i32);
463 std::vector<MVT::ValueType> NodeTys;
464 NodeTys.push_back(MVT::Other); // Returns a chain
465 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
466 std::vector<SDOperand> Ops;
467 Ops.push_back(Chain);
468 Ops.push_back(Callee);
470 // FIXME: Do not generate X86ISD::TAILCALL for now.
471 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
472 SDOperand InFlag = Chain.getValue(1);
475 NodeTys.push_back(MVT::Other); // Returns a chain
476 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
478 Ops.push_back(Chain);
479 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
480 Ops.push_back(DAG.getConstant(0, getPointerTy()));
481 Ops.push_back(InFlag);
482 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
483 InFlag = Chain.getValue(1);
486 if (RetTyVT != MVT::isVoid) {
488 default: assert(0 && "Unknown value type to return!");
491 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
492 Chain = RetVal.getValue(1);
493 if (RetTyVT == MVT::i1)
494 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
497 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
498 Chain = RetVal.getValue(1);
501 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
502 Chain = RetVal.getValue(1);
505 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
506 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
508 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
509 Chain = Hi.getValue(1);
514 std::vector<MVT::ValueType> Tys;
515 Tys.push_back(MVT::f64);
516 Tys.push_back(MVT::Other);
517 Tys.push_back(MVT::Flag);
518 std::vector<SDOperand> Ops;
519 Ops.push_back(Chain);
520 Ops.push_back(InFlag);
521 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
522 Chain = RetVal.getValue(1);
523 InFlag = RetVal.getValue(2);
525 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
526 // shouldn't be necessary except that RFP cannot be live across
527 // multiple blocks. When stackifier is fixed, they can be uncoupled.
528 MachineFunction &MF = DAG.getMachineFunction();
529 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
530 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
532 Tys.push_back(MVT::Other);
534 Ops.push_back(Chain);
535 Ops.push_back(RetVal);
536 Ops.push_back(StackSlot);
537 Ops.push_back(DAG.getValueType(RetTyVT));
538 Ops.push_back(InFlag);
539 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
540 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
541 DAG.getSrcValue(NULL));
542 Chain = RetVal.getValue(1);
545 if (RetTyVT == MVT::f32 && !X86ScalarSSE)
546 // FIXME: we would really like to remember that this FP_ROUND
547 // operation is okay to eliminate if we allow excess FP precision.
548 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
554 return std::make_pair(RetVal, Chain);
557 //===----------------------------------------------------------------------===//
558 // Fast Calling Convention implementation
559 //===----------------------------------------------------------------------===//
561 // The X86 'fast' calling convention passes up to two integer arguments in
562 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
563 // and requires that the callee pop its arguments off the stack (allowing proper
564 // tail calls), and has the same return value conventions as C calling convs.
566 // This calling convention always arranges for the callee pop value to be 8n+4
567 // bytes, which is needed for tail recursion elimination and stack alignment
570 // Note that this can be enhanced in the future to pass fp vals in registers
571 // (when we have a global fp allocator) and do other tricks.
574 /// AddLiveIn - This helper function adds the specified physical register to the
575 /// MachineFunction as a live in value. It also creates a corresponding virtual
577 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
578 TargetRegisterClass *RC) {
579 assert(RC->contains(PReg) && "Not the correct regclass!");
580 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
581 MF.addLiveIn(PReg, VReg);
586 std::vector<SDOperand>
587 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
588 std::vector<SDOperand> ArgValues;
590 MachineFunction &MF = DAG.getMachineFunction();
591 MachineFrameInfo *MFI = MF.getFrameInfo();
593 // Add DAG nodes to load the arguments... On entry to a function the stack
594 // frame looks like this:
596 // [ESP] -- return address
597 // [ESP + 4] -- first nonreg argument (leftmost lexically)
598 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
600 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
602 // Keep track of the number of integer regs passed so far. This can be either
603 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
605 unsigned NumIntRegs = 0;
607 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
608 MVT::ValueType ObjectVT = getValueType(I->getType());
609 unsigned ArgIncrement = 4;
610 unsigned ObjSize = 0;
614 default: assert(0 && "Unhandled argument type!");
617 if (NumIntRegs < 2) {
618 if (!I->use_empty()) {
619 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
620 X86::R8RegisterClass);
621 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
622 DAG.setRoot(ArgValue.getValue(1));
623 if (ObjectVT == MVT::i1)
624 // FIXME: Should insert a assertzext here.
625 ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue);
634 if (NumIntRegs < 2) {
635 if (!I->use_empty()) {
636 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
637 X86::R16RegisterClass);
638 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
639 DAG.setRoot(ArgValue.getValue(1));
647 if (NumIntRegs < 2) {
648 if (!I->use_empty()) {
649 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
650 X86::R32RegisterClass);
651 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
652 DAG.setRoot(ArgValue.getValue(1));
660 if (NumIntRegs == 0) {
661 if (!I->use_empty()) {
662 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
663 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
665 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
666 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
667 DAG.setRoot(Hi.getValue(1));
669 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
673 } else if (NumIntRegs == 1) {
674 if (!I->use_empty()) {
675 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
676 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
677 DAG.setRoot(Low.getValue(1));
679 // Load the high part from memory.
680 // Create the frame index object for this incoming parameter...
681 int FI = MFI->CreateFixedObject(4, ArgOffset);
682 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
683 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
684 DAG.getSrcValue(NULL));
685 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
691 ObjSize = ArgIncrement = 8;
693 case MVT::f32: ObjSize = 4; break;
694 case MVT::f64: ObjSize = ArgIncrement = 8; break;
697 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
699 if (ObjSize && !I->use_empty()) {
700 // Create the frame index object for this incoming parameter...
701 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
703 // Create the SelectionDAG nodes corresponding to a load from this
705 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
707 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
708 DAG.getSrcValue(NULL));
709 } else if (ArgValue.Val == 0) {
710 if (MVT::isInteger(ObjectVT))
711 ArgValue = DAG.getConstant(0, ObjectVT);
713 ArgValue = DAG.getConstantFP(0, ObjectVT);
715 ArgValues.push_back(ArgValue);
718 ArgOffset += ArgIncrement; // Move on to the next argument.
721 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
722 // arguments and the arguments after the retaddr has been pushed are aligned.
723 if ((ArgOffset & 7) == 0)
726 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
727 ReturnAddrIndex = 0; // No return address slot generated yet.
728 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
729 BytesCallerReserves = 0;
731 // Finally, inform the code generator which regs we return values in.
732 switch (getValueType(F.getReturnType())) {
733 default: assert(0 && "Unknown type!");
734 case MVT::isVoid: break;
739 MF.addLiveOut(X86::EAX);
742 MF.addLiveOut(X86::EAX);
743 MF.addLiveOut(X86::EDX);
747 MF.addLiveOut(X86::ST0);
753 std::pair<SDOperand, SDOperand>
754 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
755 bool isTailCall, SDOperand Callee,
756 ArgListTy &Args, SelectionDAG &DAG) {
757 // Count how many bytes are to be pushed on the stack.
758 unsigned NumBytes = 0;
760 // Keep track of the number of integer regs passed so far. This can be either
761 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
763 unsigned NumIntRegs = 0;
765 for (unsigned i = 0, e = Args.size(); i != e; ++i)
766 switch (getValueType(Args[i].second)) {
767 default: assert(0 && "Unknown value type!");
772 if (NumIntRegs < 2) {
781 if (NumIntRegs == 0) {
784 } else if (NumIntRegs == 1) {
796 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
797 // arguments and the arguments after the retaddr has been pushed are aligned.
798 if ((NumBytes & 7) == 0)
801 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
803 // Arguments go on the stack in reverse order, as specified by the ABI.
804 unsigned ArgOffset = 0;
805 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
807 std::vector<SDOperand> Stores;
808 std::vector<SDOperand> RegValuesToPass;
809 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
810 switch (getValueType(Args[i].second)) {
811 default: assert(0 && "Unexpected ValueType for argument!");
813 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first);
818 if (NumIntRegs < 2) {
819 RegValuesToPass.push_back(Args[i].first);
825 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
826 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
827 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
828 Args[i].first, PtrOff,
829 DAG.getSrcValue(NULL)));
834 if (NumIntRegs < 2) { // Can pass part of it in regs?
835 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
836 Args[i].first, DAG.getConstant(1, MVT::i32));
837 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
838 Args[i].first, DAG.getConstant(0, MVT::i32));
839 RegValuesToPass.push_back(Lo);
841 if (NumIntRegs < 2) { // Pass both parts in regs?
842 RegValuesToPass.push_back(Hi);
845 // Pass the high part in memory.
846 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
847 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
848 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
849 Hi, PtrOff, DAG.getSrcValue(NULL)));
856 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
857 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
858 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
859 Args[i].first, PtrOff,
860 DAG.getSrcValue(NULL)));
866 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
868 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
869 // arguments and the arguments after the retaddr has been pushed are aligned.
870 if ((ArgOffset & 7) == 0)
873 std::vector<MVT::ValueType> RetVals;
874 MVT::ValueType RetTyVT = getValueType(RetTy);
876 RetVals.push_back(MVT::Other);
878 // The result values produced have to be legal. Promote the result.
880 case MVT::isVoid: break;
882 RetVals.push_back(RetTyVT);
887 RetVals.push_back(MVT::i32);
891 RetVals.push_back(MVT::f32);
893 RetVals.push_back(MVT::f64);
896 RetVals.push_back(MVT::i32);
897 RetVals.push_back(MVT::i32);
901 // Build a sequence of copy-to-reg nodes chained together with token chain
902 // and flag operands which copy the outgoing args into registers.
904 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
906 SDOperand RegToPass = RegValuesToPass[i];
907 switch (RegToPass.getValueType()) {
908 default: assert(0 && "Bad thing to pass in regs");
910 CCReg = (i == 0) ? X86::AL : X86::DL;
913 CCReg = (i == 0) ? X86::AX : X86::DX;
916 CCReg = (i == 0) ? X86::EAX : X86::EDX;
920 Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag);
921 InFlag = Chain.getValue(1);
924 std::vector<MVT::ValueType> NodeTys;
925 NodeTys.push_back(MVT::Other); // Returns a chain
926 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
927 std::vector<SDOperand> Ops;
928 Ops.push_back(Chain);
929 Ops.push_back(Callee);
931 Ops.push_back(InFlag);
933 // FIXME: Do not generate X86ISD::TAILCALL for now.
934 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
935 InFlag = Chain.getValue(1);
938 NodeTys.push_back(MVT::Other); // Returns a chain
939 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
941 Ops.push_back(Chain);
942 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
943 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
944 Ops.push_back(InFlag);
945 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
946 InFlag = Chain.getValue(1);
949 if (RetTyVT != MVT::isVoid) {
951 default: assert(0 && "Unknown value type to return!");
954 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
955 Chain = RetVal.getValue(1);
956 if (RetTyVT == MVT::i1)
957 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
960 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
961 Chain = RetVal.getValue(1);
964 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
965 Chain = RetVal.getValue(1);
968 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
969 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
971 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
972 Chain = Hi.getValue(1);
977 std::vector<MVT::ValueType> Tys;
978 Tys.push_back(MVT::f64);
979 Tys.push_back(MVT::Other);
980 Tys.push_back(MVT::Flag);
981 std::vector<SDOperand> Ops;
982 Ops.push_back(Chain);
983 Ops.push_back(InFlag);
984 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
985 Chain = RetVal.getValue(1);
986 InFlag = RetVal.getValue(2);
988 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
989 // shouldn't be necessary except that RFP cannot be live across
990 // multiple blocks. When stackifier is fixed, they can be uncoupled.
991 MachineFunction &MF = DAG.getMachineFunction();
992 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
993 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
995 Tys.push_back(MVT::Other);
997 Ops.push_back(Chain);
998 Ops.push_back(RetVal);
999 Ops.push_back(StackSlot);
1000 Ops.push_back(DAG.getValueType(RetTyVT));
1001 Ops.push_back(InFlag);
1002 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
1003 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
1004 DAG.getSrcValue(NULL));
1005 Chain = RetVal.getValue(1);
1008 if (RetTyVT == MVT::f32 && !X86ScalarSSE)
1009 // FIXME: we would really like to remember that this FP_ROUND
1010 // operation is okay to eliminate if we allow excess FP precision.
1011 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
1017 return std::make_pair(RetVal, Chain);
1020 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1021 if (ReturnAddrIndex == 0) {
1022 // Set up a frame object for the return address.
1023 MachineFunction &MF = DAG.getMachineFunction();
1024 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1027 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
1032 std::pair<SDOperand, SDOperand> X86TargetLowering::
1033 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
1034 SelectionDAG &DAG) {
1036 if (Depth) // Depths > 0 not supported yet!
1037 Result = DAG.getConstant(0, getPointerTy());
1039 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
1040 if (!isFrameAddress)
1041 // Just load the return address
1042 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
1043 DAG.getSrcValue(NULL));
1045 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
1046 DAG.getConstant(4, MVT::i32));
1048 return std::make_pair(Result, Chain);
1051 /// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode
1052 /// which corresponds to the condition code.
1053 static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
1055 default: assert(0 && "Unknown X86 conditional code!");
1056 case X86ISD::COND_A: return X86::JA;
1057 case X86ISD::COND_AE: return X86::JAE;
1058 case X86ISD::COND_B: return X86::JB;
1059 case X86ISD::COND_BE: return X86::JBE;
1060 case X86ISD::COND_E: return X86::JE;
1061 case X86ISD::COND_G: return X86::JG;
1062 case X86ISD::COND_GE: return X86::JGE;
1063 case X86ISD::COND_L: return X86::JL;
1064 case X86ISD::COND_LE: return X86::JLE;
1065 case X86ISD::COND_NE: return X86::JNE;
1066 case X86ISD::COND_NO: return X86::JNO;
1067 case X86ISD::COND_NP: return X86::JNP;
1068 case X86ISD::COND_NS: return X86::JNS;
1069 case X86ISD::COND_O: return X86::JO;
1070 case X86ISD::COND_P: return X86::JP;
1071 case X86ISD::COND_S: return X86::JS;
1075 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1076 /// specific condition code. It returns a false if it cannot do a direct
1077 /// translation. X86CC is the translated CondCode. Flip is set to true if the
1078 /// the order of comparison operands should be flipped.
1079 static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC,
1081 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1083 X86CC = X86ISD::COND_INVALID;
1085 switch (SetCCOpcode) {
1087 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1088 case ISD::SETGT: X86CC = X86ISD::COND_G; break;
1089 case ISD::SETGE: X86CC = X86ISD::COND_GE; break;
1090 case ISD::SETLT: X86CC = X86ISD::COND_L; break;
1091 case ISD::SETLE: X86CC = X86ISD::COND_LE; break;
1092 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1093 case ISD::SETULT: X86CC = X86ISD::COND_B; break;
1094 case ISD::SETUGT: X86CC = X86ISD::COND_A; break;
1095 case ISD::SETULE: X86CC = X86ISD::COND_BE; break;
1096 case ISD::SETUGE: X86CC = X86ISD::COND_AE; break;
1099 // On a floating point condition, the flags are set as follows:
1101 // 0 | 0 | 0 | X > Y
1102 // 0 | 0 | 1 | X < Y
1103 // 1 | 0 | 0 | X == Y
1104 // 1 | 1 | 1 | unordered
1105 switch (SetCCOpcode) {
1108 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1109 case ISD::SETOLE: Flip = true; // Fallthrough
1111 case ISD::SETGT: X86CC = X86ISD::COND_A; break;
1112 case ISD::SETOLT: Flip = true; // Fallthrough
1114 case ISD::SETGE: X86CC = X86ISD::COND_AE; break;
1115 case ISD::SETUGE: Flip = true; // Fallthrough
1117 case ISD::SETLT: X86CC = X86ISD::COND_B; break;
1118 case ISD::SETUGT: Flip = true; // Fallthrough
1120 case ISD::SETLE: X86CC = X86ISD::COND_BE; break;
1122 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1123 case ISD::SETUO: X86CC = X86ISD::COND_P; break;
1124 case ISD::SETO: X86CC = X86ISD::COND_NP; break;
1128 return X86CC != X86ISD::COND_INVALID;
1131 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1132 /// code. Current x86 isa includes the following FP cmov instructions:
1133 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1134 static bool hasFPCMov(unsigned X86CC) {
1138 case X86ISD::COND_B:
1139 case X86ISD::COND_BE:
1140 case X86ISD::COND_E:
1141 case X86ISD::COND_P:
1142 case X86ISD::COND_A:
1143 case X86ISD::COND_AE:
1144 case X86ISD::COND_NE:
1145 case X86ISD::COND_NP:
1151 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1152 MachineBasicBlock *BB) {
1153 switch (MI->getOpcode()) {
1154 default: assert(false && "Unexpected instr type to insert");
1155 case X86::CMOV_FR32:
1156 case X86::CMOV_FR64: {
1157 // To "insert" a SELECT_CC instruction, we actually have to insert the
1158 // diamond control-flow pattern. The incoming instruction knows the
1159 // destination vreg to set, the condition code register to branch on, the
1160 // true/false values to select between, and a branch opcode to use.
1161 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1162 ilist<MachineBasicBlock>::iterator It = BB;
1168 // cmpTY ccX, r1, r2
1170 // fallthrough --> copy0MBB
1171 MachineBasicBlock *thisMBB = BB;
1172 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1173 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1174 unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
1175 BuildMI(BB, Opc, 1).addMBB(sinkMBB);
1176 MachineFunction *F = BB->getParent();
1177 F->getBasicBlockList().insert(It, copy0MBB);
1178 F->getBasicBlockList().insert(It, sinkMBB);
1179 // Update machine-CFG edges
1180 BB->addSuccessor(copy0MBB);
1181 BB->addSuccessor(sinkMBB);
1184 // %FalseValue = ...
1185 // # fallthrough to sinkMBB
1188 // Update machine-CFG edges
1189 BB->addSuccessor(sinkMBB);
1192 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1195 BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
1196 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1197 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1199 delete MI; // The pseudo instruction is gone now.
1203 case X86::FP_TO_INT16_IN_MEM:
1204 case X86::FP_TO_INT32_IN_MEM:
1205 case X86::FP_TO_INT64_IN_MEM: {
1206 // Change the floating point control register to use "round towards zero"
1207 // mode when truncating to an integer value.
1208 MachineFunction *F = BB->getParent();
1209 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1210 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
1212 // Load the old value of the high byte of the control word...
1214 F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass);
1215 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
1217 // Set the high part to be round to zero...
1218 addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
1220 // Reload the modified control word now...
1221 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1223 // Restore the memory image of control word to original value
1224 addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
1226 // Get the X86 opcode to use.
1228 switch (MI->getOpcode()) {
1229 default: assert(0 && "illegal opcode!");
1230 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
1231 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
1232 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
1236 MachineOperand &Op = MI->getOperand(0);
1237 if (Op.isRegister()) {
1238 AM.BaseType = X86AddressMode::RegBase;
1239 AM.Base.Reg = Op.getReg();
1241 AM.BaseType = X86AddressMode::FrameIndexBase;
1242 AM.Base.FrameIndex = Op.getFrameIndex();
1244 Op = MI->getOperand(1);
1245 if (Op.isImmediate())
1246 AM.Scale = Op.getImmedValue();
1247 Op = MI->getOperand(2);
1248 if (Op.isImmediate())
1249 AM.IndexReg = Op.getImmedValue();
1250 Op = MI->getOperand(3);
1251 if (Op.isGlobalAddress()) {
1252 AM.GV = Op.getGlobal();
1254 AM.Disp = Op.getImmedValue();
1256 addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
1258 // Reload the original control word now.
1259 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1261 delete MI; // The pseudo instruction is gone now.
1268 //===----------------------------------------------------------------------===//
1269 // X86 Custom Lowering Hooks
1270 //===----------------------------------------------------------------------===//
1272 /// LowerOperation - Provide custom lowering hooks for some operations.
1274 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1275 switch (Op.getOpcode()) {
1276 default: assert(0 && "Should not custom lower this!");
1277 case ISD::SHL_PARTS:
1278 case ISD::SRA_PARTS:
1279 case ISD::SRL_PARTS: {
1280 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1281 "Not an i64 shift!");
1282 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
1283 SDOperand ShOpLo = Op.getOperand(0);
1284 SDOperand ShOpHi = Op.getOperand(1);
1285 SDOperand ShAmt = Op.getOperand(2);
1286 SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
1287 DAG.getConstant(31, MVT::i8))
1288 : DAG.getConstant(0, MVT::i32);
1290 SDOperand Tmp2, Tmp3;
1291 if (Op.getOpcode() == ISD::SHL_PARTS) {
1292 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
1293 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
1295 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
1296 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
1299 SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
1300 ShAmt, DAG.getConstant(32, MVT::i8));
1303 SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1305 std::vector<MVT::ValueType> Tys;
1306 Tys.push_back(MVT::i32);
1307 Tys.push_back(MVT::Flag);
1308 std::vector<SDOperand> Ops;
1309 if (Op.getOpcode() == ISD::SHL_PARTS) {
1310 Ops.push_back(Tmp2);
1311 Ops.push_back(Tmp3);
1313 Ops.push_back(InFlag);
1314 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1315 InFlag = Hi.getValue(1);
1318 Ops.push_back(Tmp3);
1319 Ops.push_back(Tmp1);
1321 Ops.push_back(InFlag);
1322 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1324 Ops.push_back(Tmp2);
1325 Ops.push_back(Tmp3);
1327 Ops.push_back(InFlag);
1328 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1329 InFlag = Lo.getValue(1);
1332 Ops.push_back(Tmp3);
1333 Ops.push_back(Tmp1);
1335 Ops.push_back(InFlag);
1336 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1340 Tys.push_back(MVT::i32);
1341 Tys.push_back(MVT::i32);
1345 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1347 case ISD::SINT_TO_FP: {
1348 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
1349 Op.getOperand(0).getValueType() >= MVT::i16 &&
1350 "Unknown SINT_TO_FP to lower!");
1353 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
1354 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
1355 MachineFunction &MF = DAG.getMachineFunction();
1356 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1357 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1358 SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other,
1359 DAG.getEntryNode(), Op.getOperand(0),
1360 StackSlot, DAG.getSrcValue(NULL));
1363 std::vector<MVT::ValueType> Tys;
1364 Tys.push_back(MVT::f64);
1365 Tys.push_back(MVT::Other);
1366 if (X86ScalarSSE) Tys.push_back(MVT::Flag);
1367 std::vector<SDOperand> Ops;
1368 Ops.push_back(Chain);
1369 Ops.push_back(StackSlot);
1370 Ops.push_back(DAG.getValueType(SrcVT));
1371 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
1375 Chain = Result.getValue(1);
1376 SDOperand InFlag = Result.getValue(2);
1378 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
1379 // shouldn't be necessary except that RFP cannot be live across
1380 // multiple blocks. When stackifier is fixed, they can be uncoupled.
1381 MachineFunction &MF = DAG.getMachineFunction();
1382 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
1383 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1384 std::vector<MVT::ValueType> Tys;
1385 Tys.push_back(MVT::Other);
1386 std::vector<SDOperand> Ops;
1387 Ops.push_back(Chain);
1388 Ops.push_back(Result);
1389 Ops.push_back(StackSlot);
1390 Ops.push_back(DAG.getValueType(Op.getValueType()));
1391 Ops.push_back(InFlag);
1392 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
1393 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
1394 DAG.getSrcValue(NULL));
1399 case ISD::FP_TO_SINT: {
1400 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
1401 "Unknown FP_TO_SINT to lower!");
1402 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
1404 MachineFunction &MF = DAG.getMachineFunction();
1405 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
1406 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1407 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1410 switch (Op.getValueType()) {
1411 default: assert(0 && "Invalid FP_TO_SINT to lower!");
1412 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
1413 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
1414 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
1417 SDOperand Chain = DAG.getEntryNode();
1418 SDOperand Value = Op.getOperand(0);
1420 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
1421 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, StackSlot,
1422 DAG.getSrcValue(0));
1423 std::vector<MVT::ValueType> Tys;
1424 Tys.push_back(MVT::f64);
1425 Tys.push_back(MVT::Other);
1426 std::vector<SDOperand> Ops;
1427 Ops.push_back(Chain);
1428 Ops.push_back(StackSlot);
1429 Ops.push_back(DAG.getValueType(Op.getOperand(0).getValueType()));
1430 Value = DAG.getNode(X86ISD::FLD, Tys, Ops);
1431 Chain = Value.getValue(1);
1432 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1433 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1436 // Build the FP_TO_INT*_IN_MEM
1437 std::vector<SDOperand> Ops;
1438 Ops.push_back(Chain);
1439 Ops.push_back(Value);
1440 Ops.push_back(StackSlot);
1441 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
1444 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
1445 DAG.getSrcValue(NULL));
1447 case ISD::READCYCLECOUNTER: {
1448 std::vector<MVT::ValueType> Tys;
1449 Tys.push_back(MVT::Other);
1450 Tys.push_back(MVT::Flag);
1451 std::vector<SDOperand> Ops;
1452 Ops.push_back(Op.getOperand(0));
1453 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
1455 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
1456 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
1457 MVT::i32, Ops[0].getValue(2)));
1458 Ops.push_back(Ops[1].getValue(1));
1459 Tys[0] = Tys[1] = MVT::i32;
1460 Tys.push_back(MVT::Other);
1461 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1464 MVT::ValueType VT = Op.getValueType();
1465 const Type *OpNTy = MVT::getTypeForValueType(VT);
1466 std::vector<Constant*> CV;
1467 if (VT == MVT::f64) {
1468 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
1469 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1471 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
1472 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1473 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1474 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1476 Constant *CS = ConstantStruct::get(CV);
1477 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
1479 = DAG.getNode(X86ISD::LOAD_PACK,
1480 VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
1481 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
1484 MVT::ValueType VT = Op.getValueType();
1485 const Type *OpNTy = MVT::getTypeForValueType(VT);
1486 std::vector<Constant*> CV;
1487 if (VT == MVT::f64) {
1488 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
1489 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1491 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
1492 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1493 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1494 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1496 Constant *CS = ConstantStruct::get(CV);
1497 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
1499 = DAG.getNode(X86ISD::LOAD_PACK,
1500 VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
1501 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
1504 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
1506 SDOperand CC = Op.getOperand(2);
1507 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1508 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
1511 if (translateX86CC(CC, isFP, X86CC, Flip)) {
1513 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1514 Op.getOperand(1), Op.getOperand(0));
1516 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1517 Op.getOperand(0), Op.getOperand(1));
1518 return DAG.getNode(X86ISD::SETCC, MVT::i8,
1519 DAG.getConstant(X86CC, MVT::i8), Cond);
1521 assert(isFP && "Illegal integer SetCC!");
1523 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1524 Op.getOperand(0), Op.getOperand(1));
1525 std::vector<MVT::ValueType> Tys;
1526 std::vector<SDOperand> Ops;
1527 switch (SetCCOpcode) {
1528 default: assert(false && "Illegal floating point SetCC!");
1529 case ISD::SETOEQ: { // !PF & ZF
1530 Tys.push_back(MVT::i8);
1531 Tys.push_back(MVT::Flag);
1532 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1533 Ops.push_back(Cond);
1534 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1535 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1536 DAG.getConstant(X86ISD::COND_E, MVT::i8),
1538 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1540 case ISD::SETUNE: { // PF | !ZF
1541 Tys.push_back(MVT::i8);
1542 Tys.push_back(MVT::Flag);
1543 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1544 Ops.push_back(Cond);
1545 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1546 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1547 DAG.getConstant(X86ISD::COND_NE, MVT::i8),
1549 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1555 MVT::ValueType VT = Op.getValueType();
1556 bool isFP = MVT::isFloatingPoint(VT);
1557 bool isFPStack = isFP && !X86ScalarSSE;
1558 bool isFPSSE = isFP && X86ScalarSSE;
1559 bool addTest = false;
1560 SDOperand Op0 = Op.getOperand(0);
1562 if (Op0.getOpcode() == ISD::SETCC)
1563 Op0 = LowerOperation(Op0, DAG);
1565 if (Op0.getOpcode() == X86ISD::SETCC) {
1566 // If condition flag is set by a X86ISD::CMP, then make a copy of it
1567 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
1568 // have another use it will be eliminated.
1569 // If the X86ISD::SETCC has more than one use, then it's probably better
1570 // to use a test instead of duplicating the X86ISD::CMP (for register
1571 // pressure reason).
1572 if (Op0.getOperand(1).getOpcode() == X86ISD::CMP) {
1573 if (!Op0.hasOneUse()) {
1574 std::vector<MVT::ValueType> Tys;
1575 for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i)
1576 Tys.push_back(Op0.Val->getValueType(i));
1577 std::vector<SDOperand> Ops;
1578 for (unsigned i = 0; i < Op0.getNumOperands(); ++i)
1579 Ops.push_back(Op0.getOperand(i));
1580 Op0 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1583 CC = Op0.getOperand(0);
1584 Cond = Op0.getOperand(1);
1585 // Make a copy as flag result cannot be used by more than one.
1586 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1587 Cond.getOperand(0), Cond.getOperand(1));
1589 isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
1596 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1597 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
1600 std::vector<MVT::ValueType> Tys;
1601 Tys.push_back(Op.getValueType());
1602 Tys.push_back(MVT::Flag);
1603 std::vector<SDOperand> Ops;
1604 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
1605 // condition is true.
1606 Ops.push_back(Op.getOperand(2));
1607 Ops.push_back(Op.getOperand(1));
1609 Ops.push_back(Cond);
1610 return DAG.getNode(X86ISD::CMOV, Tys, Ops);
1613 bool addTest = false;
1614 SDOperand Cond = Op.getOperand(1);
1615 SDOperand Dest = Op.getOperand(2);
1617 if (Cond.getOpcode() == ISD::SETCC)
1618 Cond = LowerOperation(Cond, DAG);
1620 if (Cond.getOpcode() == X86ISD::SETCC) {
1621 // If condition flag is set by a X86ISD::CMP, then make a copy of it
1622 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
1623 // have another use it will be eliminated.
1624 // If the X86ISD::SETCC has more than one use, then it's probably better
1625 // to use a test instead of duplicating the X86ISD::CMP (for register
1626 // pressure reason).
1627 if (Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
1628 if (!Cond.hasOneUse()) {
1629 std::vector<MVT::ValueType> Tys;
1630 for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i)
1631 Tys.push_back(Cond.Val->getValueType(i));
1632 std::vector<SDOperand> Ops;
1633 for (unsigned i = 0; i < Cond.getNumOperands(); ++i)
1634 Ops.push_back(Cond.getOperand(i));
1635 Cond = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1638 CC = Cond.getOperand(0);
1639 Cond = Cond.getOperand(1);
1640 // Make a copy as flag result cannot be used by more than one.
1641 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1642 Cond.getOperand(0), Cond.getOperand(1));
1649 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1650 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1652 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
1653 Op.getOperand(0), Op.getOperand(2), CC, Cond);
1657 SDOperand Chain = Op.getOperand(0);
1659 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1660 if (Align == 0) Align = 1;
1662 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
1663 // If not DWORD aligned, call memset if size is less than the threshold.
1664 // It knows how to align to the right boundary first.
1665 if ((Align & 3) != 0 &&
1666 !(I && I->getValue() >= Subtarget->getMinRepStrSizeThreshold())) {
1667 MVT::ValueType IntPtr = getPointerTy();
1668 const Type *IntPtrTy = getTargetData().getIntPtrType();
1669 std::vector<std::pair<SDOperand, const Type*> > Args;
1670 Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy));
1671 // Extend the ubyte argument to be an int value for the call.
1672 SDOperand Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
1673 Args.push_back(std::make_pair(Val, IntPtrTy));
1674 Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy));
1675 std::pair<SDOperand,SDOperand> CallResult =
1676 LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false,
1677 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
1678 return CallResult.second;
1683 if (ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2))) {
1685 unsigned Val = ValC->getValue() & 255;
1687 // If the value is a constant, then we can potentially use larger sets.
1688 switch (Align & 3) {
1689 case 2: // WORD aligned
1692 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1694 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1695 DAG.getConstant(1, MVT::i8));
1696 Val = (Val << 8) | Val;
1699 case 0: // DWORD aligned
1702 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1704 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1705 DAG.getConstant(2, MVT::i8));
1706 Val = (Val << 8) | Val;
1707 Val = (Val << 16) | Val;
1710 default: // Byte aligned
1712 Count = Op.getOperand(3);
1717 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
1719 InFlag = Chain.getValue(1);
1722 Count = Op.getOperand(3);
1723 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
1724 InFlag = Chain.getValue(1);
1727 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1728 InFlag = Chain.getValue(1);
1729 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1730 InFlag = Chain.getValue(1);
1732 return DAG.getNode(X86ISD::REP_STOS, MVT::Other, Chain,
1733 DAG.getValueType(AVT), InFlag);
1736 SDOperand Chain = Op.getOperand(0);
1738 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1739 if (Align == 0) Align = 1;
1741 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
1742 // If not DWORD aligned, call memcpy if size is less than the threshold.
1743 // It knows how to align to the right boundary first.
1744 if ((Align & 3) != 0 &&
1745 !(I && I->getValue() >= Subtarget->getMinRepStrSizeThreshold())) {
1746 MVT::ValueType IntPtr = getPointerTy();
1747 const Type *IntPtrTy = getTargetData().getIntPtrType();
1748 std::vector<std::pair<SDOperand, const Type*> > Args;
1749 Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy));
1750 Args.push_back(std::make_pair(Op.getOperand(2), IntPtrTy));
1751 Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy));
1752 std::pair<SDOperand,SDOperand> CallResult =
1753 LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false,
1754 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
1755 return CallResult.second;
1760 switch (Align & 3) {
1761 case 2: // WORD aligned
1764 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1766 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1768 case 0: // DWORD aligned
1771 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1773 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1774 DAG.getConstant(2, MVT::i8));
1776 default: // Byte aligned
1778 Count = Op.getOperand(3);
1783 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1784 InFlag = Chain.getValue(1);
1785 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1786 InFlag = Chain.getValue(1);
1787 Chain = DAG.getCopyToReg(Chain, X86::ESI, Op.getOperand(2), InFlag);
1788 InFlag = Chain.getValue(1);
1790 return DAG.getNode(X86ISD::REP_MOVS, MVT::Other, Chain,
1791 DAG.getValueType(AVT), InFlag);
1793 case ISD::ConstantPool: {
1794 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1796 DAG.getTargetConstantPool(CP->get(), getPointerTy(), CP->getAlignment());
1797 // Only lower ConstantPool on Darwin.
1798 if (getTargetMachine().
1799 getSubtarget<X86Subtarget>().isTargetDarwin()) {
1800 // With PIC, the address is actually $g + Offset.
1802 Result = DAG.getNode(ISD::ADD, getPointerTy(),
1803 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
1808 case ISD::GlobalAddress: {
1810 // Only lower GlobalAddress on Darwin.
1811 if (getTargetMachine().
1812 getSubtarget<X86Subtarget>().isTargetDarwin()) {
1813 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1814 SDOperand Addr = DAG.getTargetGlobalAddress(GV, getPointerTy());
1815 // With PIC, the address is actually $g + Offset.
1817 Addr = DAG.getNode(ISD::ADD, getPointerTy(),
1818 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Addr);
1820 // For Darwin, external and weak symbols are indirect, so we want to load
1821 // the value at address GV, not the value of GV itself. This means that
1822 // the GlobalAddress must be in the base or index register of the address,
1823 // not the GV offset field.
1824 if (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
1825 (GV->isExternal() && !GV->hasNotBeenReadFromBytecode()))
1826 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(),
1827 Addr, DAG.getSrcValue(NULL));
1832 case ISD::VASTART: {
1833 // vastart just stores the address of the VarArgsFrameIndex slot into the
1834 // memory location argument.
1835 // FIXME: Replace MVT::i32 with PointerTy
1836 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
1837 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
1838 Op.getOperand(1), Op.getOperand(2));
1843 switch(Op.getNumOperands()) {
1845 assert(0 && "Do not know how to return this many arguments!");
1848 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
1849 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1851 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1852 if (MVT::isInteger(ArgVT))
1853 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EAX, Op.getOperand(1),
1855 else if (!X86ScalarSSE) {
1856 std::vector<MVT::ValueType> Tys;
1857 Tys.push_back(MVT::Other);
1858 Tys.push_back(MVT::Flag);
1859 std::vector<SDOperand> Ops;
1860 Ops.push_back(Op.getOperand(0));
1861 Ops.push_back(Op.getOperand(1));
1862 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
1865 SDOperand Chain = Op.getOperand(0);
1866 SDOperand Value = Op.getOperand(1);
1868 if (Value.getOpcode() == ISD::LOAD &&
1869 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
1870 Chain = Value.getOperand(0);
1871 MemLoc = Value.getOperand(1);
1873 // Spill the value to memory and reload it into top of stack.
1874 unsigned Size = MVT::getSizeInBits(ArgVT)/8;
1875 MachineFunction &MF = DAG.getMachineFunction();
1876 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1877 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
1878 Chain = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0),
1879 Value, MemLoc, DAG.getSrcValue(0));
1881 std::vector<MVT::ValueType> Tys;
1882 Tys.push_back(MVT::f64);
1883 Tys.push_back(MVT::Other);
1884 std::vector<SDOperand> Ops;
1885 Ops.push_back(Chain);
1886 Ops.push_back(MemLoc);
1887 Ops.push_back(DAG.getValueType(ArgVT));
1888 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
1890 Tys.push_back(MVT::Other);
1891 Tys.push_back(MVT::Flag);
1893 Ops.push_back(Copy.getValue(1));
1894 Ops.push_back(Copy);
1895 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
1900 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2),
1902 Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1));
1905 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
1906 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
1912 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1914 default: return NULL;
1915 case X86ISD::SHLD: return "X86ISD::SHLD";
1916 case X86ISD::SHRD: return "X86ISD::SHRD";
1917 case X86ISD::FAND: return "X86ISD::FAND";
1918 case X86ISD::FXOR: return "X86ISD::FXOR";
1919 case X86ISD::FILD: return "X86ISD::FILD";
1920 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
1921 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
1922 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
1923 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
1924 case X86ISD::FLD: return "X86ISD::FLD";
1925 case X86ISD::FST: return "X86ISD::FST";
1926 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
1927 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
1928 case X86ISD::CALL: return "X86ISD::CALL";
1929 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
1930 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
1931 case X86ISD::CMP: return "X86ISD::CMP";
1932 case X86ISD::TEST: return "X86ISD::TEST";
1933 case X86ISD::SETCC: return "X86ISD::SETCC";
1934 case X86ISD::CMOV: return "X86ISD::CMOV";
1935 case X86ISD::BRCOND: return "X86ISD::BRCOND";
1936 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
1937 case X86ISD::REP_STOS: return "X86ISD::RET_STOS";
1938 case X86ISD::REP_MOVS: return "X86ISD::RET_MOVS";
1939 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
1940 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
1944 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1946 uint64_t &KnownZero,
1948 unsigned Depth) const {
1950 unsigned Opc = Op.getOpcode();
1951 KnownZero = KnownOne = 0; // Don't know anything.
1955 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
1958 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
1963 std::vector<unsigned> X86TargetLowering::
1964 getRegForInlineAsmConstraint(const std::string &Constraint) const {
1965 if (Constraint.size() == 1) {
1966 // FIXME: not handling fp-stack yet!
1967 // FIXME: not handling MMX registers yet ('y' constraint).
1968 switch (Constraint[0]) { // GCC X86 Constraint Letters
1969 default: break; // Unknown constriant letter
1970 case 'r': // GENERAL_REGS
1971 case 'R': // LEGACY_REGS
1972 return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX,
1973 X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
1974 case 'l': // INDEX_REGS
1975 return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX,
1976 X86::ESI, X86::EDI, X86::EBP, 0);
1977 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
1979 return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0);
1980 case 'x': // SSE_REGS if SSE1 allowed
1981 if (Subtarget->hasSSE1())
1982 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1983 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
1985 return std::vector<unsigned>();
1986 case 'Y': // SSE_REGS if SSE2 allowed
1987 if (Subtarget->hasSSE2())
1988 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1989 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
1991 return std::vector<unsigned>();
1995 // Handle explicit register names.
1996 return TargetLowering::getRegForInlineAsmConstraint(Constraint);