1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/GlobalAlias.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/PseudoSourceValue.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/SmallSet.h"
38 #include "llvm/ADT/StringExtras.h"
39 #include "llvm/Support/CommandLine.h"
43 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
45 // Forward declarations.
46 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
49 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
50 : TargetLowering(TM) {
51 Subtarget = &TM.getSubtarget<X86Subtarget>();
52 X86ScalarSSEf64 = Subtarget->hasSSE2();
53 X86ScalarSSEf32 = Subtarget->hasSSE1();
54 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
56 RegInfo = TM.getRegisterInfo();
59 // Set up the TargetLowering object.
61 // X86 is weird, it always uses i8 for shift amounts and setcc results.
62 setShiftAmountType(MVT::i8);
63 setBooleanContents(ZeroOrOneBooleanContent);
64 setSchedulingPreference(SchedulingForRegPressure);
65 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
66 setStackPointerRegisterToSaveRestore(X86StackPtr);
68 if (Subtarget->isTargetDarwin()) {
69 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
70 setUseUnderscoreSetJmp(false);
71 setUseUnderscoreLongJmp(false);
72 } else if (Subtarget->isTargetMingw()) {
73 // MS runtime is weird: it exports _setjmp, but longjmp!
74 setUseUnderscoreSetJmp(true);
75 setUseUnderscoreLongJmp(false);
77 setUseUnderscoreSetJmp(true);
78 setUseUnderscoreLongJmp(true);
81 // Set up the register classes.
82 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
83 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
84 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
85 if (Subtarget->is64Bit())
86 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
90 // We don't accept any truncstore of integer registers.
91 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
92 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
93 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
94 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
95 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
96 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
98 // SETOEQ and SETUNE require checking two conditions.
99 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
100 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
101 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
102 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
103 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
104 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
106 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
108 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
109 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
110 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
112 if (Subtarget->is64Bit()) {
113 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
114 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
115 } else if (!UseSoftFloat) {
116 if (X86ScalarSSEf64) {
117 // We have an impenetrably clever algorithm for ui64->double only.
118 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
120 // We have an algorithm for SSE2, and we turn this into a 64-bit
121 // FILD for other targets.
122 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
125 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
127 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
128 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
131 // SSE has no i16 to fp conversion, only i32
132 if (X86ScalarSSEf32) {
133 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
134 // f32 and f64 cases are Legal, f80 case is not
135 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
137 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
138 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
141 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
142 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
145 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
146 // are Legal, f80 is custom lowered.
147 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
148 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
150 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
152 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
153 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
155 if (X86ScalarSSEf32) {
156 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
157 // f32 and f64 cases are Legal, f80 case is not
158 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
160 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
161 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
164 // Handle FP_TO_UINT by promoting the destination to a larger signed
166 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
167 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
168 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
170 if (Subtarget->is64Bit()) {
171 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
172 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
173 } else if (!UseSoftFloat) {
174 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
175 // Expand FP_TO_UINT into a select.
176 // FIXME: We would like to use a Custom expander here eventually to do
177 // the optimal thing for SSE vs. the default expansion in the legalizer.
178 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
180 // With SSE3 we can use fisttpll to convert to a signed i64; without
181 // SSE, we're stuck with a fistpll.
182 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
185 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
186 if (!X86ScalarSSEf64) {
187 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
188 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
191 // Scalar integer divide and remainder are lowered to use operations that
192 // produce two results, to match the available instructions. This exposes
193 // the two-result form to trivial CSE, which is able to combine x/y and x%y
194 // into a single instruction.
196 // Scalar integer multiply-high is also lowered to use two-result
197 // operations, to match the available instructions. However, plain multiply
198 // (low) operations are left as Legal, as there are single-result
199 // instructions for this in x86. Using the two-result multiply instructions
200 // when both high and low results are needed must be arranged by dagcombine.
201 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
202 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
203 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
204 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
205 setOperationAction(ISD::SREM , MVT::i8 , Expand);
206 setOperationAction(ISD::UREM , MVT::i8 , Expand);
207 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
208 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
209 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
210 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
211 setOperationAction(ISD::SREM , MVT::i16 , Expand);
212 setOperationAction(ISD::UREM , MVT::i16 , Expand);
213 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
214 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
215 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
216 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
217 setOperationAction(ISD::SREM , MVT::i32 , Expand);
218 setOperationAction(ISD::UREM , MVT::i32 , Expand);
219 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
220 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
221 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
222 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
223 setOperationAction(ISD::SREM , MVT::i64 , Expand);
224 setOperationAction(ISD::UREM , MVT::i64 , Expand);
226 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
227 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
228 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
229 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
230 if (Subtarget->is64Bit())
231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
232 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
233 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
234 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
235 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
236 setOperationAction(ISD::FREM , MVT::f32 , Expand);
237 setOperationAction(ISD::FREM , MVT::f64 , Expand);
238 setOperationAction(ISD::FREM , MVT::f80 , Expand);
239 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
241 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
242 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
243 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
244 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
245 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
246 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
247 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
248 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
249 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
250 if (Subtarget->is64Bit()) {
251 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
252 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
253 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
256 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
257 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
259 // These should be promoted to a larger select which is supported.
260 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
261 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
262 // X86 wants to expand cmov itself.
263 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
264 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
265 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
266 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
267 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
268 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
269 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
270 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
271 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
272 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
273 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
274 if (Subtarget->is64Bit()) {
275 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
276 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
278 // X86 ret instruction may pop stack.
279 setOperationAction(ISD::RET , MVT::Other, Custom);
280 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
283 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
284 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
285 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
286 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
287 if (Subtarget->is64Bit())
288 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
289 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
290 if (Subtarget->is64Bit()) {
291 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
292 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
293 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
294 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
296 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
297 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
298 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
299 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
300 if (Subtarget->is64Bit()) {
301 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
302 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
303 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
306 if (Subtarget->hasSSE1())
307 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
309 if (!Subtarget->hasSSE2())
310 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
312 // Expand certain atomics
313 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
314 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
315 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
316 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
318 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
319 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
320 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
321 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
323 if (!Subtarget->is64Bit()) {
324 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
325 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
326 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
327 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
328 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
329 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
330 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
333 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
334 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
335 // FIXME - use subtarget debug flags
336 if (!Subtarget->isTargetDarwin() &&
337 !Subtarget->isTargetELF() &&
338 !Subtarget->isTargetCygMing()) {
339 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
340 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
343 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
344 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
345 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
346 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
347 if (Subtarget->is64Bit()) {
348 setExceptionPointerRegister(X86::RAX);
349 setExceptionSelectorRegister(X86::RDX);
351 setExceptionPointerRegister(X86::EAX);
352 setExceptionSelectorRegister(X86::EDX);
354 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
355 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
357 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
359 setOperationAction(ISD::TRAP, MVT::Other, Legal);
361 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
362 setOperationAction(ISD::VASTART , MVT::Other, Custom);
363 setOperationAction(ISD::VAEND , MVT::Other, Expand);
364 if (Subtarget->is64Bit()) {
365 setOperationAction(ISD::VAARG , MVT::Other, Custom);
366 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
368 setOperationAction(ISD::VAARG , MVT::Other, Expand);
369 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
372 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
373 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
374 if (Subtarget->is64Bit())
375 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
376 if (Subtarget->isTargetCygMing())
377 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
379 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
381 if (!UseSoftFloat && X86ScalarSSEf64) {
382 // f32 and f64 use SSE.
383 // Set up the FP register classes.
384 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
385 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
387 // Use ANDPD to simulate FABS.
388 setOperationAction(ISD::FABS , MVT::f64, Custom);
389 setOperationAction(ISD::FABS , MVT::f32, Custom);
391 // Use XORP to simulate FNEG.
392 setOperationAction(ISD::FNEG , MVT::f64, Custom);
393 setOperationAction(ISD::FNEG , MVT::f32, Custom);
395 // Use ANDPD and ORPD to simulate FCOPYSIGN.
396 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
397 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
399 // We don't support sin/cos/fmod
400 setOperationAction(ISD::FSIN , MVT::f64, Expand);
401 setOperationAction(ISD::FCOS , MVT::f64, Expand);
402 setOperationAction(ISD::FSIN , MVT::f32, Expand);
403 setOperationAction(ISD::FCOS , MVT::f32, Expand);
405 // Expand FP immediates into loads from the stack, except for the special
407 addLegalFPImmediate(APFloat(+0.0)); // xorpd
408 addLegalFPImmediate(APFloat(+0.0f)); // xorps
409 } else if (!UseSoftFloat && X86ScalarSSEf32) {
410 // Use SSE for f32, x87 for f64.
411 // Set up the FP register classes.
412 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
413 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
415 // Use ANDPS to simulate FABS.
416 setOperationAction(ISD::FABS , MVT::f32, Custom);
418 // Use XORP to simulate FNEG.
419 setOperationAction(ISD::FNEG , MVT::f32, Custom);
421 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
423 // Use ANDPS and ORPS to simulate FCOPYSIGN.
424 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
425 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
427 // We don't support sin/cos/fmod
428 setOperationAction(ISD::FSIN , MVT::f32, Expand);
429 setOperationAction(ISD::FCOS , MVT::f32, Expand);
431 // Special cases we handle for FP constants.
432 addLegalFPImmediate(APFloat(+0.0f)); // xorps
433 addLegalFPImmediate(APFloat(+0.0)); // FLD0
434 addLegalFPImmediate(APFloat(+1.0)); // FLD1
435 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
436 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
439 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
440 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
442 } else if (!UseSoftFloat) {
443 // f32 and f64 in x87.
444 // Set up the FP register classes.
445 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
446 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
448 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
449 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
450 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
451 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
454 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
455 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
457 addLegalFPImmediate(APFloat(+0.0)); // FLD0
458 addLegalFPImmediate(APFloat(+1.0)); // FLD1
459 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
460 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
461 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
462 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
463 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
464 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
467 // Long double always uses X87.
469 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
470 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
471 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
474 APFloat TmpFlt(+0.0);
475 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
477 addLegalFPImmediate(TmpFlt); // FLD0
479 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
480 APFloat TmpFlt2(+1.0);
481 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
483 addLegalFPImmediate(TmpFlt2); // FLD1
484 TmpFlt2.changeSign();
485 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
489 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
490 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
494 // Always use a library call for pow.
495 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
496 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
497 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
499 setOperationAction(ISD::FLOG, MVT::f80, Expand);
500 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
501 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
502 setOperationAction(ISD::FEXP, MVT::f80, Expand);
503 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
505 // First set operation action for all vector types to either promote
506 // (for widening) or expand (for scalarization). Then we will selectively
507 // turn on ones that can be effectively codegen'd.
508 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
509 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
510 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
511 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
512 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
513 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
514 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
515 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
516 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
517 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
518 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
519 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
520 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
521 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
522 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
523 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
524 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
525 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
526 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
527 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
528 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
529 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
530 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
531 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
532 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
533 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
534 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
560 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
561 // with -msoft-float, disable use of MMX as well.
562 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
563 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
564 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
565 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
566 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
567 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
569 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
570 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
571 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
572 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
574 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
575 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
576 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
577 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
579 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
580 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
582 setOperationAction(ISD::AND, MVT::v8i8, Promote);
583 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
584 setOperationAction(ISD::AND, MVT::v4i16, Promote);
585 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
586 setOperationAction(ISD::AND, MVT::v2i32, Promote);
587 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
588 setOperationAction(ISD::AND, MVT::v1i64, Legal);
590 setOperationAction(ISD::OR, MVT::v8i8, Promote);
591 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
592 setOperationAction(ISD::OR, MVT::v4i16, Promote);
593 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
594 setOperationAction(ISD::OR, MVT::v2i32, Promote);
595 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
596 setOperationAction(ISD::OR, MVT::v1i64, Legal);
598 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
599 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
600 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
601 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
602 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
603 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
604 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
606 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
607 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
608 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
609 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
610 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
611 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
612 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
613 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
614 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
616 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
617 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
618 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
619 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
620 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
622 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
623 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
624 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
625 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
627 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
628 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
629 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
630 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
632 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
634 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
635 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
636 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
637 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
638 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
639 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
642 if (!UseSoftFloat && Subtarget->hasSSE1()) {
643 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
645 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
646 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
647 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
648 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
649 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
650 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
651 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
652 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
653 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
654 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
655 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
656 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
659 if (!UseSoftFloat && Subtarget->hasSSE2()) {
660 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
662 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
663 // registers cannot be used even for integer operations.
664 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
665 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
666 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
667 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
669 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
670 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
671 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
672 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
673 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
674 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
675 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
676 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
677 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
678 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
679 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
680 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
681 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
682 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
683 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
684 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
686 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
687 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
688 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
689 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
691 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
692 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
693 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
694 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
695 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
697 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
698 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
699 MVT VT = (MVT::SimpleValueType)i;
700 // Do not attempt to custom lower non-power-of-2 vectors
701 if (!isPowerOf2_32(VT.getVectorNumElements()))
703 // Do not attempt to custom lower non-128-bit vectors
704 if (!VT.is128BitVector())
706 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
707 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
708 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
711 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
712 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
713 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
714 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
715 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
716 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
718 if (Subtarget->is64Bit()) {
719 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
720 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
723 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
724 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
725 MVT VT = (MVT::SimpleValueType)i;
727 // Do not attempt to promote non-128-bit vectors
728 if (!VT.is128BitVector()) {
731 setOperationAction(ISD::AND, VT, Promote);
732 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
733 setOperationAction(ISD::OR, VT, Promote);
734 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
735 setOperationAction(ISD::XOR, VT, Promote);
736 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
737 setOperationAction(ISD::LOAD, VT, Promote);
738 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
739 setOperationAction(ISD::SELECT, VT, Promote);
740 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
743 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
745 // Custom lower v2i64 and v2f64 selects.
746 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
747 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
748 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
749 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
751 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
752 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
753 if (!DisableMMX && Subtarget->hasMMX()) {
754 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
755 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
759 if (Subtarget->hasSSE41()) {
760 // FIXME: Do we need to handle scalar-to-vector here?
761 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
763 // i8 and i16 vectors are custom , because the source register and source
764 // source memory operand types are not the same width. f32 vectors are
765 // custom since the immediate controlling the insert encodes additional
767 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
768 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
772 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
773 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
774 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
777 if (Subtarget->is64Bit()) {
778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
779 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
783 if (Subtarget->hasSSE42()) {
784 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
787 if (!UseSoftFloat && Subtarget->hasAVX()) {
788 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
789 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
790 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
791 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
793 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
794 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
795 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
796 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
797 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
798 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
799 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
800 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
801 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
802 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
803 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
804 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
805 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
806 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
807 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
809 // Operations to consider commented out -v16i16 v32i8
810 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
812 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
813 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
814 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
815 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
816 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
817 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
818 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
819 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
820 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
821 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
822 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
823 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
825 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
826 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
827 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
828 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
830 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
831 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
832 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
833 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
834 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
836 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
837 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
838 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
839 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
841 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
844 // Not sure we want to do this since there are no 256-bit integer
847 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
848 // This includes 256-bit vectors
849 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
850 MVT VT = (MVT::SimpleValueType)i;
852 // Do not attempt to custom lower non-power-of-2 vectors
853 if (!isPowerOf2_32(VT.getVectorNumElements()))
856 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
857 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
858 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
861 if (Subtarget->is64Bit()) {
862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
863 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
868 // Not sure we want to do this since there are no 256-bit integer
871 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
872 // Including 256-bit vectors
873 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
874 MVT VT = (MVT::SimpleValueType)i;
876 if (!VT.is256BitVector()) {
879 setOperationAction(ISD::AND, VT, Promote);
880 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
881 setOperationAction(ISD::OR, VT, Promote);
882 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
883 setOperationAction(ISD::XOR, VT, Promote);
884 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
885 setOperationAction(ISD::LOAD, VT, Promote);
886 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
887 setOperationAction(ISD::SELECT, VT, Promote);
888 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
891 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
895 // We want to custom lower some of our intrinsics.
896 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
898 // Add/Sub/Mul with overflow operations are custom lowered.
899 setOperationAction(ISD::SADDO, MVT::i32, Custom);
900 setOperationAction(ISD::SADDO, MVT::i64, Custom);
901 setOperationAction(ISD::UADDO, MVT::i32, Custom);
902 setOperationAction(ISD::UADDO, MVT::i64, Custom);
903 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
904 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
905 setOperationAction(ISD::USUBO, MVT::i32, Custom);
906 setOperationAction(ISD::USUBO, MVT::i64, Custom);
907 setOperationAction(ISD::SMULO, MVT::i32, Custom);
908 setOperationAction(ISD::SMULO, MVT::i64, Custom);
910 if (!Subtarget->is64Bit()) {
911 // These libcalls are not available in 32-bit.
912 setLibcallName(RTLIB::SHL_I128, 0);
913 setLibcallName(RTLIB::SRL_I128, 0);
914 setLibcallName(RTLIB::SRA_I128, 0);
917 // We have target-specific dag combine patterns for the following nodes:
918 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
919 setTargetDAGCombine(ISD::BUILD_VECTOR);
920 setTargetDAGCombine(ISD::SELECT);
921 setTargetDAGCombine(ISD::SHL);
922 setTargetDAGCombine(ISD::SRA);
923 setTargetDAGCombine(ISD::SRL);
924 setTargetDAGCombine(ISD::STORE);
925 setTargetDAGCombine(ISD::MEMBARRIER);
926 if (Subtarget->is64Bit())
927 setTargetDAGCombine(ISD::MUL);
929 computeRegisterProperties();
931 // FIXME: These should be based on subtarget info. Plus, the values should
932 // be smaller when we are in optimizing for size mode.
933 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
934 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
935 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
936 allowUnalignedMemoryAccesses = true; // x86 supports it!
937 setPrefLoopAlignment(16);
938 benefitFromCodePlacementOpt = true;
942 MVT X86TargetLowering::getSetCCResultType(MVT VT) const {
947 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
948 /// the desired ByVal argument alignment.
949 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
952 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
953 if (VTy->getBitWidth() == 128)
955 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
956 unsigned EltAlign = 0;
957 getMaxByValAlign(ATy->getElementType(), EltAlign);
958 if (EltAlign > MaxAlign)
960 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
961 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
962 unsigned EltAlign = 0;
963 getMaxByValAlign(STy->getElementType(i), EltAlign);
964 if (EltAlign > MaxAlign)
973 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
974 /// function arguments in the caller parameter area. For X86, aggregates
975 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
976 /// are at 4-byte boundaries.
977 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
978 if (Subtarget->is64Bit()) {
979 // Max of 8 and alignment of type.
980 unsigned TyAlign = TD->getABITypeAlignment(Ty);
987 if (Subtarget->hasSSE1())
988 getMaxByValAlign(Ty, Align);
992 /// getOptimalMemOpType - Returns the target specific optimal type for load
993 /// and store operations as a result of memset, memcpy, and memmove
994 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
997 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
998 bool isSrcConst, bool isSrcStr,
999 SelectionDAG &DAG) const {
1000 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1001 // linux. This is because the stack realignment code can't handle certain
1002 // cases like PR2962. This should be removed when PR2962 is fixed.
1003 const Function *F = DAG.getMachineFunction().getFunction();
1004 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1005 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1006 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1008 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1011 if (Subtarget->is64Bit() && Size >= 8)
1016 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1018 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1019 SelectionDAG &DAG) const {
1020 if (usesGlobalOffsetTable())
1021 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1022 if (!Subtarget->isPICStyleRIPRel())
1023 // This doesn't have DebugLoc associated with it, but is not really the
1024 // same as a Register.
1025 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1030 /// getFunctionAlignment - Return the Log2 alignment of this function.
1031 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1032 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4;
1035 //===----------------------------------------------------------------------===//
1036 // Return Value Calling Convention Implementation
1037 //===----------------------------------------------------------------------===//
1039 #include "X86GenCallingConv.inc"
1041 /// LowerRET - Lower an ISD::RET node.
1042 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
1043 DebugLoc dl = Op.getDebugLoc();
1044 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
1046 SmallVector<CCValAssign, 16> RVLocs;
1047 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1048 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1049 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
1050 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
1052 // If this is the first return lowered for this function, add the regs to the
1053 // liveout set for the function.
1054 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1055 for (unsigned i = 0; i != RVLocs.size(); ++i)
1056 if (RVLocs[i].isRegLoc())
1057 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1059 SDValue Chain = Op.getOperand(0);
1061 // Handle tail call return.
1062 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
1063 if (Chain.getOpcode() == X86ISD::TAILCALL) {
1064 SDValue TailCall = Chain;
1065 SDValue TargetAddress = TailCall.getOperand(1);
1066 SDValue StackAdjustment = TailCall.getOperand(2);
1067 assert(((TargetAddress.getOpcode() == ISD::Register &&
1068 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
1069 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R11)) ||
1070 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
1071 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
1072 "Expecting an global address, external symbol, or register");
1073 assert(StackAdjustment.getOpcode() == ISD::Constant &&
1074 "Expecting a const value");
1076 SmallVector<SDValue,8> Operands;
1077 Operands.push_back(Chain.getOperand(0));
1078 Operands.push_back(TargetAddress);
1079 Operands.push_back(StackAdjustment);
1080 // Copy registers used by the call. Last operand is a flag so it is not
1082 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
1083 Operands.push_back(Chain.getOperand(i));
1085 return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0],
1092 SmallVector<SDValue, 6> RetOps;
1093 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1094 // Operand #1 = Bytes To Pop
1095 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1097 // Copy the result values into the output registers.
1098 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1099 CCValAssign &VA = RVLocs[i];
1100 assert(VA.isRegLoc() && "Can only return in registers!");
1101 SDValue ValToCopy = Op.getOperand(i*2+1);
1103 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1104 // the RET instruction and handled by the FP Stackifier.
1105 if (VA.getLocReg() == X86::ST0 ||
1106 VA.getLocReg() == X86::ST1) {
1107 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1108 // change the value to the FP stack register class.
1109 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1110 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1111 RetOps.push_back(ValToCopy);
1112 // Don't emit a copytoreg.
1116 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1117 // which is returned in RAX / RDX.
1118 if (Subtarget->is64Bit()) {
1119 MVT ValVT = ValToCopy.getValueType();
1120 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1121 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1122 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1123 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1127 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1128 Flag = Chain.getValue(1);
1131 // The x86-64 ABI for returning structs by value requires that we copy
1132 // the sret argument into %rax for the return. We saved the argument into
1133 // a virtual register in the entry block, so now we copy the value out
1135 if (Subtarget->is64Bit() &&
1136 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1137 MachineFunction &MF = DAG.getMachineFunction();
1138 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1139 unsigned Reg = FuncInfo->getSRetReturnReg();
1141 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1142 FuncInfo->setSRetReturnReg(Reg);
1144 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1146 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1147 Flag = Chain.getValue(1);
1150 RetOps[0] = Chain; // Update chain.
1152 // Add the flag if we have it.
1154 RetOps.push_back(Flag);
1156 return DAG.getNode(X86ISD::RET_FLAG, dl,
1157 MVT::Other, &RetOps[0], RetOps.size());
1161 /// LowerCallResult - Lower the result values of an ISD::CALL into the
1162 /// appropriate copies out of appropriate physical registers. This assumes that
1163 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
1164 /// being lowered. The returns a SDNode with the same number of values as the
1166 SDNode *X86TargetLowering::
1167 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
1168 unsigned CallingConv, SelectionDAG &DAG) {
1170 DebugLoc dl = TheCall->getDebugLoc();
1171 // Assign locations to each value returned by this call.
1172 SmallVector<CCValAssign, 16> RVLocs;
1173 bool isVarArg = TheCall->isVarArg();
1174 bool Is64Bit = Subtarget->is64Bit();
1175 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
1176 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
1178 SmallVector<SDValue, 8> ResultVals;
1180 // Copy all of the result registers out of their specified physreg.
1181 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1182 CCValAssign &VA = RVLocs[i];
1183 MVT CopyVT = VA.getValVT();
1185 // If this is x86-64, and we disabled SSE, we can't return FP values
1186 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1187 ((Is64Bit || TheCall->isInreg()) && !Subtarget->hasSSE1())) {
1188 cerr << "SSE register return with SSE disabled\n";
1192 // If this is a call to a function that returns an fp value on the floating
1193 // point stack, but where we prefer to use the value in xmm registers, copy
1194 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1195 if ((VA.getLocReg() == X86::ST0 ||
1196 VA.getLocReg() == X86::ST1) &&
1197 isScalarFPTypeInSSEReg(VA.getValVT())) {
1202 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1203 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1204 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1205 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1206 MVT::v2i64, InFlag).getValue(1);
1207 Val = Chain.getValue(0);
1208 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1209 Val, DAG.getConstant(0, MVT::i64));
1211 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1212 MVT::i64, InFlag).getValue(1);
1213 Val = Chain.getValue(0);
1215 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1217 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1218 CopyVT, InFlag).getValue(1);
1219 Val = Chain.getValue(0);
1221 InFlag = Chain.getValue(2);
1223 if (CopyVT != VA.getValVT()) {
1224 // Round the F80 the right size, which also moves to the appropriate xmm
1226 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1227 // This truncation won't change the value.
1228 DAG.getIntPtrConstant(1));
1231 ResultVals.push_back(Val);
1234 // Merge everything together with a MERGE_VALUES node.
1235 ResultVals.push_back(Chain);
1236 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
1237 &ResultVals[0], ResultVals.size()).getNode();
1241 //===----------------------------------------------------------------------===//
1242 // C & StdCall & Fast Calling Convention implementation
1243 //===----------------------------------------------------------------------===//
1244 // StdCall calling convention seems to be standard for many Windows' API
1245 // routines and around. It differs from C calling convention just a little:
1246 // callee should clean up the stack, not caller. Symbols should be also
1247 // decorated in some fancy way :) It doesn't support any vector arguments.
1248 // For info on fast calling convention see Fast Calling Convention (tail call)
1249 // implementation LowerX86_32FastCCCallTo.
1251 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1253 static bool CallIsStructReturn(CallSDNode *TheCall) {
1254 unsigned NumOps = TheCall->getNumArgs();
1258 return TheCall->getArgFlags(0).isSRet();
1261 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1262 /// return semantics.
1263 static bool ArgsAreStructReturn(SDValue Op) {
1264 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1268 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1271 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1272 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1274 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1278 switch (CallingConv) {
1281 case CallingConv::X86_StdCall:
1282 return !Subtarget->is64Bit();
1283 case CallingConv::X86_FastCall:
1284 return !Subtarget->is64Bit();
1285 case CallingConv::Fast:
1286 return PerformTailCallOpt;
1290 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1291 /// given CallingConvention value.
1292 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1293 if (Subtarget->is64Bit()) {
1294 if (Subtarget->isTargetWin64())
1295 return CC_X86_Win64_C;
1300 if (CC == CallingConv::X86_FastCall)
1301 return CC_X86_32_FastCall;
1302 else if (CC == CallingConv::Fast)
1303 return CC_X86_32_FastCC;
1308 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1309 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1311 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1312 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1313 if (CC == CallingConv::X86_FastCall)
1315 else if (CC == CallingConv::X86_StdCall)
1321 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1322 /// in a register before calling.
1323 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1324 return !IsTailCall && !Is64Bit &&
1325 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1326 Subtarget->isPICStyleGOT();
1329 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1330 /// address to be loaded in a register.
1332 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1333 return !Is64Bit && IsTailCall &&
1334 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1335 Subtarget->isPICStyleGOT();
1338 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1339 /// by "Src" to address "Dst" with size and alignment information specified by
1340 /// the specific parameter attribute. The copy will be passed as a byval
1341 /// function parameter.
1343 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1344 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1346 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1347 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1348 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1351 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1352 const CCValAssign &VA,
1353 MachineFrameInfo *MFI,
1355 SDValue Root, unsigned i) {
1356 // Create the nodes corresponding to a load from this parameter slot.
1357 ISD::ArgFlagsTy Flags =
1358 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1359 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1360 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1362 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1363 // changed with more analysis.
1364 // In case of tail call optimization mark all arguments mutable. Since they
1365 // could be overwritten by lowering of arguments in case of a tail call.
1366 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1367 VA.getLocMemOffset(), isImmutable);
1368 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1369 if (Flags.isByVal())
1371 return DAG.getLoad(VA.getValVT(), Op.getDebugLoc(), Root, FIN,
1372 PseudoSourceValue::getFixedStack(FI), 0);
1376 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1377 MachineFunction &MF = DAG.getMachineFunction();
1378 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1379 DebugLoc dl = Op.getDebugLoc();
1381 const Function* Fn = MF.getFunction();
1382 if (Fn->hasExternalLinkage() &&
1383 Subtarget->isTargetCygMing() &&
1384 Fn->getName() == "main")
1385 FuncInfo->setForceFramePointer(true);
1387 // Decorate the function name.
1388 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1390 MachineFrameInfo *MFI = MF.getFrameInfo();
1391 SDValue Root = Op.getOperand(0);
1392 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1393 unsigned CC = MF.getFunction()->getCallingConv();
1394 bool Is64Bit = Subtarget->is64Bit();
1395 bool IsWin64 = Subtarget->isTargetWin64();
1397 assert(!(isVarArg && CC == CallingConv::Fast) &&
1398 "Var args not supported with calling convention fastcc");
1400 // Assign locations to all of the incoming arguments.
1401 SmallVector<CCValAssign, 16> ArgLocs;
1402 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1403 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
1405 SmallVector<SDValue, 8> ArgValues;
1406 unsigned LastVal = ~0U;
1407 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1408 CCValAssign &VA = ArgLocs[i];
1409 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1411 assert(VA.getValNo() != LastVal &&
1412 "Don't support value assigned to multiple locs yet");
1413 LastVal = VA.getValNo();
1415 if (VA.isRegLoc()) {
1416 MVT RegVT = VA.getLocVT();
1417 TargetRegisterClass *RC = NULL;
1418 if (RegVT == MVT::i32)
1419 RC = X86::GR32RegisterClass;
1420 else if (Is64Bit && RegVT == MVT::i64)
1421 RC = X86::GR64RegisterClass;
1422 else if (RegVT == MVT::f32)
1423 RC = X86::FR32RegisterClass;
1424 else if (RegVT == MVT::f64)
1425 RC = X86::FR64RegisterClass;
1426 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1427 RC = X86::VR128RegisterClass;
1428 else if (RegVT.isVector()) {
1429 assert(RegVT.getSizeInBits() == 64);
1431 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1433 // Darwin calling convention passes MMX values in either GPRs or
1434 // XMMs in x86-64. Other targets pass them in memory.
1435 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1436 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1439 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1444 assert(0 && "Unknown argument type!");
1447 unsigned Reg = DAG.getMachineFunction().addLiveIn(VA.getLocReg(), RC);
1448 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1450 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1451 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1453 if (VA.getLocInfo() == CCValAssign::SExt)
1454 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1455 DAG.getValueType(VA.getValVT()));
1456 else if (VA.getLocInfo() == CCValAssign::ZExt)
1457 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1458 DAG.getValueType(VA.getValVT()));
1460 if (VA.getLocInfo() != CCValAssign::Full)
1461 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1463 // Handle MMX values passed in GPRs.
1464 if (Is64Bit && RegVT != VA.getLocVT()) {
1465 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1466 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
1467 else if (RC == X86::VR128RegisterClass) {
1468 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1469 ArgValue, DAG.getConstant(0, MVT::i64));
1470 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
1474 ArgValues.push_back(ArgValue);
1476 assert(VA.isMemLoc());
1477 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1481 // The x86-64 ABI for returning structs by value requires that we copy
1482 // the sret argument into %rax for the return. Save the argument into
1483 // a virtual register so that we can access it from the return points.
1484 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1485 MachineFunction &MF = DAG.getMachineFunction();
1486 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1487 unsigned Reg = FuncInfo->getSRetReturnReg();
1489 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1490 FuncInfo->setSRetReturnReg(Reg);
1492 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
1493 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
1496 unsigned StackSize = CCInfo.getNextStackOffset();
1497 // align stack specially for tail calls
1498 if (PerformTailCallOpt && CC == CallingConv::Fast)
1499 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1501 // If the function takes variable number of arguments, make a frame index for
1502 // the start of the first vararg value... for expansion of llvm.va_start.
1504 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1505 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1508 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1510 // FIXME: We should really autogenerate these arrays
1511 static const unsigned GPR64ArgRegsWin64[] = {
1512 X86::RCX, X86::RDX, X86::R8, X86::R9
1514 static const unsigned XMMArgRegsWin64[] = {
1515 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1517 static const unsigned GPR64ArgRegs64Bit[] = {
1518 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1520 static const unsigned XMMArgRegs64Bit[] = {
1521 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1522 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1524 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1527 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1528 GPR64ArgRegs = GPR64ArgRegsWin64;
1529 XMMArgRegs = XMMArgRegsWin64;
1531 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1532 GPR64ArgRegs = GPR64ArgRegs64Bit;
1533 XMMArgRegs = XMMArgRegs64Bit;
1535 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1537 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1540 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1542 "SSE register cannot be used when SSE is disabled!");
1543 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1544 "SSE register cannot be used when SSE is disabled!");
1545 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1546 // Kernel mode asks for SSE to be disabled, so don't push them
1548 TotalNumXMMRegs = 0;
1550 // For X86-64, if there are vararg parameters that are passed via
1551 // registers, then we must store them to their spots on the stack so they
1552 // may be loaded by deferencing the result of va_next.
1553 VarArgsGPOffset = NumIntRegs * 8;
1554 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1555 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1556 TotalNumXMMRegs * 16, 16);
1558 // Store the integer parameter registers.
1559 SmallVector<SDValue, 8> MemOps;
1560 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1561 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1562 DAG.getIntPtrConstant(VarArgsGPOffset));
1563 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1564 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1565 X86::GR64RegisterClass);
1566 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
1568 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1569 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1570 MemOps.push_back(Store);
1571 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1572 DAG.getIntPtrConstant(8));
1575 // Now store the XMM (fp + vector) parameter registers.
1576 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1577 DAG.getIntPtrConstant(VarArgsFPOffset));
1578 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1579 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1580 X86::VR128RegisterClass);
1581 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32);
1583 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1584 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1585 MemOps.push_back(Store);
1586 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1587 DAG.getIntPtrConstant(16));
1589 if (!MemOps.empty())
1590 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1591 &MemOps[0], MemOps.size());
1595 ArgValues.push_back(Root);
1597 // Some CCs need callee pop.
1598 if (IsCalleePop(isVarArg, CC)) {
1599 BytesToPopOnReturn = StackSize; // Callee pops everything.
1600 BytesCallerReserves = 0;
1602 BytesToPopOnReturn = 0; // Callee pops nothing.
1603 // If this is an sret function, the return should pop the hidden pointer.
1604 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
1605 BytesToPopOnReturn = 4;
1606 BytesCallerReserves = StackSize;
1610 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1611 if (CC == CallingConv::X86_FastCall)
1612 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1615 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1617 // Return the new list of results.
1618 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1619 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1623 X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
1624 const SDValue &StackPtr,
1625 const CCValAssign &VA,
1627 SDValue Arg, ISD::ArgFlagsTy Flags) {
1628 DebugLoc dl = TheCall->getDebugLoc();
1629 unsigned LocMemOffset = VA.getLocMemOffset();
1630 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1631 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1632 if (Flags.isByVal()) {
1633 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1635 return DAG.getStore(Chain, dl, Arg, PtrOff,
1636 PseudoSourceValue::getStack(), LocMemOffset);
1639 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1640 /// optimization is performed and it is required.
1642 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1643 SDValue &OutRetAddr,
1649 if (!IsTailCall || FPDiff==0) return Chain;
1651 // Adjust the Return address stack slot.
1652 MVT VT = getPointerTy();
1653 OutRetAddr = getReturnAddressFrameIndex(DAG);
1655 // Load the "old" Return address.
1656 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1657 return SDValue(OutRetAddr.getNode(), 1);
1660 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1661 /// optimization is performed and it is required (FPDiff!=0).
1663 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1664 SDValue Chain, SDValue RetAddrFrIdx,
1665 bool Is64Bit, int FPDiff, DebugLoc dl) {
1666 // Store the return address to the appropriate stack slot.
1667 if (!FPDiff) return Chain;
1668 // Calculate the new stack slot for the return address.
1669 int SlotSize = Is64Bit ? 8 : 4;
1670 int NewReturnAddrFI =
1671 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1672 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1673 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1674 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1675 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1679 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1680 MachineFunction &MF = DAG.getMachineFunction();
1681 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1682 SDValue Chain = TheCall->getChain();
1683 unsigned CC = TheCall->getCallingConv();
1684 bool isVarArg = TheCall->isVarArg();
1685 bool IsTailCall = TheCall->isTailCall() &&
1686 CC == CallingConv::Fast && PerformTailCallOpt;
1687 SDValue Callee = TheCall->getCallee();
1688 bool Is64Bit = Subtarget->is64Bit();
1689 bool IsStructRet = CallIsStructReturn(TheCall);
1690 DebugLoc dl = TheCall->getDebugLoc();
1692 assert(!(isVarArg && CC == CallingConv::Fast) &&
1693 "Var args not supported with calling convention fastcc");
1695 // Analyze operands of the call, assigning locations to each operand.
1696 SmallVector<CCValAssign, 16> ArgLocs;
1697 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1698 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
1700 // Get a count of how many bytes are to be pushed on the stack.
1701 unsigned NumBytes = CCInfo.getNextStackOffset();
1702 if (PerformTailCallOpt && CC == CallingConv::Fast)
1703 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1707 // Lower arguments at fp - stackoffset + fpdiff.
1708 unsigned NumBytesCallerPushed =
1709 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1710 FPDiff = NumBytesCallerPushed - NumBytes;
1712 // Set the delta of movement of the returnaddr stackslot.
1713 // But only set if delta is greater than previous delta.
1714 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1715 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1718 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1720 SDValue RetAddrFrIdx;
1721 // Load return adress for tail calls.
1722 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1725 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1726 SmallVector<SDValue, 8> MemOpChains;
1729 // Walk the register/memloc assignments, inserting copies/loads. In the case
1730 // of tail call optimization arguments are handle later.
1731 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1732 CCValAssign &VA = ArgLocs[i];
1733 SDValue Arg = TheCall->getArg(i);
1734 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1735 bool isByVal = Flags.isByVal();
1737 // Promote the value if needed.
1738 switch (VA.getLocInfo()) {
1739 default: assert(0 && "Unknown loc info!");
1740 case CCValAssign::Full: break;
1741 case CCValAssign::SExt:
1742 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1744 case CCValAssign::ZExt:
1745 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1747 case CCValAssign::AExt:
1748 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1752 if (VA.isRegLoc()) {
1754 MVT RegVT = VA.getLocVT();
1755 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1756 switch (VA.getLocReg()) {
1759 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1761 // Special case: passing MMX values in GPR registers.
1762 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1765 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1766 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1767 // Special case: passing MMX values in XMM registers.
1768 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1769 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1770 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1775 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1777 if (!IsTailCall || (IsTailCall && isByVal)) {
1778 assert(VA.isMemLoc());
1779 if (StackPtr.getNode() == 0)
1780 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1782 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1783 Chain, Arg, Flags));
1788 if (!MemOpChains.empty())
1789 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1790 &MemOpChains[0], MemOpChains.size());
1792 // Build a sequence of copy-to-reg nodes chained together with token chain
1793 // and flag operands which copy the outgoing args into registers.
1795 // Tail call byval lowering might overwrite argument registers so in case of
1796 // tail call optimization the copies to registers are lowered later.
1798 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1799 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1800 RegsToPass[i].second, InFlag);
1801 InFlag = Chain.getValue(1);
1804 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1806 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1807 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1808 DAG.getNode(X86ISD::GlobalBaseReg,
1809 DebugLoc::getUnknownLoc(),
1812 InFlag = Chain.getValue(1);
1814 // If we are tail calling and generating PIC/GOT style code load the address
1815 // of the callee into ecx. The value in ecx is used as target of the tail
1816 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1817 // calls on PIC/GOT architectures. Normally we would just put the address of
1818 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1819 // restored (since ebx is callee saved) before jumping to the target@PLT.
1820 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1821 // Note: The actual moving to ecx is done further down.
1822 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1823 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1824 !G->getGlobal()->hasProtectedVisibility())
1825 Callee = LowerGlobalAddress(Callee, DAG);
1826 else if (isa<ExternalSymbolSDNode>(Callee))
1827 Callee = LowerExternalSymbol(Callee,DAG);
1830 if (Is64Bit && isVarArg) {
1831 // From AMD64 ABI document:
1832 // For calls that may call functions that use varargs or stdargs
1833 // (prototype-less calls or calls to functions containing ellipsis (...) in
1834 // the declaration) %al is used as hidden argument to specify the number
1835 // of SSE registers used. The contents of %al do not need to match exactly
1836 // the number of registers, but must be an ubound on the number of SSE
1837 // registers used and is in the range 0 - 8 inclusive.
1839 // FIXME: Verify this on Win64
1840 // Count the number of XMM registers allocated.
1841 static const unsigned XMMArgRegs[] = {
1842 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1843 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1845 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1846 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1847 && "SSE registers cannot be used when SSE is disabled");
1849 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1850 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1851 InFlag = Chain.getValue(1);
1855 // For tail calls lower the arguments to the 'real' stack slot.
1857 SmallVector<SDValue, 8> MemOpChains2;
1860 // Do not flag preceeding copytoreg stuff together with the following stuff.
1862 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1863 CCValAssign &VA = ArgLocs[i];
1864 if (!VA.isRegLoc()) {
1865 assert(VA.isMemLoc());
1866 SDValue Arg = TheCall->getArg(i);
1867 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1868 // Create frame index.
1869 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1870 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1871 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1872 FIN = DAG.getFrameIndex(FI, getPointerTy());
1874 if (Flags.isByVal()) {
1875 // Copy relative to framepointer.
1876 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1877 if (StackPtr.getNode() == 0)
1878 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1880 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1882 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1885 // Store relative to framepointer.
1886 MemOpChains2.push_back(
1887 DAG.getStore(Chain, dl, Arg, FIN,
1888 PseudoSourceValue::getFixedStack(FI), 0));
1893 if (!MemOpChains2.empty())
1894 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1895 &MemOpChains2[0], MemOpChains2.size());
1897 // Copy arguments to their registers.
1898 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1899 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1900 RegsToPass[i].second, InFlag);
1901 InFlag = Chain.getValue(1);
1905 // Store the return address to the appropriate stack slot.
1906 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1910 // If the callee is a GlobalAddress node (quite common, every direct call is)
1911 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1912 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1913 // We should use extra load for direct calls to dllimported functions in
1915 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1916 getTargetMachine(), true))
1917 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(),
1919 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1920 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1921 } else if (IsTailCall) {
1922 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
1924 Chain = DAG.getCopyToReg(Chain, dl,
1925 DAG.getRegister(Opc, getPointerTy()),
1927 Callee = DAG.getRegister(Opc, getPointerTy());
1928 // Add register as live out.
1929 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1932 // Returns a chain & a flag for retval copy to use.
1933 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1934 SmallVector<SDValue, 8> Ops;
1937 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1938 DAG.getIntPtrConstant(0, true), InFlag);
1939 InFlag = Chain.getValue(1);
1941 // Returns a chain & a flag for retval copy to use.
1942 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1946 Ops.push_back(Chain);
1947 Ops.push_back(Callee);
1950 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1952 // Add argument registers to the end of the list so that they are known live
1954 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1955 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1956 RegsToPass[i].second.getValueType()));
1958 // Add an implicit use GOT pointer in EBX.
1959 if (!IsTailCall && !Is64Bit &&
1960 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1961 Subtarget->isPICStyleGOT())
1962 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1964 // Add an implicit use of AL for x86 vararg functions.
1965 if (Is64Bit && isVarArg)
1966 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1968 if (InFlag.getNode())
1969 Ops.push_back(InFlag);
1972 assert(InFlag.getNode() &&
1973 "Flag must be set. Depend on flag being set in LowerRET");
1974 Chain = DAG.getNode(X86ISD::TAILCALL, dl,
1975 TheCall->getVTList(), &Ops[0], Ops.size());
1977 return SDValue(Chain.getNode(), Op.getResNo());
1980 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
1981 InFlag = Chain.getValue(1);
1983 // Create the CALLSEQ_END node.
1984 unsigned NumBytesForCalleeToPush;
1985 if (IsCalleePop(isVarArg, CC))
1986 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1987 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
1988 // If this is is a call to a struct-return function, the callee
1989 // pops the hidden struct pointer, so we have to push it back.
1990 // This is common for Darwin/X86, Linux & Mingw32 targets.
1991 NumBytesForCalleeToPush = 4;
1993 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1995 // Returns a flag for retval copy to use.
1996 Chain = DAG.getCALLSEQ_END(Chain,
1997 DAG.getIntPtrConstant(NumBytes, true),
1998 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2001 InFlag = Chain.getValue(1);
2003 // Handle result values, copying them out of physregs into vregs that we
2005 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
2010 //===----------------------------------------------------------------------===//
2011 // Fast Calling Convention (tail call) implementation
2012 //===----------------------------------------------------------------------===//
2014 // Like std call, callee cleans arguments, convention except that ECX is
2015 // reserved for storing the tail called function address. Only 2 registers are
2016 // free for argument passing (inreg). Tail call optimization is performed
2018 // * tailcallopt is enabled
2019 // * caller/callee are fastcc
2020 // On X86_64 architecture with GOT-style position independent code only local
2021 // (within module) calls are supported at the moment.
2022 // To keep the stack aligned according to platform abi the function
2023 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2024 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2025 // If a tail called function callee has more arguments than the caller the
2026 // caller needs to make sure that there is room to move the RETADDR to. This is
2027 // achieved by reserving an area the size of the argument delta right after the
2028 // original REtADDR, but before the saved framepointer or the spilled registers
2029 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2041 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2042 /// for a 16 byte align requirement.
2043 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2044 SelectionDAG& DAG) {
2045 MachineFunction &MF = DAG.getMachineFunction();
2046 const TargetMachine &TM = MF.getTarget();
2047 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2048 unsigned StackAlignment = TFI.getStackAlignment();
2049 uint64_t AlignMask = StackAlignment - 1;
2050 int64_t Offset = StackSize;
2051 uint64_t SlotSize = TD->getPointerSize();
2052 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2053 // Number smaller than 12 so just add the difference.
2054 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2056 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2057 Offset = ((~AlignMask) & Offset) + StackAlignment +
2058 (StackAlignment-SlotSize);
2063 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
2064 /// following the call is a return. A function is eligible if caller/callee
2065 /// calling conventions match, currently only fastcc supports tail calls, and
2066 /// the function CALL is immediatly followed by a RET.
2067 bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
2069 SelectionDAG& DAG) const {
2070 if (!PerformTailCallOpt)
2073 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
2074 MachineFunction &MF = DAG.getMachineFunction();
2075 unsigned CallerCC = MF.getFunction()->getCallingConv();
2076 unsigned CalleeCC= TheCall->getCallingConv();
2077 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2078 SDValue Callee = TheCall->getCallee();
2079 // On x86/32Bit PIC/GOT tail calls are supported.
2080 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
2081 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
2084 // Can only do local tail calls (in same module, hidden or protected) on
2085 // x86_64 PIC/GOT at the moment.
2086 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2087 return G->getGlobal()->hasHiddenVisibility()
2088 || G->getGlobal()->hasProtectedVisibility();
2096 X86TargetLowering::createFastISel(MachineFunction &mf,
2097 MachineModuleInfo *mmo,
2099 DenseMap<const Value *, unsigned> &vm,
2100 DenseMap<const BasicBlock *,
2101 MachineBasicBlock *> &bm,
2102 DenseMap<const AllocaInst *, int> &am
2104 , SmallSet<Instruction*, 8> &cil
2107 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2115 //===----------------------------------------------------------------------===//
2116 // Other Lowering Hooks
2117 //===----------------------------------------------------------------------===//
2120 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2121 MachineFunction &MF = DAG.getMachineFunction();
2122 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2123 int ReturnAddrIndex = FuncInfo->getRAIndex();
2125 if (ReturnAddrIndex == 0) {
2126 // Set up a frame object for the return address.
2127 uint64_t SlotSize = TD->getPointerSize();
2128 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
2129 FuncInfo->setRAIndex(ReturnAddrIndex);
2132 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2136 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2137 /// specific condition code, returning the condition code and the LHS/RHS of the
2138 /// comparison to make.
2139 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2140 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2142 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2143 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2144 // X > -1 -> X == 0, jump !sign.
2145 RHS = DAG.getConstant(0, RHS.getValueType());
2146 return X86::COND_NS;
2147 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2148 // X < 0 -> X == 0, jump on sign.
2150 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2152 RHS = DAG.getConstant(0, RHS.getValueType());
2153 return X86::COND_LE;
2157 switch (SetCCOpcode) {
2158 default: assert(0 && "Invalid integer condition!");
2159 case ISD::SETEQ: return X86::COND_E;
2160 case ISD::SETGT: return X86::COND_G;
2161 case ISD::SETGE: return X86::COND_GE;
2162 case ISD::SETLT: return X86::COND_L;
2163 case ISD::SETLE: return X86::COND_LE;
2164 case ISD::SETNE: return X86::COND_NE;
2165 case ISD::SETULT: return X86::COND_B;
2166 case ISD::SETUGT: return X86::COND_A;
2167 case ISD::SETULE: return X86::COND_BE;
2168 case ISD::SETUGE: return X86::COND_AE;
2172 // First determine if it is required or is profitable to flip the operands.
2174 // If LHS is a foldable load, but RHS is not, flip the condition.
2175 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2176 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2177 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2178 std::swap(LHS, RHS);
2181 switch (SetCCOpcode) {
2187 std::swap(LHS, RHS);
2191 // On a floating point condition, the flags are set as follows:
2193 // 0 | 0 | 0 | X > Y
2194 // 0 | 0 | 1 | X < Y
2195 // 1 | 0 | 0 | X == Y
2196 // 1 | 1 | 1 | unordered
2197 switch (SetCCOpcode) {
2198 default: assert(0 && "Condcode should be pre-legalized away");
2200 case ISD::SETEQ: return X86::COND_E;
2201 case ISD::SETOLT: // flipped
2203 case ISD::SETGT: return X86::COND_A;
2204 case ISD::SETOLE: // flipped
2206 case ISD::SETGE: return X86::COND_AE;
2207 case ISD::SETUGT: // flipped
2209 case ISD::SETLT: return X86::COND_B;
2210 case ISD::SETUGE: // flipped
2212 case ISD::SETLE: return X86::COND_BE;
2214 case ISD::SETNE: return X86::COND_NE;
2215 case ISD::SETUO: return X86::COND_P;
2216 case ISD::SETO: return X86::COND_NP;
2220 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2221 /// code. Current x86 isa includes the following FP cmov instructions:
2222 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2223 static bool hasFPCMov(unsigned X86CC) {
2239 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2240 /// the specified range (L, H].
2241 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2242 return (Val < 0) || (Val >= Low && Val < Hi);
2245 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2246 /// specified value.
2247 static bool isUndefOrEqual(int Val, int CmpVal) {
2248 if (Val < 0 || Val == CmpVal)
2253 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2254 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2255 /// the second operand.
2256 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2257 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2258 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2259 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2260 return (Mask[0] < 2 && Mask[1] < 2);
2264 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2265 SmallVector<int, 8> M;
2267 return ::isPSHUFDMask(M, N->getValueType(0));
2270 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2271 /// is suitable for input to PSHUFHW.
2272 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2273 if (VT != MVT::v8i16)
2276 // Lower quadword copied in order or undef.
2277 for (int i = 0; i != 4; ++i)
2278 if (Mask[i] >= 0 && Mask[i] != i)
2281 // Upper quadword shuffled.
2282 for (int i = 4; i != 8; ++i)
2283 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2289 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2290 SmallVector<int, 8> M;
2292 return ::isPSHUFHWMask(M, N->getValueType(0));
2295 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2296 /// is suitable for input to PSHUFLW.
2297 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2298 if (VT != MVT::v8i16)
2301 // Upper quadword copied in order.
2302 for (int i = 4; i != 8; ++i)
2303 if (Mask[i] >= 0 && Mask[i] != i)
2306 // Lower quadword shuffled.
2307 for (int i = 0; i != 4; ++i)
2314 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2315 SmallVector<int, 8> M;
2317 return ::isPSHUFLWMask(M, N->getValueType(0));
2320 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2321 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2322 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2323 int NumElems = VT.getVectorNumElements();
2324 if (NumElems != 2 && NumElems != 4)
2327 int Half = NumElems / 2;
2328 for (int i = 0; i < Half; ++i)
2329 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2331 for (int i = Half; i < NumElems; ++i)
2332 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2338 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2339 SmallVector<int, 8> M;
2341 return ::isSHUFPMask(M, N->getValueType(0));
2344 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2345 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2346 /// half elements to come from vector 1 (which would equal the dest.) and
2347 /// the upper half to come from vector 2.
2348 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2349 int NumElems = VT.getVectorNumElements();
2351 if (NumElems != 2 && NumElems != 4)
2354 int Half = NumElems / 2;
2355 for (int i = 0; i < Half; ++i)
2356 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2358 for (int i = Half; i < NumElems; ++i)
2359 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2364 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2365 SmallVector<int, 8> M;
2367 return isCommutedSHUFPMask(M, N->getValueType(0));
2370 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2371 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2372 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2373 if (N->getValueType(0).getVectorNumElements() != 4)
2376 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2377 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2378 isUndefOrEqual(N->getMaskElt(1), 7) &&
2379 isUndefOrEqual(N->getMaskElt(2), 2) &&
2380 isUndefOrEqual(N->getMaskElt(3), 3);
2383 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2384 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2385 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2386 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2388 if (NumElems != 2 && NumElems != 4)
2391 for (unsigned i = 0; i < NumElems/2; ++i)
2392 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2395 for (unsigned i = NumElems/2; i < NumElems; ++i)
2396 if (!isUndefOrEqual(N->getMaskElt(i), i))
2402 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2403 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2405 bool X86::isMOVHPMask(ShuffleVectorSDNode *N) {
2406 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2408 if (NumElems != 2 && NumElems != 4)
2411 for (unsigned i = 0; i < NumElems/2; ++i)
2412 if (!isUndefOrEqual(N->getMaskElt(i), i))
2415 for (unsigned i = 0; i < NumElems/2; ++i)
2416 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2422 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2423 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2425 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2426 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2431 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2432 isUndefOrEqual(N->getMaskElt(1), 3) &&
2433 isUndefOrEqual(N->getMaskElt(2), 2) &&
2434 isUndefOrEqual(N->getMaskElt(3), 3);
2437 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2438 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2439 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, MVT VT,
2440 bool V2IsSplat = false) {
2441 int NumElts = VT.getVectorNumElements();
2442 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2445 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2447 int BitI1 = Mask[i+1];
2448 if (!isUndefOrEqual(BitI, j))
2451 if (!isUndefOrEqual(BitI1, NumElts))
2454 if (!isUndefOrEqual(BitI1, j + NumElts))
2461 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2462 SmallVector<int, 8> M;
2464 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2467 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2468 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2469 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, MVT VT,
2470 bool V2IsSplat = false) {
2471 int NumElts = VT.getVectorNumElements();
2472 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2475 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2477 int BitI1 = Mask[i+1];
2478 if (!isUndefOrEqual(BitI, j + NumElts/2))
2481 if (isUndefOrEqual(BitI1, NumElts))
2484 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2491 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2492 SmallVector<int, 8> M;
2494 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2497 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2498 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2500 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
2501 int NumElems = VT.getVectorNumElements();
2502 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2505 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2507 int BitI1 = Mask[i+1];
2508 if (!isUndefOrEqual(BitI, j))
2510 if (!isUndefOrEqual(BitI1, j))
2516 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2517 SmallVector<int, 8> M;
2519 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2522 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2523 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2525 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
2526 int NumElems = VT.getVectorNumElements();
2527 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2530 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2532 int BitI1 = Mask[i+1];
2533 if (!isUndefOrEqual(BitI, j))
2535 if (!isUndefOrEqual(BitI1, j))
2541 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2542 SmallVector<int, 8> M;
2544 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2547 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2548 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2549 /// MOVSD, and MOVD, i.e. setting the lowest element.
2550 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2551 if (VT.getVectorElementType().getSizeInBits() < 32)
2554 int NumElts = VT.getVectorNumElements();
2556 if (!isUndefOrEqual(Mask[0], NumElts))
2559 for (int i = 1; i < NumElts; ++i)
2560 if (!isUndefOrEqual(Mask[i], i))
2566 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2567 SmallVector<int, 8> M;
2569 return ::isMOVLMask(M, N->getValueType(0));
2572 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2573 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2574 /// element of vector 2 and the other elements to come from vector 1 in order.
2575 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT,
2576 bool V2IsSplat = false, bool V2IsUndef = false) {
2577 int NumOps = VT.getVectorNumElements();
2578 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2581 if (!isUndefOrEqual(Mask[0], 0))
2584 for (int i = 1; i < NumOps; ++i)
2585 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2586 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2587 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2593 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2594 bool V2IsUndef = false) {
2595 SmallVector<int, 8> M;
2597 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2600 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2601 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2602 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2603 if (N->getValueType(0).getVectorNumElements() != 4)
2606 // Expect 1, 1, 3, 3
2607 for (unsigned i = 0; i < 2; ++i) {
2608 int Elt = N->getMaskElt(i);
2609 if (Elt >= 0 && Elt != 1)
2614 for (unsigned i = 2; i < 4; ++i) {
2615 int Elt = N->getMaskElt(i);
2616 if (Elt >= 0 && Elt != 3)
2621 // Don't use movshdup if it can be done with a shufps.
2622 // FIXME: verify that matching u, u, 3, 3 is what we want.
2626 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2627 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2628 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2629 if (N->getValueType(0).getVectorNumElements() != 4)
2632 // Expect 0, 0, 2, 2
2633 for (unsigned i = 0; i < 2; ++i)
2634 if (N->getMaskElt(i) > 0)
2638 for (unsigned i = 2; i < 4; ++i) {
2639 int Elt = N->getMaskElt(i);
2640 if (Elt >= 0 && Elt != 2)
2645 // Don't use movsldup if it can be done with a shufps.
2649 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2650 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2651 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2652 int e = N->getValueType(0).getVectorNumElements() / 2;
2654 for (int i = 0; i < e; ++i)
2655 if (!isUndefOrEqual(N->getMaskElt(i), i))
2657 for (int i = 0; i < e; ++i)
2658 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2663 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2664 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2666 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2667 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2668 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2670 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2672 for (int i = 0; i < NumOperands; ++i) {
2673 int Val = SVOp->getMaskElt(NumOperands-i-1);
2674 if (Val < 0) Val = 0;
2675 if (Val >= NumOperands) Val -= NumOperands;
2677 if (i != NumOperands - 1)
2683 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2684 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2686 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2687 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2689 // 8 nodes, but we only care about the last 4.
2690 for (unsigned i = 7; i >= 4; --i) {
2691 int Val = SVOp->getMaskElt(i);
2700 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2701 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2703 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2704 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2706 // 8 nodes, but we only care about the first 4.
2707 for (int i = 3; i >= 0; --i) {
2708 int Val = SVOp->getMaskElt(i);
2717 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2718 /// their permute mask.
2719 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2720 SelectionDAG &DAG) {
2721 MVT VT = SVOp->getValueType(0);
2722 unsigned NumElems = VT.getVectorNumElements();
2723 SmallVector<int, 8> MaskVec;
2725 for (unsigned i = 0; i != NumElems; ++i) {
2726 int idx = SVOp->getMaskElt(i);
2728 MaskVec.push_back(idx);
2729 else if (idx < (int)NumElems)
2730 MaskVec.push_back(idx + NumElems);
2732 MaskVec.push_back(idx - NumElems);
2734 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2735 SVOp->getOperand(0), &MaskVec[0]);
2738 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2739 /// the two vector operands have swapped position.
2740 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, MVT VT) {
2741 unsigned NumElems = VT.getVectorNumElements();
2742 for (unsigned i = 0; i != NumElems; ++i) {
2746 else if (idx < (int)NumElems)
2747 Mask[i] = idx + NumElems;
2749 Mask[i] = idx - NumElems;
2753 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2754 /// match movhlps. The lower half elements should come from upper half of
2755 /// V1 (and in order), and the upper half elements should come from the upper
2756 /// half of V2 (and in order).
2757 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2758 if (Op->getValueType(0).getVectorNumElements() != 4)
2760 for (unsigned i = 0, e = 2; i != e; ++i)
2761 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2763 for (unsigned i = 2; i != 4; ++i)
2764 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2769 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2770 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2772 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2773 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2775 N = N->getOperand(0).getNode();
2776 if (!ISD::isNON_EXTLoad(N))
2779 *LD = cast<LoadSDNode>(N);
2783 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2784 /// match movlp{s|d}. The lower half elements should come from lower half of
2785 /// V1 (and in order), and the upper half elements should come from the upper
2786 /// half of V2 (and in order). And since V1 will become the source of the
2787 /// MOVLP, it must be either a vector load or a scalar load to vector.
2788 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2789 ShuffleVectorSDNode *Op) {
2790 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2792 // Is V2 is a vector load, don't do this transformation. We will try to use
2793 // load folding shufps op.
2794 if (ISD::isNON_EXTLoad(V2))
2797 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
2799 if (NumElems != 2 && NumElems != 4)
2801 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2802 if (!isUndefOrEqual(Op->getMaskElt(i), i))
2804 for (unsigned i = NumElems/2; i != NumElems; ++i)
2805 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
2810 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2812 static bool isSplatVector(SDNode *N) {
2813 if (N->getOpcode() != ISD::BUILD_VECTOR)
2816 SDValue SplatValue = N->getOperand(0);
2817 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2818 if (N->getOperand(i) != SplatValue)
2823 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2825 static inline bool isZeroNode(SDValue Elt) {
2826 return ((isa<ConstantSDNode>(Elt) &&
2827 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2828 (isa<ConstantFPSDNode>(Elt) &&
2829 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2832 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2833 /// to an zero vector.
2834 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
2835 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
2836 SDValue V1 = N->getOperand(0);
2837 SDValue V2 = N->getOperand(1);
2838 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2839 for (unsigned i = 0; i != NumElems; ++i) {
2840 int Idx = N->getMaskElt(i);
2841 if (Idx >= (int)NumElems) {
2842 unsigned Opc = V2.getOpcode();
2843 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2845 if (Opc != ISD::BUILD_VECTOR || !isZeroNode(V2.getOperand(Idx-NumElems)))
2847 } else if (Idx >= 0) {
2848 unsigned Opc = V1.getOpcode();
2849 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2851 if (Opc != ISD::BUILD_VECTOR || !isZeroNode(V1.getOperand(Idx)))
2858 /// getZeroVector - Returns a vector of specified type with all zero elements.
2860 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG,
2862 assert(VT.isVector() && "Expected a vector type");
2864 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2865 // type. This ensures they get CSE'd.
2867 if (VT.getSizeInBits() == 64) { // MMX
2868 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2869 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2870 } else if (HasSSE2) { // SSE2
2871 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2872 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2874 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2875 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
2877 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2880 /// getOnesVector - Returns a vector of specified type with all bits set.
2882 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
2883 assert(VT.isVector() && "Expected a vector type");
2885 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2886 // type. This ensures they get CSE'd.
2887 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2889 if (VT.getSizeInBits() == 64) // MMX
2890 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2892 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2893 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2897 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2898 /// that point to V2 points to its first element.
2899 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
2900 MVT VT = SVOp->getValueType(0);
2901 unsigned NumElems = VT.getVectorNumElements();
2903 bool Changed = false;
2904 SmallVector<int, 8> MaskVec;
2905 SVOp->getMask(MaskVec);
2907 for (unsigned i = 0; i != NumElems; ++i) {
2908 if (MaskVec[i] > (int)NumElems) {
2909 MaskVec[i] = NumElems;
2914 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
2915 SVOp->getOperand(1), &MaskVec[0]);
2916 return SDValue(SVOp, 0);
2919 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2920 /// operation of specified width.
2921 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2923 unsigned NumElems = VT.getVectorNumElements();
2924 SmallVector<int, 8> Mask;
2925 Mask.push_back(NumElems);
2926 for (unsigned i = 1; i != NumElems; ++i)
2928 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2931 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
2932 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2934 unsigned NumElems = VT.getVectorNumElements();
2935 SmallVector<int, 8> Mask;
2936 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2938 Mask.push_back(i + NumElems);
2940 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2943 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
2944 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2946 unsigned NumElems = VT.getVectorNumElements();
2947 unsigned Half = NumElems/2;
2948 SmallVector<int, 8> Mask;
2949 for (unsigned i = 0; i != Half; ++i) {
2950 Mask.push_back(i + Half);
2951 Mask.push_back(i + NumElems + Half);
2953 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2956 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2957 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
2959 if (SV->getValueType(0).getVectorNumElements() <= 4)
2960 return SDValue(SV, 0);
2962 MVT PVT = MVT::v4f32;
2963 MVT VT = SV->getValueType(0);
2964 DebugLoc dl = SV->getDebugLoc();
2965 SDValue V1 = SV->getOperand(0);
2966 int NumElems = VT.getVectorNumElements();
2967 int EltNo = SV->getSplatIndex();
2969 // unpack elements to the correct location
2970 while (NumElems > 4) {
2971 if (EltNo < NumElems/2) {
2972 V1 = getUnpackl(DAG, dl, VT, V1, V1);
2974 V1 = getUnpackh(DAG, dl, VT, V1, V1);
2975 EltNo -= NumElems/2;
2980 // Perform the splat.
2981 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
2982 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
2983 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
2984 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
2987 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2988 /// vector of zero or undef vector. This produces a shuffle where the low
2989 /// element of V2 is swizzled into the zero/undef vector, landing at element
2990 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
2991 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
2992 bool isZero, bool HasSSE2,
2993 SelectionDAG &DAG) {
2994 MVT VT = V2.getValueType();
2996 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
2997 unsigned NumElems = VT.getVectorNumElements();
2998 SmallVector<int, 16> MaskVec;
2999 for (unsigned i = 0; i != NumElems; ++i)
3000 // If this is the insertion idx, put the low elt of V2 here.
3001 MaskVec.push_back(i == Idx ? NumElems : i);
3002 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3005 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3006 /// a shuffle that is zero.
3008 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3009 bool Low, SelectionDAG &DAG) {
3010 unsigned NumZeros = 0;
3011 for (int i = 0; i < NumElems; ++i) {
3012 unsigned Index = Low ? i : NumElems-i-1;
3013 int Idx = SVOp->getMaskElt(Index);
3018 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3019 if (Elt.getNode() && isZeroNode(Elt))
3027 /// isVectorShift - Returns true if the shuffle can be implemented as a
3028 /// logical left or right shift of a vector.
3029 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3030 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3031 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3032 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3035 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3038 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3042 bool SeenV1 = false;
3043 bool SeenV2 = false;
3044 for (int i = NumZeros; i < NumElems; ++i) {
3045 int Val = isLeft ? (i - NumZeros) : i;
3046 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3058 if (SeenV1 && SeenV2)
3061 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3067 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3069 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3070 unsigned NumNonZero, unsigned NumZero,
3071 SelectionDAG &DAG, TargetLowering &TLI) {
3075 DebugLoc dl = Op.getDebugLoc();
3078 for (unsigned i = 0; i < 16; ++i) {
3079 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3080 if (ThisIsNonZero && First) {
3082 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3084 V = DAG.getUNDEF(MVT::v8i16);
3089 SDValue ThisElt(0, 0), LastElt(0, 0);
3090 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3091 if (LastIsNonZero) {
3092 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3093 MVT::i16, Op.getOperand(i-1));
3095 if (ThisIsNonZero) {
3096 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3097 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3098 ThisElt, DAG.getConstant(8, MVT::i8));
3100 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3104 if (ThisElt.getNode())
3105 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3106 DAG.getIntPtrConstant(i/2));
3110 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3113 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3115 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3116 unsigned NumNonZero, unsigned NumZero,
3117 SelectionDAG &DAG, TargetLowering &TLI) {
3121 DebugLoc dl = Op.getDebugLoc();
3124 for (unsigned i = 0; i < 8; ++i) {
3125 bool isNonZero = (NonZeros & (1 << i)) != 0;
3129 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3131 V = DAG.getUNDEF(MVT::v8i16);
3134 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3135 MVT::v8i16, V, Op.getOperand(i),
3136 DAG.getIntPtrConstant(i));
3143 /// getVShift - Return a vector logical shift node.
3145 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3146 unsigned NumBits, SelectionDAG &DAG,
3147 const TargetLowering &TLI, DebugLoc dl) {
3148 bool isMMX = VT.getSizeInBits() == 64;
3149 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3150 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3151 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3152 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3153 DAG.getNode(Opc, dl, ShVT, SrcOp,
3154 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3158 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3159 DebugLoc dl = Op.getDebugLoc();
3160 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3161 if (ISD::isBuildVectorAllZeros(Op.getNode())
3162 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3163 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3164 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3165 // eliminated on x86-32 hosts.
3166 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3169 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3170 return getOnesVector(Op.getValueType(), DAG, dl);
3171 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3174 MVT VT = Op.getValueType();
3175 MVT EVT = VT.getVectorElementType();
3176 unsigned EVTBits = EVT.getSizeInBits();
3178 unsigned NumElems = Op.getNumOperands();
3179 unsigned NumZero = 0;
3180 unsigned NumNonZero = 0;
3181 unsigned NonZeros = 0;
3182 bool IsAllConstants = true;
3183 SmallSet<SDValue, 8> Values;
3184 for (unsigned i = 0; i < NumElems; ++i) {
3185 SDValue Elt = Op.getOperand(i);
3186 if (Elt.getOpcode() == ISD::UNDEF)
3189 if (Elt.getOpcode() != ISD::Constant &&
3190 Elt.getOpcode() != ISD::ConstantFP)
3191 IsAllConstants = false;
3192 if (isZeroNode(Elt))
3195 NonZeros |= (1 << i);
3200 if (NumNonZero == 0) {
3201 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3202 return DAG.getUNDEF(VT);
3205 // Special case for single non-zero, non-undef, element.
3206 if (NumNonZero == 1) {
3207 unsigned Idx = CountTrailingZeros_32(NonZeros);
3208 SDValue Item = Op.getOperand(Idx);
3210 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3211 // the value are obviously zero, truncate the value to i32 and do the
3212 // insertion that way. Only do this if the value is non-constant or if the
3213 // value is a constant being inserted into element 0. It is cheaper to do
3214 // a constant pool load than it is to do a movd + shuffle.
3215 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3216 (!IsAllConstants || Idx == 0)) {
3217 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3218 // Handle MMX and SSE both.
3219 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3220 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3222 // Truncate the value (which may itself be a constant) to i32, and
3223 // convert it to a vector with movd (S2V+shuffle to zero extend).
3224 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3225 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3226 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3227 Subtarget->hasSSE2(), DAG);
3229 // Now we have our 32-bit value zero extended in the low element of
3230 // a vector. If Idx != 0, swizzle it into place.
3232 SmallVector<int, 4> Mask;
3233 Mask.push_back(Idx);
3234 for (unsigned i = 1; i != VecElts; ++i)
3236 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3237 DAG.getUNDEF(Item.getValueType()),
3240 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3244 // If we have a constant or non-constant insertion into the low element of
3245 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3246 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3247 // depending on what the source datatype is.
3250 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3251 } else if (EVT == MVT::i32 || EVT == MVT::f32 || EVT == MVT::f64 ||
3252 (EVT == MVT::i64 && Subtarget->is64Bit())) {
3253 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3254 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3255 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3257 } else if (EVT == MVT::i16 || EVT == MVT::i8) {
3258 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3259 MVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3260 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3261 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3262 Subtarget->hasSSE2(), DAG);
3263 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3267 // Is it a vector logical left shift?
3268 if (NumElems == 2 && Idx == 1 &&
3269 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3270 unsigned NumBits = VT.getSizeInBits();
3271 return getVShift(true, VT,
3272 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3273 VT, Op.getOperand(1)),
3274 NumBits/2, DAG, *this, dl);
3277 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3280 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3281 // is a non-constant being inserted into an element other than the low one,
3282 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3283 // movd/movss) to move this into the low element, then shuffle it into
3285 if (EVTBits == 32) {
3286 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3288 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3289 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3290 Subtarget->hasSSE2(), DAG);
3291 SmallVector<int, 8> MaskVec;
3292 for (unsigned i = 0; i < NumElems; i++)
3293 MaskVec.push_back(i == Idx ? 0 : 1);
3294 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3298 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3299 if (Values.size() == 1)
3302 // A vector full of immediates; various special cases are already
3303 // handled, so this is best done with a single constant-pool load.
3307 // Let legalizer expand 2-wide build_vectors.
3308 if (EVTBits == 64) {
3309 if (NumNonZero == 1) {
3310 // One half is zero or undef.
3311 unsigned Idx = CountTrailingZeros_32(NonZeros);
3312 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3313 Op.getOperand(Idx));
3314 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3315 Subtarget->hasSSE2(), DAG);
3320 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3321 if (EVTBits == 8 && NumElems == 16) {
3322 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3324 if (V.getNode()) return V;
3327 if (EVTBits == 16 && NumElems == 8) {
3328 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3330 if (V.getNode()) return V;
3333 // If element VT is == 32 bits, turn it into a number of shuffles.
3334 SmallVector<SDValue, 8> V;
3336 if (NumElems == 4 && NumZero > 0) {
3337 for (unsigned i = 0; i < 4; ++i) {
3338 bool isZero = !(NonZeros & (1 << i));
3340 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3342 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3345 for (unsigned i = 0; i < 2; ++i) {
3346 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3349 V[i] = V[i*2]; // Must be a zero vector.
3352 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3355 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3358 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3363 SmallVector<int, 8> MaskVec;
3364 bool Reverse = (NonZeros & 0x3) == 2;
3365 for (unsigned i = 0; i < 2; ++i)
3366 MaskVec.push_back(Reverse ? 1-i : i);
3367 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3368 for (unsigned i = 0; i < 2; ++i)
3369 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3370 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3373 if (Values.size() > 2) {
3374 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3375 // values to be inserted is equal to the number of elements, in which case
3376 // use the unpack code below in the hopes of matching the consecutive elts
3377 // load merge pattern for shuffles.
3378 // FIXME: We could probably just check that here directly.
3379 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3380 getSubtarget()->hasSSE41()) {
3381 V[0] = DAG.getUNDEF(VT);
3382 for (unsigned i = 0; i < NumElems; ++i)
3383 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3384 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3385 Op.getOperand(i), DAG.getIntPtrConstant(i));
3388 // Expand into a number of unpckl*.
3390 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3391 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3392 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3393 for (unsigned i = 0; i < NumElems; ++i)
3394 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3396 while (NumElems != 0) {
3397 for (unsigned i = 0; i < NumElems; ++i)
3398 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3407 // v8i16 shuffles - Prefer shuffles in the following order:
3408 // 1. [all] pshuflw, pshufhw, optional move
3409 // 2. [ssse3] 1 x pshufb
3410 // 3. [ssse3] 2 x pshufb + 1 x por
3411 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3413 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3414 SelectionDAG &DAG, X86TargetLowering &TLI) {
3415 SDValue V1 = SVOp->getOperand(0);
3416 SDValue V2 = SVOp->getOperand(1);
3417 DebugLoc dl = SVOp->getDebugLoc();
3418 SmallVector<int, 8> MaskVals;
3420 // Determine if more than 1 of the words in each of the low and high quadwords
3421 // of the result come from the same quadword of one of the two inputs. Undef
3422 // mask values count as coming from any quadword, for better codegen.
3423 SmallVector<unsigned, 4> LoQuad(4);
3424 SmallVector<unsigned, 4> HiQuad(4);
3425 BitVector InputQuads(4);
3426 for (unsigned i = 0; i < 8; ++i) {
3427 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3428 int EltIdx = SVOp->getMaskElt(i);
3429 MaskVals.push_back(EltIdx);
3438 InputQuads.set(EltIdx / 4);
3441 int BestLoQuad = -1;
3442 unsigned MaxQuad = 1;
3443 for (unsigned i = 0; i < 4; ++i) {
3444 if (LoQuad[i] > MaxQuad) {
3446 MaxQuad = LoQuad[i];
3450 int BestHiQuad = -1;
3452 for (unsigned i = 0; i < 4; ++i) {
3453 if (HiQuad[i] > MaxQuad) {
3455 MaxQuad = HiQuad[i];
3459 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3460 // of the two input vectors, shuffle them into one input vector so only a
3461 // single pshufb instruction is necessary. If There are more than 2 input
3462 // quads, disable the next transformation since it does not help SSSE3.
3463 bool V1Used = InputQuads[0] || InputQuads[1];
3464 bool V2Used = InputQuads[2] || InputQuads[3];
3465 if (TLI.getSubtarget()->hasSSSE3()) {
3466 if (InputQuads.count() == 2 && V1Used && V2Used) {
3467 BestLoQuad = InputQuads.find_first();
3468 BestHiQuad = InputQuads.find_next(BestLoQuad);
3470 if (InputQuads.count() > 2) {
3476 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3477 // the shuffle mask. If a quad is scored as -1, that means that it contains
3478 // words from all 4 input quadwords.
3480 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3481 SmallVector<int, 8> MaskV;
3482 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3483 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3484 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3485 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3486 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3487 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3489 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3490 // source words for the shuffle, to aid later transformations.
3491 bool AllWordsInNewV = true;
3492 bool InOrder[2] = { true, true };
3493 for (unsigned i = 0; i != 8; ++i) {
3494 int idx = MaskVals[i];
3496 InOrder[i/4] = false;
3497 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3499 AllWordsInNewV = false;
3503 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3504 if (AllWordsInNewV) {
3505 for (int i = 0; i != 8; ++i) {
3506 int idx = MaskVals[i];
3509 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3510 if ((idx != i) && idx < 4)
3512 if ((idx != i) && idx > 3)
3521 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3522 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3523 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3524 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3525 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3529 // If we have SSSE3, and all words of the result are from 1 input vector,
3530 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3531 // is present, fall back to case 4.
3532 if (TLI.getSubtarget()->hasSSSE3()) {
3533 SmallVector<SDValue,16> pshufbMask;
3535 // If we have elements from both input vectors, set the high bit of the
3536 // shuffle mask element to zero out elements that come from V2 in the V1
3537 // mask, and elements that come from V1 in the V2 mask, so that the two
3538 // results can be OR'd together.
3539 bool TwoInputs = V1Used && V2Used;
3540 for (unsigned i = 0; i != 8; ++i) {
3541 int EltIdx = MaskVals[i] * 2;
3542 if (TwoInputs && (EltIdx >= 16)) {
3543 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3544 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3547 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3548 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3550 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3551 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3552 DAG.getNode(ISD::BUILD_VECTOR, dl,
3553 MVT::v16i8, &pshufbMask[0], 16));
3555 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3557 // Calculate the shuffle mask for the second input, shuffle it, and
3558 // OR it with the first shuffled input.
3560 for (unsigned i = 0; i != 8; ++i) {
3561 int EltIdx = MaskVals[i] * 2;
3563 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3564 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3567 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3568 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3570 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3571 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3572 DAG.getNode(ISD::BUILD_VECTOR, dl,
3573 MVT::v16i8, &pshufbMask[0], 16));
3574 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3575 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3578 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3579 // and update MaskVals with new element order.
3580 BitVector InOrder(8);
3581 if (BestLoQuad >= 0) {
3582 SmallVector<int, 8> MaskV;
3583 for (int i = 0; i != 4; ++i) {
3584 int idx = MaskVals[i];
3586 MaskV.push_back(-1);
3588 } else if ((idx / 4) == BestLoQuad) {
3589 MaskV.push_back(idx & 3);
3592 MaskV.push_back(-1);
3595 for (unsigned i = 4; i != 8; ++i)
3597 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3601 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3602 // and update MaskVals with the new element order.
3603 if (BestHiQuad >= 0) {
3604 SmallVector<int, 8> MaskV;
3605 for (unsigned i = 0; i != 4; ++i)
3607 for (unsigned i = 4; i != 8; ++i) {
3608 int idx = MaskVals[i];
3610 MaskV.push_back(-1);
3612 } else if ((idx / 4) == BestHiQuad) {
3613 MaskV.push_back((idx & 3) + 4);
3616 MaskV.push_back(-1);
3619 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3623 // In case BestHi & BestLo were both -1, which means each quadword has a word
3624 // from each of the four input quadwords, calculate the InOrder bitvector now
3625 // before falling through to the insert/extract cleanup.
3626 if (BestLoQuad == -1 && BestHiQuad == -1) {
3628 for (int i = 0; i != 8; ++i)
3629 if (MaskVals[i] < 0 || MaskVals[i] == i)
3633 // The other elements are put in the right place using pextrw and pinsrw.
3634 for (unsigned i = 0; i != 8; ++i) {
3637 int EltIdx = MaskVals[i];
3640 SDValue ExtOp = (EltIdx < 8)
3641 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3642 DAG.getIntPtrConstant(EltIdx))
3643 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3644 DAG.getIntPtrConstant(EltIdx - 8));
3645 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3646 DAG.getIntPtrConstant(i));
3651 // v16i8 shuffles - Prefer shuffles in the following order:
3652 // 1. [ssse3] 1 x pshufb
3653 // 2. [ssse3] 2 x pshufb + 1 x por
3654 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3656 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3657 SelectionDAG &DAG, X86TargetLowering &TLI) {
3658 SDValue V1 = SVOp->getOperand(0);
3659 SDValue V2 = SVOp->getOperand(1);
3660 DebugLoc dl = SVOp->getDebugLoc();
3661 SmallVector<int, 16> MaskVals;
3662 SVOp->getMask(MaskVals);
3664 // If we have SSSE3, case 1 is generated when all result bytes come from
3665 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3666 // present, fall back to case 3.
3667 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3670 for (unsigned i = 0; i < 16; ++i) {
3671 int EltIdx = MaskVals[i];
3680 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3681 if (TLI.getSubtarget()->hasSSSE3()) {
3682 SmallVector<SDValue,16> pshufbMask;
3684 // If all result elements are from one input vector, then only translate
3685 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3687 // Otherwise, we have elements from both input vectors, and must zero out
3688 // elements that come from V2 in the first mask, and V1 in the second mask
3689 // so that we can OR them together.
3690 bool TwoInputs = !(V1Only || V2Only);
3691 for (unsigned i = 0; i != 16; ++i) {
3692 int EltIdx = MaskVals[i];
3693 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3694 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3697 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3699 // If all the elements are from V2, assign it to V1 and return after
3700 // building the first pshufb.
3703 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3704 DAG.getNode(ISD::BUILD_VECTOR, dl,
3705 MVT::v16i8, &pshufbMask[0], 16));
3709 // Calculate the shuffle mask for the second input, shuffle it, and
3710 // OR it with the first shuffled input.
3712 for (unsigned i = 0; i != 16; ++i) {
3713 int EltIdx = MaskVals[i];
3715 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3718 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3720 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3721 DAG.getNode(ISD::BUILD_VECTOR, dl,
3722 MVT::v16i8, &pshufbMask[0], 16));
3723 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3726 // No SSSE3 - Calculate in place words and then fix all out of place words
3727 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
3728 // the 16 different words that comprise the two doublequadword input vectors.
3729 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3730 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
3731 SDValue NewV = V2Only ? V2 : V1;
3732 for (int i = 0; i != 8; ++i) {
3733 int Elt0 = MaskVals[i*2];
3734 int Elt1 = MaskVals[i*2+1];
3736 // This word of the result is all undef, skip it.
3737 if (Elt0 < 0 && Elt1 < 0)
3740 // This word of the result is already in the correct place, skip it.
3741 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
3743 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
3746 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
3747 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
3750 // If Elt0 and Elt1 are defined, are consecutive, and can be load
3751 // using a single extract together, load it and store it.
3752 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
3753 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3754 DAG.getIntPtrConstant(Elt1 / 2));
3755 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3756 DAG.getIntPtrConstant(i));
3760 // If Elt1 is defined, extract it from the appropriate source. If the
3761 // source byte is not also odd, shift the extracted word left 8 bits
3762 // otherwise clear the bottom 8 bits if we need to do an or.
3764 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3765 DAG.getIntPtrConstant(Elt1 / 2));
3766 if ((Elt1 & 1) == 0)
3767 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
3768 DAG.getConstant(8, TLI.getShiftAmountTy()));
3770 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
3771 DAG.getConstant(0xFF00, MVT::i16));
3773 // If Elt0 is defined, extract it from the appropriate source. If the
3774 // source byte is not also even, shift the extracted word right 8 bits. If
3775 // Elt1 was also defined, OR the extracted values together before
3776 // inserting them in the result.
3778 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
3779 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
3780 if ((Elt0 & 1) != 0)
3781 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
3782 DAG.getConstant(8, TLI.getShiftAmountTy()));
3784 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
3785 DAG.getConstant(0x00FF, MVT::i16));
3786 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
3789 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3790 DAG.getIntPtrConstant(i));
3792 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
3795 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3796 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3797 /// done when every pair / quad of shuffle mask elements point to elements in
3798 /// the right sequence. e.g.
3799 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3801 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
3803 TargetLowering &TLI, DebugLoc dl) {
3804 MVT VT = SVOp->getValueType(0);
3805 SDValue V1 = SVOp->getOperand(0);
3806 SDValue V2 = SVOp->getOperand(1);
3807 unsigned NumElems = VT.getVectorNumElements();
3808 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3809 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3810 MVT MaskEltVT = MaskVT.getVectorElementType();
3812 switch (VT.getSimpleVT()) {
3813 default: assert(false && "Unexpected!");
3814 case MVT::v4f32: NewVT = MVT::v2f64; break;
3815 case MVT::v4i32: NewVT = MVT::v2i64; break;
3816 case MVT::v8i16: NewVT = MVT::v4i32; break;
3817 case MVT::v16i8: NewVT = MVT::v4i32; break;
3820 if (NewWidth == 2) {
3826 int Scale = NumElems / NewWidth;
3827 SmallVector<int, 8> MaskVec;
3828 for (unsigned i = 0; i < NumElems; i += Scale) {
3830 for (int j = 0; j < Scale; ++j) {
3831 int EltIdx = SVOp->getMaskElt(i+j);
3835 StartIdx = EltIdx - (EltIdx % Scale);
3836 if (EltIdx != StartIdx + j)
3840 MaskVec.push_back(-1);
3842 MaskVec.push_back(StartIdx / Scale);
3845 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
3846 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
3847 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
3850 /// getVZextMovL - Return a zero-extending vector move low node.
3852 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3853 SDValue SrcOp, SelectionDAG &DAG,
3854 const X86Subtarget *Subtarget, DebugLoc dl) {
3855 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3856 LoadSDNode *LD = NULL;
3857 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3858 LD = dyn_cast<LoadSDNode>(SrcOp);
3860 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3862 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3863 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3864 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3865 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3866 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3868 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3869 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3870 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3871 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3879 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3880 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3881 DAG.getNode(ISD::BIT_CONVERT, dl,
3885 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3888 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3889 SDValue V1 = SVOp->getOperand(0);
3890 SDValue V2 = SVOp->getOperand(1);
3891 DebugLoc dl = SVOp->getDebugLoc();
3892 MVT VT = SVOp->getValueType(0);
3894 SmallVector<std::pair<int, int>, 8> Locs;
3896 SmallVector<int, 8> Mask1(4U, -1);
3897 SmallVector<int, 8> PermMask;
3898 SVOp->getMask(PermMask);
3902 for (unsigned i = 0; i != 4; ++i) {
3903 int Idx = PermMask[i];
3905 Locs[i] = std::make_pair(-1, -1);
3907 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
3909 Locs[i] = std::make_pair(0, NumLo);
3913 Locs[i] = std::make_pair(1, NumHi);
3915 Mask1[2+NumHi] = Idx;
3921 if (NumLo <= 2 && NumHi <= 2) {
3922 // If no more than two elements come from either vector. This can be
3923 // implemented with two shuffles. First shuffle gather the elements.
3924 // The second shuffle, which takes the first shuffle as both of its
3925 // vector operands, put the elements into the right order.
3926 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
3928 SmallVector<int, 8> Mask2(4U, -1);
3930 for (unsigned i = 0; i != 4; ++i) {
3931 if (Locs[i].first == -1)
3934 unsigned Idx = (i < 2) ? 0 : 4;
3935 Idx += Locs[i].first * 2 + Locs[i].second;
3940 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
3941 } else if (NumLo == 3 || NumHi == 3) {
3942 // Otherwise, we must have three elements from one vector, call it X, and
3943 // one element from the other, call it Y. First, use a shufps to build an
3944 // intermediate vector with the one element from Y and the element from X
3945 // that will be in the same half in the final destination (the indexes don't
3946 // matter). Then, use a shufps to build the final vector, taking the half
3947 // containing the element from Y from the intermediate, and the other half
3950 // Normalize it so the 3 elements come from V1.
3951 CommuteVectorShuffleMask(PermMask, VT);
3955 // Find the element from V2.
3957 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3958 int Val = PermMask[HiIndex];
3965 Mask1[0] = PermMask[HiIndex];
3967 Mask1[2] = PermMask[HiIndex^1];
3969 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
3972 Mask1[0] = PermMask[0];
3973 Mask1[1] = PermMask[1];
3974 Mask1[2] = HiIndex & 1 ? 6 : 4;
3975 Mask1[3] = HiIndex & 1 ? 4 : 6;
3976 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
3978 Mask1[0] = HiIndex & 1 ? 2 : 0;
3979 Mask1[1] = HiIndex & 1 ? 0 : 2;
3980 Mask1[2] = PermMask[2];
3981 Mask1[3] = PermMask[3];
3986 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
3990 // Break it into (shuffle shuffle_hi, shuffle_lo).
3992 SmallVector<int,8> LoMask(4U, -1);
3993 SmallVector<int,8> HiMask(4U, -1);
3995 SmallVector<int,8> *MaskPtr = &LoMask;
3996 unsigned MaskIdx = 0;
3999 for (unsigned i = 0; i != 4; ++i) {
4006 int Idx = PermMask[i];
4008 Locs[i] = std::make_pair(-1, -1);
4009 } else if (Idx < 4) {
4010 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4011 (*MaskPtr)[LoIdx] = Idx;
4014 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4015 (*MaskPtr)[HiIdx] = Idx;
4020 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4021 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4022 SmallVector<int, 8> MaskOps;
4023 for (unsigned i = 0; i != 4; ++i) {
4024 if (Locs[i].first == -1) {
4025 MaskOps.push_back(-1);
4027 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4028 MaskOps.push_back(Idx);
4031 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4035 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4036 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4037 SDValue V1 = Op.getOperand(0);
4038 SDValue V2 = Op.getOperand(1);
4039 MVT VT = Op.getValueType();
4040 DebugLoc dl = Op.getDebugLoc();
4041 unsigned NumElems = VT.getVectorNumElements();
4042 bool isMMX = VT.getSizeInBits() == 64;
4043 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4044 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4045 bool V1IsSplat = false;
4046 bool V2IsSplat = false;
4048 if (isZeroShuffle(SVOp))
4049 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4051 // Promote splats to v4f32.
4052 if (SVOp->isSplat()) {
4053 if (isMMX || NumElems < 4)
4055 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4058 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4060 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4061 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4062 if (NewOp.getNode())
4063 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4064 LowerVECTOR_SHUFFLE(NewOp, DAG));
4065 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4066 // FIXME: Figure out a cleaner way to do this.
4067 // Try to make use of movq to zero out the top part.
4068 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4069 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4070 if (NewOp.getNode()) {
4071 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4072 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4073 DAG, Subtarget, dl);
4075 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4076 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4077 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4078 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4079 DAG, Subtarget, dl);
4083 if (X86::isPSHUFDMask(SVOp))
4086 // Check if this can be converted into a logical shift.
4087 bool isLeft = false;
4090 bool isShift = getSubtarget()->hasSSE2() &&
4091 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4092 if (isShift && ShVal.hasOneUse()) {
4093 // If the shifted value has multiple uses, it may be cheaper to use
4094 // v_set0 + movlhps or movhlps, etc.
4095 MVT EVT = VT.getVectorElementType();
4096 ShAmt *= EVT.getSizeInBits();
4097 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4100 if (X86::isMOVLMask(SVOp)) {
4103 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4104 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4109 // FIXME: fold these into legal mask.
4110 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4111 X86::isMOVSLDUPMask(SVOp) ||
4112 X86::isMOVHLPSMask(SVOp) ||
4113 X86::isMOVHPMask(SVOp) ||
4114 X86::isMOVLPMask(SVOp)))
4117 if (ShouldXformToMOVHLPS(SVOp) ||
4118 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4119 return CommuteVectorShuffle(SVOp, DAG);
4122 // No better options. Use a vshl / vsrl.
4123 MVT EVT = VT.getVectorElementType();
4124 ShAmt *= EVT.getSizeInBits();
4125 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4128 bool Commuted = false;
4129 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4130 // 1,1,1,1 -> v8i16 though.
4131 V1IsSplat = isSplatVector(V1.getNode());
4132 V2IsSplat = isSplatVector(V2.getNode());
4134 // Canonicalize the splat or undef, if present, to be on the RHS.
4135 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4136 Op = CommuteVectorShuffle(SVOp, DAG);
4137 SVOp = cast<ShuffleVectorSDNode>(Op);
4138 V1 = SVOp->getOperand(0);
4139 V2 = SVOp->getOperand(1);
4140 std::swap(V1IsSplat, V2IsSplat);
4141 std::swap(V1IsUndef, V2IsUndef);
4145 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4146 // Shuffling low element of v1 into undef, just return v1.
4149 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4150 // the instruction selector will not match, so get a canonical MOVL with
4151 // swapped operands to undo the commute.
4152 return getMOVL(DAG, dl, VT, V2, V1);
4155 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4156 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4157 X86::isUNPCKLMask(SVOp) ||
4158 X86::isUNPCKHMask(SVOp))
4162 // Normalize mask so all entries that point to V2 points to its first
4163 // element then try to match unpck{h|l} again. If match, return a
4164 // new vector_shuffle with the corrected mask.
4165 SDValue NewMask = NormalizeMask(SVOp, DAG);
4166 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4167 if (NSVOp != SVOp) {
4168 if (X86::isUNPCKLMask(NSVOp, true)) {
4170 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4177 // Commute is back and try unpck* again.
4178 // FIXME: this seems wrong.
4179 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4180 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4181 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4182 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4183 X86::isUNPCKLMask(NewSVOp) ||
4184 X86::isUNPCKHMask(NewSVOp))
4188 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4190 // Normalize the node to match x86 shuffle ops if needed
4191 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4192 return CommuteVectorShuffle(SVOp, DAG);
4194 // Check for legal shuffle and return?
4195 SmallVector<int, 16> PermMask;
4196 SVOp->getMask(PermMask);
4197 if (isShuffleMaskLegal(PermMask, VT))
4200 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4201 if (VT == MVT::v8i16) {
4202 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4203 if (NewOp.getNode())
4207 if (VT == MVT::v16i8) {
4208 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4209 if (NewOp.getNode())
4213 // Handle all 4 wide cases with a number of shuffles except for MMX.
4214 if (NumElems == 4 && !isMMX)
4215 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4221 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4222 SelectionDAG &DAG) {
4223 MVT VT = Op.getValueType();
4224 DebugLoc dl = Op.getDebugLoc();
4225 if (VT.getSizeInBits() == 8) {
4226 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4227 Op.getOperand(0), Op.getOperand(1));
4228 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4229 DAG.getValueType(VT));
4230 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4231 } else if (VT.getSizeInBits() == 16) {
4232 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4233 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4235 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4236 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4237 DAG.getNode(ISD::BIT_CONVERT, dl,
4241 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4242 Op.getOperand(0), Op.getOperand(1));
4243 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4244 DAG.getValueType(VT));
4245 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4246 } else if (VT == MVT::f32) {
4247 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4248 // the result back to FR32 register. It's only worth matching if the
4249 // result has a single use which is a store or a bitcast to i32. And in
4250 // the case of a store, it's not worth it if the index is a constant 0,
4251 // because a MOVSSmr can be used instead, which is smaller and faster.
4252 if (!Op.hasOneUse())
4254 SDNode *User = *Op.getNode()->use_begin();
4255 if ((User->getOpcode() != ISD::STORE ||
4256 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4257 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4258 (User->getOpcode() != ISD::BIT_CONVERT ||
4259 User->getValueType(0) != MVT::i32))
4261 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4262 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4265 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4266 } else if (VT == MVT::i32) {
4267 // ExtractPS works with constant index.
4268 if (isa<ConstantSDNode>(Op.getOperand(1)))
4276 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4277 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4280 if (Subtarget->hasSSE41()) {
4281 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4286 MVT VT = Op.getValueType();
4287 DebugLoc dl = Op.getDebugLoc();
4288 // TODO: handle v16i8.
4289 if (VT.getSizeInBits() == 16) {
4290 SDValue Vec = Op.getOperand(0);
4291 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4293 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4294 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4295 DAG.getNode(ISD::BIT_CONVERT, dl,
4298 // Transform it so it match pextrw which produces a 32-bit result.
4299 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4300 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
4301 Op.getOperand(0), Op.getOperand(1));
4302 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
4303 DAG.getValueType(VT));
4304 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4305 } else if (VT.getSizeInBits() == 32) {
4306 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4310 // SHUFPS the element to the lowest double word, then movss.
4311 int Mask[4] = { Idx, -1, -1, -1 };
4312 MVT VVT = Op.getOperand(0).getValueType();
4313 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4314 DAG.getUNDEF(VVT), Mask);
4315 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4316 DAG.getIntPtrConstant(0));
4317 } else if (VT.getSizeInBits() == 64) {
4318 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4319 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4320 // to match extract_elt for f64.
4321 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4325 // UNPCKHPD the element to the lowest double word, then movsd.
4326 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4327 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4328 int Mask[2] = { 1, -1 };
4329 MVT VVT = Op.getOperand(0).getValueType();
4330 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4331 DAG.getUNDEF(VVT), Mask);
4332 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4333 DAG.getIntPtrConstant(0));
4340 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4341 MVT VT = Op.getValueType();
4342 MVT EVT = VT.getVectorElementType();
4343 DebugLoc dl = Op.getDebugLoc();
4345 SDValue N0 = Op.getOperand(0);
4346 SDValue N1 = Op.getOperand(1);
4347 SDValue N2 = Op.getOperand(2);
4349 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4350 isa<ConstantSDNode>(N2)) {
4351 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4353 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4355 if (N1.getValueType() != MVT::i32)
4356 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4357 if (N2.getValueType() != MVT::i32)
4358 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4359 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4360 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4361 // Bits [7:6] of the constant are the source select. This will always be
4362 // zero here. The DAG Combiner may combine an extract_elt index into these
4363 // bits. For example (insert (extract, 3), 2) could be matched by putting
4364 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4365 // Bits [5:4] of the constant are the destination select. This is the
4366 // value of the incoming immediate.
4367 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4368 // combine either bitwise AND or insert of float 0.0 to set these bits.
4369 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4370 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4371 } else if (EVT == MVT::i32) {
4372 // InsertPS works with constant index.
4373 if (isa<ConstantSDNode>(N2))
4380 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4381 MVT VT = Op.getValueType();
4382 MVT EVT = VT.getVectorElementType();
4384 if (Subtarget->hasSSE41())
4385 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4390 DebugLoc dl = Op.getDebugLoc();
4391 SDValue N0 = Op.getOperand(0);
4392 SDValue N1 = Op.getOperand(1);
4393 SDValue N2 = Op.getOperand(2);
4395 if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4396 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4397 // as its second argument.
4398 if (N1.getValueType() != MVT::i32)
4399 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4400 if (N2.getValueType() != MVT::i32)
4401 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4402 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4408 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4409 DebugLoc dl = Op.getDebugLoc();
4410 if (Op.getValueType() == MVT::v2f32)
4411 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4412 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4413 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4414 Op.getOperand(0))));
4416 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4417 MVT VT = MVT::v2i32;
4418 switch (Op.getValueType().getSimpleVT()) {
4425 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4426 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4429 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4430 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4431 // one of the above mentioned nodes. It has to be wrapped because otherwise
4432 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4433 // be used to form addressing mode. These wrapped nodes will be selected
4436 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4437 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4439 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4441 unsigned char OpFlag = 0;
4442 unsigned WrapperKind = X86ISD::Wrapper;
4443 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
4444 if (Subtarget->isPICStyleStub())
4445 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4446 else if (Subtarget->isPICStyleGOT())
4447 OpFlag = X86II::MO_GOTOFF;
4448 else if (Subtarget->isPICStyleRIPRel() &&
4449 getTargetMachine().getCodeModel() == CodeModel::Small)
4450 WrapperKind = X86ISD::WrapperRIP;
4453 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4455 CP->getOffset(), OpFlag);
4456 DebugLoc DL = CP->getDebugLoc();
4457 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4458 // With PIC, the address is actually $g + Offset.
4460 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4461 DAG.getNode(X86ISD::GlobalBaseReg,
4462 DebugLoc::getUnknownLoc(), getPointerTy()),
4469 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4470 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4472 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4474 unsigned char OpFlag = 0;
4475 unsigned WrapperKind = X86ISD::Wrapper;
4476 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
4477 if (Subtarget->isPICStyleStub())
4478 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4479 else if (Subtarget->isPICStyleGOT())
4480 OpFlag = X86II::MO_GOTOFF;
4481 else if (Subtarget->isPICStyleRIPRel())
4482 WrapperKind = X86ISD::WrapperRIP;
4485 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4487 DebugLoc DL = JT->getDebugLoc();
4488 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4490 // With PIC, the address is actually $g + Offset.
4492 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4493 DAG.getNode(X86ISD::GlobalBaseReg,
4494 DebugLoc::getUnknownLoc(), getPointerTy()),
4502 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4503 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4505 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4507 unsigned char OpFlag = 0;
4508 unsigned WrapperKind = X86ISD::Wrapper;
4509 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
4510 if (Subtarget->isPICStyleStub())
4511 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4512 else if (Subtarget->isPICStyleGOT())
4513 OpFlag = X86II::MO_GOTOFF;
4514 else if (Subtarget->isPICStyleRIPRel())
4515 WrapperKind = X86ISD::WrapperRIP;
4518 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4520 DebugLoc DL = Op.getDebugLoc();
4521 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4524 // With PIC, the address is actually $g + Offset.
4525 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4526 !Subtarget->isPICStyleRIPRel()) {
4527 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4528 DAG.getNode(X86ISD::GlobalBaseReg,
4529 DebugLoc::getUnknownLoc(),
4538 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4540 SelectionDAG &DAG) const {
4541 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
4542 bool ExtraLoadRequired =
4543 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false);
4545 // Create the TargetGlobalAddress node, folding in the constant
4546 // offset if it is legal.
4548 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) {
4549 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4552 unsigned char OpFlags = 0;
4554 if (Subtarget->isPICStyleRIPRel() &&
4555 getTargetMachine().getRelocationModel() != Reloc::Static) {
4556 if (ExtraLoadRequired)
4557 OpFlags = X86II::MO_GOTPCREL;
4558 } else if (Subtarget->isPICStyleGOT() &&
4559 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
4560 if (ExtraLoadRequired)
4561 OpFlags = X86II::MO_GOT;
4563 OpFlags = X86II::MO_GOTOFF;
4566 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4569 if (Subtarget->isPICStyleRIPRel() &&
4570 getTargetMachine().getCodeModel() == CodeModel::Small)
4571 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4573 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4575 // With PIC, the address is actually $g + Offset.
4576 if (IsPic && !Subtarget->isPICStyleRIPRel()) {
4577 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4578 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4582 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4583 // load the value at address GV, not the value of GV itself. This means that
4584 // the GlobalAddress must be in the base or index register of the address, not
4585 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4586 // The same applies for external symbols during PIC codegen
4587 if (ExtraLoadRequired)
4588 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4589 PseudoSourceValue::getGOT(), 0);
4591 // If there was a non-zero offset that we didn't fold, create an explicit
4594 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4595 DAG.getConstant(Offset, getPointerTy()));
4601 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4602 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4603 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4604 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4608 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4609 SDValue *InFlag, const MVT PtrVT, unsigned ReturnReg,
4610 unsigned char OperandFlags) {
4611 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4612 DebugLoc dl = GA->getDebugLoc();
4613 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4614 GA->getValueType(0),
4618 SDValue Ops[] = { Chain, TGA, *InFlag };
4619 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4621 SDValue Ops[] = { Chain, TGA };
4622 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4624 SDValue Flag = Chain.getValue(1);
4625 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4628 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4630 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4633 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4634 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4635 DAG.getNode(X86ISD::GlobalBaseReg,
4636 DebugLoc::getUnknownLoc(),
4638 InFlag = Chain.getValue(1);
4640 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4643 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4645 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4647 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4648 X86::RAX, X86II::MO_TLSGD);
4651 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4652 // "local exec" model.
4653 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4654 const MVT PtrVT, TLSModel::Model model,
4656 DebugLoc dl = GA->getDebugLoc();
4657 // Get the Thread Pointer
4658 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4659 DebugLoc::getUnknownLoc(), PtrVT,
4660 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4663 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4666 unsigned char OperandFlags = 0;
4667 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4669 unsigned WrapperKind = X86ISD::Wrapper;
4670 if (model == TLSModel::LocalExec) {
4671 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4672 } else if (is64Bit) {
4673 assert(model == TLSModel::InitialExec);
4674 OperandFlags = X86II::MO_GOTTPOFF;
4675 WrapperKind = X86ISD::WrapperRIP;
4677 assert(model == TLSModel::InitialExec);
4678 OperandFlags = X86II::MO_INDNTPOFF;
4681 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4683 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4684 GA->getOffset(), OperandFlags);
4685 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4687 if (model == TLSModel::InitialExec)
4688 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4689 PseudoSourceValue::getGOT(), 0);
4691 // The address of the thread local variable is the add of the thread
4692 // pointer with the offset of the variable.
4693 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
4697 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4698 // TODO: implement the "local dynamic" model
4699 // TODO: implement the "initial exec"model for pic executables
4700 assert(Subtarget->isTargetELF() &&
4701 "TLS not implemented for non-ELF targets");
4702 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4703 const GlobalValue *GV = GA->getGlobal();
4705 // If GV is an alias then use the aliasee for determining
4706 // thread-localness.
4707 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
4708 GV = GA->resolveAliasedGlobal(false);
4710 TLSModel::Model model = getTLSModel(GV,
4711 getTargetMachine().getRelocationModel());
4714 case TLSModel::GeneralDynamic:
4715 case TLSModel::LocalDynamic: // not implemented
4716 if (Subtarget->is64Bit())
4717 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4718 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4720 case TLSModel::InitialExec:
4721 case TLSModel::LocalExec:
4722 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
4723 Subtarget->is64Bit());
4726 assert(0 && "Unreachable");
4731 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4732 /// take a 2 x i32 value to shift plus a shift amount.
4733 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4734 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4735 MVT VT = Op.getValueType();
4736 unsigned VTBits = VT.getSizeInBits();
4737 DebugLoc dl = Op.getDebugLoc();
4738 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4739 SDValue ShOpLo = Op.getOperand(0);
4740 SDValue ShOpHi = Op.getOperand(1);
4741 SDValue ShAmt = Op.getOperand(2);
4742 SDValue Tmp1 = isSRA ?
4743 DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
4744 DAG.getConstant(VTBits - 1, MVT::i8)) :
4745 DAG.getConstant(0, VT);
4748 if (Op.getOpcode() == ISD::SHL_PARTS) {
4749 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
4750 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4752 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
4753 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
4756 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
4757 DAG.getConstant(VTBits, MVT::i8));
4758 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
4759 AndNode, DAG.getConstant(0, MVT::i8));
4762 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4763 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4764 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4766 if (Op.getOpcode() == ISD::SHL_PARTS) {
4767 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4768 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4770 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4771 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4774 SDValue Ops[2] = { Lo, Hi };
4775 return DAG.getMergeValues(Ops, 2, dl);
4778 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4779 MVT SrcVT = Op.getOperand(0).getValueType();
4781 if (SrcVT.isVector()) {
4782 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
4788 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4789 "Unknown SINT_TO_FP to lower!");
4791 // These are really Legal; return the operand so the caller accepts it as
4793 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4795 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
4796 Subtarget->is64Bit()) {
4800 DebugLoc dl = Op.getDebugLoc();
4801 unsigned Size = SrcVT.getSizeInBits()/8;
4802 MachineFunction &MF = DAG.getMachineFunction();
4803 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4804 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4805 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
4807 PseudoSourceValue::getFixedStack(SSFI), 0);
4808 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
4811 SDValue X86TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain,
4813 SelectionDAG &DAG) {
4815 DebugLoc dl = Op.getDebugLoc();
4817 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4819 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4821 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4822 SmallVector<SDValue, 8> Ops;
4823 Ops.push_back(Chain);
4824 Ops.push_back(StackSlot);
4825 Ops.push_back(DAG.getValueType(SrcVT));
4826 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
4827 Tys, &Ops[0], Ops.size());
4830 Chain = Result.getValue(1);
4831 SDValue InFlag = Result.getValue(2);
4833 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4834 // shouldn't be necessary except that RFP cannot be live across
4835 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4836 MachineFunction &MF = DAG.getMachineFunction();
4837 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4838 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4839 Tys = DAG.getVTList(MVT::Other);
4840 SmallVector<SDValue, 8> Ops;
4841 Ops.push_back(Chain);
4842 Ops.push_back(Result);
4843 Ops.push_back(StackSlot);
4844 Ops.push_back(DAG.getValueType(Op.getValueType()));
4845 Ops.push_back(InFlag);
4846 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
4847 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
4848 PseudoSourceValue::getFixedStack(SSFI), 0);
4854 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
4855 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
4856 // This algorithm is not obvious. Here it is in C code, more or less:
4858 double uint64_to_double( uint32_t hi, uint32_t lo ) {
4859 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4860 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
4862 // Copy ints to xmm registers.
4863 __m128i xh = _mm_cvtsi32_si128( hi );
4864 __m128i xl = _mm_cvtsi32_si128( lo );
4866 // Combine into low half of a single xmm register.
4867 __m128i x = _mm_unpacklo_epi32( xh, xl );
4871 // Merge in appropriate exponents to give the integer bits the right
4873 x = _mm_unpacklo_epi32( x, exp );
4875 // Subtract away the biases to deal with the IEEE-754 double precision
4877 d = _mm_sub_pd( (__m128d) x, bias );
4879 // All conversions up to here are exact. The correctly rounded result is
4880 // calculated using the current rounding mode using the following
4882 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4883 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
4884 // store doesn't really need to be here (except
4885 // maybe to zero the other double)
4890 DebugLoc dl = Op.getDebugLoc();
4892 // Build some magic constants.
4893 std::vector<Constant*> CV0;
4894 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000)));
4895 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000)));
4896 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4897 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4898 Constant *C0 = ConstantVector::get(CV0);
4899 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
4901 std::vector<Constant*> CV1;
4902 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL))));
4903 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL))));
4904 Constant *C1 = ConstantVector::get(CV1);
4905 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
4907 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4908 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4910 DAG.getIntPtrConstant(1)));
4911 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4912 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4914 DAG.getIntPtrConstant(0)));
4915 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
4916 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
4917 PseudoSourceValue::getConstantPool(), 0,
4919 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
4920 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
4921 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
4922 PseudoSourceValue::getConstantPool(), 0,
4924 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
4926 // Add the halves; easiest way is to swap them into another reg first.
4927 int ShufMask[2] = { 1, -1 };
4928 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
4929 DAG.getUNDEF(MVT::v2f64), ShufMask);
4930 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
4931 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
4932 DAG.getIntPtrConstant(0));
4935 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
4936 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
4937 DebugLoc dl = Op.getDebugLoc();
4938 // FP constant to bias correct the final result.
4939 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
4942 // Load the 32-bit value into an XMM register.
4943 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4944 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4946 DAG.getIntPtrConstant(0)));
4948 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4949 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
4950 DAG.getIntPtrConstant(0));
4952 // Or the load with the bias.
4953 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
4954 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4955 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4957 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4958 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4959 MVT::v2f64, Bias)));
4960 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4961 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
4962 DAG.getIntPtrConstant(0));
4964 // Subtract the bias.
4965 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
4967 // Handle final rounding.
4968 MVT DestVT = Op.getValueType();
4970 if (DestVT.bitsLT(MVT::f64)) {
4971 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
4972 DAG.getIntPtrConstant(0));
4973 } else if (DestVT.bitsGT(MVT::f64)) {
4974 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
4977 // Handle final rounding.
4981 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4982 SDValue N0 = Op.getOperand(0);
4983 DebugLoc dl = Op.getDebugLoc();
4985 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
4986 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
4987 // the optimization here.
4988 if (DAG.SignBitIsZero(N0))
4989 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
4991 MVT SrcVT = N0.getValueType();
4992 if (SrcVT == MVT::i64) {
4993 // We only handle SSE2 f64 target here; caller can expand the rest.
4994 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
4997 return LowerUINT_TO_FP_i64(Op, DAG);
4998 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
4999 return LowerUINT_TO_FP_i32(Op, DAG);
5002 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5004 // Make a 64-bit buffer, and use it to build an FILD.
5005 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5006 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5007 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5008 getPointerTy(), StackSlot, WordOff);
5009 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5010 StackSlot, NULL, 0);
5011 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5012 OffsetSlot, NULL, 0);
5013 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5016 std::pair<SDValue,SDValue> X86TargetLowering::
5017 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5018 DebugLoc dl = Op.getDebugLoc();
5020 MVT DstTy = Op.getValueType();
5023 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5027 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5028 DstTy.getSimpleVT() >= MVT::i16 &&
5029 "Unknown FP_TO_SINT to lower!");
5031 // These are really Legal.
5032 if (DstTy == MVT::i32 &&
5033 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5034 return std::make_pair(SDValue(), SDValue());
5035 if (Subtarget->is64Bit() &&
5036 DstTy == MVT::i64 &&
5037 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5038 return std::make_pair(SDValue(), SDValue());
5040 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5042 MachineFunction &MF = DAG.getMachineFunction();
5043 unsigned MemSize = DstTy.getSizeInBits()/8;
5044 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5045 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5048 switch (DstTy.getSimpleVT()) {
5049 default: assert(0 && "Invalid FP_TO_SINT to lower!");
5050 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5051 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5052 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5055 SDValue Chain = DAG.getEntryNode();
5056 SDValue Value = Op.getOperand(0);
5057 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5058 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5059 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5060 PseudoSourceValue::getFixedStack(SSFI), 0);
5061 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5063 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5065 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5066 Chain = Value.getValue(1);
5067 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5068 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5071 // Build the FP_TO_INT*_IN_MEM
5072 SDValue Ops[] = { Chain, Value, StackSlot };
5073 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5075 return std::make_pair(FIST, StackSlot);
5078 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5079 if (Op.getValueType().isVector()) {
5080 if (Op.getValueType() == MVT::v2i32 &&
5081 Op.getOperand(0).getValueType() == MVT::v2f64) {
5087 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5088 SDValue FIST = Vals.first, StackSlot = Vals.second;
5089 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5090 if (FIST.getNode() == 0) return Op;
5093 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5094 FIST, StackSlot, NULL, 0);
5097 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5098 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5099 SDValue FIST = Vals.first, StackSlot = Vals.second;
5100 assert(FIST.getNode() && "Unexpected failure");
5103 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5104 FIST, StackSlot, NULL, 0);
5107 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5108 DebugLoc dl = Op.getDebugLoc();
5109 MVT VT = Op.getValueType();
5112 EltVT = VT.getVectorElementType();
5113 std::vector<Constant*> CV;
5114 if (EltVT == MVT::f64) {
5115 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
5119 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
5125 Constant *C = ConstantVector::get(CV);
5126 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5127 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5128 PseudoSourceValue::getConstantPool(), 0,
5130 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5133 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5134 DebugLoc dl = Op.getDebugLoc();
5135 MVT VT = Op.getValueType();
5137 unsigned EltNum = 1;
5138 if (VT.isVector()) {
5139 EltVT = VT.getVectorElementType();
5140 EltNum = VT.getVectorNumElements();
5142 std::vector<Constant*> CV;
5143 if (EltVT == MVT::f64) {
5144 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
5148 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
5154 Constant *C = ConstantVector::get(CV);
5155 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5156 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5157 PseudoSourceValue::getConstantPool(), 0,
5159 if (VT.isVector()) {
5160 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5161 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5162 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5164 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5166 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5170 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5171 SDValue Op0 = Op.getOperand(0);
5172 SDValue Op1 = Op.getOperand(1);
5173 DebugLoc dl = Op.getDebugLoc();
5174 MVT VT = Op.getValueType();
5175 MVT SrcVT = Op1.getValueType();
5177 // If second operand is smaller, extend it first.
5178 if (SrcVT.bitsLT(VT)) {
5179 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5182 // And if it is bigger, shrink it first.
5183 if (SrcVT.bitsGT(VT)) {
5184 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5188 // At this point the operands and the result should have the same
5189 // type, and that won't be f80 since that is not custom lowered.
5191 // First get the sign bit of second operand.
5192 std::vector<Constant*> CV;
5193 if (SrcVT == MVT::f64) {
5194 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
5195 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
5197 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
5198 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5199 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5200 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5202 Constant *C = ConstantVector::get(CV);
5203 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5204 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5205 PseudoSourceValue::getConstantPool(), 0,
5207 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5209 // Shift sign bit right or left if the two operands have different types.
5210 if (SrcVT.bitsGT(VT)) {
5211 // Op0 is MVT::f32, Op1 is MVT::f64.
5212 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5213 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5214 DAG.getConstant(32, MVT::i32));
5215 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5216 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5217 DAG.getIntPtrConstant(0));
5220 // Clear first operand sign bit.
5222 if (VT == MVT::f64) {
5223 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
5224 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
5226 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
5227 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5228 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5229 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5231 C = ConstantVector::get(CV);
5232 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5233 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5234 PseudoSourceValue::getConstantPool(), 0,
5236 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5238 // Or the value with the sign bit.
5239 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5242 /// Emit nodes that will be selected as "test Op0,Op0", or something
5244 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5245 SelectionDAG &DAG) {
5246 DebugLoc dl = Op.getDebugLoc();
5248 // CF and OF aren't always set the way we want. Determine which
5249 // of these we need.
5250 bool NeedCF = false;
5251 bool NeedOF = false;
5253 case X86::COND_A: case X86::COND_AE:
5254 case X86::COND_B: case X86::COND_BE:
5257 case X86::COND_G: case X86::COND_GE:
5258 case X86::COND_L: case X86::COND_LE:
5259 case X86::COND_O: case X86::COND_NO:
5265 // See if we can use the EFLAGS value from the operand instead of
5266 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5267 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5268 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5269 unsigned Opcode = 0;
5270 unsigned NumOperands = 0;
5271 switch (Op.getNode()->getOpcode()) {
5273 // Due to an isel shortcoming, be conservative if this add is likely to
5274 // be selected as part of a load-modify-store instruction. When the root
5275 // node in a match is a store, isel doesn't know how to remap non-chain
5276 // non-flag uses of other nodes in the match, such as the ADD in this
5277 // case. This leads to the ADD being left around and reselected, with
5278 // the result being two adds in the output.
5279 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5280 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5281 if (UI->getOpcode() == ISD::STORE)
5283 if (ConstantSDNode *C =
5284 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5285 // An add of one will be selected as an INC.
5286 if (C->getAPIntValue() == 1) {
5287 Opcode = X86ISD::INC;
5291 // An add of negative one (subtract of one) will be selected as a DEC.
5292 if (C->getAPIntValue().isAllOnesValue()) {
5293 Opcode = X86ISD::DEC;
5298 // Otherwise use a regular EFLAGS-setting add.
5299 Opcode = X86ISD::ADD;
5303 // Due to the ISEL shortcoming noted above, be conservative if this sub is
5304 // likely to be selected as part of a load-modify-store instruction.
5305 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5306 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5307 if (UI->getOpcode() == ISD::STORE)
5309 // Otherwise use a regular EFLAGS-setting sub.
5310 Opcode = X86ISD::SUB;
5317 return SDValue(Op.getNode(), 1);
5323 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5324 SmallVector<SDValue, 4> Ops;
5325 for (unsigned i = 0; i != NumOperands; ++i)
5326 Ops.push_back(Op.getOperand(i));
5327 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5328 DAG.ReplaceAllUsesWith(Op, New);
5329 return SDValue(New.getNode(), 1);
5333 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5334 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5335 DAG.getConstant(0, Op.getValueType()));
5338 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5340 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5341 SelectionDAG &DAG) {
5342 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5343 if (C->getAPIntValue() == 0)
5344 return EmitTest(Op0, X86CC, DAG);
5346 DebugLoc dl = Op0.getDebugLoc();
5347 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5350 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5351 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5352 SDValue Op0 = Op.getOperand(0);
5353 SDValue Op1 = Op.getOperand(1);
5354 DebugLoc dl = Op.getDebugLoc();
5355 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5357 // Lower (X & (1 << N)) == 0 to BT(X, N).
5358 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5359 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5360 if (Op0.getOpcode() == ISD::AND &&
5362 Op1.getOpcode() == ISD::Constant &&
5363 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5364 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5366 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5367 if (ConstantSDNode *Op010C =
5368 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5369 if (Op010C->getZExtValue() == 1) {
5370 LHS = Op0.getOperand(0);
5371 RHS = Op0.getOperand(1).getOperand(1);
5373 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5374 if (ConstantSDNode *Op000C =
5375 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5376 if (Op000C->getZExtValue() == 1) {
5377 LHS = Op0.getOperand(1);
5378 RHS = Op0.getOperand(0).getOperand(1);
5380 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5381 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5382 SDValue AndLHS = Op0.getOperand(0);
5383 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5384 LHS = AndLHS.getOperand(0);
5385 RHS = AndLHS.getOperand(1);
5389 if (LHS.getNode()) {
5390 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5391 // instruction. Since the shift amount is in-range-or-undefined, we know
5392 // that doing a bittest on the i16 value is ok. We extend to i32 because
5393 // the encoding for the i16 version is larger than the i32 version.
5394 if (LHS.getValueType() == MVT::i8)
5395 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5397 // If the operand types disagree, extend the shift amount to match. Since
5398 // BT ignores high bits (like shifts) we can use anyextend.
5399 if (LHS.getValueType() != RHS.getValueType())
5400 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5402 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5403 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5404 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5405 DAG.getConstant(Cond, MVT::i8), BT);
5409 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5410 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5412 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5413 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5414 DAG.getConstant(X86CC, MVT::i8), Cond);
5417 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5419 SDValue Op0 = Op.getOperand(0);
5420 SDValue Op1 = Op.getOperand(1);
5421 SDValue CC = Op.getOperand(2);
5422 MVT VT = Op.getValueType();
5423 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5424 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5425 DebugLoc dl = Op.getDebugLoc();
5429 MVT VT0 = Op0.getValueType();
5430 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5431 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5434 switch (SetCCOpcode) {
5437 case ISD::SETEQ: SSECC = 0; break;
5439 case ISD::SETGT: Swap = true; // Fallthrough
5441 case ISD::SETOLT: SSECC = 1; break;
5443 case ISD::SETGE: Swap = true; // Fallthrough
5445 case ISD::SETOLE: SSECC = 2; break;
5446 case ISD::SETUO: SSECC = 3; break;
5448 case ISD::SETNE: SSECC = 4; break;
5449 case ISD::SETULE: Swap = true;
5450 case ISD::SETUGE: SSECC = 5; break;
5451 case ISD::SETULT: Swap = true;
5452 case ISD::SETUGT: SSECC = 6; break;
5453 case ISD::SETO: SSECC = 7; break;
5456 std::swap(Op0, Op1);
5458 // In the two special cases we can't handle, emit two comparisons.
5460 if (SetCCOpcode == ISD::SETUEQ) {
5462 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5463 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5464 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5466 else if (SetCCOpcode == ISD::SETONE) {
5468 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5469 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5470 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5472 assert(0 && "Illegal FP comparison");
5474 // Handle all other FP comparisons here.
5475 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5478 // We are handling one of the integer comparisons here. Since SSE only has
5479 // GT and EQ comparisons for integer, swapping operands and multiple
5480 // operations may be required for some comparisons.
5481 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5482 bool Swap = false, Invert = false, FlipSigns = false;
5484 switch (VT.getSimpleVT()) {
5486 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5487 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5488 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5489 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5492 switch (SetCCOpcode) {
5494 case ISD::SETNE: Invert = true;
5495 case ISD::SETEQ: Opc = EQOpc; break;
5496 case ISD::SETLT: Swap = true;
5497 case ISD::SETGT: Opc = GTOpc; break;
5498 case ISD::SETGE: Swap = true;
5499 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5500 case ISD::SETULT: Swap = true;
5501 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5502 case ISD::SETUGE: Swap = true;
5503 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5506 std::swap(Op0, Op1);
5508 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5509 // bits of the inputs before performing those operations.
5511 MVT EltVT = VT.getVectorElementType();
5512 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5514 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5515 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5517 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5518 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5521 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5523 // If the logical-not of the result is required, perform that now.
5525 Result = DAG.getNOT(dl, Result, VT);
5530 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5531 static bool isX86LogicalCmp(SDValue Op) {
5532 unsigned Opc = Op.getNode()->getOpcode();
5533 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5535 if (Op.getResNo() == 1 &&
5536 (Opc == X86ISD::ADD ||
5537 Opc == X86ISD::SUB ||
5538 Opc == X86ISD::SMUL ||
5539 Opc == X86ISD::UMUL ||
5540 Opc == X86ISD::INC ||
5541 Opc == X86ISD::DEC))
5547 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5548 bool addTest = true;
5549 SDValue Cond = Op.getOperand(0);
5550 DebugLoc dl = Op.getDebugLoc();
5553 if (Cond.getOpcode() == ISD::SETCC)
5554 Cond = LowerSETCC(Cond, DAG);
5556 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5557 // setting operand in place of the X86ISD::SETCC.
5558 if (Cond.getOpcode() == X86ISD::SETCC) {
5559 CC = Cond.getOperand(0);
5561 SDValue Cmp = Cond.getOperand(1);
5562 unsigned Opc = Cmp.getOpcode();
5563 MVT VT = Op.getValueType();
5565 bool IllegalFPCMov = false;
5566 if (VT.isFloatingPoint() && !VT.isVector() &&
5567 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5568 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5570 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5571 Opc == X86ISD::BT) { // FIXME
5578 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5579 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5582 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5583 SmallVector<SDValue, 4> Ops;
5584 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5585 // condition is true.
5586 Ops.push_back(Op.getOperand(2));
5587 Ops.push_back(Op.getOperand(1));
5589 Ops.push_back(Cond);
5590 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
5593 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5594 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5595 // from the AND / OR.
5596 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5597 Opc = Op.getOpcode();
5598 if (Opc != ISD::OR && Opc != ISD::AND)
5600 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5601 Op.getOperand(0).hasOneUse() &&
5602 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5603 Op.getOperand(1).hasOneUse());
5606 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5607 // 1 and that the SETCC node has a single use.
5608 static bool isXor1OfSetCC(SDValue Op) {
5609 if (Op.getOpcode() != ISD::XOR)
5611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5612 if (N1C && N1C->getAPIntValue() == 1) {
5613 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5614 Op.getOperand(0).hasOneUse();
5619 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5620 bool addTest = true;
5621 SDValue Chain = Op.getOperand(0);
5622 SDValue Cond = Op.getOperand(1);
5623 SDValue Dest = Op.getOperand(2);
5624 DebugLoc dl = Op.getDebugLoc();
5627 if (Cond.getOpcode() == ISD::SETCC)
5628 Cond = LowerSETCC(Cond, DAG);
5630 // FIXME: LowerXALUO doesn't handle these!!
5631 else if (Cond.getOpcode() == X86ISD::ADD ||
5632 Cond.getOpcode() == X86ISD::SUB ||
5633 Cond.getOpcode() == X86ISD::SMUL ||
5634 Cond.getOpcode() == X86ISD::UMUL)
5635 Cond = LowerXALUO(Cond, DAG);
5638 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5639 // setting operand in place of the X86ISD::SETCC.
5640 if (Cond.getOpcode() == X86ISD::SETCC) {
5641 CC = Cond.getOperand(0);
5643 SDValue Cmp = Cond.getOperand(1);
5644 unsigned Opc = Cmp.getOpcode();
5645 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5646 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
5650 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5654 // These can only come from an arithmetic instruction with overflow,
5655 // e.g. SADDO, UADDO.
5656 Cond = Cond.getNode()->getOperand(1);
5663 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5664 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5665 if (CondOpc == ISD::OR) {
5666 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5667 // two branches instead of an explicit OR instruction with a
5669 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5670 isX86LogicalCmp(Cmp)) {
5671 CC = Cond.getOperand(0).getOperand(0);
5672 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5673 Chain, Dest, CC, Cmp);
5674 CC = Cond.getOperand(1).getOperand(0);
5678 } else { // ISD::AND
5679 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5680 // two branches instead of an explicit AND instruction with a
5681 // separate test. However, we only do this if this block doesn't
5682 // have a fall-through edge, because this requires an explicit
5683 // jmp when the condition is false.
5684 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5685 isX86LogicalCmp(Cmp) &&
5686 Op.getNode()->hasOneUse()) {
5687 X86::CondCode CCode =
5688 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5689 CCode = X86::GetOppositeBranchCondition(CCode);
5690 CC = DAG.getConstant(CCode, MVT::i8);
5691 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5692 // Look for an unconditional branch following this conditional branch.
5693 // We need this because we need to reverse the successors in order
5694 // to implement FCMP_OEQ.
5695 if (User.getOpcode() == ISD::BR) {
5696 SDValue FalseBB = User.getOperand(1);
5698 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5699 assert(NewBR == User);
5702 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5703 Chain, Dest, CC, Cmp);
5704 X86::CondCode CCode =
5705 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5706 CCode = X86::GetOppositeBranchCondition(CCode);
5707 CC = DAG.getConstant(CCode, MVT::i8);
5713 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5714 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5715 // It should be transformed during dag combiner except when the condition
5716 // is set by a arithmetics with overflow node.
5717 X86::CondCode CCode =
5718 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5719 CCode = X86::GetOppositeBranchCondition(CCode);
5720 CC = DAG.getConstant(CCode, MVT::i8);
5721 Cond = Cond.getOperand(0).getOperand(1);
5727 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5728 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5730 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5731 Chain, Dest, CC, Cond);
5735 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5736 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5737 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5738 // that the guard pages used by the OS virtual memory manager are allocated in
5739 // correct sequence.
5741 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5742 SelectionDAG &DAG) {
5743 assert(Subtarget->isTargetCygMing() &&
5744 "This should be used only on Cygwin/Mingw targets");
5745 DebugLoc dl = Op.getDebugLoc();
5748 SDValue Chain = Op.getOperand(0);
5749 SDValue Size = Op.getOperand(1);
5750 // FIXME: Ensure alignment here
5754 MVT IntPtr = getPointerTy();
5755 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5757 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5759 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
5760 Flag = Chain.getValue(1);
5762 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5763 SDValue Ops[] = { Chain,
5764 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5765 DAG.getRegister(X86::EAX, IntPtr),
5766 DAG.getRegister(X86StackPtr, SPTy),
5768 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
5769 Flag = Chain.getValue(1);
5771 Chain = DAG.getCALLSEQ_END(Chain,
5772 DAG.getIntPtrConstant(0, true),
5773 DAG.getIntPtrConstant(0, true),
5776 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
5778 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5779 return DAG.getMergeValues(Ops1, 2, dl);
5783 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
5785 SDValue Dst, SDValue Src,
5786 SDValue Size, unsigned Align,
5788 uint64_t DstSVOff) {
5789 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5791 // If not DWORD aligned or size is more than the threshold, call the library.
5792 // The libc version is likely to be faster for these cases. It can use the
5793 // address value and run time information about the CPU.
5794 if ((Align & 3) != 0 ||
5796 ConstantSize->getZExtValue() >
5797 getSubtarget()->getMaxInlineSizeThreshold()) {
5798 SDValue InFlag(0, 0);
5800 // Check to see if there is a specialized entry-point for memory zeroing.
5801 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5803 if (const char *bzeroEntry = V &&
5804 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5805 MVT IntPtr = getPointerTy();
5806 const Type *IntPtrTy = TD->getIntPtrType();
5807 TargetLowering::ArgListTy Args;
5808 TargetLowering::ArgListEntry Entry;
5810 Entry.Ty = IntPtrTy;
5811 Args.push_back(Entry);
5813 Args.push_back(Entry);
5814 std::pair<SDValue,SDValue> CallResult =
5815 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
5816 CallingConv::C, false,
5817 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
5818 return CallResult.second;
5821 // Otherwise have the target-independent code call memset.
5825 uint64_t SizeVal = ConstantSize->getZExtValue();
5826 SDValue InFlag(0, 0);
5829 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5830 unsigned BytesLeft = 0;
5831 bool TwoRepStos = false;
5834 uint64_t Val = ValC->getZExtValue() & 255;
5836 // If the value is a constant, then we can potentially use larger sets.
5837 switch (Align & 3) {
5838 case 2: // WORD aligned
5841 Val = (Val << 8) | Val;
5843 case 0: // DWORD aligned
5846 Val = (Val << 8) | Val;
5847 Val = (Val << 16) | Val;
5848 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5851 Val = (Val << 32) | Val;
5854 default: // Byte aligned
5857 Count = DAG.getIntPtrConstant(SizeVal);
5861 if (AVT.bitsGT(MVT::i8)) {
5862 unsigned UBytes = AVT.getSizeInBits() / 8;
5863 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5864 BytesLeft = SizeVal % UBytes;
5867 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
5869 InFlag = Chain.getValue(1);
5872 Count = DAG.getIntPtrConstant(SizeVal);
5873 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
5874 InFlag = Chain.getValue(1);
5877 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5880 InFlag = Chain.getValue(1);
5881 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5884 InFlag = Chain.getValue(1);
5886 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5887 SmallVector<SDValue, 8> Ops;
5888 Ops.push_back(Chain);
5889 Ops.push_back(DAG.getValueType(AVT));
5890 Ops.push_back(InFlag);
5891 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5894 InFlag = Chain.getValue(1);
5896 MVT CVT = Count.getValueType();
5897 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
5898 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5899 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
5902 InFlag = Chain.getValue(1);
5903 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5905 Ops.push_back(Chain);
5906 Ops.push_back(DAG.getValueType(MVT::i8));
5907 Ops.push_back(InFlag);
5908 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5909 } else if (BytesLeft) {
5910 // Handle the last 1 - 7 bytes.
5911 unsigned Offset = SizeVal - BytesLeft;
5912 MVT AddrVT = Dst.getValueType();
5913 MVT SizeVT = Size.getValueType();
5915 Chain = DAG.getMemset(Chain, dl,
5916 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
5917 DAG.getConstant(Offset, AddrVT)),
5919 DAG.getConstant(BytesLeft, SizeVT),
5920 Align, DstSV, DstSVOff + Offset);
5923 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5928 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
5929 SDValue Chain, SDValue Dst, SDValue Src,
5930 SDValue Size, unsigned Align,
5932 const Value *DstSV, uint64_t DstSVOff,
5933 const Value *SrcSV, uint64_t SrcSVOff) {
5934 // This requires the copy size to be a constant, preferrably
5935 // within a subtarget-specific limit.
5936 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5939 uint64_t SizeVal = ConstantSize->getZExtValue();
5940 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5943 /// If not DWORD aligned, call the library.
5944 if ((Align & 3) != 0)
5949 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5952 unsigned UBytes = AVT.getSizeInBits() / 8;
5953 unsigned CountVal = SizeVal / UBytes;
5954 SDValue Count = DAG.getIntPtrConstant(CountVal);
5955 unsigned BytesLeft = SizeVal % UBytes;
5957 SDValue InFlag(0, 0);
5958 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5961 InFlag = Chain.getValue(1);
5962 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5965 InFlag = Chain.getValue(1);
5966 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
5969 InFlag = Chain.getValue(1);
5971 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5972 SmallVector<SDValue, 8> Ops;
5973 Ops.push_back(Chain);
5974 Ops.push_back(DAG.getValueType(AVT));
5975 Ops.push_back(InFlag);
5976 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
5978 SmallVector<SDValue, 4> Results;
5979 Results.push_back(RepMovs);
5981 // Handle the last 1 - 7 bytes.
5982 unsigned Offset = SizeVal - BytesLeft;
5983 MVT DstVT = Dst.getValueType();
5984 MVT SrcVT = Src.getValueType();
5985 MVT SizeVT = Size.getValueType();
5986 Results.push_back(DAG.getMemcpy(Chain, dl,
5987 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
5988 DAG.getConstant(Offset, DstVT)),
5989 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
5990 DAG.getConstant(Offset, SrcVT)),
5991 DAG.getConstant(BytesLeft, SizeVT),
5992 Align, AlwaysInline,
5993 DstSV, DstSVOff + Offset,
5994 SrcSV, SrcSVOff + Offset));
5997 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5998 &Results[0], Results.size());
6001 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6002 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6003 DebugLoc dl = Op.getDebugLoc();
6005 if (!Subtarget->is64Bit()) {
6006 // vastart just stores the address of the VarArgsFrameIndex slot into the
6007 // memory location argument.
6008 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6009 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6013 // gp_offset (0 - 6 * 8)
6014 // fp_offset (48 - 48 + 8 * 16)
6015 // overflow_arg_area (point to parameters coming in memory).
6017 SmallVector<SDValue, 8> MemOps;
6018 SDValue FIN = Op.getOperand(1);
6020 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6021 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6023 MemOps.push_back(Store);
6026 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6027 FIN, DAG.getIntPtrConstant(4));
6028 Store = DAG.getStore(Op.getOperand(0), dl,
6029 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6031 MemOps.push_back(Store);
6033 // Store ptr to overflow_arg_area
6034 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6035 FIN, DAG.getIntPtrConstant(4));
6036 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6037 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6038 MemOps.push_back(Store);
6040 // Store ptr to reg_save_area.
6041 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6042 FIN, DAG.getIntPtrConstant(8));
6043 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6044 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6045 MemOps.push_back(Store);
6046 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6047 &MemOps[0], MemOps.size());
6050 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6051 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6052 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6053 SDValue Chain = Op.getOperand(0);
6054 SDValue SrcPtr = Op.getOperand(1);
6055 SDValue SrcSV = Op.getOperand(2);
6057 assert(0 && "VAArgInst is not yet implemented for x86-64!");
6062 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6063 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6064 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6065 SDValue Chain = Op.getOperand(0);
6066 SDValue DstPtr = Op.getOperand(1);
6067 SDValue SrcPtr = Op.getOperand(2);
6068 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6069 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6070 DebugLoc dl = Op.getDebugLoc();
6072 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6073 DAG.getIntPtrConstant(24), 8, false,
6074 DstSV, 0, SrcSV, 0);
6078 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6079 DebugLoc dl = Op.getDebugLoc();
6080 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6082 default: return SDValue(); // Don't custom lower most intrinsics.
6083 // Comparison intrinsics.
6084 case Intrinsic::x86_sse_comieq_ss:
6085 case Intrinsic::x86_sse_comilt_ss:
6086 case Intrinsic::x86_sse_comile_ss:
6087 case Intrinsic::x86_sse_comigt_ss:
6088 case Intrinsic::x86_sse_comige_ss:
6089 case Intrinsic::x86_sse_comineq_ss:
6090 case Intrinsic::x86_sse_ucomieq_ss:
6091 case Intrinsic::x86_sse_ucomilt_ss:
6092 case Intrinsic::x86_sse_ucomile_ss:
6093 case Intrinsic::x86_sse_ucomigt_ss:
6094 case Intrinsic::x86_sse_ucomige_ss:
6095 case Intrinsic::x86_sse_ucomineq_ss:
6096 case Intrinsic::x86_sse2_comieq_sd:
6097 case Intrinsic::x86_sse2_comilt_sd:
6098 case Intrinsic::x86_sse2_comile_sd:
6099 case Intrinsic::x86_sse2_comigt_sd:
6100 case Intrinsic::x86_sse2_comige_sd:
6101 case Intrinsic::x86_sse2_comineq_sd:
6102 case Intrinsic::x86_sse2_ucomieq_sd:
6103 case Intrinsic::x86_sse2_ucomilt_sd:
6104 case Intrinsic::x86_sse2_ucomile_sd:
6105 case Intrinsic::x86_sse2_ucomigt_sd:
6106 case Intrinsic::x86_sse2_ucomige_sd:
6107 case Intrinsic::x86_sse2_ucomineq_sd: {
6109 ISD::CondCode CC = ISD::SETCC_INVALID;
6112 case Intrinsic::x86_sse_comieq_ss:
6113 case Intrinsic::x86_sse2_comieq_sd:
6117 case Intrinsic::x86_sse_comilt_ss:
6118 case Intrinsic::x86_sse2_comilt_sd:
6122 case Intrinsic::x86_sse_comile_ss:
6123 case Intrinsic::x86_sse2_comile_sd:
6127 case Intrinsic::x86_sse_comigt_ss:
6128 case Intrinsic::x86_sse2_comigt_sd:
6132 case Intrinsic::x86_sse_comige_ss:
6133 case Intrinsic::x86_sse2_comige_sd:
6137 case Intrinsic::x86_sse_comineq_ss:
6138 case Intrinsic::x86_sse2_comineq_sd:
6142 case Intrinsic::x86_sse_ucomieq_ss:
6143 case Intrinsic::x86_sse2_ucomieq_sd:
6144 Opc = X86ISD::UCOMI;
6147 case Intrinsic::x86_sse_ucomilt_ss:
6148 case Intrinsic::x86_sse2_ucomilt_sd:
6149 Opc = X86ISD::UCOMI;
6152 case Intrinsic::x86_sse_ucomile_ss:
6153 case Intrinsic::x86_sse2_ucomile_sd:
6154 Opc = X86ISD::UCOMI;
6157 case Intrinsic::x86_sse_ucomigt_ss:
6158 case Intrinsic::x86_sse2_ucomigt_sd:
6159 Opc = X86ISD::UCOMI;
6162 case Intrinsic::x86_sse_ucomige_ss:
6163 case Intrinsic::x86_sse2_ucomige_sd:
6164 Opc = X86ISD::UCOMI;
6167 case Intrinsic::x86_sse_ucomineq_ss:
6168 case Intrinsic::x86_sse2_ucomineq_sd:
6169 Opc = X86ISD::UCOMI;
6174 SDValue LHS = Op.getOperand(1);
6175 SDValue RHS = Op.getOperand(2);
6176 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6177 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6178 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6179 DAG.getConstant(X86CC, MVT::i8), Cond);
6180 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6183 // Fix vector shift instructions where the last operand is a non-immediate
6185 case Intrinsic::x86_sse2_pslli_w:
6186 case Intrinsic::x86_sse2_pslli_d:
6187 case Intrinsic::x86_sse2_pslli_q:
6188 case Intrinsic::x86_sse2_psrli_w:
6189 case Intrinsic::x86_sse2_psrli_d:
6190 case Intrinsic::x86_sse2_psrli_q:
6191 case Intrinsic::x86_sse2_psrai_w:
6192 case Intrinsic::x86_sse2_psrai_d:
6193 case Intrinsic::x86_mmx_pslli_w:
6194 case Intrinsic::x86_mmx_pslli_d:
6195 case Intrinsic::x86_mmx_pslli_q:
6196 case Intrinsic::x86_mmx_psrli_w:
6197 case Intrinsic::x86_mmx_psrli_d:
6198 case Intrinsic::x86_mmx_psrli_q:
6199 case Intrinsic::x86_mmx_psrai_w:
6200 case Intrinsic::x86_mmx_psrai_d: {
6201 SDValue ShAmt = Op.getOperand(2);
6202 if (isa<ConstantSDNode>(ShAmt))
6205 unsigned NewIntNo = 0;
6206 MVT ShAmtVT = MVT::v4i32;
6208 case Intrinsic::x86_sse2_pslli_w:
6209 NewIntNo = Intrinsic::x86_sse2_psll_w;
6211 case Intrinsic::x86_sse2_pslli_d:
6212 NewIntNo = Intrinsic::x86_sse2_psll_d;
6214 case Intrinsic::x86_sse2_pslli_q:
6215 NewIntNo = Intrinsic::x86_sse2_psll_q;
6217 case Intrinsic::x86_sse2_psrli_w:
6218 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6220 case Intrinsic::x86_sse2_psrli_d:
6221 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6223 case Intrinsic::x86_sse2_psrli_q:
6224 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6226 case Intrinsic::x86_sse2_psrai_w:
6227 NewIntNo = Intrinsic::x86_sse2_psra_w;
6229 case Intrinsic::x86_sse2_psrai_d:
6230 NewIntNo = Intrinsic::x86_sse2_psra_d;
6233 ShAmtVT = MVT::v2i32;
6235 case Intrinsic::x86_mmx_pslli_w:
6236 NewIntNo = Intrinsic::x86_mmx_psll_w;
6238 case Intrinsic::x86_mmx_pslli_d:
6239 NewIntNo = Intrinsic::x86_mmx_psll_d;
6241 case Intrinsic::x86_mmx_pslli_q:
6242 NewIntNo = Intrinsic::x86_mmx_psll_q;
6244 case Intrinsic::x86_mmx_psrli_w:
6245 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6247 case Intrinsic::x86_mmx_psrli_d:
6248 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6250 case Intrinsic::x86_mmx_psrli_q:
6251 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6253 case Intrinsic::x86_mmx_psrai_w:
6254 NewIntNo = Intrinsic::x86_mmx_psra_w;
6256 case Intrinsic::x86_mmx_psrai_d:
6257 NewIntNo = Intrinsic::x86_mmx_psra_d;
6259 default: abort(); // Can't reach here.
6264 MVT VT = Op.getValueType();
6265 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6266 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
6267 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6268 DAG.getConstant(NewIntNo, MVT::i32),
6269 Op.getOperand(1), ShAmt);
6274 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6275 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6276 DebugLoc dl = Op.getDebugLoc();
6279 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6281 DAG.getConstant(TD->getPointerSize(),
6282 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6283 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6284 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6289 // Just load the return address.
6290 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6291 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6292 RetAddrFI, NULL, 0);
6295 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6296 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6297 MFI->setFrameAddressIsTaken(true);
6298 MVT VT = Op.getValueType();
6299 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6300 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6301 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6302 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6304 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6308 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6309 SelectionDAG &DAG) {
6310 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6313 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6315 MachineFunction &MF = DAG.getMachineFunction();
6316 SDValue Chain = Op.getOperand(0);
6317 SDValue Offset = Op.getOperand(1);
6318 SDValue Handler = Op.getOperand(2);
6319 DebugLoc dl = Op.getDebugLoc();
6321 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6323 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6325 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6326 DAG.getIntPtrConstant(-TD->getPointerSize()));
6327 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6328 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6329 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6330 MF.getRegInfo().addLiveOut(StoreAddrReg);
6332 return DAG.getNode(X86ISD::EH_RETURN, dl,
6334 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6337 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6338 SelectionDAG &DAG) {
6339 SDValue Root = Op.getOperand(0);
6340 SDValue Trmp = Op.getOperand(1); // trampoline
6341 SDValue FPtr = Op.getOperand(2); // nested function
6342 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6343 DebugLoc dl = Op.getDebugLoc();
6345 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6347 const X86InstrInfo *TII =
6348 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6350 if (Subtarget->is64Bit()) {
6351 SDValue OutChains[6];
6353 // Large code-model.
6355 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6356 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6358 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6359 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6361 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6363 // Load the pointer to the nested function into R11.
6364 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6365 SDValue Addr = Trmp;
6366 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6369 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6370 DAG.getConstant(2, MVT::i64));
6371 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6373 // Load the 'nest' parameter value into R10.
6374 // R10 is specified in X86CallingConv.td
6375 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6376 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6377 DAG.getConstant(10, MVT::i64));
6378 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6379 Addr, TrmpAddr, 10);
6381 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6382 DAG.getConstant(12, MVT::i64));
6383 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6385 // Jump to the nested function.
6386 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6387 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6388 DAG.getConstant(20, MVT::i64));
6389 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6390 Addr, TrmpAddr, 20);
6392 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6393 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6394 DAG.getConstant(22, MVT::i64));
6395 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6399 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6400 return DAG.getMergeValues(Ops, 2, dl);
6402 const Function *Func =
6403 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6404 unsigned CC = Func->getCallingConv();
6409 assert(0 && "Unsupported calling convention");
6410 case CallingConv::C:
6411 case CallingConv::X86_StdCall: {
6412 // Pass 'nest' parameter in ECX.
6413 // Must be kept in sync with X86CallingConv.td
6416 // Check that ECX wasn't needed by an 'inreg' parameter.
6417 const FunctionType *FTy = Func->getFunctionType();
6418 const AttrListPtr &Attrs = Func->getAttributes();
6420 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6421 unsigned InRegCount = 0;
6424 for (FunctionType::param_iterator I = FTy->param_begin(),
6425 E = FTy->param_end(); I != E; ++I, ++Idx)
6426 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6427 // FIXME: should only count parameters that are lowered to integers.
6428 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6430 if (InRegCount > 2) {
6431 cerr << "Nest register in use - reduce number of inreg parameters!\n";
6437 case CallingConv::X86_FastCall:
6438 case CallingConv::Fast:
6439 // Pass 'nest' parameter in EAX.
6440 // Must be kept in sync with X86CallingConv.td
6445 SDValue OutChains[4];
6448 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6449 DAG.getConstant(10, MVT::i32));
6450 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6452 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6453 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6454 OutChains[0] = DAG.getStore(Root, dl,
6455 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6458 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6459 DAG.getConstant(1, MVT::i32));
6460 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6462 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6463 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6464 DAG.getConstant(5, MVT::i32));
6465 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6466 TrmpAddr, 5, false, 1);
6468 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6469 DAG.getConstant(6, MVT::i32));
6470 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6473 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6474 return DAG.getMergeValues(Ops, 2, dl);
6478 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6480 The rounding mode is in bits 11:10 of FPSR, and has the following
6487 FLT_ROUNDS, on the other hand, expects the following:
6494 To perform the conversion, we do:
6495 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6498 MachineFunction &MF = DAG.getMachineFunction();
6499 const TargetMachine &TM = MF.getTarget();
6500 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6501 unsigned StackAlignment = TFI.getStackAlignment();
6502 MVT VT = Op.getValueType();
6503 DebugLoc dl = Op.getDebugLoc();
6505 // Save FP Control Word to stack slot
6506 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6507 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6509 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6510 DAG.getEntryNode(), StackSlot);
6512 // Load FP Control Word from stack slot
6513 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6515 // Transform as necessary
6517 DAG.getNode(ISD::SRL, dl, MVT::i16,
6518 DAG.getNode(ISD::AND, dl, MVT::i16,
6519 CWD, DAG.getConstant(0x800, MVT::i16)),
6520 DAG.getConstant(11, MVT::i8));
6522 DAG.getNode(ISD::SRL, dl, MVT::i16,
6523 DAG.getNode(ISD::AND, dl, MVT::i16,
6524 CWD, DAG.getConstant(0x400, MVT::i16)),
6525 DAG.getConstant(9, MVT::i8));
6528 DAG.getNode(ISD::AND, dl, MVT::i16,
6529 DAG.getNode(ISD::ADD, dl, MVT::i16,
6530 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6531 DAG.getConstant(1, MVT::i16)),
6532 DAG.getConstant(3, MVT::i16));
6535 return DAG.getNode((VT.getSizeInBits() < 16 ?
6536 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6539 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6540 MVT VT = Op.getValueType();
6542 unsigned NumBits = VT.getSizeInBits();
6543 DebugLoc dl = Op.getDebugLoc();
6545 Op = Op.getOperand(0);
6546 if (VT == MVT::i8) {
6547 // Zero extend to i32 since there is not an i8 bsr.
6549 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6552 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6553 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6554 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6556 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6557 SmallVector<SDValue, 4> Ops;
6559 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6560 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6561 Ops.push_back(Op.getValue(1));
6562 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6564 // Finally xor with NumBits-1.
6565 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6568 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6572 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6573 MVT VT = Op.getValueType();
6575 unsigned NumBits = VT.getSizeInBits();
6576 DebugLoc dl = Op.getDebugLoc();
6578 Op = Op.getOperand(0);
6579 if (VT == MVT::i8) {
6581 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6584 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6585 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6586 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
6588 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6589 SmallVector<SDValue, 4> Ops;
6591 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6592 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6593 Ops.push_back(Op.getValue(1));
6594 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6597 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6601 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6602 MVT VT = Op.getValueType();
6603 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6604 DebugLoc dl = Op.getDebugLoc();
6606 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6607 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6608 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6609 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6610 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6612 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6613 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6614 // return AloBlo + AloBhi + AhiBlo;
6616 SDValue A = Op.getOperand(0);
6617 SDValue B = Op.getOperand(1);
6619 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6620 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6621 A, DAG.getConstant(32, MVT::i32));
6622 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6623 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6624 B, DAG.getConstant(32, MVT::i32));
6625 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6626 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6628 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6629 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6631 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6632 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6634 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6635 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6636 AloBhi, DAG.getConstant(32, MVT::i32));
6637 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6638 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6639 AhiBlo, DAG.getConstant(32, MVT::i32));
6640 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
6641 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
6646 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6647 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6648 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6649 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6650 // has only one use.
6651 SDNode *N = Op.getNode();
6652 SDValue LHS = N->getOperand(0);
6653 SDValue RHS = N->getOperand(1);
6654 unsigned BaseOp = 0;
6656 DebugLoc dl = Op.getDebugLoc();
6658 switch (Op.getOpcode()) {
6659 default: assert(0 && "Unknown ovf instruction!");
6661 // A subtract of one will be selected as a INC. Note that INC doesn't
6662 // set CF, so we can't do this for UADDO.
6663 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6664 if (C->getAPIntValue() == 1) {
6665 BaseOp = X86ISD::INC;
6669 BaseOp = X86ISD::ADD;
6673 BaseOp = X86ISD::ADD;
6677 // A subtract of one will be selected as a DEC. Note that DEC doesn't
6678 // set CF, so we can't do this for USUBO.
6679 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6680 if (C->getAPIntValue() == 1) {
6681 BaseOp = X86ISD::DEC;
6685 BaseOp = X86ISD::SUB;
6689 BaseOp = X86ISD::SUB;
6693 BaseOp = X86ISD::SMUL;
6697 BaseOp = X86ISD::UMUL;
6702 // Also sets EFLAGS.
6703 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6704 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
6707 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
6708 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6710 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6714 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6715 MVT T = Op.getValueType();
6716 DebugLoc dl = Op.getDebugLoc();
6719 switch(T.getSimpleVT()) {
6721 assert(false && "Invalid value type!");
6722 case MVT::i8: Reg = X86::AL; size = 1; break;
6723 case MVT::i16: Reg = X86::AX; size = 2; break;
6724 case MVT::i32: Reg = X86::EAX; size = 4; break;
6726 assert(Subtarget->is64Bit() && "Node not type legal!");
6727 Reg = X86::RAX; size = 8;
6730 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
6731 Op.getOperand(2), SDValue());
6732 SDValue Ops[] = { cpIn.getValue(0),
6735 DAG.getTargetConstant(size, MVT::i8),
6737 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6738 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
6740 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
6744 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6745 SelectionDAG &DAG) {
6746 assert(Subtarget->is64Bit() && "Result not type legalized?");
6747 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6748 SDValue TheChain = Op.getOperand(0);
6749 DebugLoc dl = Op.getDebugLoc();
6750 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6751 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
6752 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
6754 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
6755 DAG.getConstant(32, MVT::i8));
6757 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
6760 return DAG.getMergeValues(Ops, 2, dl);
6763 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6764 SDNode *Node = Op.getNode();
6765 DebugLoc dl = Node->getDebugLoc();
6766 MVT T = Node->getValueType(0);
6767 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
6768 DAG.getConstant(0, T), Node->getOperand(2));
6769 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
6770 cast<AtomicSDNode>(Node)->getMemoryVT(),
6771 Node->getOperand(0),
6772 Node->getOperand(1), negOp,
6773 cast<AtomicSDNode>(Node)->getSrcValue(),
6774 cast<AtomicSDNode>(Node)->getAlignment());
6777 /// LowerOperation - Provide custom lowering hooks for some operations.
6779 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6780 switch (Op.getOpcode()) {
6781 default: assert(0 && "Should not custom lower this!");
6782 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6783 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
6784 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6785 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6786 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6787 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6788 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6789 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6790 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6791 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6792 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6793 case ISD::SHL_PARTS:
6794 case ISD::SRA_PARTS:
6795 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6796 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6797 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6798 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6799 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
6800 case ISD::FABS: return LowerFABS(Op, DAG);
6801 case ISD::FNEG: return LowerFNEG(Op, DAG);
6802 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6803 case ISD::SETCC: return LowerSETCC(Op, DAG);
6804 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6805 case ISD::SELECT: return LowerSELECT(Op, DAG);
6806 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6807 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6808 case ISD::CALL: return LowerCALL(Op, DAG);
6809 case ISD::RET: return LowerRET(Op, DAG);
6810 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
6811 case ISD::VASTART: return LowerVASTART(Op, DAG);
6812 case ISD::VAARG: return LowerVAARG(Op, DAG);
6813 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6814 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6815 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6816 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6817 case ISD::FRAME_TO_ARGS_OFFSET:
6818 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6819 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6820 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6821 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6822 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6823 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6824 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6825 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
6831 case ISD::UMULO: return LowerXALUO(Op, DAG);
6832 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6836 void X86TargetLowering::
6837 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6838 SelectionDAG &DAG, unsigned NewOp) {
6839 MVT T = Node->getValueType(0);
6840 DebugLoc dl = Node->getDebugLoc();
6841 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6843 SDValue Chain = Node->getOperand(0);
6844 SDValue In1 = Node->getOperand(1);
6845 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6846 Node->getOperand(2), DAG.getIntPtrConstant(0));
6847 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6848 Node->getOperand(2), DAG.getIntPtrConstant(1));
6849 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6850 // have a MemOperand. Pass the info through as a normal operand.
6851 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6852 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6853 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6854 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
6855 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6856 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6857 Results.push_back(Result.getValue(2));
6860 /// ReplaceNodeResults - Replace a node with an illegal result type
6861 /// with a new node built out of custom code.
6862 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
6863 SmallVectorImpl<SDValue>&Results,
6864 SelectionDAG &DAG) {
6865 DebugLoc dl = N->getDebugLoc();
6866 switch (N->getOpcode()) {
6868 assert(false && "Do not know how to custom type legalize this operation!");
6870 case ISD::FP_TO_SINT: {
6871 std::pair<SDValue,SDValue> Vals =
6872 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
6873 SDValue FIST = Vals.first, StackSlot = Vals.second;
6874 if (FIST.getNode() != 0) {
6875 MVT VT = N->getValueType(0);
6876 // Return a load from the stack slot.
6877 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
6881 case ISD::READCYCLECOUNTER: {
6882 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6883 SDValue TheChain = N->getOperand(0);
6884 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6885 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
6887 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
6889 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
6890 SDValue Ops[] = { eax, edx };
6891 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
6892 Results.push_back(edx.getValue(1));
6895 case ISD::ATOMIC_CMP_SWAP: {
6896 MVT T = N->getValueType(0);
6897 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6898 SDValue cpInL, cpInH;
6899 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6900 DAG.getConstant(0, MVT::i32));
6901 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6902 DAG.getConstant(1, MVT::i32));
6903 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
6904 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
6906 SDValue swapInL, swapInH;
6907 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
6908 DAG.getConstant(0, MVT::i32));
6909 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
6910 DAG.getConstant(1, MVT::i32));
6911 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
6913 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
6914 swapInL.getValue(1));
6915 SDValue Ops[] = { swapInH.getValue(0),
6917 swapInH.getValue(1) };
6918 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6919 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
6920 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
6921 MVT::i32, Result.getValue(1));
6922 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
6923 MVT::i32, cpOutL.getValue(2));
6924 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
6925 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6926 Results.push_back(cpOutH.getValue(1));
6929 case ISD::ATOMIC_LOAD_ADD:
6930 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
6932 case ISD::ATOMIC_LOAD_AND:
6933 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
6935 case ISD::ATOMIC_LOAD_NAND:
6936 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
6938 case ISD::ATOMIC_LOAD_OR:
6939 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
6941 case ISD::ATOMIC_LOAD_SUB:
6942 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
6944 case ISD::ATOMIC_LOAD_XOR:
6945 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
6947 case ISD::ATOMIC_SWAP:
6948 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
6953 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
6955 default: return NULL;
6956 case X86ISD::BSF: return "X86ISD::BSF";
6957 case X86ISD::BSR: return "X86ISD::BSR";
6958 case X86ISD::SHLD: return "X86ISD::SHLD";
6959 case X86ISD::SHRD: return "X86ISD::SHRD";
6960 case X86ISD::FAND: return "X86ISD::FAND";
6961 case X86ISD::FOR: return "X86ISD::FOR";
6962 case X86ISD::FXOR: return "X86ISD::FXOR";
6963 case X86ISD::FSRL: return "X86ISD::FSRL";
6964 case X86ISD::FILD: return "X86ISD::FILD";
6965 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
6966 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
6967 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
6968 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
6969 case X86ISD::FLD: return "X86ISD::FLD";
6970 case X86ISD::FST: return "X86ISD::FST";
6971 case X86ISD::CALL: return "X86ISD::CALL";
6972 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
6973 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
6974 case X86ISD::BT: return "X86ISD::BT";
6975 case X86ISD::CMP: return "X86ISD::CMP";
6976 case X86ISD::COMI: return "X86ISD::COMI";
6977 case X86ISD::UCOMI: return "X86ISD::UCOMI";
6978 case X86ISD::SETCC: return "X86ISD::SETCC";
6979 case X86ISD::CMOV: return "X86ISD::CMOV";
6980 case X86ISD::BRCOND: return "X86ISD::BRCOND";
6981 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
6982 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
6983 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
6984 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
6985 case X86ISD::Wrapper: return "X86ISD::Wrapper";
6986 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
6987 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
6988 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
6989 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6990 case X86ISD::PINSRB: return "X86ISD::PINSRB";
6991 case X86ISD::PINSRW: return "X86ISD::PINSRW";
6992 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
6993 case X86ISD::FMAX: return "X86ISD::FMAX";
6994 case X86ISD::FMIN: return "X86ISD::FMIN";
6995 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
6996 case X86ISD::FRCP: return "X86ISD::FRCP";
6997 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
6998 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
6999 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7000 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7001 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7002 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7003 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7004 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7005 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7006 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7007 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7008 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7009 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7010 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7011 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7012 case X86ISD::VSHL: return "X86ISD::VSHL";
7013 case X86ISD::VSRL: return "X86ISD::VSRL";
7014 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7015 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7016 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7017 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7018 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7019 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7020 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7021 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7022 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7023 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7024 case X86ISD::ADD: return "X86ISD::ADD";
7025 case X86ISD::SUB: return "X86ISD::SUB";
7026 case X86ISD::SMUL: return "X86ISD::SMUL";
7027 case X86ISD::UMUL: return "X86ISD::UMUL";
7028 case X86ISD::INC: return "X86ISD::INC";
7029 case X86ISD::DEC: return "X86ISD::DEC";
7030 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7034 // isLegalAddressingMode - Return true if the addressing mode represented
7035 // by AM is legal for this target, for a load/store of the specified type.
7036 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7037 const Type *Ty) const {
7038 // X86 supports extremely general addressing modes.
7040 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7041 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
7045 // We can only fold this if we don't need an extra load.
7046 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
7048 // If BaseGV requires a register, we cannot also have a BaseReg.
7049 if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) &&
7053 // X86-64 only supports addr of globals in small code model.
7054 if (Subtarget->is64Bit()) {
7055 if (getTargetMachine().getCodeModel() != CodeModel::Small)
7057 // If lower 4G is not available, then we must use rip-relative addressing.
7058 if (AM.BaseOffs || AM.Scale > 1)
7069 // These scales always work.
7074 // These scales are formed with basereg+scalereg. Only accept if there is
7079 default: // Other stuff never works.
7087 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7088 if (!Ty1->isInteger() || !Ty2->isInteger())
7090 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7091 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7092 if (NumBits1 <= NumBits2)
7094 return Subtarget->is64Bit() || NumBits1 < 64;
7097 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
7098 if (!VT1.isInteger() || !VT2.isInteger())
7100 unsigned NumBits1 = VT1.getSizeInBits();
7101 unsigned NumBits2 = VT2.getSizeInBits();
7102 if (NumBits1 <= NumBits2)
7104 return Subtarget->is64Bit() || NumBits1 < 64;
7107 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7108 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7109 return Ty1 == Type::Int32Ty && Ty2 == Type::Int64Ty && Subtarget->is64Bit();
7112 bool X86TargetLowering::isZExtFree(MVT VT1, MVT VT2) const {
7113 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7114 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7117 bool X86TargetLowering::isNarrowingProfitable(MVT VT1, MVT VT2) const {
7118 // i16 instructions are longer (0x66 prefix) and potentially slower.
7119 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7122 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7123 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7124 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7125 /// are assumed to be legal.
7127 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7129 // Only do shuffles on 128-bit vector types for now.
7130 if (VT.getSizeInBits() == 64)
7133 // FIXME: pshufb, blends, palignr, shifts.
7134 return (VT.getVectorNumElements() == 2 ||
7135 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7136 isMOVLMask(M, VT) ||
7137 isSHUFPMask(M, VT) ||
7138 isPSHUFDMask(M, VT) ||
7139 isPSHUFHWMask(M, VT) ||
7140 isPSHUFLWMask(M, VT) ||
7141 isUNPCKLMask(M, VT) ||
7142 isUNPCKHMask(M, VT) ||
7143 isUNPCKL_v_undef_Mask(M, VT) ||
7144 isUNPCKH_v_undef_Mask(M, VT));
7148 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7150 unsigned NumElts = VT.getVectorNumElements();
7151 // FIXME: This collection of masks seems suspect.
7154 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7155 return (isMOVLMask(Mask, VT) ||
7156 isCommutedMOVLMask(Mask, VT, true) ||
7157 isSHUFPMask(Mask, VT) ||
7158 isCommutedSHUFPMask(Mask, VT));
7163 //===----------------------------------------------------------------------===//
7164 // X86 Scheduler Hooks
7165 //===----------------------------------------------------------------------===//
7167 // private utility function
7169 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7170 MachineBasicBlock *MBB,
7178 TargetRegisterClass *RC,
7179 bool invSrc) const {
7180 // For the atomic bitwise operator, we generate
7183 // ld t1 = [bitinstr.addr]
7184 // op t2 = t1, [bitinstr.val]
7186 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7188 // fallthrough -->nextMBB
7189 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7190 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7191 MachineFunction::iterator MBBIter = MBB;
7194 /// First build the CFG
7195 MachineFunction *F = MBB->getParent();
7196 MachineBasicBlock *thisMBB = MBB;
7197 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7198 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7199 F->insert(MBBIter, newMBB);
7200 F->insert(MBBIter, nextMBB);
7202 // Move all successors to thisMBB to nextMBB
7203 nextMBB->transferSuccessors(thisMBB);
7205 // Update thisMBB to fall through to newMBB
7206 thisMBB->addSuccessor(newMBB);
7208 // newMBB jumps to itself and fall through to nextMBB
7209 newMBB->addSuccessor(nextMBB);
7210 newMBB->addSuccessor(newMBB);
7212 // Insert instructions into newMBB based on incoming instruction
7213 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7214 "unexpected number of operands");
7215 DebugLoc dl = bInstr->getDebugLoc();
7216 MachineOperand& destOper = bInstr->getOperand(0);
7217 MachineOperand* argOpers[2 + X86AddrNumOperands];
7218 int numArgs = bInstr->getNumOperands() - 1;
7219 for (int i=0; i < numArgs; ++i)
7220 argOpers[i] = &bInstr->getOperand(i+1);
7222 // x86 address has 4 operands: base, index, scale, and displacement
7223 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7224 int valArgIndx = lastAddrIndx + 1;
7226 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7227 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7228 for (int i=0; i <= lastAddrIndx; ++i)
7229 (*MIB).addOperand(*argOpers[i]);
7231 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7233 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7238 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7239 assert((argOpers[valArgIndx]->isReg() ||
7240 argOpers[valArgIndx]->isImm()) &&
7242 if (argOpers[valArgIndx]->isReg())
7243 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7245 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7247 (*MIB).addOperand(*argOpers[valArgIndx]);
7249 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7252 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7253 for (int i=0; i <= lastAddrIndx; ++i)
7254 (*MIB).addOperand(*argOpers[i]);
7256 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7257 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7259 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7263 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7265 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7269 // private utility function: 64 bit atomics on 32 bit host.
7271 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7272 MachineBasicBlock *MBB,
7277 bool invSrc) const {
7278 // For the atomic bitwise operator, we generate
7279 // thisMBB (instructions are in pairs, except cmpxchg8b)
7280 // ld t1,t2 = [bitinstr.addr]
7282 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7283 // op t5, t6 <- out1, out2, [bitinstr.val]
7284 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7285 // mov ECX, EBX <- t5, t6
7286 // mov EAX, EDX <- t1, t2
7287 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7288 // mov t3, t4 <- EAX, EDX
7290 // result in out1, out2
7291 // fallthrough -->nextMBB
7293 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7294 const unsigned LoadOpc = X86::MOV32rm;
7295 const unsigned copyOpc = X86::MOV32rr;
7296 const unsigned NotOpc = X86::NOT32r;
7297 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7298 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7299 MachineFunction::iterator MBBIter = MBB;
7302 /// First build the CFG
7303 MachineFunction *F = MBB->getParent();
7304 MachineBasicBlock *thisMBB = MBB;
7305 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7306 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7307 F->insert(MBBIter, newMBB);
7308 F->insert(MBBIter, nextMBB);
7310 // Move all successors to thisMBB to nextMBB
7311 nextMBB->transferSuccessors(thisMBB);
7313 // Update thisMBB to fall through to newMBB
7314 thisMBB->addSuccessor(newMBB);
7316 // newMBB jumps to itself and fall through to nextMBB
7317 newMBB->addSuccessor(nextMBB);
7318 newMBB->addSuccessor(newMBB);
7320 DebugLoc dl = bInstr->getDebugLoc();
7321 // Insert instructions into newMBB based on incoming instruction
7322 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7323 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7324 "unexpected number of operands");
7325 MachineOperand& dest1Oper = bInstr->getOperand(0);
7326 MachineOperand& dest2Oper = bInstr->getOperand(1);
7327 MachineOperand* argOpers[2 + X86AddrNumOperands];
7328 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7329 argOpers[i] = &bInstr->getOperand(i+2);
7331 // x86 address has 4 operands: base, index, scale, and displacement
7332 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7334 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7335 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7336 for (int i=0; i <= lastAddrIndx; ++i)
7337 (*MIB).addOperand(*argOpers[i]);
7338 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7339 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7340 // add 4 to displacement.
7341 for (int i=0; i <= lastAddrIndx-2; ++i)
7342 (*MIB).addOperand(*argOpers[i]);
7343 MachineOperand newOp3 = *(argOpers[3]);
7345 newOp3.setImm(newOp3.getImm()+4);
7347 newOp3.setOffset(newOp3.getOffset()+4);
7348 (*MIB).addOperand(newOp3);
7349 (*MIB).addOperand(*argOpers[lastAddrIndx]);
7351 // t3/4 are defined later, at the bottom of the loop
7352 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7353 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7354 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7355 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7356 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7357 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7359 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7360 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7362 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7363 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7369 int valArgIndx = lastAddrIndx + 1;
7370 assert((argOpers[valArgIndx]->isReg() ||
7371 argOpers[valArgIndx]->isImm()) &&
7373 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7374 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7375 if (argOpers[valArgIndx]->isReg())
7376 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7378 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7379 if (regOpcL != X86::MOV32rr)
7381 (*MIB).addOperand(*argOpers[valArgIndx]);
7382 assert(argOpers[valArgIndx + 1]->isReg() ==
7383 argOpers[valArgIndx]->isReg());
7384 assert(argOpers[valArgIndx + 1]->isImm() ==
7385 argOpers[valArgIndx]->isImm());
7386 if (argOpers[valArgIndx + 1]->isReg())
7387 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7389 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7390 if (regOpcH != X86::MOV32rr)
7392 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7394 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7396 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7399 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7401 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7404 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7405 for (int i=0; i <= lastAddrIndx; ++i)
7406 (*MIB).addOperand(*argOpers[i]);
7408 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7409 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7411 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7412 MIB.addReg(X86::EAX);
7413 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7414 MIB.addReg(X86::EDX);
7417 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7419 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7423 // private utility function
7425 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7426 MachineBasicBlock *MBB,
7427 unsigned cmovOpc) const {
7428 // For the atomic min/max operator, we generate
7431 // ld t1 = [min/max.addr]
7432 // mov t2 = [min/max.val]
7434 // cmov[cond] t2 = t1
7436 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7438 // fallthrough -->nextMBB
7440 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7441 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7442 MachineFunction::iterator MBBIter = MBB;
7445 /// First build the CFG
7446 MachineFunction *F = MBB->getParent();
7447 MachineBasicBlock *thisMBB = MBB;
7448 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7449 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7450 F->insert(MBBIter, newMBB);
7451 F->insert(MBBIter, nextMBB);
7453 // Move all successors to thisMBB to nextMBB
7454 nextMBB->transferSuccessors(thisMBB);
7456 // Update thisMBB to fall through to newMBB
7457 thisMBB->addSuccessor(newMBB);
7459 // newMBB jumps to newMBB and fall through to nextMBB
7460 newMBB->addSuccessor(nextMBB);
7461 newMBB->addSuccessor(newMBB);
7463 DebugLoc dl = mInstr->getDebugLoc();
7464 // Insert instructions into newMBB based on incoming instruction
7465 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7466 "unexpected number of operands");
7467 MachineOperand& destOper = mInstr->getOperand(0);
7468 MachineOperand* argOpers[2 + X86AddrNumOperands];
7469 int numArgs = mInstr->getNumOperands() - 1;
7470 for (int i=0; i < numArgs; ++i)
7471 argOpers[i] = &mInstr->getOperand(i+1);
7473 // x86 address has 4 operands: base, index, scale, and displacement
7474 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7475 int valArgIndx = lastAddrIndx + 1;
7477 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7478 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7479 for (int i=0; i <= lastAddrIndx; ++i)
7480 (*MIB).addOperand(*argOpers[i]);
7482 // We only support register and immediate values
7483 assert((argOpers[valArgIndx]->isReg() ||
7484 argOpers[valArgIndx]->isImm()) &&
7487 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7488 if (argOpers[valArgIndx]->isReg())
7489 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7491 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7492 (*MIB).addOperand(*argOpers[valArgIndx]);
7494 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7497 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7502 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7503 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7507 // Cmp and exchange if none has modified the memory location
7508 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7509 for (int i=0; i <= lastAddrIndx; ++i)
7510 (*MIB).addOperand(*argOpers[i]);
7512 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7513 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
7515 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7516 MIB.addReg(X86::EAX);
7519 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7521 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7527 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7528 MachineBasicBlock *BB) const {
7529 DebugLoc dl = MI->getDebugLoc();
7530 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7531 switch (MI->getOpcode()) {
7532 default: assert(false && "Unexpected instr type to insert");
7533 case X86::CMOV_V1I64:
7534 case X86::CMOV_FR32:
7535 case X86::CMOV_FR64:
7536 case X86::CMOV_V4F32:
7537 case X86::CMOV_V2F64:
7538 case X86::CMOV_V2I64: {
7539 // To "insert" a SELECT_CC instruction, we actually have to insert the
7540 // diamond control-flow pattern. The incoming instruction knows the
7541 // destination vreg to set, the condition code register to branch on, the
7542 // true/false values to select between, and a branch opcode to use.
7543 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7544 MachineFunction::iterator It = BB;
7550 // cmpTY ccX, r1, r2
7552 // fallthrough --> copy0MBB
7553 MachineBasicBlock *thisMBB = BB;
7554 MachineFunction *F = BB->getParent();
7555 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7556 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7558 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7559 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
7560 F->insert(It, copy0MBB);
7561 F->insert(It, sinkMBB);
7562 // Update machine-CFG edges by transferring all successors of the current
7563 // block to the new block which will contain the Phi node for the select.
7564 sinkMBB->transferSuccessors(BB);
7566 // Add the true and fallthrough blocks as its successors.
7567 BB->addSuccessor(copy0MBB);
7568 BB->addSuccessor(sinkMBB);
7571 // %FalseValue = ...
7572 // # fallthrough to sinkMBB
7575 // Update machine-CFG edges
7576 BB->addSuccessor(sinkMBB);
7579 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7582 BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg())
7583 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7584 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7586 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7590 case X86::FP32_TO_INT16_IN_MEM:
7591 case X86::FP32_TO_INT32_IN_MEM:
7592 case X86::FP32_TO_INT64_IN_MEM:
7593 case X86::FP64_TO_INT16_IN_MEM:
7594 case X86::FP64_TO_INT32_IN_MEM:
7595 case X86::FP64_TO_INT64_IN_MEM:
7596 case X86::FP80_TO_INT16_IN_MEM:
7597 case X86::FP80_TO_INT32_IN_MEM:
7598 case X86::FP80_TO_INT64_IN_MEM: {
7599 // Change the floating point control register to use "round towards zero"
7600 // mode when truncating to an integer value.
7601 MachineFunction *F = BB->getParent();
7602 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7603 addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7605 // Load the old value of the high byte of the control word...
7607 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7608 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
7611 // Set the high part to be round to zero...
7612 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx)
7615 // Reload the modified control word now...
7616 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7618 // Restore the memory image of control word to original value
7619 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx)
7622 // Get the X86 opcode to use.
7624 switch (MI->getOpcode()) {
7625 default: assert(0 && "illegal opcode!");
7626 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7627 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7628 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7629 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7630 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7631 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7632 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7633 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7634 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7638 MachineOperand &Op = MI->getOperand(0);
7640 AM.BaseType = X86AddressMode::RegBase;
7641 AM.Base.Reg = Op.getReg();
7643 AM.BaseType = X86AddressMode::FrameIndexBase;
7644 AM.Base.FrameIndex = Op.getIndex();
7646 Op = MI->getOperand(1);
7648 AM.Scale = Op.getImm();
7649 Op = MI->getOperand(2);
7651 AM.IndexReg = Op.getImm();
7652 Op = MI->getOperand(3);
7653 if (Op.isGlobal()) {
7654 AM.GV = Op.getGlobal();
7656 AM.Disp = Op.getImm();
7658 addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
7659 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
7661 // Reload the original control word now.
7662 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7664 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7667 case X86::ATOMAND32:
7668 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7669 X86::AND32ri, X86::MOV32rm,
7670 X86::LCMPXCHG32, X86::MOV32rr,
7671 X86::NOT32r, X86::EAX,
7672 X86::GR32RegisterClass);
7674 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7675 X86::OR32ri, X86::MOV32rm,
7676 X86::LCMPXCHG32, X86::MOV32rr,
7677 X86::NOT32r, X86::EAX,
7678 X86::GR32RegisterClass);
7679 case X86::ATOMXOR32:
7680 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7681 X86::XOR32ri, X86::MOV32rm,
7682 X86::LCMPXCHG32, X86::MOV32rr,
7683 X86::NOT32r, X86::EAX,
7684 X86::GR32RegisterClass);
7685 case X86::ATOMNAND32:
7686 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7687 X86::AND32ri, X86::MOV32rm,
7688 X86::LCMPXCHG32, X86::MOV32rr,
7689 X86::NOT32r, X86::EAX,
7690 X86::GR32RegisterClass, true);
7691 case X86::ATOMMIN32:
7692 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7693 case X86::ATOMMAX32:
7694 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7695 case X86::ATOMUMIN32:
7696 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7697 case X86::ATOMUMAX32:
7698 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7700 case X86::ATOMAND16:
7701 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7702 X86::AND16ri, X86::MOV16rm,
7703 X86::LCMPXCHG16, X86::MOV16rr,
7704 X86::NOT16r, X86::AX,
7705 X86::GR16RegisterClass);
7707 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7708 X86::OR16ri, X86::MOV16rm,
7709 X86::LCMPXCHG16, X86::MOV16rr,
7710 X86::NOT16r, X86::AX,
7711 X86::GR16RegisterClass);
7712 case X86::ATOMXOR16:
7713 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7714 X86::XOR16ri, X86::MOV16rm,
7715 X86::LCMPXCHG16, X86::MOV16rr,
7716 X86::NOT16r, X86::AX,
7717 X86::GR16RegisterClass);
7718 case X86::ATOMNAND16:
7719 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7720 X86::AND16ri, X86::MOV16rm,
7721 X86::LCMPXCHG16, X86::MOV16rr,
7722 X86::NOT16r, X86::AX,
7723 X86::GR16RegisterClass, true);
7724 case X86::ATOMMIN16:
7725 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7726 case X86::ATOMMAX16:
7727 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7728 case X86::ATOMUMIN16:
7729 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7730 case X86::ATOMUMAX16:
7731 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7734 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7735 X86::AND8ri, X86::MOV8rm,
7736 X86::LCMPXCHG8, X86::MOV8rr,
7737 X86::NOT8r, X86::AL,
7738 X86::GR8RegisterClass);
7740 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7741 X86::OR8ri, X86::MOV8rm,
7742 X86::LCMPXCHG8, X86::MOV8rr,
7743 X86::NOT8r, X86::AL,
7744 X86::GR8RegisterClass);
7746 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7747 X86::XOR8ri, X86::MOV8rm,
7748 X86::LCMPXCHG8, X86::MOV8rr,
7749 X86::NOT8r, X86::AL,
7750 X86::GR8RegisterClass);
7751 case X86::ATOMNAND8:
7752 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7753 X86::AND8ri, X86::MOV8rm,
7754 X86::LCMPXCHG8, X86::MOV8rr,
7755 X86::NOT8r, X86::AL,
7756 X86::GR8RegisterClass, true);
7757 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7758 // This group is for 64-bit host.
7759 case X86::ATOMAND64:
7760 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7761 X86::AND64ri32, X86::MOV64rm,
7762 X86::LCMPXCHG64, X86::MOV64rr,
7763 X86::NOT64r, X86::RAX,
7764 X86::GR64RegisterClass);
7766 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7767 X86::OR64ri32, X86::MOV64rm,
7768 X86::LCMPXCHG64, X86::MOV64rr,
7769 X86::NOT64r, X86::RAX,
7770 X86::GR64RegisterClass);
7771 case X86::ATOMXOR64:
7772 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
7773 X86::XOR64ri32, X86::MOV64rm,
7774 X86::LCMPXCHG64, X86::MOV64rr,
7775 X86::NOT64r, X86::RAX,
7776 X86::GR64RegisterClass);
7777 case X86::ATOMNAND64:
7778 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7779 X86::AND64ri32, X86::MOV64rm,
7780 X86::LCMPXCHG64, X86::MOV64rr,
7781 X86::NOT64r, X86::RAX,
7782 X86::GR64RegisterClass, true);
7783 case X86::ATOMMIN64:
7784 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7785 case X86::ATOMMAX64:
7786 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7787 case X86::ATOMUMIN64:
7788 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7789 case X86::ATOMUMAX64:
7790 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
7792 // This group does 64-bit operations on a 32-bit host.
7793 case X86::ATOMAND6432:
7794 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7795 X86::AND32rr, X86::AND32rr,
7796 X86::AND32ri, X86::AND32ri,
7798 case X86::ATOMOR6432:
7799 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7800 X86::OR32rr, X86::OR32rr,
7801 X86::OR32ri, X86::OR32ri,
7803 case X86::ATOMXOR6432:
7804 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7805 X86::XOR32rr, X86::XOR32rr,
7806 X86::XOR32ri, X86::XOR32ri,
7808 case X86::ATOMNAND6432:
7809 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7810 X86::AND32rr, X86::AND32rr,
7811 X86::AND32ri, X86::AND32ri,
7813 case X86::ATOMADD6432:
7814 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7815 X86::ADD32rr, X86::ADC32rr,
7816 X86::ADD32ri, X86::ADC32ri,
7818 case X86::ATOMSUB6432:
7819 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7820 X86::SUB32rr, X86::SBB32rr,
7821 X86::SUB32ri, X86::SBB32ri,
7823 case X86::ATOMSWAP6432:
7824 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7825 X86::MOV32rr, X86::MOV32rr,
7826 X86::MOV32ri, X86::MOV32ri,
7831 //===----------------------------------------------------------------------===//
7832 // X86 Optimization Hooks
7833 //===----------------------------------------------------------------------===//
7835 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7839 const SelectionDAG &DAG,
7840 unsigned Depth) const {
7841 unsigned Opc = Op.getOpcode();
7842 assert((Opc >= ISD::BUILTIN_OP_END ||
7843 Opc == ISD::INTRINSIC_WO_CHAIN ||
7844 Opc == ISD::INTRINSIC_W_CHAIN ||
7845 Opc == ISD::INTRINSIC_VOID) &&
7846 "Should use MaskedValueIsZero if you don't know whether Op"
7847 " is a target node!");
7849 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7858 // These nodes' second result is a boolean.
7859 if (Op.getResNo() == 0)
7863 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7864 Mask.getBitWidth() - 1);
7869 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7870 /// node is a GlobalAddress + offset.
7871 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7872 GlobalValue* &GA, int64_t &Offset) const{
7873 if (N->getOpcode() == X86ISD::Wrapper) {
7874 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
7875 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
7876 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
7880 return TargetLowering::isGAPlusOffset(N, GA, Offset);
7883 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7884 const TargetLowering &TLI) {
7887 if (TLI.isGAPlusOffset(Base, GV, Offset))
7888 return (GV->getAlignment() >= N && (Offset % N) == 0);
7889 // DAG combine handles the stack object case.
7893 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
7894 MVT EVT, LoadSDNode *&LDBase,
7895 unsigned &LastLoadedElt,
7896 SelectionDAG &DAG, MachineFrameInfo *MFI,
7897 const TargetLowering &TLI) {
7899 LastLoadedElt = -1U;
7900 for (unsigned i = 0; i < NumElems; ++i) {
7901 if (N->getMaskElt(i) < 0) {
7907 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7908 if (!Elt.getNode() ||
7909 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7912 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
7914 LDBase = cast<LoadSDNode>(Elt.getNode());
7918 if (Elt.getOpcode() == ISD::UNDEF)
7921 LoadSDNode *LD = cast<LoadSDNode>(Elt);
7922 if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI))
7929 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7930 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7931 /// if the load addresses are consecutive, non-overlapping, and in the right
7932 /// order. In the case of v2i64, it will see if it can rewrite the
7933 /// shuffle to be an appropriate build vector so it can take advantage of
7934 // performBuildVectorCombine.
7935 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7936 const TargetLowering &TLI) {
7937 DebugLoc dl = N->getDebugLoc();
7938 MVT VT = N->getValueType(0);
7939 MVT EVT = VT.getVectorElementType();
7940 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7941 unsigned NumElems = VT.getVectorNumElements();
7943 if (VT.getSizeInBits() != 128)
7946 // Try to combine a vector_shuffle into a 128-bit load.
7947 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7948 LoadSDNode *LD = NULL;
7949 unsigned LastLoadedElt;
7950 if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG,
7954 if (LastLoadedElt == NumElems - 1) {
7955 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI))
7956 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
7957 LD->getSrcValue(), LD->getSrcValueOffset(),
7959 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
7960 LD->getSrcValue(), LD->getSrcValueOffset(),
7961 LD->isVolatile(), LD->getAlignment());
7962 } else if (NumElems == 4 && LastLoadedElt == 1) {
7963 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
7964 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
7965 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
7966 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
7971 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
7972 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
7973 const X86Subtarget *Subtarget) {
7974 DebugLoc DL = N->getDebugLoc();
7975 SDValue Cond = N->getOperand(0);
7976 // Get the LHS/RHS of the select.
7977 SDValue LHS = N->getOperand(1);
7978 SDValue RHS = N->getOperand(2);
7980 // If we have SSE[12] support, try to form min/max nodes.
7981 if (Subtarget->hasSSE2() &&
7982 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
7983 Cond.getOpcode() == ISD::SETCC) {
7984 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
7986 unsigned Opcode = 0;
7987 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
7990 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
7993 if (!UnsafeFPMath) break;
7995 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
7997 Opcode = X86ISD::FMIN;
8000 case ISD::SETOGT: // (X > Y) ? X : Y -> max
8003 if (!UnsafeFPMath) break;
8005 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
8007 Opcode = X86ISD::FMAX;
8010 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8013 case ISD::SETOGT: // (X > Y) ? Y : X -> min
8016 if (!UnsafeFPMath) break;
8018 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
8020 Opcode = X86ISD::FMIN;
8023 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
8026 if (!UnsafeFPMath) break;
8028 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
8030 Opcode = X86ISD::FMAX;
8036 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8039 // If this is a select between two integer constants, try to do some
8041 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8042 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8043 // Don't do this for crazy integer types.
8044 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8045 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8046 // so that TrueC (the true value) is larger than FalseC.
8047 bool NeedsCondInvert = false;
8049 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8050 // Efficiently invertible.
8051 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8052 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8053 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8054 NeedsCondInvert = true;
8055 std::swap(TrueC, FalseC);
8058 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8059 if (FalseC->getAPIntValue() == 0 &&
8060 TrueC->getAPIntValue().isPowerOf2()) {
8061 if (NeedsCondInvert) // Invert the condition if needed.
8062 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8063 DAG.getConstant(1, Cond.getValueType()));
8065 // Zero extend the condition if needed.
8066 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8068 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8069 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8070 DAG.getConstant(ShAmt, MVT::i8));
8073 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8074 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8075 if (NeedsCondInvert) // Invert the condition if needed.
8076 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8077 DAG.getConstant(1, Cond.getValueType()));
8079 // Zero extend the condition if needed.
8080 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8081 FalseC->getValueType(0), Cond);
8082 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8083 SDValue(FalseC, 0));
8086 // Optimize cases that will turn into an LEA instruction. This requires
8087 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8088 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8089 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8090 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8092 bool isFastMultiplier = false;
8094 switch ((unsigned char)Diff) {
8096 case 1: // result = add base, cond
8097 case 2: // result = lea base( , cond*2)
8098 case 3: // result = lea base(cond, cond*2)
8099 case 4: // result = lea base( , cond*4)
8100 case 5: // result = lea base(cond, cond*4)
8101 case 8: // result = lea base( , cond*8)
8102 case 9: // result = lea base(cond, cond*8)
8103 isFastMultiplier = true;
8108 if (isFastMultiplier) {
8109 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8110 if (NeedsCondInvert) // Invert the condition if needed.
8111 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8112 DAG.getConstant(1, Cond.getValueType()));
8114 // Zero extend the condition if needed.
8115 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8117 // Scale the condition by the difference.
8119 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8120 DAG.getConstant(Diff, Cond.getValueType()));
8122 // Add the base if non-zero.
8123 if (FalseC->getAPIntValue() != 0)
8124 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8125 SDValue(FalseC, 0));
8135 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8136 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8137 TargetLowering::DAGCombinerInfo &DCI) {
8138 DebugLoc DL = N->getDebugLoc();
8140 // If the flag operand isn't dead, don't touch this CMOV.
8141 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8144 // If this is a select between two integer constants, try to do some
8145 // optimizations. Note that the operands are ordered the opposite of SELECT
8147 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8148 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8149 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8150 // larger than FalseC (the false value).
8151 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8153 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8154 CC = X86::GetOppositeBranchCondition(CC);
8155 std::swap(TrueC, FalseC);
8158 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8159 // This is efficient for any integer data type (including i8/i16) and
8161 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8162 SDValue Cond = N->getOperand(3);
8163 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8164 DAG.getConstant(CC, MVT::i8), Cond);
8166 // Zero extend the condition if needed.
8167 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8169 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8170 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8171 DAG.getConstant(ShAmt, MVT::i8));
8172 if (N->getNumValues() == 2) // Dead flag value?
8173 return DCI.CombineTo(N, Cond, SDValue());
8177 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8178 // for any integer data type, including i8/i16.
8179 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8180 SDValue Cond = N->getOperand(3);
8181 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8182 DAG.getConstant(CC, MVT::i8), Cond);
8184 // Zero extend the condition if needed.
8185 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8186 FalseC->getValueType(0), Cond);
8187 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8188 SDValue(FalseC, 0));
8190 if (N->getNumValues() == 2) // Dead flag value?
8191 return DCI.CombineTo(N, Cond, SDValue());
8195 // Optimize cases that will turn into an LEA instruction. This requires
8196 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8197 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8198 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8199 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8201 bool isFastMultiplier = false;
8203 switch ((unsigned char)Diff) {
8205 case 1: // result = add base, cond
8206 case 2: // result = lea base( , cond*2)
8207 case 3: // result = lea base(cond, cond*2)
8208 case 4: // result = lea base( , cond*4)
8209 case 5: // result = lea base(cond, cond*4)
8210 case 8: // result = lea base( , cond*8)
8211 case 9: // result = lea base(cond, cond*8)
8212 isFastMultiplier = true;
8217 if (isFastMultiplier) {
8218 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8219 SDValue Cond = N->getOperand(3);
8220 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8221 DAG.getConstant(CC, MVT::i8), Cond);
8222 // Zero extend the condition if needed.
8223 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8225 // Scale the condition by the difference.
8227 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8228 DAG.getConstant(Diff, Cond.getValueType()));
8230 // Add the base if non-zero.
8231 if (FalseC->getAPIntValue() != 0)
8232 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8233 SDValue(FalseC, 0));
8234 if (N->getNumValues() == 2) // Dead flag value?
8235 return DCI.CombineTo(N, Cond, SDValue());
8245 /// PerformMulCombine - Optimize a single multiply with constant into two
8246 /// in order to implement it with two cheaper instructions, e.g.
8247 /// LEA + SHL, LEA + LEA.
8248 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8249 TargetLowering::DAGCombinerInfo &DCI) {
8250 if (DAG.getMachineFunction().
8251 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8254 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8257 MVT VT = N->getValueType(0);
8261 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8264 uint64_t MulAmt = C->getZExtValue();
8265 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8268 uint64_t MulAmt1 = 0;
8269 uint64_t MulAmt2 = 0;
8270 if ((MulAmt % 9) == 0) {
8272 MulAmt2 = MulAmt / 9;
8273 } else if ((MulAmt % 5) == 0) {
8275 MulAmt2 = MulAmt / 5;
8276 } else if ((MulAmt % 3) == 0) {
8278 MulAmt2 = MulAmt / 3;
8281 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8282 DebugLoc DL = N->getDebugLoc();
8284 if (isPowerOf2_64(MulAmt2) &&
8285 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8286 // If second multiplifer is pow2, issue it first. We want the multiply by
8287 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8289 std::swap(MulAmt1, MulAmt2);
8292 if (isPowerOf2_64(MulAmt1))
8293 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8294 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8296 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8297 DAG.getConstant(MulAmt1, VT));
8299 if (isPowerOf2_64(MulAmt2))
8300 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8301 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8303 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
8304 DAG.getConstant(MulAmt2, VT));
8306 // Do not add new nodes to DAG combiner worklist.
8307 DCI.CombineTo(N, NewMul, false);
8313 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
8315 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
8316 const X86Subtarget *Subtarget) {
8317 // On X86 with SSE2 support, we can transform this to a vector shift if
8318 // all elements are shifted by the same amount. We can't do this in legalize
8319 // because the a constant vector is typically transformed to a constant pool
8320 // so we have no knowledge of the shift amount.
8321 if (!Subtarget->hasSSE2())
8324 MVT VT = N->getValueType(0);
8325 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
8328 SDValue ShAmtOp = N->getOperand(1);
8329 MVT EltVT = VT.getVectorElementType();
8330 DebugLoc DL = N->getDebugLoc();
8332 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
8333 unsigned NumElts = VT.getVectorNumElements();
8335 for (; i != NumElts; ++i) {
8336 SDValue Arg = ShAmtOp.getOperand(i);
8337 if (Arg.getOpcode() == ISD::UNDEF) continue;
8341 for (; i != NumElts; ++i) {
8342 SDValue Arg = ShAmtOp.getOperand(i);
8343 if (Arg.getOpcode() == ISD::UNDEF) continue;
8344 if (Arg != BaseShAmt) {
8348 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
8349 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
8350 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
8351 DAG.getIntPtrConstant(0));
8355 if (EltVT.bitsGT(MVT::i32))
8356 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
8357 else if (EltVT.bitsLT(MVT::i32))
8358 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt);
8360 // The shift amount is identical so we can do a vector shift.
8361 SDValue ValOp = N->getOperand(0);
8362 switch (N->getOpcode()) {
8364 assert(0 && "Unknown shift opcode!");
8367 if (VT == MVT::v2i64)
8368 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8369 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8371 if (VT == MVT::v4i32)
8372 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8373 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8375 if (VT == MVT::v8i16)
8376 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8377 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8381 if (VT == MVT::v4i32)
8382 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8383 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
8385 if (VT == MVT::v8i16)
8386 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8387 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
8391 if (VT == MVT::v2i64)
8392 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8393 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8395 if (VT == MVT::v4i32)
8396 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8397 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
8399 if (VT == MVT::v8i16)
8400 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8401 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
8408 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
8409 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
8410 const X86Subtarget *Subtarget) {
8411 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
8412 // the FP state in cases where an emms may be missing.
8413 // A preferable solution to the general problem is to figure out the right
8414 // places to insert EMMS. This qualifies as a quick hack.
8416 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
8417 StoreSDNode *St = cast<StoreSDNode>(N);
8418 MVT VT = St->getValue().getValueType();
8419 if (VT.getSizeInBits() != 64)
8422 const Function *F = DAG.getMachineFunction().getFunction();
8423 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
8424 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
8425 && Subtarget->hasSSE2();
8426 if ((VT.isVector() ||
8427 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
8428 isa<LoadSDNode>(St->getValue()) &&
8429 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
8430 St->getChain().hasOneUse() && !St->isVolatile()) {
8431 SDNode* LdVal = St->getValue().getNode();
8433 int TokenFactorIndex = -1;
8434 SmallVector<SDValue, 8> Ops;
8435 SDNode* ChainVal = St->getChain().getNode();
8436 // Must be a store of a load. We currently handle two cases: the load
8437 // is a direct child, and it's under an intervening TokenFactor. It is
8438 // possible to dig deeper under nested TokenFactors.
8439 if (ChainVal == LdVal)
8440 Ld = cast<LoadSDNode>(St->getChain());
8441 else if (St->getValue().hasOneUse() &&
8442 ChainVal->getOpcode() == ISD::TokenFactor) {
8443 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
8444 if (ChainVal->getOperand(i).getNode() == LdVal) {
8445 TokenFactorIndex = i;
8446 Ld = cast<LoadSDNode>(St->getValue());
8448 Ops.push_back(ChainVal->getOperand(i));
8452 if (!Ld || !ISD::isNormalLoad(Ld))
8455 // If this is not the MMX case, i.e. we are just turning i64 load/store
8456 // into f64 load/store, avoid the transformation if there are multiple
8457 // uses of the loaded value.
8458 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
8461 DebugLoc LdDL = Ld->getDebugLoc();
8462 DebugLoc StDL = N->getDebugLoc();
8463 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
8464 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
8466 if (Subtarget->is64Bit() || F64IsLegal) {
8467 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
8468 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
8469 Ld->getBasePtr(), Ld->getSrcValue(),
8470 Ld->getSrcValueOffset(), Ld->isVolatile(),
8471 Ld->getAlignment());
8472 SDValue NewChain = NewLd.getValue(1);
8473 if (TokenFactorIndex != -1) {
8474 Ops.push_back(NewChain);
8475 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8478 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
8479 St->getSrcValue(), St->getSrcValueOffset(),
8480 St->isVolatile(), St->getAlignment());
8483 // Otherwise, lower to two pairs of 32-bit loads / stores.
8484 SDValue LoAddr = Ld->getBasePtr();
8485 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
8486 DAG.getConstant(4, MVT::i32));
8488 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
8489 Ld->getSrcValue(), Ld->getSrcValueOffset(),
8490 Ld->isVolatile(), Ld->getAlignment());
8491 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
8492 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
8494 MinAlign(Ld->getAlignment(), 4));
8496 SDValue NewChain = LoLd.getValue(1);
8497 if (TokenFactorIndex != -1) {
8498 Ops.push_back(LoLd);
8499 Ops.push_back(HiLd);
8500 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8504 LoAddr = St->getBasePtr();
8505 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
8506 DAG.getConstant(4, MVT::i32));
8508 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
8509 St->getSrcValue(), St->getSrcValueOffset(),
8510 St->isVolatile(), St->getAlignment());
8511 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
8513 St->getSrcValueOffset() + 4,
8515 MinAlign(St->getAlignment(), 4));
8516 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
8521 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
8522 /// X86ISD::FXOR nodes.
8523 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
8524 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
8525 // F[X]OR(0.0, x) -> x
8526 // F[X]OR(x, 0.0) -> x
8527 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8528 if (C->getValueAPF().isPosZero())
8529 return N->getOperand(1);
8530 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8531 if (C->getValueAPF().isPosZero())
8532 return N->getOperand(0);
8536 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
8537 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
8538 // FAND(0.0, x) -> 0.0
8539 // FAND(x, 0.0) -> 0.0
8540 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8541 if (C->getValueAPF().isPosZero())
8542 return N->getOperand(0);
8543 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8544 if (C->getValueAPF().isPosZero())
8545 return N->getOperand(1);
8549 static SDValue PerformBTCombine(SDNode *N,
8551 TargetLowering::DAGCombinerInfo &DCI) {
8552 // BT ignores high bits in the bit index operand.
8553 SDValue Op1 = N->getOperand(1);
8554 if (Op1.hasOneUse()) {
8555 unsigned BitWidth = Op1.getValueSizeInBits();
8556 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
8557 APInt KnownZero, KnownOne;
8558 TargetLowering::TargetLoweringOpt TLO(DAG);
8559 TargetLowering &TLI = DAG.getTargetLoweringInfo();
8560 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
8561 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
8562 DCI.CommitTargetLoweringOpt(TLO);
8567 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
8568 SDValue Op = N->getOperand(0);
8569 if (Op.getOpcode() == ISD::BIT_CONVERT)
8570 Op = Op.getOperand(0);
8571 MVT VT = N->getValueType(0), OpVT = Op.getValueType();
8572 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
8573 VT.getVectorElementType().getSizeInBits() ==
8574 OpVT.getVectorElementType().getSizeInBits()) {
8575 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
8580 // On X86 and X86-64, atomic operations are lowered to locked instructions.
8581 // Locked instructions, in turn, have implicit fence semantics (all memory
8582 // operations are flushed before issuing the locked instruction, and the
8583 // are not buffered), so we can fold away the common pattern of
8584 // fence-atomic-fence.
8585 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
8586 SDValue atomic = N->getOperand(0);
8587 switch (atomic.getOpcode()) {
8588 case ISD::ATOMIC_CMP_SWAP:
8589 case ISD::ATOMIC_SWAP:
8590 case ISD::ATOMIC_LOAD_ADD:
8591 case ISD::ATOMIC_LOAD_SUB:
8592 case ISD::ATOMIC_LOAD_AND:
8593 case ISD::ATOMIC_LOAD_OR:
8594 case ISD::ATOMIC_LOAD_XOR:
8595 case ISD::ATOMIC_LOAD_NAND:
8596 case ISD::ATOMIC_LOAD_MIN:
8597 case ISD::ATOMIC_LOAD_MAX:
8598 case ISD::ATOMIC_LOAD_UMIN:
8599 case ISD::ATOMIC_LOAD_UMAX:
8605 SDValue fence = atomic.getOperand(0);
8606 if (fence.getOpcode() != ISD::MEMBARRIER)
8609 switch (atomic.getOpcode()) {
8610 case ISD::ATOMIC_CMP_SWAP:
8611 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8612 atomic.getOperand(1), atomic.getOperand(2),
8613 atomic.getOperand(3));
8614 case ISD::ATOMIC_SWAP:
8615 case ISD::ATOMIC_LOAD_ADD:
8616 case ISD::ATOMIC_LOAD_SUB:
8617 case ISD::ATOMIC_LOAD_AND:
8618 case ISD::ATOMIC_LOAD_OR:
8619 case ISD::ATOMIC_LOAD_XOR:
8620 case ISD::ATOMIC_LOAD_NAND:
8621 case ISD::ATOMIC_LOAD_MIN:
8622 case ISD::ATOMIC_LOAD_MAX:
8623 case ISD::ATOMIC_LOAD_UMIN:
8624 case ISD::ATOMIC_LOAD_UMAX:
8625 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8626 atomic.getOperand(1), atomic.getOperand(2));
8632 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
8633 DAGCombinerInfo &DCI) const {
8634 SelectionDAG &DAG = DCI.DAG;
8635 switch (N->getOpcode()) {
8637 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
8638 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
8639 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
8640 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
8643 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
8644 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
8646 case X86ISD::FOR: return PerformFORCombine(N, DAG);
8647 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
8648 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
8649 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
8650 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
8656 //===----------------------------------------------------------------------===//
8657 // X86 Inline Assembly Support
8658 //===----------------------------------------------------------------------===//
8660 /// getConstraintType - Given a constraint letter, return the type of
8661 /// constraint it is for this target.
8662 X86TargetLowering::ConstraintType
8663 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
8664 if (Constraint.size() == 1) {
8665 switch (Constraint[0]) {
8677 return C_RegisterClass;
8685 return TargetLowering::getConstraintType(Constraint);
8688 /// LowerXConstraint - try to replace an X constraint, which matches anything,
8689 /// with another that has more specific requirements based on the type of the
8690 /// corresponding operand.
8691 const char *X86TargetLowering::
8692 LowerXConstraint(MVT ConstraintVT) const {
8693 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
8694 // 'f' like normal targets.
8695 if (ConstraintVT.isFloatingPoint()) {
8696 if (Subtarget->hasSSE2())
8698 if (Subtarget->hasSSE1())
8702 return TargetLowering::LowerXConstraint(ConstraintVT);
8705 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8706 /// vector. If it is invalid, don't add anything to Ops.
8707 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8710 std::vector<SDValue>&Ops,
8711 SelectionDAG &DAG) const {
8712 SDValue Result(0, 0);
8714 switch (Constraint) {
8717 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8718 if (C->getZExtValue() <= 31) {
8719 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8725 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8726 if (C->getZExtValue() <= 63) {
8727 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8733 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8734 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
8735 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8741 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8742 if (C->getZExtValue() <= 255) {
8743 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8749 // 32-bit signed value
8750 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8751 const ConstantInt *CI = C->getConstantIntValue();
8752 if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) {
8753 // Widen to 64 bits here to get it sign extended.
8754 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
8757 // FIXME gcc accepts some relocatable values here too, but only in certain
8758 // memory models; it's complicated.
8763 // 32-bit unsigned value
8764 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8765 const ConstantInt *CI = C->getConstantIntValue();
8766 if (CI->isValueValidForType(Type::Int32Ty, C->getZExtValue())) {
8767 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8771 // FIXME gcc accepts some relocatable values here too, but only in certain
8772 // memory models; it's complicated.
8776 // Literal immediates are always ok.
8777 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
8778 // Widen to 64 bits here to get it sign extended.
8779 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
8783 // If we are in non-pic codegen mode, we allow the address of a global (with
8784 // an optional displacement) to be used with 'i'.
8785 GlobalAddressSDNode *GA = 0;
8788 // Match either (GA), (GA+C), (GA+C1+C2), etc.
8790 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
8791 Offset += GA->getOffset();
8793 } else if (Op.getOpcode() == ISD::ADD) {
8794 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
8795 Offset += C->getZExtValue();
8796 Op = Op.getOperand(0);
8799 } else if (Op.getOpcode() == ISD::SUB) {
8800 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
8801 Offset += -C->getZExtValue();
8802 Op = Op.getOperand(0);
8807 // Otherwise, this isn't something we can handle, reject it.
8812 Op = LowerGlobalAddress(GA->getGlobal(), Op.getDebugLoc(), Offset, DAG);
8814 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
8821 if (Result.getNode()) {
8822 Ops.push_back(Result);
8825 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
8829 std::vector<unsigned> X86TargetLowering::
8830 getRegClassForInlineAsmConstraint(const std::string &Constraint,
8832 if (Constraint.size() == 1) {
8833 // FIXME: not handling fp-stack yet!
8834 switch (Constraint[0]) { // GCC X86 Constraint Letters
8835 default: break; // Unknown constraint letter
8836 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
8839 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
8840 else if (VT == MVT::i16)
8841 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
8842 else if (VT == MVT::i8)
8843 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
8844 else if (VT == MVT::i64)
8845 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
8850 return std::vector<unsigned>();
8853 std::pair<unsigned, const TargetRegisterClass*>
8854 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8856 // First, see if this is a constraint that directly corresponds to an LLVM
8858 if (Constraint.size() == 1) {
8859 // GCC Constraint Letters
8860 switch (Constraint[0]) {
8862 case 'r': // GENERAL_REGS
8863 case 'R': // LEGACY_REGS
8864 case 'l': // INDEX_REGS
8866 return std::make_pair(0U, X86::GR8RegisterClass);
8868 return std::make_pair(0U, X86::GR16RegisterClass);
8869 if (VT == MVT::i32 || !Subtarget->is64Bit())
8870 return std::make_pair(0U, X86::GR32RegisterClass);
8871 return std::make_pair(0U, X86::GR64RegisterClass);
8872 case 'f': // FP Stack registers.
8873 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
8874 // value to the correct fpstack register class.
8875 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
8876 return std::make_pair(0U, X86::RFP32RegisterClass);
8877 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
8878 return std::make_pair(0U, X86::RFP64RegisterClass);
8879 return std::make_pair(0U, X86::RFP80RegisterClass);
8880 case 'y': // MMX_REGS if MMX allowed.
8881 if (!Subtarget->hasMMX()) break;
8882 return std::make_pair(0U, X86::VR64RegisterClass);
8883 case 'Y': // SSE_REGS if SSE2 allowed
8884 if (!Subtarget->hasSSE2()) break;
8886 case 'x': // SSE_REGS if SSE1 allowed
8887 if (!Subtarget->hasSSE1()) break;
8889 switch (VT.getSimpleVT()) {
8891 // Scalar SSE types.
8894 return std::make_pair(0U, X86::FR32RegisterClass);
8897 return std::make_pair(0U, X86::FR64RegisterClass);
8905 return std::make_pair(0U, X86::VR128RegisterClass);
8911 // Use the default implementation in TargetLowering to convert the register
8912 // constraint into a member of a register class.
8913 std::pair<unsigned, const TargetRegisterClass*> Res;
8914 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8916 // Not found as a standard register?
8917 if (Res.second == 0) {
8918 // GCC calls "st(0)" just plain "st".
8919 if (StringsEqualNoCase("{st}", Constraint)) {
8920 Res.first = X86::ST0;
8921 Res.second = X86::RFP80RegisterClass;
8923 // 'A' means EAX + EDX.
8924 if (Constraint == "A") {
8925 Res.first = X86::EAX;
8926 Res.second = X86::GRADRegisterClass;
8931 // Otherwise, check to see if this is a register class of the wrong value
8932 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
8933 // turn into {ax},{dx}.
8934 if (Res.second->hasType(VT))
8935 return Res; // Correct type already, nothing to do.
8937 // All of the single-register GCC register classes map their values onto
8938 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
8939 // really want an 8-bit or 32-bit register, map to the appropriate register
8940 // class and return the appropriate register.
8941 if (Res.second == X86::GR16RegisterClass) {
8942 if (VT == MVT::i8) {
8943 unsigned DestReg = 0;
8944 switch (Res.first) {
8946 case X86::AX: DestReg = X86::AL; break;
8947 case X86::DX: DestReg = X86::DL; break;
8948 case X86::CX: DestReg = X86::CL; break;
8949 case X86::BX: DestReg = X86::BL; break;
8952 Res.first = DestReg;
8953 Res.second = X86::GR8RegisterClass;
8955 } else if (VT == MVT::i32) {
8956 unsigned DestReg = 0;
8957 switch (Res.first) {
8959 case X86::AX: DestReg = X86::EAX; break;
8960 case X86::DX: DestReg = X86::EDX; break;
8961 case X86::CX: DestReg = X86::ECX; break;
8962 case X86::BX: DestReg = X86::EBX; break;
8963 case X86::SI: DestReg = X86::ESI; break;
8964 case X86::DI: DestReg = X86::EDI; break;
8965 case X86::BP: DestReg = X86::EBP; break;
8966 case X86::SP: DestReg = X86::ESP; break;
8969 Res.first = DestReg;
8970 Res.second = X86::GR32RegisterClass;
8972 } else if (VT == MVT::i64) {
8973 unsigned DestReg = 0;
8974 switch (Res.first) {
8976 case X86::AX: DestReg = X86::RAX; break;
8977 case X86::DX: DestReg = X86::RDX; break;
8978 case X86::CX: DestReg = X86::RCX; break;
8979 case X86::BX: DestReg = X86::RBX; break;
8980 case X86::SI: DestReg = X86::RSI; break;
8981 case X86::DI: DestReg = X86::RDI; break;
8982 case X86::BP: DestReg = X86::RBP; break;
8983 case X86::SP: DestReg = X86::RSP; break;
8986 Res.first = DestReg;
8987 Res.second = X86::GR64RegisterClass;
8990 } else if (Res.second == X86::FR32RegisterClass ||
8991 Res.second == X86::FR64RegisterClass ||
8992 Res.second == X86::VR128RegisterClass) {
8993 // Handle references to XMM physical registers that got mapped into the
8994 // wrong class. This can happen with constraints like {xmm0} where the
8995 // target independent register mapper will just pick the first match it can
8996 // find, ignoring the required type.
8998 Res.second = X86::FR32RegisterClass;
8999 else if (VT == MVT::f64)
9000 Res.second = X86::FR64RegisterClass;
9001 else if (X86::VR128RegisterClass->hasType(VT))
9002 Res.second = X86::VR128RegisterClass;
9008 //===----------------------------------------------------------------------===//
9009 // X86 Widen vector type
9010 //===----------------------------------------------------------------------===//
9012 /// getWidenVectorType: given a vector type, returns the type to widen
9013 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9014 /// If there is no vector type that we want to widen to, returns MVT::Other
9015 /// When and where to widen is target dependent based on the cost of
9016 /// scalarizing vs using the wider vector type.
9018 MVT X86TargetLowering::getWidenVectorType(MVT VT) const {
9019 assert(VT.isVector());
9020 if (isTypeLegal(VT))
9023 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9024 // type based on element type. This would speed up our search (though
9025 // it may not be worth it since the size of the list is relatively
9027 MVT EltVT = VT.getVectorElementType();
9028 unsigned NElts = VT.getVectorNumElements();
9030 // On X86, it make sense to widen any vector wider than 1
9034 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9035 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9036 MVT SVT = (MVT::SimpleValueType)nVT;
9038 if (isTypeLegal(SVT) &&
9039 SVT.getVectorElementType() == EltVT &&
9040 SVT.getVectorNumElements() > NElts)