1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
32 cl::desc("Enable fastcc on X86"));
34 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
35 : TargetLowering(TM) {
36 Subtarget = &TM.getSubtarget<X86Subtarget>();
37 X86ScalarSSE = Subtarget->hasSSE2();
39 // Set up the TargetLowering object.
41 // X86 is weird, it always uses i8 for shift amounts and setcc results.
42 setShiftAmountType(MVT::i8);
43 setSetCCResultType(MVT::i8);
44 setSetCCResultContents(ZeroOrOneSetCCResult);
45 setSchedulingPreference(SchedulingForRegPressure);
46 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
47 setStackPointerRegisterToSaveRestore(X86::ESP);
49 // Set up the register classes.
50 addRegisterClass(MVT::i8, X86::R8RegisterClass);
51 addRegisterClass(MVT::i16, X86::R16RegisterClass);
52 addRegisterClass(MVT::i32, X86::R32RegisterClass);
54 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
56 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
57 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
58 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
61 // No SSE i64 SINT_TO_FP, so expand i32 UINT_TO_FP instead.
62 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
64 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
66 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
68 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
69 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
72 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
74 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
75 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
76 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
77 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
80 // Handle FP_TO_UINT by promoting the destination to a larger signed
82 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
83 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
84 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
87 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
89 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
91 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
92 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
93 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
95 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
96 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
99 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
101 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
102 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
103 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
105 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
107 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
108 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
109 setOperationAction(ISD::FREM , MVT::f64 , Expand);
110 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
111 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
112 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
113 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
114 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
115 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
116 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
117 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
118 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
119 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
122 setOperationAction(ISD::BSWAP , MVT::i32 , Expand);
123 setOperationAction(ISD::ROTL , MVT::i8 , Expand);
124 setOperationAction(ISD::ROTR , MVT::i8 , Expand);
125 setOperationAction(ISD::ROTL , MVT::i16 , Expand);
126 setOperationAction(ISD::ROTR , MVT::i16 , Expand);
127 setOperationAction(ISD::ROTL , MVT::i32 , Expand);
128 setOperationAction(ISD::ROTR , MVT::i32 , Expand);
130 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
132 setOperationAction(ISD::READIO , MVT::i1 , Expand);
133 setOperationAction(ISD::READIO , MVT::i8 , Expand);
134 setOperationAction(ISD::READIO , MVT::i16 , Expand);
135 setOperationAction(ISD::READIO , MVT::i32 , Expand);
136 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
137 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
138 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
139 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
141 // These should be promoted to a larger select which is supported.
142 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
143 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
145 // X86 wants to expand cmov itself.
146 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
147 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
148 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
149 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
150 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
151 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
152 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
153 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
154 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
155 // X86 ret instruction may pop stack.
156 setOperationAction(ISD::RET , MVT::Other, Custom);
158 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
159 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
160 setOperationAction(ISD::ADD_PARTS , MVT::i32 , Custom);
161 setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom);
162 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
163 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
164 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
165 // X86 wants to expand memset / memcpy itself.
166 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
167 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
170 // We don't have line number support yet.
171 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
172 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
173 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
175 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
176 setOperationAction(ISD::VASTART , MVT::Other, Custom);
178 // Use the default implementation.
179 setOperationAction(ISD::VAARG , MVT::Other, Expand);
180 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
181 setOperationAction(ISD::VAEND , MVT::Other, Expand);
182 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
183 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
184 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
187 // Set up the FP register classes.
188 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
189 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
191 // SSE has no load+extend ops
192 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
193 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
195 // SSE has no i16 to fp conversion, only i32
196 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
197 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
199 // Expand FP_TO_UINT into a select.
200 // FIXME: We would like to use a Custom expander here eventually to do
201 // the optimal thing for SSE vs. the default expansion in the legalizer.
202 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
204 // We don't support sin/cos/sqrt/fmod
205 setOperationAction(ISD::FSIN , MVT::f64, Expand);
206 setOperationAction(ISD::FCOS , MVT::f64, Expand);
207 setOperationAction(ISD::FABS , MVT::f64, Expand);
208 setOperationAction(ISD::FNEG , MVT::f64, Expand);
209 setOperationAction(ISD::FREM , MVT::f64, Expand);
210 setOperationAction(ISD::FSIN , MVT::f32, Expand);
211 setOperationAction(ISD::FCOS , MVT::f32, Expand);
212 setOperationAction(ISD::FABS , MVT::f32, Expand);
213 setOperationAction(ISD::FNEG , MVT::f32, Expand);
214 setOperationAction(ISD::FREM , MVT::f32, Expand);
216 // Expand FP immediates into loads from the stack, except for the special
218 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
219 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
220 addLegalFPImmediate(+0.0); // xorps / xorpd
222 // Set up the FP register classes.
223 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
225 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
228 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
229 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
233 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
234 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
237 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
238 addLegalFPImmediate(+0.0); // FLD0
239 addLegalFPImmediate(+1.0); // FLD1
240 addLegalFPImmediate(-0.0); // FLD0/FCHS
241 addLegalFPImmediate(-1.0); // FLD1/FCHS
243 computeRegisterProperties();
245 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
246 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
247 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
248 allowUnalignedMemoryAccesses = true; // x86 supports it!
251 std::vector<SDOperand>
252 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
253 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
254 return LowerFastCCArguments(F, DAG);
255 return LowerCCCArguments(F, DAG);
258 std::pair<SDOperand, SDOperand>
259 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
260 bool isVarArg, unsigned CallingConv,
262 SDOperand Callee, ArgListTy &Args,
264 assert((!isVarArg || CallingConv == CallingConv::C) &&
265 "Only C takes varargs!");
267 // If the callee is a GlobalAddress node (quite common, every direct call is)
268 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
269 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
270 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
271 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
272 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
274 if (CallingConv == CallingConv::Fast && EnableFastCC)
275 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
276 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
279 //===----------------------------------------------------------------------===//
280 // C Calling Convention implementation
281 //===----------------------------------------------------------------------===//
283 std::vector<SDOperand>
284 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
285 std::vector<SDOperand> ArgValues;
287 MachineFunction &MF = DAG.getMachineFunction();
288 MachineFrameInfo *MFI = MF.getFrameInfo();
290 // Add DAG nodes to load the arguments... On entry to a function on the X86,
291 // the stack frame looks like this:
293 // [ESP] -- return address
294 // [ESP + 4] -- first argument (leftmost lexically)
295 // [ESP + 8] -- second argument, if first argument is four bytes in size
298 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
299 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
300 MVT::ValueType ObjectVT = getValueType(I->getType());
301 unsigned ArgIncrement = 4;
304 default: assert(0 && "Unhandled argument type!");
306 case MVT::i8: ObjSize = 1; break;
307 case MVT::i16: ObjSize = 2; break;
308 case MVT::i32: ObjSize = 4; break;
309 case MVT::i64: ObjSize = ArgIncrement = 8; break;
310 case MVT::f32: ObjSize = 4; break;
311 case MVT::f64: ObjSize = ArgIncrement = 8; break;
313 // Create the frame index object for this incoming parameter...
314 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
316 // Create the SelectionDAG nodes corresponding to a load from this parameter
317 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
319 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
323 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
324 DAG.getSrcValue(NULL));
326 if (MVT::isInteger(ObjectVT))
327 ArgValue = DAG.getConstant(0, ObjectVT);
329 ArgValue = DAG.getConstantFP(0, ObjectVT);
331 ArgValues.push_back(ArgValue);
333 ArgOffset += ArgIncrement; // Move on to the next argument...
336 // If the function takes variable number of arguments, make a frame index for
337 // the start of the first vararg value... for expansion of llvm.va_start.
339 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
340 ReturnAddrIndex = 0; // No return address slot generated yet.
341 BytesToPopOnReturn = 0; // Callee pops nothing.
342 BytesCallerReserves = ArgOffset;
344 // Finally, inform the code generator which regs we return values in.
345 switch (getValueType(F.getReturnType())) {
346 default: assert(0 && "Unknown type!");
347 case MVT::isVoid: break;
352 MF.addLiveOut(X86::EAX);
355 MF.addLiveOut(X86::EAX);
356 MF.addLiveOut(X86::EDX);
360 MF.addLiveOut(X86::ST0);
366 std::pair<SDOperand, SDOperand>
367 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
368 bool isVarArg, bool isTailCall,
369 SDOperand Callee, ArgListTy &Args,
371 // Count how many bytes are to be pushed on the stack.
372 unsigned NumBytes = 0;
376 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
377 DAG.getConstant(0, getPointerTy()));
379 for (unsigned i = 0, e = Args.size(); i != e; ++i)
380 switch (getValueType(Args[i].second)) {
381 default: assert(0 && "Unknown value type!");
395 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
396 DAG.getConstant(NumBytes, getPointerTy()));
398 // Arguments go on the stack in reverse order, as specified by the ABI.
399 unsigned ArgOffset = 0;
400 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
401 std::vector<SDOperand> Stores;
403 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
404 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
405 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
407 switch (getValueType(Args[i].second)) {
408 default: assert(0 && "Unexpected ValueType for argument!");
412 // Promote the integer to 32 bits. If the input type is signed use a
413 // sign extend, otherwise use a zero extend.
414 if (Args[i].second->isSigned())
415 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
417 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
422 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
423 Args[i].first, PtrOff,
424 DAG.getSrcValue(NULL)));
429 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
430 Args[i].first, PtrOff,
431 DAG.getSrcValue(NULL)));
436 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
439 std::vector<MVT::ValueType> RetVals;
440 MVT::ValueType RetTyVT = getValueType(RetTy);
441 RetVals.push_back(MVT::Other);
443 // The result values produced have to be legal. Promote the result.
445 case MVT::isVoid: break;
447 RetVals.push_back(RetTyVT);
452 RetVals.push_back(MVT::i32);
456 RetVals.push_back(MVT::f32);
458 RetVals.push_back(MVT::f64);
461 RetVals.push_back(MVT::i32);
462 RetVals.push_back(MVT::i32);
467 std::vector<MVT::ValueType> NodeTys;
468 NodeTys.push_back(MVT::Other); // Returns a chain
469 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
470 std::vector<SDOperand> Ops;
471 Ops.push_back(Chain);
472 Ops.push_back(Callee);
474 // FIXME: Do not generate X86ISD::TAILCALL for now.
475 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
476 SDOperand InFlag = Chain.getValue(1);
479 NodeTys.push_back(MVT::Other); // Returns a chain
480 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
482 Ops.push_back(Chain);
483 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
484 Ops.push_back(DAG.getConstant(0, getPointerTy()));
485 Ops.push_back(InFlag);
486 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
487 InFlag = Chain.getValue(1);
490 if (RetTyVT != MVT::isVoid) {
492 default: assert(0 && "Unknown value type to return!");
495 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
496 Chain = RetVal.getValue(1);
497 if (RetTyVT == MVT::i1)
498 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
501 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
502 Chain = RetVal.getValue(1);
505 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
506 Chain = RetVal.getValue(1);
509 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
510 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
512 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
513 Chain = Hi.getValue(1);
518 std::vector<MVT::ValueType> Tys;
519 Tys.push_back(MVT::f64);
520 Tys.push_back(MVT::Other);
521 Tys.push_back(MVT::Flag);
522 std::vector<SDOperand> Ops;
523 Ops.push_back(Chain);
524 Ops.push_back(InFlag);
525 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
526 Chain = RetVal.getValue(1);
527 InFlag = RetVal.getValue(2);
529 // FIXME:Currently the FST is flagged to the FP_GET_RESULT. This
530 // shouldn't be necessary except for RFP cannot be live across
531 // multiple blocks. When stackifier is fixed, they can be uncoupled.
532 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
533 MachineFunction &MF = DAG.getMachineFunction();
534 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
535 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
537 Tys.push_back(MVT::Other);
539 Ops.push_back(Chain);
540 Ops.push_back(RetVal);
541 Ops.push_back(StackSlot);
542 Ops.push_back(DAG.getValueType(RetTyVT));
543 Ops.push_back(InFlag);
544 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
545 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
546 DAG.getSrcValue(NULL));
547 Chain = RetVal.getValue(1);
550 if (RetTyVT == MVT::f32 && !X86ScalarSSE)
551 // FIXME: we would really like to remember that this FP_ROUND
552 // operation is okay to eliminate if we allow excess FP precision.
553 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
559 return std::make_pair(RetVal, Chain);
561 std::vector<SDOperand> Ops;
562 Ops.push_back(Chain);
563 Ops.push_back(Callee);
564 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
565 Ops.push_back(DAG.getConstant(0, getPointerTy()));
567 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
572 case MVT::isVoid: break;
574 ResultVal = TheCall.getValue(1);
579 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
582 // FIXME: we would really like to remember that this FP_ROUND operation is
583 // okay to eliminate if we allow excess FP precision.
584 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
587 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
588 TheCall.getValue(2));
592 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
593 return std::make_pair(ResultVal, Chain);
597 //===----------------------------------------------------------------------===//
598 // Fast Calling Convention implementation
599 //===----------------------------------------------------------------------===//
601 // The X86 'fast' calling convention passes up to two integer arguments in
602 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
603 // and requires that the callee pop its arguments off the stack (allowing proper
604 // tail calls), and has the same return value conventions as C calling convs.
606 // This calling convention always arranges for the callee pop value to be 8n+4
607 // bytes, which is needed for tail recursion elimination and stack alignment
610 // Note that this can be enhanced in the future to pass fp vals in registers
611 // (when we have a global fp allocator) and do other tricks.
614 /// AddLiveIn - This helper function adds the specified physical register to the
615 /// MachineFunction as a live in value. It also creates a corresponding virtual
617 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
618 TargetRegisterClass *RC) {
619 assert(RC->contains(PReg) && "Not the correct regclass!");
620 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
621 MF.addLiveIn(PReg, VReg);
626 std::vector<SDOperand>
627 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
628 std::vector<SDOperand> ArgValues;
630 MachineFunction &MF = DAG.getMachineFunction();
631 MachineFrameInfo *MFI = MF.getFrameInfo();
633 // Add DAG nodes to load the arguments... On entry to a function the stack
634 // frame looks like this:
636 // [ESP] -- return address
637 // [ESP + 4] -- first nonreg argument (leftmost lexically)
638 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
640 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
642 // Keep track of the number of integer regs passed so far. This can be either
643 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
645 unsigned NumIntRegs = 0;
647 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
648 MVT::ValueType ObjectVT = getValueType(I->getType());
649 unsigned ArgIncrement = 4;
650 unsigned ObjSize = 0;
654 default: assert(0 && "Unhandled argument type!");
657 if (NumIntRegs < 2) {
658 if (!I->use_empty()) {
659 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
660 X86::R8RegisterClass);
661 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
662 DAG.setRoot(ArgValue.getValue(1));
663 if (ObjectVT == MVT::i1)
664 // FIXME: Should insert a assertzext here.
665 ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue);
674 if (NumIntRegs < 2) {
675 if (!I->use_empty()) {
676 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
677 X86::R16RegisterClass);
678 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
679 DAG.setRoot(ArgValue.getValue(1));
687 if (NumIntRegs < 2) {
688 if (!I->use_empty()) {
689 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
690 X86::R32RegisterClass);
691 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
692 DAG.setRoot(ArgValue.getValue(1));
700 if (NumIntRegs == 0) {
701 if (!I->use_empty()) {
702 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
703 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
705 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
706 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
707 DAG.setRoot(Hi.getValue(1));
709 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
713 } else if (NumIntRegs == 1) {
714 if (!I->use_empty()) {
715 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
716 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
717 DAG.setRoot(Low.getValue(1));
719 // Load the high part from memory.
720 // Create the frame index object for this incoming parameter...
721 int FI = MFI->CreateFixedObject(4, ArgOffset);
722 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
723 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
724 DAG.getSrcValue(NULL));
725 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
731 ObjSize = ArgIncrement = 8;
733 case MVT::f32: ObjSize = 4; break;
734 case MVT::f64: ObjSize = ArgIncrement = 8; break;
737 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
739 if (ObjSize && !I->use_empty()) {
740 // Create the frame index object for this incoming parameter...
741 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
743 // Create the SelectionDAG nodes corresponding to a load from this
745 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
747 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
748 DAG.getSrcValue(NULL));
749 } else if (ArgValue.Val == 0) {
750 if (MVT::isInteger(ObjectVT))
751 ArgValue = DAG.getConstant(0, ObjectVT);
753 ArgValue = DAG.getConstantFP(0, ObjectVT);
755 ArgValues.push_back(ArgValue);
758 ArgOffset += ArgIncrement; // Move on to the next argument.
761 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
762 // arguments and the arguments after the retaddr has been pushed are aligned.
763 if ((ArgOffset & 7) == 0)
766 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
767 ReturnAddrIndex = 0; // No return address slot generated yet.
768 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
769 BytesCallerReserves = 0;
771 // Finally, inform the code generator which regs we return values in.
772 switch (getValueType(F.getReturnType())) {
773 default: assert(0 && "Unknown type!");
774 case MVT::isVoid: break;
779 MF.addLiveOut(X86::EAX);
782 MF.addLiveOut(X86::EAX);
783 MF.addLiveOut(X86::EDX);
787 MF.addLiveOut(X86::ST0);
793 std::pair<SDOperand, SDOperand>
794 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
795 bool isTailCall, SDOperand Callee,
796 ArgListTy &Args, SelectionDAG &DAG) {
797 // Count how many bytes are to be pushed on the stack.
798 unsigned NumBytes = 0;
800 // Keep track of the number of integer regs passed so far. This can be either
801 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
803 unsigned NumIntRegs = 0;
805 for (unsigned i = 0, e = Args.size(); i != e; ++i)
806 switch (getValueType(Args[i].second)) {
807 default: assert(0 && "Unknown value type!");
812 if (NumIntRegs < 2) {
821 if (NumIntRegs == 0) {
824 } else if (NumIntRegs == 1) {
836 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
837 // arguments and the arguments after the retaddr has been pushed are aligned.
838 if ((NumBytes & 7) == 0)
841 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
842 DAG.getConstant(NumBytes, getPointerTy()));
844 // Arguments go on the stack in reverse order, as specified by the ABI.
845 unsigned ArgOffset = 0;
846 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
848 std::vector<SDOperand> Stores;
849 std::vector<SDOperand> RegValuesToPass;
850 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
851 switch (getValueType(Args[i].second)) {
852 default: assert(0 && "Unexpected ValueType for argument!");
854 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first);
859 if (NumIntRegs < 2) {
860 RegValuesToPass.push_back(Args[i].first);
866 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
867 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
868 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
869 Args[i].first, PtrOff,
870 DAG.getSrcValue(NULL)));
875 if (NumIntRegs < 2) { // Can pass part of it in regs?
876 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
877 Args[i].first, DAG.getConstant(1, MVT::i32));
878 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
879 Args[i].first, DAG.getConstant(0, MVT::i32));
880 RegValuesToPass.push_back(Lo);
882 if (NumIntRegs < 2) { // Pass both parts in regs?
883 RegValuesToPass.push_back(Hi);
886 // Pass the high part in memory.
887 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
888 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
889 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
890 Hi, PtrOff, DAG.getSrcValue(NULL)));
897 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
898 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
899 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
900 Args[i].first, PtrOff,
901 DAG.getSrcValue(NULL)));
907 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
909 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
910 // arguments and the arguments after the retaddr has been pushed are aligned.
911 if ((ArgOffset & 7) == 0)
914 std::vector<MVT::ValueType> RetVals;
915 MVT::ValueType RetTyVT = getValueType(RetTy);
917 RetVals.push_back(MVT::Other);
919 // The result values produced have to be legal. Promote the result.
921 case MVT::isVoid: break;
923 RetVals.push_back(RetTyVT);
928 RetVals.push_back(MVT::i32);
932 RetVals.push_back(MVT::f32);
934 RetVals.push_back(MVT::f64);
937 RetVals.push_back(MVT::i32);
938 RetVals.push_back(MVT::i32);
943 // Build a sequence of copy-to-reg nodes chained together with token chain
944 // and flag operands which copy the outgoing args into registers.
946 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
948 SDOperand RegToPass = RegValuesToPass[i];
949 switch (RegToPass.getValueType()) {
950 default: assert(0 && "Bad thing to pass in regs");
952 CCReg = (i == 0) ? X86::AL : X86::DL;
955 CCReg = (i == 0) ? X86::AX : X86::DX;
958 CCReg = (i == 0) ? X86::EAX : X86::EDX;
962 Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag);
963 InFlag = Chain.getValue(1);
966 std::vector<MVT::ValueType> NodeTys;
967 NodeTys.push_back(MVT::Other); // Returns a chain
968 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
969 std::vector<SDOperand> Ops;
970 Ops.push_back(Chain);
971 Ops.push_back(Callee);
973 Ops.push_back(InFlag);
975 // FIXME: Do not generate X86ISD::TAILCALL for now.
976 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
977 InFlag = Chain.getValue(1);
980 NodeTys.push_back(MVT::Other); // Returns a chain
981 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
983 Ops.push_back(Chain);
984 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
985 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
986 Ops.push_back(InFlag);
987 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
988 InFlag = Chain.getValue(1);
991 if (RetTyVT != MVT::isVoid) {
993 default: assert(0 && "Unknown value type to return!");
996 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
997 Chain = RetVal.getValue(1);
998 if (RetTyVT == MVT::i1)
999 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
1002 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
1003 Chain = RetVal.getValue(1);
1006 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1007 Chain = RetVal.getValue(1);
1010 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1011 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
1013 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1014 Chain = Hi.getValue(1);
1019 std::vector<MVT::ValueType> Tys;
1020 Tys.push_back(MVT::f64);
1021 Tys.push_back(MVT::Other);
1022 Tys.push_back(MVT::Flag);
1023 std::vector<SDOperand> Ops;
1024 Ops.push_back(Chain);
1025 Ops.push_back(InFlag);
1026 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
1027 Chain = RetVal.getValue(1);
1028 InFlag = RetVal.getValue(2);
1030 // FIXME:Currently the FST is flagged to the FP_GET_RESULT. This
1031 // shouldn't be necessary except for RFP cannot be live across
1032 // multiple blocks. When stackifier is fixed, they can be uncoupled.
1033 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
1034 MachineFunction &MF = DAG.getMachineFunction();
1035 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1036 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1038 Tys.push_back(MVT::Other);
1040 Ops.push_back(Chain);
1041 Ops.push_back(RetVal);
1042 Ops.push_back(StackSlot);
1043 Ops.push_back(DAG.getValueType(RetTyVT));
1044 Ops.push_back(InFlag);
1045 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
1046 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
1047 DAG.getSrcValue(NULL));
1048 Chain = RetVal.getValue(1);
1051 if (RetTyVT == MVT::f32 && !X86ScalarSSE)
1052 // FIXME: we would really like to remember that this FP_ROUND
1053 // operation is okay to eliminate if we allow excess FP precision.
1054 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
1060 return std::make_pair(RetVal, Chain);
1062 std::vector<SDOperand> Ops;
1063 Ops.push_back(Chain);
1064 Ops.push_back(Callee);
1065 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1066 // Callee pops all arg values on the stack.
1067 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1069 // Pass register arguments as needed.
1070 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
1072 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1074 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
1076 SDOperand ResultVal;
1078 case MVT::isVoid: break;
1080 ResultVal = TheCall.getValue(1);
1085 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
1088 // FIXME: we would really like to remember that this FP_ROUND operation is
1089 // okay to eliminate if we allow excess FP precision.
1090 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
1093 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
1094 TheCall.getValue(2));
1098 return std::make_pair(ResultVal, Chain);
1102 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1103 if (ReturnAddrIndex == 0) {
1104 // Set up a frame object for the return address.
1105 MachineFunction &MF = DAG.getMachineFunction();
1106 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1109 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
1114 std::pair<SDOperand, SDOperand> X86TargetLowering::
1115 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
1116 SelectionDAG &DAG) {
1118 if (Depth) // Depths > 0 not supported yet!
1119 Result = DAG.getConstant(0, getPointerTy());
1121 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
1122 if (!isFrameAddress)
1123 // Just load the return address
1124 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
1125 DAG.getSrcValue(NULL));
1127 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
1128 DAG.getConstant(4, MVT::i32));
1130 return std::make_pair(Result, Chain);
1133 /// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode
1134 /// which corresponds to the condition code.
1135 static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
1137 default: assert(0 && "Unknown X86 conditional code!");
1138 case X86ISD::COND_A: return X86::JA;
1139 case X86ISD::COND_AE: return X86::JAE;
1140 case X86ISD::COND_B: return X86::JB;
1141 case X86ISD::COND_BE: return X86::JBE;
1142 case X86ISD::COND_E: return X86::JE;
1143 case X86ISD::COND_G: return X86::JG;
1144 case X86ISD::COND_GE: return X86::JGE;
1145 case X86ISD::COND_L: return X86::JL;
1146 case X86ISD::COND_LE: return X86::JLE;
1147 case X86ISD::COND_NE: return X86::JNE;
1148 case X86ISD::COND_NO: return X86::JNO;
1149 case X86ISD::COND_NP: return X86::JNP;
1150 case X86ISD::COND_NS: return X86::JNS;
1151 case X86ISD::COND_O: return X86::JO;
1152 case X86ISD::COND_P: return X86::JP;
1153 case X86ISD::COND_S: return X86::JS;
1157 /// getX86CC - do a one to one translation of a ISD::CondCode to the X86
1158 /// specific condition code. It returns a X86ISD::COND_INVALID if it cannot
1159 /// do a direct translation.
1160 static unsigned getX86CC(SDOperand CC, bool isFP) {
1161 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1162 unsigned X86CC = X86ISD::COND_INVALID;
1164 switch (SetCCOpcode) {
1166 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1167 case ISD::SETGT: X86CC = X86ISD::COND_G; break;
1168 case ISD::SETGE: X86CC = X86ISD::COND_GE; break;
1169 case ISD::SETLT: X86CC = X86ISD::COND_L; break;
1170 case ISD::SETLE: X86CC = X86ISD::COND_LE; break;
1171 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1172 case ISD::SETULT: X86CC = X86ISD::COND_B; break;
1173 case ISD::SETUGT: X86CC = X86ISD::COND_A; break;
1174 case ISD::SETULE: X86CC = X86ISD::COND_BE; break;
1175 case ISD::SETUGE: X86CC = X86ISD::COND_AE; break;
1178 // On a floating point condition, the flags are set as follows:
1180 // 0 | 0 | 0 | X > Y
1181 // 0 | 0 | 1 | X < Y
1182 // 1 | 0 | 0 | X == Y
1183 // 1 | 1 | 1 | unordered
1184 switch (SetCCOpcode) {
1187 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1189 case ISD::SETGT: X86CC = X86ISD::COND_A; break;
1191 case ISD::SETGE: X86CC = X86ISD::COND_AE; break;
1193 case ISD::SETLT: X86CC = X86ISD::COND_B; break;
1195 case ISD::SETLE: X86CC = X86ISD::COND_BE; break;
1197 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1198 case ISD::SETUO: X86CC = X86ISD::COND_P; break;
1199 case ISD::SETO: X86CC = X86ISD::COND_NP; break;
1205 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1206 /// code. Current x86 isa includes the following FP cmov instructions:
1207 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1208 static bool hasFPCMov(unsigned X86CC) {
1212 case X86ISD::COND_B:
1213 case X86ISD::COND_BE:
1214 case X86ISD::COND_E:
1215 case X86ISD::COND_P:
1216 case X86ISD::COND_A:
1217 case X86ISD::COND_AE:
1218 case X86ISD::COND_NE:
1219 case X86ISD::COND_NP:
1225 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1226 MachineBasicBlock *BB) {
1227 switch (MI->getOpcode()) {
1228 default: assert(false && "Unexpected instr type to insert");
1229 case X86::CMOV_FR32:
1230 case X86::CMOV_FR64: {
1231 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1232 // control-flow pattern. The incoming instruction knows the destination vreg
1233 // to set, the condition code register to branch on, the true/false values to
1234 // select between, and a branch opcode to use.
1235 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1236 ilist<MachineBasicBlock>::iterator It = BB;
1242 // cmpTY ccX, r1, r2
1244 // fallthrough --> copy0MBB
1245 MachineBasicBlock *thisMBB = BB;
1246 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1247 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1248 unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
1249 BuildMI(BB, Opc, 1).addMBB(sinkMBB);
1250 MachineFunction *F = BB->getParent();
1251 F->getBasicBlockList().insert(It, copy0MBB);
1252 F->getBasicBlockList().insert(It, sinkMBB);
1253 // Update machine-CFG edges
1254 BB->addSuccessor(copy0MBB);
1255 BB->addSuccessor(sinkMBB);
1258 // %FalseValue = ...
1259 // # fallthrough to sinkMBB
1262 // Update machine-CFG edges
1263 BB->addSuccessor(sinkMBB);
1266 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1269 BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
1270 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1271 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1273 delete MI; // The pseudo instruction is gone now.
1277 case X86::FP_TO_INT16_IN_MEM:
1278 case X86::FP_TO_INT32_IN_MEM:
1279 case X86::FP_TO_INT64_IN_MEM: {
1280 // Change the floating point control register to use "round towards zero"
1281 // mode when truncating to an integer value.
1282 MachineFunction *F = BB->getParent();
1283 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1284 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
1286 // Load the old value of the high byte of the control word...
1288 F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass);
1289 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
1291 // Set the high part to be round to zero...
1292 addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
1294 // Reload the modified control word now...
1295 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1297 // Restore the memory image of control word to original value
1298 addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
1300 // Get the X86 opcode to use.
1302 switch (MI->getOpcode()) {
1303 default: assert(0 && "illegal opcode!");
1304 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
1305 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
1306 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
1310 MachineOperand &Op = MI->getOperand(0);
1311 if (Op.isRegister()) {
1312 AM.BaseType = X86AddressMode::RegBase;
1313 AM.Base.Reg = Op.getReg();
1315 AM.BaseType = X86AddressMode::FrameIndexBase;
1316 AM.Base.FrameIndex = Op.getFrameIndex();
1318 Op = MI->getOperand(1);
1319 if (Op.isImmediate())
1320 AM.Scale = Op.getImmedValue();
1321 Op = MI->getOperand(2);
1322 if (Op.isImmediate())
1323 AM.IndexReg = Op.getImmedValue();
1324 Op = MI->getOperand(3);
1325 if (Op.isGlobalAddress()) {
1326 AM.GV = Op.getGlobal();
1328 AM.Disp = Op.getImmedValue();
1330 addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
1332 // Reload the original control word now.
1333 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1335 delete MI; // The pseudo instruction is gone now.
1342 //===----------------------------------------------------------------------===//
1343 // X86 Custom Lowering Hooks
1344 //===----------------------------------------------------------------------===//
1346 /// LowerOperation - Provide custom lowering hooks for some operations.
1348 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1349 switch (Op.getOpcode()) {
1350 default: assert(0 && "Should not custom lower this!");
1351 case ISD::ADD_PARTS:
1352 case ISD::SUB_PARTS: {
1353 assert(Op.getNumOperands() == 4 && Op.getValueType() == MVT::i32 &&
1354 "Not an i64 add/sub!");
1355 bool isAdd = Op.getOpcode() == ISD::ADD_PARTS;
1356 std::vector<MVT::ValueType> Tys;
1357 Tys.push_back(MVT::i32);
1358 Tys.push_back(MVT::Flag);
1359 std::vector<SDOperand> Ops;
1360 Ops.push_back(Op.getOperand(0));
1361 Ops.push_back(Op.getOperand(2));
1362 SDOperand Lo = DAG.getNode(isAdd ? X86ISD::ADD_FLAG : X86ISD::SUB_FLAG,
1364 SDOperand Hi = DAG.getNode(isAdd ? X86ISD::ADC : X86ISD::SBB, MVT::i32,
1365 Op.getOperand(1), Op.getOperand(3),
1368 Tys.push_back(MVT::i32);
1369 Tys.push_back(MVT::i32);
1373 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1375 case ISD::SHL_PARTS:
1376 case ISD::SRA_PARTS:
1377 case ISD::SRL_PARTS: {
1378 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1379 "Not an i64 shift!");
1380 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
1381 SDOperand ShOpLo = Op.getOperand(0);
1382 SDOperand ShOpHi = Op.getOperand(1);
1383 SDOperand ShAmt = Op.getOperand(2);
1384 SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
1385 DAG.getConstant(31, MVT::i8))
1386 : DAG.getConstant(0, MVT::i32);
1388 SDOperand Tmp2, Tmp3;
1389 if (Op.getOpcode() == ISD::SHL_PARTS) {
1390 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
1391 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
1393 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
1394 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
1397 SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
1398 ShAmt, DAG.getConstant(32, MVT::i8));
1401 SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1403 std::vector<MVT::ValueType> Tys;
1404 Tys.push_back(MVT::i32);
1405 Tys.push_back(MVT::Flag);
1406 std::vector<SDOperand> Ops;
1407 if (Op.getOpcode() == ISD::SHL_PARTS) {
1408 Ops.push_back(Tmp2);
1409 Ops.push_back(Tmp3);
1411 Ops.push_back(InFlag);
1412 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1413 InFlag = Hi.getValue(1);
1416 Ops.push_back(Tmp3);
1417 Ops.push_back(Tmp1);
1419 Ops.push_back(InFlag);
1420 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1422 Ops.push_back(Tmp2);
1423 Ops.push_back(Tmp3);
1425 Ops.push_back(InFlag);
1426 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1427 InFlag = Lo.getValue(1);
1430 Ops.push_back(Tmp3);
1431 Ops.push_back(Tmp1);
1433 Ops.push_back(InFlag);
1434 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1438 Tys.push_back(MVT::i32);
1439 Tys.push_back(MVT::i32);
1443 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1445 case ISD::SINT_TO_FP: {
1446 assert(Op.getValueType() == MVT::f64 &&
1447 Op.getOperand(0).getValueType() <= MVT::i64 &&
1448 Op.getOperand(0).getValueType() >= MVT::i16 &&
1449 "Unknown SINT_TO_FP to lower!");
1452 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
1453 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
1454 MachineFunction &MF = DAG.getMachineFunction();
1455 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1456 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1457 SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other,
1458 DAG.getEntryNode(), Op.getOperand(0),
1459 StackSlot, DAG.getSrcValue(NULL));
1462 std::vector<MVT::ValueType> Tys;
1463 Tys.push_back(MVT::f64);
1464 Tys.push_back(MVT::Flag);
1465 std::vector<SDOperand> Ops;
1466 Ops.push_back(Chain);
1467 Ops.push_back(StackSlot);
1468 Ops.push_back(DAG.getValueType(SrcVT));
1469 Result = DAG.getNode(X86ISD::FILD, Tys, Ops);
1472 case ISD::FP_TO_SINT: {
1473 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
1474 Op.getOperand(0).getValueType() == MVT::f64 &&
1475 "Unknown FP_TO_SINT to lower!");
1476 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
1478 MachineFunction &MF = DAG.getMachineFunction();
1479 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
1480 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1481 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1484 switch (Op.getValueType()) {
1485 default: assert(0 && "Invalid FP_TO_SINT to lower!");
1486 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
1487 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
1488 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
1491 // Build the FP_TO_INT*_IN_MEM
1492 std::vector<SDOperand> Ops;
1493 Ops.push_back(DAG.getEntryNode());
1494 Ops.push_back(Op.getOperand(0));
1495 Ops.push_back(StackSlot);
1496 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
1499 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
1500 DAG.getSrcValue(NULL));
1502 case ISD::READCYCLECOUNTER: {
1503 std::vector<MVT::ValueType> Tys;
1504 Tys.push_back(MVT::Other);
1505 Tys.push_back(MVT::Flag);
1506 std::vector<SDOperand> Ops;
1507 Ops.push_back(Op.getOperand(0));
1508 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
1510 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
1511 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
1512 MVT::i32, Ops[0].getValue(2)));
1513 Ops.push_back(Ops[1].getValue(1));
1514 Tys[0] = Tys[1] = MVT::i32;
1515 Tys.push_back(MVT::Other);
1516 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1519 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
1520 SDOperand CC = Op.getOperand(2);
1521 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1522 Op.getOperand(0), Op.getOperand(1));
1523 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1524 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
1525 unsigned X86CC = getX86CC(CC, isFP);
1526 if (X86CC != X86ISD::COND_INVALID) {
1527 return DAG.getNode(X86ISD::SETCC, MVT::i8,
1528 DAG.getConstant(X86CC, MVT::i8), Cond);
1530 assert(isFP && "Illegal integer SetCC!");
1532 std::vector<MVT::ValueType> Tys;
1533 std::vector<SDOperand> Ops;
1534 switch (SetCCOpcode) {
1535 default: assert(false && "Illegal floating point SetCC!");
1536 case ISD::SETOEQ: { // !PF & ZF
1537 Tys.push_back(MVT::i8);
1538 Tys.push_back(MVT::Flag);
1539 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1540 Ops.push_back(Cond);
1541 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1542 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1543 DAG.getConstant(X86ISD::COND_E, MVT::i8),
1545 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1547 case ISD::SETOLT: { // !PF & CF
1548 Tys.push_back(MVT::i8);
1549 Tys.push_back(MVT::Flag);
1550 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1551 Ops.push_back(Cond);
1552 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1553 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1554 DAG.getConstant(X86ISD::COND_B, MVT::i8),
1556 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1558 case ISD::SETOLE: { // !PF & (CF || ZF)
1559 Tys.push_back(MVT::i8);
1560 Tys.push_back(MVT::Flag);
1561 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1562 Ops.push_back(Cond);
1563 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1564 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1565 DAG.getConstant(X86ISD::COND_BE, MVT::i8),
1567 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1569 case ISD::SETUGT: { // PF | (!ZF & !CF)
1570 Tys.push_back(MVT::i8);
1571 Tys.push_back(MVT::Flag);
1572 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1573 Ops.push_back(Cond);
1574 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1575 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1576 DAG.getConstant(X86ISD::COND_A, MVT::i8),
1578 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1580 case ISD::SETUGE: { // PF | !CF
1581 Tys.push_back(MVT::i8);
1582 Tys.push_back(MVT::Flag);
1583 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1584 Ops.push_back(Cond);
1585 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1586 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1587 DAG.getConstant(X86ISD::COND_AE, MVT::i8),
1589 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1591 case ISD::SETUNE: { // PF | !ZF
1592 Tys.push_back(MVT::i8);
1593 Tys.push_back(MVT::Flag);
1594 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1595 Ops.push_back(Cond);
1596 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1597 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1598 DAG.getConstant(X86ISD::COND_NE, MVT::i8),
1600 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1606 MVT::ValueType VT = Op.getValueType();
1607 bool isFP = MVT::isFloatingPoint(VT);
1608 bool isFPStack = isFP && !X86ScalarSSE;
1609 bool isFPSSE = isFP && X86ScalarSSE;
1610 bool addTest = false;
1611 SDOperand Op0 = Op.getOperand(0);
1613 if (Op0.getOpcode() == X86ISD::SETCC) {
1614 // If condition flag is set by a X86ISD::CMP, then make a copy of it
1615 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
1616 // have another use it will be eliminated.
1617 // If the X86ISD::SETCC has more than one use, then it's probably better
1618 // to use a test instead of duplicating the X86ISD::CMP (for register
1619 // pressure reason).
1620 if (Op0.getOperand(1).getOpcode() == X86ISD::CMP) {
1621 if (!Op0.hasOneUse()) {
1622 std::vector<MVT::ValueType> Tys;
1623 for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i)
1624 Tys.push_back(Op0.Val->getValueType(i));
1625 std::vector<SDOperand> Ops;
1626 for (unsigned i = 0; i < Op0.getNumOperands(); ++i)
1627 Ops.push_back(Op0.getOperand(i));
1628 Op0 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1631 CC = Op0.getOperand(0);
1632 Cond = Op0.getOperand(1);
1633 // Make a copy as flag result cannot be used by more than one.
1634 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1635 Cond.getOperand(0), Cond.getOperand(1));
1637 isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
1640 } else if (Op0.getOpcode() == ISD::SETCC) {
1641 CC = Op0.getOperand(2);
1642 bool isFP = MVT::isFloatingPoint(Op0.getOperand(1).getValueType());
1643 unsigned X86CC = getX86CC(CC, isFP);
1644 CC = DAG.getConstant(X86CC, MVT::i8);
1645 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1646 Op0.getOperand(0), Op0.getOperand(1));
1651 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1652 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
1655 std::vector<MVT::ValueType> Tys;
1656 Tys.push_back(Op.getValueType());
1657 Tys.push_back(MVT::Flag);
1658 std::vector<SDOperand> Ops;
1659 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
1660 // condition is true.
1661 Ops.push_back(Op.getOperand(2));
1662 Ops.push_back(Op.getOperand(1));
1664 Ops.push_back(Cond);
1665 return DAG.getNode(X86ISD::CMOV, Tys, Ops);
1668 bool addTest = false;
1669 SDOperand Cond = Op.getOperand(1);
1670 SDOperand Dest = Op.getOperand(2);
1672 if (Cond.getOpcode() == X86ISD::SETCC) {
1673 // If condition flag is set by a X86ISD::CMP, then make a copy of it
1674 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
1675 // have another use it will be eliminated.
1676 // If the X86ISD::SETCC has more than one use, then it's probably better
1677 // to use a test instead of duplicating the X86ISD::CMP (for register
1678 // pressure reason).
1679 if (Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
1680 if (!Cond.hasOneUse()) {
1681 std::vector<MVT::ValueType> Tys;
1682 for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i)
1683 Tys.push_back(Cond.Val->getValueType(i));
1684 std::vector<SDOperand> Ops;
1685 for (unsigned i = 0; i < Cond.getNumOperands(); ++i)
1686 Ops.push_back(Cond.getOperand(i));
1687 Cond = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1690 CC = Cond.getOperand(0);
1691 Cond = Cond.getOperand(1);
1692 // Make a copy as flag result cannot be used by more than one.
1693 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1694 Cond.getOperand(0), Cond.getOperand(1));
1697 } else if (Cond.getOpcode() == ISD::SETCC) {
1698 CC = Cond.getOperand(2);
1699 bool isFP = MVT::isFloatingPoint(Cond.getOperand(1).getValueType());
1700 unsigned X86CC = getX86CC(CC, isFP);
1701 CC = DAG.getConstant(X86CC, MVT::i8);
1702 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1703 Cond.getOperand(0), Cond.getOperand(1));
1708 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1709 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1711 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
1712 Op.getOperand(0), Op.getOperand(2), CC, Cond);
1716 SDOperand Chain = Op.getOperand(0);
1718 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1719 if (Align == 0) Align = 1;
1723 if (ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2))) {
1725 unsigned Val = ValC->getValue() & 255;
1727 // If the value is a constant, then we can potentially use larger sets.
1728 switch (Align & 3) {
1729 case 2: // WORD aligned
1731 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1732 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1734 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1735 DAG.getConstant(1, MVT::i8));
1736 Val = (Val << 8) | Val;
1739 case 0: // DWORD aligned
1741 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1742 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1744 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1745 DAG.getConstant(2, MVT::i8));
1746 Val = (Val << 8) | Val;
1747 Val = (Val << 16) | Val;
1750 default: // Byte aligned
1752 Count = Op.getOperand(3);
1757 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
1759 InFlag = Chain.getValue(1);
1762 Count = Op.getOperand(3);
1763 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
1764 InFlag = Chain.getValue(1);
1767 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1768 InFlag = Chain.getValue(1);
1769 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1770 InFlag = Chain.getValue(1);
1772 return DAG.getNode(X86ISD::REP_STOS, MVT::Other, Chain,
1773 DAG.getValueType(AVT), InFlag);
1776 SDOperand Chain = Op.getOperand(0);
1778 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1779 if (Align == 0) Align = 1;
1783 switch (Align & 3) {
1784 case 2: // WORD aligned
1786 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1787 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1789 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1790 DAG.getConstant(1, MVT::i8));
1792 case 0: // DWORD aligned
1794 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1795 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1797 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1798 DAG.getConstant(2, MVT::i8));
1800 default: // Byte aligned
1802 Count = Op.getOperand(3);
1807 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1808 InFlag = Chain.getValue(1);
1809 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1810 InFlag = Chain.getValue(1);
1811 Chain = DAG.getCopyToReg(Chain, X86::ESI, Op.getOperand(2), InFlag);
1812 InFlag = Chain.getValue(1);
1814 return DAG.getNode(X86ISD::REP_MOVS, MVT::Other, Chain,
1815 DAG.getValueType(AVT), InFlag);
1817 case ISD::GlobalAddress: {
1819 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1820 // For Darwin, external and weak symbols are indirect, so we want to load
1821 // the value at address GV, not the value of GV itself. This means that
1822 // the GlobalAddress must be in the base or index register of the address,
1823 // not the GV offset field.
1824 if (getTargetMachine().
1825 getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() &&
1826 (GV->hasWeakLinkage() || GV->isExternal()))
1827 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(),
1828 DAG.getTargetGlobalAddress(GV, getPointerTy()),
1829 DAG.getSrcValue(NULL));
1832 case ISD::VASTART: {
1833 // vastart just stores the address of the VarArgsFrameIndex slot into the
1834 // memory location argument.
1835 // FIXME: Replace MVT::i32 with PointerTy
1836 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
1837 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
1838 Op.getOperand(1), Op.getOperand(2));
1843 switch(Op.getNumOperands()) {
1845 assert(0 && "Do not know how to return this many arguments!");
1848 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
1849 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1851 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1852 if (MVT::isInteger(ArgVT))
1853 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EAX, Op.getOperand(1),
1855 else if (!X86ScalarSSE) {
1856 std::vector<MVT::ValueType> Tys;
1857 Tys.push_back(MVT::Other);
1858 Tys.push_back(MVT::Flag);
1859 std::vector<SDOperand> Ops;
1860 Ops.push_back(Op.getOperand(0));
1861 Ops.push_back(Op.getOperand(1));
1862 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
1864 // Spill the value to memory and reload it into top of stack.
1865 unsigned Size = MVT::getSizeInBits(ArgVT)/8;
1866 MachineFunction &MF = DAG.getMachineFunction();
1867 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1868 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1869 SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0),
1870 Op.getOperand(1), StackSlot,
1871 DAG.getSrcValue(0));
1872 std::vector<MVT::ValueType> Tys;
1873 Tys.push_back(MVT::f64);
1874 Tys.push_back(MVT::Other);
1875 std::vector<SDOperand> Ops;
1876 Ops.push_back(Chain);
1877 Ops.push_back(StackSlot);
1878 Ops.push_back(DAG.getValueType(ArgVT));
1879 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
1881 Tys.push_back(MVT::Other);
1882 Tys.push_back(MVT::Flag);
1884 Ops.push_back(Copy.getValue(1));
1885 Ops.push_back(Copy);
1886 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
1891 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2),
1893 Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1));
1896 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
1897 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
1903 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1905 default: return NULL;
1906 case X86ISD::ADD_FLAG: return "X86ISD::ADD_FLAG";
1907 case X86ISD::SUB_FLAG: return "X86ISD::SUB_FLAG";
1908 case X86ISD::ADC: return "X86ISD::ADC";
1909 case X86ISD::SBB: return "X86ISD::SBB";
1910 case X86ISD::SHLD: return "X86ISD::SHLD";
1911 case X86ISD::SHRD: return "X86ISD::SHRD";
1912 case X86ISD::FILD: return "X86ISD::FILD";
1913 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
1914 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
1915 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
1916 case X86ISD::FLD: return "X86ISD::FLD";
1917 case X86ISD::FST: return "X86ISD::FST";
1918 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
1919 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
1920 case X86ISD::CALL: return "X86ISD::CALL";
1921 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
1922 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
1923 case X86ISD::CMP: return "X86ISD::CMP";
1924 case X86ISD::TEST: return "X86ISD::TEST";
1925 case X86ISD::SETCC: return "X86ISD::SETCC";
1926 case X86ISD::CMOV: return "X86ISD::CMOV";
1927 case X86ISD::BRCOND: return "X86ISD::BRCOND";
1928 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
1929 case X86ISD::REP_STOS: return "X86ISD::RET_STOS";
1930 case X86ISD::REP_MOVS: return "X86ISD::RET_MOVS";
1934 bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
1935 uint64_t Mask) const {
1937 unsigned Opc = Op.getOpcode();
1941 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
1943 case X86ISD::SETCC: return (Mask & 1) == 0;