1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86CallingConv.h"
20 #include "X86InstrBuilder.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetWindows())
193 return new X86WindowsTargetObjectFile();
194 if (Subtarget->isTargetCOFF())
195 return new TargetLoweringObjectFileCOFF();
196 llvm_unreachable("unknown subtarget type");
199 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
200 : TargetLowering(TM, createTLOF(TM)) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird, it always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit since we have so many registers use the ILP scheduler, for
234 // 32-bit code use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2
247 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
248 addBypassSlowDiv(32, 8);
249 if (Subtarget->is64Bit())
250 addBypassSlowDiv(64, 16);
253 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
254 // Setup Windows compiler runtime calls.
255 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
256 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
257 setLibcallName(RTLIB::SREM_I64, "_allrem");
258 setLibcallName(RTLIB::UREM_I64, "_aullrem");
259 setLibcallName(RTLIB::MUL_I64, "_allmul");
260 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
266 // The _ftol2 runtime function has an unusual calling conv, which
267 // is modeled by a special pseudo-instruction.
268 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
270 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
271 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
274 if (Subtarget->isTargetDarwin()) {
275 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
276 setUseUnderscoreSetJmp(false);
277 setUseUnderscoreLongJmp(false);
278 } else if (Subtarget->isTargetMingw()) {
279 // MS runtime is weird: it exports _setjmp, but longjmp!
280 setUseUnderscoreSetJmp(true);
281 setUseUnderscoreLongJmp(false);
283 setUseUnderscoreSetJmp(true);
284 setUseUnderscoreLongJmp(true);
287 // Set up the register classes.
288 addRegisterClass(MVT::i8, &X86::GR8RegClass);
289 addRegisterClass(MVT::i16, &X86::GR16RegClass);
290 addRegisterClass(MVT::i32, &X86::GR32RegClass);
291 if (Subtarget->is64Bit())
292 addRegisterClass(MVT::i64, &X86::GR64RegClass);
294 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
296 // We don't accept any truncstore of integer registers.
297 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
298 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
301 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
302 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
304 // SETOEQ and SETUNE require checking two conditions.
305 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
312 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
314 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
315 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
316 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
318 if (Subtarget->is64Bit()) {
319 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
320 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
321 } else if (!TM.Options.UseSoftFloat) {
322 // We have an algorithm for SSE2->double, and we turn this into a
323 // 64-bit FILD followed by conditional FADD for other targets.
324 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
325 // We have an algorithm for SSE2, and we turn this into a 64-bit
326 // FILD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
330 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
332 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
333 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
335 if (!TM.Options.UseSoftFloat) {
336 // SSE has no i16 to fp conversion, only i32
337 if (X86ScalarSSEf32) {
338 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
339 // f32 and f64 cases are Legal, f80 case is not
340 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
342 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
347 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
350 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
351 // are Legal, f80 is custom lowered.
352 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
355 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
357 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
358 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
360 if (X86ScalarSSEf32) {
361 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
362 // f32 and f64 cases are Legal, f80 case is not
363 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
369 // Handle FP_TO_UINT by promoting the destination to a larger signed
371 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
372 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
373 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
375 if (Subtarget->is64Bit()) {
376 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
377 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
378 } else if (!TM.Options.UseSoftFloat) {
379 // Since AVX is a superset of SSE3, only check for SSE here.
380 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
381 // Expand FP_TO_UINT into a select.
382 // FIXME: We would like to use a Custom expander here eventually to do
383 // the optimal thing for SSE vs. the default expansion in the legalizer.
384 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
386 // With SSE3 we can use fisttpll to convert to a signed i64; without
387 // SSE, we're stuck with a fistpll.
388 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
391 if (isTargetFTOL()) {
392 // Use the _ftol2 runtime function, which has a pseudo-instruction
393 // to handle its weird calling convention.
394 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
397 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
398 if (!X86ScalarSSEf64) {
399 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
400 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
401 if (Subtarget->is64Bit()) {
402 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
403 // Without SSE, i64->f64 goes through memory.
404 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
408 // Scalar integer divide and remainder are lowered to use operations that
409 // produce two results, to match the available instructions. This exposes
410 // the two-result form to trivial CSE, which is able to combine x/y and x%y
411 // into a single instruction.
413 // Scalar integer multiply-high is also lowered to use two-result
414 // operations, to match the available instructions. However, plain multiply
415 // (low) operations are left as Legal, as there are single-result
416 // instructions for this in x86. Using the two-result multiply instructions
417 // when both high and low results are needed must be arranged by dagcombine.
418 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
420 setOperationAction(ISD::MULHS, VT, Expand);
421 setOperationAction(ISD::MULHU, VT, Expand);
422 setOperationAction(ISD::SDIV, VT, Expand);
423 setOperationAction(ISD::UDIV, VT, Expand);
424 setOperationAction(ISD::SREM, VT, Expand);
425 setOperationAction(ISD::UREM, VT, Expand);
427 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
428 setOperationAction(ISD::ADDC, VT, Custom);
429 setOperationAction(ISD::ADDE, VT, Custom);
430 setOperationAction(ISD::SUBC, VT, Custom);
431 setOperationAction(ISD::SUBE, VT, Custom);
434 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
435 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
436 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
437 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
438 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
441 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
443 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
444 if (Subtarget->is64Bit())
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
448 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
449 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
450 setOperationAction(ISD::FREM , MVT::f32 , Expand);
451 setOperationAction(ISD::FREM , MVT::f64 , Expand);
452 setOperationAction(ISD::FREM , MVT::f80 , Expand);
453 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
455 // Promote the i8 variants and force them on up to i32 which has a shorter
457 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
459 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
460 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
461 if (Subtarget->hasBMI()) {
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
464 if (Subtarget->is64Bit())
465 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
467 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
468 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
473 if (Subtarget->hasLZCNT()) {
474 // When promoting the i8 variants, force them to i32 for a shorter
476 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
482 if (Subtarget->is64Bit())
483 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
485 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
486 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
487 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
491 if (Subtarget->is64Bit()) {
492 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
497 if (Subtarget->hasPOPCNT()) {
498 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
500 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
501 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
502 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
507 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
508 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
510 // These should be promoted to a larger select which is supported.
511 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
512 // X86 wants to expand cmov itself.
513 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
514 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
515 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
517 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
518 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
520 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
521 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
523 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
524 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
525 if (Subtarget->is64Bit()) {
526 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
527 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
529 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
530 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
531 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
532 // support continuation, user-level threading, and etc.. As a result, no
533 // other SjLj exception interfaces are implemented and please don't build
534 // your own exception handling based on them.
535 // LLVM/Clang supports zero-cost DWARF exception handling.
536 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
537 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
540 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
541 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
542 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
544 if (Subtarget->is64Bit())
545 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
546 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
547 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
548 if (Subtarget->is64Bit()) {
549 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
550 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
551 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
552 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
553 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
555 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
556 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
557 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
558 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
559 if (Subtarget->is64Bit()) {
560 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
561 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
562 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
565 if (Subtarget->hasSSE1())
566 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
568 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
570 // Expand certain atomics
571 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
573 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
574 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
575 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
578 if (!Subtarget->is64Bit()) {
579 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
590 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
593 if (Subtarget->hasCmpxchg16b()) {
594 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
597 // FIXME - use subtarget debug flags
598 if (!Subtarget->isTargetDarwin() &&
599 !Subtarget->isTargetELF() &&
600 !Subtarget->isTargetCygMing()) {
601 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
604 if (Subtarget->is64Bit()) {
605 setExceptionPointerRegister(X86::RAX);
606 setExceptionSelectorRegister(X86::RDX);
608 setExceptionPointerRegister(X86::EAX);
609 setExceptionSelectorRegister(X86::EDX);
611 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
612 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
614 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
617 setOperationAction(ISD::TRAP, MVT::Other, Legal);
618 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
620 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
621 setOperationAction(ISD::VASTART , MVT::Other, Custom);
622 setOperationAction(ISD::VAEND , MVT::Other, Expand);
623 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
624 // TargetInfo::X86_64ABIBuiltinVaList
625 setOperationAction(ISD::VAARG , MVT::Other, Custom);
626 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
628 // TargetInfo::CharPtrBuiltinVaList
629 setOperationAction(ISD::VAARG , MVT::Other, Expand);
630 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
633 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
634 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
636 if (Subtarget->isOSWindows() && !Subtarget->isTargetMacho())
637 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
638 MVT::i64 : MVT::i32, Custom);
639 else if (TM.Options.EnableSegmentedStacks)
640 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
641 MVT::i64 : MVT::i32, Custom);
643 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
644 MVT::i64 : MVT::i32, Expand);
646 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
647 // f32 and f64 use SSE.
648 // Set up the FP register classes.
649 addRegisterClass(MVT::f32, &X86::FR32RegClass);
650 addRegisterClass(MVT::f64, &X86::FR64RegClass);
652 // Use ANDPD to simulate FABS.
653 setOperationAction(ISD::FABS , MVT::f64, Custom);
654 setOperationAction(ISD::FABS , MVT::f32, Custom);
656 // Use XORP to simulate FNEG.
657 setOperationAction(ISD::FNEG , MVT::f64, Custom);
658 setOperationAction(ISD::FNEG , MVT::f32, Custom);
660 // Use ANDPD and ORPD to simulate FCOPYSIGN.
661 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
662 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
664 // Lower this to FGETSIGNx86 plus an AND.
665 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
666 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
668 // We don't support sin/cos/fmod
669 setOperationAction(ISD::FSIN , MVT::f64, Expand);
670 setOperationAction(ISD::FCOS , MVT::f64, Expand);
671 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
672 setOperationAction(ISD::FSIN , MVT::f32, Expand);
673 setOperationAction(ISD::FCOS , MVT::f32, Expand);
674 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
676 // Expand FP immediates into loads from the stack, except for the special
678 addLegalFPImmediate(APFloat(+0.0)); // xorpd
679 addLegalFPImmediate(APFloat(+0.0f)); // xorps
680 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
681 // Use SSE for f32, x87 for f64.
682 // Set up the FP register classes.
683 addRegisterClass(MVT::f32, &X86::FR32RegClass);
684 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
686 // Use ANDPS to simulate FABS.
687 setOperationAction(ISD::FABS , MVT::f32, Custom);
689 // Use XORP to simulate FNEG.
690 setOperationAction(ISD::FNEG , MVT::f32, Custom);
692 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
694 // Use ANDPS and ORPS to simulate FCOPYSIGN.
695 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
696 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
698 // We don't support sin/cos/fmod
699 setOperationAction(ISD::FSIN , MVT::f32, Expand);
700 setOperationAction(ISD::FCOS , MVT::f32, Expand);
701 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
703 // Special cases we handle for FP constants.
704 addLegalFPImmediate(APFloat(+0.0f)); // xorps
705 addLegalFPImmediate(APFloat(+0.0)); // FLD0
706 addLegalFPImmediate(APFloat(+1.0)); // FLD1
707 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
708 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
710 if (!TM.Options.UnsafeFPMath) {
711 setOperationAction(ISD::FSIN , MVT::f64, Expand);
712 setOperationAction(ISD::FCOS , MVT::f64, Expand);
713 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
715 } else if (!TM.Options.UseSoftFloat) {
716 // f32 and f64 in x87.
717 // Set up the FP register classes.
718 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
719 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
721 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
722 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
723 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
724 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
726 if (!TM.Options.UnsafeFPMath) {
727 setOperationAction(ISD::FSIN , MVT::f64, Expand);
728 setOperationAction(ISD::FSIN , MVT::f32, Expand);
729 setOperationAction(ISD::FCOS , MVT::f64, Expand);
730 setOperationAction(ISD::FCOS , MVT::f32, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
732 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
734 addLegalFPImmediate(APFloat(+0.0)); // FLD0
735 addLegalFPImmediate(APFloat(+1.0)); // FLD1
736 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
737 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
738 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
739 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
740 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
741 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
744 // We don't support FMA.
745 setOperationAction(ISD::FMA, MVT::f64, Expand);
746 setOperationAction(ISD::FMA, MVT::f32, Expand);
748 // Long double always uses X87.
749 if (!TM.Options.UseSoftFloat) {
750 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
751 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
752 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
754 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
755 addLegalFPImmediate(TmpFlt); // FLD0
757 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
760 APFloat TmpFlt2(+1.0);
761 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
763 addLegalFPImmediate(TmpFlt2); // FLD1
764 TmpFlt2.changeSign();
765 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
768 if (!TM.Options.UnsafeFPMath) {
769 setOperationAction(ISD::FSIN , MVT::f80, Expand);
770 setOperationAction(ISD::FCOS , MVT::f80, Expand);
771 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
774 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
775 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
776 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
777 setOperationAction(ISD::FRINT, MVT::f80, Expand);
778 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
779 setOperationAction(ISD::FMA, MVT::f80, Expand);
782 // Always use a library call for pow.
783 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
784 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
785 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
787 setOperationAction(ISD::FLOG, MVT::f80, Expand);
788 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
789 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
790 setOperationAction(ISD::FEXP, MVT::f80, Expand);
791 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
793 // First set operation action for all vector types to either promote
794 // (for widening) or expand (for scalarization). Then we will selectively
795 // turn on ones that can be effectively codegen'd.
796 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
797 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
798 MVT VT = (MVT::SimpleValueType)i;
799 setOperationAction(ISD::ADD , VT, Expand);
800 setOperationAction(ISD::SUB , VT, Expand);
801 setOperationAction(ISD::FADD, VT, Expand);
802 setOperationAction(ISD::FNEG, VT, Expand);
803 setOperationAction(ISD::FSUB, VT, Expand);
804 setOperationAction(ISD::MUL , VT, Expand);
805 setOperationAction(ISD::FMUL, VT, Expand);
806 setOperationAction(ISD::SDIV, VT, Expand);
807 setOperationAction(ISD::UDIV, VT, Expand);
808 setOperationAction(ISD::FDIV, VT, Expand);
809 setOperationAction(ISD::SREM, VT, Expand);
810 setOperationAction(ISD::UREM, VT, Expand);
811 setOperationAction(ISD::LOAD, VT, Expand);
812 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
813 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
814 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
815 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
816 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
817 setOperationAction(ISD::FABS, VT, Expand);
818 setOperationAction(ISD::FSIN, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FCOS, VT, Expand);
821 setOperationAction(ISD::FSINCOS, VT, Expand);
822 setOperationAction(ISD::FREM, VT, Expand);
823 setOperationAction(ISD::FMA, VT, Expand);
824 setOperationAction(ISD::FPOWI, VT, Expand);
825 setOperationAction(ISD::FSQRT, VT, Expand);
826 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
827 setOperationAction(ISD::FFLOOR, VT, Expand);
828 setOperationAction(ISD::FCEIL, VT, Expand);
829 setOperationAction(ISD::FTRUNC, VT, Expand);
830 setOperationAction(ISD::FRINT, VT, Expand);
831 setOperationAction(ISD::FNEARBYINT, VT, Expand);
832 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
834 setOperationAction(ISD::SDIVREM, VT, Expand);
835 setOperationAction(ISD::UDIVREM, VT, Expand);
836 setOperationAction(ISD::FPOW, VT, Expand);
837 setOperationAction(ISD::CTPOP, VT, Expand);
838 setOperationAction(ISD::CTTZ, VT, Expand);
839 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::CTLZ, VT, Expand);
841 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
842 setOperationAction(ISD::SHL, VT, Expand);
843 setOperationAction(ISD::SRA, VT, Expand);
844 setOperationAction(ISD::SRL, VT, Expand);
845 setOperationAction(ISD::ROTL, VT, Expand);
846 setOperationAction(ISD::ROTR, VT, Expand);
847 setOperationAction(ISD::BSWAP, VT, Expand);
848 setOperationAction(ISD::SETCC, VT, Expand);
849 setOperationAction(ISD::FLOG, VT, Expand);
850 setOperationAction(ISD::FLOG2, VT, Expand);
851 setOperationAction(ISD::FLOG10, VT, Expand);
852 setOperationAction(ISD::FEXP, VT, Expand);
853 setOperationAction(ISD::FEXP2, VT, Expand);
854 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
855 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
856 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
859 setOperationAction(ISD::TRUNCATE, VT, Expand);
860 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
861 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
862 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
863 setOperationAction(ISD::VSELECT, VT, Expand);
864 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
865 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
866 setTruncStoreAction(VT,
867 (MVT::SimpleValueType)InnerVT, Expand);
868 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
870 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
873 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
874 // with -msoft-float, disable use of MMX as well.
875 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
876 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
877 // No operations on x86mmx supported, everything uses intrinsics.
880 // MMX-sized vectors (other than x86mmx) are expected to be expanded
881 // into smaller operations.
882 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
883 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
884 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
885 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
886 setOperationAction(ISD::AND, MVT::v8i8, Expand);
887 setOperationAction(ISD::AND, MVT::v4i16, Expand);
888 setOperationAction(ISD::AND, MVT::v2i32, Expand);
889 setOperationAction(ISD::AND, MVT::v1i64, Expand);
890 setOperationAction(ISD::OR, MVT::v8i8, Expand);
891 setOperationAction(ISD::OR, MVT::v4i16, Expand);
892 setOperationAction(ISD::OR, MVT::v2i32, Expand);
893 setOperationAction(ISD::OR, MVT::v1i64, Expand);
894 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
895 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
896 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
897 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
901 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
903 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
904 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
905 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
906 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
910 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
912 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
913 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
915 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
916 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
917 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
918 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
919 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
920 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
921 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
922 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
923 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
924 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
925 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
926 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
929 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
930 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
932 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
933 // registers cannot be used even for integer operations.
934 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
935 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
936 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
937 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
939 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
940 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
941 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
942 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
943 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
944 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
945 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
946 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
947 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
948 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
949 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
950 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
951 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
952 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
953 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
954 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
955 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
956 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
958 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
959 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
960 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
961 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
964 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
969 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
970 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
971 MVT VT = (MVT::SimpleValueType)i;
972 // Do not attempt to custom lower non-power-of-2 vectors
973 if (!isPowerOf2_32(VT.getVectorNumElements()))
975 // Do not attempt to custom lower non-128-bit vectors
976 if (!VT.is128BitVector())
978 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
979 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
980 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
983 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
984 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
986 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
988 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
990 if (Subtarget->is64Bit()) {
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
995 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
996 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
997 MVT VT = (MVT::SimpleValueType)i;
999 // Do not attempt to promote non-128-bit vectors
1000 if (!VT.is128BitVector())
1003 setOperationAction(ISD::AND, VT, Promote);
1004 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1005 setOperationAction(ISD::OR, VT, Promote);
1006 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1007 setOperationAction(ISD::XOR, VT, Promote);
1008 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1009 setOperationAction(ISD::LOAD, VT, Promote);
1010 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1011 setOperationAction(ISD::SELECT, VT, Promote);
1012 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1015 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1017 // Custom lower v2i64 and v2f64 selects.
1018 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1019 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1020 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1021 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1024 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1026 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1027 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1028 // As there is no 64-bit GPR available, we need build a special custom
1029 // sequence to convert from v2i32 to v2f32.
1030 if (!Subtarget->is64Bit())
1031 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1033 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1034 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1036 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1039 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1040 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1041 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1042 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1043 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1044 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1045 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1046 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1047 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1048 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1051 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1055 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1056 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1059 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1060 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1062 // FIXME: Do we need to handle scalar-to-vector here?
1063 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1069 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1071 // i8 and i16 vectors are custom , because the source register and source
1072 // source memory operand types are not the same width. f32 vectors are
1073 // custom since the immediate controlling the insert encodes additional
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1077 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1078 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1082 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1083 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1085 // FIXME: these should be Legal but thats only for the case where
1086 // the index is constant. For now custom expand to deal with that.
1087 if (Subtarget->is64Bit()) {
1088 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1089 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1093 if (Subtarget->hasSSE2()) {
1094 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1095 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1097 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1098 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1100 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1101 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1103 // In the customized shift lowering, the legal cases in AVX2 will be
1105 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1106 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1108 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1109 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1113 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1114 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1117 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1118 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1122 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1123 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1125 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1126 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1127 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1129 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1139 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1142 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1152 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1153 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1155 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1157 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1158 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1160 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1163 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1165 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1167 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1168 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1170 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1171 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1173 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1174 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1176 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1184 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1187 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1189 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1190 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1193 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1200 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1202 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1203 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1205 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1206 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1209 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1210 setOperationAction(ISD::FMA, MVT::f32, Legal);
1211 setOperationAction(ISD::FMA, MVT::f64, Legal);
1214 if (Subtarget->hasInt256()) {
1215 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1216 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1217 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1218 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1220 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1221 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1222 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1223 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1225 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1226 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1227 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1228 // Don't lower v32i8 because there is no 128-bit byte mul
1230 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1232 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1234 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1235 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1236 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1237 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1239 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1241 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1242 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1244 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1245 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1246 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1247 // Don't lower v32i8 because there is no 128-bit byte mul
1250 // In the customized shift lowering, the legal cases in AVX2 will be
1252 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1253 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1255 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1256 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1258 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1260 // Custom lower several nodes for 256-bit types.
1261 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1262 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1263 MVT VT = (MVT::SimpleValueType)i;
1265 // Extract subvector is special because the value type
1266 // (result) is 128-bit but the source is 256-bit wide.
1267 if (VT.is128BitVector())
1268 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1270 // Do not attempt to custom lower other non-256-bit vectors
1271 if (!VT.is256BitVector())
1274 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1275 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1276 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1277 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1278 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1279 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1280 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1283 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1284 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1285 MVT VT = (MVT::SimpleValueType)i;
1287 // Do not attempt to promote non-256-bit vectors
1288 if (!VT.is256BitVector())
1291 setOperationAction(ISD::AND, VT, Promote);
1292 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1293 setOperationAction(ISD::OR, VT, Promote);
1294 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1295 setOperationAction(ISD::XOR, VT, Promote);
1296 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1297 setOperationAction(ISD::LOAD, VT, Promote);
1298 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1299 setOperationAction(ISD::SELECT, VT, Promote);
1300 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1304 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1305 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1308 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1310 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1311 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1312 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1314 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1315 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1316 setOperationAction(ISD::XOR, MVT::i1, Legal);
1317 setOperationAction(ISD::OR, MVT::i1, Legal);
1318 setOperationAction(ISD::AND, MVT::i1, Legal);
1319 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1320 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1321 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1322 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1323 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1324 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1326 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1328 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1329 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1330 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1331 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1333 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1334 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1335 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1336 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1337 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1338 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1339 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1340 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1341 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1343 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1344 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1345 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1346 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1347 if (Subtarget->is64Bit()) {
1348 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1349 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1350 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1351 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1353 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1355 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1356 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1357 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1359 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1360 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1362 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1363 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1364 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1365 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1366 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1367 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1368 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1369 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1370 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1371 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1372 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1373 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1374 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1376 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1377 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1378 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1379 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1380 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1381 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1383 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1384 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1386 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1388 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1390 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1391 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1392 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1393 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1396 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1397 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1399 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1400 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1402 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1404 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1405 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1407 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1408 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1410 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1411 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1413 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1414 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1415 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1416 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1417 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1418 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1420 // Custom lower several nodes.
1421 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1422 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1423 MVT VT = (MVT::SimpleValueType)i;
1425 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1426 // Extract subvector is special because the value type
1427 // (result) is 256/128-bit but the source is 512-bit wide.
1428 if (VT.is128BitVector() || VT.is256BitVector())
1429 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1431 if (VT.getVectorElementType() == MVT::i1)
1432 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1434 // Do not attempt to custom lower other non-512-bit vectors
1435 if (!VT.is512BitVector())
1438 if ( EltSize >= 32) {
1439 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1440 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1441 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1442 setOperationAction(ISD::VSELECT, VT, Legal);
1443 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1444 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1445 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1448 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1449 MVT VT = (MVT::SimpleValueType)i;
1451 // Do not attempt to promote non-256-bit vectors
1452 if (!VT.is512BitVector())
1455 setOperationAction(ISD::SELECT, VT, Promote);
1456 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1460 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1461 // of this type with custom code.
1462 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1463 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1464 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1468 // We want to custom lower some of our intrinsics.
1469 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1470 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1471 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1473 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1474 // handle type legalization for these operations here.
1476 // FIXME: We really should do custom legalization for addition and
1477 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1478 // than generic legalization for 64-bit multiplication-with-overflow, though.
1479 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1480 // Add/Sub/Mul with overflow operations are custom lowered.
1482 setOperationAction(ISD::SADDO, VT, Custom);
1483 setOperationAction(ISD::UADDO, VT, Custom);
1484 setOperationAction(ISD::SSUBO, VT, Custom);
1485 setOperationAction(ISD::USUBO, VT, Custom);
1486 setOperationAction(ISD::SMULO, VT, Custom);
1487 setOperationAction(ISD::UMULO, VT, Custom);
1490 // There are no 8-bit 3-address imul/mul instructions
1491 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1492 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1494 if (!Subtarget->is64Bit()) {
1495 // These libcalls are not available in 32-bit.
1496 setLibcallName(RTLIB::SHL_I128, 0);
1497 setLibcallName(RTLIB::SRL_I128, 0);
1498 setLibcallName(RTLIB::SRA_I128, 0);
1501 // Combine sin / cos into one node or libcall if possible.
1502 if (Subtarget->hasSinCos()) {
1503 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1504 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1505 if (Subtarget->isTargetDarwin()) {
1506 // For MacOSX, we don't want to the normal expansion of a libcall to
1507 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1509 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1510 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1514 // We have target-specific dag combine patterns for the following nodes:
1515 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1516 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1517 setTargetDAGCombine(ISD::VSELECT);
1518 setTargetDAGCombine(ISD::SELECT);
1519 setTargetDAGCombine(ISD::SHL);
1520 setTargetDAGCombine(ISD::SRA);
1521 setTargetDAGCombine(ISD::SRL);
1522 setTargetDAGCombine(ISD::OR);
1523 setTargetDAGCombine(ISD::AND);
1524 setTargetDAGCombine(ISD::ADD);
1525 setTargetDAGCombine(ISD::FADD);
1526 setTargetDAGCombine(ISD::FSUB);
1527 setTargetDAGCombine(ISD::FMA);
1528 setTargetDAGCombine(ISD::SUB);
1529 setTargetDAGCombine(ISD::LOAD);
1530 setTargetDAGCombine(ISD::STORE);
1531 setTargetDAGCombine(ISD::ZERO_EXTEND);
1532 setTargetDAGCombine(ISD::ANY_EXTEND);
1533 setTargetDAGCombine(ISD::SIGN_EXTEND);
1534 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1535 setTargetDAGCombine(ISD::TRUNCATE);
1536 setTargetDAGCombine(ISD::SINT_TO_FP);
1537 setTargetDAGCombine(ISD::SETCC);
1538 if (Subtarget->is64Bit())
1539 setTargetDAGCombine(ISD::MUL);
1540 setTargetDAGCombine(ISD::XOR);
1542 computeRegisterProperties();
1544 // On Darwin, -Os means optimize for size without hurting performance,
1545 // do not reduce the limit.
1546 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1547 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1548 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1549 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1550 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1551 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1552 setPrefLoopAlignment(4); // 2^4 bytes.
1554 // Predictable cmov don't hurt on atom because it's in-order.
1555 PredictableSelectIsExpensive = !Subtarget->isAtom();
1557 setPrefFunctionAlignment(4); // 2^4 bytes.
1560 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1562 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1564 if (Subtarget->hasAVX512())
1565 switch(VT.getVectorNumElements()) {
1566 case 8: return MVT::v8i1;
1567 case 16: return MVT::v16i1;
1570 return VT.changeVectorElementTypeToInteger();
1573 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1574 /// the desired ByVal argument alignment.
1575 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1578 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1579 if (VTy->getBitWidth() == 128)
1581 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1582 unsigned EltAlign = 0;
1583 getMaxByValAlign(ATy->getElementType(), EltAlign);
1584 if (EltAlign > MaxAlign)
1585 MaxAlign = EltAlign;
1586 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1587 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1588 unsigned EltAlign = 0;
1589 getMaxByValAlign(STy->getElementType(i), EltAlign);
1590 if (EltAlign > MaxAlign)
1591 MaxAlign = EltAlign;
1598 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1599 /// function arguments in the caller parameter area. For X86, aggregates
1600 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1601 /// are at 4-byte boundaries.
1602 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1603 if (Subtarget->is64Bit()) {
1604 // Max of 8 and alignment of type.
1605 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1612 if (Subtarget->hasSSE1())
1613 getMaxByValAlign(Ty, Align);
1617 /// getOptimalMemOpType - Returns the target specific optimal type for load
1618 /// and store operations as a result of memset, memcpy, and memmove
1619 /// lowering. If DstAlign is zero that means it's safe to destination
1620 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1621 /// means there isn't a need to check it against alignment requirement,
1622 /// probably because the source does not need to be loaded. If 'IsMemset' is
1623 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1624 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1625 /// source is constant so it does not need to be loaded.
1626 /// It returns EVT::Other if the type should be determined using generic
1627 /// target-independent logic.
1629 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1630 unsigned DstAlign, unsigned SrcAlign,
1631 bool IsMemset, bool ZeroMemset,
1633 MachineFunction &MF) const {
1634 const Function *F = MF.getFunction();
1635 if ((!IsMemset || ZeroMemset) &&
1636 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1637 Attribute::NoImplicitFloat)) {
1639 (Subtarget->isUnalignedMemAccessFast() ||
1640 ((DstAlign == 0 || DstAlign >= 16) &&
1641 (SrcAlign == 0 || SrcAlign >= 16)))) {
1643 if (Subtarget->hasInt256())
1645 if (Subtarget->hasFp256())
1648 if (Subtarget->hasSSE2())
1650 if (Subtarget->hasSSE1())
1652 } else if (!MemcpyStrSrc && Size >= 8 &&
1653 !Subtarget->is64Bit() &&
1654 Subtarget->hasSSE2()) {
1655 // Do not use f64 to lower memcpy if source is string constant. It's
1656 // better to use i32 to avoid the loads.
1660 if (Subtarget->is64Bit() && Size >= 8)
1665 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1667 return X86ScalarSSEf32;
1668 else if (VT == MVT::f64)
1669 return X86ScalarSSEf64;
1674 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
1678 *Fast = Subtarget->isUnalignedMemAccessFast();
1682 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1683 /// current function. The returned value is a member of the
1684 /// MachineJumpTableInfo::JTEntryKind enum.
1685 unsigned X86TargetLowering::getJumpTableEncoding() const {
1686 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1688 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1689 Subtarget->isPICStyleGOT())
1690 return MachineJumpTableInfo::EK_Custom32;
1692 // Otherwise, use the normal jump table encoding heuristics.
1693 return TargetLowering::getJumpTableEncoding();
1697 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1698 const MachineBasicBlock *MBB,
1699 unsigned uid,MCContext &Ctx) const{
1700 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1701 Subtarget->isPICStyleGOT());
1702 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1704 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1705 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1708 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1710 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1711 SelectionDAG &DAG) const {
1712 if (!Subtarget->is64Bit())
1713 // This doesn't have SDLoc associated with it, but is not really the
1714 // same as a Register.
1715 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1719 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1720 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1722 const MCExpr *X86TargetLowering::
1723 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1724 MCContext &Ctx) const {
1725 // X86-64 uses RIP relative addressing based on the jump table label.
1726 if (Subtarget->isPICStyleRIPRel())
1727 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1729 // Otherwise, the reference is relative to the PIC base.
1730 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1733 // FIXME: Why this routine is here? Move to RegInfo!
1734 std::pair<const TargetRegisterClass*, uint8_t>
1735 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1736 const TargetRegisterClass *RRC = 0;
1738 switch (VT.SimpleTy) {
1740 return TargetLowering::findRepresentativeClass(VT);
1741 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1742 RRC = Subtarget->is64Bit() ?
1743 (const TargetRegisterClass*)&X86::GR64RegClass :
1744 (const TargetRegisterClass*)&X86::GR32RegClass;
1747 RRC = &X86::VR64RegClass;
1749 case MVT::f32: case MVT::f64:
1750 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1751 case MVT::v4f32: case MVT::v2f64:
1752 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1754 RRC = &X86::VR128RegClass;
1757 return std::make_pair(RRC, Cost);
1760 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1761 unsigned &Offset) const {
1762 if (!Subtarget->isTargetLinux())
1765 if (Subtarget->is64Bit()) {
1766 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1768 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1780 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1781 unsigned DestAS) const {
1782 assert(SrcAS != DestAS && "Expected different address spaces!");
1784 return SrcAS < 256 && DestAS < 256;
1787 //===----------------------------------------------------------------------===//
1788 // Return Value Calling Convention Implementation
1789 //===----------------------------------------------------------------------===//
1791 #include "X86GenCallingConv.inc"
1794 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1795 MachineFunction &MF, bool isVarArg,
1796 const SmallVectorImpl<ISD::OutputArg> &Outs,
1797 LLVMContext &Context) const {
1798 SmallVector<CCValAssign, 16> RVLocs;
1799 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1801 return CCInfo.CheckReturn(Outs, RetCC_X86);
1804 const uint16_t *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1805 static const uint16_t ScratchRegs[] = { X86::R11, 0 };
1810 X86TargetLowering::LowerReturn(SDValue Chain,
1811 CallingConv::ID CallConv, bool isVarArg,
1812 const SmallVectorImpl<ISD::OutputArg> &Outs,
1813 const SmallVectorImpl<SDValue> &OutVals,
1814 SDLoc dl, SelectionDAG &DAG) const {
1815 MachineFunction &MF = DAG.getMachineFunction();
1816 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1818 SmallVector<CCValAssign, 16> RVLocs;
1819 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1820 RVLocs, *DAG.getContext());
1821 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1824 SmallVector<SDValue, 6> RetOps;
1825 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1826 // Operand #1 = Bytes To Pop
1827 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1830 // Copy the result values into the output registers.
1831 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1832 CCValAssign &VA = RVLocs[i];
1833 assert(VA.isRegLoc() && "Can only return in registers!");
1834 SDValue ValToCopy = OutVals[i];
1835 EVT ValVT = ValToCopy.getValueType();
1837 // Promote values to the appropriate types
1838 if (VA.getLocInfo() == CCValAssign::SExt)
1839 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1840 else if (VA.getLocInfo() == CCValAssign::ZExt)
1841 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1842 else if (VA.getLocInfo() == CCValAssign::AExt)
1843 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1844 else if (VA.getLocInfo() == CCValAssign::BCvt)
1845 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1847 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1848 "Unexpected FP-extend for return value.");
1850 // If this is x86-64, and we disabled SSE, we can't return FP values,
1851 // or SSE or MMX vectors.
1852 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1853 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1854 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1855 report_fatal_error("SSE register return with SSE disabled");
1857 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1858 // llvm-gcc has never done it right and no one has noticed, so this
1859 // should be OK for now.
1860 if (ValVT == MVT::f64 &&
1861 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1862 report_fatal_error("SSE2 register return with SSE2 disabled");
1864 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1865 // the RET instruction and handled by the FP Stackifier.
1866 if (VA.getLocReg() == X86::ST0 ||
1867 VA.getLocReg() == X86::ST1) {
1868 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1869 // change the value to the FP stack register class.
1870 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1871 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1872 RetOps.push_back(ValToCopy);
1873 // Don't emit a copytoreg.
1877 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1878 // which is returned in RAX / RDX.
1879 if (Subtarget->is64Bit()) {
1880 if (ValVT == MVT::x86mmx) {
1881 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1882 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1883 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1885 // If we don't have SSE2 available, convert to v4f32 so the generated
1886 // register is legal.
1887 if (!Subtarget->hasSSE2())
1888 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1893 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1894 Flag = Chain.getValue(1);
1895 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1898 // The x86-64 ABIs require that for returning structs by value we copy
1899 // the sret argument into %rax/%eax (depending on ABI) for the return.
1900 // Win32 requires us to put the sret argument to %eax as well.
1901 // We saved the argument into a virtual register in the entry block,
1902 // so now we copy the value out and into %rax/%eax.
1903 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1904 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1905 MachineFunction &MF = DAG.getMachineFunction();
1906 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1907 unsigned Reg = FuncInfo->getSRetReturnReg();
1909 "SRetReturnReg should have been set in LowerFormalArguments().");
1910 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1913 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1914 X86::RAX : X86::EAX;
1915 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1916 Flag = Chain.getValue(1);
1918 // RAX/EAX now acts like a return value.
1919 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1922 RetOps[0] = Chain; // Update chain.
1924 // Add the flag if we have it.
1926 RetOps.push_back(Flag);
1928 return DAG.getNode(X86ISD::RET_FLAG, dl,
1929 MVT::Other, &RetOps[0], RetOps.size());
1932 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1933 if (N->getNumValues() != 1)
1935 if (!N->hasNUsesOfValue(1, 0))
1938 SDValue TCChain = Chain;
1939 SDNode *Copy = *N->use_begin();
1940 if (Copy->getOpcode() == ISD::CopyToReg) {
1941 // If the copy has a glue operand, we conservatively assume it isn't safe to
1942 // perform a tail call.
1943 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1945 TCChain = Copy->getOperand(0);
1946 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1949 bool HasRet = false;
1950 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1952 if (UI->getOpcode() != X86ISD::RET_FLAG)
1965 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1966 ISD::NodeType ExtendKind) const {
1968 // TODO: Is this also valid on 32-bit?
1969 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1970 ReturnMVT = MVT::i8;
1972 ReturnMVT = MVT::i32;
1974 MVT MinVT = getRegisterType(ReturnMVT);
1975 return VT.bitsLT(MinVT) ? MinVT : VT;
1978 /// LowerCallResult - Lower the result values of a call into the
1979 /// appropriate copies out of appropriate physical registers.
1982 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1983 CallingConv::ID CallConv, bool isVarArg,
1984 const SmallVectorImpl<ISD::InputArg> &Ins,
1985 SDLoc dl, SelectionDAG &DAG,
1986 SmallVectorImpl<SDValue> &InVals) const {
1988 // Assign locations to each value returned by this call.
1989 SmallVector<CCValAssign, 16> RVLocs;
1990 bool Is64Bit = Subtarget->is64Bit();
1991 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1992 getTargetMachine(), RVLocs, *DAG.getContext());
1993 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1995 // Copy all of the result registers out of their specified physreg.
1996 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1997 CCValAssign &VA = RVLocs[i];
1998 EVT CopyVT = VA.getValVT();
2000 // If this is x86-64, and we disabled SSE, we can't return FP values
2001 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2002 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2003 report_fatal_error("SSE register return with SSE disabled");
2008 // If this is a call to a function that returns an fp value on the floating
2009 // point stack, we must guarantee the value is popped from the stack, so
2010 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2011 // if the return value is not used. We use the FpPOP_RETVAL instruction
2013 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2014 // If we prefer to use the value in xmm registers, copy it out as f80 and
2015 // use a truncate to move it from fp stack reg to xmm reg.
2016 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2017 SDValue Ops[] = { Chain, InFlag };
2018 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2019 MVT::Other, MVT::Glue, Ops), 1);
2020 Val = Chain.getValue(0);
2022 // Round the f80 to the right size, which also moves it to the appropriate
2024 if (CopyVT != VA.getValVT())
2025 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2026 // This truncation won't change the value.
2027 DAG.getIntPtrConstant(1));
2029 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2030 CopyVT, InFlag).getValue(1);
2031 Val = Chain.getValue(0);
2033 InFlag = Chain.getValue(2);
2034 InVals.push_back(Val);
2040 //===----------------------------------------------------------------------===//
2041 // C & StdCall & Fast Calling Convention implementation
2042 //===----------------------------------------------------------------------===//
2043 // StdCall calling convention seems to be standard for many Windows' API
2044 // routines and around. It differs from C calling convention just a little:
2045 // callee should clean up the stack, not caller. Symbols should be also
2046 // decorated in some fancy way :) It doesn't support any vector arguments.
2047 // For info on fast calling convention see Fast Calling Convention (tail call)
2048 // implementation LowerX86_32FastCCCallTo.
2050 /// CallIsStructReturn - Determines whether a call uses struct return
2052 enum StructReturnType {
2057 static StructReturnType
2058 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2060 return NotStructReturn;
2062 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2063 if (!Flags.isSRet())
2064 return NotStructReturn;
2065 if (Flags.isInReg())
2066 return RegStructReturn;
2067 return StackStructReturn;
2070 /// ArgsAreStructReturn - Determines whether a function uses struct
2071 /// return semantics.
2072 static StructReturnType
2073 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2075 return NotStructReturn;
2077 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2078 if (!Flags.isSRet())
2079 return NotStructReturn;
2080 if (Flags.isInReg())
2081 return RegStructReturn;
2082 return StackStructReturn;
2085 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2086 /// by "Src" to address "Dst" with size and alignment information specified by
2087 /// the specific parameter attribute. The copy will be passed as a byval
2088 /// function parameter.
2090 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2091 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2093 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2095 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2096 /*isVolatile*/false, /*AlwaysInline=*/true,
2097 MachinePointerInfo(), MachinePointerInfo());
2100 /// IsTailCallConvention - Return true if the calling convention is one that
2101 /// supports tail call optimization.
2102 static bool IsTailCallConvention(CallingConv::ID CC) {
2103 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2104 CC == CallingConv::HiPE);
2107 /// \brief Return true if the calling convention is a C calling convention.
2108 static bool IsCCallConvention(CallingConv::ID CC) {
2109 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2110 CC == CallingConv::X86_64_SysV);
2113 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2114 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2118 CallingConv::ID CalleeCC = CS.getCallingConv();
2119 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2125 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2126 /// a tailcall target by changing its ABI.
2127 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2128 bool GuaranteedTailCallOpt) {
2129 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2133 X86TargetLowering::LowerMemArgument(SDValue Chain,
2134 CallingConv::ID CallConv,
2135 const SmallVectorImpl<ISD::InputArg> &Ins,
2136 SDLoc dl, SelectionDAG &DAG,
2137 const CCValAssign &VA,
2138 MachineFrameInfo *MFI,
2140 // Create the nodes corresponding to a load from this parameter slot.
2141 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2142 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2143 getTargetMachine().Options.GuaranteedTailCallOpt);
2144 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2147 // If value is passed by pointer we have address passed instead of the value
2149 if (VA.getLocInfo() == CCValAssign::Indirect)
2150 ValVT = VA.getLocVT();
2152 ValVT = VA.getValVT();
2154 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2155 // changed with more analysis.
2156 // In case of tail call optimization mark all arguments mutable. Since they
2157 // could be overwritten by lowering of arguments in case of a tail call.
2158 if (Flags.isByVal()) {
2159 unsigned Bytes = Flags.getByValSize();
2160 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2161 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2162 return DAG.getFrameIndex(FI, getPointerTy());
2164 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2165 VA.getLocMemOffset(), isImmutable);
2166 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2167 return DAG.getLoad(ValVT, dl, Chain, FIN,
2168 MachinePointerInfo::getFixedStack(FI),
2169 false, false, false, 0);
2174 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2175 CallingConv::ID CallConv,
2177 const SmallVectorImpl<ISD::InputArg> &Ins,
2180 SmallVectorImpl<SDValue> &InVals)
2182 MachineFunction &MF = DAG.getMachineFunction();
2183 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2185 const Function* Fn = MF.getFunction();
2186 if (Fn->hasExternalLinkage() &&
2187 Subtarget->isTargetCygMing() &&
2188 Fn->getName() == "main")
2189 FuncInfo->setForceFramePointer(true);
2191 MachineFrameInfo *MFI = MF.getFrameInfo();
2192 bool Is64Bit = Subtarget->is64Bit();
2193 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2195 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2196 "Var args not supported with calling convention fastcc, ghc or hipe");
2198 // Assign locations to all of the incoming arguments.
2199 SmallVector<CCValAssign, 16> ArgLocs;
2200 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2201 ArgLocs, *DAG.getContext());
2203 // Allocate shadow area for Win64
2205 CCInfo.AllocateStack(32, 8);
2207 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2209 unsigned LastVal = ~0U;
2211 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2212 CCValAssign &VA = ArgLocs[i];
2213 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2215 assert(VA.getValNo() != LastVal &&
2216 "Don't support value assigned to multiple locs yet");
2218 LastVal = VA.getValNo();
2220 if (VA.isRegLoc()) {
2221 EVT RegVT = VA.getLocVT();
2222 const TargetRegisterClass *RC;
2223 if (RegVT == MVT::i32)
2224 RC = &X86::GR32RegClass;
2225 else if (Is64Bit && RegVT == MVT::i64)
2226 RC = &X86::GR64RegClass;
2227 else if (RegVT == MVT::f32)
2228 RC = &X86::FR32RegClass;
2229 else if (RegVT == MVT::f64)
2230 RC = &X86::FR64RegClass;
2231 else if (RegVT.is512BitVector())
2232 RC = &X86::VR512RegClass;
2233 else if (RegVT.is256BitVector())
2234 RC = &X86::VR256RegClass;
2235 else if (RegVT.is128BitVector())
2236 RC = &X86::VR128RegClass;
2237 else if (RegVT == MVT::x86mmx)
2238 RC = &X86::VR64RegClass;
2239 else if (RegVT == MVT::i1)
2240 RC = &X86::VK1RegClass;
2241 else if (RegVT == MVT::v8i1)
2242 RC = &X86::VK8RegClass;
2243 else if (RegVT == MVT::v16i1)
2244 RC = &X86::VK16RegClass;
2246 llvm_unreachable("Unknown argument type!");
2248 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2249 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2251 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2252 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2254 if (VA.getLocInfo() == CCValAssign::SExt)
2255 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2256 DAG.getValueType(VA.getValVT()));
2257 else if (VA.getLocInfo() == CCValAssign::ZExt)
2258 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2259 DAG.getValueType(VA.getValVT()));
2260 else if (VA.getLocInfo() == CCValAssign::BCvt)
2261 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2263 if (VA.isExtInLoc()) {
2264 // Handle MMX values passed in XMM regs.
2265 if (RegVT.isVector())
2266 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2268 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2271 assert(VA.isMemLoc());
2272 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2275 // If value is passed via pointer - do a load.
2276 if (VA.getLocInfo() == CCValAssign::Indirect)
2277 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2278 MachinePointerInfo(), false, false, false, 0);
2280 InVals.push_back(ArgValue);
2283 // The x86-64 ABIs require that for returning structs by value we copy
2284 // the sret argument into %rax/%eax (depending on ABI) for the return.
2285 // Win32 requires us to put the sret argument to %eax as well.
2286 // Save the argument into a virtual register so that we can access it
2287 // from the return points.
2288 if (MF.getFunction()->hasStructRetAttr() &&
2289 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2290 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2291 unsigned Reg = FuncInfo->getSRetReturnReg();
2293 MVT PtrTy = getPointerTy();
2294 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2295 FuncInfo->setSRetReturnReg(Reg);
2297 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2298 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2301 unsigned StackSize = CCInfo.getNextStackOffset();
2302 // Align stack specially for tail calls.
2303 if (FuncIsMadeTailCallSafe(CallConv,
2304 MF.getTarget().Options.GuaranteedTailCallOpt))
2305 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2307 // If the function takes variable number of arguments, make a frame index for
2308 // the start of the first vararg value... for expansion of llvm.va_start.
2310 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2311 CallConv != CallingConv::X86_ThisCall)) {
2312 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2315 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2317 // FIXME: We should really autogenerate these arrays
2318 static const uint16_t GPR64ArgRegsWin64[] = {
2319 X86::RCX, X86::RDX, X86::R8, X86::R9
2321 static const uint16_t GPR64ArgRegs64Bit[] = {
2322 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2324 static const uint16_t XMMArgRegs64Bit[] = {
2325 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2326 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2328 const uint16_t *GPR64ArgRegs;
2329 unsigned NumXMMRegs = 0;
2332 // The XMM registers which might contain var arg parameters are shadowed
2333 // in their paired GPR. So we only need to save the GPR to their home
2335 TotalNumIntRegs = 4;
2336 GPR64ArgRegs = GPR64ArgRegsWin64;
2338 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2339 GPR64ArgRegs = GPR64ArgRegs64Bit;
2341 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2344 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2347 bool NoImplicitFloatOps = Fn->getAttributes().
2348 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2349 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2350 "SSE register cannot be used when SSE is disabled!");
2351 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2352 NoImplicitFloatOps) &&
2353 "SSE register cannot be used when SSE is disabled!");
2354 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2355 !Subtarget->hasSSE1())
2356 // Kernel mode asks for SSE to be disabled, so don't push them
2358 TotalNumXMMRegs = 0;
2361 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2362 // Get to the caller-allocated home save location. Add 8 to account
2363 // for the return address.
2364 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2365 FuncInfo->setRegSaveFrameIndex(
2366 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2367 // Fixup to set vararg frame on shadow area (4 x i64).
2369 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2371 // For X86-64, if there are vararg parameters that are passed via
2372 // registers, then we must store them to their spots on the stack so
2373 // they may be loaded by deferencing the result of va_next.
2374 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2375 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2376 FuncInfo->setRegSaveFrameIndex(
2377 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2381 // Store the integer parameter registers.
2382 SmallVector<SDValue, 8> MemOps;
2383 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2385 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2386 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2387 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2388 DAG.getIntPtrConstant(Offset));
2389 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2390 &X86::GR64RegClass);
2391 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2393 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2394 MachinePointerInfo::getFixedStack(
2395 FuncInfo->getRegSaveFrameIndex(), Offset),
2397 MemOps.push_back(Store);
2401 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2402 // Now store the XMM (fp + vector) parameter registers.
2403 SmallVector<SDValue, 11> SaveXMMOps;
2404 SaveXMMOps.push_back(Chain);
2406 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2407 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2408 SaveXMMOps.push_back(ALVal);
2410 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2411 FuncInfo->getRegSaveFrameIndex()));
2412 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2413 FuncInfo->getVarArgsFPOffset()));
2415 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2416 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2417 &X86::VR128RegClass);
2418 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2419 SaveXMMOps.push_back(Val);
2421 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2423 &SaveXMMOps[0], SaveXMMOps.size()));
2426 if (!MemOps.empty())
2427 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2428 &MemOps[0], MemOps.size());
2432 // Some CCs need callee pop.
2433 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2434 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2435 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2437 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2438 // If this is an sret function, the return should pop the hidden pointer.
2439 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2440 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2441 argsAreStructReturn(Ins) == StackStructReturn)
2442 FuncInfo->setBytesToPopOnReturn(4);
2446 // RegSaveFrameIndex is X86-64 only.
2447 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2448 if (CallConv == CallingConv::X86_FastCall ||
2449 CallConv == CallingConv::X86_ThisCall)
2450 // fastcc functions can't have varargs.
2451 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2454 FuncInfo->setArgumentStackSize(StackSize);
2460 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2461 SDValue StackPtr, SDValue Arg,
2462 SDLoc dl, SelectionDAG &DAG,
2463 const CCValAssign &VA,
2464 ISD::ArgFlagsTy Flags) const {
2465 unsigned LocMemOffset = VA.getLocMemOffset();
2466 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2467 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2468 if (Flags.isByVal())
2469 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2471 return DAG.getStore(Chain, dl, Arg, PtrOff,
2472 MachinePointerInfo::getStack(LocMemOffset),
2476 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2477 /// optimization is performed and it is required.
2479 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2480 SDValue &OutRetAddr, SDValue Chain,
2481 bool IsTailCall, bool Is64Bit,
2482 int FPDiff, SDLoc dl) const {
2483 // Adjust the Return address stack slot.
2484 EVT VT = getPointerTy();
2485 OutRetAddr = getReturnAddressFrameIndex(DAG);
2487 // Load the "old" Return address.
2488 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2489 false, false, false, 0);
2490 return SDValue(OutRetAddr.getNode(), 1);
2493 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2494 /// optimization is performed and it is required (FPDiff!=0).
2496 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2497 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2498 unsigned SlotSize, int FPDiff, SDLoc dl) {
2499 // Store the return address to the appropriate stack slot.
2500 if (!FPDiff) return Chain;
2501 // Calculate the new stack slot for the return address.
2502 int NewReturnAddrFI =
2503 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2505 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2506 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2507 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2513 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2514 SmallVectorImpl<SDValue> &InVals) const {
2515 SelectionDAG &DAG = CLI.DAG;
2517 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2518 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2519 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2520 SDValue Chain = CLI.Chain;
2521 SDValue Callee = CLI.Callee;
2522 CallingConv::ID CallConv = CLI.CallConv;
2523 bool &isTailCall = CLI.IsTailCall;
2524 bool isVarArg = CLI.IsVarArg;
2526 MachineFunction &MF = DAG.getMachineFunction();
2527 bool Is64Bit = Subtarget->is64Bit();
2528 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2529 StructReturnType SR = callIsStructReturn(Outs);
2530 bool IsSibcall = false;
2532 if (MF.getTarget().Options.DisableTailCalls)
2536 // Check if it's really possible to do a tail call.
2537 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2538 isVarArg, SR != NotStructReturn,
2539 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2540 Outs, OutVals, Ins, DAG);
2542 // Sibcalls are automatically detected tailcalls which do not require
2544 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2551 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2552 "Var args not supported with calling convention fastcc, ghc or hipe");
2554 // Analyze operands of the call, assigning locations to each operand.
2555 SmallVector<CCValAssign, 16> ArgLocs;
2556 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2557 ArgLocs, *DAG.getContext());
2559 // Allocate shadow area for Win64
2561 CCInfo.AllocateStack(32, 8);
2563 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2565 // Get a count of how many bytes are to be pushed on the stack.
2566 unsigned NumBytes = CCInfo.getNextStackOffset();
2568 // This is a sibcall. The memory operands are available in caller's
2569 // own caller's stack.
2571 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2572 IsTailCallConvention(CallConv))
2573 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2576 if (isTailCall && !IsSibcall) {
2577 // Lower arguments at fp - stackoffset + fpdiff.
2578 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2579 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2581 FPDiff = NumBytesCallerPushed - NumBytes;
2583 // Set the delta of movement of the returnaddr stackslot.
2584 // But only set if delta is greater than previous delta.
2585 if (FPDiff < X86Info->getTCReturnAddrDelta())
2586 X86Info->setTCReturnAddrDelta(FPDiff);
2589 unsigned NumBytesToPush = NumBytes;
2590 unsigned NumBytesToPop = NumBytes;
2592 // If we have an inalloca argument, all stack space has already been allocated
2593 // for us and be right at the top of the stack. We don't support multiple
2594 // arguments passed in memory when using inalloca.
2595 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2597 assert(ArgLocs.back().getLocMemOffset() == 0 &&
2598 "an inalloca argument must be the only memory argument");
2602 Chain = DAG.getCALLSEQ_START(
2603 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2605 SDValue RetAddrFrIdx;
2606 // Load return address for tail calls.
2607 if (isTailCall && FPDiff)
2608 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2609 Is64Bit, FPDiff, dl);
2611 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2612 SmallVector<SDValue, 8> MemOpChains;
2615 // Walk the register/memloc assignments, inserting copies/loads. In the case
2616 // of tail call optimization arguments are handle later.
2617 const X86RegisterInfo *RegInfo =
2618 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2619 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2620 // Skip inalloca arguments, they have already been written.
2621 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2622 if (Flags.isInAlloca())
2625 CCValAssign &VA = ArgLocs[i];
2626 EVT RegVT = VA.getLocVT();
2627 SDValue Arg = OutVals[i];
2628 bool isByVal = Flags.isByVal();
2630 // Promote the value if needed.
2631 switch (VA.getLocInfo()) {
2632 default: llvm_unreachable("Unknown loc info!");
2633 case CCValAssign::Full: break;
2634 case CCValAssign::SExt:
2635 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2637 case CCValAssign::ZExt:
2638 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2640 case CCValAssign::AExt:
2641 if (RegVT.is128BitVector()) {
2642 // Special case: passing MMX values in XMM registers.
2643 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2644 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2645 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2647 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2649 case CCValAssign::BCvt:
2650 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2652 case CCValAssign::Indirect: {
2653 // Store the argument.
2654 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2655 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2656 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2657 MachinePointerInfo::getFixedStack(FI),
2664 if (VA.isRegLoc()) {
2665 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2666 if (isVarArg && IsWin64) {
2667 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2668 // shadow reg if callee is a varargs function.
2669 unsigned ShadowReg = 0;
2670 switch (VA.getLocReg()) {
2671 case X86::XMM0: ShadowReg = X86::RCX; break;
2672 case X86::XMM1: ShadowReg = X86::RDX; break;
2673 case X86::XMM2: ShadowReg = X86::R8; break;
2674 case X86::XMM3: ShadowReg = X86::R9; break;
2677 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2679 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2680 assert(VA.isMemLoc());
2681 if (StackPtr.getNode() == 0)
2682 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2684 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2685 dl, DAG, VA, Flags));
2689 if (!MemOpChains.empty())
2690 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2691 &MemOpChains[0], MemOpChains.size());
2693 if (Subtarget->isPICStyleGOT()) {
2694 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2697 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2698 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2700 // If we are tail calling and generating PIC/GOT style code load the
2701 // address of the callee into ECX. The value in ecx is used as target of
2702 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2703 // for tail calls on PIC/GOT architectures. Normally we would just put the
2704 // address of GOT into ebx and then call target@PLT. But for tail calls
2705 // ebx would be restored (since ebx is callee saved) before jumping to the
2708 // Note: The actual moving to ECX is done further down.
2709 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2710 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2711 !G->getGlobal()->hasProtectedVisibility())
2712 Callee = LowerGlobalAddress(Callee, DAG);
2713 else if (isa<ExternalSymbolSDNode>(Callee))
2714 Callee = LowerExternalSymbol(Callee, DAG);
2718 if (Is64Bit && isVarArg && !IsWin64) {
2719 // From AMD64 ABI document:
2720 // For calls that may call functions that use varargs or stdargs
2721 // (prototype-less calls or calls to functions containing ellipsis (...) in
2722 // the declaration) %al is used as hidden argument to specify the number
2723 // of SSE registers used. The contents of %al do not need to match exactly
2724 // the number of registers, but must be an ubound on the number of SSE
2725 // registers used and is in the range 0 - 8 inclusive.
2727 // Count the number of XMM registers allocated.
2728 static const uint16_t XMMArgRegs[] = {
2729 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2730 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2732 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2733 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2734 && "SSE registers cannot be used when SSE is disabled");
2736 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2737 DAG.getConstant(NumXMMRegs, MVT::i8)));
2740 // For tail calls lower the arguments to the 'real' stack slot.
2742 // Force all the incoming stack arguments to be loaded from the stack
2743 // before any new outgoing arguments are stored to the stack, because the
2744 // outgoing stack slots may alias the incoming argument stack slots, and
2745 // the alias isn't otherwise explicit. This is slightly more conservative
2746 // than necessary, because it means that each store effectively depends
2747 // on every argument instead of just those arguments it would clobber.
2748 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2750 SmallVector<SDValue, 8> MemOpChains2;
2753 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2754 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2755 CCValAssign &VA = ArgLocs[i];
2758 assert(VA.isMemLoc());
2759 SDValue Arg = OutVals[i];
2760 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2761 // Create frame index.
2762 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2763 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2764 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2765 FIN = DAG.getFrameIndex(FI, getPointerTy());
2767 if (Flags.isByVal()) {
2768 // Copy relative to framepointer.
2769 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2770 if (StackPtr.getNode() == 0)
2771 StackPtr = DAG.getCopyFromReg(Chain, dl,
2772 RegInfo->getStackRegister(),
2774 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2776 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2780 // Store relative to framepointer.
2781 MemOpChains2.push_back(
2782 DAG.getStore(ArgChain, dl, Arg, FIN,
2783 MachinePointerInfo::getFixedStack(FI),
2789 if (!MemOpChains2.empty())
2790 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2791 &MemOpChains2[0], MemOpChains2.size());
2793 // Store the return address to the appropriate stack slot.
2794 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2795 getPointerTy(), RegInfo->getSlotSize(),
2799 // Build a sequence of copy-to-reg nodes chained together with token chain
2800 // and flag operands which copy the outgoing args into registers.
2802 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2803 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2804 RegsToPass[i].second, InFlag);
2805 InFlag = Chain.getValue(1);
2808 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2809 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2810 // In the 64-bit large code model, we have to make all calls
2811 // through a register, since the call instruction's 32-bit
2812 // pc-relative offset may not be large enough to hold the whole
2814 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2815 // If the callee is a GlobalAddress node (quite common, every direct call
2816 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2819 // We should use extra load for direct calls to dllimported functions in
2821 const GlobalValue *GV = G->getGlobal();
2822 if (!GV->hasDLLImportStorageClass()) {
2823 unsigned char OpFlags = 0;
2824 bool ExtraLoad = false;
2825 unsigned WrapperKind = ISD::DELETED_NODE;
2827 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2828 // external symbols most go through the PLT in PIC mode. If the symbol
2829 // has hidden or protected visibility, or if it is static or local, then
2830 // we don't need to use the PLT - we can directly call it.
2831 if (Subtarget->isTargetELF() &&
2832 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2833 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2834 OpFlags = X86II::MO_PLT;
2835 } else if (Subtarget->isPICStyleStubAny() &&
2836 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2837 (!Subtarget->getTargetTriple().isMacOSX() ||
2838 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2839 // PC-relative references to external symbols should go through $stub,
2840 // unless we're building with the leopard linker or later, which
2841 // automatically synthesizes these stubs.
2842 OpFlags = X86II::MO_DARWIN_STUB;
2843 } else if (Subtarget->isPICStyleRIPRel() &&
2844 isa<Function>(GV) &&
2845 cast<Function>(GV)->getAttributes().
2846 hasAttribute(AttributeSet::FunctionIndex,
2847 Attribute::NonLazyBind)) {
2848 // If the function is marked as non-lazy, generate an indirect call
2849 // which loads from the GOT directly. This avoids runtime overhead
2850 // at the cost of eager binding (and one extra byte of encoding).
2851 OpFlags = X86II::MO_GOTPCREL;
2852 WrapperKind = X86ISD::WrapperRIP;
2856 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2857 G->getOffset(), OpFlags);
2859 // Add a wrapper if needed.
2860 if (WrapperKind != ISD::DELETED_NODE)
2861 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2862 // Add extra indirection if needed.
2864 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2865 MachinePointerInfo::getGOT(),
2866 false, false, false, 0);
2868 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2869 unsigned char OpFlags = 0;
2871 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2872 // external symbols should go through the PLT.
2873 if (Subtarget->isTargetELF() &&
2874 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2875 OpFlags = X86II::MO_PLT;
2876 } else if (Subtarget->isPICStyleStubAny() &&
2877 (!Subtarget->getTargetTriple().isMacOSX() ||
2878 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2879 // PC-relative references to external symbols should go through $stub,
2880 // unless we're building with the leopard linker or later, which
2881 // automatically synthesizes these stubs.
2882 OpFlags = X86II::MO_DARWIN_STUB;
2885 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2889 // Returns a chain & a flag for retval copy to use.
2890 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2891 SmallVector<SDValue, 8> Ops;
2893 if (!IsSibcall && isTailCall) {
2894 Chain = DAG.getCALLSEQ_END(Chain,
2895 DAG.getIntPtrConstant(NumBytesToPop, true),
2896 DAG.getIntPtrConstant(0, true), InFlag, dl);
2897 InFlag = Chain.getValue(1);
2900 Ops.push_back(Chain);
2901 Ops.push_back(Callee);
2904 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2906 // Add argument registers to the end of the list so that they are known live
2908 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2909 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2910 RegsToPass[i].second.getValueType()));
2912 // Add a register mask operand representing the call-preserved registers.
2913 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2914 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2915 assert(Mask && "Missing call preserved mask for calling convention");
2916 Ops.push_back(DAG.getRegisterMask(Mask));
2918 if (InFlag.getNode())
2919 Ops.push_back(InFlag);
2923 //// If this is the first return lowered for this function, add the regs
2924 //// to the liveout set for the function.
2925 // This isn't right, although it's probably harmless on x86; liveouts
2926 // should be computed from returns not tail calls. Consider a void
2927 // function making a tail call to a function returning int.
2928 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2931 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2932 InFlag = Chain.getValue(1);
2934 // Create the CALLSEQ_END node.
2935 unsigned NumBytesForCalleeToPop;
2936 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2937 getTargetMachine().Options.GuaranteedTailCallOpt))
2938 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
2939 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2940 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2941 SR == StackStructReturn)
2942 // If this is a call to a struct-return function, the callee
2943 // pops the hidden struct pointer, so we have to push it back.
2944 // This is common for Darwin/X86, Linux & Mingw32 targets.
2945 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2946 NumBytesForCalleeToPop = 4;
2948 NumBytesForCalleeToPop = 0; // Callee pops nothing.
2950 // Returns a flag for retval copy to use.
2952 Chain = DAG.getCALLSEQ_END(Chain,
2953 DAG.getIntPtrConstant(NumBytesToPop, true),
2954 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
2957 InFlag = Chain.getValue(1);
2960 // Handle result values, copying them out of physregs into vregs that we
2962 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2963 Ins, dl, DAG, InVals);
2966 //===----------------------------------------------------------------------===//
2967 // Fast Calling Convention (tail call) implementation
2968 //===----------------------------------------------------------------------===//
2970 // Like std call, callee cleans arguments, convention except that ECX is
2971 // reserved for storing the tail called function address. Only 2 registers are
2972 // free for argument passing (inreg). Tail call optimization is performed
2974 // * tailcallopt is enabled
2975 // * caller/callee are fastcc
2976 // On X86_64 architecture with GOT-style position independent code only local
2977 // (within module) calls are supported at the moment.
2978 // To keep the stack aligned according to platform abi the function
2979 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2980 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2981 // If a tail called function callee has more arguments than the caller the
2982 // caller needs to make sure that there is room to move the RETADDR to. This is
2983 // achieved by reserving an area the size of the argument delta right after the
2984 // original REtADDR, but before the saved framepointer or the spilled registers
2985 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2997 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2998 /// for a 16 byte align requirement.
3000 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3001 SelectionDAG& DAG) const {
3002 MachineFunction &MF = DAG.getMachineFunction();
3003 const TargetMachine &TM = MF.getTarget();
3004 const X86RegisterInfo *RegInfo =
3005 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
3006 const TargetFrameLowering &TFI = *TM.getFrameLowering();
3007 unsigned StackAlignment = TFI.getStackAlignment();
3008 uint64_t AlignMask = StackAlignment - 1;
3009 int64_t Offset = StackSize;
3010 unsigned SlotSize = RegInfo->getSlotSize();
3011 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3012 // Number smaller than 12 so just add the difference.
3013 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3015 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3016 Offset = ((~AlignMask) & Offset) + StackAlignment +
3017 (StackAlignment-SlotSize);
3022 /// MatchingStackOffset - Return true if the given stack call argument is
3023 /// already available in the same position (relatively) of the caller's
3024 /// incoming argument stack.
3026 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3027 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3028 const X86InstrInfo *TII) {
3029 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3031 if (Arg.getOpcode() == ISD::CopyFromReg) {
3032 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3033 if (!TargetRegisterInfo::isVirtualRegister(VR))
3035 MachineInstr *Def = MRI->getVRegDef(VR);
3038 if (!Flags.isByVal()) {
3039 if (!TII->isLoadFromStackSlot(Def, FI))
3042 unsigned Opcode = Def->getOpcode();
3043 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3044 Def->getOperand(1).isFI()) {
3045 FI = Def->getOperand(1).getIndex();
3046 Bytes = Flags.getByValSize();
3050 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3051 if (Flags.isByVal())
3052 // ByVal argument is passed in as a pointer but it's now being
3053 // dereferenced. e.g.
3054 // define @foo(%struct.X* %A) {
3055 // tail call @bar(%struct.X* byval %A)
3058 SDValue Ptr = Ld->getBasePtr();
3059 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3062 FI = FINode->getIndex();
3063 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3064 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3065 FI = FINode->getIndex();
3066 Bytes = Flags.getByValSize();
3070 assert(FI != INT_MAX);
3071 if (!MFI->isFixedObjectIndex(FI))
3073 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3076 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3077 /// for tail call optimization. Targets which want to do tail call
3078 /// optimization should implement this function.
3080 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3081 CallingConv::ID CalleeCC,
3083 bool isCalleeStructRet,
3084 bool isCallerStructRet,
3086 const SmallVectorImpl<ISD::OutputArg> &Outs,
3087 const SmallVectorImpl<SDValue> &OutVals,
3088 const SmallVectorImpl<ISD::InputArg> &Ins,
3089 SelectionDAG &DAG) const {
3090 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3093 // If -tailcallopt is specified, make fastcc functions tail-callable.
3094 const MachineFunction &MF = DAG.getMachineFunction();
3095 const Function *CallerF = MF.getFunction();
3097 // If the function return type is x86_fp80 and the callee return type is not,
3098 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3099 // perform a tailcall optimization here.
3100 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3103 CallingConv::ID CallerCC = CallerF->getCallingConv();
3104 bool CCMatch = CallerCC == CalleeCC;
3105 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3106 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3108 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3109 if (IsTailCallConvention(CalleeCC) && CCMatch)
3114 // Look for obvious safe cases to perform tail call optimization that do not
3115 // require ABI changes. This is what gcc calls sibcall.
3117 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3118 // emit a special epilogue.
3119 const X86RegisterInfo *RegInfo =
3120 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3121 if (RegInfo->needsStackRealignment(MF))
3124 // Also avoid sibcall optimization if either caller or callee uses struct
3125 // return semantics.
3126 if (isCalleeStructRet || isCallerStructRet)
3129 // An stdcall/thiscall caller is expected to clean up its arguments; the
3130 // callee isn't going to do that.
3131 // FIXME: this is more restrictive than needed. We could produce a tailcall
3132 // when the stack adjustment matches. For example, with a thiscall that takes
3133 // only one argument.
3134 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3135 CallerCC == CallingConv::X86_ThisCall))
3138 // Do not sibcall optimize vararg calls unless all arguments are passed via
3140 if (isVarArg && !Outs.empty()) {
3142 // Optimizing for varargs on Win64 is unlikely to be safe without
3143 // additional testing.
3144 if (IsCalleeWin64 || IsCallerWin64)
3147 SmallVector<CCValAssign, 16> ArgLocs;
3148 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3149 getTargetMachine(), ArgLocs, *DAG.getContext());
3151 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3152 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3153 if (!ArgLocs[i].isRegLoc())
3157 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3158 // stack. Therefore, if it's not used by the call it is not safe to optimize
3159 // this into a sibcall.
3160 bool Unused = false;
3161 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3168 SmallVector<CCValAssign, 16> RVLocs;
3169 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3170 getTargetMachine(), RVLocs, *DAG.getContext());
3171 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3172 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3173 CCValAssign &VA = RVLocs[i];
3174 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3179 // If the calling conventions do not match, then we'd better make sure the
3180 // results are returned in the same way as what the caller expects.
3182 SmallVector<CCValAssign, 16> RVLocs1;
3183 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3184 getTargetMachine(), RVLocs1, *DAG.getContext());
3185 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3187 SmallVector<CCValAssign, 16> RVLocs2;
3188 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3189 getTargetMachine(), RVLocs2, *DAG.getContext());
3190 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3192 if (RVLocs1.size() != RVLocs2.size())
3194 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3195 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3197 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3199 if (RVLocs1[i].isRegLoc()) {
3200 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3203 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3209 // If the callee takes no arguments then go on to check the results of the
3211 if (!Outs.empty()) {
3212 // Check if stack adjustment is needed. For now, do not do this if any
3213 // argument is passed on the stack.
3214 SmallVector<CCValAssign, 16> ArgLocs;
3215 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3216 getTargetMachine(), ArgLocs, *DAG.getContext());
3218 // Allocate shadow area for Win64
3220 CCInfo.AllocateStack(32, 8);
3222 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3223 if (CCInfo.getNextStackOffset()) {
3224 MachineFunction &MF = DAG.getMachineFunction();
3225 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3228 // Check if the arguments are already laid out in the right way as
3229 // the caller's fixed stack objects.
3230 MachineFrameInfo *MFI = MF.getFrameInfo();
3231 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3232 const X86InstrInfo *TII =
3233 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3234 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3235 CCValAssign &VA = ArgLocs[i];
3236 SDValue Arg = OutVals[i];
3237 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3238 if (VA.getLocInfo() == CCValAssign::Indirect)
3240 if (!VA.isRegLoc()) {
3241 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3248 // If the tailcall address may be in a register, then make sure it's
3249 // possible to register allocate for it. In 32-bit, the call address can
3250 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3251 // callee-saved registers are restored. These happen to be the same
3252 // registers used to pass 'inreg' arguments so watch out for those.
3253 if (!Subtarget->is64Bit() &&
3254 ((!isa<GlobalAddressSDNode>(Callee) &&
3255 !isa<ExternalSymbolSDNode>(Callee)) ||
3256 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3257 unsigned NumInRegs = 0;
3258 // In PIC we need an extra register to formulate the address computation
3260 unsigned MaxInRegs =
3261 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3263 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3264 CCValAssign &VA = ArgLocs[i];
3267 unsigned Reg = VA.getLocReg();
3270 case X86::EAX: case X86::EDX: case X86::ECX:
3271 if (++NumInRegs == MaxInRegs)
3283 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3284 const TargetLibraryInfo *libInfo) const {
3285 return X86::createFastISel(funcInfo, libInfo);
3288 //===----------------------------------------------------------------------===//
3289 // Other Lowering Hooks
3290 //===----------------------------------------------------------------------===//
3292 static bool MayFoldLoad(SDValue Op) {
3293 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3296 static bool MayFoldIntoStore(SDValue Op) {
3297 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3300 static bool isTargetShuffle(unsigned Opcode) {
3302 default: return false;
3303 case X86ISD::PSHUFD:
3304 case X86ISD::PSHUFHW:
3305 case X86ISD::PSHUFLW:
3307 case X86ISD::PALIGNR:
3308 case X86ISD::MOVLHPS:
3309 case X86ISD::MOVLHPD:
3310 case X86ISD::MOVHLPS:
3311 case X86ISD::MOVLPS:
3312 case X86ISD::MOVLPD:
3313 case X86ISD::MOVSHDUP:
3314 case X86ISD::MOVSLDUP:
3315 case X86ISD::MOVDDUP:
3318 case X86ISD::UNPCKL:
3319 case X86ISD::UNPCKH:
3320 case X86ISD::VPERMILP:
3321 case X86ISD::VPERM2X128:
3322 case X86ISD::VPERMI:
3327 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3328 SDValue V1, SelectionDAG &DAG) {
3330 default: llvm_unreachable("Unknown x86 shuffle node");
3331 case X86ISD::MOVSHDUP:
3332 case X86ISD::MOVSLDUP:
3333 case X86ISD::MOVDDUP:
3334 return DAG.getNode(Opc, dl, VT, V1);
3338 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3339 SDValue V1, unsigned TargetMask,
3340 SelectionDAG &DAG) {
3342 default: llvm_unreachable("Unknown x86 shuffle node");
3343 case X86ISD::PSHUFD:
3344 case X86ISD::PSHUFHW:
3345 case X86ISD::PSHUFLW:
3346 case X86ISD::VPERMILP:
3347 case X86ISD::VPERMI:
3348 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3352 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3353 SDValue V1, SDValue V2, unsigned TargetMask,
3354 SelectionDAG &DAG) {
3356 default: llvm_unreachable("Unknown x86 shuffle node");
3357 case X86ISD::PALIGNR:
3359 case X86ISD::VPERM2X128:
3360 return DAG.getNode(Opc, dl, VT, V1, V2,
3361 DAG.getConstant(TargetMask, MVT::i8));
3365 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3366 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3368 default: llvm_unreachable("Unknown x86 shuffle node");
3369 case X86ISD::MOVLHPS:
3370 case X86ISD::MOVLHPD:
3371 case X86ISD::MOVHLPS:
3372 case X86ISD::MOVLPS:
3373 case X86ISD::MOVLPD:
3376 case X86ISD::UNPCKL:
3377 case X86ISD::UNPCKH:
3378 return DAG.getNode(Opc, dl, VT, V1, V2);
3382 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3383 MachineFunction &MF = DAG.getMachineFunction();
3384 const X86RegisterInfo *RegInfo =
3385 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3386 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3387 int ReturnAddrIndex = FuncInfo->getRAIndex();
3389 if (ReturnAddrIndex == 0) {
3390 // Set up a frame object for the return address.
3391 unsigned SlotSize = RegInfo->getSlotSize();
3392 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3395 FuncInfo->setRAIndex(ReturnAddrIndex);
3398 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3401 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3402 bool hasSymbolicDisplacement) {
3403 // Offset should fit into 32 bit immediate field.
3404 if (!isInt<32>(Offset))
3407 // If we don't have a symbolic displacement - we don't have any extra
3409 if (!hasSymbolicDisplacement)
3412 // FIXME: Some tweaks might be needed for medium code model.
3413 if (M != CodeModel::Small && M != CodeModel::Kernel)
3416 // For small code model we assume that latest object is 16MB before end of 31
3417 // bits boundary. We may also accept pretty large negative constants knowing
3418 // that all objects are in the positive half of address space.
3419 if (M == CodeModel::Small && Offset < 16*1024*1024)
3422 // For kernel code model we know that all object resist in the negative half
3423 // of 32bits address space. We may not accept negative offsets, since they may
3424 // be just off and we may accept pretty large positive ones.
3425 if (M == CodeModel::Kernel && Offset > 0)
3431 /// isCalleePop - Determines whether the callee is required to pop its
3432 /// own arguments. Callee pop is necessary to support tail calls.
3433 bool X86::isCalleePop(CallingConv::ID CallingConv,
3434 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3438 switch (CallingConv) {
3441 case CallingConv::X86_StdCall:
3443 case CallingConv::X86_FastCall:
3445 case CallingConv::X86_ThisCall:
3447 case CallingConv::Fast:
3449 case CallingConv::GHC:
3451 case CallingConv::HiPE:
3456 /// \brief Return true if the condition is an unsigned comparison operation.
3457 static bool isX86CCUnsigned(unsigned X86CC) {
3459 default: llvm_unreachable("Invalid integer condition!");
3460 case X86::COND_E: return true;
3461 case X86::COND_G: return false;
3462 case X86::COND_GE: return false;
3463 case X86::COND_L: return false;
3464 case X86::COND_LE: return false;
3465 case X86::COND_NE: return true;
3466 case X86::COND_B: return true;
3467 case X86::COND_A: return true;
3468 case X86::COND_BE: return true;
3469 case X86::COND_AE: return true;
3471 llvm_unreachable("covered switch fell through?!");
3474 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3475 /// specific condition code, returning the condition code and the LHS/RHS of the
3476 /// comparison to make.
3477 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3478 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3480 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3481 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3482 // X > -1 -> X == 0, jump !sign.
3483 RHS = DAG.getConstant(0, RHS.getValueType());
3484 return X86::COND_NS;
3486 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3487 // X < 0 -> X == 0, jump on sign.
3490 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3492 RHS = DAG.getConstant(0, RHS.getValueType());
3493 return X86::COND_LE;
3497 switch (SetCCOpcode) {
3498 default: llvm_unreachable("Invalid integer condition!");
3499 case ISD::SETEQ: return X86::COND_E;
3500 case ISD::SETGT: return X86::COND_G;
3501 case ISD::SETGE: return X86::COND_GE;
3502 case ISD::SETLT: return X86::COND_L;
3503 case ISD::SETLE: return X86::COND_LE;
3504 case ISD::SETNE: return X86::COND_NE;
3505 case ISD::SETULT: return X86::COND_B;
3506 case ISD::SETUGT: return X86::COND_A;
3507 case ISD::SETULE: return X86::COND_BE;
3508 case ISD::SETUGE: return X86::COND_AE;
3512 // First determine if it is required or is profitable to flip the operands.
3514 // If LHS is a foldable load, but RHS is not, flip the condition.
3515 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3516 !ISD::isNON_EXTLoad(RHS.getNode())) {
3517 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3518 std::swap(LHS, RHS);
3521 switch (SetCCOpcode) {
3527 std::swap(LHS, RHS);
3531 // On a floating point condition, the flags are set as follows:
3533 // 0 | 0 | 0 | X > Y
3534 // 0 | 0 | 1 | X < Y
3535 // 1 | 0 | 0 | X == Y
3536 // 1 | 1 | 1 | unordered
3537 switch (SetCCOpcode) {
3538 default: llvm_unreachable("Condcode should be pre-legalized away");
3540 case ISD::SETEQ: return X86::COND_E;
3541 case ISD::SETOLT: // flipped
3543 case ISD::SETGT: return X86::COND_A;
3544 case ISD::SETOLE: // flipped
3546 case ISD::SETGE: return X86::COND_AE;
3547 case ISD::SETUGT: // flipped
3549 case ISD::SETLT: return X86::COND_B;
3550 case ISD::SETUGE: // flipped
3552 case ISD::SETLE: return X86::COND_BE;
3554 case ISD::SETNE: return X86::COND_NE;
3555 case ISD::SETUO: return X86::COND_P;
3556 case ISD::SETO: return X86::COND_NP;
3558 case ISD::SETUNE: return X86::COND_INVALID;
3562 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3563 /// code. Current x86 isa includes the following FP cmov instructions:
3564 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3565 static bool hasFPCMov(unsigned X86CC) {
3581 /// isFPImmLegal - Returns true if the target can instruction select the
3582 /// specified FP immediate natively. If false, the legalizer will
3583 /// materialize the FP immediate as a load from a constant pool.
3584 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3585 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3586 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3592 /// \brief Returns true if it is beneficial to convert a load of a constant
3593 /// to just the constant itself.
3594 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3596 assert(Ty->isIntegerTy());
3598 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3599 if (BitSize == 0 || BitSize > 64)
3604 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3605 /// the specified range (L, H].
3606 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3607 return (Val < 0) || (Val >= Low && Val < Hi);
3610 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3611 /// specified value.
3612 static bool isUndefOrEqual(int Val, int CmpVal) {
3613 return (Val < 0 || Val == CmpVal);
3616 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3617 /// from position Pos and ending in Pos+Size, falls within the specified
3618 /// sequential range (L, L+Pos]. or is undef.
3619 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3620 unsigned Pos, unsigned Size, int Low) {
3621 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3622 if (!isUndefOrEqual(Mask[i], Low))
3627 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3628 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3629 /// the second operand.
3630 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3631 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3632 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3633 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3634 return (Mask[0] < 2 && Mask[1] < 2);
3638 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3639 /// is suitable for input to PSHUFHW.
3640 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3641 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3644 // Lower quadword copied in order or undef.
3645 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3648 // Upper quadword shuffled.
3649 for (unsigned i = 4; i != 8; ++i)
3650 if (!isUndefOrInRange(Mask[i], 4, 8))
3653 if (VT == MVT::v16i16) {
3654 // Lower quadword copied in order or undef.
3655 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3658 // Upper quadword shuffled.
3659 for (unsigned i = 12; i != 16; ++i)
3660 if (!isUndefOrInRange(Mask[i], 12, 16))
3667 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3668 /// is suitable for input to PSHUFLW.
3669 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3670 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3673 // Upper quadword copied in order.
3674 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3677 // Lower quadword shuffled.
3678 for (unsigned i = 0; i != 4; ++i)
3679 if (!isUndefOrInRange(Mask[i], 0, 4))
3682 if (VT == MVT::v16i16) {
3683 // Upper quadword copied in order.
3684 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3687 // Lower quadword shuffled.
3688 for (unsigned i = 8; i != 12; ++i)
3689 if (!isUndefOrInRange(Mask[i], 8, 12))
3696 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3697 /// is suitable for input to PALIGNR.
3698 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3699 const X86Subtarget *Subtarget) {
3700 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3701 (VT.is256BitVector() && !Subtarget->hasInt256()))
3704 unsigned NumElts = VT.getVectorNumElements();
3705 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3706 unsigned NumLaneElts = NumElts/NumLanes;
3708 // Do not handle 64-bit element shuffles with palignr.
3709 if (NumLaneElts == 2)
3712 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3714 for (i = 0; i != NumLaneElts; ++i) {
3719 // Lane is all undef, go to next lane
3720 if (i == NumLaneElts)
3723 int Start = Mask[i+l];
3725 // Make sure its in this lane in one of the sources
3726 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3727 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3730 // If not lane 0, then we must match lane 0
3731 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3734 // Correct second source to be contiguous with first source
3735 if (Start >= (int)NumElts)
3736 Start -= NumElts - NumLaneElts;
3738 // Make sure we're shifting in the right direction.
3739 if (Start <= (int)(i+l))
3744 // Check the rest of the elements to see if they are consecutive.
3745 for (++i; i != NumLaneElts; ++i) {
3746 int Idx = Mask[i+l];
3748 // Make sure its in this lane
3749 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3750 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3753 // If not lane 0, then we must match lane 0
3754 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3757 if (Idx >= (int)NumElts)
3758 Idx -= NumElts - NumLaneElts;
3760 if (!isUndefOrEqual(Idx, Start+i))
3769 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3770 /// the two vector operands have swapped position.
3771 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3772 unsigned NumElems) {
3773 for (unsigned i = 0; i != NumElems; ++i) {
3777 else if (idx < (int)NumElems)
3778 Mask[i] = idx + NumElems;
3780 Mask[i] = idx - NumElems;
3784 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3785 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3786 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3787 /// reverse of what x86 shuffles want.
3788 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3790 unsigned NumElems = VT.getVectorNumElements();
3791 unsigned NumLanes = VT.getSizeInBits()/128;
3792 unsigned NumLaneElems = NumElems/NumLanes;
3794 if (NumLaneElems != 2 && NumLaneElems != 4)
3797 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3798 bool symetricMaskRequired =
3799 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3801 // VSHUFPSY divides the resulting vector into 4 chunks.
3802 // The sources are also splitted into 4 chunks, and each destination
3803 // chunk must come from a different source chunk.
3805 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3806 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3808 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3809 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3811 // VSHUFPDY divides the resulting vector into 4 chunks.
3812 // The sources are also splitted into 4 chunks, and each destination
3813 // chunk must come from a different source chunk.
3815 // SRC1 => X3 X2 X1 X0
3816 // SRC2 => Y3 Y2 Y1 Y0
3818 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3820 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3821 unsigned HalfLaneElems = NumLaneElems/2;
3822 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3823 for (unsigned i = 0; i != NumLaneElems; ++i) {
3824 int Idx = Mask[i+l];
3825 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3826 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3828 // For VSHUFPSY, the mask of the second half must be the same as the
3829 // first but with the appropriate offsets. This works in the same way as
3830 // VPERMILPS works with masks.
3831 if (!symetricMaskRequired || Idx < 0)
3833 if (MaskVal[i] < 0) {
3834 MaskVal[i] = Idx - l;
3837 if ((signed)(Idx - l) != MaskVal[i])
3845 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3846 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3847 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3848 if (!VT.is128BitVector())
3851 unsigned NumElems = VT.getVectorNumElements();
3856 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3857 return isUndefOrEqual(Mask[0], 6) &&
3858 isUndefOrEqual(Mask[1], 7) &&
3859 isUndefOrEqual(Mask[2], 2) &&
3860 isUndefOrEqual(Mask[3], 3);
3863 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3864 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3866 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3867 if (!VT.is128BitVector())
3870 unsigned NumElems = VT.getVectorNumElements();
3875 return isUndefOrEqual(Mask[0], 2) &&
3876 isUndefOrEqual(Mask[1], 3) &&
3877 isUndefOrEqual(Mask[2], 2) &&
3878 isUndefOrEqual(Mask[3], 3);
3881 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3882 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3883 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3884 if (!VT.is128BitVector())
3887 unsigned NumElems = VT.getVectorNumElements();
3889 if (NumElems != 2 && NumElems != 4)
3892 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3893 if (!isUndefOrEqual(Mask[i], i + NumElems))
3896 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3897 if (!isUndefOrEqual(Mask[i], i))
3903 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3904 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3905 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3906 if (!VT.is128BitVector())
3909 unsigned NumElems = VT.getVectorNumElements();
3911 if (NumElems != 2 && NumElems != 4)
3914 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3915 if (!isUndefOrEqual(Mask[i], i))
3918 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3919 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3926 // Some special combinations that can be optimized.
3929 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3930 SelectionDAG &DAG) {
3931 MVT VT = SVOp->getSimpleValueType(0);
3934 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3937 ArrayRef<int> Mask = SVOp->getMask();
3939 // These are the special masks that may be optimized.
3940 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3941 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3942 bool MatchEvenMask = true;
3943 bool MatchOddMask = true;
3944 for (int i=0; i<8; ++i) {
3945 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3946 MatchEvenMask = false;
3947 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3948 MatchOddMask = false;
3951 if (!MatchEvenMask && !MatchOddMask)
3954 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3956 SDValue Op0 = SVOp->getOperand(0);
3957 SDValue Op1 = SVOp->getOperand(1);
3959 if (MatchEvenMask) {
3960 // Shift the second operand right to 32 bits.
3961 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3962 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3964 // Shift the first operand left to 32 bits.
3965 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3966 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3968 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3969 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3972 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3973 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3974 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3975 bool HasInt256, bool V2IsSplat = false) {
3977 assert(VT.getSizeInBits() >= 128 &&
3978 "Unsupported vector type for unpckl");
3980 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3982 unsigned NumOf256BitLanes;
3983 unsigned NumElts = VT.getVectorNumElements();
3984 if (VT.is256BitVector()) {
3985 if (NumElts != 4 && NumElts != 8 &&
3986 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3989 NumOf256BitLanes = 1;
3990 } else if (VT.is512BitVector()) {
3991 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3992 "Unsupported vector type for unpckh");
3994 NumOf256BitLanes = 2;
3997 NumOf256BitLanes = 1;
4000 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4001 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4003 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4004 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4005 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4006 int BitI = Mask[l256*NumEltsInStride+l+i];
4007 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4008 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4010 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4012 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4020 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4021 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4022 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4023 bool HasInt256, bool V2IsSplat = false) {
4024 assert(VT.getSizeInBits() >= 128 &&
4025 "Unsupported vector type for unpckh");
4027 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4029 unsigned NumOf256BitLanes;
4030 unsigned NumElts = VT.getVectorNumElements();
4031 if (VT.is256BitVector()) {
4032 if (NumElts != 4 && NumElts != 8 &&
4033 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4036 NumOf256BitLanes = 1;
4037 } else if (VT.is512BitVector()) {
4038 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4039 "Unsupported vector type for unpckh");
4041 NumOf256BitLanes = 2;
4044 NumOf256BitLanes = 1;
4047 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4048 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4050 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4051 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4052 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4053 int BitI = Mask[l256*NumEltsInStride+l+i];
4054 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4055 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4057 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4059 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4067 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4068 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4070 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4071 unsigned NumElts = VT.getVectorNumElements();
4072 bool Is256BitVec = VT.is256BitVector();
4074 if (VT.is512BitVector())
4076 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4077 "Unsupported vector type for unpckh");
4079 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4080 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4083 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4084 // FIXME: Need a better way to get rid of this, there's no latency difference
4085 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4086 // the former later. We should also remove the "_undef" special mask.
4087 if (NumElts == 4 && Is256BitVec)
4090 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4091 // independently on 128-bit lanes.
4092 unsigned NumLanes = VT.getSizeInBits()/128;
4093 unsigned NumLaneElts = NumElts/NumLanes;
4095 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4096 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4097 int BitI = Mask[l+i];
4098 int BitI1 = Mask[l+i+1];
4100 if (!isUndefOrEqual(BitI, j))
4102 if (!isUndefOrEqual(BitI1, j))
4110 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4111 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4113 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4114 unsigned NumElts = VT.getVectorNumElements();
4116 if (VT.is512BitVector())
4119 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4120 "Unsupported vector type for unpckh");
4122 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4123 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4126 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4127 // independently on 128-bit lanes.
4128 unsigned NumLanes = VT.getSizeInBits()/128;
4129 unsigned NumLaneElts = NumElts/NumLanes;
4131 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4132 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4133 int BitI = Mask[l+i];
4134 int BitI1 = Mask[l+i+1];
4135 if (!isUndefOrEqual(BitI, j))
4137 if (!isUndefOrEqual(BitI1, j))
4144 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4145 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4146 /// MOVSD, and MOVD, i.e. setting the lowest element.
4147 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4148 if (VT.getVectorElementType().getSizeInBits() < 32)
4150 if (!VT.is128BitVector())
4153 unsigned NumElts = VT.getVectorNumElements();
4155 if (!isUndefOrEqual(Mask[0], NumElts))
4158 for (unsigned i = 1; i != NumElts; ++i)
4159 if (!isUndefOrEqual(Mask[i], i))
4165 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4166 /// as permutations between 128-bit chunks or halves. As an example: this
4168 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4169 /// The first half comes from the second half of V1 and the second half from the
4170 /// the second half of V2.
4171 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4172 if (!HasFp256 || !VT.is256BitVector())
4175 // The shuffle result is divided into half A and half B. In total the two
4176 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4177 // B must come from C, D, E or F.
4178 unsigned HalfSize = VT.getVectorNumElements()/2;
4179 bool MatchA = false, MatchB = false;
4181 // Check if A comes from one of C, D, E, F.
4182 for (unsigned Half = 0; Half != 4; ++Half) {
4183 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4189 // Check if B comes from one of C, D, E, F.
4190 for (unsigned Half = 0; Half != 4; ++Half) {
4191 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4197 return MatchA && MatchB;
4200 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4201 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4202 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4203 MVT VT = SVOp->getSimpleValueType(0);
4205 unsigned HalfSize = VT.getVectorNumElements()/2;
4207 unsigned FstHalf = 0, SndHalf = 0;
4208 for (unsigned i = 0; i < HalfSize; ++i) {
4209 if (SVOp->getMaskElt(i) > 0) {
4210 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4214 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4215 if (SVOp->getMaskElt(i) > 0) {
4216 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4221 return (FstHalf | (SndHalf << 4));
4224 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4225 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4226 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4230 unsigned NumElts = VT.getVectorNumElements();
4232 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4233 for (unsigned i = 0; i != NumElts; ++i) {
4236 Imm8 |= Mask[i] << (i*2);
4241 unsigned LaneSize = 4;
4242 SmallVector<int, 4> MaskVal(LaneSize, -1);
4244 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4245 for (unsigned i = 0; i != LaneSize; ++i) {
4246 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4250 if (MaskVal[i] < 0) {
4251 MaskVal[i] = Mask[i+l] - l;
4252 Imm8 |= MaskVal[i] << (i*2);
4255 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4262 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4263 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4264 /// Note that VPERMIL mask matching is different depending whether theunderlying
4265 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4266 /// to the same elements of the low, but to the higher half of the source.
4267 /// In VPERMILPD the two lanes could be shuffled independently of each other
4268 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4269 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4270 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4271 if (VT.getSizeInBits() < 256 || EltSize < 32)
4273 bool symetricMaskRequired = (EltSize == 32);
4274 unsigned NumElts = VT.getVectorNumElements();
4276 unsigned NumLanes = VT.getSizeInBits()/128;
4277 unsigned LaneSize = NumElts/NumLanes;
4278 // 2 or 4 elements in one lane
4280 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4281 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4282 for (unsigned i = 0; i != LaneSize; ++i) {
4283 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4285 if (symetricMaskRequired) {
4286 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4287 ExpectedMaskVal[i] = Mask[i+l] - l;
4290 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4298 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4299 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4300 /// element of vector 2 and the other elements to come from vector 1 in order.
4301 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4302 bool V2IsSplat = false, bool V2IsUndef = false) {
4303 if (!VT.is128BitVector())
4306 unsigned NumOps = VT.getVectorNumElements();
4307 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4310 if (!isUndefOrEqual(Mask[0], 0))
4313 for (unsigned i = 1; i != NumOps; ++i)
4314 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4315 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4316 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4322 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4323 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4324 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4325 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4326 const X86Subtarget *Subtarget) {
4327 if (!Subtarget->hasSSE3())
4330 unsigned NumElems = VT.getVectorNumElements();
4332 if ((VT.is128BitVector() && NumElems != 4) ||
4333 (VT.is256BitVector() && NumElems != 8) ||
4334 (VT.is512BitVector() && NumElems != 16))
4337 // "i+1" is the value the indexed mask element must have
4338 for (unsigned i = 0; i != NumElems; i += 2)
4339 if (!isUndefOrEqual(Mask[i], i+1) ||
4340 !isUndefOrEqual(Mask[i+1], i+1))
4346 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4347 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4348 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4349 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4350 const X86Subtarget *Subtarget) {
4351 if (!Subtarget->hasSSE3())
4354 unsigned NumElems = VT.getVectorNumElements();
4356 if ((VT.is128BitVector() && NumElems != 4) ||
4357 (VT.is256BitVector() && NumElems != 8) ||
4358 (VT.is512BitVector() && NumElems != 16))
4361 // "i" is the value the indexed mask element must have
4362 for (unsigned i = 0; i != NumElems; i += 2)
4363 if (!isUndefOrEqual(Mask[i], i) ||
4364 !isUndefOrEqual(Mask[i+1], i))
4370 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4371 /// specifies a shuffle of elements that is suitable for input to 256-bit
4372 /// version of MOVDDUP.
4373 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4374 if (!HasFp256 || !VT.is256BitVector())
4377 unsigned NumElts = VT.getVectorNumElements();
4381 for (unsigned i = 0; i != NumElts/2; ++i)
4382 if (!isUndefOrEqual(Mask[i], 0))
4384 for (unsigned i = NumElts/2; i != NumElts; ++i)
4385 if (!isUndefOrEqual(Mask[i], NumElts/2))
4390 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4391 /// specifies a shuffle of elements that is suitable for input to 128-bit
4392 /// version of MOVDDUP.
4393 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4394 if (!VT.is128BitVector())
4397 unsigned e = VT.getVectorNumElements() / 2;
4398 for (unsigned i = 0; i != e; ++i)
4399 if (!isUndefOrEqual(Mask[i], i))
4401 for (unsigned i = 0; i != e; ++i)
4402 if (!isUndefOrEqual(Mask[e+i], i))
4407 /// isVEXTRACTIndex - Return true if the specified
4408 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4409 /// suitable for instruction that extract 128 or 256 bit vectors
4410 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4411 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4412 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4415 // The index should be aligned on a vecWidth-bit boundary.
4417 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4419 MVT VT = N->getSimpleValueType(0);
4420 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4421 bool Result = (Index * ElSize) % vecWidth == 0;
4426 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4427 /// operand specifies a subvector insert that is suitable for input to
4428 /// insertion of 128 or 256-bit subvectors
4429 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4430 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4431 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4433 // The index should be aligned on a vecWidth-bit boundary.
4435 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4437 MVT VT = N->getSimpleValueType(0);
4438 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4439 bool Result = (Index * ElSize) % vecWidth == 0;
4444 bool X86::isVINSERT128Index(SDNode *N) {
4445 return isVINSERTIndex(N, 128);
4448 bool X86::isVINSERT256Index(SDNode *N) {
4449 return isVINSERTIndex(N, 256);
4452 bool X86::isVEXTRACT128Index(SDNode *N) {
4453 return isVEXTRACTIndex(N, 128);
4456 bool X86::isVEXTRACT256Index(SDNode *N) {
4457 return isVEXTRACTIndex(N, 256);
4460 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4461 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4462 /// Handles 128-bit and 256-bit.
4463 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4464 MVT VT = N->getSimpleValueType(0);
4466 assert((VT.getSizeInBits() >= 128) &&
4467 "Unsupported vector type for PSHUF/SHUFP");
4469 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4470 // independently on 128-bit lanes.
4471 unsigned NumElts = VT.getVectorNumElements();
4472 unsigned NumLanes = VT.getSizeInBits()/128;
4473 unsigned NumLaneElts = NumElts/NumLanes;
4475 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4476 "Only supports 2, 4 or 8 elements per lane");
4478 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4480 for (unsigned i = 0; i != NumElts; ++i) {
4481 int Elt = N->getMaskElt(i);
4482 if (Elt < 0) continue;
4483 Elt &= NumLaneElts - 1;
4484 unsigned ShAmt = (i << Shift) % 8;
4485 Mask |= Elt << ShAmt;
4491 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4492 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4493 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4494 MVT VT = N->getSimpleValueType(0);
4496 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4497 "Unsupported vector type for PSHUFHW");
4499 unsigned NumElts = VT.getVectorNumElements();
4502 for (unsigned l = 0; l != NumElts; l += 8) {
4503 // 8 nodes per lane, but we only care about the last 4.
4504 for (unsigned i = 0; i < 4; ++i) {
4505 int Elt = N->getMaskElt(l+i+4);
4506 if (Elt < 0) continue;
4507 Elt &= 0x3; // only 2-bits.
4508 Mask |= Elt << (i * 2);
4515 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4516 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4517 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4518 MVT VT = N->getSimpleValueType(0);
4520 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4521 "Unsupported vector type for PSHUFHW");
4523 unsigned NumElts = VT.getVectorNumElements();
4526 for (unsigned l = 0; l != NumElts; l += 8) {
4527 // 8 nodes per lane, but we only care about the first 4.
4528 for (unsigned i = 0; i < 4; ++i) {
4529 int Elt = N->getMaskElt(l+i);
4530 if (Elt < 0) continue;
4531 Elt &= 0x3; // only 2-bits
4532 Mask |= Elt << (i * 2);
4539 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4540 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4541 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4542 MVT VT = SVOp->getSimpleValueType(0);
4543 unsigned EltSize = VT.is512BitVector() ? 1 :
4544 VT.getVectorElementType().getSizeInBits() >> 3;
4546 unsigned NumElts = VT.getVectorNumElements();
4547 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4548 unsigned NumLaneElts = NumElts/NumLanes;
4552 for (i = 0; i != NumElts; ++i) {
4553 Val = SVOp->getMaskElt(i);
4557 if (Val >= (int)NumElts)
4558 Val -= NumElts - NumLaneElts;
4560 assert(Val - i > 0 && "PALIGNR imm should be positive");
4561 return (Val - i) * EltSize;
4564 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4565 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4566 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4567 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4570 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4572 MVT VecVT = N->getOperand(0).getSimpleValueType();
4573 MVT ElVT = VecVT.getVectorElementType();
4575 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4576 return Index / NumElemsPerChunk;
4579 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4580 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4581 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4582 llvm_unreachable("Illegal insert subvector for VINSERT");
4585 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4587 MVT VecVT = N->getSimpleValueType(0);
4588 MVT ElVT = VecVT.getVectorElementType();
4590 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4591 return Index / NumElemsPerChunk;
4594 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4595 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4596 /// and VINSERTI128 instructions.
4597 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4598 return getExtractVEXTRACTImmediate(N, 128);
4601 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4602 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4603 /// and VINSERTI64x4 instructions.
4604 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4605 return getExtractVEXTRACTImmediate(N, 256);
4608 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4609 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4610 /// and VINSERTI128 instructions.
4611 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4612 return getInsertVINSERTImmediate(N, 128);
4615 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4616 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4617 /// and VINSERTI64x4 instructions.
4618 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4619 return getInsertVINSERTImmediate(N, 256);
4622 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4624 bool X86::isZeroNode(SDValue Elt) {
4625 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4626 return CN->isNullValue();
4627 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4628 return CFP->getValueAPF().isPosZero();
4632 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4633 /// their permute mask.
4634 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4635 SelectionDAG &DAG) {
4636 MVT VT = SVOp->getSimpleValueType(0);
4637 unsigned NumElems = VT.getVectorNumElements();
4638 SmallVector<int, 8> MaskVec;
4640 for (unsigned i = 0; i != NumElems; ++i) {
4641 int Idx = SVOp->getMaskElt(i);
4643 if (Idx < (int)NumElems)
4648 MaskVec.push_back(Idx);
4650 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4651 SVOp->getOperand(0), &MaskVec[0]);
4654 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4655 /// match movhlps. The lower half elements should come from upper half of
4656 /// V1 (and in order), and the upper half elements should come from the upper
4657 /// half of V2 (and in order).
4658 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4659 if (!VT.is128BitVector())
4661 if (VT.getVectorNumElements() != 4)
4663 for (unsigned i = 0, e = 2; i != e; ++i)
4664 if (!isUndefOrEqual(Mask[i], i+2))
4666 for (unsigned i = 2; i != 4; ++i)
4667 if (!isUndefOrEqual(Mask[i], i+4))
4672 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4673 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4675 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4676 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4678 N = N->getOperand(0).getNode();
4679 if (!ISD::isNON_EXTLoad(N))
4682 *LD = cast<LoadSDNode>(N);
4686 // Test whether the given value is a vector value which will be legalized
4688 static bool WillBeConstantPoolLoad(SDNode *N) {
4689 if (N->getOpcode() != ISD::BUILD_VECTOR)
4692 // Check for any non-constant elements.
4693 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4694 switch (N->getOperand(i).getNode()->getOpcode()) {
4696 case ISD::ConstantFP:
4703 // Vectors of all-zeros and all-ones are materialized with special
4704 // instructions rather than being loaded.
4705 return !ISD::isBuildVectorAllZeros(N) &&
4706 !ISD::isBuildVectorAllOnes(N);
4709 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4710 /// match movlp{s|d}. The lower half elements should come from lower half of
4711 /// V1 (and in order), and the upper half elements should come from the upper
4712 /// half of V2 (and in order). And since V1 will become the source of the
4713 /// MOVLP, it must be either a vector load or a scalar load to vector.
4714 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4715 ArrayRef<int> Mask, MVT VT) {
4716 if (!VT.is128BitVector())
4719 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4721 // Is V2 is a vector load, don't do this transformation. We will try to use
4722 // load folding shufps op.
4723 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4726 unsigned NumElems = VT.getVectorNumElements();
4728 if (NumElems != 2 && NumElems != 4)
4730 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4731 if (!isUndefOrEqual(Mask[i], i))
4733 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4734 if (!isUndefOrEqual(Mask[i], i+NumElems))
4739 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4741 static bool isSplatVector(SDNode *N) {
4742 if (N->getOpcode() != ISD::BUILD_VECTOR)
4745 SDValue SplatValue = N->getOperand(0);
4746 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4747 if (N->getOperand(i) != SplatValue)
4752 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4753 /// to an zero vector.
4754 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4755 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4756 SDValue V1 = N->getOperand(0);
4757 SDValue V2 = N->getOperand(1);
4758 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4759 for (unsigned i = 0; i != NumElems; ++i) {
4760 int Idx = N->getMaskElt(i);
4761 if (Idx >= (int)NumElems) {
4762 unsigned Opc = V2.getOpcode();
4763 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4765 if (Opc != ISD::BUILD_VECTOR ||
4766 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4768 } else if (Idx >= 0) {
4769 unsigned Opc = V1.getOpcode();
4770 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4772 if (Opc != ISD::BUILD_VECTOR ||
4773 !X86::isZeroNode(V1.getOperand(Idx)))
4780 /// getZeroVector - Returns a vector of specified type with all zero elements.
4782 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4783 SelectionDAG &DAG, SDLoc dl) {
4784 assert(VT.isVector() && "Expected a vector type");
4786 // Always build SSE zero vectors as <4 x i32> bitcasted
4787 // to their dest type. This ensures they get CSE'd.
4789 if (VT.is128BitVector()) { // SSE
4790 if (Subtarget->hasSSE2()) { // SSE2
4791 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4792 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4794 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4795 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4797 } else if (VT.is256BitVector()) { // AVX
4798 if (Subtarget->hasInt256()) { // AVX2
4799 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4800 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4801 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4802 array_lengthof(Ops));
4804 // 256-bit logic and arithmetic instructions in AVX are all
4805 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4806 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4807 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4808 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4809 array_lengthof(Ops));
4811 } else if (VT.is512BitVector()) { // AVX-512
4812 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4813 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4814 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4815 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4816 } else if (VT.getScalarType() == MVT::i1) {
4817 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4818 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4819 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4820 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4821 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
4822 Ops, VT.getVectorNumElements());
4824 llvm_unreachable("Unexpected vector type");
4826 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4829 /// getOnesVector - Returns a vector of specified type with all bits set.
4830 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4831 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4832 /// Then bitcast to their original type, ensuring they get CSE'd.
4833 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4835 assert(VT.isVector() && "Expected a vector type");
4837 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4839 if (VT.is256BitVector()) {
4840 if (HasInt256) { // AVX2
4841 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4842 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4843 array_lengthof(Ops));
4845 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4846 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4848 } else if (VT.is128BitVector()) {
4849 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4851 llvm_unreachable("Unexpected vector type");
4853 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4856 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4857 /// that point to V2 points to its first element.
4858 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4859 for (unsigned i = 0; i != NumElems; ++i) {
4860 if (Mask[i] > (int)NumElems) {
4866 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4867 /// operation of specified width.
4868 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4870 unsigned NumElems = VT.getVectorNumElements();
4871 SmallVector<int, 8> Mask;
4872 Mask.push_back(NumElems);
4873 for (unsigned i = 1; i != NumElems; ++i)
4875 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4878 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4879 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4881 unsigned NumElems = VT.getVectorNumElements();
4882 SmallVector<int, 8> Mask;
4883 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4885 Mask.push_back(i + NumElems);
4887 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4890 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4891 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4893 unsigned NumElems = VT.getVectorNumElements();
4894 SmallVector<int, 8> Mask;
4895 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4896 Mask.push_back(i + Half);
4897 Mask.push_back(i + NumElems + Half);
4899 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4902 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4903 // a generic shuffle instruction because the target has no such instructions.
4904 // Generate shuffles which repeat i16 and i8 several times until they can be
4905 // represented by v4f32 and then be manipulated by target suported shuffles.
4906 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4907 MVT VT = V.getSimpleValueType();
4908 int NumElems = VT.getVectorNumElements();
4911 while (NumElems > 4) {
4912 if (EltNo < NumElems/2) {
4913 V = getUnpackl(DAG, dl, VT, V, V);
4915 V = getUnpackh(DAG, dl, VT, V, V);
4916 EltNo -= NumElems/2;
4923 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4924 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4925 MVT VT = V.getSimpleValueType();
4928 if (VT.is128BitVector()) {
4929 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4930 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4931 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4933 } else if (VT.is256BitVector()) {
4934 // To use VPERMILPS to splat scalars, the second half of indicies must
4935 // refer to the higher part, which is a duplication of the lower one,
4936 // because VPERMILPS can only handle in-lane permutations.
4937 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4938 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4940 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4941 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4944 llvm_unreachable("Vector size not supported");
4946 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4949 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4950 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4951 MVT SrcVT = SV->getSimpleValueType(0);
4952 SDValue V1 = SV->getOperand(0);
4955 int EltNo = SV->getSplatIndex();
4956 int NumElems = SrcVT.getVectorNumElements();
4957 bool Is256BitVec = SrcVT.is256BitVector();
4959 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4960 "Unknown how to promote splat for type");
4962 // Extract the 128-bit part containing the splat element and update
4963 // the splat element index when it refers to the higher register.
4965 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4966 if (EltNo >= NumElems/2)
4967 EltNo -= NumElems/2;
4970 // All i16 and i8 vector types can't be used directly by a generic shuffle
4971 // instruction because the target has no such instruction. Generate shuffles
4972 // which repeat i16 and i8 several times until they fit in i32, and then can
4973 // be manipulated by target suported shuffles.
4974 MVT EltVT = SrcVT.getVectorElementType();
4975 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4976 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4978 // Recreate the 256-bit vector and place the same 128-bit vector
4979 // into the low and high part. This is necessary because we want
4980 // to use VPERM* to shuffle the vectors
4982 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4985 return getLegalSplat(DAG, V1, EltNo);
4988 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4989 /// vector of zero or undef vector. This produces a shuffle where the low
4990 /// element of V2 is swizzled into the zero/undef vector, landing at element
4991 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4992 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4994 const X86Subtarget *Subtarget,
4995 SelectionDAG &DAG) {
4996 MVT VT = V2.getSimpleValueType();
4998 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4999 unsigned NumElems = VT.getVectorNumElements();
5000 SmallVector<int, 16> MaskVec;
5001 for (unsigned i = 0; i != NumElems; ++i)
5002 // If this is the insertion idx, put the low elt of V2 here.
5003 MaskVec.push_back(i == Idx ? NumElems : i);
5004 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5007 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5008 /// target specific opcode. Returns true if the Mask could be calculated.
5009 /// Sets IsUnary to true if only uses one source.
5010 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5011 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5012 unsigned NumElems = VT.getVectorNumElements();
5016 switch(N->getOpcode()) {
5018 ImmN = N->getOperand(N->getNumOperands()-1);
5019 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5021 case X86ISD::UNPCKH:
5022 DecodeUNPCKHMask(VT, Mask);
5024 case X86ISD::UNPCKL:
5025 DecodeUNPCKLMask(VT, Mask);
5027 case X86ISD::MOVHLPS:
5028 DecodeMOVHLPSMask(NumElems, Mask);
5030 case X86ISD::MOVLHPS:
5031 DecodeMOVLHPSMask(NumElems, Mask);
5033 case X86ISD::PALIGNR:
5034 ImmN = N->getOperand(N->getNumOperands()-1);
5035 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5037 case X86ISD::PSHUFD:
5038 case X86ISD::VPERMILP:
5039 ImmN = N->getOperand(N->getNumOperands()-1);
5040 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5043 case X86ISD::PSHUFHW:
5044 ImmN = N->getOperand(N->getNumOperands()-1);
5045 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5048 case X86ISD::PSHUFLW:
5049 ImmN = N->getOperand(N->getNumOperands()-1);
5050 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5053 case X86ISD::VPERMI:
5054 ImmN = N->getOperand(N->getNumOperands()-1);
5055 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5059 case X86ISD::MOVSD: {
5060 // The index 0 always comes from the first element of the second source,
5061 // this is why MOVSS and MOVSD are used in the first place. The other
5062 // elements come from the other positions of the first source vector
5063 Mask.push_back(NumElems);
5064 for (unsigned i = 1; i != NumElems; ++i) {
5069 case X86ISD::VPERM2X128:
5070 ImmN = N->getOperand(N->getNumOperands()-1);
5071 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5072 if (Mask.empty()) return false;
5074 case X86ISD::MOVDDUP:
5075 case X86ISD::MOVLHPD:
5076 case X86ISD::MOVLPD:
5077 case X86ISD::MOVLPS:
5078 case X86ISD::MOVSHDUP:
5079 case X86ISD::MOVSLDUP:
5080 // Not yet implemented
5082 default: llvm_unreachable("unknown target shuffle node");
5088 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5089 /// element of the result of the vector shuffle.
5090 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5093 return SDValue(); // Limit search depth.
5095 SDValue V = SDValue(N, 0);
5096 EVT VT = V.getValueType();
5097 unsigned Opcode = V.getOpcode();
5099 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5100 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5101 int Elt = SV->getMaskElt(Index);
5104 return DAG.getUNDEF(VT.getVectorElementType());
5106 unsigned NumElems = VT.getVectorNumElements();
5107 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5108 : SV->getOperand(1);
5109 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5112 // Recurse into target specific vector shuffles to find scalars.
5113 if (isTargetShuffle(Opcode)) {
5114 MVT ShufVT = V.getSimpleValueType();
5115 unsigned NumElems = ShufVT.getVectorNumElements();
5116 SmallVector<int, 16> ShuffleMask;
5119 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5122 int Elt = ShuffleMask[Index];
5124 return DAG.getUNDEF(ShufVT.getVectorElementType());
5126 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5128 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5132 // Actual nodes that may contain scalar elements
5133 if (Opcode == ISD::BITCAST) {
5134 V = V.getOperand(0);
5135 EVT SrcVT = V.getValueType();
5136 unsigned NumElems = VT.getVectorNumElements();
5138 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5142 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5143 return (Index == 0) ? V.getOperand(0)
5144 : DAG.getUNDEF(VT.getVectorElementType());
5146 if (V.getOpcode() == ISD::BUILD_VECTOR)
5147 return V.getOperand(Index);
5152 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5153 /// shuffle operation which come from a consecutively from a zero. The
5154 /// search can start in two different directions, from left or right.
5155 /// We count undefs as zeros until PreferredNum is reached.
5156 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5157 unsigned NumElems, bool ZerosFromLeft,
5159 unsigned PreferredNum = -1U) {
5160 unsigned NumZeros = 0;
5161 for (unsigned i = 0; i != NumElems; ++i) {
5162 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5163 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5167 if (X86::isZeroNode(Elt))
5169 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5170 NumZeros = std::min(NumZeros + 1, PreferredNum);
5178 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5179 /// correspond consecutively to elements from one of the vector operands,
5180 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5182 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5183 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5184 unsigned NumElems, unsigned &OpNum) {
5185 bool SeenV1 = false;
5186 bool SeenV2 = false;
5188 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5189 int Idx = SVOp->getMaskElt(i);
5190 // Ignore undef indicies
5194 if (Idx < (int)NumElems)
5199 // Only accept consecutive elements from the same vector
5200 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5204 OpNum = SeenV1 ? 0 : 1;
5208 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5209 /// logical left shift of a vector.
5210 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5211 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5213 SVOp->getSimpleValueType(0).getVectorNumElements();
5214 unsigned NumZeros = getNumOfConsecutiveZeros(
5215 SVOp, NumElems, false /* check zeros from right */, DAG,
5216 SVOp->getMaskElt(0));
5222 // Considering the elements in the mask that are not consecutive zeros,
5223 // check if they consecutively come from only one of the source vectors.
5225 // V1 = {X, A, B, C} 0
5227 // vector_shuffle V1, V2 <1, 2, 3, X>
5229 if (!isShuffleMaskConsecutive(SVOp,
5230 0, // Mask Start Index
5231 NumElems-NumZeros, // Mask End Index(exclusive)
5232 NumZeros, // Where to start looking in the src vector
5233 NumElems, // Number of elements in vector
5234 OpSrc)) // Which source operand ?
5239 ShVal = SVOp->getOperand(OpSrc);
5243 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5244 /// logical left shift of a vector.
5245 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5246 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5248 SVOp->getSimpleValueType(0).getVectorNumElements();
5249 unsigned NumZeros = getNumOfConsecutiveZeros(
5250 SVOp, NumElems, true /* check zeros from left */, DAG,
5251 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5257 // Considering the elements in the mask that are not consecutive zeros,
5258 // check if they consecutively come from only one of the source vectors.
5260 // 0 { A, B, X, X } = V2
5262 // vector_shuffle V1, V2 <X, X, 4, 5>
5264 if (!isShuffleMaskConsecutive(SVOp,
5265 NumZeros, // Mask Start Index
5266 NumElems, // Mask End Index(exclusive)
5267 0, // Where to start looking in the src vector
5268 NumElems, // Number of elements in vector
5269 OpSrc)) // Which source operand ?
5274 ShVal = SVOp->getOperand(OpSrc);
5278 /// isVectorShift - Returns true if the shuffle can be implemented as a
5279 /// logical left or right shift of a vector.
5280 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5281 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5282 // Although the logic below support any bitwidth size, there are no
5283 // shift instructions which handle more than 128-bit vectors.
5284 if (!SVOp->getSimpleValueType(0).is128BitVector())
5287 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5288 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5294 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5296 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5297 unsigned NumNonZero, unsigned NumZero,
5299 const X86Subtarget* Subtarget,
5300 const TargetLowering &TLI) {
5307 for (unsigned i = 0; i < 16; ++i) {
5308 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5309 if (ThisIsNonZero && First) {
5311 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5313 V = DAG.getUNDEF(MVT::v8i16);
5318 SDValue ThisElt(0, 0), LastElt(0, 0);
5319 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5320 if (LastIsNonZero) {
5321 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5322 MVT::i16, Op.getOperand(i-1));
5324 if (ThisIsNonZero) {
5325 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5326 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5327 ThisElt, DAG.getConstant(8, MVT::i8));
5329 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5333 if (ThisElt.getNode())
5334 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5335 DAG.getIntPtrConstant(i/2));
5339 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5342 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5344 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5345 unsigned NumNonZero, unsigned NumZero,
5347 const X86Subtarget* Subtarget,
5348 const TargetLowering &TLI) {
5355 for (unsigned i = 0; i < 8; ++i) {
5356 bool isNonZero = (NonZeros & (1 << i)) != 0;
5360 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5362 V = DAG.getUNDEF(MVT::v8i16);
5365 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5366 MVT::v8i16, V, Op.getOperand(i),
5367 DAG.getIntPtrConstant(i));
5374 /// getVShift - Return a vector logical shift node.
5376 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5377 unsigned NumBits, SelectionDAG &DAG,
5378 const TargetLowering &TLI, SDLoc dl) {
5379 assert(VT.is128BitVector() && "Unknown type for VShift");
5380 EVT ShVT = MVT::v2i64;
5381 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5382 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5383 return DAG.getNode(ISD::BITCAST, dl, VT,
5384 DAG.getNode(Opc, dl, ShVT, SrcOp,
5385 DAG.getConstant(NumBits,
5386 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5390 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5392 // Check if the scalar load can be widened into a vector load. And if
5393 // the address is "base + cst" see if the cst can be "absorbed" into
5394 // the shuffle mask.
5395 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5396 SDValue Ptr = LD->getBasePtr();
5397 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5399 EVT PVT = LD->getValueType(0);
5400 if (PVT != MVT::i32 && PVT != MVT::f32)
5405 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5406 FI = FINode->getIndex();
5408 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5409 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5410 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5411 Offset = Ptr.getConstantOperandVal(1);
5412 Ptr = Ptr.getOperand(0);
5417 // FIXME: 256-bit vector instructions don't require a strict alignment,
5418 // improve this code to support it better.
5419 unsigned RequiredAlign = VT.getSizeInBits()/8;
5420 SDValue Chain = LD->getChain();
5421 // Make sure the stack object alignment is at least 16 or 32.
5422 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5423 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5424 if (MFI->isFixedObjectIndex(FI)) {
5425 // Can't change the alignment. FIXME: It's possible to compute
5426 // the exact stack offset and reference FI + adjust offset instead.
5427 // If someone *really* cares about this. That's the way to implement it.
5430 MFI->setObjectAlignment(FI, RequiredAlign);
5434 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5435 // Ptr + (Offset & ~15).
5438 if ((Offset % RequiredAlign) & 3)
5440 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5442 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5443 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5445 int EltNo = (Offset - StartOffset) >> 2;
5446 unsigned NumElems = VT.getVectorNumElements();
5448 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5449 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5450 LD->getPointerInfo().getWithOffset(StartOffset),
5451 false, false, false, 0);
5453 SmallVector<int, 8> Mask;
5454 for (unsigned i = 0; i != NumElems; ++i)
5455 Mask.push_back(EltNo);
5457 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5463 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5464 /// vector of type 'VT', see if the elements can be replaced by a single large
5465 /// load which has the same value as a build_vector whose operands are 'elts'.
5467 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5469 /// FIXME: we'd also like to handle the case where the last elements are zero
5470 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5471 /// There's even a handy isZeroNode for that purpose.
5472 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5473 SDLoc &DL, SelectionDAG &DAG,
5474 bool isAfterLegalize) {
5475 EVT EltVT = VT.getVectorElementType();
5476 unsigned NumElems = Elts.size();
5478 LoadSDNode *LDBase = NULL;
5479 unsigned LastLoadedElt = -1U;
5481 // For each element in the initializer, see if we've found a load or an undef.
5482 // If we don't find an initial load element, or later load elements are
5483 // non-consecutive, bail out.
5484 for (unsigned i = 0; i < NumElems; ++i) {
5485 SDValue Elt = Elts[i];
5487 if (!Elt.getNode() ||
5488 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5491 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5493 LDBase = cast<LoadSDNode>(Elt.getNode());
5497 if (Elt.getOpcode() == ISD::UNDEF)
5500 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5501 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5506 // If we have found an entire vector of loads and undefs, then return a large
5507 // load of the entire vector width starting at the base pointer. If we found
5508 // consecutive loads for the low half, generate a vzext_load node.
5509 if (LastLoadedElt == NumElems - 1) {
5511 if (isAfterLegalize &&
5512 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5515 SDValue NewLd = SDValue();
5517 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5518 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5519 LDBase->getPointerInfo(),
5520 LDBase->isVolatile(), LDBase->isNonTemporal(),
5521 LDBase->isInvariant(), 0);
5522 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5523 LDBase->getPointerInfo(),
5524 LDBase->isVolatile(), LDBase->isNonTemporal(),
5525 LDBase->isInvariant(), LDBase->getAlignment());
5527 if (LDBase->hasAnyUseOfValue(1)) {
5528 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5530 SDValue(NewLd.getNode(), 1));
5531 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5532 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5533 SDValue(NewLd.getNode(), 1));
5538 if (NumElems == 4 && LastLoadedElt == 1 &&
5539 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5540 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5541 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5543 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5544 array_lengthof(Ops), MVT::i64,
5545 LDBase->getPointerInfo(),
5546 LDBase->getAlignment(),
5547 false/*isVolatile*/, true/*ReadMem*/,
5550 // Make sure the newly-created LOAD is in the same position as LDBase in
5551 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5552 // update uses of LDBase's output chain to use the TokenFactor.
5553 if (LDBase->hasAnyUseOfValue(1)) {
5554 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5555 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5556 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5557 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5558 SDValue(ResNode.getNode(), 1));
5561 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5566 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5567 /// to generate a splat value for the following cases:
5568 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5569 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5570 /// a scalar load, or a constant.
5571 /// The VBROADCAST node is returned when a pattern is found,
5572 /// or SDValue() otherwise.
5573 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5574 SelectionDAG &DAG) {
5575 if (!Subtarget->hasFp256())
5578 MVT VT = Op.getSimpleValueType();
5581 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5582 "Unsupported vector type for broadcast.");
5587 switch (Op.getOpcode()) {
5589 // Unknown pattern found.
5592 case ISD::BUILD_VECTOR: {
5593 // The BUILD_VECTOR node must be a splat.
5594 if (!isSplatVector(Op.getNode()))
5597 Ld = Op.getOperand(0);
5598 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5599 Ld.getOpcode() == ISD::ConstantFP);
5601 // The suspected load node has several users. Make sure that all
5602 // of its users are from the BUILD_VECTOR node.
5603 // Constants may have multiple users.
5604 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5609 case ISD::VECTOR_SHUFFLE: {
5610 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5612 // Shuffles must have a splat mask where the first element is
5614 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5617 SDValue Sc = Op.getOperand(0);
5618 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5619 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5621 if (!Subtarget->hasInt256())
5624 // Use the register form of the broadcast instruction available on AVX2.
5625 if (VT.getSizeInBits() >= 256)
5626 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5627 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5630 Ld = Sc.getOperand(0);
5631 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5632 Ld.getOpcode() == ISD::ConstantFP);
5634 // The scalar_to_vector node and the suspected
5635 // load node must have exactly one user.
5636 // Constants may have multiple users.
5638 // AVX-512 has register version of the broadcast
5639 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5640 Ld.getValueType().getSizeInBits() >= 32;
5641 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5648 bool IsGE256 = (VT.getSizeInBits() >= 256);
5650 // Handle the broadcasting a single constant scalar from the constant pool
5651 // into a vector. On Sandybridge it is still better to load a constant vector
5652 // from the constant pool and not to broadcast it from a scalar.
5653 if (ConstSplatVal && Subtarget->hasInt256()) {
5654 EVT CVT = Ld.getValueType();
5655 assert(!CVT.isVector() && "Must not broadcast a vector type");
5656 unsigned ScalarSize = CVT.getSizeInBits();
5658 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5659 const Constant *C = 0;
5660 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5661 C = CI->getConstantIntValue();
5662 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5663 C = CF->getConstantFPValue();
5665 assert(C && "Invalid constant type");
5667 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5668 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5669 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5670 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5671 MachinePointerInfo::getConstantPool(),
5672 false, false, false, Alignment);
5674 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5678 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5679 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5681 // Handle AVX2 in-register broadcasts.
5682 if (!IsLoad && Subtarget->hasInt256() &&
5683 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5684 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5686 // The scalar source must be a normal load.
5690 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5691 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5693 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5694 // double since there is no vbroadcastsd xmm
5695 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5696 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5697 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5700 // Unsupported broadcast.
5704 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5705 MVT VT = Op.getSimpleValueType();
5707 // Skip if insert_vec_elt is not supported.
5708 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5709 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5713 unsigned NumElems = Op.getNumOperands();
5717 SmallVector<unsigned, 4> InsertIndices;
5718 SmallVector<int, 8> Mask(NumElems, -1);
5720 for (unsigned i = 0; i != NumElems; ++i) {
5721 unsigned Opc = Op.getOperand(i).getOpcode();
5723 if (Opc == ISD::UNDEF)
5726 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5727 // Quit if more than 1 elements need inserting.
5728 if (InsertIndices.size() > 1)
5731 InsertIndices.push_back(i);
5735 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5736 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5738 // Quit if extracted from vector of different type.
5739 if (ExtractedFromVec.getValueType() != VT)
5742 // Quit if non-constant index.
5743 if (!isa<ConstantSDNode>(ExtIdx))
5746 if (VecIn1.getNode() == 0)
5747 VecIn1 = ExtractedFromVec;
5748 else if (VecIn1 != ExtractedFromVec) {
5749 if (VecIn2.getNode() == 0)
5750 VecIn2 = ExtractedFromVec;
5751 else if (VecIn2 != ExtractedFromVec)
5752 // Quit if more than 2 vectors to shuffle
5756 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5758 if (ExtractedFromVec == VecIn1)
5760 else if (ExtractedFromVec == VecIn2)
5761 Mask[i] = Idx + NumElems;
5764 if (VecIn1.getNode() == 0)
5767 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5768 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5769 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5770 unsigned Idx = InsertIndices[i];
5771 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5772 DAG.getIntPtrConstant(Idx));
5778 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5780 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5782 MVT VT = Op.getSimpleValueType();
5783 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5784 "Unexpected type in LowerBUILD_VECTORvXi1!");
5787 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5788 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5789 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5790 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5791 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5792 Ops, VT.getVectorNumElements());
5795 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5796 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5797 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5798 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5799 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5800 Ops, VT.getVectorNumElements());
5803 bool AllContants = true;
5804 uint64_t Immediate = 0;
5805 int NonConstIdx = -1;
5806 bool IsSplat = true;
5807 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5808 SDValue In = Op.getOperand(idx);
5809 if (In.getOpcode() == ISD::UNDEF)
5811 if (!isa<ConstantSDNode>(In)) {
5812 AllContants = false;
5815 else if (cast<ConstantSDNode>(In)->getZExtValue())
5816 Immediate |= (1ULL << idx);
5817 if (In != Op.getOperand(0))
5822 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5823 DAG.getConstant(Immediate, MVT::i16));
5824 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5825 DAG.getIntPtrConstant(0));
5828 if (!IsSplat && (NonConstIdx != 0))
5829 llvm_unreachable("Unsupported BUILD_VECTOR operation");
5830 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
5833 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5834 DAG.getConstant(-1, SelectVT),
5835 DAG.getConstant(0, SelectVT));
5837 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5838 DAG.getConstant((Immediate | 1), SelectVT),
5839 DAG.getConstant(Immediate, SelectVT));
5840 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
5844 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5847 MVT VT = Op.getSimpleValueType();
5848 MVT ExtVT = VT.getVectorElementType();
5849 unsigned NumElems = Op.getNumOperands();
5851 // Generate vectors for predicate vectors.
5852 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5853 return LowerBUILD_VECTORvXi1(Op, DAG);
5855 // Vectors containing all zeros can be matched by pxor and xorps later
5856 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5857 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5858 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5859 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5862 return getZeroVector(VT, Subtarget, DAG, dl);
5865 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5866 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5867 // vpcmpeqd on 256-bit vectors.
5868 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5869 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5872 if (!VT.is512BitVector())
5873 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5876 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5877 if (Broadcast.getNode())
5880 unsigned EVTBits = ExtVT.getSizeInBits();
5882 unsigned NumZero = 0;
5883 unsigned NumNonZero = 0;
5884 unsigned NonZeros = 0;
5885 bool IsAllConstants = true;
5886 SmallSet<SDValue, 8> Values;
5887 for (unsigned i = 0; i < NumElems; ++i) {
5888 SDValue Elt = Op.getOperand(i);
5889 if (Elt.getOpcode() == ISD::UNDEF)
5892 if (Elt.getOpcode() != ISD::Constant &&
5893 Elt.getOpcode() != ISD::ConstantFP)
5894 IsAllConstants = false;
5895 if (X86::isZeroNode(Elt))
5898 NonZeros |= (1 << i);
5903 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5904 if (NumNonZero == 0)
5905 return DAG.getUNDEF(VT);
5907 // Special case for single non-zero, non-undef, element.
5908 if (NumNonZero == 1) {
5909 unsigned Idx = countTrailingZeros(NonZeros);
5910 SDValue Item = Op.getOperand(Idx);
5912 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5913 // the value are obviously zero, truncate the value to i32 and do the
5914 // insertion that way. Only do this if the value is non-constant or if the
5915 // value is a constant being inserted into element 0. It is cheaper to do
5916 // a constant pool load than it is to do a movd + shuffle.
5917 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5918 (!IsAllConstants || Idx == 0)) {
5919 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5921 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5922 EVT VecVT = MVT::v4i32;
5923 unsigned VecElts = 4;
5925 // Truncate the value (which may itself be a constant) to i32, and
5926 // convert it to a vector with movd (S2V+shuffle to zero extend).
5927 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5928 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5929 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5931 // Now we have our 32-bit value zero extended in the low element of
5932 // a vector. If Idx != 0, swizzle it into place.
5934 SmallVector<int, 4> Mask;
5935 Mask.push_back(Idx);
5936 for (unsigned i = 1; i != VecElts; ++i)
5938 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5941 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5945 // If we have a constant or non-constant insertion into the low element of
5946 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5947 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5948 // depending on what the source datatype is.
5951 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5953 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5954 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5955 if (VT.is256BitVector() || VT.is512BitVector()) {
5956 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5957 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5958 Item, DAG.getIntPtrConstant(0));
5960 assert(VT.is128BitVector() && "Expected an SSE value type!");
5961 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5962 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5963 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5966 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5967 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5968 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5969 if (VT.is256BitVector()) {
5970 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5971 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5973 assert(VT.is128BitVector() && "Expected an SSE value type!");
5974 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5976 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5980 // Is it a vector logical left shift?
5981 if (NumElems == 2 && Idx == 1 &&
5982 X86::isZeroNode(Op.getOperand(0)) &&
5983 !X86::isZeroNode(Op.getOperand(1))) {
5984 unsigned NumBits = VT.getSizeInBits();
5985 return getVShift(true, VT,
5986 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5987 VT, Op.getOperand(1)),
5988 NumBits/2, DAG, *this, dl);
5991 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5994 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5995 // is a non-constant being inserted into an element other than the low one,
5996 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5997 // movd/movss) to move this into the low element, then shuffle it into
5999 if (EVTBits == 32) {
6000 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6002 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6003 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6004 SmallVector<int, 8> MaskVec;
6005 for (unsigned i = 0; i != NumElems; ++i)
6006 MaskVec.push_back(i == Idx ? 0 : 1);
6007 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6011 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6012 if (Values.size() == 1) {
6013 if (EVTBits == 32) {
6014 // Instead of a shuffle like this:
6015 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6016 // Check if it's possible to issue this instead.
6017 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6018 unsigned Idx = countTrailingZeros(NonZeros);
6019 SDValue Item = Op.getOperand(Idx);
6020 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6021 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6026 // A vector full of immediates; various special cases are already
6027 // handled, so this is best done with a single constant-pool load.
6031 // For AVX-length vectors, build the individual 128-bit pieces and use
6032 // shuffles to put them in place.
6033 if (VT.is256BitVector() || VT.is512BitVector()) {
6034 SmallVector<SDValue, 64> V;
6035 for (unsigned i = 0; i != NumElems; ++i)
6036 V.push_back(Op.getOperand(i));
6038 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6040 // Build both the lower and upper subvector.
6041 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
6042 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
6045 // Recreate the wider vector with the lower and upper part.
6046 if (VT.is256BitVector())
6047 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6048 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6051 // Let legalizer expand 2-wide build_vectors.
6052 if (EVTBits == 64) {
6053 if (NumNonZero == 1) {
6054 // One half is zero or undef.
6055 unsigned Idx = countTrailingZeros(NonZeros);
6056 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6057 Op.getOperand(Idx));
6058 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6063 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6064 if (EVTBits == 8 && NumElems == 16) {
6065 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6067 if (V.getNode()) return V;
6070 if (EVTBits == 16 && NumElems == 8) {
6071 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6073 if (V.getNode()) return V;
6076 // If element VT is == 32 bits, turn it into a number of shuffles.
6077 SmallVector<SDValue, 8> V(NumElems);
6078 if (NumElems == 4 && NumZero > 0) {
6079 for (unsigned i = 0; i < 4; ++i) {
6080 bool isZero = !(NonZeros & (1 << i));
6082 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6084 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6087 for (unsigned i = 0; i < 2; ++i) {
6088 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6091 V[i] = V[i*2]; // Must be a zero vector.
6094 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6097 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6100 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6105 bool Reverse1 = (NonZeros & 0x3) == 2;
6106 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6110 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6111 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6113 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6116 if (Values.size() > 1 && VT.is128BitVector()) {
6117 // Check for a build vector of consecutive loads.
6118 for (unsigned i = 0; i < NumElems; ++i)
6119 V[i] = Op.getOperand(i);
6121 // Check for elements which are consecutive loads.
6122 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6126 // Check for a build vector from mostly shuffle plus few inserting.
6127 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6131 // For SSE 4.1, use insertps to put the high elements into the low element.
6132 if (getSubtarget()->hasSSE41()) {
6134 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6135 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6137 Result = DAG.getUNDEF(VT);
6139 for (unsigned i = 1; i < NumElems; ++i) {
6140 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6141 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6142 Op.getOperand(i), DAG.getIntPtrConstant(i));
6147 // Otherwise, expand into a number of unpckl*, start by extending each of
6148 // our (non-undef) elements to the full vector width with the element in the
6149 // bottom slot of the vector (which generates no code for SSE).
6150 for (unsigned i = 0; i < NumElems; ++i) {
6151 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6152 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6154 V[i] = DAG.getUNDEF(VT);
6157 // Next, we iteratively mix elements, e.g. for v4f32:
6158 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6159 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6160 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6161 unsigned EltStride = NumElems >> 1;
6162 while (EltStride != 0) {
6163 for (unsigned i = 0; i < EltStride; ++i) {
6164 // If V[i+EltStride] is undef and this is the first round of mixing,
6165 // then it is safe to just drop this shuffle: V[i] is already in the
6166 // right place, the one element (since it's the first round) being
6167 // inserted as undef can be dropped. This isn't safe for successive
6168 // rounds because they will permute elements within both vectors.
6169 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6170 EltStride == NumElems/2)
6173 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6182 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6183 // to create 256-bit vectors from two other 128-bit ones.
6184 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6186 MVT ResVT = Op.getSimpleValueType();
6188 assert((ResVT.is256BitVector() ||
6189 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6191 SDValue V1 = Op.getOperand(0);
6192 SDValue V2 = Op.getOperand(1);
6193 unsigned NumElems = ResVT.getVectorNumElements();
6194 if(ResVT.is256BitVector())
6195 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6197 if (Op.getNumOperands() == 4) {
6198 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6199 ResVT.getVectorNumElements()/2);
6200 SDValue V3 = Op.getOperand(2);
6201 SDValue V4 = Op.getOperand(3);
6202 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6203 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6205 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6208 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6209 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6210 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6211 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6212 Op.getNumOperands() == 4)));
6214 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6215 // from two other 128-bit ones.
6217 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6218 return LowerAVXCONCAT_VECTORS(Op, DAG);
6221 // Try to lower a shuffle node into a simple blend instruction.
6223 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6224 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6225 SDValue V1 = SVOp->getOperand(0);
6226 SDValue V2 = SVOp->getOperand(1);
6228 MVT VT = SVOp->getSimpleValueType(0);
6229 MVT EltVT = VT.getVectorElementType();
6230 unsigned NumElems = VT.getVectorNumElements();
6232 // There is no blend with immediate in AVX-512.
6233 if (VT.is512BitVector())
6236 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6238 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6241 // Check the mask for BLEND and build the value.
6242 unsigned MaskValue = 0;
6243 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6244 unsigned NumLanes = (NumElems-1)/8 + 1;
6245 unsigned NumElemsInLane = NumElems / NumLanes;
6247 // Blend for v16i16 should be symetric for the both lanes.
6248 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6250 int SndLaneEltIdx = (NumLanes == 2) ?
6251 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6252 int EltIdx = SVOp->getMaskElt(i);
6254 if ((EltIdx < 0 || EltIdx == (int)i) &&
6255 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6258 if (((unsigned)EltIdx == (i + NumElems)) &&
6259 (SndLaneEltIdx < 0 ||
6260 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6261 MaskValue |= (1<<i);
6266 // Convert i32 vectors to floating point if it is not AVX2.
6267 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6269 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6270 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6272 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6273 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6276 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6277 DAG.getConstant(MaskValue, MVT::i32));
6278 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6281 // v8i16 shuffles - Prefer shuffles in the following order:
6282 // 1. [all] pshuflw, pshufhw, optional move
6283 // 2. [ssse3] 1 x pshufb
6284 // 3. [ssse3] 2 x pshufb + 1 x por
6285 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6287 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6288 SelectionDAG &DAG) {
6289 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6290 SDValue V1 = SVOp->getOperand(0);
6291 SDValue V2 = SVOp->getOperand(1);
6293 SmallVector<int, 8> MaskVals;
6295 // Determine if more than 1 of the words in each of the low and high quadwords
6296 // of the result come from the same quadword of one of the two inputs. Undef
6297 // mask values count as coming from any quadword, for better codegen.
6298 unsigned LoQuad[] = { 0, 0, 0, 0 };
6299 unsigned HiQuad[] = { 0, 0, 0, 0 };
6300 std::bitset<4> InputQuads;
6301 for (unsigned i = 0; i < 8; ++i) {
6302 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6303 int EltIdx = SVOp->getMaskElt(i);
6304 MaskVals.push_back(EltIdx);
6313 InputQuads.set(EltIdx / 4);
6316 int BestLoQuad = -1;
6317 unsigned MaxQuad = 1;
6318 for (unsigned i = 0; i < 4; ++i) {
6319 if (LoQuad[i] > MaxQuad) {
6321 MaxQuad = LoQuad[i];
6325 int BestHiQuad = -1;
6327 for (unsigned i = 0; i < 4; ++i) {
6328 if (HiQuad[i] > MaxQuad) {
6330 MaxQuad = HiQuad[i];
6334 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6335 // of the two input vectors, shuffle them into one input vector so only a
6336 // single pshufb instruction is necessary. If There are more than 2 input
6337 // quads, disable the next transformation since it does not help SSSE3.
6338 bool V1Used = InputQuads[0] || InputQuads[1];
6339 bool V2Used = InputQuads[2] || InputQuads[3];
6340 if (Subtarget->hasSSSE3()) {
6341 if (InputQuads.count() == 2 && V1Used && V2Used) {
6342 BestLoQuad = InputQuads[0] ? 0 : 1;
6343 BestHiQuad = InputQuads[2] ? 2 : 3;
6345 if (InputQuads.count() > 2) {
6351 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6352 // the shuffle mask. If a quad is scored as -1, that means that it contains
6353 // words from all 4 input quadwords.
6355 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6357 BestLoQuad < 0 ? 0 : BestLoQuad,
6358 BestHiQuad < 0 ? 1 : BestHiQuad
6360 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6361 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6362 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6363 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6365 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6366 // source words for the shuffle, to aid later transformations.
6367 bool AllWordsInNewV = true;
6368 bool InOrder[2] = { true, true };
6369 for (unsigned i = 0; i != 8; ++i) {
6370 int idx = MaskVals[i];
6372 InOrder[i/4] = false;
6373 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6375 AllWordsInNewV = false;
6379 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6380 if (AllWordsInNewV) {
6381 for (int i = 0; i != 8; ++i) {
6382 int idx = MaskVals[i];
6385 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6386 if ((idx != i) && idx < 4)
6388 if ((idx != i) && idx > 3)
6397 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6398 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6399 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6400 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6401 unsigned TargetMask = 0;
6402 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6403 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6404 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6405 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6406 getShufflePSHUFLWImmediate(SVOp);
6407 V1 = NewV.getOperand(0);
6408 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6412 // Promote splats to a larger type which usually leads to more efficient code.
6413 // FIXME: Is this true if pshufb is available?
6414 if (SVOp->isSplat())
6415 return PromoteSplat(SVOp, DAG);
6417 // If we have SSSE3, and all words of the result are from 1 input vector,
6418 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6419 // is present, fall back to case 4.
6420 if (Subtarget->hasSSSE3()) {
6421 SmallVector<SDValue,16> pshufbMask;
6423 // If we have elements from both input vectors, set the high bit of the
6424 // shuffle mask element to zero out elements that come from V2 in the V1
6425 // mask, and elements that come from V1 in the V2 mask, so that the two
6426 // results can be OR'd together.
6427 bool TwoInputs = V1Used && V2Used;
6428 for (unsigned i = 0; i != 8; ++i) {
6429 int EltIdx = MaskVals[i] * 2;
6430 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6431 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6432 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6433 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6435 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6436 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6437 DAG.getNode(ISD::BUILD_VECTOR, dl,
6438 MVT::v16i8, &pshufbMask[0], 16));
6440 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6442 // Calculate the shuffle mask for the second input, shuffle it, and
6443 // OR it with the first shuffled input.
6445 for (unsigned i = 0; i != 8; ++i) {
6446 int EltIdx = MaskVals[i] * 2;
6447 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6448 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6449 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6450 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6452 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6453 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6454 DAG.getNode(ISD::BUILD_VECTOR, dl,
6455 MVT::v16i8, &pshufbMask[0], 16));
6456 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6457 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6460 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6461 // and update MaskVals with new element order.
6462 std::bitset<8> InOrder;
6463 if (BestLoQuad >= 0) {
6464 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6465 for (int i = 0; i != 4; ++i) {
6466 int idx = MaskVals[i];
6469 } else if ((idx / 4) == BestLoQuad) {
6474 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6477 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6478 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6479 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6481 getShufflePSHUFLWImmediate(SVOp), DAG);
6485 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6486 // and update MaskVals with the new element order.
6487 if (BestHiQuad >= 0) {
6488 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6489 for (unsigned i = 4; i != 8; ++i) {
6490 int idx = MaskVals[i];
6493 } else if ((idx / 4) == BestHiQuad) {
6494 MaskV[i] = (idx & 3) + 4;
6498 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6501 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6502 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6503 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6505 getShufflePSHUFHWImmediate(SVOp), DAG);
6509 // In case BestHi & BestLo were both -1, which means each quadword has a word
6510 // from each of the four input quadwords, calculate the InOrder bitvector now
6511 // before falling through to the insert/extract cleanup.
6512 if (BestLoQuad == -1 && BestHiQuad == -1) {
6514 for (int i = 0; i != 8; ++i)
6515 if (MaskVals[i] < 0 || MaskVals[i] == i)
6519 // The other elements are put in the right place using pextrw and pinsrw.
6520 for (unsigned i = 0; i != 8; ++i) {
6523 int EltIdx = MaskVals[i];
6526 SDValue ExtOp = (EltIdx < 8) ?
6527 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6528 DAG.getIntPtrConstant(EltIdx)) :
6529 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6530 DAG.getIntPtrConstant(EltIdx - 8));
6531 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6532 DAG.getIntPtrConstant(i));
6537 // v16i8 shuffles - Prefer shuffles in the following order:
6538 // 1. [ssse3] 1 x pshufb
6539 // 2. [ssse3] 2 x pshufb + 1 x por
6540 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6541 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6542 const X86Subtarget* Subtarget,
6543 SelectionDAG &DAG) {
6544 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6545 SDValue V1 = SVOp->getOperand(0);
6546 SDValue V2 = SVOp->getOperand(1);
6548 ArrayRef<int> MaskVals = SVOp->getMask();
6550 // Promote splats to a larger type which usually leads to more efficient code.
6551 // FIXME: Is this true if pshufb is available?
6552 if (SVOp->isSplat())
6553 return PromoteSplat(SVOp, DAG);
6555 // If we have SSSE3, case 1 is generated when all result bytes come from
6556 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6557 // present, fall back to case 3.
6559 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6560 if (Subtarget->hasSSSE3()) {
6561 SmallVector<SDValue,16> pshufbMask;
6563 // If all result elements are from one input vector, then only translate
6564 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6566 // Otherwise, we have elements from both input vectors, and must zero out
6567 // elements that come from V2 in the first mask, and V1 in the second mask
6568 // so that we can OR them together.
6569 for (unsigned i = 0; i != 16; ++i) {
6570 int EltIdx = MaskVals[i];
6571 if (EltIdx < 0 || EltIdx >= 16)
6573 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6575 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6576 DAG.getNode(ISD::BUILD_VECTOR, dl,
6577 MVT::v16i8, &pshufbMask[0], 16));
6579 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6580 // the 2nd operand if it's undefined or zero.
6581 if (V2.getOpcode() == ISD::UNDEF ||
6582 ISD::isBuildVectorAllZeros(V2.getNode()))
6585 // Calculate the shuffle mask for the second input, shuffle it, and
6586 // OR it with the first shuffled input.
6588 for (unsigned i = 0; i != 16; ++i) {
6589 int EltIdx = MaskVals[i];
6590 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6591 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6593 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6594 DAG.getNode(ISD::BUILD_VECTOR, dl,
6595 MVT::v16i8, &pshufbMask[0], 16));
6596 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6599 // No SSSE3 - Calculate in place words and then fix all out of place words
6600 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6601 // the 16 different words that comprise the two doublequadword input vectors.
6602 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6603 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6605 for (int i = 0; i != 8; ++i) {
6606 int Elt0 = MaskVals[i*2];
6607 int Elt1 = MaskVals[i*2+1];
6609 // This word of the result is all undef, skip it.
6610 if (Elt0 < 0 && Elt1 < 0)
6613 // This word of the result is already in the correct place, skip it.
6614 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6617 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6618 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6621 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6622 // using a single extract together, load it and store it.
6623 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6624 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6625 DAG.getIntPtrConstant(Elt1 / 2));
6626 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6627 DAG.getIntPtrConstant(i));
6631 // If Elt1 is defined, extract it from the appropriate source. If the
6632 // source byte is not also odd, shift the extracted word left 8 bits
6633 // otherwise clear the bottom 8 bits if we need to do an or.
6635 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6636 DAG.getIntPtrConstant(Elt1 / 2));
6637 if ((Elt1 & 1) == 0)
6638 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6640 TLI.getShiftAmountTy(InsElt.getValueType())));
6642 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6643 DAG.getConstant(0xFF00, MVT::i16));
6645 // If Elt0 is defined, extract it from the appropriate source. If the
6646 // source byte is not also even, shift the extracted word right 8 bits. If
6647 // Elt1 was also defined, OR the extracted values together before
6648 // inserting them in the result.
6650 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6651 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6652 if ((Elt0 & 1) != 0)
6653 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6655 TLI.getShiftAmountTy(InsElt0.getValueType())));
6657 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6658 DAG.getConstant(0x00FF, MVT::i16));
6659 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6662 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6663 DAG.getIntPtrConstant(i));
6665 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6668 // v32i8 shuffles - Translate to VPSHUFB if possible.
6670 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6671 const X86Subtarget *Subtarget,
6672 SelectionDAG &DAG) {
6673 MVT VT = SVOp->getSimpleValueType(0);
6674 SDValue V1 = SVOp->getOperand(0);
6675 SDValue V2 = SVOp->getOperand(1);
6677 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6679 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6680 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6681 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6683 // VPSHUFB may be generated if
6684 // (1) one of input vector is undefined or zeroinitializer.
6685 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6686 // And (2) the mask indexes don't cross the 128-bit lane.
6687 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6688 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6691 if (V1IsAllZero && !V2IsAllZero) {
6692 CommuteVectorShuffleMask(MaskVals, 32);
6695 SmallVector<SDValue, 32> pshufbMask;
6696 for (unsigned i = 0; i != 32; i++) {
6697 int EltIdx = MaskVals[i];
6698 if (EltIdx < 0 || EltIdx >= 32)
6701 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6702 // Cross lane is not allowed.
6706 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6708 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6709 DAG.getNode(ISD::BUILD_VECTOR, dl,
6710 MVT::v32i8, &pshufbMask[0], 32));
6713 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6714 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6715 /// done when every pair / quad of shuffle mask elements point to elements in
6716 /// the right sequence. e.g.
6717 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6719 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6720 SelectionDAG &DAG) {
6721 MVT VT = SVOp->getSimpleValueType(0);
6723 unsigned NumElems = VT.getVectorNumElements();
6726 switch (VT.SimpleTy) {
6727 default: llvm_unreachable("Unexpected!");
6728 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6729 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6730 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6731 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6732 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6733 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6736 SmallVector<int, 8> MaskVec;
6737 for (unsigned i = 0; i != NumElems; i += Scale) {
6739 for (unsigned j = 0; j != Scale; ++j) {
6740 int EltIdx = SVOp->getMaskElt(i+j);
6744 StartIdx = (EltIdx / Scale);
6745 if (EltIdx != (int)(StartIdx*Scale + j))
6748 MaskVec.push_back(StartIdx);
6751 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6752 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6753 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6756 /// getVZextMovL - Return a zero-extending vector move low node.
6758 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6759 SDValue SrcOp, SelectionDAG &DAG,
6760 const X86Subtarget *Subtarget, SDLoc dl) {
6761 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6762 LoadSDNode *LD = NULL;
6763 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6764 LD = dyn_cast<LoadSDNode>(SrcOp);
6766 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6768 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6769 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6770 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6771 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6772 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6774 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6775 return DAG.getNode(ISD::BITCAST, dl, VT,
6776 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6777 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6785 return DAG.getNode(ISD::BITCAST, dl, VT,
6786 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6787 DAG.getNode(ISD::BITCAST, dl,
6791 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6792 /// which could not be matched by any known target speficic shuffle
6794 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6796 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6797 if (NewOp.getNode())
6800 MVT VT = SVOp->getSimpleValueType(0);
6802 unsigned NumElems = VT.getVectorNumElements();
6803 unsigned NumLaneElems = NumElems / 2;
6806 MVT EltVT = VT.getVectorElementType();
6807 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6810 SmallVector<int, 16> Mask;
6811 for (unsigned l = 0; l < 2; ++l) {
6812 // Build a shuffle mask for the output, discovering on the fly which
6813 // input vectors to use as shuffle operands (recorded in InputUsed).
6814 // If building a suitable shuffle vector proves too hard, then bail
6815 // out with UseBuildVector set.
6816 bool UseBuildVector = false;
6817 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6818 unsigned LaneStart = l * NumLaneElems;
6819 for (unsigned i = 0; i != NumLaneElems; ++i) {
6820 // The mask element. This indexes into the input.
6821 int Idx = SVOp->getMaskElt(i+LaneStart);
6823 // the mask element does not index into any input vector.
6828 // The input vector this mask element indexes into.
6829 int Input = Idx / NumLaneElems;
6831 // Turn the index into an offset from the start of the input vector.
6832 Idx -= Input * NumLaneElems;
6834 // Find or create a shuffle vector operand to hold this input.
6836 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6837 if (InputUsed[OpNo] == Input)
6838 // This input vector is already an operand.
6840 if (InputUsed[OpNo] < 0) {
6841 // Create a new operand for this input vector.
6842 InputUsed[OpNo] = Input;
6847 if (OpNo >= array_lengthof(InputUsed)) {
6848 // More than two input vectors used! Give up on trying to create a
6849 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6850 UseBuildVector = true;
6854 // Add the mask index for the new shuffle vector.
6855 Mask.push_back(Idx + OpNo * NumLaneElems);
6858 if (UseBuildVector) {
6859 SmallVector<SDValue, 16> SVOps;
6860 for (unsigned i = 0; i != NumLaneElems; ++i) {
6861 // The mask element. This indexes into the input.
6862 int Idx = SVOp->getMaskElt(i+LaneStart);
6864 SVOps.push_back(DAG.getUNDEF(EltVT));
6868 // The input vector this mask element indexes into.
6869 int Input = Idx / NumElems;
6871 // Turn the index into an offset from the start of the input vector.
6872 Idx -= Input * NumElems;
6874 // Extract the vector element by hand.
6875 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6876 SVOp->getOperand(Input),
6877 DAG.getIntPtrConstant(Idx)));
6880 // Construct the output using a BUILD_VECTOR.
6881 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6883 } else if (InputUsed[0] < 0) {
6884 // No input vectors were used! The result is undefined.
6885 Output[l] = DAG.getUNDEF(NVT);
6887 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6888 (InputUsed[0] % 2) * NumLaneElems,
6890 // If only one input was used, use an undefined vector for the other.
6891 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6892 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6893 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6894 // At least one input vector was used. Create a new shuffle vector.
6895 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6901 // Concatenate the result back
6902 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6905 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6906 /// 4 elements, and match them with several different shuffle types.
6908 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6909 SDValue V1 = SVOp->getOperand(0);
6910 SDValue V2 = SVOp->getOperand(1);
6912 MVT VT = SVOp->getSimpleValueType(0);
6914 assert(VT.is128BitVector() && "Unsupported vector size");
6916 std::pair<int, int> Locs[4];
6917 int Mask1[] = { -1, -1, -1, -1 };
6918 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6922 for (unsigned i = 0; i != 4; ++i) {
6923 int Idx = PermMask[i];
6925 Locs[i] = std::make_pair(-1, -1);
6927 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6929 Locs[i] = std::make_pair(0, NumLo);
6933 Locs[i] = std::make_pair(1, NumHi);
6935 Mask1[2+NumHi] = Idx;
6941 if (NumLo <= 2 && NumHi <= 2) {
6942 // If no more than two elements come from either vector. This can be
6943 // implemented with two shuffles. First shuffle gather the elements.
6944 // The second shuffle, which takes the first shuffle as both of its
6945 // vector operands, put the elements into the right order.
6946 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6948 int Mask2[] = { -1, -1, -1, -1 };
6950 for (unsigned i = 0; i != 4; ++i)
6951 if (Locs[i].first != -1) {
6952 unsigned Idx = (i < 2) ? 0 : 4;
6953 Idx += Locs[i].first * 2 + Locs[i].second;
6957 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6960 if (NumLo == 3 || NumHi == 3) {
6961 // Otherwise, we must have three elements from one vector, call it X, and
6962 // one element from the other, call it Y. First, use a shufps to build an
6963 // intermediate vector with the one element from Y and the element from X
6964 // that will be in the same half in the final destination (the indexes don't
6965 // matter). Then, use a shufps to build the final vector, taking the half
6966 // containing the element from Y from the intermediate, and the other half
6969 // Normalize it so the 3 elements come from V1.
6970 CommuteVectorShuffleMask(PermMask, 4);
6974 // Find the element from V2.
6976 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6977 int Val = PermMask[HiIndex];
6984 Mask1[0] = PermMask[HiIndex];
6986 Mask1[2] = PermMask[HiIndex^1];
6988 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6991 Mask1[0] = PermMask[0];
6992 Mask1[1] = PermMask[1];
6993 Mask1[2] = HiIndex & 1 ? 6 : 4;
6994 Mask1[3] = HiIndex & 1 ? 4 : 6;
6995 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6998 Mask1[0] = HiIndex & 1 ? 2 : 0;
6999 Mask1[1] = HiIndex & 1 ? 0 : 2;
7000 Mask1[2] = PermMask[2];
7001 Mask1[3] = PermMask[3];
7006 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
7009 // Break it into (shuffle shuffle_hi, shuffle_lo).
7010 int LoMask[] = { -1, -1, -1, -1 };
7011 int HiMask[] = { -1, -1, -1, -1 };
7013 int *MaskPtr = LoMask;
7014 unsigned MaskIdx = 0;
7017 for (unsigned i = 0; i != 4; ++i) {
7024 int Idx = PermMask[i];
7026 Locs[i] = std::make_pair(-1, -1);
7027 } else if (Idx < 4) {
7028 Locs[i] = std::make_pair(MaskIdx, LoIdx);
7029 MaskPtr[LoIdx] = Idx;
7032 Locs[i] = std::make_pair(MaskIdx, HiIdx);
7033 MaskPtr[HiIdx] = Idx;
7038 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
7039 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
7040 int MaskOps[] = { -1, -1, -1, -1 };
7041 for (unsigned i = 0; i != 4; ++i)
7042 if (Locs[i].first != -1)
7043 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
7044 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
7047 static bool MayFoldVectorLoad(SDValue V) {
7048 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
7049 V = V.getOperand(0);
7051 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7052 V = V.getOperand(0);
7053 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7054 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7055 // BUILD_VECTOR (load), undef
7056 V = V.getOperand(0);
7058 return MayFoldLoad(V);
7062 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7063 MVT VT = Op.getSimpleValueType();
7065 // Canonizalize to v2f64.
7066 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7067 return DAG.getNode(ISD::BITCAST, dl, VT,
7068 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7073 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7075 SDValue V1 = Op.getOperand(0);
7076 SDValue V2 = Op.getOperand(1);
7077 MVT VT = Op.getSimpleValueType();
7079 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7081 if (HasSSE2 && VT == MVT::v2f64)
7082 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7084 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7085 return DAG.getNode(ISD::BITCAST, dl, VT,
7086 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7087 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7088 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7092 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7093 SDValue V1 = Op.getOperand(0);
7094 SDValue V2 = Op.getOperand(1);
7095 MVT VT = Op.getSimpleValueType();
7097 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7098 "unsupported shuffle type");
7100 if (V2.getOpcode() == ISD::UNDEF)
7104 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7108 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7109 SDValue V1 = Op.getOperand(0);
7110 SDValue V2 = Op.getOperand(1);
7111 MVT VT = Op.getSimpleValueType();
7112 unsigned NumElems = VT.getVectorNumElements();
7114 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7115 // operand of these instructions is only memory, so check if there's a
7116 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7118 bool CanFoldLoad = false;
7120 // Trivial case, when V2 comes from a load.
7121 if (MayFoldVectorLoad(V2))
7124 // When V1 is a load, it can be folded later into a store in isel, example:
7125 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7127 // (MOVLPSmr addr:$src1, VR128:$src2)
7128 // So, recognize this potential and also use MOVLPS or MOVLPD
7129 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7132 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7134 if (HasSSE2 && NumElems == 2)
7135 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7138 // If we don't care about the second element, proceed to use movss.
7139 if (SVOp->getMaskElt(1) != -1)
7140 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7143 // movl and movlp will both match v2i64, but v2i64 is never matched by
7144 // movl earlier because we make it strict to avoid messing with the movlp load
7145 // folding logic (see the code above getMOVLP call). Match it here then,
7146 // this is horrible, but will stay like this until we move all shuffle
7147 // matching to x86 specific nodes. Note that for the 1st condition all
7148 // types are matched with movsd.
7150 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7151 // as to remove this logic from here, as much as possible
7152 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7153 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7154 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7157 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7159 // Invert the operand order and use SHUFPS to match it.
7160 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7161 getShuffleSHUFImmediate(SVOp), DAG);
7164 // Reduce a vector shuffle to zext.
7165 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7166 SelectionDAG &DAG) {
7167 // PMOVZX is only available from SSE41.
7168 if (!Subtarget->hasSSE41())
7171 MVT VT = Op.getSimpleValueType();
7173 // Only AVX2 support 256-bit vector integer extending.
7174 if (!Subtarget->hasInt256() && VT.is256BitVector())
7177 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7179 SDValue V1 = Op.getOperand(0);
7180 SDValue V2 = Op.getOperand(1);
7181 unsigned NumElems = VT.getVectorNumElements();
7183 // Extending is an unary operation and the element type of the source vector
7184 // won't be equal to or larger than i64.
7185 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7186 VT.getVectorElementType() == MVT::i64)
7189 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7190 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7191 while ((1U << Shift) < NumElems) {
7192 if (SVOp->getMaskElt(1U << Shift) == 1)
7195 // The maximal ratio is 8, i.e. from i8 to i64.
7200 // Check the shuffle mask.
7201 unsigned Mask = (1U << Shift) - 1;
7202 for (unsigned i = 0; i != NumElems; ++i) {
7203 int EltIdx = SVOp->getMaskElt(i);
7204 if ((i & Mask) != 0 && EltIdx != -1)
7206 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7210 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7211 MVT NeVT = MVT::getIntegerVT(NBits);
7212 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7214 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7217 // Simplify the operand as it's prepared to be fed into shuffle.
7218 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7219 if (V1.getOpcode() == ISD::BITCAST &&
7220 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7221 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7222 V1.getOperand(0).getOperand(0)
7223 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7224 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7225 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7226 ConstantSDNode *CIdx =
7227 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7228 // If it's foldable, i.e. normal load with single use, we will let code
7229 // selection to fold it. Otherwise, we will short the conversion sequence.
7230 if (CIdx && CIdx->getZExtValue() == 0 &&
7231 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7232 MVT FullVT = V.getSimpleValueType();
7233 MVT V1VT = V1.getSimpleValueType();
7234 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7235 // The "ext_vec_elt" node is wider than the result node.
7236 // In this case we should extract subvector from V.
7237 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7238 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7239 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7240 FullVT.getVectorNumElements()/Ratio);
7241 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7242 DAG.getIntPtrConstant(0));
7244 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7248 return DAG.getNode(ISD::BITCAST, DL, VT,
7249 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7253 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7254 SelectionDAG &DAG) {
7255 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7256 MVT VT = Op.getSimpleValueType();
7258 SDValue V1 = Op.getOperand(0);
7259 SDValue V2 = Op.getOperand(1);
7261 if (isZeroShuffle(SVOp))
7262 return getZeroVector(VT, Subtarget, DAG, dl);
7264 // Handle splat operations
7265 if (SVOp->isSplat()) {
7266 // Use vbroadcast whenever the splat comes from a foldable load
7267 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7268 if (Broadcast.getNode())
7272 // Check integer expanding shuffles.
7273 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7274 if (NewOp.getNode())
7277 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7279 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7280 VT == MVT::v16i16 || VT == MVT::v32i8) {
7281 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7282 if (NewOp.getNode())
7283 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7284 } else if ((VT == MVT::v4i32 ||
7285 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7286 // FIXME: Figure out a cleaner way to do this.
7287 // Try to make use of movq to zero out the top part.
7288 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7289 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7290 if (NewOp.getNode()) {
7291 MVT NewVT = NewOp.getSimpleValueType();
7292 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7293 NewVT, true, false))
7294 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7295 DAG, Subtarget, dl);
7297 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7298 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7299 if (NewOp.getNode()) {
7300 MVT NewVT = NewOp.getSimpleValueType();
7301 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7302 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7303 DAG, Subtarget, dl);
7311 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7312 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7313 SDValue V1 = Op.getOperand(0);
7314 SDValue V2 = Op.getOperand(1);
7315 MVT VT = Op.getSimpleValueType();
7317 unsigned NumElems = VT.getVectorNumElements();
7318 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7319 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7320 bool V1IsSplat = false;
7321 bool V2IsSplat = false;
7322 bool HasSSE2 = Subtarget->hasSSE2();
7323 bool HasFp256 = Subtarget->hasFp256();
7324 bool HasInt256 = Subtarget->hasInt256();
7325 MachineFunction &MF = DAG.getMachineFunction();
7326 bool OptForSize = MF.getFunction()->getAttributes().
7327 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7329 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7331 if (V1IsUndef && V2IsUndef)
7332 return DAG.getUNDEF(VT);
7334 // When we create a shuffle node we put the UNDEF node to second operand,
7335 // but in some cases the first operand may be transformed to UNDEF.
7336 // In this case we should just commute the node.
7338 return CommuteVectorShuffle(SVOp, DAG);
7340 // Vector shuffle lowering takes 3 steps:
7342 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7343 // narrowing and commutation of operands should be handled.
7344 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7346 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7347 // so the shuffle can be broken into other shuffles and the legalizer can
7348 // try the lowering again.
7350 // The general idea is that no vector_shuffle operation should be left to
7351 // be matched during isel, all of them must be converted to a target specific
7354 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7355 // narrowing and commutation of operands should be handled. The actual code
7356 // doesn't include all of those, work in progress...
7357 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7358 if (NewOp.getNode())
7361 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7363 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7364 // unpckh_undef). Only use pshufd if speed is more important than size.
7365 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7366 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7367 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7368 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7370 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7371 V2IsUndef && MayFoldVectorLoad(V1))
7372 return getMOVDDup(Op, dl, V1, DAG);
7374 if (isMOVHLPS_v_undef_Mask(M, VT))
7375 return getMOVHighToLow(Op, dl, DAG);
7377 // Use to match splats
7378 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7379 (VT == MVT::v2f64 || VT == MVT::v2i64))
7380 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7382 if (isPSHUFDMask(M, VT)) {
7383 // The actual implementation will match the mask in the if above and then
7384 // during isel it can match several different instructions, not only pshufd
7385 // as its name says, sad but true, emulate the behavior for now...
7386 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7387 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7389 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7391 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7392 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7394 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7395 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7398 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7402 if (isPALIGNRMask(M, VT, Subtarget))
7403 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7404 getShufflePALIGNRImmediate(SVOp),
7407 // Check if this can be converted into a logical shift.
7408 bool isLeft = false;
7411 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7412 if (isShift && ShVal.hasOneUse()) {
7413 // If the shifted value has multiple uses, it may be cheaper to use
7414 // v_set0 + movlhps or movhlps, etc.
7415 MVT EltVT = VT.getVectorElementType();
7416 ShAmt *= EltVT.getSizeInBits();
7417 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7420 if (isMOVLMask(M, VT)) {
7421 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7422 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7423 if (!isMOVLPMask(M, VT)) {
7424 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7425 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7427 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7428 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7432 // FIXME: fold these into legal mask.
7433 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7434 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7436 if (isMOVHLPSMask(M, VT))
7437 return getMOVHighToLow(Op, dl, DAG);
7439 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7440 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7442 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7443 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7445 if (isMOVLPMask(M, VT))
7446 return getMOVLP(Op, dl, DAG, HasSSE2);
7448 if (ShouldXformToMOVHLPS(M, VT) ||
7449 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7450 return CommuteVectorShuffle(SVOp, DAG);
7453 // No better options. Use a vshldq / vsrldq.
7454 MVT EltVT = VT.getVectorElementType();
7455 ShAmt *= EltVT.getSizeInBits();
7456 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7459 bool Commuted = false;
7460 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7461 // 1,1,1,1 -> v8i16 though.
7462 V1IsSplat = isSplatVector(V1.getNode());
7463 V2IsSplat = isSplatVector(V2.getNode());
7465 // Canonicalize the splat or undef, if present, to be on the RHS.
7466 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7467 CommuteVectorShuffleMask(M, NumElems);
7469 std::swap(V1IsSplat, V2IsSplat);
7473 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7474 // Shuffling low element of v1 into undef, just return v1.
7477 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7478 // the instruction selector will not match, so get a canonical MOVL with
7479 // swapped operands to undo the commute.
7480 return getMOVL(DAG, dl, VT, V2, V1);
7483 if (isUNPCKLMask(M, VT, HasInt256))
7484 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7486 if (isUNPCKHMask(M, VT, HasInt256))
7487 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7490 // Normalize mask so all entries that point to V2 points to its first
7491 // element then try to match unpck{h|l} again. If match, return a
7492 // new vector_shuffle with the corrected mask.p
7493 SmallVector<int, 8> NewMask(M.begin(), M.end());
7494 NormalizeMask(NewMask, NumElems);
7495 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7496 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7497 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7498 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7502 // Commute is back and try unpck* again.
7503 // FIXME: this seems wrong.
7504 CommuteVectorShuffleMask(M, NumElems);
7506 std::swap(V1IsSplat, V2IsSplat);
7509 if (isUNPCKLMask(M, VT, HasInt256))
7510 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7512 if (isUNPCKHMask(M, VT, HasInt256))
7513 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7516 // Normalize the node to match x86 shuffle ops if needed
7517 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7518 return CommuteVectorShuffle(SVOp, DAG);
7520 // The checks below are all present in isShuffleMaskLegal, but they are
7521 // inlined here right now to enable us to directly emit target specific
7522 // nodes, and remove one by one until they don't return Op anymore.
7524 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7525 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7526 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7527 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7530 if (isPSHUFHWMask(M, VT, HasInt256))
7531 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7532 getShufflePSHUFHWImmediate(SVOp),
7535 if (isPSHUFLWMask(M, VT, HasInt256))
7536 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7537 getShufflePSHUFLWImmediate(SVOp),
7540 if (isSHUFPMask(M, VT))
7541 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7542 getShuffleSHUFImmediate(SVOp), DAG);
7544 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7545 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7546 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7547 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7549 //===--------------------------------------------------------------------===//
7550 // Generate target specific nodes for 128 or 256-bit shuffles only
7551 // supported in the AVX instruction set.
7554 // Handle VMOVDDUPY permutations
7555 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7556 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7558 // Handle VPERMILPS/D* permutations
7559 if (isVPERMILPMask(M, VT)) {
7560 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7561 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7562 getShuffleSHUFImmediate(SVOp), DAG);
7563 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7564 getShuffleSHUFImmediate(SVOp), DAG);
7567 // Handle VPERM2F128/VPERM2I128 permutations
7568 if (isVPERM2X128Mask(M, VT, HasFp256))
7569 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7570 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7572 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7573 if (BlendOp.getNode())
7577 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7578 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7580 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7581 VT.is512BitVector()) {
7582 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7583 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7584 SmallVector<SDValue, 16> permclMask;
7585 for (unsigned i = 0; i != NumElems; ++i) {
7586 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7589 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7590 &permclMask[0], NumElems);
7592 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7593 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7594 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7595 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
7596 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
7599 //===--------------------------------------------------------------------===//
7600 // Since no target specific shuffle was selected for this generic one,
7601 // lower it into other known shuffles. FIXME: this isn't true yet, but
7602 // this is the plan.
7605 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7606 if (VT == MVT::v8i16) {
7607 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7608 if (NewOp.getNode())
7612 if (VT == MVT::v16i8) {
7613 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7614 if (NewOp.getNode())
7618 if (VT == MVT::v32i8) {
7619 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7620 if (NewOp.getNode())
7624 // Handle all 128-bit wide vectors with 4 elements, and match them with
7625 // several different shuffle types.
7626 if (NumElems == 4 && VT.is128BitVector())
7627 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7629 // Handle general 256-bit shuffles
7630 if (VT.is256BitVector())
7631 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7636 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7637 MVT VT = Op.getSimpleValueType();
7640 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7643 if (VT.getSizeInBits() == 8) {
7644 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7645 Op.getOperand(0), Op.getOperand(1));
7646 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7647 DAG.getValueType(VT));
7648 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7651 if (VT.getSizeInBits() == 16) {
7652 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7653 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7655 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7656 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7657 DAG.getNode(ISD::BITCAST, dl,
7661 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7662 Op.getOperand(0), Op.getOperand(1));
7663 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7664 DAG.getValueType(VT));
7665 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7668 if (VT == MVT::f32) {
7669 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7670 // the result back to FR32 register. It's only worth matching if the
7671 // result has a single use which is a store or a bitcast to i32. And in
7672 // the case of a store, it's not worth it if the index is a constant 0,
7673 // because a MOVSSmr can be used instead, which is smaller and faster.
7674 if (!Op.hasOneUse())
7676 SDNode *User = *Op.getNode()->use_begin();
7677 if ((User->getOpcode() != ISD::STORE ||
7678 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7679 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7680 (User->getOpcode() != ISD::BITCAST ||
7681 User->getValueType(0) != MVT::i32))
7683 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7684 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7687 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7690 if (VT == MVT::i32 || VT == MVT::i64) {
7691 // ExtractPS/pextrq works with constant index.
7692 if (isa<ConstantSDNode>(Op.getOperand(1)))
7698 /// Extract one bit from mask vector, like v16i1 or v8i1.
7699 /// AVX-512 feature.
7701 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
7702 SDValue Vec = Op.getOperand(0);
7704 MVT VecVT = Vec.getSimpleValueType();
7705 SDValue Idx = Op.getOperand(1);
7706 MVT EltVT = Op.getSimpleValueType();
7708 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
7710 // variable index can't be handled in mask registers,
7711 // extend vector to VR512
7712 if (!isa<ConstantSDNode>(Idx)) {
7713 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
7714 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
7715 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
7716 ExtVT.getVectorElementType(), Ext, Idx);
7717 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
7720 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7721 const TargetRegisterClass* rc = getRegClassFor(VecVT);
7722 unsigned MaxSift = rc->getSize()*8 - 1;
7723 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
7724 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
7725 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
7726 DAG.getConstant(MaxSift, MVT::i8));
7727 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
7728 DAG.getIntPtrConstant(0));
7732 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7733 SelectionDAG &DAG) const {
7735 SDValue Vec = Op.getOperand(0);
7736 MVT VecVT = Vec.getSimpleValueType();
7737 SDValue Idx = Op.getOperand(1);
7739 if (Op.getSimpleValueType() == MVT::i1)
7740 return ExtractBitFromMaskVector(Op, DAG);
7742 if (!isa<ConstantSDNode>(Idx)) {
7743 if (VecVT.is512BitVector() ||
7744 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7745 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7748 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7749 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7750 MaskEltVT.getSizeInBits());
7752 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7753 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7754 getZeroVector(MaskVT, Subtarget, DAG, dl),
7755 Idx, DAG.getConstant(0, getPointerTy()));
7756 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7757 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7758 Perm, DAG.getConstant(0, getPointerTy()));
7763 // If this is a 256-bit vector result, first extract the 128-bit vector and
7764 // then extract the element from the 128-bit vector.
7765 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7767 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7768 // Get the 128-bit vector.
7769 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7770 MVT EltVT = VecVT.getVectorElementType();
7772 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7774 //if (IdxVal >= NumElems/2)
7775 // IdxVal -= NumElems/2;
7776 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7777 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7778 DAG.getConstant(IdxVal, MVT::i32));
7781 assert(VecVT.is128BitVector() && "Unexpected vector length");
7783 if (Subtarget->hasSSE41()) {
7784 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7789 MVT VT = Op.getSimpleValueType();
7790 // TODO: handle v16i8.
7791 if (VT.getSizeInBits() == 16) {
7792 SDValue Vec = Op.getOperand(0);
7793 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7795 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7796 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7797 DAG.getNode(ISD::BITCAST, dl,
7800 // Transform it so it match pextrw which produces a 32-bit result.
7801 MVT EltVT = MVT::i32;
7802 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7803 Op.getOperand(0), Op.getOperand(1));
7804 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7805 DAG.getValueType(VT));
7806 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7809 if (VT.getSizeInBits() == 32) {
7810 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7814 // SHUFPS the element to the lowest double word, then movss.
7815 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7816 MVT VVT = Op.getOperand(0).getSimpleValueType();
7817 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7818 DAG.getUNDEF(VVT), Mask);
7819 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7820 DAG.getIntPtrConstant(0));
7823 if (VT.getSizeInBits() == 64) {
7824 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7825 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7826 // to match extract_elt for f64.
7827 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7831 // UNPCKHPD the element to the lowest double word, then movsd.
7832 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7833 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7834 int Mask[2] = { 1, -1 };
7835 MVT VVT = Op.getOperand(0).getSimpleValueType();
7836 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7837 DAG.getUNDEF(VVT), Mask);
7838 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7839 DAG.getIntPtrConstant(0));
7845 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7846 MVT VT = Op.getSimpleValueType();
7847 MVT EltVT = VT.getVectorElementType();
7850 SDValue N0 = Op.getOperand(0);
7851 SDValue N1 = Op.getOperand(1);
7852 SDValue N2 = Op.getOperand(2);
7854 if (!VT.is128BitVector())
7857 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7858 isa<ConstantSDNode>(N2)) {
7860 if (VT == MVT::v8i16)
7861 Opc = X86ISD::PINSRW;
7862 else if (VT == MVT::v16i8)
7863 Opc = X86ISD::PINSRB;
7865 Opc = X86ISD::PINSRB;
7867 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7869 if (N1.getValueType() != MVT::i32)
7870 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7871 if (N2.getValueType() != MVT::i32)
7872 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7873 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7876 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7877 // Bits [7:6] of the constant are the source select. This will always be
7878 // zero here. The DAG Combiner may combine an extract_elt index into these
7879 // bits. For example (insert (extract, 3), 2) could be matched by putting
7880 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7881 // Bits [5:4] of the constant are the destination select. This is the
7882 // value of the incoming immediate.
7883 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7884 // combine either bitwise AND or insert of float 0.0 to set these bits.
7885 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7886 // Create this as a scalar to vector..
7887 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7888 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7891 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7892 // PINSR* works with constant index.
7899 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7900 MVT VT = Op.getSimpleValueType();
7901 MVT EltVT = VT.getVectorElementType();
7904 SDValue N0 = Op.getOperand(0);
7905 SDValue N1 = Op.getOperand(1);
7906 SDValue N2 = Op.getOperand(2);
7908 // If this is a 256-bit vector result, first extract the 128-bit vector,
7909 // insert the element into the extracted half and then place it back.
7910 if (VT.is256BitVector() || VT.is512BitVector()) {
7911 if (!isa<ConstantSDNode>(N2))
7914 // Get the desired 128-bit vector half.
7915 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7916 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7918 // Insert the element into the desired half.
7919 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7920 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7922 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7923 DAG.getConstant(IdxIn128, MVT::i32));
7925 // Insert the changed part back to the 256-bit vector
7926 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7929 if (Subtarget->hasSSE41())
7930 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7932 if (EltVT == MVT::i8)
7935 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7936 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7937 // as its second argument.
7938 if (N1.getValueType() != MVT::i32)
7939 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7940 if (N2.getValueType() != MVT::i32)
7941 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7942 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7947 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7949 MVT OpVT = Op.getSimpleValueType();
7951 // If this is a 256-bit vector result, first insert into a 128-bit
7952 // vector and then insert into the 256-bit vector.
7953 if (!OpVT.is128BitVector()) {
7954 // Insert into a 128-bit vector.
7955 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7956 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7957 OpVT.getVectorNumElements() / SizeFactor);
7959 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7961 // Insert the 128-bit vector.
7962 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7965 if (OpVT == MVT::v1i64 &&
7966 Op.getOperand(0).getValueType() == MVT::i64)
7967 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7969 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7970 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7971 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7972 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7975 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7976 // a simple subregister reference or explicit instructions to grab
7977 // upper bits of a vector.
7978 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7979 SelectionDAG &DAG) {
7981 SDValue In = Op.getOperand(0);
7982 SDValue Idx = Op.getOperand(1);
7983 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7984 MVT ResVT = Op.getSimpleValueType();
7985 MVT InVT = In.getSimpleValueType();
7987 if (Subtarget->hasFp256()) {
7988 if (ResVT.is128BitVector() &&
7989 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7990 isa<ConstantSDNode>(Idx)) {
7991 return Extract128BitVector(In, IdxVal, DAG, dl);
7993 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7994 isa<ConstantSDNode>(Idx)) {
7995 return Extract256BitVector(In, IdxVal, DAG, dl);
8001 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
8002 // simple superregister reference or explicit instructions to insert
8003 // the upper bits of a vector.
8004 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
8005 SelectionDAG &DAG) {
8006 if (Subtarget->hasFp256()) {
8007 SDLoc dl(Op.getNode());
8008 SDValue Vec = Op.getNode()->getOperand(0);
8009 SDValue SubVec = Op.getNode()->getOperand(1);
8010 SDValue Idx = Op.getNode()->getOperand(2);
8012 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
8013 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
8014 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
8015 isa<ConstantSDNode>(Idx)) {
8016 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8017 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
8020 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
8021 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
8022 isa<ConstantSDNode>(Idx)) {
8023 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8024 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
8030 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
8031 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
8032 // one of the above mentioned nodes. It has to be wrapped because otherwise
8033 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
8034 // be used to form addressing mode. These wrapped nodes will be selected
8037 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
8038 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
8040 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8042 unsigned char OpFlag = 0;
8043 unsigned WrapperKind = X86ISD::Wrapper;
8044 CodeModel::Model M = getTargetMachine().getCodeModel();
8046 if (Subtarget->isPICStyleRIPRel() &&
8047 (M == CodeModel::Small || M == CodeModel::Kernel))
8048 WrapperKind = X86ISD::WrapperRIP;
8049 else if (Subtarget->isPICStyleGOT())
8050 OpFlag = X86II::MO_GOTOFF;
8051 else if (Subtarget->isPICStyleStubPIC())
8052 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8054 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
8056 CP->getOffset(), OpFlag);
8058 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8059 // With PIC, the address is actually $g + Offset.
8061 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8062 DAG.getNode(X86ISD::GlobalBaseReg,
8063 SDLoc(), getPointerTy()),
8070 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
8071 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
8073 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8075 unsigned char OpFlag = 0;
8076 unsigned WrapperKind = X86ISD::Wrapper;
8077 CodeModel::Model M = getTargetMachine().getCodeModel();
8079 if (Subtarget->isPICStyleRIPRel() &&
8080 (M == CodeModel::Small || M == CodeModel::Kernel))
8081 WrapperKind = X86ISD::WrapperRIP;
8082 else if (Subtarget->isPICStyleGOT())
8083 OpFlag = X86II::MO_GOTOFF;
8084 else if (Subtarget->isPICStyleStubPIC())
8085 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8087 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
8090 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8092 // With PIC, the address is actually $g + Offset.
8094 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8095 DAG.getNode(X86ISD::GlobalBaseReg,
8096 SDLoc(), getPointerTy()),
8103 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8104 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8106 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8108 unsigned char OpFlag = 0;
8109 unsigned WrapperKind = X86ISD::Wrapper;
8110 CodeModel::Model M = getTargetMachine().getCodeModel();
8112 if (Subtarget->isPICStyleRIPRel() &&
8113 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8114 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8115 OpFlag = X86II::MO_GOTPCREL;
8116 WrapperKind = X86ISD::WrapperRIP;
8117 } else if (Subtarget->isPICStyleGOT()) {
8118 OpFlag = X86II::MO_GOT;
8119 } else if (Subtarget->isPICStyleStubPIC()) {
8120 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8121 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8122 OpFlag = X86II::MO_DARWIN_NONLAZY;
8125 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8128 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8130 // With PIC, the address is actually $g + Offset.
8131 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8132 !Subtarget->is64Bit()) {
8133 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8134 DAG.getNode(X86ISD::GlobalBaseReg,
8135 SDLoc(), getPointerTy()),
8139 // For symbols that require a load from a stub to get the address, emit the
8141 if (isGlobalStubReference(OpFlag))
8142 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8143 MachinePointerInfo::getGOT(), false, false, false, 0);
8149 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8150 // Create the TargetBlockAddressAddress node.
8151 unsigned char OpFlags =
8152 Subtarget->ClassifyBlockAddressReference();
8153 CodeModel::Model M = getTargetMachine().getCodeModel();
8154 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8155 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8157 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8160 if (Subtarget->isPICStyleRIPRel() &&
8161 (M == CodeModel::Small || M == CodeModel::Kernel))
8162 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8164 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8166 // With PIC, the address is actually $g + Offset.
8167 if (isGlobalRelativeToPICBase(OpFlags)) {
8168 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8169 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8177 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8178 int64_t Offset, SelectionDAG &DAG) const {
8179 // Create the TargetGlobalAddress node, folding in the constant
8180 // offset if it is legal.
8181 unsigned char OpFlags =
8182 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8183 CodeModel::Model M = getTargetMachine().getCodeModel();
8185 if (OpFlags == X86II::MO_NO_FLAG &&
8186 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8187 // A direct static reference to a global.
8188 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8191 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8194 if (Subtarget->isPICStyleRIPRel() &&
8195 (M == CodeModel::Small || M == CodeModel::Kernel))
8196 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8198 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8200 // With PIC, the address is actually $g + Offset.
8201 if (isGlobalRelativeToPICBase(OpFlags)) {
8202 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8203 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8207 // For globals that require a load from a stub to get the address, emit the
8209 if (isGlobalStubReference(OpFlags))
8210 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8211 MachinePointerInfo::getGOT(), false, false, false, 0);
8213 // If there was a non-zero offset that we didn't fold, create an explicit
8216 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8217 DAG.getConstant(Offset, getPointerTy()));
8223 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8224 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8225 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8226 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8230 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8231 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8232 unsigned char OperandFlags, bool LocalDynamic = false) {
8233 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8234 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8236 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8237 GA->getValueType(0),
8241 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8245 SDValue Ops[] = { Chain, TGA, *InFlag };
8246 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8248 SDValue Ops[] = { Chain, TGA };
8249 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8252 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8253 MFI->setAdjustsStack(true);
8255 SDValue Flag = Chain.getValue(1);
8256 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8259 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8261 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8264 SDLoc dl(GA); // ? function entry point might be better
8265 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8266 DAG.getNode(X86ISD::GlobalBaseReg,
8267 SDLoc(), PtrVT), InFlag);
8268 InFlag = Chain.getValue(1);
8270 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8273 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8275 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8277 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8278 X86::RAX, X86II::MO_TLSGD);
8281 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8287 // Get the start address of the TLS block for this module.
8288 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8289 .getInfo<X86MachineFunctionInfo>();
8290 MFI->incNumLocalDynamicTLSAccesses();
8294 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8295 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8298 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8299 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8300 InFlag = Chain.getValue(1);
8301 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8302 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8305 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8309 unsigned char OperandFlags = X86II::MO_DTPOFF;
8310 unsigned WrapperKind = X86ISD::Wrapper;
8311 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8312 GA->getValueType(0),
8313 GA->getOffset(), OperandFlags);
8314 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8316 // Add x@dtpoff with the base.
8317 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8320 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8321 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8322 const EVT PtrVT, TLSModel::Model model,
8323 bool is64Bit, bool isPIC) {
8326 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8327 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8328 is64Bit ? 257 : 256));
8330 SDValue ThreadPointer =
8331 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8332 MachinePointerInfo(Ptr), false, false, false, 0);
8334 unsigned char OperandFlags = 0;
8335 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8337 unsigned WrapperKind = X86ISD::Wrapper;
8338 if (model == TLSModel::LocalExec) {
8339 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8340 } else if (model == TLSModel::InitialExec) {
8342 OperandFlags = X86II::MO_GOTTPOFF;
8343 WrapperKind = X86ISD::WrapperRIP;
8345 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8348 llvm_unreachable("Unexpected model");
8351 // emit "addl x@ntpoff,%eax" (local exec)
8352 // or "addl x@indntpoff,%eax" (initial exec)
8353 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8355 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8356 GA->getOffset(), OperandFlags);
8357 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8359 if (model == TLSModel::InitialExec) {
8360 if (isPIC && !is64Bit) {
8361 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8362 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8366 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8367 MachinePointerInfo::getGOT(), false, false, false, 0);
8370 // The address of the thread local variable is the add of the thread
8371 // pointer with the offset of the variable.
8372 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8376 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8378 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8379 const GlobalValue *GV = GA->getGlobal();
8381 if (Subtarget->isTargetELF()) {
8382 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8385 case TLSModel::GeneralDynamic:
8386 if (Subtarget->is64Bit())
8387 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8388 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8389 case TLSModel::LocalDynamic:
8390 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8391 Subtarget->is64Bit());
8392 case TLSModel::InitialExec:
8393 case TLSModel::LocalExec:
8394 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8395 Subtarget->is64Bit(),
8396 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8398 llvm_unreachable("Unknown TLS model.");
8401 if (Subtarget->isTargetDarwin()) {
8402 // Darwin only has one model of TLS. Lower to that.
8403 unsigned char OpFlag = 0;
8404 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8405 X86ISD::WrapperRIP : X86ISD::Wrapper;
8407 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8409 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8410 !Subtarget->is64Bit();
8412 OpFlag = X86II::MO_TLVP_PIC_BASE;
8414 OpFlag = X86II::MO_TLVP;
8416 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8417 GA->getValueType(0),
8418 GA->getOffset(), OpFlag);
8419 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8421 // With PIC32, the address is actually $g + Offset.
8423 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8424 DAG.getNode(X86ISD::GlobalBaseReg,
8425 SDLoc(), getPointerTy()),
8428 // Lowering the machine isd will make sure everything is in the right
8430 SDValue Chain = DAG.getEntryNode();
8431 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8432 SDValue Args[] = { Chain, Offset };
8433 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8435 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8436 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8437 MFI->setAdjustsStack(true);
8439 // And our return value (tls address) is in the standard call return value
8441 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8442 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8446 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8447 // Just use the implicit TLS architecture
8448 // Need to generate someting similar to:
8449 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8451 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8452 // mov rcx, qword [rdx+rcx*8]
8453 // mov eax, .tls$:tlsvar
8454 // [rax+rcx] contains the address
8455 // Windows 64bit: gs:0x58
8456 // Windows 32bit: fs:__tls_array
8458 // If GV is an alias then use the aliasee for determining
8459 // thread-localness.
8460 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8461 GV = GA->resolveAliasedGlobal(false);
8463 SDValue Chain = DAG.getEntryNode();
8465 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8466 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8467 // use its literal value of 0x2C.
8468 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8469 ? Type::getInt8PtrTy(*DAG.getContext(),
8471 : Type::getInt32PtrTy(*DAG.getContext(),
8474 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8475 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8476 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8478 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8479 MachinePointerInfo(Ptr),
8480 false, false, false, 0);
8482 // Load the _tls_index variable
8483 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8484 if (Subtarget->is64Bit())
8485 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8486 IDX, MachinePointerInfo(), MVT::i32,
8489 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8490 false, false, false, 0);
8492 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8494 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8496 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8497 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8498 false, false, false, 0);
8500 // Get the offset of start of .tls section
8501 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8502 GA->getValueType(0),
8503 GA->getOffset(), X86II::MO_SECREL);
8504 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8506 // The address of the thread local variable is the add of the thread
8507 // pointer with the offset of the variable.
8508 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8511 llvm_unreachable("TLS not implemented for this target.");
8514 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8515 /// and take a 2 x i32 value to shift plus a shift amount.
8516 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
8517 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8518 MVT VT = Op.getSimpleValueType();
8519 unsigned VTBits = VT.getSizeInBits();
8521 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8522 SDValue ShOpLo = Op.getOperand(0);
8523 SDValue ShOpHi = Op.getOperand(1);
8524 SDValue ShAmt = Op.getOperand(2);
8525 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
8526 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
8528 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8529 DAG.getConstant(VTBits - 1, MVT::i8));
8530 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8531 DAG.getConstant(VTBits - 1, MVT::i8))
8532 : DAG.getConstant(0, VT);
8535 if (Op.getOpcode() == ISD::SHL_PARTS) {
8536 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8537 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
8539 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8540 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
8543 // If the shift amount is larger or equal than the width of a part we can't
8544 // rely on the results of shld/shrd. Insert a test and select the appropriate
8545 // values for large shift amounts.
8546 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8547 DAG.getConstant(VTBits, MVT::i8));
8548 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8549 AndNode, DAG.getConstant(0, MVT::i8));
8552 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8553 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8554 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8556 if (Op.getOpcode() == ISD::SHL_PARTS) {
8557 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8558 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8560 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8561 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8564 SDValue Ops[2] = { Lo, Hi };
8565 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8568 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8569 SelectionDAG &DAG) const {
8570 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
8572 if (SrcVT.isVector())
8575 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
8576 "Unknown SINT_TO_FP to lower!");
8578 // These are really Legal; return the operand so the caller accepts it as
8580 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8582 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8583 Subtarget->is64Bit()) {
8588 unsigned Size = SrcVT.getSizeInBits()/8;
8589 MachineFunction &MF = DAG.getMachineFunction();
8590 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8591 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8592 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8594 MachinePointerInfo::getFixedStack(SSFI),
8596 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8599 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8601 SelectionDAG &DAG) const {
8605 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8607 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8609 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8611 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8613 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8614 MachineMemOperand *MMO;
8616 int SSFI = FI->getIndex();
8618 DAG.getMachineFunction()
8619 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8620 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8622 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8623 StackSlot = StackSlot.getOperand(1);
8625 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8626 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8628 Tys, Ops, array_lengthof(Ops),
8632 Chain = Result.getValue(1);
8633 SDValue InFlag = Result.getValue(2);
8635 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8636 // shouldn't be necessary except that RFP cannot be live across
8637 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8638 MachineFunction &MF = DAG.getMachineFunction();
8639 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8640 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8641 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8642 Tys = DAG.getVTList(MVT::Other);
8644 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8646 MachineMemOperand *MMO =
8647 DAG.getMachineFunction()
8648 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8649 MachineMemOperand::MOStore, SSFISize, SSFISize);
8651 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8652 Ops, array_lengthof(Ops),
8653 Op.getValueType(), MMO);
8654 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8655 MachinePointerInfo::getFixedStack(SSFI),
8656 false, false, false, 0);
8662 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8663 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8664 SelectionDAG &DAG) const {
8665 // This algorithm is not obvious. Here it is what we're trying to output:
8668 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8669 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8673 pshufd $0x4e, %xmm0, %xmm1
8679 LLVMContext *Context = DAG.getContext();
8681 // Build some magic constants.
8682 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8683 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8684 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8686 SmallVector<Constant*,2> CV1;
8688 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8689 APInt(64, 0x4330000000000000ULL))));
8691 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8692 APInt(64, 0x4530000000000000ULL))));
8693 Constant *C1 = ConstantVector::get(CV1);
8694 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8696 // Load the 64-bit value into an XMM register.
8697 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8699 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8700 MachinePointerInfo::getConstantPool(),
8701 false, false, false, 16);
8702 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8703 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8706 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8707 MachinePointerInfo::getConstantPool(),
8708 false, false, false, 16);
8709 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8710 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8713 if (Subtarget->hasSSE3()) {
8714 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8715 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8717 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8718 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8720 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8721 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8725 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8726 DAG.getIntPtrConstant(0));
8729 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8730 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8731 SelectionDAG &DAG) const {
8733 // FP constant to bias correct the final result.
8734 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8737 // Load the 32-bit value into an XMM register.
8738 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8741 // Zero out the upper parts of the register.
8742 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8744 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8745 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8746 DAG.getIntPtrConstant(0));
8748 // Or the load with the bias.
8749 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8750 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8751 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8753 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8754 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8755 MVT::v2f64, Bias)));
8756 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8757 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8758 DAG.getIntPtrConstant(0));
8760 // Subtract the bias.
8761 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8763 // Handle final rounding.
8764 EVT DestVT = Op.getValueType();
8766 if (DestVT.bitsLT(MVT::f64))
8767 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8768 DAG.getIntPtrConstant(0));
8769 if (DestVT.bitsGT(MVT::f64))
8770 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8772 // Handle final rounding.
8776 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8777 SelectionDAG &DAG) const {
8778 SDValue N0 = Op.getOperand(0);
8779 MVT SVT = N0.getSimpleValueType();
8782 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8783 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8784 "Custom UINT_TO_FP is not supported!");
8786 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
8787 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8788 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8791 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8792 SelectionDAG &DAG) const {
8793 SDValue N0 = Op.getOperand(0);
8796 if (Op.getValueType().isVector())
8797 return lowerUINT_TO_FP_vec(Op, DAG);
8799 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8800 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8801 // the optimization here.
8802 if (DAG.SignBitIsZero(N0))
8803 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8805 MVT SrcVT = N0.getSimpleValueType();
8806 MVT DstVT = Op.getSimpleValueType();
8807 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8808 return LowerUINT_TO_FP_i64(Op, DAG);
8809 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8810 return LowerUINT_TO_FP_i32(Op, DAG);
8811 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8814 // Make a 64-bit buffer, and use it to build an FILD.
8815 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8816 if (SrcVT == MVT::i32) {
8817 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8818 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8819 getPointerTy(), StackSlot, WordOff);
8820 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8821 StackSlot, MachinePointerInfo(),
8823 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8824 OffsetSlot, MachinePointerInfo(),
8826 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8830 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8831 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8832 StackSlot, MachinePointerInfo(),
8834 // For i64 source, we need to add the appropriate power of 2 if the input
8835 // was negative. This is the same as the optimization in
8836 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8837 // we must be careful to do the computation in x87 extended precision, not
8838 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8839 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8840 MachineMemOperand *MMO =
8841 DAG.getMachineFunction()
8842 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8843 MachineMemOperand::MOLoad, 8, 8);
8845 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8846 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8847 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8848 array_lengthof(Ops), MVT::i64, MMO);
8850 APInt FF(32, 0x5F800000ULL);
8852 // Check whether the sign bit is set.
8853 SDValue SignSet = DAG.getSetCC(dl,
8854 getSetCCResultType(*DAG.getContext(), MVT::i64),
8855 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8858 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8859 SDValue FudgePtr = DAG.getConstantPool(
8860 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8863 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8864 SDValue Zero = DAG.getIntPtrConstant(0);
8865 SDValue Four = DAG.getIntPtrConstant(4);
8866 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8868 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8870 // Load the value out, extending it from f32 to f80.
8871 // FIXME: Avoid the extend by constructing the right constant pool?
8872 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8873 FudgePtr, MachinePointerInfo::getConstantPool(),
8874 MVT::f32, false, false, 4);
8875 // Extend everything to 80 bits to force it to be done on x87.
8876 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8877 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8880 std::pair<SDValue,SDValue>
8881 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8882 bool IsSigned, bool IsReplace) const {
8885 EVT DstTy = Op.getValueType();
8887 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8888 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8892 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8893 DstTy.getSimpleVT() >= MVT::i16 &&
8894 "Unknown FP_TO_INT to lower!");
8896 // These are really Legal.
8897 if (DstTy == MVT::i32 &&
8898 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8899 return std::make_pair(SDValue(), SDValue());
8900 if (Subtarget->is64Bit() &&
8901 DstTy == MVT::i64 &&
8902 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8903 return std::make_pair(SDValue(), SDValue());
8905 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8906 // stack slot, or into the FTOL runtime function.
8907 MachineFunction &MF = DAG.getMachineFunction();
8908 unsigned MemSize = DstTy.getSizeInBits()/8;
8909 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8910 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8913 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8914 Opc = X86ISD::WIN_FTOL;
8916 switch (DstTy.getSimpleVT().SimpleTy) {
8917 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8918 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8919 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8920 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8923 SDValue Chain = DAG.getEntryNode();
8924 SDValue Value = Op.getOperand(0);
8925 EVT TheVT = Op.getOperand(0).getValueType();
8926 // FIXME This causes a redundant load/store if the SSE-class value is already
8927 // in memory, such as if it is on the callstack.
8928 if (isScalarFPTypeInSSEReg(TheVT)) {
8929 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8930 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8931 MachinePointerInfo::getFixedStack(SSFI),
8933 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8935 Chain, StackSlot, DAG.getValueType(TheVT)
8938 MachineMemOperand *MMO =
8939 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8940 MachineMemOperand::MOLoad, MemSize, MemSize);
8941 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8942 array_lengthof(Ops), DstTy, MMO);
8943 Chain = Value.getValue(1);
8944 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8945 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8948 MachineMemOperand *MMO =
8949 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8950 MachineMemOperand::MOStore, MemSize, MemSize);
8952 if (Opc != X86ISD::WIN_FTOL) {
8953 // Build the FP_TO_INT*_IN_MEM
8954 SDValue Ops[] = { Chain, Value, StackSlot };
8955 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8956 Ops, array_lengthof(Ops), DstTy,
8958 return std::make_pair(FIST, StackSlot);
8960 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8961 DAG.getVTList(MVT::Other, MVT::Glue),
8963 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8964 MVT::i32, ftol.getValue(1));
8965 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8966 MVT::i32, eax.getValue(2));
8967 SDValue Ops[] = { eax, edx };
8968 SDValue pair = IsReplace
8969 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8970 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8971 return std::make_pair(pair, SDValue());
8975 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8976 const X86Subtarget *Subtarget) {
8977 MVT VT = Op->getSimpleValueType(0);
8978 SDValue In = Op->getOperand(0);
8979 MVT InVT = In.getSimpleValueType();
8982 // Optimize vectors in AVX mode:
8985 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8986 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8987 // Concat upper and lower parts.
8990 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8991 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8992 // Concat upper and lower parts.
8995 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
8996 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8997 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
9000 if (Subtarget->hasInt256())
9001 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
9003 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
9004 SDValue Undef = DAG.getUNDEF(InVT);
9005 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
9006 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9007 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9009 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
9010 VT.getVectorNumElements()/2);
9012 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
9013 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
9015 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9018 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
9019 SelectionDAG &DAG) {
9020 MVT VT = Op->getSimpleValueType(0);
9021 SDValue In = Op->getOperand(0);
9022 MVT InVT = In.getSimpleValueType();
9024 unsigned int NumElts = VT.getVectorNumElements();
9025 if (NumElts != 8 && NumElts != 16)
9028 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
9029 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
9031 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
9032 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9033 // Now we have only mask extension
9034 assert(InVT.getVectorElementType() == MVT::i1);
9035 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
9036 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9037 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
9038 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9039 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9040 MachinePointerInfo::getConstantPool(),
9041 false, false, false, Alignment);
9043 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
9044 if (VT.is512BitVector())
9046 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
9049 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9050 SelectionDAG &DAG) {
9051 if (Subtarget->hasFp256()) {
9052 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9060 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9061 SelectionDAG &DAG) {
9063 MVT VT = Op.getSimpleValueType();
9064 SDValue In = Op.getOperand(0);
9065 MVT SVT = In.getSimpleValueType();
9067 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
9068 return LowerZERO_EXTEND_AVX512(Op, DAG);
9070 if (Subtarget->hasFp256()) {
9071 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9076 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
9077 VT.getVectorNumElements() != SVT.getVectorNumElements());
9081 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
9083 MVT VT = Op.getSimpleValueType();
9084 SDValue In = Op.getOperand(0);
9085 MVT InVT = In.getSimpleValueType();
9087 if (VT == MVT::i1) {
9088 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
9089 "Invalid scalar TRUNCATE operation");
9090 if (InVT == MVT::i32)
9092 if (InVT.getSizeInBits() == 64)
9093 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
9094 else if (InVT.getSizeInBits() < 32)
9095 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
9096 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
9098 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
9099 "Invalid TRUNCATE operation");
9101 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
9102 if (VT.getVectorElementType().getSizeInBits() >=8)
9103 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
9105 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
9106 unsigned NumElts = InVT.getVectorNumElements();
9107 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
9108 if (InVT.getSizeInBits() < 512) {
9109 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9110 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9114 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9115 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9116 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9117 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9118 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9119 MachinePointerInfo::getConstantPool(),
9120 false, false, false, Alignment);
9121 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9122 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9123 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9126 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9127 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9128 if (Subtarget->hasInt256()) {
9129 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9130 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9131 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9133 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9134 DAG.getIntPtrConstant(0));
9137 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9138 DAG.getIntPtrConstant(0));
9139 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9140 DAG.getIntPtrConstant(2));
9141 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9142 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9143 static const int ShufMask[] = {0, 2, 4, 6};
9144 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
9147 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9148 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9149 if (Subtarget->hasInt256()) {
9150 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9152 SmallVector<SDValue,32> pshufbMask;
9153 for (unsigned i = 0; i < 2; ++i) {
9154 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9155 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9156 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9157 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9158 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9159 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9160 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9161 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9162 for (unsigned j = 0; j < 8; ++j)
9163 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9165 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9166 &pshufbMask[0], 32);
9167 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9168 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9170 static const int ShufMask[] = {0, 2, -1, -1};
9171 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9173 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9174 DAG.getIntPtrConstant(0));
9175 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9178 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9179 DAG.getIntPtrConstant(0));
9181 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9182 DAG.getIntPtrConstant(4));
9184 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9185 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9188 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9189 -1, -1, -1, -1, -1, -1, -1, -1};
9191 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9192 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9193 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9195 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9196 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9198 // The MOVLHPS Mask:
9199 static const int ShufMask2[] = {0, 1, 4, 5};
9200 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9201 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9204 // Handle truncation of V256 to V128 using shuffles.
9205 if (!VT.is128BitVector() || !InVT.is256BitVector())
9208 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9210 unsigned NumElems = VT.getVectorNumElements();
9211 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
9213 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9214 // Prepare truncation shuffle mask
9215 for (unsigned i = 0; i != NumElems; ++i)
9217 SDValue V = DAG.getVectorShuffle(NVT, DL,
9218 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9219 DAG.getUNDEF(NVT), &MaskVec[0]);
9220 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9221 DAG.getIntPtrConstant(0));
9224 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9225 SelectionDAG &DAG) const {
9226 MVT VT = Op.getSimpleValueType();
9227 if (VT.isVector()) {
9228 if (VT == MVT::v8i16)
9229 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9230 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9231 MVT::v8i32, Op.getOperand(0)));
9235 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9236 /*IsSigned=*/ true, /*IsReplace=*/ false);
9237 SDValue FIST = Vals.first, StackSlot = Vals.second;
9238 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9239 if (FIST.getNode() == 0) return Op;
9241 if (StackSlot.getNode())
9243 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9244 FIST, StackSlot, MachinePointerInfo(),
9245 false, false, false, 0);
9247 // The node is the result.
9251 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9252 SelectionDAG &DAG) const {
9253 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9254 /*IsSigned=*/ false, /*IsReplace=*/ false);
9255 SDValue FIST = Vals.first, StackSlot = Vals.second;
9256 assert(FIST.getNode() && "Unexpected failure");
9258 if (StackSlot.getNode())
9260 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9261 FIST, StackSlot, MachinePointerInfo(),
9262 false, false, false, 0);
9264 // The node is the result.
9268 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9270 MVT VT = Op.getSimpleValueType();
9271 SDValue In = Op.getOperand(0);
9272 MVT SVT = In.getSimpleValueType();
9274 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9276 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9277 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9278 In, DAG.getUNDEF(SVT)));
9281 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
9282 LLVMContext *Context = DAG.getContext();
9284 MVT VT = Op.getSimpleValueType();
9286 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9287 if (VT.isVector()) {
9288 EltVT = VT.getVectorElementType();
9289 NumElts = VT.getVectorNumElements();
9292 if (EltVT == MVT::f64)
9293 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9294 APInt(64, ~(1ULL << 63))));
9296 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9297 APInt(32, ~(1U << 31))));
9298 C = ConstantVector::getSplat(NumElts, C);
9299 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9300 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9301 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9302 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9303 MachinePointerInfo::getConstantPool(),
9304 false, false, false, Alignment);
9305 if (VT.isVector()) {
9306 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9307 return DAG.getNode(ISD::BITCAST, dl, VT,
9308 DAG.getNode(ISD::AND, dl, ANDVT,
9309 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9311 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9313 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9316 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
9317 LLVMContext *Context = DAG.getContext();
9319 MVT VT = Op.getSimpleValueType();
9321 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9322 if (VT.isVector()) {
9323 EltVT = VT.getVectorElementType();
9324 NumElts = VT.getVectorNumElements();
9327 if (EltVT == MVT::f64)
9328 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9329 APInt(64, 1ULL << 63)));
9331 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9332 APInt(32, 1U << 31)));
9333 C = ConstantVector::getSplat(NumElts, C);
9334 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9335 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9336 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9337 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9338 MachinePointerInfo::getConstantPool(),
9339 false, false, false, Alignment);
9340 if (VT.isVector()) {
9341 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9342 return DAG.getNode(ISD::BITCAST, dl, VT,
9343 DAG.getNode(ISD::XOR, dl, XORVT,
9344 DAG.getNode(ISD::BITCAST, dl, XORVT,
9346 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9349 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9352 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
9353 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9354 LLVMContext *Context = DAG.getContext();
9355 SDValue Op0 = Op.getOperand(0);
9356 SDValue Op1 = Op.getOperand(1);
9358 MVT VT = Op.getSimpleValueType();
9359 MVT SrcVT = Op1.getSimpleValueType();
9361 // If second operand is smaller, extend it first.
9362 if (SrcVT.bitsLT(VT)) {
9363 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9366 // And if it is bigger, shrink it first.
9367 if (SrcVT.bitsGT(VT)) {
9368 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9372 // At this point the operands and the result should have the same
9373 // type, and that won't be f80 since that is not custom lowered.
9375 // First get the sign bit of second operand.
9376 SmallVector<Constant*,4> CV;
9377 if (SrcVT == MVT::f64) {
9378 const fltSemantics &Sem = APFloat::IEEEdouble;
9379 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9380 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9382 const fltSemantics &Sem = APFloat::IEEEsingle;
9383 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9384 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9385 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9386 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9388 Constant *C = ConstantVector::get(CV);
9389 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9390 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9391 MachinePointerInfo::getConstantPool(),
9392 false, false, false, 16);
9393 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9395 // Shift sign bit right or left if the two operands have different types.
9396 if (SrcVT.bitsGT(VT)) {
9397 // Op0 is MVT::f32, Op1 is MVT::f64.
9398 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9399 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9400 DAG.getConstant(32, MVT::i32));
9401 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9402 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9403 DAG.getIntPtrConstant(0));
9406 // Clear first operand sign bit.
9408 if (VT == MVT::f64) {
9409 const fltSemantics &Sem = APFloat::IEEEdouble;
9410 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9411 APInt(64, ~(1ULL << 63)))));
9412 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9414 const fltSemantics &Sem = APFloat::IEEEsingle;
9415 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9416 APInt(32, ~(1U << 31)))));
9417 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9418 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9419 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9421 C = ConstantVector::get(CV);
9422 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9423 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9424 MachinePointerInfo::getConstantPool(),
9425 false, false, false, 16);
9426 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9428 // Or the value with the sign bit.
9429 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9432 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9433 SDValue N0 = Op.getOperand(0);
9435 MVT VT = Op.getSimpleValueType();
9437 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9438 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9439 DAG.getConstant(1, VT));
9440 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9443 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9445 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9446 SelectionDAG &DAG) {
9447 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9449 if (!Subtarget->hasSSE41())
9452 if (!Op->hasOneUse())
9455 SDNode *N = Op.getNode();
9458 SmallVector<SDValue, 8> Opnds;
9459 DenseMap<SDValue, unsigned> VecInMap;
9460 EVT VT = MVT::Other;
9462 // Recognize a special case where a vector is casted into wide integer to
9464 Opnds.push_back(N->getOperand(0));
9465 Opnds.push_back(N->getOperand(1));
9467 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9468 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9469 // BFS traverse all OR'd operands.
9470 if (I->getOpcode() == ISD::OR) {
9471 Opnds.push_back(I->getOperand(0));
9472 Opnds.push_back(I->getOperand(1));
9473 // Re-evaluate the number of nodes to be traversed.
9474 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9478 // Quit if a non-EXTRACT_VECTOR_ELT
9479 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9482 // Quit if without a constant index.
9483 SDValue Idx = I->getOperand(1);
9484 if (!isa<ConstantSDNode>(Idx))
9487 SDValue ExtractedFromVec = I->getOperand(0);
9488 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9489 if (M == VecInMap.end()) {
9490 VT = ExtractedFromVec.getValueType();
9491 // Quit if not 128/256-bit vector.
9492 if (!VT.is128BitVector() && !VT.is256BitVector())
9494 // Quit if not the same type.
9495 if (VecInMap.begin() != VecInMap.end() &&
9496 VT != VecInMap.begin()->first.getValueType())
9498 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9500 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9503 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9504 "Not extracted from 128-/256-bit vector.");
9506 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9507 SmallVector<SDValue, 8> VecIns;
9509 for (DenseMap<SDValue, unsigned>::const_iterator
9510 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9511 // Quit if not all elements are used.
9512 if (I->second != FullMask)
9514 VecIns.push_back(I->first);
9517 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9519 // Cast all vectors into TestVT for PTEST.
9520 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9521 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9523 // If more than one full vectors are evaluated, OR them first before PTEST.
9524 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9525 // Each iteration will OR 2 nodes and append the result until there is only
9526 // 1 node left, i.e. the final OR'd value of all vectors.
9527 SDValue LHS = VecIns[Slot];
9528 SDValue RHS = VecIns[Slot + 1];
9529 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9532 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9533 VecIns.back(), VecIns.back());
9536 /// Emit nodes that will be selected as "test Op0,Op0", or something
9538 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9539 SelectionDAG &DAG) const {
9542 if (Op.getValueType() == MVT::i1)
9543 // KORTEST instruction should be selected
9544 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9545 DAG.getConstant(0, Op.getValueType()));
9547 // CF and OF aren't always set the way we want. Determine which
9548 // of these we need.
9549 bool NeedCF = false;
9550 bool NeedOF = false;
9553 case X86::COND_A: case X86::COND_AE:
9554 case X86::COND_B: case X86::COND_BE:
9557 case X86::COND_G: case X86::COND_GE:
9558 case X86::COND_L: case X86::COND_LE:
9559 case X86::COND_O: case X86::COND_NO:
9563 // See if we can use the EFLAGS value from the operand instead of
9564 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9565 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9566 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
9567 // Emit a CMP with 0, which is the TEST pattern.
9568 //if (Op.getValueType() == MVT::i1)
9569 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
9570 // DAG.getConstant(0, MVT::i1));
9571 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9572 DAG.getConstant(0, Op.getValueType()));
9574 unsigned Opcode = 0;
9575 unsigned NumOperands = 0;
9577 // Truncate operations may prevent the merge of the SETCC instruction
9578 // and the arithmetic instruction before it. Attempt to truncate the operands
9579 // of the arithmetic instruction and use a reduced bit-width instruction.
9580 bool NeedTruncation = false;
9581 SDValue ArithOp = Op;
9582 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9583 SDValue Arith = Op->getOperand(0);
9584 // Both the trunc and the arithmetic op need to have one user each.
9585 if (Arith->hasOneUse())
9586 switch (Arith.getOpcode()) {
9593 NeedTruncation = true;
9599 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9600 // which may be the result of a CAST. We use the variable 'Op', which is the
9601 // non-casted variable when we check for possible users.
9602 switch (ArithOp.getOpcode()) {
9604 // Due to an isel shortcoming, be conservative if this add is likely to be
9605 // selected as part of a load-modify-store instruction. When the root node
9606 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9607 // uses of other nodes in the match, such as the ADD in this case. This
9608 // leads to the ADD being left around and reselected, with the result being
9609 // two adds in the output. Alas, even if none our users are stores, that
9610 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9611 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9612 // climbing the DAG back to the root, and it doesn't seem to be worth the
9614 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9615 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9616 if (UI->getOpcode() != ISD::CopyToReg &&
9617 UI->getOpcode() != ISD::SETCC &&
9618 UI->getOpcode() != ISD::STORE)
9621 if (ConstantSDNode *C =
9622 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9623 // An add of one will be selected as an INC.
9624 if (C->getAPIntValue() == 1) {
9625 Opcode = X86ISD::INC;
9630 // An add of negative one (subtract of one) will be selected as a DEC.
9631 if (C->getAPIntValue().isAllOnesValue()) {
9632 Opcode = X86ISD::DEC;
9638 // Otherwise use a regular EFLAGS-setting add.
9639 Opcode = X86ISD::ADD;
9643 // If the primary and result isn't used, don't bother using X86ISD::AND,
9644 // because a TEST instruction will be better.
9645 bool NonFlagUse = false;
9646 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9647 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9649 unsigned UOpNo = UI.getOperandNo();
9650 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9651 // Look pass truncate.
9652 UOpNo = User->use_begin().getOperandNo();
9653 User = *User->use_begin();
9656 if (User->getOpcode() != ISD::BRCOND &&
9657 User->getOpcode() != ISD::SETCC &&
9658 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9671 // Due to the ISEL shortcoming noted above, be conservative if this op is
9672 // likely to be selected as part of a load-modify-store instruction.
9673 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9674 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9675 if (UI->getOpcode() == ISD::STORE)
9678 // Otherwise use a regular EFLAGS-setting instruction.
9679 switch (ArithOp.getOpcode()) {
9680 default: llvm_unreachable("unexpected operator!");
9681 case ISD::SUB: Opcode = X86ISD::SUB; break;
9682 case ISD::XOR: Opcode = X86ISD::XOR; break;
9683 case ISD::AND: Opcode = X86ISD::AND; break;
9685 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9686 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9687 if (EFLAGS.getNode())
9690 Opcode = X86ISD::OR;
9704 return SDValue(Op.getNode(), 1);
9710 // If we found that truncation is beneficial, perform the truncation and
9712 if (NeedTruncation) {
9713 EVT VT = Op.getValueType();
9714 SDValue WideVal = Op->getOperand(0);
9715 EVT WideVT = WideVal.getValueType();
9716 unsigned ConvertedOp = 0;
9717 // Use a target machine opcode to prevent further DAGCombine
9718 // optimizations that may separate the arithmetic operations
9719 // from the setcc node.
9720 switch (WideVal.getOpcode()) {
9722 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9723 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9724 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9725 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9726 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9730 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9731 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9732 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9733 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9734 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9740 // Emit a CMP with 0, which is the TEST pattern.
9741 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9742 DAG.getConstant(0, Op.getValueType()));
9744 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9745 SmallVector<SDValue, 4> Ops;
9746 for (unsigned i = 0; i != NumOperands; ++i)
9747 Ops.push_back(Op.getOperand(i));
9749 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9750 DAG.ReplaceAllUsesWith(Op, New);
9751 return SDValue(New.getNode(), 1);
9754 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9756 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9757 SelectionDAG &DAG) const {
9759 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
9760 if (C->getAPIntValue() == 0)
9761 return EmitTest(Op0, X86CC, DAG);
9763 if (Op0.getValueType() == MVT::i1)
9764 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
9767 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9768 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9769 // Do the comparison at i32 if it's smaller. This avoids subregister
9770 // aliasing issues. Keep the smaller reference if we're optimizing for
9771 // size, however, as that'll allow better folding of memory operations.
9772 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
9773 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
9774 AttributeSet::FunctionIndex, Attribute::MinSize)) {
9776 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
9777 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
9778 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
9780 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9781 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9782 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9784 return SDValue(Sub.getNode(), 1);
9786 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9789 /// Convert a comparison if required by the subtarget.
9790 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9791 SelectionDAG &DAG) const {
9792 // If the subtarget does not support the FUCOMI instruction, floating-point
9793 // comparisons have to be converted.
9794 if (Subtarget->hasCMov() ||
9795 Cmp.getOpcode() != X86ISD::CMP ||
9796 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9797 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9800 // The instruction selector will select an FUCOM instruction instead of
9801 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9802 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9803 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9805 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9806 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9807 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9808 DAG.getConstant(8, MVT::i8));
9809 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9810 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9813 static bool isAllOnes(SDValue V) {
9814 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9815 return C && C->isAllOnesValue();
9818 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9819 /// if it's possible.
9820 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9821 SDLoc dl, SelectionDAG &DAG) const {
9822 SDValue Op0 = And.getOperand(0);
9823 SDValue Op1 = And.getOperand(1);
9824 if (Op0.getOpcode() == ISD::TRUNCATE)
9825 Op0 = Op0.getOperand(0);
9826 if (Op1.getOpcode() == ISD::TRUNCATE)
9827 Op1 = Op1.getOperand(0);
9830 if (Op1.getOpcode() == ISD::SHL)
9831 std::swap(Op0, Op1);
9832 if (Op0.getOpcode() == ISD::SHL) {
9833 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9834 if (And00C->getZExtValue() == 1) {
9835 // If we looked past a truncate, check that it's only truncating away
9837 unsigned BitWidth = Op0.getValueSizeInBits();
9838 unsigned AndBitWidth = And.getValueSizeInBits();
9839 if (BitWidth > AndBitWidth) {
9841 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9842 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9846 RHS = Op0.getOperand(1);
9848 } else if (Op1.getOpcode() == ISD::Constant) {
9849 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9850 uint64_t AndRHSVal = AndRHS->getZExtValue();
9851 SDValue AndLHS = Op0;
9853 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9854 LHS = AndLHS.getOperand(0);
9855 RHS = AndLHS.getOperand(1);
9858 // Use BT if the immediate can't be encoded in a TEST instruction.
9859 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9861 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9865 if (LHS.getNode()) {
9866 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9867 // instruction. Since the shift amount is in-range-or-undefined, we know
9868 // that doing a bittest on the i32 value is ok. We extend to i32 because
9869 // the encoding for the i16 version is larger than the i32 version.
9870 // Also promote i16 to i32 for performance / code size reason.
9871 if (LHS.getValueType() == MVT::i8 ||
9872 LHS.getValueType() == MVT::i16)
9873 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9875 // If the operand types disagree, extend the shift amount to match. Since
9876 // BT ignores high bits (like shifts) we can use anyextend.
9877 if (LHS.getValueType() != RHS.getValueType())
9878 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9880 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9881 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9882 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9883 DAG.getConstant(Cond, MVT::i8), BT);
9889 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9891 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9896 // SSE Condition code mapping:
9905 switch (SetCCOpcode) {
9906 default: llvm_unreachable("Unexpected SETCC condition");
9908 case ISD::SETEQ: SSECC = 0; break;
9910 case ISD::SETGT: Swap = true; // Fallthrough
9912 case ISD::SETOLT: SSECC = 1; break;
9914 case ISD::SETGE: Swap = true; // Fallthrough
9916 case ISD::SETOLE: SSECC = 2; break;
9917 case ISD::SETUO: SSECC = 3; break;
9919 case ISD::SETNE: SSECC = 4; break;
9920 case ISD::SETULE: Swap = true; // Fallthrough
9921 case ISD::SETUGE: SSECC = 5; break;
9922 case ISD::SETULT: Swap = true; // Fallthrough
9923 case ISD::SETUGT: SSECC = 6; break;
9924 case ISD::SETO: SSECC = 7; break;
9926 case ISD::SETONE: SSECC = 8; break;
9929 std::swap(Op0, Op1);
9934 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9935 // ones, and then concatenate the result back.
9936 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9937 MVT VT = Op.getSimpleValueType();
9939 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9940 "Unsupported value type for operation");
9942 unsigned NumElems = VT.getVectorNumElements();
9944 SDValue CC = Op.getOperand(2);
9946 // Extract the LHS vectors
9947 SDValue LHS = Op.getOperand(0);
9948 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9949 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9951 // Extract the RHS vectors
9952 SDValue RHS = Op.getOperand(1);
9953 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9954 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9956 // Issue the operation on the smaller types and concatenate the result back
9957 MVT EltVT = VT.getVectorElementType();
9958 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9959 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9960 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9961 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9964 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
9965 const X86Subtarget *Subtarget) {
9966 SDValue Op0 = Op.getOperand(0);
9967 SDValue Op1 = Op.getOperand(1);
9968 SDValue CC = Op.getOperand(2);
9969 MVT VT = Op.getSimpleValueType();
9972 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9973 Op.getValueType().getScalarType() == MVT::i1 &&
9974 "Cannot set masked compare for this operation");
9976 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9978 bool Unsigned = false;
9981 switch (SetCCOpcode) {
9982 default: llvm_unreachable("Unexpected SETCC condition");
9983 case ISD::SETNE: SSECC = 4; break;
9984 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
9985 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
9986 case ISD::SETLT: Swap = true; //fall-through
9987 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
9988 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
9989 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
9990 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
9991 case ISD::SETULE: Unsigned = true; //fall-through
9992 case ISD::SETLE: SSECC = 2; break;
9996 std::swap(Op0, Op1);
9998 return DAG.getNode(Opc, dl, VT, Op0, Op1);
9999 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
10000 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10001 DAG.getConstant(SSECC, MVT::i8));
10004 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
10005 /// operand \p Op1. If non-trivial (for example because it's not constant)
10006 /// return an empty value.
10007 static SDValue ChangeVSETULTtoVSETULE(SDValue Op1, SelectionDAG &DAG)
10009 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
10013 MVT VT = Op1.getSimpleValueType();
10014 MVT EVT = VT.getVectorElementType();
10015 unsigned n = VT.getVectorNumElements();
10016 SmallVector<SDValue, 8> ULTOp1;
10018 for (unsigned i = 0; i < n; ++i) {
10019 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
10020 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
10023 // Avoid underflow.
10024 APInt Val = Elt->getAPIntValue();
10028 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
10031 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op1), VT, ULTOp1.data(),
10035 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
10036 SelectionDAG &DAG) {
10037 SDValue Op0 = Op.getOperand(0);
10038 SDValue Op1 = Op.getOperand(1);
10039 SDValue CC = Op.getOperand(2);
10040 MVT VT = Op.getSimpleValueType();
10041 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10042 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
10047 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
10048 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
10051 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
10052 unsigned Opc = X86ISD::CMPP;
10053 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
10054 assert(VT.getVectorNumElements() <= 16);
10055 Opc = X86ISD::CMPM;
10057 // In the two special cases we can't handle, emit two comparisons.
10060 unsigned CombineOpc;
10061 if (SetCCOpcode == ISD::SETUEQ) {
10062 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
10064 assert(SetCCOpcode == ISD::SETONE);
10065 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
10068 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10069 DAG.getConstant(CC0, MVT::i8));
10070 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10071 DAG.getConstant(CC1, MVT::i8));
10072 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
10074 // Handle all other FP comparisons here.
10075 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10076 DAG.getConstant(SSECC, MVT::i8));
10079 // Break 256-bit integer vector compare into smaller ones.
10080 if (VT.is256BitVector() && !Subtarget->hasInt256())
10081 return Lower256IntVSETCC(Op, DAG);
10083 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
10084 EVT OpVT = Op1.getValueType();
10085 if (Subtarget->hasAVX512()) {
10086 if (Op1.getValueType().is512BitVector() ||
10087 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
10088 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
10090 // In AVX-512 architecture setcc returns mask with i1 elements,
10091 // But there is no compare instruction for i8 and i16 elements.
10092 // We are not talking about 512-bit operands in this case, these
10093 // types are illegal.
10095 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
10096 OpVT.getVectorElementType().getSizeInBits() >= 8))
10097 return DAG.getNode(ISD::TRUNCATE, dl, VT,
10098 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
10101 // We are handling one of the integer comparisons here. Since SSE only has
10102 // GT and EQ comparisons for integer, swapping operands and multiple
10103 // operations may be required for some comparisons.
10105 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
10106 bool Subus = false;
10108 switch (SetCCOpcode) {
10109 default: llvm_unreachable("Unexpected SETCC condition");
10110 case ISD::SETNE: Invert = true;
10111 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
10112 case ISD::SETLT: Swap = true;
10113 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
10114 case ISD::SETGE: Swap = true;
10115 case ISD::SETLE: Opc = X86ISD::PCMPGT;
10116 Invert = true; break;
10117 case ISD::SETULT: Swap = true;
10118 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
10119 FlipSigns = true; break;
10120 case ISD::SETUGE: Swap = true;
10121 case ISD::SETULE: Opc = X86ISD::PCMPGT;
10122 FlipSigns = true; Invert = true; break;
10125 // Special case: Use min/max operations for SETULE/SETUGE
10126 MVT VET = VT.getVectorElementType();
10128 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
10129 || (Subtarget->hasSSE2() && (VET == MVT::i8));
10132 switch (SetCCOpcode) {
10134 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
10135 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
10138 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
10141 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
10142 if (!MinMax && hasSubus) {
10143 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
10145 // t = psubus Op0, Op1
10146 // pcmpeq t, <0..0>
10147 switch (SetCCOpcode) {
10149 case ISD::SETULT: {
10150 // If the comparison is against a constant we can turn this into a
10151 // setule. With psubus, setule does not require a swap. This is
10152 // beneficial because the constant in the register is no longer
10153 // destructed as the destination so it can be hoisted out of a loop.
10154 // Only do this pre-AVX since vpcmp* is no longer destructive.
10155 if (Subtarget->hasAVX())
10157 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(Op1, DAG);
10158 if (ULEOp1.getNode()) {
10160 Subus = true; Invert = false; Swap = false;
10164 // Psubus is better than flip-sign because it requires no inversion.
10165 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
10166 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
10170 Opc = X86ISD::SUBUS;
10176 std::swap(Op0, Op1);
10178 // Check that the operation in question is available (most are plain SSE2,
10179 // but PCMPGTQ and PCMPEQQ have different requirements).
10180 if (VT == MVT::v2i64) {
10181 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
10182 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
10184 // First cast everything to the right type.
10185 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10186 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10188 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10189 // bits of the inputs before performing those operations. The lower
10190 // compare is always unsigned.
10193 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
10195 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
10196 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10197 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10198 Sign, Zero, Sign, Zero);
10200 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10201 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10203 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10204 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10205 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10207 // Create masks for only the low parts/high parts of the 64 bit integers.
10208 static const int MaskHi[] = { 1, 1, 3, 3 };
10209 static const int MaskLo[] = { 0, 0, 2, 2 };
10210 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10211 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10212 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10214 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10215 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10218 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10220 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10223 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10224 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10225 // pcmpeqd + pshufd + pand.
10226 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10228 // First cast everything to the right type.
10229 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10230 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10233 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10235 // Make sure the lower and upper halves are both all-ones.
10236 static const int Mask[] = { 1, 0, 3, 2 };
10237 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10238 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10241 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10243 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10247 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10248 // bits of the inputs before performing those operations.
10250 EVT EltVT = VT.getVectorElementType();
10251 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10252 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10253 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10256 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10258 // If the logical-not of the result is required, perform that now.
10260 Result = DAG.getNOT(dl, Result, VT);
10263 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10266 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
10267 getZeroVector(VT, Subtarget, DAG, dl));
10272 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10274 MVT VT = Op.getSimpleValueType();
10276 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10278 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
10279 && "SetCC type must be 8-bit or 1-bit integer");
10280 SDValue Op0 = Op.getOperand(0);
10281 SDValue Op1 = Op.getOperand(1);
10283 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10285 // Optimize to BT if possible.
10286 // Lower (X & (1 << N)) == 0 to BT(X, N).
10287 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10288 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10289 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10290 Op1.getOpcode() == ISD::Constant &&
10291 cast<ConstantSDNode>(Op1)->isNullValue() &&
10292 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10293 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10294 if (NewSetCC.getNode())
10298 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10300 if (Op1.getOpcode() == ISD::Constant &&
10301 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10302 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10303 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10305 // If the input is a setcc, then reuse the input setcc or use a new one with
10306 // the inverted condition.
10307 if (Op0.getOpcode() == X86ISD::SETCC) {
10308 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10309 bool Invert = (CC == ISD::SETNE) ^
10310 cast<ConstantSDNode>(Op1)->isNullValue();
10314 CCode = X86::GetOppositeBranchCondition(CCode);
10315 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10316 DAG.getConstant(CCode, MVT::i8),
10317 Op0.getOperand(1));
10319 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10323 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
10324 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
10325 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10327 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
10328 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
10331 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10332 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10333 if (X86CC == X86::COND_INVALID)
10336 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10337 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10338 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10339 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10341 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10345 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10346 static bool isX86LogicalCmp(SDValue Op) {
10347 unsigned Opc = Op.getNode()->getOpcode();
10348 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10349 Opc == X86ISD::SAHF)
10351 if (Op.getResNo() == 1 &&
10352 (Opc == X86ISD::ADD ||
10353 Opc == X86ISD::SUB ||
10354 Opc == X86ISD::ADC ||
10355 Opc == X86ISD::SBB ||
10356 Opc == X86ISD::SMUL ||
10357 Opc == X86ISD::UMUL ||
10358 Opc == X86ISD::INC ||
10359 Opc == X86ISD::DEC ||
10360 Opc == X86ISD::OR ||
10361 Opc == X86ISD::XOR ||
10362 Opc == X86ISD::AND))
10365 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10371 static bool isZero(SDValue V) {
10372 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10373 return C && C->isNullValue();
10376 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10377 if (V.getOpcode() != ISD::TRUNCATE)
10380 SDValue VOp0 = V.getOperand(0);
10381 unsigned InBits = VOp0.getValueSizeInBits();
10382 unsigned Bits = V.getValueSizeInBits();
10383 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10386 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10387 bool addTest = true;
10388 SDValue Cond = Op.getOperand(0);
10389 SDValue Op1 = Op.getOperand(1);
10390 SDValue Op2 = Op.getOperand(2);
10392 EVT VT = Op1.getValueType();
10395 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10396 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10397 // sequence later on.
10398 if (Cond.getOpcode() == ISD::SETCC &&
10399 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10400 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10401 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10402 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10403 int SSECC = translateX86FSETCC(
10404 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10407 if (Subtarget->hasAVX512()) {
10408 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
10409 DAG.getConstant(SSECC, MVT::i8));
10410 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
10412 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
10413 DAG.getConstant(SSECC, MVT::i8));
10414 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10415 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10416 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10420 if (Cond.getOpcode() == ISD::SETCC) {
10421 SDValue NewCond = LowerSETCC(Cond, DAG);
10422 if (NewCond.getNode())
10426 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10427 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10428 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10429 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10430 if (Cond.getOpcode() == X86ISD::SETCC &&
10431 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10432 isZero(Cond.getOperand(1).getOperand(1))) {
10433 SDValue Cmp = Cond.getOperand(1);
10435 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10437 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10438 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10439 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10441 SDValue CmpOp0 = Cmp.getOperand(0);
10442 // Apply further optimizations for special cases
10443 // (select (x != 0), -1, 0) -> neg & sbb
10444 // (select (x == 0), 0, -1) -> neg & sbb
10445 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10446 if (YC->isNullValue() &&
10447 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10448 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10449 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10450 DAG.getConstant(0, CmpOp0.getValueType()),
10452 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10453 DAG.getConstant(X86::COND_B, MVT::i8),
10454 SDValue(Neg.getNode(), 1));
10458 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10459 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10460 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10462 SDValue Res = // Res = 0 or -1.
10463 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10464 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10466 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10467 Res = DAG.getNOT(DL, Res, Res.getValueType());
10469 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10470 if (N2C == 0 || !N2C->isNullValue())
10471 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10476 // Look past (and (setcc_carry (cmp ...)), 1).
10477 if (Cond.getOpcode() == ISD::AND &&
10478 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10479 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10480 if (C && C->getAPIntValue() == 1)
10481 Cond = Cond.getOperand(0);
10484 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10485 // setting operand in place of the X86ISD::SETCC.
10486 unsigned CondOpcode = Cond.getOpcode();
10487 if (CondOpcode == X86ISD::SETCC ||
10488 CondOpcode == X86ISD::SETCC_CARRY) {
10489 CC = Cond.getOperand(0);
10491 SDValue Cmp = Cond.getOperand(1);
10492 unsigned Opc = Cmp.getOpcode();
10493 MVT VT = Op.getSimpleValueType();
10495 bool IllegalFPCMov = false;
10496 if (VT.isFloatingPoint() && !VT.isVector() &&
10497 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10498 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10500 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10501 Opc == X86ISD::BT) { // FIXME
10505 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10506 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10507 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10508 Cond.getOperand(0).getValueType() != MVT::i8)) {
10509 SDValue LHS = Cond.getOperand(0);
10510 SDValue RHS = Cond.getOperand(1);
10511 unsigned X86Opcode;
10514 switch (CondOpcode) {
10515 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10516 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10517 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10518 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10519 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10520 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10521 default: llvm_unreachable("unexpected overflowing operator");
10523 if (CondOpcode == ISD::UMULO)
10524 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10527 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10529 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10531 if (CondOpcode == ISD::UMULO)
10532 Cond = X86Op.getValue(2);
10534 Cond = X86Op.getValue(1);
10536 CC = DAG.getConstant(X86Cond, MVT::i8);
10541 // Look pass the truncate if the high bits are known zero.
10542 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10543 Cond = Cond.getOperand(0);
10545 // We know the result of AND is compared against zero. Try to match
10547 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10548 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10549 if (NewSetCC.getNode()) {
10550 CC = NewSetCC.getOperand(0);
10551 Cond = NewSetCC.getOperand(1);
10558 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10559 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10562 // a < b ? -1 : 0 -> RES = ~setcc_carry
10563 // a < b ? 0 : -1 -> RES = setcc_carry
10564 // a >= b ? -1 : 0 -> RES = setcc_carry
10565 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10566 if (Cond.getOpcode() == X86ISD::SUB) {
10567 Cond = ConvertCmpIfNecessary(Cond, DAG);
10568 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10570 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10571 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10572 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10573 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10574 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10575 return DAG.getNOT(DL, Res, Res.getValueType());
10580 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10581 // widen the cmov and push the truncate through. This avoids introducing a new
10582 // branch during isel and doesn't add any extensions.
10583 if (Op.getValueType() == MVT::i8 &&
10584 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10585 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10586 if (T1.getValueType() == T2.getValueType() &&
10587 // Blacklist CopyFromReg to avoid partial register stalls.
10588 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10589 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10590 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10591 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10595 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10596 // condition is true.
10597 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10598 SDValue Ops[] = { Op2, Op1, CC, Cond };
10599 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10602 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10603 MVT VT = Op->getSimpleValueType(0);
10604 SDValue In = Op->getOperand(0);
10605 MVT InVT = In.getSimpleValueType();
10608 unsigned int NumElts = VT.getVectorNumElements();
10609 if (NumElts != 8 && NumElts != 16)
10612 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10613 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10615 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10616 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10618 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10619 Constant *C = ConstantInt::get(*DAG.getContext(),
10620 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10622 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10623 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10624 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10625 MachinePointerInfo::getConstantPool(),
10626 false, false, false, Alignment);
10627 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10628 if (VT.is512BitVector())
10630 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10633 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10634 SelectionDAG &DAG) {
10635 MVT VT = Op->getSimpleValueType(0);
10636 SDValue In = Op->getOperand(0);
10637 MVT InVT = In.getSimpleValueType();
10640 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10641 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10643 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10644 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10645 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10648 if (Subtarget->hasInt256())
10649 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10651 // Optimize vectors in AVX mode
10652 // Sign extend v8i16 to v8i32 and
10655 // Divide input vector into two parts
10656 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10657 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10658 // concat the vectors to original VT
10660 unsigned NumElems = InVT.getVectorNumElements();
10661 SDValue Undef = DAG.getUNDEF(InVT);
10663 SmallVector<int,8> ShufMask1(NumElems, -1);
10664 for (unsigned i = 0; i != NumElems/2; ++i)
10667 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10669 SmallVector<int,8> ShufMask2(NumElems, -1);
10670 for (unsigned i = 0; i != NumElems/2; ++i)
10671 ShufMask2[i] = i + NumElems/2;
10673 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10675 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10676 VT.getVectorNumElements()/2);
10678 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
10679 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
10681 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10684 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10685 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10686 // from the AND / OR.
10687 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10688 Opc = Op.getOpcode();
10689 if (Opc != ISD::OR && Opc != ISD::AND)
10691 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10692 Op.getOperand(0).hasOneUse() &&
10693 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10694 Op.getOperand(1).hasOneUse());
10697 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10698 // 1 and that the SETCC node has a single use.
10699 static bool isXor1OfSetCC(SDValue Op) {
10700 if (Op.getOpcode() != ISD::XOR)
10702 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10703 if (N1C && N1C->getAPIntValue() == 1) {
10704 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10705 Op.getOperand(0).hasOneUse();
10710 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10711 bool addTest = true;
10712 SDValue Chain = Op.getOperand(0);
10713 SDValue Cond = Op.getOperand(1);
10714 SDValue Dest = Op.getOperand(2);
10717 bool Inverted = false;
10719 if (Cond.getOpcode() == ISD::SETCC) {
10720 // Check for setcc([su]{add,sub,mul}o == 0).
10721 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10722 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10723 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10724 Cond.getOperand(0).getResNo() == 1 &&
10725 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10726 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10727 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10728 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10729 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10730 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10732 Cond = Cond.getOperand(0);
10734 SDValue NewCond = LowerSETCC(Cond, DAG);
10735 if (NewCond.getNode())
10740 // FIXME: LowerXALUO doesn't handle these!!
10741 else if (Cond.getOpcode() == X86ISD::ADD ||
10742 Cond.getOpcode() == X86ISD::SUB ||
10743 Cond.getOpcode() == X86ISD::SMUL ||
10744 Cond.getOpcode() == X86ISD::UMUL)
10745 Cond = LowerXALUO(Cond, DAG);
10748 // Look pass (and (setcc_carry (cmp ...)), 1).
10749 if (Cond.getOpcode() == ISD::AND &&
10750 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10751 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10752 if (C && C->getAPIntValue() == 1)
10753 Cond = Cond.getOperand(0);
10756 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10757 // setting operand in place of the X86ISD::SETCC.
10758 unsigned CondOpcode = Cond.getOpcode();
10759 if (CondOpcode == X86ISD::SETCC ||
10760 CondOpcode == X86ISD::SETCC_CARRY) {
10761 CC = Cond.getOperand(0);
10763 SDValue Cmp = Cond.getOperand(1);
10764 unsigned Opc = Cmp.getOpcode();
10765 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10766 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10770 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10774 // These can only come from an arithmetic instruction with overflow,
10775 // e.g. SADDO, UADDO.
10776 Cond = Cond.getNode()->getOperand(1);
10782 CondOpcode = Cond.getOpcode();
10783 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10784 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10785 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10786 Cond.getOperand(0).getValueType() != MVT::i8)) {
10787 SDValue LHS = Cond.getOperand(0);
10788 SDValue RHS = Cond.getOperand(1);
10789 unsigned X86Opcode;
10792 // Keep this in sync with LowerXALUO, otherwise we might create redundant
10793 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
10795 switch (CondOpcode) {
10796 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10798 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10800 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
10803 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10804 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10806 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10808 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
10811 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10812 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10813 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10814 default: llvm_unreachable("unexpected overflowing operator");
10817 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10818 if (CondOpcode == ISD::UMULO)
10819 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10822 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10824 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10826 if (CondOpcode == ISD::UMULO)
10827 Cond = X86Op.getValue(2);
10829 Cond = X86Op.getValue(1);
10831 CC = DAG.getConstant(X86Cond, MVT::i8);
10835 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10836 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10837 if (CondOpc == ISD::OR) {
10838 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10839 // two branches instead of an explicit OR instruction with a
10841 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10842 isX86LogicalCmp(Cmp)) {
10843 CC = Cond.getOperand(0).getOperand(0);
10844 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10845 Chain, Dest, CC, Cmp);
10846 CC = Cond.getOperand(1).getOperand(0);
10850 } else { // ISD::AND
10851 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10852 // two branches instead of an explicit AND instruction with a
10853 // separate test. However, we only do this if this block doesn't
10854 // have a fall-through edge, because this requires an explicit
10855 // jmp when the condition is false.
10856 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10857 isX86LogicalCmp(Cmp) &&
10858 Op.getNode()->hasOneUse()) {
10859 X86::CondCode CCode =
10860 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10861 CCode = X86::GetOppositeBranchCondition(CCode);
10862 CC = DAG.getConstant(CCode, MVT::i8);
10863 SDNode *User = *Op.getNode()->use_begin();
10864 // Look for an unconditional branch following this conditional branch.
10865 // We need this because we need to reverse the successors in order
10866 // to implement FCMP_OEQ.
10867 if (User->getOpcode() == ISD::BR) {
10868 SDValue FalseBB = User->getOperand(1);
10870 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10871 assert(NewBR == User);
10875 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10876 Chain, Dest, CC, Cmp);
10877 X86::CondCode CCode =
10878 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10879 CCode = X86::GetOppositeBranchCondition(CCode);
10880 CC = DAG.getConstant(CCode, MVT::i8);
10886 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10887 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10888 // It should be transformed during dag combiner except when the condition
10889 // is set by a arithmetics with overflow node.
10890 X86::CondCode CCode =
10891 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10892 CCode = X86::GetOppositeBranchCondition(CCode);
10893 CC = DAG.getConstant(CCode, MVT::i8);
10894 Cond = Cond.getOperand(0).getOperand(1);
10896 } else if (Cond.getOpcode() == ISD::SETCC &&
10897 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10898 // For FCMP_OEQ, we can emit
10899 // two branches instead of an explicit AND instruction with a
10900 // separate test. However, we only do this if this block doesn't
10901 // have a fall-through edge, because this requires an explicit
10902 // jmp when the condition is false.
10903 if (Op.getNode()->hasOneUse()) {
10904 SDNode *User = *Op.getNode()->use_begin();
10905 // Look for an unconditional branch following this conditional branch.
10906 // We need this because we need to reverse the successors in order
10907 // to implement FCMP_OEQ.
10908 if (User->getOpcode() == ISD::BR) {
10909 SDValue FalseBB = User->getOperand(1);
10911 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10912 assert(NewBR == User);
10916 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10917 Cond.getOperand(0), Cond.getOperand(1));
10918 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10919 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10920 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10921 Chain, Dest, CC, Cmp);
10922 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10927 } else if (Cond.getOpcode() == ISD::SETCC &&
10928 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10929 // For FCMP_UNE, we can emit
10930 // two branches instead of an explicit AND instruction with a
10931 // separate test. However, we only do this if this block doesn't
10932 // have a fall-through edge, because this requires an explicit
10933 // jmp when the condition is false.
10934 if (Op.getNode()->hasOneUse()) {
10935 SDNode *User = *Op.getNode()->use_begin();
10936 // Look for an unconditional branch following this conditional branch.
10937 // We need this because we need to reverse the successors in order
10938 // to implement FCMP_UNE.
10939 if (User->getOpcode() == ISD::BR) {
10940 SDValue FalseBB = User->getOperand(1);
10942 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10943 assert(NewBR == User);
10946 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10947 Cond.getOperand(0), Cond.getOperand(1));
10948 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10949 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10950 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10951 Chain, Dest, CC, Cmp);
10952 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10962 // Look pass the truncate if the high bits are known zero.
10963 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10964 Cond = Cond.getOperand(0);
10966 // We know the result of AND is compared against zero. Try to match
10968 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10969 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10970 if (NewSetCC.getNode()) {
10971 CC = NewSetCC.getOperand(0);
10972 Cond = NewSetCC.getOperand(1);
10979 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10980 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10982 Cond = ConvertCmpIfNecessary(Cond, DAG);
10983 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10984 Chain, Dest, CC, Cond);
10987 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10988 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10989 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10990 // that the guard pages used by the OS virtual memory manager are allocated in
10991 // correct sequence.
10993 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10994 SelectionDAG &DAG) const {
10995 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10996 getTargetMachine().Options.EnableSegmentedStacks) &&
10997 "This should be used only on Windows targets or when segmented stacks "
10999 assert(!Subtarget->isTargetMacho() && "Not implemented");
11003 SDValue Chain = Op.getOperand(0);
11004 SDValue Size = Op.getOperand(1);
11005 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
11006 EVT VT = Op.getNode()->getValueType(0);
11008 bool Is64Bit = Subtarget->is64Bit();
11009 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
11011 if (getTargetMachine().Options.EnableSegmentedStacks) {
11012 MachineFunction &MF = DAG.getMachineFunction();
11013 MachineRegisterInfo &MRI = MF.getRegInfo();
11016 // The 64 bit implementation of segmented stacks needs to clobber both r10
11017 // r11. This makes it impossible to use it along with nested parameters.
11018 const Function *F = MF.getFunction();
11020 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
11022 if (I->hasNestAttr())
11023 report_fatal_error("Cannot use segmented stacks with functions that "
11024 "have nested arguments.");
11027 const TargetRegisterClass *AddrRegClass =
11028 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
11029 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
11030 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
11031 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
11032 DAG.getRegister(Vreg, SPTy));
11033 SDValue Ops1[2] = { Value, Chain };
11034 return DAG.getMergeValues(Ops1, 2, dl);
11037 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
11039 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
11040 Flag = Chain.getValue(1);
11041 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11043 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
11045 const X86RegisterInfo *RegInfo =
11046 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11047 unsigned SPReg = RegInfo->getStackRegister();
11048 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
11049 Chain = SP.getValue(1);
11052 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
11053 DAG.getConstant(-(uint64_t)Align, VT));
11054 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
11057 SDValue Ops1[2] = { SP, Chain };
11058 return DAG.getMergeValues(Ops1, 2, dl);
11062 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
11063 MachineFunction &MF = DAG.getMachineFunction();
11064 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
11066 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11069 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
11070 // vastart just stores the address of the VarArgsFrameIndex slot into the
11071 // memory location argument.
11072 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11074 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
11075 MachinePointerInfo(SV), false, false, 0);
11079 // gp_offset (0 - 6 * 8)
11080 // fp_offset (48 - 48 + 8 * 16)
11081 // overflow_arg_area (point to parameters coming in memory).
11083 SmallVector<SDValue, 8> MemOps;
11084 SDValue FIN = Op.getOperand(1);
11086 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
11087 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
11089 FIN, MachinePointerInfo(SV), false, false, 0);
11090 MemOps.push_back(Store);
11093 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11094 FIN, DAG.getIntPtrConstant(4));
11095 Store = DAG.getStore(Op.getOperand(0), DL,
11096 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
11098 FIN, MachinePointerInfo(SV, 4), false, false, 0);
11099 MemOps.push_back(Store);
11101 // Store ptr to overflow_arg_area
11102 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11103 FIN, DAG.getIntPtrConstant(4));
11104 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11106 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
11107 MachinePointerInfo(SV, 8),
11109 MemOps.push_back(Store);
11111 // Store ptr to reg_save_area.
11112 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11113 FIN, DAG.getIntPtrConstant(8));
11114 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
11116 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
11117 MachinePointerInfo(SV, 16), false, false, 0);
11118 MemOps.push_back(Store);
11119 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
11120 &MemOps[0], MemOps.size());
11123 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
11124 assert(Subtarget->is64Bit() &&
11125 "LowerVAARG only handles 64-bit va_arg!");
11126 assert((Subtarget->isTargetLinux() ||
11127 Subtarget->isTargetDarwin()) &&
11128 "Unhandled target in LowerVAARG");
11129 assert(Op.getNode()->getNumOperands() == 4);
11130 SDValue Chain = Op.getOperand(0);
11131 SDValue SrcPtr = Op.getOperand(1);
11132 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11133 unsigned Align = Op.getConstantOperandVal(3);
11136 EVT ArgVT = Op.getNode()->getValueType(0);
11137 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11138 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
11141 // Decide which area this value should be read from.
11142 // TODO: Implement the AMD64 ABI in its entirety. This simple
11143 // selection mechanism works only for the basic types.
11144 if (ArgVT == MVT::f80) {
11145 llvm_unreachable("va_arg for f80 not yet implemented");
11146 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
11147 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
11148 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
11149 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
11151 llvm_unreachable("Unhandled argument type in LowerVAARG");
11154 if (ArgMode == 2) {
11155 // Sanity Check: Make sure using fp_offset makes sense.
11156 assert(!getTargetMachine().Options.UseSoftFloat &&
11157 !(DAG.getMachineFunction()
11158 .getFunction()->getAttributes()
11159 .hasAttribute(AttributeSet::FunctionIndex,
11160 Attribute::NoImplicitFloat)) &&
11161 Subtarget->hasSSE1());
11164 // Insert VAARG_64 node into the DAG
11165 // VAARG_64 returns two values: Variable Argument Address, Chain
11166 SmallVector<SDValue, 11> InstOps;
11167 InstOps.push_back(Chain);
11168 InstOps.push_back(SrcPtr);
11169 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
11170 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
11171 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
11172 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
11173 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
11174 VTs, &InstOps[0], InstOps.size(),
11176 MachinePointerInfo(SV),
11178 /*Volatile=*/false,
11180 /*WriteMem=*/true);
11181 Chain = VAARG.getValue(1);
11183 // Load the next argument and return it
11184 return DAG.getLoad(ArgVT, dl,
11187 MachinePointerInfo(),
11188 false, false, false, 0);
11191 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
11192 SelectionDAG &DAG) {
11193 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
11194 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
11195 SDValue Chain = Op.getOperand(0);
11196 SDValue DstPtr = Op.getOperand(1);
11197 SDValue SrcPtr = Op.getOperand(2);
11198 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
11199 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11202 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
11203 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
11205 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
11208 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
11209 // amount is a constant. Takes immediate version of shift as input.
11210 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
11211 SDValue SrcOp, uint64_t ShiftAmt,
11212 SelectionDAG &DAG) {
11213 MVT ElementType = VT.getVectorElementType();
11215 // Check for ShiftAmt >= element width
11216 if (ShiftAmt >= ElementType.getSizeInBits()) {
11217 if (Opc == X86ISD::VSRAI)
11218 ShiftAmt = ElementType.getSizeInBits() - 1;
11220 return DAG.getConstant(0, VT);
11223 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
11224 && "Unknown target vector shift-by-constant node");
11226 // Fold this packed vector shift into a build vector if SrcOp is a
11227 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
11228 if (VT == SrcOp.getSimpleValueType() &&
11229 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
11230 SmallVector<SDValue, 8> Elts;
11231 unsigned NumElts = SrcOp->getNumOperands();
11232 ConstantSDNode *ND;
11235 default: llvm_unreachable(0);
11236 case X86ISD::VSHLI:
11237 for (unsigned i=0; i!=NumElts; ++i) {
11238 SDValue CurrentOp = SrcOp->getOperand(i);
11239 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11240 Elts.push_back(CurrentOp);
11243 ND = cast<ConstantSDNode>(CurrentOp);
11244 const APInt &C = ND->getAPIntValue();
11245 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
11248 case X86ISD::VSRLI:
11249 for (unsigned i=0; i!=NumElts; ++i) {
11250 SDValue CurrentOp = SrcOp->getOperand(i);
11251 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11252 Elts.push_back(CurrentOp);
11255 ND = cast<ConstantSDNode>(CurrentOp);
11256 const APInt &C = ND->getAPIntValue();
11257 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
11260 case X86ISD::VSRAI:
11261 for (unsigned i=0; i!=NumElts; ++i) {
11262 SDValue CurrentOp = SrcOp->getOperand(i);
11263 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11264 Elts.push_back(CurrentOp);
11267 ND = cast<ConstantSDNode>(CurrentOp);
11268 const APInt &C = ND->getAPIntValue();
11269 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
11274 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Elts[0], NumElts);
11277 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
11280 // getTargetVShiftNode - Handle vector element shifts where the shift amount
11281 // may or may not be a constant. Takes immediate version of shift as input.
11282 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
11283 SDValue SrcOp, SDValue ShAmt,
11284 SelectionDAG &DAG) {
11285 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
11287 // Catch shift-by-constant.
11288 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11289 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11290 CShAmt->getZExtValue(), DAG);
11292 // Change opcode to non-immediate version
11294 default: llvm_unreachable("Unknown target vector shift node");
11295 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11296 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11297 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11300 // Need to build a vector containing shift amount
11301 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11304 ShOps[1] = DAG.getConstant(0, MVT::i32);
11305 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11306 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
11308 // The return type has to be a 128-bit type with the same element
11309 // type as the input type.
11310 MVT EltVT = VT.getVectorElementType();
11311 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11313 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11314 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11317 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11319 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11321 default: return SDValue(); // Don't custom lower most intrinsics.
11322 // Comparison intrinsics.
11323 case Intrinsic::x86_sse_comieq_ss:
11324 case Intrinsic::x86_sse_comilt_ss:
11325 case Intrinsic::x86_sse_comile_ss:
11326 case Intrinsic::x86_sse_comigt_ss:
11327 case Intrinsic::x86_sse_comige_ss:
11328 case Intrinsic::x86_sse_comineq_ss:
11329 case Intrinsic::x86_sse_ucomieq_ss:
11330 case Intrinsic::x86_sse_ucomilt_ss:
11331 case Intrinsic::x86_sse_ucomile_ss:
11332 case Intrinsic::x86_sse_ucomigt_ss:
11333 case Intrinsic::x86_sse_ucomige_ss:
11334 case Intrinsic::x86_sse_ucomineq_ss:
11335 case Intrinsic::x86_sse2_comieq_sd:
11336 case Intrinsic::x86_sse2_comilt_sd:
11337 case Intrinsic::x86_sse2_comile_sd:
11338 case Intrinsic::x86_sse2_comigt_sd:
11339 case Intrinsic::x86_sse2_comige_sd:
11340 case Intrinsic::x86_sse2_comineq_sd:
11341 case Intrinsic::x86_sse2_ucomieq_sd:
11342 case Intrinsic::x86_sse2_ucomilt_sd:
11343 case Intrinsic::x86_sse2_ucomile_sd:
11344 case Intrinsic::x86_sse2_ucomigt_sd:
11345 case Intrinsic::x86_sse2_ucomige_sd:
11346 case Intrinsic::x86_sse2_ucomineq_sd: {
11350 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11351 case Intrinsic::x86_sse_comieq_ss:
11352 case Intrinsic::x86_sse2_comieq_sd:
11353 Opc = X86ISD::COMI;
11356 case Intrinsic::x86_sse_comilt_ss:
11357 case Intrinsic::x86_sse2_comilt_sd:
11358 Opc = X86ISD::COMI;
11361 case Intrinsic::x86_sse_comile_ss:
11362 case Intrinsic::x86_sse2_comile_sd:
11363 Opc = X86ISD::COMI;
11366 case Intrinsic::x86_sse_comigt_ss:
11367 case Intrinsic::x86_sse2_comigt_sd:
11368 Opc = X86ISD::COMI;
11371 case Intrinsic::x86_sse_comige_ss:
11372 case Intrinsic::x86_sse2_comige_sd:
11373 Opc = X86ISD::COMI;
11376 case Intrinsic::x86_sse_comineq_ss:
11377 case Intrinsic::x86_sse2_comineq_sd:
11378 Opc = X86ISD::COMI;
11381 case Intrinsic::x86_sse_ucomieq_ss:
11382 case Intrinsic::x86_sse2_ucomieq_sd:
11383 Opc = X86ISD::UCOMI;
11386 case Intrinsic::x86_sse_ucomilt_ss:
11387 case Intrinsic::x86_sse2_ucomilt_sd:
11388 Opc = X86ISD::UCOMI;
11391 case Intrinsic::x86_sse_ucomile_ss:
11392 case Intrinsic::x86_sse2_ucomile_sd:
11393 Opc = X86ISD::UCOMI;
11396 case Intrinsic::x86_sse_ucomigt_ss:
11397 case Intrinsic::x86_sse2_ucomigt_sd:
11398 Opc = X86ISD::UCOMI;
11401 case Intrinsic::x86_sse_ucomige_ss:
11402 case Intrinsic::x86_sse2_ucomige_sd:
11403 Opc = X86ISD::UCOMI;
11406 case Intrinsic::x86_sse_ucomineq_ss:
11407 case Intrinsic::x86_sse2_ucomineq_sd:
11408 Opc = X86ISD::UCOMI;
11413 SDValue LHS = Op.getOperand(1);
11414 SDValue RHS = Op.getOperand(2);
11415 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11416 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11417 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11418 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11419 DAG.getConstant(X86CC, MVT::i8), Cond);
11420 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11423 // Arithmetic intrinsics.
11424 case Intrinsic::x86_sse2_pmulu_dq:
11425 case Intrinsic::x86_avx2_pmulu_dq:
11426 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11427 Op.getOperand(1), Op.getOperand(2));
11429 // SSE2/AVX2 sub with unsigned saturation intrinsics
11430 case Intrinsic::x86_sse2_psubus_b:
11431 case Intrinsic::x86_sse2_psubus_w:
11432 case Intrinsic::x86_avx2_psubus_b:
11433 case Intrinsic::x86_avx2_psubus_w:
11434 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11435 Op.getOperand(1), Op.getOperand(2));
11437 // SSE3/AVX horizontal add/sub intrinsics
11438 case Intrinsic::x86_sse3_hadd_ps:
11439 case Intrinsic::x86_sse3_hadd_pd:
11440 case Intrinsic::x86_avx_hadd_ps_256:
11441 case Intrinsic::x86_avx_hadd_pd_256:
11442 case Intrinsic::x86_sse3_hsub_ps:
11443 case Intrinsic::x86_sse3_hsub_pd:
11444 case Intrinsic::x86_avx_hsub_ps_256:
11445 case Intrinsic::x86_avx_hsub_pd_256:
11446 case Intrinsic::x86_ssse3_phadd_w_128:
11447 case Intrinsic::x86_ssse3_phadd_d_128:
11448 case Intrinsic::x86_avx2_phadd_w:
11449 case Intrinsic::x86_avx2_phadd_d:
11450 case Intrinsic::x86_ssse3_phsub_w_128:
11451 case Intrinsic::x86_ssse3_phsub_d_128:
11452 case Intrinsic::x86_avx2_phsub_w:
11453 case Intrinsic::x86_avx2_phsub_d: {
11456 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11457 case Intrinsic::x86_sse3_hadd_ps:
11458 case Intrinsic::x86_sse3_hadd_pd:
11459 case Intrinsic::x86_avx_hadd_ps_256:
11460 case Intrinsic::x86_avx_hadd_pd_256:
11461 Opcode = X86ISD::FHADD;
11463 case Intrinsic::x86_sse3_hsub_ps:
11464 case Intrinsic::x86_sse3_hsub_pd:
11465 case Intrinsic::x86_avx_hsub_ps_256:
11466 case Intrinsic::x86_avx_hsub_pd_256:
11467 Opcode = X86ISD::FHSUB;
11469 case Intrinsic::x86_ssse3_phadd_w_128:
11470 case Intrinsic::x86_ssse3_phadd_d_128:
11471 case Intrinsic::x86_avx2_phadd_w:
11472 case Intrinsic::x86_avx2_phadd_d:
11473 Opcode = X86ISD::HADD;
11475 case Intrinsic::x86_ssse3_phsub_w_128:
11476 case Intrinsic::x86_ssse3_phsub_d_128:
11477 case Intrinsic::x86_avx2_phsub_w:
11478 case Intrinsic::x86_avx2_phsub_d:
11479 Opcode = X86ISD::HSUB;
11482 return DAG.getNode(Opcode, dl, Op.getValueType(),
11483 Op.getOperand(1), Op.getOperand(2));
11486 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11487 case Intrinsic::x86_sse2_pmaxu_b:
11488 case Intrinsic::x86_sse41_pmaxuw:
11489 case Intrinsic::x86_sse41_pmaxud:
11490 case Intrinsic::x86_avx2_pmaxu_b:
11491 case Intrinsic::x86_avx2_pmaxu_w:
11492 case Intrinsic::x86_avx2_pmaxu_d:
11493 case Intrinsic::x86_sse2_pminu_b:
11494 case Intrinsic::x86_sse41_pminuw:
11495 case Intrinsic::x86_sse41_pminud:
11496 case Intrinsic::x86_avx2_pminu_b:
11497 case Intrinsic::x86_avx2_pminu_w:
11498 case Intrinsic::x86_avx2_pminu_d:
11499 case Intrinsic::x86_sse41_pmaxsb:
11500 case Intrinsic::x86_sse2_pmaxs_w:
11501 case Intrinsic::x86_sse41_pmaxsd:
11502 case Intrinsic::x86_avx2_pmaxs_b:
11503 case Intrinsic::x86_avx2_pmaxs_w:
11504 case Intrinsic::x86_avx2_pmaxs_d:
11505 case Intrinsic::x86_sse41_pminsb:
11506 case Intrinsic::x86_sse2_pmins_w:
11507 case Intrinsic::x86_sse41_pminsd:
11508 case Intrinsic::x86_avx2_pmins_b:
11509 case Intrinsic::x86_avx2_pmins_w:
11510 case Intrinsic::x86_avx2_pmins_d: {
11513 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11514 case Intrinsic::x86_sse2_pmaxu_b:
11515 case Intrinsic::x86_sse41_pmaxuw:
11516 case Intrinsic::x86_sse41_pmaxud:
11517 case Intrinsic::x86_avx2_pmaxu_b:
11518 case Intrinsic::x86_avx2_pmaxu_w:
11519 case Intrinsic::x86_avx2_pmaxu_d:
11520 Opcode = X86ISD::UMAX;
11522 case Intrinsic::x86_sse2_pminu_b:
11523 case Intrinsic::x86_sse41_pminuw:
11524 case Intrinsic::x86_sse41_pminud:
11525 case Intrinsic::x86_avx2_pminu_b:
11526 case Intrinsic::x86_avx2_pminu_w:
11527 case Intrinsic::x86_avx2_pminu_d:
11528 Opcode = X86ISD::UMIN;
11530 case Intrinsic::x86_sse41_pmaxsb:
11531 case Intrinsic::x86_sse2_pmaxs_w:
11532 case Intrinsic::x86_sse41_pmaxsd:
11533 case Intrinsic::x86_avx2_pmaxs_b:
11534 case Intrinsic::x86_avx2_pmaxs_w:
11535 case Intrinsic::x86_avx2_pmaxs_d:
11536 Opcode = X86ISD::SMAX;
11538 case Intrinsic::x86_sse41_pminsb:
11539 case Intrinsic::x86_sse2_pmins_w:
11540 case Intrinsic::x86_sse41_pminsd:
11541 case Intrinsic::x86_avx2_pmins_b:
11542 case Intrinsic::x86_avx2_pmins_w:
11543 case Intrinsic::x86_avx2_pmins_d:
11544 Opcode = X86ISD::SMIN;
11547 return DAG.getNode(Opcode, dl, Op.getValueType(),
11548 Op.getOperand(1), Op.getOperand(2));
11551 // SSE/SSE2/AVX floating point max/min intrinsics.
11552 case Intrinsic::x86_sse_max_ps:
11553 case Intrinsic::x86_sse2_max_pd:
11554 case Intrinsic::x86_avx_max_ps_256:
11555 case Intrinsic::x86_avx_max_pd_256:
11556 case Intrinsic::x86_sse_min_ps:
11557 case Intrinsic::x86_sse2_min_pd:
11558 case Intrinsic::x86_avx_min_ps_256:
11559 case Intrinsic::x86_avx_min_pd_256: {
11562 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11563 case Intrinsic::x86_sse_max_ps:
11564 case Intrinsic::x86_sse2_max_pd:
11565 case Intrinsic::x86_avx_max_ps_256:
11566 case Intrinsic::x86_avx_max_pd_256:
11567 Opcode = X86ISD::FMAX;
11569 case Intrinsic::x86_sse_min_ps:
11570 case Intrinsic::x86_sse2_min_pd:
11571 case Intrinsic::x86_avx_min_ps_256:
11572 case Intrinsic::x86_avx_min_pd_256:
11573 Opcode = X86ISD::FMIN;
11576 return DAG.getNode(Opcode, dl, Op.getValueType(),
11577 Op.getOperand(1), Op.getOperand(2));
11580 // AVX2 variable shift intrinsics
11581 case Intrinsic::x86_avx2_psllv_d:
11582 case Intrinsic::x86_avx2_psllv_q:
11583 case Intrinsic::x86_avx2_psllv_d_256:
11584 case Intrinsic::x86_avx2_psllv_q_256:
11585 case Intrinsic::x86_avx2_psrlv_d:
11586 case Intrinsic::x86_avx2_psrlv_q:
11587 case Intrinsic::x86_avx2_psrlv_d_256:
11588 case Intrinsic::x86_avx2_psrlv_q_256:
11589 case Intrinsic::x86_avx2_psrav_d:
11590 case Intrinsic::x86_avx2_psrav_d_256: {
11593 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11594 case Intrinsic::x86_avx2_psllv_d:
11595 case Intrinsic::x86_avx2_psllv_q:
11596 case Intrinsic::x86_avx2_psllv_d_256:
11597 case Intrinsic::x86_avx2_psllv_q_256:
11600 case Intrinsic::x86_avx2_psrlv_d:
11601 case Intrinsic::x86_avx2_psrlv_q:
11602 case Intrinsic::x86_avx2_psrlv_d_256:
11603 case Intrinsic::x86_avx2_psrlv_q_256:
11606 case Intrinsic::x86_avx2_psrav_d:
11607 case Intrinsic::x86_avx2_psrav_d_256:
11611 return DAG.getNode(Opcode, dl, Op.getValueType(),
11612 Op.getOperand(1), Op.getOperand(2));
11615 case Intrinsic::x86_ssse3_pshuf_b_128:
11616 case Intrinsic::x86_avx2_pshuf_b:
11617 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11618 Op.getOperand(1), Op.getOperand(2));
11620 case Intrinsic::x86_ssse3_psign_b_128:
11621 case Intrinsic::x86_ssse3_psign_w_128:
11622 case Intrinsic::x86_ssse3_psign_d_128:
11623 case Intrinsic::x86_avx2_psign_b:
11624 case Intrinsic::x86_avx2_psign_w:
11625 case Intrinsic::x86_avx2_psign_d:
11626 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11627 Op.getOperand(1), Op.getOperand(2));
11629 case Intrinsic::x86_sse41_insertps:
11630 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11631 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11633 case Intrinsic::x86_avx_vperm2f128_ps_256:
11634 case Intrinsic::x86_avx_vperm2f128_pd_256:
11635 case Intrinsic::x86_avx_vperm2f128_si_256:
11636 case Intrinsic::x86_avx2_vperm2i128:
11637 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11638 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11640 case Intrinsic::x86_avx2_permd:
11641 case Intrinsic::x86_avx2_permps:
11642 // Operands intentionally swapped. Mask is last operand to intrinsic,
11643 // but second operand for node/instruction.
11644 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11645 Op.getOperand(2), Op.getOperand(1));
11647 case Intrinsic::x86_sse_sqrt_ps:
11648 case Intrinsic::x86_sse2_sqrt_pd:
11649 case Intrinsic::x86_avx_sqrt_ps_256:
11650 case Intrinsic::x86_avx_sqrt_pd_256:
11651 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11653 // ptest and testp intrinsics. The intrinsic these come from are designed to
11654 // return an integer value, not just an instruction so lower it to the ptest
11655 // or testp pattern and a setcc for the result.
11656 case Intrinsic::x86_sse41_ptestz:
11657 case Intrinsic::x86_sse41_ptestc:
11658 case Intrinsic::x86_sse41_ptestnzc:
11659 case Intrinsic::x86_avx_ptestz_256:
11660 case Intrinsic::x86_avx_ptestc_256:
11661 case Intrinsic::x86_avx_ptestnzc_256:
11662 case Intrinsic::x86_avx_vtestz_ps:
11663 case Intrinsic::x86_avx_vtestc_ps:
11664 case Intrinsic::x86_avx_vtestnzc_ps:
11665 case Intrinsic::x86_avx_vtestz_pd:
11666 case Intrinsic::x86_avx_vtestc_pd:
11667 case Intrinsic::x86_avx_vtestnzc_pd:
11668 case Intrinsic::x86_avx_vtestz_ps_256:
11669 case Intrinsic::x86_avx_vtestc_ps_256:
11670 case Intrinsic::x86_avx_vtestnzc_ps_256:
11671 case Intrinsic::x86_avx_vtestz_pd_256:
11672 case Intrinsic::x86_avx_vtestc_pd_256:
11673 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11674 bool IsTestPacked = false;
11677 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11678 case Intrinsic::x86_avx_vtestz_ps:
11679 case Intrinsic::x86_avx_vtestz_pd:
11680 case Intrinsic::x86_avx_vtestz_ps_256:
11681 case Intrinsic::x86_avx_vtestz_pd_256:
11682 IsTestPacked = true; // Fallthrough
11683 case Intrinsic::x86_sse41_ptestz:
11684 case Intrinsic::x86_avx_ptestz_256:
11686 X86CC = X86::COND_E;
11688 case Intrinsic::x86_avx_vtestc_ps:
11689 case Intrinsic::x86_avx_vtestc_pd:
11690 case Intrinsic::x86_avx_vtestc_ps_256:
11691 case Intrinsic::x86_avx_vtestc_pd_256:
11692 IsTestPacked = true; // Fallthrough
11693 case Intrinsic::x86_sse41_ptestc:
11694 case Intrinsic::x86_avx_ptestc_256:
11696 X86CC = X86::COND_B;
11698 case Intrinsic::x86_avx_vtestnzc_ps:
11699 case Intrinsic::x86_avx_vtestnzc_pd:
11700 case Intrinsic::x86_avx_vtestnzc_ps_256:
11701 case Intrinsic::x86_avx_vtestnzc_pd_256:
11702 IsTestPacked = true; // Fallthrough
11703 case Intrinsic::x86_sse41_ptestnzc:
11704 case Intrinsic::x86_avx_ptestnzc_256:
11706 X86CC = X86::COND_A;
11710 SDValue LHS = Op.getOperand(1);
11711 SDValue RHS = Op.getOperand(2);
11712 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11713 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11714 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11715 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11716 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11718 case Intrinsic::x86_avx512_kortestz_w:
11719 case Intrinsic::x86_avx512_kortestc_w: {
11720 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
11721 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11722 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11723 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11724 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11725 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
11726 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11729 // SSE/AVX shift intrinsics
11730 case Intrinsic::x86_sse2_psll_w:
11731 case Intrinsic::x86_sse2_psll_d:
11732 case Intrinsic::x86_sse2_psll_q:
11733 case Intrinsic::x86_avx2_psll_w:
11734 case Intrinsic::x86_avx2_psll_d:
11735 case Intrinsic::x86_avx2_psll_q:
11736 case Intrinsic::x86_sse2_psrl_w:
11737 case Intrinsic::x86_sse2_psrl_d:
11738 case Intrinsic::x86_sse2_psrl_q:
11739 case Intrinsic::x86_avx2_psrl_w:
11740 case Intrinsic::x86_avx2_psrl_d:
11741 case Intrinsic::x86_avx2_psrl_q:
11742 case Intrinsic::x86_sse2_psra_w:
11743 case Intrinsic::x86_sse2_psra_d:
11744 case Intrinsic::x86_avx2_psra_w:
11745 case Intrinsic::x86_avx2_psra_d: {
11748 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11749 case Intrinsic::x86_sse2_psll_w:
11750 case Intrinsic::x86_sse2_psll_d:
11751 case Intrinsic::x86_sse2_psll_q:
11752 case Intrinsic::x86_avx2_psll_w:
11753 case Intrinsic::x86_avx2_psll_d:
11754 case Intrinsic::x86_avx2_psll_q:
11755 Opcode = X86ISD::VSHL;
11757 case Intrinsic::x86_sse2_psrl_w:
11758 case Intrinsic::x86_sse2_psrl_d:
11759 case Intrinsic::x86_sse2_psrl_q:
11760 case Intrinsic::x86_avx2_psrl_w:
11761 case Intrinsic::x86_avx2_psrl_d:
11762 case Intrinsic::x86_avx2_psrl_q:
11763 Opcode = X86ISD::VSRL;
11765 case Intrinsic::x86_sse2_psra_w:
11766 case Intrinsic::x86_sse2_psra_d:
11767 case Intrinsic::x86_avx2_psra_w:
11768 case Intrinsic::x86_avx2_psra_d:
11769 Opcode = X86ISD::VSRA;
11772 return DAG.getNode(Opcode, dl, Op.getValueType(),
11773 Op.getOperand(1), Op.getOperand(2));
11776 // SSE/AVX immediate shift intrinsics
11777 case Intrinsic::x86_sse2_pslli_w:
11778 case Intrinsic::x86_sse2_pslli_d:
11779 case Intrinsic::x86_sse2_pslli_q:
11780 case Intrinsic::x86_avx2_pslli_w:
11781 case Intrinsic::x86_avx2_pslli_d:
11782 case Intrinsic::x86_avx2_pslli_q:
11783 case Intrinsic::x86_sse2_psrli_w:
11784 case Intrinsic::x86_sse2_psrli_d:
11785 case Intrinsic::x86_sse2_psrli_q:
11786 case Intrinsic::x86_avx2_psrli_w:
11787 case Intrinsic::x86_avx2_psrli_d:
11788 case Intrinsic::x86_avx2_psrli_q:
11789 case Intrinsic::x86_sse2_psrai_w:
11790 case Intrinsic::x86_sse2_psrai_d:
11791 case Intrinsic::x86_avx2_psrai_w:
11792 case Intrinsic::x86_avx2_psrai_d: {
11795 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11796 case Intrinsic::x86_sse2_pslli_w:
11797 case Intrinsic::x86_sse2_pslli_d:
11798 case Intrinsic::x86_sse2_pslli_q:
11799 case Intrinsic::x86_avx2_pslli_w:
11800 case Intrinsic::x86_avx2_pslli_d:
11801 case Intrinsic::x86_avx2_pslli_q:
11802 Opcode = X86ISD::VSHLI;
11804 case Intrinsic::x86_sse2_psrli_w:
11805 case Intrinsic::x86_sse2_psrli_d:
11806 case Intrinsic::x86_sse2_psrli_q:
11807 case Intrinsic::x86_avx2_psrli_w:
11808 case Intrinsic::x86_avx2_psrli_d:
11809 case Intrinsic::x86_avx2_psrli_q:
11810 Opcode = X86ISD::VSRLI;
11812 case Intrinsic::x86_sse2_psrai_w:
11813 case Intrinsic::x86_sse2_psrai_d:
11814 case Intrinsic::x86_avx2_psrai_w:
11815 case Intrinsic::x86_avx2_psrai_d:
11816 Opcode = X86ISD::VSRAI;
11819 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
11820 Op.getOperand(1), Op.getOperand(2), DAG);
11823 case Intrinsic::x86_sse42_pcmpistria128:
11824 case Intrinsic::x86_sse42_pcmpestria128:
11825 case Intrinsic::x86_sse42_pcmpistric128:
11826 case Intrinsic::x86_sse42_pcmpestric128:
11827 case Intrinsic::x86_sse42_pcmpistrio128:
11828 case Intrinsic::x86_sse42_pcmpestrio128:
11829 case Intrinsic::x86_sse42_pcmpistris128:
11830 case Intrinsic::x86_sse42_pcmpestris128:
11831 case Intrinsic::x86_sse42_pcmpistriz128:
11832 case Intrinsic::x86_sse42_pcmpestriz128: {
11836 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11837 case Intrinsic::x86_sse42_pcmpistria128:
11838 Opcode = X86ISD::PCMPISTRI;
11839 X86CC = X86::COND_A;
11841 case Intrinsic::x86_sse42_pcmpestria128:
11842 Opcode = X86ISD::PCMPESTRI;
11843 X86CC = X86::COND_A;
11845 case Intrinsic::x86_sse42_pcmpistric128:
11846 Opcode = X86ISD::PCMPISTRI;
11847 X86CC = X86::COND_B;
11849 case Intrinsic::x86_sse42_pcmpestric128:
11850 Opcode = X86ISD::PCMPESTRI;
11851 X86CC = X86::COND_B;
11853 case Intrinsic::x86_sse42_pcmpistrio128:
11854 Opcode = X86ISD::PCMPISTRI;
11855 X86CC = X86::COND_O;
11857 case Intrinsic::x86_sse42_pcmpestrio128:
11858 Opcode = X86ISD::PCMPESTRI;
11859 X86CC = X86::COND_O;
11861 case Intrinsic::x86_sse42_pcmpistris128:
11862 Opcode = X86ISD::PCMPISTRI;
11863 X86CC = X86::COND_S;
11865 case Intrinsic::x86_sse42_pcmpestris128:
11866 Opcode = X86ISD::PCMPESTRI;
11867 X86CC = X86::COND_S;
11869 case Intrinsic::x86_sse42_pcmpistriz128:
11870 Opcode = X86ISD::PCMPISTRI;
11871 X86CC = X86::COND_E;
11873 case Intrinsic::x86_sse42_pcmpestriz128:
11874 Opcode = X86ISD::PCMPESTRI;
11875 X86CC = X86::COND_E;
11878 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11879 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11880 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11881 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11882 DAG.getConstant(X86CC, MVT::i8),
11883 SDValue(PCMP.getNode(), 1));
11884 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11887 case Intrinsic::x86_sse42_pcmpistri128:
11888 case Intrinsic::x86_sse42_pcmpestri128: {
11890 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11891 Opcode = X86ISD::PCMPISTRI;
11893 Opcode = X86ISD::PCMPESTRI;
11895 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11896 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11897 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11899 case Intrinsic::x86_fma_vfmadd_ps:
11900 case Intrinsic::x86_fma_vfmadd_pd:
11901 case Intrinsic::x86_fma_vfmsub_ps:
11902 case Intrinsic::x86_fma_vfmsub_pd:
11903 case Intrinsic::x86_fma_vfnmadd_ps:
11904 case Intrinsic::x86_fma_vfnmadd_pd:
11905 case Intrinsic::x86_fma_vfnmsub_ps:
11906 case Intrinsic::x86_fma_vfnmsub_pd:
11907 case Intrinsic::x86_fma_vfmaddsub_ps:
11908 case Intrinsic::x86_fma_vfmaddsub_pd:
11909 case Intrinsic::x86_fma_vfmsubadd_ps:
11910 case Intrinsic::x86_fma_vfmsubadd_pd:
11911 case Intrinsic::x86_fma_vfmadd_ps_256:
11912 case Intrinsic::x86_fma_vfmadd_pd_256:
11913 case Intrinsic::x86_fma_vfmsub_ps_256:
11914 case Intrinsic::x86_fma_vfmsub_pd_256:
11915 case Intrinsic::x86_fma_vfnmadd_ps_256:
11916 case Intrinsic::x86_fma_vfnmadd_pd_256:
11917 case Intrinsic::x86_fma_vfnmsub_ps_256:
11918 case Intrinsic::x86_fma_vfnmsub_pd_256:
11919 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11920 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11921 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11922 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11923 case Intrinsic::x86_fma_vfmadd_ps_512:
11924 case Intrinsic::x86_fma_vfmadd_pd_512:
11925 case Intrinsic::x86_fma_vfmsub_ps_512:
11926 case Intrinsic::x86_fma_vfmsub_pd_512:
11927 case Intrinsic::x86_fma_vfnmadd_ps_512:
11928 case Intrinsic::x86_fma_vfnmadd_pd_512:
11929 case Intrinsic::x86_fma_vfnmsub_ps_512:
11930 case Intrinsic::x86_fma_vfnmsub_pd_512:
11931 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11932 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11933 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11934 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
11937 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11938 case Intrinsic::x86_fma_vfmadd_ps:
11939 case Intrinsic::x86_fma_vfmadd_pd:
11940 case Intrinsic::x86_fma_vfmadd_ps_256:
11941 case Intrinsic::x86_fma_vfmadd_pd_256:
11942 case Intrinsic::x86_fma_vfmadd_ps_512:
11943 case Intrinsic::x86_fma_vfmadd_pd_512:
11944 Opc = X86ISD::FMADD;
11946 case Intrinsic::x86_fma_vfmsub_ps:
11947 case Intrinsic::x86_fma_vfmsub_pd:
11948 case Intrinsic::x86_fma_vfmsub_ps_256:
11949 case Intrinsic::x86_fma_vfmsub_pd_256:
11950 case Intrinsic::x86_fma_vfmsub_ps_512:
11951 case Intrinsic::x86_fma_vfmsub_pd_512:
11952 Opc = X86ISD::FMSUB;
11954 case Intrinsic::x86_fma_vfnmadd_ps:
11955 case Intrinsic::x86_fma_vfnmadd_pd:
11956 case Intrinsic::x86_fma_vfnmadd_ps_256:
11957 case Intrinsic::x86_fma_vfnmadd_pd_256:
11958 case Intrinsic::x86_fma_vfnmadd_ps_512:
11959 case Intrinsic::x86_fma_vfnmadd_pd_512:
11960 Opc = X86ISD::FNMADD;
11962 case Intrinsic::x86_fma_vfnmsub_ps:
11963 case Intrinsic::x86_fma_vfnmsub_pd:
11964 case Intrinsic::x86_fma_vfnmsub_ps_256:
11965 case Intrinsic::x86_fma_vfnmsub_pd_256:
11966 case Intrinsic::x86_fma_vfnmsub_ps_512:
11967 case Intrinsic::x86_fma_vfnmsub_pd_512:
11968 Opc = X86ISD::FNMSUB;
11970 case Intrinsic::x86_fma_vfmaddsub_ps:
11971 case Intrinsic::x86_fma_vfmaddsub_pd:
11972 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11973 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11974 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11975 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11976 Opc = X86ISD::FMADDSUB;
11978 case Intrinsic::x86_fma_vfmsubadd_ps:
11979 case Intrinsic::x86_fma_vfmsubadd_pd:
11980 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11981 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11982 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11983 case Intrinsic::x86_fma_vfmsubadd_pd_512:
11984 Opc = X86ISD::FMSUBADD;
11988 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11989 Op.getOperand(2), Op.getOperand(3));
11994 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11995 SDValue Base, SDValue Index,
11996 SDValue ScaleOp, SDValue Chain,
11997 const X86Subtarget * Subtarget) {
11999 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12000 assert(C && "Invalid scale type");
12001 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12002 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
12003 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12004 Index.getSimpleValueType().getVectorNumElements());
12005 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
12006 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
12007 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12008 SDValue Segment = DAG.getRegister(0, MVT::i32);
12009 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
12010 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12011 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
12012 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
12015 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12016 SDValue Src, SDValue Mask, SDValue Base,
12017 SDValue Index, SDValue ScaleOp, SDValue Chain,
12018 const X86Subtarget * Subtarget) {
12020 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12021 assert(C && "Invalid scale type");
12022 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12023 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12024 Index.getSimpleValueType().getVectorNumElements());
12025 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12026 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
12027 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12028 SDValue Segment = DAG.getRegister(0, MVT::i32);
12029 if (Src.getOpcode() == ISD::UNDEF)
12030 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
12031 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
12032 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12033 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
12034 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
12037 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12038 SDValue Src, SDValue Base, SDValue Index,
12039 SDValue ScaleOp, SDValue Chain) {
12041 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12042 assert(C && "Invalid scale type");
12043 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12044 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12045 SDValue Segment = DAG.getRegister(0, MVT::i32);
12046 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12047 Index.getSimpleValueType().getVectorNumElements());
12048 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
12049 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
12050 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
12051 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12052 return SDValue(Res, 1);
12055 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
12056 SDValue Src, SDValue Mask, SDValue Base,
12057 SDValue Index, SDValue ScaleOp, SDValue Chain) {
12059 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
12060 assert(C && "Invalid scale type");
12061 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12062 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12063 SDValue Segment = DAG.getRegister(0, MVT::i32);
12064 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12065 Index.getSimpleValueType().getVectorNumElements());
12066 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12067 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
12068 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
12069 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12070 return SDValue(Res, 1);
12073 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
12074 SelectionDAG &DAG) {
12076 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12078 default: return SDValue(); // Don't custom lower most intrinsics.
12080 // RDRAND/RDSEED intrinsics.
12081 case Intrinsic::x86_rdrand_16:
12082 case Intrinsic::x86_rdrand_32:
12083 case Intrinsic::x86_rdrand_64:
12084 case Intrinsic::x86_rdseed_16:
12085 case Intrinsic::x86_rdseed_32:
12086 case Intrinsic::x86_rdseed_64: {
12087 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
12088 IntNo == Intrinsic::x86_rdseed_32 ||
12089 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
12091 // Emit the node with the right value type.
12092 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
12093 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
12095 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
12096 // Otherwise return the value from Rand, which is always 0, casted to i32.
12097 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
12098 DAG.getConstant(1, Op->getValueType(1)),
12099 DAG.getConstant(X86::COND_B, MVT::i32),
12100 SDValue(Result.getNode(), 1) };
12101 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
12102 DAG.getVTList(Op->getValueType(1), MVT::Glue),
12103 Ops, array_lengthof(Ops));
12105 // Return { result, isValid, chain }.
12106 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
12107 SDValue(Result.getNode(), 2));
12109 //int_gather(index, base, scale);
12110 case Intrinsic::x86_avx512_gather_qpd_512:
12111 case Intrinsic::x86_avx512_gather_qps_512:
12112 case Intrinsic::x86_avx512_gather_dpd_512:
12113 case Intrinsic::x86_avx512_gather_qpi_512:
12114 case Intrinsic::x86_avx512_gather_qpq_512:
12115 case Intrinsic::x86_avx512_gather_dpq_512:
12116 case Intrinsic::x86_avx512_gather_dps_512:
12117 case Intrinsic::x86_avx512_gather_dpi_512: {
12120 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12121 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
12122 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
12123 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
12124 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
12125 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
12126 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
12127 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
12128 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
12130 SDValue Chain = Op.getOperand(0);
12131 SDValue Index = Op.getOperand(2);
12132 SDValue Base = Op.getOperand(3);
12133 SDValue Scale = Op.getOperand(4);
12134 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
12136 //int_gather_mask(v1, mask, index, base, scale);
12137 case Intrinsic::x86_avx512_gather_qps_mask_512:
12138 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12139 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12140 case Intrinsic::x86_avx512_gather_dps_mask_512:
12141 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12142 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12143 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12144 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
12147 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12148 case Intrinsic::x86_avx512_gather_qps_mask_512:
12149 Opc = X86::VGATHERQPSZrm; break;
12150 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12151 Opc = X86::VGATHERQPDZrm; break;
12152 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12153 Opc = X86::VGATHERDPDZrm; break;
12154 case Intrinsic::x86_avx512_gather_dps_mask_512:
12155 Opc = X86::VGATHERDPSZrm; break;
12156 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12157 Opc = X86::VPGATHERQDZrm; break;
12158 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12159 Opc = X86::VPGATHERQQZrm; break;
12160 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12161 Opc = X86::VPGATHERDDZrm; break;
12162 case Intrinsic::x86_avx512_gather_dpq_mask_512:
12163 Opc = X86::VPGATHERDQZrm; break;
12165 SDValue Chain = Op.getOperand(0);
12166 SDValue Src = Op.getOperand(2);
12167 SDValue Mask = Op.getOperand(3);
12168 SDValue Index = Op.getOperand(4);
12169 SDValue Base = Op.getOperand(5);
12170 SDValue Scale = Op.getOperand(6);
12171 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
12174 //int_scatter(base, index, v1, scale);
12175 case Intrinsic::x86_avx512_scatter_qpd_512:
12176 case Intrinsic::x86_avx512_scatter_qps_512:
12177 case Intrinsic::x86_avx512_scatter_dpd_512:
12178 case Intrinsic::x86_avx512_scatter_qpi_512:
12179 case Intrinsic::x86_avx512_scatter_qpq_512:
12180 case Intrinsic::x86_avx512_scatter_dpq_512:
12181 case Intrinsic::x86_avx512_scatter_dps_512:
12182 case Intrinsic::x86_avx512_scatter_dpi_512: {
12185 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12186 case Intrinsic::x86_avx512_scatter_qpd_512:
12187 Opc = X86::VSCATTERQPDZmr; break;
12188 case Intrinsic::x86_avx512_scatter_qps_512:
12189 Opc = X86::VSCATTERQPSZmr; break;
12190 case Intrinsic::x86_avx512_scatter_dpd_512:
12191 Opc = X86::VSCATTERDPDZmr; break;
12192 case Intrinsic::x86_avx512_scatter_dps_512:
12193 Opc = X86::VSCATTERDPSZmr; break;
12194 case Intrinsic::x86_avx512_scatter_qpi_512:
12195 Opc = X86::VPSCATTERQDZmr; break;
12196 case Intrinsic::x86_avx512_scatter_qpq_512:
12197 Opc = X86::VPSCATTERQQZmr; break;
12198 case Intrinsic::x86_avx512_scatter_dpq_512:
12199 Opc = X86::VPSCATTERDQZmr; break;
12200 case Intrinsic::x86_avx512_scatter_dpi_512:
12201 Opc = X86::VPSCATTERDDZmr; break;
12203 SDValue Chain = Op.getOperand(0);
12204 SDValue Base = Op.getOperand(2);
12205 SDValue Index = Op.getOperand(3);
12206 SDValue Src = Op.getOperand(4);
12207 SDValue Scale = Op.getOperand(5);
12208 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
12210 //int_scatter_mask(base, mask, index, v1, scale);
12211 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12212 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12213 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12214 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12215 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12216 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12217 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12218 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
12221 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12222 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12223 Opc = X86::VSCATTERQPDZmr; break;
12224 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12225 Opc = X86::VSCATTERQPSZmr; break;
12226 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12227 Opc = X86::VSCATTERDPDZmr; break;
12228 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12229 Opc = X86::VSCATTERDPSZmr; break;
12230 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12231 Opc = X86::VPSCATTERQDZmr; break;
12232 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12233 Opc = X86::VPSCATTERQQZmr; break;
12234 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
12235 Opc = X86::VPSCATTERDQZmr; break;
12236 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12237 Opc = X86::VPSCATTERDDZmr; break;
12239 SDValue Chain = Op.getOperand(0);
12240 SDValue Base = Op.getOperand(2);
12241 SDValue Mask = Op.getOperand(3);
12242 SDValue Index = Op.getOperand(4);
12243 SDValue Src = Op.getOperand(5);
12244 SDValue Scale = Op.getOperand(6);
12245 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
12247 // XTEST intrinsics.
12248 case Intrinsic::x86_xtest: {
12249 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
12250 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
12251 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12252 DAG.getConstant(X86::COND_NE, MVT::i8),
12254 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12255 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
12256 Ret, SDValue(InTrans.getNode(), 1));
12261 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
12262 SelectionDAG &DAG) const {
12263 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12264 MFI->setReturnAddressIsTaken(true);
12266 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
12269 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12271 EVT PtrVT = getPointerTy();
12274 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12275 const X86RegisterInfo *RegInfo =
12276 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12277 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12278 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12279 DAG.getNode(ISD::ADD, dl, PtrVT,
12280 FrameAddr, Offset),
12281 MachinePointerInfo(), false, false, false, 0);
12284 // Just load the return address.
12285 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12286 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12287 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12290 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12291 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12292 MFI->setFrameAddressIsTaken(true);
12294 EVT VT = Op.getValueType();
12295 SDLoc dl(Op); // FIXME probably not meaningful
12296 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12297 const X86RegisterInfo *RegInfo =
12298 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12299 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12300 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12301 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12302 "Invalid Frame Register!");
12303 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12305 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12306 MachinePointerInfo(),
12307 false, false, false, 0);
12311 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12312 SelectionDAG &DAG) const {
12313 const X86RegisterInfo *RegInfo =
12314 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12315 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12318 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12319 SDValue Chain = Op.getOperand(0);
12320 SDValue Offset = Op.getOperand(1);
12321 SDValue Handler = Op.getOperand(2);
12324 EVT PtrVT = getPointerTy();
12325 const X86RegisterInfo *RegInfo =
12326 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12327 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12328 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12329 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12330 "Invalid Frame Register!");
12331 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12332 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12334 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12335 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12336 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12337 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12339 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12341 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12342 DAG.getRegister(StoreAddrReg, PtrVT));
12345 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12346 SelectionDAG &DAG) const {
12348 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12349 DAG.getVTList(MVT::i32, MVT::Other),
12350 Op.getOperand(0), Op.getOperand(1));
12353 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12354 SelectionDAG &DAG) const {
12356 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12357 Op.getOperand(0), Op.getOperand(1));
12360 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12361 return Op.getOperand(0);
12364 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12365 SelectionDAG &DAG) const {
12366 SDValue Root = Op.getOperand(0);
12367 SDValue Trmp = Op.getOperand(1); // trampoline
12368 SDValue FPtr = Op.getOperand(2); // nested function
12369 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12372 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12373 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12375 if (Subtarget->is64Bit()) {
12376 SDValue OutChains[6];
12378 // Large code-model.
12379 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12380 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12382 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12383 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12385 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12387 // Load the pointer to the nested function into R11.
12388 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12389 SDValue Addr = Trmp;
12390 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12391 Addr, MachinePointerInfo(TrmpAddr),
12394 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12395 DAG.getConstant(2, MVT::i64));
12396 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12397 MachinePointerInfo(TrmpAddr, 2),
12400 // Load the 'nest' parameter value into R10.
12401 // R10 is specified in X86CallingConv.td
12402 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12403 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12404 DAG.getConstant(10, MVT::i64));
12405 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12406 Addr, MachinePointerInfo(TrmpAddr, 10),
12409 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12410 DAG.getConstant(12, MVT::i64));
12411 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12412 MachinePointerInfo(TrmpAddr, 12),
12415 // Jump to the nested function.
12416 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12417 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12418 DAG.getConstant(20, MVT::i64));
12419 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12420 Addr, MachinePointerInfo(TrmpAddr, 20),
12423 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12424 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12425 DAG.getConstant(22, MVT::i64));
12426 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12427 MachinePointerInfo(TrmpAddr, 22),
12430 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12432 const Function *Func =
12433 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12434 CallingConv::ID CC = Func->getCallingConv();
12439 llvm_unreachable("Unsupported calling convention");
12440 case CallingConv::C:
12441 case CallingConv::X86_StdCall: {
12442 // Pass 'nest' parameter in ECX.
12443 // Must be kept in sync with X86CallingConv.td
12444 NestReg = X86::ECX;
12446 // Check that ECX wasn't needed by an 'inreg' parameter.
12447 FunctionType *FTy = Func->getFunctionType();
12448 const AttributeSet &Attrs = Func->getAttributes();
12450 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12451 unsigned InRegCount = 0;
12454 for (FunctionType::param_iterator I = FTy->param_begin(),
12455 E = FTy->param_end(); I != E; ++I, ++Idx)
12456 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12457 // FIXME: should only count parameters that are lowered to integers.
12458 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12460 if (InRegCount > 2) {
12461 report_fatal_error("Nest register in use - reduce number of inreg"
12467 case CallingConv::X86_FastCall:
12468 case CallingConv::X86_ThisCall:
12469 case CallingConv::Fast:
12470 // Pass 'nest' parameter in EAX.
12471 // Must be kept in sync with X86CallingConv.td
12472 NestReg = X86::EAX;
12476 SDValue OutChains[4];
12477 SDValue Addr, Disp;
12479 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12480 DAG.getConstant(10, MVT::i32));
12481 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12483 // This is storing the opcode for MOV32ri.
12484 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12485 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12486 OutChains[0] = DAG.getStore(Root, dl,
12487 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12488 Trmp, MachinePointerInfo(TrmpAddr),
12491 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12492 DAG.getConstant(1, MVT::i32));
12493 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12494 MachinePointerInfo(TrmpAddr, 1),
12497 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12498 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12499 DAG.getConstant(5, MVT::i32));
12500 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12501 MachinePointerInfo(TrmpAddr, 5),
12504 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12505 DAG.getConstant(6, MVT::i32));
12506 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12507 MachinePointerInfo(TrmpAddr, 6),
12510 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12514 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12515 SelectionDAG &DAG) const {
12517 The rounding mode is in bits 11:10 of FPSR, and has the following
12519 00 Round to nearest
12524 FLT_ROUNDS, on the other hand, expects the following:
12531 To perform the conversion, we do:
12532 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12535 MachineFunction &MF = DAG.getMachineFunction();
12536 const TargetMachine &TM = MF.getTarget();
12537 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12538 unsigned StackAlignment = TFI.getStackAlignment();
12539 MVT VT = Op.getSimpleValueType();
12542 // Save FP Control Word to stack slot
12543 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12544 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12546 MachineMemOperand *MMO =
12547 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12548 MachineMemOperand::MOStore, 2, 2);
12550 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12551 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12552 DAG.getVTList(MVT::Other),
12553 Ops, array_lengthof(Ops), MVT::i16,
12556 // Load FP Control Word from stack slot
12557 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12558 MachinePointerInfo(), false, false, false, 0);
12560 // Transform as necessary
12562 DAG.getNode(ISD::SRL, DL, MVT::i16,
12563 DAG.getNode(ISD::AND, DL, MVT::i16,
12564 CWD, DAG.getConstant(0x800, MVT::i16)),
12565 DAG.getConstant(11, MVT::i8));
12567 DAG.getNode(ISD::SRL, DL, MVT::i16,
12568 DAG.getNode(ISD::AND, DL, MVT::i16,
12569 CWD, DAG.getConstant(0x400, MVT::i16)),
12570 DAG.getConstant(9, MVT::i8));
12573 DAG.getNode(ISD::AND, DL, MVT::i16,
12574 DAG.getNode(ISD::ADD, DL, MVT::i16,
12575 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12576 DAG.getConstant(1, MVT::i16)),
12577 DAG.getConstant(3, MVT::i16));
12579 return DAG.getNode((VT.getSizeInBits() < 16 ?
12580 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12583 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12584 MVT VT = Op.getSimpleValueType();
12586 unsigned NumBits = VT.getSizeInBits();
12589 Op = Op.getOperand(0);
12590 if (VT == MVT::i8) {
12591 // Zero extend to i32 since there is not an i8 bsr.
12593 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12596 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12597 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12598 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12600 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12603 DAG.getConstant(NumBits+NumBits-1, OpVT),
12604 DAG.getConstant(X86::COND_E, MVT::i8),
12607 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12609 // Finally xor with NumBits-1.
12610 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12613 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12617 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12618 MVT VT = Op.getSimpleValueType();
12620 unsigned NumBits = VT.getSizeInBits();
12623 Op = Op.getOperand(0);
12624 if (VT == MVT::i8) {
12625 // Zero extend to i32 since there is not an i8 bsr.
12627 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12630 // Issue a bsr (scan bits in reverse).
12631 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12632 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12634 // And xor with NumBits-1.
12635 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12638 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12642 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12643 MVT VT = Op.getSimpleValueType();
12644 unsigned NumBits = VT.getSizeInBits();
12646 Op = Op.getOperand(0);
12648 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12649 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12650 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12652 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12655 DAG.getConstant(NumBits, VT),
12656 DAG.getConstant(X86::COND_E, MVT::i8),
12659 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12662 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12663 // ones, and then concatenate the result back.
12664 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12665 MVT VT = Op.getSimpleValueType();
12667 assert(VT.is256BitVector() && VT.isInteger() &&
12668 "Unsupported value type for operation");
12670 unsigned NumElems = VT.getVectorNumElements();
12673 // Extract the LHS vectors
12674 SDValue LHS = Op.getOperand(0);
12675 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12676 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12678 // Extract the RHS vectors
12679 SDValue RHS = Op.getOperand(1);
12680 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12681 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12683 MVT EltVT = VT.getVectorElementType();
12684 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12686 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12687 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12688 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12691 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12692 assert(Op.getSimpleValueType().is256BitVector() &&
12693 Op.getSimpleValueType().isInteger() &&
12694 "Only handle AVX 256-bit vector integer operation");
12695 return Lower256IntArith(Op, DAG);
12698 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12699 assert(Op.getSimpleValueType().is256BitVector() &&
12700 Op.getSimpleValueType().isInteger() &&
12701 "Only handle AVX 256-bit vector integer operation");
12702 return Lower256IntArith(Op, DAG);
12705 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12706 SelectionDAG &DAG) {
12708 MVT VT = Op.getSimpleValueType();
12710 // Decompose 256-bit ops into smaller 128-bit ops.
12711 if (VT.is256BitVector() && !Subtarget->hasInt256())
12712 return Lower256IntArith(Op, DAG);
12714 SDValue A = Op.getOperand(0);
12715 SDValue B = Op.getOperand(1);
12717 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12718 if (VT == MVT::v4i32) {
12719 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12720 "Should not custom lower when pmuldq is available!");
12722 // Extract the odd parts.
12723 static const int UnpackMask[] = { 1, -1, 3, -1 };
12724 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12725 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12727 // Multiply the even parts.
12728 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12729 // Now multiply odd parts.
12730 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12732 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12733 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12735 // Merge the two vectors back together with a shuffle. This expands into 2
12737 static const int ShufMask[] = { 0, 4, 2, 6 };
12738 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12741 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12742 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12744 // Ahi = psrlqi(a, 32);
12745 // Bhi = psrlqi(b, 32);
12747 // AloBlo = pmuludq(a, b);
12748 // AloBhi = pmuludq(a, Bhi);
12749 // AhiBlo = pmuludq(Ahi, b);
12751 // AloBhi = psllqi(AloBhi, 32);
12752 // AhiBlo = psllqi(AhiBlo, 32);
12753 // return AloBlo + AloBhi + AhiBlo;
12755 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12756 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12758 // Bit cast to 32-bit vectors for MULUDQ
12759 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12760 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12761 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12762 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12763 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12764 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12766 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12767 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12768 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12770 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12771 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12773 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12774 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12777 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12778 MVT VT = Op.getSimpleValueType();
12779 MVT EltTy = VT.getVectorElementType();
12780 unsigned NumElts = VT.getVectorNumElements();
12781 SDValue N0 = Op.getOperand(0);
12784 // Lower sdiv X, pow2-const.
12785 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12789 APInt SplatValue, SplatUndef;
12790 unsigned SplatBitSize;
12792 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12794 EltTy.getSizeInBits() < SplatBitSize)
12797 if ((SplatValue != 0) &&
12798 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12799 unsigned Lg2 = SplatValue.countTrailingZeros();
12800 // Splat the sign bit.
12801 SmallVector<SDValue, 16> Sz(NumElts,
12802 DAG.getConstant(EltTy.getSizeInBits() - 1,
12804 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12805 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12807 // Add (N0 < 0) ? abs2 - 1 : 0;
12808 SmallVector<SDValue, 16> Amt(NumElts,
12809 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12811 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12812 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12814 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12815 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12816 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12817 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12820 // If we're dividing by a positive value, we're done. Otherwise, we must
12821 // negate the result.
12822 if (SplatValue.isNonNegative())
12825 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12826 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12827 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12832 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12833 const X86Subtarget *Subtarget) {
12834 MVT VT = Op.getSimpleValueType();
12836 SDValue R = Op.getOperand(0);
12837 SDValue Amt = Op.getOperand(1);
12839 // Optimize shl/srl/sra with constant shift amount.
12840 if (isSplatVector(Amt.getNode())) {
12841 SDValue SclrAmt = Amt->getOperand(0);
12842 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12843 uint64_t ShiftAmt = C->getZExtValue();
12845 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12846 (Subtarget->hasInt256() &&
12847 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12848 (Subtarget->hasAVX512() &&
12849 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12850 if (Op.getOpcode() == ISD::SHL)
12851 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12853 if (Op.getOpcode() == ISD::SRL)
12854 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12856 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12857 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12861 if (VT == MVT::v16i8) {
12862 if (Op.getOpcode() == ISD::SHL) {
12863 // Make a large shift.
12864 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12865 MVT::v8i16, R, ShiftAmt,
12867 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12868 // Zero out the rightmost bits.
12869 SmallVector<SDValue, 16> V(16,
12870 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12872 return DAG.getNode(ISD::AND, dl, VT, SHL,
12873 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12875 if (Op.getOpcode() == ISD::SRL) {
12876 // Make a large shift.
12877 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12878 MVT::v8i16, R, ShiftAmt,
12880 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12881 // Zero out the leftmost bits.
12882 SmallVector<SDValue, 16> V(16,
12883 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12885 return DAG.getNode(ISD::AND, dl, VT, SRL,
12886 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12888 if (Op.getOpcode() == ISD::SRA) {
12889 if (ShiftAmt == 7) {
12890 // R s>> 7 === R s< 0
12891 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12892 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12895 // R s>> a === ((R u>> a) ^ m) - m
12896 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12897 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12899 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12900 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12901 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12904 llvm_unreachable("Unknown shift opcode.");
12907 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12908 if (Op.getOpcode() == ISD::SHL) {
12909 // Make a large shift.
12910 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12911 MVT::v16i16, R, ShiftAmt,
12913 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12914 // Zero out the rightmost bits.
12915 SmallVector<SDValue, 32> V(32,
12916 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12918 return DAG.getNode(ISD::AND, dl, VT, SHL,
12919 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12921 if (Op.getOpcode() == ISD::SRL) {
12922 // Make a large shift.
12923 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12924 MVT::v16i16, R, ShiftAmt,
12926 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12927 // Zero out the leftmost bits.
12928 SmallVector<SDValue, 32> V(32,
12929 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12931 return DAG.getNode(ISD::AND, dl, VT, SRL,
12932 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12934 if (Op.getOpcode() == ISD::SRA) {
12935 if (ShiftAmt == 7) {
12936 // R s>> 7 === R s< 0
12937 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12938 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12941 // R s>> a === ((R u>> a) ^ m) - m
12942 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12943 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12945 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12946 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12947 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12950 llvm_unreachable("Unknown shift opcode.");
12955 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12956 if (!Subtarget->is64Bit() &&
12957 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12958 Amt.getOpcode() == ISD::BITCAST &&
12959 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12960 Amt = Amt.getOperand(0);
12961 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
12962 VT.getVectorNumElements();
12963 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12964 uint64_t ShiftAmt = 0;
12965 for (unsigned i = 0; i != Ratio; ++i) {
12966 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12970 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12972 // Check remaining shift amounts.
12973 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12974 uint64_t ShAmt = 0;
12975 for (unsigned j = 0; j != Ratio; ++j) {
12976 ConstantSDNode *C =
12977 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12981 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12983 if (ShAmt != ShiftAmt)
12986 switch (Op.getOpcode()) {
12988 llvm_unreachable("Unknown shift opcode!");
12990 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12993 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12996 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
13004 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
13005 const X86Subtarget* Subtarget) {
13006 MVT VT = Op.getSimpleValueType();
13008 SDValue R = Op.getOperand(0);
13009 SDValue Amt = Op.getOperand(1);
13011 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
13012 VT == MVT::v4i32 || VT == MVT::v8i16 ||
13013 (Subtarget->hasInt256() &&
13014 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
13015 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
13016 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
13018 EVT EltVT = VT.getVectorElementType();
13020 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
13021 unsigned NumElts = VT.getVectorNumElements();
13023 for (i = 0; i != NumElts; ++i) {
13024 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
13028 for (j = i; j != NumElts; ++j) {
13029 SDValue Arg = Amt.getOperand(j);
13030 if (Arg.getOpcode() == ISD::UNDEF) continue;
13031 if (Arg != Amt.getOperand(i))
13034 if (i != NumElts && j == NumElts)
13035 BaseShAmt = Amt.getOperand(i);
13037 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
13038 Amt = Amt.getOperand(0);
13039 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
13040 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
13041 SDValue InVec = Amt.getOperand(0);
13042 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13043 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13045 for (; i != NumElts; ++i) {
13046 SDValue Arg = InVec.getOperand(i);
13047 if (Arg.getOpcode() == ISD::UNDEF) continue;
13051 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13052 if (ConstantSDNode *C =
13053 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13054 unsigned SplatIdx =
13055 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
13056 if (C->getZExtValue() == SplatIdx)
13057 BaseShAmt = InVec.getOperand(1);
13060 if (BaseShAmt.getNode() == 0)
13061 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
13062 DAG.getIntPtrConstant(0));
13066 if (BaseShAmt.getNode()) {
13067 if (EltVT.bitsGT(MVT::i32))
13068 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
13069 else if (EltVT.bitsLT(MVT::i32))
13070 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
13072 switch (Op.getOpcode()) {
13074 llvm_unreachable("Unknown shift opcode!");
13076 switch (VT.SimpleTy) {
13077 default: return SDValue();
13086 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
13089 switch (VT.SimpleTy) {
13090 default: return SDValue();
13097 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
13100 switch (VT.SimpleTy) {
13101 default: return SDValue();
13110 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
13116 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
13117 if (!Subtarget->is64Bit() &&
13118 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
13119 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
13120 Amt.getOpcode() == ISD::BITCAST &&
13121 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
13122 Amt = Amt.getOperand(0);
13123 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
13124 VT.getVectorNumElements();
13125 std::vector<SDValue> Vals(Ratio);
13126 for (unsigned i = 0; i != Ratio; ++i)
13127 Vals[i] = Amt.getOperand(i);
13128 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
13129 for (unsigned j = 0; j != Ratio; ++j)
13130 if (Vals[j] != Amt.getOperand(i + j))
13133 switch (Op.getOpcode()) {
13135 llvm_unreachable("Unknown shift opcode!");
13137 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
13139 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
13141 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
13148 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
13149 SelectionDAG &DAG) {
13151 MVT VT = Op.getSimpleValueType();
13153 SDValue R = Op.getOperand(0);
13154 SDValue Amt = Op.getOperand(1);
13157 if (!Subtarget->hasSSE2())
13160 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
13164 V = LowerScalarVariableShift(Op, DAG, Subtarget);
13168 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
13170 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
13171 if (Subtarget->hasInt256()) {
13172 if (Op.getOpcode() == ISD::SRL &&
13173 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13174 VT == MVT::v4i64 || VT == MVT::v8i32))
13176 if (Op.getOpcode() == ISD::SHL &&
13177 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13178 VT == MVT::v4i64 || VT == MVT::v8i32))
13180 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
13184 // If possible, lower this packed shift into a vector multiply instead of
13185 // expanding it into a sequence of scalar shifts.
13186 // Do this only if the vector shift count is a constant build_vector.
13187 if (Op.getOpcode() == ISD::SHL &&
13188 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
13189 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
13190 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
13191 SmallVector<SDValue, 8> Elts;
13192 EVT SVT = VT.getScalarType();
13193 unsigned SVTBits = SVT.getSizeInBits();
13194 const APInt &One = APInt(SVTBits, 1);
13195 unsigned NumElems = VT.getVectorNumElements();
13197 for (unsigned i=0; i !=NumElems; ++i) {
13198 SDValue Op = Amt->getOperand(i);
13199 if (Op->getOpcode() == ISD::UNDEF) {
13200 Elts.push_back(Op);
13204 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
13205 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
13206 uint64_t ShAmt = C.getZExtValue();
13207 if (ShAmt >= SVTBits) {
13208 Elts.push_back(DAG.getUNDEF(SVT));
13211 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
13213 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Elts[0], NumElems);
13214 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
13217 // Lower SHL with variable shift amount.
13218 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
13219 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
13221 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
13222 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
13223 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
13224 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
13227 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
13228 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
13231 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
13232 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
13234 // Turn 'a' into a mask suitable for VSELECT
13235 SDValue VSelM = DAG.getConstant(0x80, VT);
13236 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13237 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13239 SDValue CM1 = DAG.getConstant(0x0f, VT);
13240 SDValue CM2 = DAG.getConstant(0x3f, VT);
13242 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
13243 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
13244 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
13245 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13246 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13249 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13250 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13251 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13253 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
13254 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
13255 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
13256 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13257 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13260 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13261 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13262 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13264 // return VSELECT(r, r+r, a);
13265 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
13266 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
13270 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
13271 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
13272 // solution better.
13273 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
13274 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
13276 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
13277 R = DAG.getNode(ExtOpc, dl, NewVT, R);
13278 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
13279 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13280 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
13283 // Decompose 256-bit shifts into smaller 128-bit shifts.
13284 if (VT.is256BitVector()) {
13285 unsigned NumElems = VT.getVectorNumElements();
13286 MVT EltVT = VT.getVectorElementType();
13287 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13289 // Extract the two vectors
13290 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
13291 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
13293 // Recreate the shift amount vectors
13294 SDValue Amt1, Amt2;
13295 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
13296 // Constant shift amount
13297 SmallVector<SDValue, 4> Amt1Csts;
13298 SmallVector<SDValue, 4> Amt2Csts;
13299 for (unsigned i = 0; i != NumElems/2; ++i)
13300 Amt1Csts.push_back(Amt->getOperand(i));
13301 for (unsigned i = NumElems/2; i != NumElems; ++i)
13302 Amt2Csts.push_back(Amt->getOperand(i));
13304 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13305 &Amt1Csts[0], NumElems/2);
13306 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13307 &Amt2Csts[0], NumElems/2);
13309 // Variable shift amount
13310 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
13311 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
13314 // Issue new vector shifts for the smaller types
13315 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
13316 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
13318 // Concatenate the result back
13319 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
13325 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
13326 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
13327 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
13328 // looks for this combo and may remove the "setcc" instruction if the "setcc"
13329 // has only one use.
13330 SDNode *N = Op.getNode();
13331 SDValue LHS = N->getOperand(0);
13332 SDValue RHS = N->getOperand(1);
13333 unsigned BaseOp = 0;
13336 switch (Op.getOpcode()) {
13337 default: llvm_unreachable("Unknown ovf instruction!");
13339 // A subtract of one will be selected as a INC. Note that INC doesn't
13340 // set CF, so we can't do this for UADDO.
13341 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13343 BaseOp = X86ISD::INC;
13344 Cond = X86::COND_O;
13347 BaseOp = X86ISD::ADD;
13348 Cond = X86::COND_O;
13351 BaseOp = X86ISD::ADD;
13352 Cond = X86::COND_B;
13355 // A subtract of one will be selected as a DEC. Note that DEC doesn't
13356 // set CF, so we can't do this for USUBO.
13357 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13359 BaseOp = X86ISD::DEC;
13360 Cond = X86::COND_O;
13363 BaseOp = X86ISD::SUB;
13364 Cond = X86::COND_O;
13367 BaseOp = X86ISD::SUB;
13368 Cond = X86::COND_B;
13371 BaseOp = X86ISD::SMUL;
13372 Cond = X86::COND_O;
13374 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
13375 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
13377 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
13380 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13381 DAG.getConstant(X86::COND_O, MVT::i32),
13382 SDValue(Sum.getNode(), 2));
13384 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13388 // Also sets EFLAGS.
13389 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13390 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13393 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13394 DAG.getConstant(Cond, MVT::i32),
13395 SDValue(Sum.getNode(), 1));
13397 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13400 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13401 SelectionDAG &DAG) const {
13403 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13404 MVT VT = Op.getSimpleValueType();
13406 if (!Subtarget->hasSSE2() || !VT.isVector())
13409 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13410 ExtraVT.getScalarType().getSizeInBits();
13412 switch (VT.SimpleTy) {
13413 default: return SDValue();
13416 if (!Subtarget->hasFp256())
13418 if (!Subtarget->hasInt256()) {
13419 // needs to be split
13420 unsigned NumElems = VT.getVectorNumElements();
13422 // Extract the LHS vectors
13423 SDValue LHS = Op.getOperand(0);
13424 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13425 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13427 MVT EltVT = VT.getVectorElementType();
13428 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13430 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13431 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13432 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13434 SDValue Extra = DAG.getValueType(ExtraVT);
13436 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13437 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13439 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13444 SDValue Op0 = Op.getOperand(0);
13445 SDValue Op00 = Op0.getOperand(0);
13447 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13448 if (Op0.getOpcode() == ISD::BITCAST &&
13449 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
13450 // (sext (vzext x)) -> (vsext x)
13451 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13452 if (Tmp1.getNode()) {
13453 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13454 // This folding is only valid when the in-reg type is a vector of i8,
13456 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
13457 ExtraEltVT == MVT::i32) {
13458 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13459 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13460 "This optimization is invalid without a VZEXT.");
13461 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13467 // If the above didn't work, then just use Shift-Left + Shift-Right.
13468 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13470 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13476 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13477 SelectionDAG &DAG) {
13479 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13480 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13481 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13482 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13484 // The only fence that needs an instruction is a sequentially-consistent
13485 // cross-thread fence.
13486 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13487 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13488 // no-sse2). There isn't any reason to disable it if the target processor
13490 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13491 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13493 SDValue Chain = Op.getOperand(0);
13494 SDValue Zero = DAG.getConstant(0, MVT::i32);
13496 DAG.getRegister(X86::ESP, MVT::i32), // Base
13497 DAG.getTargetConstant(1, MVT::i8), // Scale
13498 DAG.getRegister(0, MVT::i32), // Index
13499 DAG.getTargetConstant(0, MVT::i32), // Disp
13500 DAG.getRegister(0, MVT::i32), // Segment.
13504 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13505 return SDValue(Res, 0);
13508 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13509 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13512 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13513 SelectionDAG &DAG) {
13514 MVT T = Op.getSimpleValueType();
13518 switch(T.SimpleTy) {
13519 default: llvm_unreachable("Invalid value type!");
13520 case MVT::i8: Reg = X86::AL; size = 1; break;
13521 case MVT::i16: Reg = X86::AX; size = 2; break;
13522 case MVT::i32: Reg = X86::EAX; size = 4; break;
13524 assert(Subtarget->is64Bit() && "Node not type legal!");
13525 Reg = X86::RAX; size = 8;
13528 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13529 Op.getOperand(2), SDValue());
13530 SDValue Ops[] = { cpIn.getValue(0),
13533 DAG.getTargetConstant(size, MVT::i8),
13534 cpIn.getValue(1) };
13535 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13536 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13537 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13538 Ops, array_lengthof(Ops), T, MMO);
13540 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13544 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13545 SelectionDAG &DAG) {
13546 assert(Subtarget->is64Bit() && "Result not type legalized?");
13547 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13548 SDValue TheChain = Op.getOperand(0);
13550 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13551 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13552 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13554 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13555 DAG.getConstant(32, MVT::i8));
13557 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13560 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13563 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13564 SelectionDAG &DAG) {
13565 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13566 MVT DstVT = Op.getSimpleValueType();
13567 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13568 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13569 assert((DstVT == MVT::i64 ||
13570 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13571 "Unexpected custom BITCAST");
13572 // i64 <=> MMX conversions are Legal.
13573 if (SrcVT==MVT::i64 && DstVT.isVector())
13575 if (DstVT==MVT::i64 && SrcVT.isVector())
13577 // MMX <=> MMX conversions are Legal.
13578 if (SrcVT.isVector() && DstVT.isVector())
13580 // All other conversions need to be expanded.
13584 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13585 SDNode *Node = Op.getNode();
13587 EVT T = Node->getValueType(0);
13588 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13589 DAG.getConstant(0, T), Node->getOperand(2));
13590 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13591 cast<AtomicSDNode>(Node)->getMemoryVT(),
13592 Node->getOperand(0),
13593 Node->getOperand(1), negOp,
13594 cast<AtomicSDNode>(Node)->getSrcValue(),
13595 cast<AtomicSDNode>(Node)->getAlignment(),
13596 cast<AtomicSDNode>(Node)->getOrdering(),
13597 cast<AtomicSDNode>(Node)->getSynchScope());
13600 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13601 SDNode *Node = Op.getNode();
13603 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13605 // Convert seq_cst store -> xchg
13606 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13607 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13608 // (The only way to get a 16-byte store is cmpxchg16b)
13609 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13610 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13611 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13612 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13613 cast<AtomicSDNode>(Node)->getMemoryVT(),
13614 Node->getOperand(0),
13615 Node->getOperand(1), Node->getOperand(2),
13616 cast<AtomicSDNode>(Node)->getMemOperand(),
13617 cast<AtomicSDNode>(Node)->getOrdering(),
13618 cast<AtomicSDNode>(Node)->getSynchScope());
13619 return Swap.getValue(1);
13621 // Other atomic stores have a simple pattern.
13625 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13626 EVT VT = Op.getNode()->getSimpleValueType(0);
13628 // Let legalize expand this if it isn't a legal type yet.
13629 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13632 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13635 bool ExtraOp = false;
13636 switch (Op.getOpcode()) {
13637 default: llvm_unreachable("Invalid code");
13638 case ISD::ADDC: Opc = X86ISD::ADD; break;
13639 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13640 case ISD::SUBC: Opc = X86ISD::SUB; break;
13641 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13645 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13647 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13648 Op.getOperand(1), Op.getOperand(2));
13651 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13652 SelectionDAG &DAG) {
13653 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13655 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13656 // which returns the values as { float, float } (in XMM0) or
13657 // { double, double } (which is returned in XMM0, XMM1).
13659 SDValue Arg = Op.getOperand(0);
13660 EVT ArgVT = Arg.getValueType();
13661 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13663 TargetLowering::ArgListTy Args;
13664 TargetLowering::ArgListEntry Entry;
13668 Entry.isSExt = false;
13669 Entry.isZExt = false;
13670 Args.push_back(Entry);
13672 bool isF64 = ArgVT == MVT::f64;
13673 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13674 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13675 // the results are returned via SRet in memory.
13676 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13677 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13678 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13680 Type *RetTy = isF64
13681 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13682 : (Type*)VectorType::get(ArgTy, 4);
13684 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13685 false, false, false, false, 0,
13686 CallingConv::C, /*isTaillCall=*/false,
13687 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13688 Callee, Args, DAG, dl);
13689 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13692 // Returned in xmm0 and xmm1.
13693 return CallResult.first;
13695 // Returned in bits 0:31 and 32:64 xmm0.
13696 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13697 CallResult.first, DAG.getIntPtrConstant(0));
13698 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13699 CallResult.first, DAG.getIntPtrConstant(1));
13700 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13701 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13704 /// LowerOperation - Provide custom lowering hooks for some operations.
13706 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13707 switch (Op.getOpcode()) {
13708 default: llvm_unreachable("Should not custom lower this!");
13709 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13710 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13711 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13712 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13713 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13714 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13715 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13716 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13717 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13718 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13719 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13720 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13721 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13722 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13723 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13724 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13725 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13726 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13727 case ISD::SHL_PARTS:
13728 case ISD::SRA_PARTS:
13729 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13730 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13731 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13732 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13733 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13734 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13735 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13736 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13737 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13738 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13739 case ISD::FABS: return LowerFABS(Op, DAG);
13740 case ISD::FNEG: return LowerFNEG(Op, DAG);
13741 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13742 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13743 case ISD::SETCC: return LowerSETCC(Op, DAG);
13744 case ISD::SELECT: return LowerSELECT(Op, DAG);
13745 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13746 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13747 case ISD::VASTART: return LowerVASTART(Op, DAG);
13748 case ISD::VAARG: return LowerVAARG(Op, DAG);
13749 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13750 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13751 case ISD::INTRINSIC_VOID:
13752 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13753 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13754 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13755 case ISD::FRAME_TO_ARGS_OFFSET:
13756 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13757 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13758 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13759 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13760 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13761 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13762 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13763 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13764 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13765 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13766 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13767 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13770 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13776 case ISD::UMULO: return LowerXALUO(Op, DAG);
13777 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13778 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13782 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13783 case ISD::ADD: return LowerADD(Op, DAG);
13784 case ISD::SUB: return LowerSUB(Op, DAG);
13785 case ISD::SDIV: return LowerSDIV(Op, DAG);
13786 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13790 static void ReplaceATOMIC_LOAD(SDNode *Node,
13791 SmallVectorImpl<SDValue> &Results,
13792 SelectionDAG &DAG) {
13794 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13796 // Convert wide load -> cmpxchg8b/cmpxchg16b
13797 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13798 // (The only way to get a 16-byte load is cmpxchg16b)
13799 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13800 SDValue Zero = DAG.getConstant(0, VT);
13801 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13802 Node->getOperand(0),
13803 Node->getOperand(1), Zero, Zero,
13804 cast<AtomicSDNode>(Node)->getMemOperand(),
13805 cast<AtomicSDNode>(Node)->getOrdering(),
13806 cast<AtomicSDNode>(Node)->getSynchScope());
13807 Results.push_back(Swap.getValue(0));
13808 Results.push_back(Swap.getValue(1));
13812 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13813 SelectionDAG &DAG, unsigned NewOp) {
13815 assert (Node->getValueType(0) == MVT::i64 &&
13816 "Only know how to expand i64 atomics");
13818 SDValue Chain = Node->getOperand(0);
13819 SDValue In1 = Node->getOperand(1);
13820 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13821 Node->getOperand(2), DAG.getIntPtrConstant(0));
13822 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13823 Node->getOperand(2), DAG.getIntPtrConstant(1));
13824 SDValue Ops[] = { Chain, In1, In2L, In2H };
13825 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13827 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13828 cast<MemSDNode>(Node)->getMemOperand());
13829 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13830 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13831 Results.push_back(Result.getValue(2));
13834 /// ReplaceNodeResults - Replace a node with an illegal result type
13835 /// with a new node built out of custom code.
13836 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13837 SmallVectorImpl<SDValue>&Results,
13838 SelectionDAG &DAG) const {
13840 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13841 switch (N->getOpcode()) {
13843 llvm_unreachable("Do not know how to custom type legalize this operation!");
13844 case ISD::SIGN_EXTEND_INREG:
13849 // We don't want to expand or promote these.
13851 case ISD::FP_TO_SINT:
13852 case ISD::FP_TO_UINT: {
13853 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13855 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13858 std::pair<SDValue,SDValue> Vals =
13859 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13860 SDValue FIST = Vals.first, StackSlot = Vals.second;
13861 if (FIST.getNode() != 0) {
13862 EVT VT = N->getValueType(0);
13863 // Return a load from the stack slot.
13864 if (StackSlot.getNode() != 0)
13865 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13866 MachinePointerInfo(),
13867 false, false, false, 0));
13869 Results.push_back(FIST);
13873 case ISD::UINT_TO_FP: {
13874 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13875 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13876 N->getValueType(0) != MVT::v2f32)
13878 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13880 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13882 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13883 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13884 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13885 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13886 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13887 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13890 case ISD::FP_ROUND: {
13891 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13893 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13894 Results.push_back(V);
13897 case ISD::READCYCLECOUNTER: {
13898 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13899 SDValue TheChain = N->getOperand(0);
13900 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13901 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13903 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13905 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13906 SDValue Ops[] = { eax, edx };
13907 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13908 array_lengthof(Ops)));
13909 Results.push_back(edx.getValue(1));
13912 case ISD::ATOMIC_CMP_SWAP: {
13913 EVT T = N->getValueType(0);
13914 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13915 bool Regs64bit = T == MVT::i128;
13916 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13917 SDValue cpInL, cpInH;
13918 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13919 DAG.getConstant(0, HalfT));
13920 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13921 DAG.getConstant(1, HalfT));
13922 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13923 Regs64bit ? X86::RAX : X86::EAX,
13925 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13926 Regs64bit ? X86::RDX : X86::EDX,
13927 cpInH, cpInL.getValue(1));
13928 SDValue swapInL, swapInH;
13929 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13930 DAG.getConstant(0, HalfT));
13931 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13932 DAG.getConstant(1, HalfT));
13933 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13934 Regs64bit ? X86::RBX : X86::EBX,
13935 swapInL, cpInH.getValue(1));
13936 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13937 Regs64bit ? X86::RCX : X86::ECX,
13938 swapInH, swapInL.getValue(1));
13939 SDValue Ops[] = { swapInH.getValue(0),
13941 swapInH.getValue(1) };
13942 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13943 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13944 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13945 X86ISD::LCMPXCHG8_DAG;
13946 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13947 Ops, array_lengthof(Ops), T, MMO);
13948 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13949 Regs64bit ? X86::RAX : X86::EAX,
13950 HalfT, Result.getValue(1));
13951 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13952 Regs64bit ? X86::RDX : X86::EDX,
13953 HalfT, cpOutL.getValue(2));
13954 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13955 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13956 Results.push_back(cpOutH.getValue(1));
13959 case ISD::ATOMIC_LOAD_ADD:
13960 case ISD::ATOMIC_LOAD_AND:
13961 case ISD::ATOMIC_LOAD_NAND:
13962 case ISD::ATOMIC_LOAD_OR:
13963 case ISD::ATOMIC_LOAD_SUB:
13964 case ISD::ATOMIC_LOAD_XOR:
13965 case ISD::ATOMIC_LOAD_MAX:
13966 case ISD::ATOMIC_LOAD_MIN:
13967 case ISD::ATOMIC_LOAD_UMAX:
13968 case ISD::ATOMIC_LOAD_UMIN:
13969 case ISD::ATOMIC_SWAP: {
13971 switch (N->getOpcode()) {
13972 default: llvm_unreachable("Unexpected opcode");
13973 case ISD::ATOMIC_LOAD_ADD:
13974 Opc = X86ISD::ATOMADD64_DAG;
13976 case ISD::ATOMIC_LOAD_AND:
13977 Opc = X86ISD::ATOMAND64_DAG;
13979 case ISD::ATOMIC_LOAD_NAND:
13980 Opc = X86ISD::ATOMNAND64_DAG;
13982 case ISD::ATOMIC_LOAD_OR:
13983 Opc = X86ISD::ATOMOR64_DAG;
13985 case ISD::ATOMIC_LOAD_SUB:
13986 Opc = X86ISD::ATOMSUB64_DAG;
13988 case ISD::ATOMIC_LOAD_XOR:
13989 Opc = X86ISD::ATOMXOR64_DAG;
13991 case ISD::ATOMIC_LOAD_MAX:
13992 Opc = X86ISD::ATOMMAX64_DAG;
13994 case ISD::ATOMIC_LOAD_MIN:
13995 Opc = X86ISD::ATOMMIN64_DAG;
13997 case ISD::ATOMIC_LOAD_UMAX:
13998 Opc = X86ISD::ATOMUMAX64_DAG;
14000 case ISD::ATOMIC_LOAD_UMIN:
14001 Opc = X86ISD::ATOMUMIN64_DAG;
14003 case ISD::ATOMIC_SWAP:
14004 Opc = X86ISD::ATOMSWAP64_DAG;
14007 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
14010 case ISD::ATOMIC_LOAD:
14011 ReplaceATOMIC_LOAD(N, Results, DAG);
14015 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
14017 default: return NULL;
14018 case X86ISD::BSF: return "X86ISD::BSF";
14019 case X86ISD::BSR: return "X86ISD::BSR";
14020 case X86ISD::SHLD: return "X86ISD::SHLD";
14021 case X86ISD::SHRD: return "X86ISD::SHRD";
14022 case X86ISD::FAND: return "X86ISD::FAND";
14023 case X86ISD::FANDN: return "X86ISD::FANDN";
14024 case X86ISD::FOR: return "X86ISD::FOR";
14025 case X86ISD::FXOR: return "X86ISD::FXOR";
14026 case X86ISD::FSRL: return "X86ISD::FSRL";
14027 case X86ISD::FILD: return "X86ISD::FILD";
14028 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
14029 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
14030 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
14031 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
14032 case X86ISD::FLD: return "X86ISD::FLD";
14033 case X86ISD::FST: return "X86ISD::FST";
14034 case X86ISD::CALL: return "X86ISD::CALL";
14035 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
14036 case X86ISD::BT: return "X86ISD::BT";
14037 case X86ISD::CMP: return "X86ISD::CMP";
14038 case X86ISD::COMI: return "X86ISD::COMI";
14039 case X86ISD::UCOMI: return "X86ISD::UCOMI";
14040 case X86ISD::CMPM: return "X86ISD::CMPM";
14041 case X86ISD::CMPMU: return "X86ISD::CMPMU";
14042 case X86ISD::SETCC: return "X86ISD::SETCC";
14043 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
14044 case X86ISD::FSETCC: return "X86ISD::FSETCC";
14045 case X86ISD::CMOV: return "X86ISD::CMOV";
14046 case X86ISD::BRCOND: return "X86ISD::BRCOND";
14047 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
14048 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
14049 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
14050 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
14051 case X86ISD::Wrapper: return "X86ISD::Wrapper";
14052 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
14053 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
14054 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
14055 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
14056 case X86ISD::PINSRB: return "X86ISD::PINSRB";
14057 case X86ISD::PINSRW: return "X86ISD::PINSRW";
14058 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
14059 case X86ISD::ANDNP: return "X86ISD::ANDNP";
14060 case X86ISD::PSIGN: return "X86ISD::PSIGN";
14061 case X86ISD::BLENDV: return "X86ISD::BLENDV";
14062 case X86ISD::BLENDI: return "X86ISD::BLENDI";
14063 case X86ISD::SUBUS: return "X86ISD::SUBUS";
14064 case X86ISD::HADD: return "X86ISD::HADD";
14065 case X86ISD::HSUB: return "X86ISD::HSUB";
14066 case X86ISD::FHADD: return "X86ISD::FHADD";
14067 case X86ISD::FHSUB: return "X86ISD::FHSUB";
14068 case X86ISD::UMAX: return "X86ISD::UMAX";
14069 case X86ISD::UMIN: return "X86ISD::UMIN";
14070 case X86ISD::SMAX: return "X86ISD::SMAX";
14071 case X86ISD::SMIN: return "X86ISD::SMIN";
14072 case X86ISD::FMAX: return "X86ISD::FMAX";
14073 case X86ISD::FMIN: return "X86ISD::FMIN";
14074 case X86ISD::FMAXC: return "X86ISD::FMAXC";
14075 case X86ISD::FMINC: return "X86ISD::FMINC";
14076 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
14077 case X86ISD::FRCP: return "X86ISD::FRCP";
14078 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
14079 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
14080 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
14081 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
14082 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
14083 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
14084 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
14085 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
14086 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
14087 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
14088 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
14089 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
14090 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
14091 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
14092 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
14093 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
14094 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
14095 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
14096 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
14097 case X86ISD::VZEXT: return "X86ISD::VZEXT";
14098 case X86ISD::VSEXT: return "X86ISD::VSEXT";
14099 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
14100 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
14101 case X86ISD::VINSERT: return "X86ISD::VINSERT";
14102 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
14103 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
14104 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
14105 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
14106 case X86ISD::VSHL: return "X86ISD::VSHL";
14107 case X86ISD::VSRL: return "X86ISD::VSRL";
14108 case X86ISD::VSRA: return "X86ISD::VSRA";
14109 case X86ISD::VSHLI: return "X86ISD::VSHLI";
14110 case X86ISD::VSRLI: return "X86ISD::VSRLI";
14111 case X86ISD::VSRAI: return "X86ISD::VSRAI";
14112 case X86ISD::CMPP: return "X86ISD::CMPP";
14113 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
14114 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
14115 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
14116 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
14117 case X86ISD::ADD: return "X86ISD::ADD";
14118 case X86ISD::SUB: return "X86ISD::SUB";
14119 case X86ISD::ADC: return "X86ISD::ADC";
14120 case X86ISD::SBB: return "X86ISD::SBB";
14121 case X86ISD::SMUL: return "X86ISD::SMUL";
14122 case X86ISD::UMUL: return "X86ISD::UMUL";
14123 case X86ISD::INC: return "X86ISD::INC";
14124 case X86ISD::DEC: return "X86ISD::DEC";
14125 case X86ISD::OR: return "X86ISD::OR";
14126 case X86ISD::XOR: return "X86ISD::XOR";
14127 case X86ISD::AND: return "X86ISD::AND";
14128 case X86ISD::BZHI: return "X86ISD::BZHI";
14129 case X86ISD::BEXTR: return "X86ISD::BEXTR";
14130 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
14131 case X86ISD::PTEST: return "X86ISD::PTEST";
14132 case X86ISD::TESTP: return "X86ISD::TESTP";
14133 case X86ISD::TESTM: return "X86ISD::TESTM";
14134 case X86ISD::TESTNM: return "X86ISD::TESTNM";
14135 case X86ISD::KORTEST: return "X86ISD::KORTEST";
14136 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
14137 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
14138 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
14139 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
14140 case X86ISD::SHUFP: return "X86ISD::SHUFP";
14141 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
14142 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
14143 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
14144 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
14145 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
14146 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
14147 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
14148 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
14149 case X86ISD::MOVSD: return "X86ISD::MOVSD";
14150 case X86ISD::MOVSS: return "X86ISD::MOVSS";
14151 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
14152 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
14153 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
14154 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
14155 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
14156 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
14157 case X86ISD::VPERMV: return "X86ISD::VPERMV";
14158 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
14159 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
14160 case X86ISD::VPERMI: return "X86ISD::VPERMI";
14161 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
14162 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
14163 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
14164 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
14165 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
14166 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
14167 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
14168 case X86ISD::SAHF: return "X86ISD::SAHF";
14169 case X86ISD::RDRAND: return "X86ISD::RDRAND";
14170 case X86ISD::RDSEED: return "X86ISD::RDSEED";
14171 case X86ISD::FMADD: return "X86ISD::FMADD";
14172 case X86ISD::FMSUB: return "X86ISD::FMSUB";
14173 case X86ISD::FNMADD: return "X86ISD::FNMADD";
14174 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
14175 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
14176 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
14177 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
14178 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
14179 case X86ISD::XTEST: return "X86ISD::XTEST";
14183 // isLegalAddressingMode - Return true if the addressing mode represented
14184 // by AM is legal for this target, for a load/store of the specified type.
14185 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
14187 // X86 supports extremely general addressing modes.
14188 CodeModel::Model M = getTargetMachine().getCodeModel();
14189 Reloc::Model R = getTargetMachine().getRelocationModel();
14191 // X86 allows a sign-extended 32-bit immediate field as a displacement.
14192 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
14197 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
14199 // If a reference to this global requires an extra load, we can't fold it.
14200 if (isGlobalStubReference(GVFlags))
14203 // If BaseGV requires a register for the PIC base, we cannot also have a
14204 // BaseReg specified.
14205 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
14208 // If lower 4G is not available, then we must use rip-relative addressing.
14209 if ((M != CodeModel::Small || R != Reloc::Static) &&
14210 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
14214 switch (AM.Scale) {
14220 // These scales always work.
14225 // These scales are formed with basereg+scalereg. Only accept if there is
14230 default: // Other stuff never works.
14237 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
14238 unsigned Bits = Ty->getScalarSizeInBits();
14240 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
14241 // particularly cheaper than those without.
14245 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
14246 // variable shifts just as cheap as scalar ones.
14247 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
14250 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
14251 // fully general vector.
14255 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
14256 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14258 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
14259 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
14260 return NumBits1 > NumBits2;
14263 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
14264 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14267 if (!isTypeLegal(EVT::getEVT(Ty1)))
14270 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
14272 // Assuming the caller doesn't have a zeroext or signext return parameter,
14273 // truncation all the way down to i1 is valid.
14277 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
14278 return isInt<32>(Imm);
14281 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
14282 // Can also use sub to handle negated immediates.
14283 return isInt<32>(Imm);
14286 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
14287 if (!VT1.isInteger() || !VT2.isInteger())
14289 unsigned NumBits1 = VT1.getSizeInBits();
14290 unsigned NumBits2 = VT2.getSizeInBits();
14291 return NumBits1 > NumBits2;
14294 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
14295 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14296 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
14299 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
14300 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14301 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
14304 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
14305 EVT VT1 = Val.getValueType();
14306 if (isZExtFree(VT1, VT2))
14309 if (Val.getOpcode() != ISD::LOAD)
14312 if (!VT1.isSimple() || !VT1.isInteger() ||
14313 !VT2.isSimple() || !VT2.isInteger())
14316 switch (VT1.getSimpleVT().SimpleTy) {
14321 // X86 has 8, 16, and 32-bit zero-extending loads.
14329 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
14330 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
14333 VT = VT.getScalarType();
14335 if (!VT.isSimple())
14338 switch (VT.getSimpleVT().SimpleTy) {
14349 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
14350 // i16 instructions are longer (0x66 prefix) and potentially slower.
14351 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
14354 /// isShuffleMaskLegal - Targets can use this to indicate that they only
14355 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
14356 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
14357 /// are assumed to be legal.
14359 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
14361 if (!VT.isSimple())
14364 MVT SVT = VT.getSimpleVT();
14366 // Very little shuffling can be done for 64-bit vectors right now.
14367 if (VT.getSizeInBits() == 64)
14370 // FIXME: pshufb, blends, shifts.
14371 return (SVT.getVectorNumElements() == 2 ||
14372 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
14373 isMOVLMask(M, SVT) ||
14374 isSHUFPMask(M, SVT) ||
14375 isPSHUFDMask(M, SVT) ||
14376 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
14377 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
14378 isPALIGNRMask(M, SVT, Subtarget) ||
14379 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
14380 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
14381 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
14382 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
14386 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
14388 if (!VT.isSimple())
14391 MVT SVT = VT.getSimpleVT();
14392 unsigned NumElts = SVT.getVectorNumElements();
14393 // FIXME: This collection of masks seems suspect.
14396 if (NumElts == 4 && SVT.is128BitVector()) {
14397 return (isMOVLMask(Mask, SVT) ||
14398 isCommutedMOVLMask(Mask, SVT, true) ||
14399 isSHUFPMask(Mask, SVT) ||
14400 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14405 //===----------------------------------------------------------------------===//
14406 // X86 Scheduler Hooks
14407 //===----------------------------------------------------------------------===//
14409 /// Utility function to emit xbegin specifying the start of an RTM region.
14410 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14411 const TargetInstrInfo *TII) {
14412 DebugLoc DL = MI->getDebugLoc();
14414 const BasicBlock *BB = MBB->getBasicBlock();
14415 MachineFunction::iterator I = MBB;
14418 // For the v = xbegin(), we generate
14429 MachineBasicBlock *thisMBB = MBB;
14430 MachineFunction *MF = MBB->getParent();
14431 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14432 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14433 MF->insert(I, mainMBB);
14434 MF->insert(I, sinkMBB);
14436 // Transfer the remainder of BB and its successor edges to sinkMBB.
14437 sinkMBB->splice(sinkMBB->begin(), MBB,
14438 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
14439 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14443 // # fallthrough to mainMBB
14444 // # abortion to sinkMBB
14445 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14446 thisMBB->addSuccessor(mainMBB);
14447 thisMBB->addSuccessor(sinkMBB);
14451 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14452 mainMBB->addSuccessor(sinkMBB);
14455 // EAX is live into the sinkMBB
14456 sinkMBB->addLiveIn(X86::EAX);
14457 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14458 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14461 MI->eraseFromParent();
14465 // Get CMPXCHG opcode for the specified data type.
14466 static unsigned getCmpXChgOpcode(EVT VT) {
14467 switch (VT.getSimpleVT().SimpleTy) {
14468 case MVT::i8: return X86::LCMPXCHG8;
14469 case MVT::i16: return X86::LCMPXCHG16;
14470 case MVT::i32: return X86::LCMPXCHG32;
14471 case MVT::i64: return X86::LCMPXCHG64;
14475 llvm_unreachable("Invalid operand size!");
14478 // Get LOAD opcode for the specified data type.
14479 static unsigned getLoadOpcode(EVT VT) {
14480 switch (VT.getSimpleVT().SimpleTy) {
14481 case MVT::i8: return X86::MOV8rm;
14482 case MVT::i16: return X86::MOV16rm;
14483 case MVT::i32: return X86::MOV32rm;
14484 case MVT::i64: return X86::MOV64rm;
14488 llvm_unreachable("Invalid operand size!");
14491 // Get opcode of the non-atomic one from the specified atomic instruction.
14492 static unsigned getNonAtomicOpcode(unsigned Opc) {
14494 case X86::ATOMAND8: return X86::AND8rr;
14495 case X86::ATOMAND16: return X86::AND16rr;
14496 case X86::ATOMAND32: return X86::AND32rr;
14497 case X86::ATOMAND64: return X86::AND64rr;
14498 case X86::ATOMOR8: return X86::OR8rr;
14499 case X86::ATOMOR16: return X86::OR16rr;
14500 case X86::ATOMOR32: return X86::OR32rr;
14501 case X86::ATOMOR64: return X86::OR64rr;
14502 case X86::ATOMXOR8: return X86::XOR8rr;
14503 case X86::ATOMXOR16: return X86::XOR16rr;
14504 case X86::ATOMXOR32: return X86::XOR32rr;
14505 case X86::ATOMXOR64: return X86::XOR64rr;
14507 llvm_unreachable("Unhandled atomic-load-op opcode!");
14510 // Get opcode of the non-atomic one from the specified atomic instruction with
14512 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14513 unsigned &ExtraOpc) {
14515 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14516 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14517 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14518 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14519 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14520 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14521 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14522 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14523 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14524 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14525 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14526 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14527 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14528 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14529 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14530 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14531 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14532 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14533 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14534 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14536 llvm_unreachable("Unhandled atomic-load-op opcode!");
14539 // Get opcode of the non-atomic one from the specified atomic instruction for
14540 // 64-bit data type on 32-bit target.
14541 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14543 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14544 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14545 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14546 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14547 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14548 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14549 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14550 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14551 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14552 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14554 llvm_unreachable("Unhandled atomic-load-op opcode!");
14557 // Get opcode of the non-atomic one from the specified atomic instruction for
14558 // 64-bit data type on 32-bit target with extra opcode.
14559 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14561 unsigned &ExtraOpc) {
14563 case X86::ATOMNAND6432:
14564 ExtraOpc = X86::NOT32r;
14565 HiOpc = X86::AND32rr;
14566 return X86::AND32rr;
14568 llvm_unreachable("Unhandled atomic-load-op opcode!");
14571 // Get pseudo CMOV opcode from the specified data type.
14572 static unsigned getPseudoCMOVOpc(EVT VT) {
14573 switch (VT.getSimpleVT().SimpleTy) {
14574 case MVT::i8: return X86::CMOV_GR8;
14575 case MVT::i16: return X86::CMOV_GR16;
14576 case MVT::i32: return X86::CMOV_GR32;
14580 llvm_unreachable("Unknown CMOV opcode!");
14583 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14584 // They will be translated into a spin-loop or compare-exchange loop from
14587 // dst = atomic-fetch-op MI.addr, MI.val
14593 // t1 = LOAD MI.addr
14595 // t4 = phi(t1, t3 / loop)
14596 // t2 = OP MI.val, t4
14598 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14604 MachineBasicBlock *
14605 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14606 MachineBasicBlock *MBB) const {
14607 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14608 DebugLoc DL = MI->getDebugLoc();
14610 MachineFunction *MF = MBB->getParent();
14611 MachineRegisterInfo &MRI = MF->getRegInfo();
14613 const BasicBlock *BB = MBB->getBasicBlock();
14614 MachineFunction::iterator I = MBB;
14617 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14618 "Unexpected number of operands");
14620 assert(MI->hasOneMemOperand() &&
14621 "Expected atomic-load-op to have one memoperand");
14623 // Memory Reference
14624 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14625 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14627 unsigned DstReg, SrcReg;
14628 unsigned MemOpndSlot;
14630 unsigned CurOp = 0;
14632 DstReg = MI->getOperand(CurOp++).getReg();
14633 MemOpndSlot = CurOp;
14634 CurOp += X86::AddrNumOperands;
14635 SrcReg = MI->getOperand(CurOp++).getReg();
14637 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14638 MVT::SimpleValueType VT = *RC->vt_begin();
14639 unsigned t1 = MRI.createVirtualRegister(RC);
14640 unsigned t2 = MRI.createVirtualRegister(RC);
14641 unsigned t3 = MRI.createVirtualRegister(RC);
14642 unsigned t4 = MRI.createVirtualRegister(RC);
14643 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14645 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14646 unsigned LOADOpc = getLoadOpcode(VT);
14648 // For the atomic load-arith operator, we generate
14651 // t1 = LOAD [MI.addr]
14653 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14654 // t1 = OP MI.val, EAX
14656 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14662 MachineBasicBlock *thisMBB = MBB;
14663 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14664 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14665 MF->insert(I, mainMBB);
14666 MF->insert(I, sinkMBB);
14668 MachineInstrBuilder MIB;
14670 // Transfer the remainder of BB and its successor edges to sinkMBB.
14671 sinkMBB->splice(sinkMBB->begin(), MBB,
14672 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
14673 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14676 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14677 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14678 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14680 NewMO.setIsKill(false);
14681 MIB.addOperand(NewMO);
14683 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14684 unsigned flags = (*MMOI)->getFlags();
14685 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14686 MachineMemOperand *MMO =
14687 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14688 (*MMOI)->getSize(),
14689 (*MMOI)->getBaseAlignment(),
14690 (*MMOI)->getTBAAInfo(),
14691 (*MMOI)->getRanges());
14692 MIB.addMemOperand(MMO);
14695 thisMBB->addSuccessor(mainMBB);
14698 MachineBasicBlock *origMainMBB = mainMBB;
14701 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14702 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14704 unsigned Opc = MI->getOpcode();
14707 llvm_unreachable("Unhandled atomic-load-op opcode!");
14708 case X86::ATOMAND8:
14709 case X86::ATOMAND16:
14710 case X86::ATOMAND32:
14711 case X86::ATOMAND64:
14713 case X86::ATOMOR16:
14714 case X86::ATOMOR32:
14715 case X86::ATOMOR64:
14716 case X86::ATOMXOR8:
14717 case X86::ATOMXOR16:
14718 case X86::ATOMXOR32:
14719 case X86::ATOMXOR64: {
14720 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14721 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14725 case X86::ATOMNAND8:
14726 case X86::ATOMNAND16:
14727 case X86::ATOMNAND32:
14728 case X86::ATOMNAND64: {
14729 unsigned Tmp = MRI.createVirtualRegister(RC);
14731 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14732 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14734 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14737 case X86::ATOMMAX8:
14738 case X86::ATOMMAX16:
14739 case X86::ATOMMAX32:
14740 case X86::ATOMMAX64:
14741 case X86::ATOMMIN8:
14742 case X86::ATOMMIN16:
14743 case X86::ATOMMIN32:
14744 case X86::ATOMMIN64:
14745 case X86::ATOMUMAX8:
14746 case X86::ATOMUMAX16:
14747 case X86::ATOMUMAX32:
14748 case X86::ATOMUMAX64:
14749 case X86::ATOMUMIN8:
14750 case X86::ATOMUMIN16:
14751 case X86::ATOMUMIN32:
14752 case X86::ATOMUMIN64: {
14754 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14756 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14760 if (Subtarget->hasCMov()) {
14761 if (VT != MVT::i8) {
14763 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14767 // Promote i8 to i32 to use CMOV32
14768 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14769 const TargetRegisterClass *RC32 =
14770 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14771 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14772 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14773 unsigned Tmp = MRI.createVirtualRegister(RC32);
14775 unsigned Undef = MRI.createVirtualRegister(RC32);
14776 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14778 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14781 .addImm(X86::sub_8bit);
14782 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14785 .addImm(X86::sub_8bit);
14787 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14791 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14792 .addReg(Tmp, 0, X86::sub_8bit);
14795 // Use pseudo select and lower them.
14796 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14797 "Invalid atomic-load-op transformation!");
14798 unsigned SelOpc = getPseudoCMOVOpc(VT);
14799 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14800 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14801 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14802 .addReg(SrcReg).addReg(t4)
14804 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14805 // Replace the original PHI node as mainMBB is changed after CMOV
14807 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14808 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14809 Phi->eraseFromParent();
14815 // Copy PhyReg back from virtual register.
14816 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14819 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14820 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14821 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14823 NewMO.setIsKill(false);
14824 MIB.addOperand(NewMO);
14827 MIB.setMemRefs(MMOBegin, MMOEnd);
14829 // Copy PhyReg back to virtual register.
14830 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14833 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14835 mainMBB->addSuccessor(origMainMBB);
14836 mainMBB->addSuccessor(sinkMBB);
14839 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14840 TII->get(TargetOpcode::COPY), DstReg)
14843 MI->eraseFromParent();
14847 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14848 // instructions. They will be translated into a spin-loop or compare-exchange
14852 // dst = atomic-fetch-op MI.addr, MI.val
14858 // t1L = LOAD [MI.addr + 0]
14859 // t1H = LOAD [MI.addr + 4]
14861 // t4L = phi(t1L, t3L / loop)
14862 // t4H = phi(t1H, t3H / loop)
14863 // t2L = OP MI.val.lo, t4L
14864 // t2H = OP MI.val.hi, t4H
14869 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14877 MachineBasicBlock *
14878 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14879 MachineBasicBlock *MBB) const {
14880 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14881 DebugLoc DL = MI->getDebugLoc();
14883 MachineFunction *MF = MBB->getParent();
14884 MachineRegisterInfo &MRI = MF->getRegInfo();
14886 const BasicBlock *BB = MBB->getBasicBlock();
14887 MachineFunction::iterator I = MBB;
14890 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14891 "Unexpected number of operands");
14893 assert(MI->hasOneMemOperand() &&
14894 "Expected atomic-load-op32 to have one memoperand");
14896 // Memory Reference
14897 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14898 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14900 unsigned DstLoReg, DstHiReg;
14901 unsigned SrcLoReg, SrcHiReg;
14902 unsigned MemOpndSlot;
14904 unsigned CurOp = 0;
14906 DstLoReg = MI->getOperand(CurOp++).getReg();
14907 DstHiReg = MI->getOperand(CurOp++).getReg();
14908 MemOpndSlot = CurOp;
14909 CurOp += X86::AddrNumOperands;
14910 SrcLoReg = MI->getOperand(CurOp++).getReg();
14911 SrcHiReg = MI->getOperand(CurOp++).getReg();
14913 const TargetRegisterClass *RC = &X86::GR32RegClass;
14914 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14916 unsigned t1L = MRI.createVirtualRegister(RC);
14917 unsigned t1H = MRI.createVirtualRegister(RC);
14918 unsigned t2L = MRI.createVirtualRegister(RC);
14919 unsigned t2H = MRI.createVirtualRegister(RC);
14920 unsigned t3L = MRI.createVirtualRegister(RC);
14921 unsigned t3H = MRI.createVirtualRegister(RC);
14922 unsigned t4L = MRI.createVirtualRegister(RC);
14923 unsigned t4H = MRI.createVirtualRegister(RC);
14925 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14926 unsigned LOADOpc = X86::MOV32rm;
14928 // For the atomic load-arith operator, we generate
14931 // t1L = LOAD [MI.addr + 0]
14932 // t1H = LOAD [MI.addr + 4]
14934 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14935 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14936 // t2L = OP MI.val.lo, t4L
14937 // t2H = OP MI.val.hi, t4H
14940 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14948 MachineBasicBlock *thisMBB = MBB;
14949 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14950 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14951 MF->insert(I, mainMBB);
14952 MF->insert(I, sinkMBB);
14954 MachineInstrBuilder MIB;
14956 // Transfer the remainder of BB and its successor edges to sinkMBB.
14957 sinkMBB->splice(sinkMBB->begin(), MBB,
14958 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
14959 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14963 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14964 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14965 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14967 NewMO.setIsKill(false);
14968 MIB.addOperand(NewMO);
14970 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14971 unsigned flags = (*MMOI)->getFlags();
14972 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14973 MachineMemOperand *MMO =
14974 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14975 (*MMOI)->getSize(),
14976 (*MMOI)->getBaseAlignment(),
14977 (*MMOI)->getTBAAInfo(),
14978 (*MMOI)->getRanges());
14979 MIB.addMemOperand(MMO);
14981 MachineInstr *LowMI = MIB;
14984 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14985 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14986 if (i == X86::AddrDisp) {
14987 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14989 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14991 NewMO.setIsKill(false);
14992 MIB.addOperand(NewMO);
14995 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14997 thisMBB->addSuccessor(mainMBB);
15000 MachineBasicBlock *origMainMBB = mainMBB;
15003 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
15004 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
15005 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
15006 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
15008 unsigned Opc = MI->getOpcode();
15011 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
15012 case X86::ATOMAND6432:
15013 case X86::ATOMOR6432:
15014 case X86::ATOMXOR6432:
15015 case X86::ATOMADD6432:
15016 case X86::ATOMSUB6432: {
15018 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15019 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
15021 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
15025 case X86::ATOMNAND6432: {
15026 unsigned HiOpc, NOTOpc;
15027 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
15028 unsigned TmpL = MRI.createVirtualRegister(RC);
15029 unsigned TmpH = MRI.createVirtualRegister(RC);
15030 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
15032 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
15034 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
15035 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
15038 case X86::ATOMMAX6432:
15039 case X86::ATOMMIN6432:
15040 case X86::ATOMUMAX6432:
15041 case X86::ATOMUMIN6432: {
15043 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15044 unsigned cL = MRI.createVirtualRegister(RC8);
15045 unsigned cH = MRI.createVirtualRegister(RC8);
15046 unsigned cL32 = MRI.createVirtualRegister(RC);
15047 unsigned cH32 = MRI.createVirtualRegister(RC);
15048 unsigned cc = MRI.createVirtualRegister(RC);
15049 // cl := cmp src_lo, lo
15050 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
15051 .addReg(SrcLoReg).addReg(t4L);
15052 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
15053 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
15054 // ch := cmp src_hi, hi
15055 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
15056 .addReg(SrcHiReg).addReg(t4H);
15057 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
15058 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
15059 // cc := if (src_hi == hi) ? cl : ch;
15060 if (Subtarget->hasCMov()) {
15061 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
15062 .addReg(cH32).addReg(cL32);
15064 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
15065 .addReg(cH32).addReg(cL32)
15066 .addImm(X86::COND_E);
15067 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15069 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
15070 if (Subtarget->hasCMov()) {
15071 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
15072 .addReg(SrcLoReg).addReg(t4L);
15073 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
15074 .addReg(SrcHiReg).addReg(t4H);
15076 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
15077 .addReg(SrcLoReg).addReg(t4L)
15078 .addImm(X86::COND_NE);
15079 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15080 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
15081 // 2nd CMOV lowering.
15082 mainMBB->addLiveIn(X86::EFLAGS);
15083 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
15084 .addReg(SrcHiReg).addReg(t4H)
15085 .addImm(X86::COND_NE);
15086 mainMBB = EmitLoweredSelect(MIB, mainMBB);
15087 // Replace the original PHI node as mainMBB is changed after CMOV
15089 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
15090 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
15091 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
15092 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
15093 PhiL->eraseFromParent();
15094 PhiH->eraseFromParent();
15098 case X86::ATOMSWAP6432: {
15100 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
15101 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
15102 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
15107 // Copy EDX:EAX back from HiReg:LoReg
15108 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
15109 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
15110 // Copy ECX:EBX from t1H:t1L
15111 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
15112 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
15114 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
15115 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15116 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
15118 NewMO.setIsKill(false);
15119 MIB.addOperand(NewMO);
15121 MIB.setMemRefs(MMOBegin, MMOEnd);
15123 // Copy EDX:EAX back to t3H:t3L
15124 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
15125 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
15127 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
15129 mainMBB->addSuccessor(origMainMBB);
15130 mainMBB->addSuccessor(sinkMBB);
15133 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15134 TII->get(TargetOpcode::COPY), DstLoReg)
15136 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15137 TII->get(TargetOpcode::COPY), DstHiReg)
15140 MI->eraseFromParent();
15144 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
15145 // or XMM0_V32I8 in AVX all of this code can be replaced with that
15146 // in the .td file.
15147 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
15148 const TargetInstrInfo *TII) {
15150 switch (MI->getOpcode()) {
15151 default: llvm_unreachable("illegal opcode!");
15152 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
15153 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
15154 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
15155 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
15156 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
15157 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
15158 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
15159 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
15162 DebugLoc dl = MI->getDebugLoc();
15163 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15165 unsigned NumArgs = MI->getNumOperands();
15166 for (unsigned i = 1; i < NumArgs; ++i) {
15167 MachineOperand &Op = MI->getOperand(i);
15168 if (!(Op.isReg() && Op.isImplicit()))
15169 MIB.addOperand(Op);
15171 if (MI->hasOneMemOperand())
15172 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15174 BuildMI(*BB, MI, dl,
15175 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15176 .addReg(X86::XMM0);
15178 MI->eraseFromParent();
15182 // FIXME: Custom handling because TableGen doesn't support multiple implicit
15183 // defs in an instruction pattern
15184 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
15185 const TargetInstrInfo *TII) {
15187 switch (MI->getOpcode()) {
15188 default: llvm_unreachable("illegal opcode!");
15189 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
15190 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
15191 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
15192 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
15193 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
15194 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
15195 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
15196 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
15199 DebugLoc dl = MI->getDebugLoc();
15200 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15202 unsigned NumArgs = MI->getNumOperands(); // remove the results
15203 for (unsigned i = 1; i < NumArgs; ++i) {
15204 MachineOperand &Op = MI->getOperand(i);
15205 if (!(Op.isReg() && Op.isImplicit()))
15206 MIB.addOperand(Op);
15208 if (MI->hasOneMemOperand())
15209 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15211 BuildMI(*BB, MI, dl,
15212 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15215 MI->eraseFromParent();
15219 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
15220 const TargetInstrInfo *TII,
15221 const X86Subtarget* Subtarget) {
15222 DebugLoc dl = MI->getDebugLoc();
15224 // Address into RAX/EAX, other two args into ECX, EDX.
15225 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
15226 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
15227 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
15228 for (int i = 0; i < X86::AddrNumOperands; ++i)
15229 MIB.addOperand(MI->getOperand(i));
15231 unsigned ValOps = X86::AddrNumOperands;
15232 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
15233 .addReg(MI->getOperand(ValOps).getReg());
15234 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
15235 .addReg(MI->getOperand(ValOps+1).getReg());
15237 // The instruction doesn't actually take any operands though.
15238 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
15240 MI->eraseFromParent(); // The pseudo is gone now.
15244 MachineBasicBlock *
15245 X86TargetLowering::EmitVAARG64WithCustomInserter(
15247 MachineBasicBlock *MBB) const {
15248 // Emit va_arg instruction on X86-64.
15250 // Operands to this pseudo-instruction:
15251 // 0 ) Output : destination address (reg)
15252 // 1-5) Input : va_list address (addr, i64mem)
15253 // 6 ) ArgSize : Size (in bytes) of vararg type
15254 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
15255 // 8 ) Align : Alignment of type
15256 // 9 ) EFLAGS (implicit-def)
15258 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
15259 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
15261 unsigned DestReg = MI->getOperand(0).getReg();
15262 MachineOperand &Base = MI->getOperand(1);
15263 MachineOperand &Scale = MI->getOperand(2);
15264 MachineOperand &Index = MI->getOperand(3);
15265 MachineOperand &Disp = MI->getOperand(4);
15266 MachineOperand &Segment = MI->getOperand(5);
15267 unsigned ArgSize = MI->getOperand(6).getImm();
15268 unsigned ArgMode = MI->getOperand(7).getImm();
15269 unsigned Align = MI->getOperand(8).getImm();
15271 // Memory Reference
15272 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
15273 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15274 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15276 // Machine Information
15277 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15278 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
15279 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
15280 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
15281 DebugLoc DL = MI->getDebugLoc();
15283 // struct va_list {
15286 // i64 overflow_area (address)
15287 // i64 reg_save_area (address)
15289 // sizeof(va_list) = 24
15290 // alignment(va_list) = 8
15292 unsigned TotalNumIntRegs = 6;
15293 unsigned TotalNumXMMRegs = 8;
15294 bool UseGPOffset = (ArgMode == 1);
15295 bool UseFPOffset = (ArgMode == 2);
15296 unsigned MaxOffset = TotalNumIntRegs * 8 +
15297 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
15299 /* Align ArgSize to a multiple of 8 */
15300 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
15301 bool NeedsAlign = (Align > 8);
15303 MachineBasicBlock *thisMBB = MBB;
15304 MachineBasicBlock *overflowMBB;
15305 MachineBasicBlock *offsetMBB;
15306 MachineBasicBlock *endMBB;
15308 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
15309 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
15310 unsigned OffsetReg = 0;
15312 if (!UseGPOffset && !UseFPOffset) {
15313 // If we only pull from the overflow region, we don't create a branch.
15314 // We don't need to alter control flow.
15315 OffsetDestReg = 0; // unused
15316 OverflowDestReg = DestReg;
15319 overflowMBB = thisMBB;
15322 // First emit code to check if gp_offset (or fp_offset) is below the bound.
15323 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
15324 // If not, pull from overflow_area. (branch to overflowMBB)
15329 // offsetMBB overflowMBB
15334 // Registers for the PHI in endMBB
15335 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
15336 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
15338 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15339 MachineFunction *MF = MBB->getParent();
15340 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15341 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15342 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15344 MachineFunction::iterator MBBIter = MBB;
15347 // Insert the new basic blocks
15348 MF->insert(MBBIter, offsetMBB);
15349 MF->insert(MBBIter, overflowMBB);
15350 MF->insert(MBBIter, endMBB);
15352 // Transfer the remainder of MBB and its successor edges to endMBB.
15353 endMBB->splice(endMBB->begin(), thisMBB,
15354 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
15355 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
15357 // Make offsetMBB and overflowMBB successors of thisMBB
15358 thisMBB->addSuccessor(offsetMBB);
15359 thisMBB->addSuccessor(overflowMBB);
15361 // endMBB is a successor of both offsetMBB and overflowMBB
15362 offsetMBB->addSuccessor(endMBB);
15363 overflowMBB->addSuccessor(endMBB);
15365 // Load the offset value into a register
15366 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15367 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
15371 .addDisp(Disp, UseFPOffset ? 4 : 0)
15372 .addOperand(Segment)
15373 .setMemRefs(MMOBegin, MMOEnd);
15375 // Check if there is enough room left to pull this argument.
15376 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
15378 .addImm(MaxOffset + 8 - ArgSizeA8);
15380 // Branch to "overflowMBB" if offset >= max
15381 // Fall through to "offsetMBB" otherwise
15382 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
15383 .addMBB(overflowMBB);
15386 // In offsetMBB, emit code to use the reg_save_area.
15388 assert(OffsetReg != 0);
15390 // Read the reg_save_area address.
15391 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
15392 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
15397 .addOperand(Segment)
15398 .setMemRefs(MMOBegin, MMOEnd);
15400 // Zero-extend the offset
15401 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
15402 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15405 .addImm(X86::sub_32bit);
15407 // Add the offset to the reg_save_area to get the final address.
15408 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15409 .addReg(OffsetReg64)
15410 .addReg(RegSaveReg);
15412 // Compute the offset for the next argument
15413 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15414 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15416 .addImm(UseFPOffset ? 16 : 8);
15418 // Store it back into the va_list.
15419 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15423 .addDisp(Disp, UseFPOffset ? 4 : 0)
15424 .addOperand(Segment)
15425 .addReg(NextOffsetReg)
15426 .setMemRefs(MMOBegin, MMOEnd);
15429 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15434 // Emit code to use overflow area
15437 // Load the overflow_area address into a register.
15438 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15439 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15444 .addOperand(Segment)
15445 .setMemRefs(MMOBegin, MMOEnd);
15447 // If we need to align it, do so. Otherwise, just copy the address
15448 // to OverflowDestReg.
15450 // Align the overflow address
15451 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15452 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15454 // aligned_addr = (addr + (align-1)) & ~(align-1)
15455 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15456 .addReg(OverflowAddrReg)
15459 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15461 .addImm(~(uint64_t)(Align-1));
15463 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15464 .addReg(OverflowAddrReg);
15467 // Compute the next overflow address after this argument.
15468 // (the overflow address should be kept 8-byte aligned)
15469 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15470 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15471 .addReg(OverflowDestReg)
15472 .addImm(ArgSizeA8);
15474 // Store the new overflow address.
15475 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15480 .addOperand(Segment)
15481 .addReg(NextAddrReg)
15482 .setMemRefs(MMOBegin, MMOEnd);
15484 // If we branched, emit the PHI to the front of endMBB.
15486 BuildMI(*endMBB, endMBB->begin(), DL,
15487 TII->get(X86::PHI), DestReg)
15488 .addReg(OffsetDestReg).addMBB(offsetMBB)
15489 .addReg(OverflowDestReg).addMBB(overflowMBB);
15492 // Erase the pseudo instruction
15493 MI->eraseFromParent();
15498 MachineBasicBlock *
15499 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15501 MachineBasicBlock *MBB) const {
15502 // Emit code to save XMM registers to the stack. The ABI says that the
15503 // number of registers to save is given in %al, so it's theoretically
15504 // possible to do an indirect jump trick to avoid saving all of them,
15505 // however this code takes a simpler approach and just executes all
15506 // of the stores if %al is non-zero. It's less code, and it's probably
15507 // easier on the hardware branch predictor, and stores aren't all that
15508 // expensive anyway.
15510 // Create the new basic blocks. One block contains all the XMM stores,
15511 // and one block is the final destination regardless of whether any
15512 // stores were performed.
15513 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15514 MachineFunction *F = MBB->getParent();
15515 MachineFunction::iterator MBBIter = MBB;
15517 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15518 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15519 F->insert(MBBIter, XMMSaveMBB);
15520 F->insert(MBBIter, EndMBB);
15522 // Transfer the remainder of MBB and its successor edges to EndMBB.
15523 EndMBB->splice(EndMBB->begin(), MBB,
15524 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
15525 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15527 // The original block will now fall through to the XMM save block.
15528 MBB->addSuccessor(XMMSaveMBB);
15529 // The XMMSaveMBB will fall through to the end block.
15530 XMMSaveMBB->addSuccessor(EndMBB);
15532 // Now add the instructions.
15533 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15534 DebugLoc DL = MI->getDebugLoc();
15536 unsigned CountReg = MI->getOperand(0).getReg();
15537 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15538 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15540 if (!Subtarget->isTargetWin64()) {
15541 // If %al is 0, branch around the XMM save block.
15542 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15543 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15544 MBB->addSuccessor(EndMBB);
15547 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
15548 // that was just emitted, but clearly shouldn't be "saved".
15549 assert((MI->getNumOperands() <= 3 ||
15550 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
15551 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
15552 && "Expected last argument to be EFLAGS");
15553 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15554 // In the XMM save block, save all the XMM argument registers.
15555 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
15556 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15557 MachineMemOperand *MMO =
15558 F->getMachineMemOperand(
15559 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15560 MachineMemOperand::MOStore,
15561 /*Size=*/16, /*Align=*/16);
15562 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15563 .addFrameIndex(RegSaveFrameIndex)
15564 .addImm(/*Scale=*/1)
15565 .addReg(/*IndexReg=*/0)
15566 .addImm(/*Disp=*/Offset)
15567 .addReg(/*Segment=*/0)
15568 .addReg(MI->getOperand(i).getReg())
15569 .addMemOperand(MMO);
15572 MI->eraseFromParent(); // The pseudo instruction is gone now.
15577 // The EFLAGS operand of SelectItr might be missing a kill marker
15578 // because there were multiple uses of EFLAGS, and ISel didn't know
15579 // which to mark. Figure out whether SelectItr should have had a
15580 // kill marker, and set it if it should. Returns the correct kill
15582 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15583 MachineBasicBlock* BB,
15584 const TargetRegisterInfo* TRI) {
15585 // Scan forward through BB for a use/def of EFLAGS.
15586 MachineBasicBlock::iterator miI(std::next(SelectItr));
15587 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15588 const MachineInstr& mi = *miI;
15589 if (mi.readsRegister(X86::EFLAGS))
15591 if (mi.definesRegister(X86::EFLAGS))
15592 break; // Should have kill-flag - update below.
15595 // If we hit the end of the block, check whether EFLAGS is live into a
15597 if (miI == BB->end()) {
15598 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15599 sEnd = BB->succ_end();
15600 sItr != sEnd; ++sItr) {
15601 MachineBasicBlock* succ = *sItr;
15602 if (succ->isLiveIn(X86::EFLAGS))
15607 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15608 // out. SelectMI should have a kill flag on EFLAGS.
15609 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15613 MachineBasicBlock *
15614 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15615 MachineBasicBlock *BB) const {
15616 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15617 DebugLoc DL = MI->getDebugLoc();
15619 // To "insert" a SELECT_CC instruction, we actually have to insert the
15620 // diamond control-flow pattern. The incoming instruction knows the
15621 // destination vreg to set, the condition code register to branch on, the
15622 // true/false values to select between, and a branch opcode to use.
15623 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15624 MachineFunction::iterator It = BB;
15630 // cmpTY ccX, r1, r2
15632 // fallthrough --> copy0MBB
15633 MachineBasicBlock *thisMBB = BB;
15634 MachineFunction *F = BB->getParent();
15635 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15636 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15637 F->insert(It, copy0MBB);
15638 F->insert(It, sinkMBB);
15640 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15641 // live into the sink and copy blocks.
15642 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15643 if (!MI->killsRegister(X86::EFLAGS) &&
15644 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15645 copy0MBB->addLiveIn(X86::EFLAGS);
15646 sinkMBB->addLiveIn(X86::EFLAGS);
15649 // Transfer the remainder of BB and its successor edges to sinkMBB.
15650 sinkMBB->splice(sinkMBB->begin(), BB,
15651 std::next(MachineBasicBlock::iterator(MI)), BB->end());
15652 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15654 // Add the true and fallthrough blocks as its successors.
15655 BB->addSuccessor(copy0MBB);
15656 BB->addSuccessor(sinkMBB);
15658 // Create the conditional branch instruction.
15660 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15661 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15664 // %FalseValue = ...
15665 // # fallthrough to sinkMBB
15666 copy0MBB->addSuccessor(sinkMBB);
15669 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15671 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15672 TII->get(X86::PHI), MI->getOperand(0).getReg())
15673 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15674 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15676 MI->eraseFromParent(); // The pseudo instruction is gone now.
15680 MachineBasicBlock *
15681 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15682 bool Is64Bit) const {
15683 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15684 DebugLoc DL = MI->getDebugLoc();
15685 MachineFunction *MF = BB->getParent();
15686 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15688 assert(getTargetMachine().Options.EnableSegmentedStacks);
15690 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15691 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15694 // ... [Till the alloca]
15695 // If stacklet is not large enough, jump to mallocMBB
15698 // Allocate by subtracting from RSP
15699 // Jump to continueMBB
15702 // Allocate by call to runtime
15706 // [rest of original BB]
15709 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15710 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15711 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15713 MachineRegisterInfo &MRI = MF->getRegInfo();
15714 const TargetRegisterClass *AddrRegClass =
15715 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15717 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15718 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15719 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15720 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15721 sizeVReg = MI->getOperand(1).getReg(),
15722 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15724 MachineFunction::iterator MBBIter = BB;
15727 MF->insert(MBBIter, bumpMBB);
15728 MF->insert(MBBIter, mallocMBB);
15729 MF->insert(MBBIter, continueMBB);
15731 continueMBB->splice(continueMBB->begin(), BB,
15732 std::next(MachineBasicBlock::iterator(MI)), BB->end());
15733 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15735 // Add code to the main basic block to check if the stack limit has been hit,
15736 // and if so, jump to mallocMBB otherwise to bumpMBB.
15737 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15738 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15739 .addReg(tmpSPVReg).addReg(sizeVReg);
15740 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15741 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15742 .addReg(SPLimitVReg);
15743 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15745 // bumpMBB simply decreases the stack pointer, since we know the current
15746 // stacklet has enough space.
15747 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15748 .addReg(SPLimitVReg);
15749 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15750 .addReg(SPLimitVReg);
15751 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15753 // Calls into a routine in libgcc to allocate more space from the heap.
15754 const uint32_t *RegMask =
15755 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15757 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15759 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15760 .addExternalSymbol("__morestack_allocate_stack_space")
15761 .addRegMask(RegMask)
15762 .addReg(X86::RDI, RegState::Implicit)
15763 .addReg(X86::RAX, RegState::ImplicitDefine);
15765 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15767 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15768 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15769 .addExternalSymbol("__morestack_allocate_stack_space")
15770 .addRegMask(RegMask)
15771 .addReg(X86::EAX, RegState::ImplicitDefine);
15775 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15778 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15779 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15780 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15782 // Set up the CFG correctly.
15783 BB->addSuccessor(bumpMBB);
15784 BB->addSuccessor(mallocMBB);
15785 mallocMBB->addSuccessor(continueMBB);
15786 bumpMBB->addSuccessor(continueMBB);
15788 // Take care of the PHI nodes.
15789 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15790 MI->getOperand(0).getReg())
15791 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15792 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15794 // Delete the original pseudo instruction.
15795 MI->eraseFromParent();
15798 return continueMBB;
15801 MachineBasicBlock *
15802 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15803 MachineBasicBlock *BB) const {
15804 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15805 DebugLoc DL = MI->getDebugLoc();
15807 assert(!Subtarget->isTargetMacho());
15809 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15810 // non-trivial part is impdef of ESP.
15812 if (Subtarget->isTargetWin64()) {
15813 if (Subtarget->isTargetCygMing()) {
15814 // ___chkstk(Mingw64):
15815 // Clobbers R10, R11, RAX and EFLAGS.
15817 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15818 .addExternalSymbol("___chkstk")
15819 .addReg(X86::RAX, RegState::Implicit)
15820 .addReg(X86::RSP, RegState::Implicit)
15821 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15822 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15823 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15825 // __chkstk(MSVCRT): does not update stack pointer.
15826 // Clobbers R10, R11 and EFLAGS.
15827 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15828 .addExternalSymbol("__chkstk")
15829 .addReg(X86::RAX, RegState::Implicit)
15830 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15831 // RAX has the offset to be subtracted from RSP.
15832 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15837 const char *StackProbeSymbol =
15838 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15840 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15841 .addExternalSymbol(StackProbeSymbol)
15842 .addReg(X86::EAX, RegState::Implicit)
15843 .addReg(X86::ESP, RegState::Implicit)
15844 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15845 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15846 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15849 MI->eraseFromParent(); // The pseudo instruction is gone now.
15853 MachineBasicBlock *
15854 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15855 MachineBasicBlock *BB) const {
15856 // This is pretty easy. We're taking the value that we received from
15857 // our load from the relocation, sticking it in either RDI (x86-64)
15858 // or EAX and doing an indirect call. The return value will then
15859 // be in the normal return register.
15860 const X86InstrInfo *TII
15861 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15862 DebugLoc DL = MI->getDebugLoc();
15863 MachineFunction *F = BB->getParent();
15865 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15866 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15868 // Get a register mask for the lowered call.
15869 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15870 // proper register mask.
15871 const uint32_t *RegMask =
15872 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15873 if (Subtarget->is64Bit()) {
15874 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15875 TII->get(X86::MOV64rm), X86::RDI)
15877 .addImm(0).addReg(0)
15878 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15879 MI->getOperand(3).getTargetFlags())
15881 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15882 addDirectMem(MIB, X86::RDI);
15883 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15884 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15885 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15886 TII->get(X86::MOV32rm), X86::EAX)
15888 .addImm(0).addReg(0)
15889 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15890 MI->getOperand(3).getTargetFlags())
15892 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15893 addDirectMem(MIB, X86::EAX);
15894 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15896 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15897 TII->get(X86::MOV32rm), X86::EAX)
15898 .addReg(TII->getGlobalBaseReg(F))
15899 .addImm(0).addReg(0)
15900 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15901 MI->getOperand(3).getTargetFlags())
15903 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15904 addDirectMem(MIB, X86::EAX);
15905 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15908 MI->eraseFromParent(); // The pseudo instruction is gone now.
15912 MachineBasicBlock *
15913 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15914 MachineBasicBlock *MBB) const {
15915 DebugLoc DL = MI->getDebugLoc();
15916 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15918 MachineFunction *MF = MBB->getParent();
15919 MachineRegisterInfo &MRI = MF->getRegInfo();
15921 const BasicBlock *BB = MBB->getBasicBlock();
15922 MachineFunction::iterator I = MBB;
15925 // Memory Reference
15926 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15927 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15930 unsigned MemOpndSlot = 0;
15932 unsigned CurOp = 0;
15934 DstReg = MI->getOperand(CurOp++).getReg();
15935 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15936 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15937 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15938 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15940 MemOpndSlot = CurOp;
15942 MVT PVT = getPointerTy();
15943 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15944 "Invalid Pointer Size!");
15946 // For v = setjmp(buf), we generate
15949 // buf[LabelOffset] = restoreMBB
15950 // SjLjSetup restoreMBB
15956 // v = phi(main, restore)
15961 MachineBasicBlock *thisMBB = MBB;
15962 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15963 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15964 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15965 MF->insert(I, mainMBB);
15966 MF->insert(I, sinkMBB);
15967 MF->push_back(restoreMBB);
15969 MachineInstrBuilder MIB;
15971 // Transfer the remainder of BB and its successor edges to sinkMBB.
15972 sinkMBB->splice(sinkMBB->begin(), MBB,
15973 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
15974 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15977 unsigned PtrStoreOpc = 0;
15978 unsigned LabelReg = 0;
15979 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15980 Reloc::Model RM = getTargetMachine().getRelocationModel();
15981 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15982 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15984 // Prepare IP either in reg or imm.
15985 if (!UseImmLabel) {
15986 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15987 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15988 LabelReg = MRI.createVirtualRegister(PtrRC);
15989 if (Subtarget->is64Bit()) {
15990 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15994 .addMBB(restoreMBB)
15997 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15998 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15999 .addReg(XII->getGlobalBaseReg(MF))
16002 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
16006 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
16008 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
16009 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16010 if (i == X86::AddrDisp)
16011 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
16013 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
16016 MIB.addReg(LabelReg);
16018 MIB.addMBB(restoreMBB);
16019 MIB.setMemRefs(MMOBegin, MMOEnd);
16021 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
16022 .addMBB(restoreMBB);
16024 const X86RegisterInfo *RegInfo =
16025 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
16026 MIB.addRegMask(RegInfo->getNoPreservedMask());
16027 thisMBB->addSuccessor(mainMBB);
16028 thisMBB->addSuccessor(restoreMBB);
16032 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
16033 mainMBB->addSuccessor(sinkMBB);
16036 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
16037 TII->get(X86::PHI), DstReg)
16038 .addReg(mainDstReg).addMBB(mainMBB)
16039 .addReg(restoreDstReg).addMBB(restoreMBB);
16042 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
16043 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
16044 restoreMBB->addSuccessor(sinkMBB);
16046 MI->eraseFromParent();
16050 MachineBasicBlock *
16051 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
16052 MachineBasicBlock *MBB) const {
16053 DebugLoc DL = MI->getDebugLoc();
16054 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16056 MachineFunction *MF = MBB->getParent();
16057 MachineRegisterInfo &MRI = MF->getRegInfo();
16059 // Memory Reference
16060 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
16061 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
16063 MVT PVT = getPointerTy();
16064 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
16065 "Invalid Pointer Size!");
16067 const TargetRegisterClass *RC =
16068 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
16069 unsigned Tmp = MRI.createVirtualRegister(RC);
16070 // Since FP is only updated here but NOT referenced, it's treated as GPR.
16071 const X86RegisterInfo *RegInfo =
16072 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
16073 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
16074 unsigned SP = RegInfo->getStackRegister();
16076 MachineInstrBuilder MIB;
16078 const int64_t LabelOffset = 1 * PVT.getStoreSize();
16079 const int64_t SPOffset = 2 * PVT.getStoreSize();
16081 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
16082 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
16085 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
16086 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
16087 MIB.addOperand(MI->getOperand(i));
16088 MIB.setMemRefs(MMOBegin, MMOEnd);
16090 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
16091 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16092 if (i == X86::AddrDisp)
16093 MIB.addDisp(MI->getOperand(i), LabelOffset);
16095 MIB.addOperand(MI->getOperand(i));
16097 MIB.setMemRefs(MMOBegin, MMOEnd);
16099 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
16100 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
16101 if (i == X86::AddrDisp)
16102 MIB.addDisp(MI->getOperand(i), SPOffset);
16104 MIB.addOperand(MI->getOperand(i));
16106 MIB.setMemRefs(MMOBegin, MMOEnd);
16108 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
16110 MI->eraseFromParent();
16114 // Replace 213-type (isel default) FMA3 instructions with 231-type for
16115 // accumulator loops. Writing back to the accumulator allows the coalescer
16116 // to remove extra copies in the loop.
16117 MachineBasicBlock *
16118 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
16119 MachineBasicBlock *MBB) const {
16120 MachineOperand &AddendOp = MI->getOperand(3);
16122 // Bail out early if the addend isn't a register - we can't switch these.
16123 if (!AddendOp.isReg())
16126 MachineFunction &MF = *MBB->getParent();
16127 MachineRegisterInfo &MRI = MF.getRegInfo();
16129 // Check whether the addend is defined by a PHI:
16130 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
16131 MachineInstr &AddendDef = *MRI.def_begin(AddendOp.getReg());
16132 if (!AddendDef.isPHI())
16135 // Look for the following pattern:
16137 // %addend = phi [%entry, 0], [%loop, %result]
16139 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
16143 // %addend = phi [%entry, 0], [%loop, %result]
16145 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
16147 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
16148 assert(AddendDef.getOperand(i).isReg());
16149 MachineOperand PHISrcOp = AddendDef.getOperand(i);
16150 MachineInstr &PHISrcInst = *MRI.def_begin(PHISrcOp.getReg());
16151 if (&PHISrcInst == MI) {
16152 // Found a matching instruction.
16153 unsigned NewFMAOpc = 0;
16154 switch (MI->getOpcode()) {
16155 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
16156 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
16157 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
16158 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
16159 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
16160 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
16161 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
16162 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
16163 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
16164 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
16165 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
16166 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
16167 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
16168 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
16169 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
16170 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
16171 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
16172 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
16173 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
16174 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
16175 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
16176 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
16177 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
16178 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
16179 default: llvm_unreachable("Unrecognized FMA variant.");
16182 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
16183 MachineInstrBuilder MIB =
16184 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
16185 .addOperand(MI->getOperand(0))
16186 .addOperand(MI->getOperand(3))
16187 .addOperand(MI->getOperand(2))
16188 .addOperand(MI->getOperand(1));
16189 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
16190 MI->eraseFromParent();
16197 MachineBasicBlock *
16198 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
16199 MachineBasicBlock *BB) const {
16200 switch (MI->getOpcode()) {
16201 default: llvm_unreachable("Unexpected instr type to insert");
16202 case X86::TAILJMPd64:
16203 case X86::TAILJMPr64:
16204 case X86::TAILJMPm64:
16205 llvm_unreachable("TAILJMP64 would not be touched here.");
16206 case X86::TCRETURNdi64:
16207 case X86::TCRETURNri64:
16208 case X86::TCRETURNmi64:
16210 case X86::WIN_ALLOCA:
16211 return EmitLoweredWinAlloca(MI, BB);
16212 case X86::SEG_ALLOCA_32:
16213 return EmitLoweredSegAlloca(MI, BB, false);
16214 case X86::SEG_ALLOCA_64:
16215 return EmitLoweredSegAlloca(MI, BB, true);
16216 case X86::TLSCall_32:
16217 case X86::TLSCall_64:
16218 return EmitLoweredTLSCall(MI, BB);
16219 case X86::CMOV_GR8:
16220 case X86::CMOV_FR32:
16221 case X86::CMOV_FR64:
16222 case X86::CMOV_V4F32:
16223 case X86::CMOV_V2F64:
16224 case X86::CMOV_V2I64:
16225 case X86::CMOV_V8F32:
16226 case X86::CMOV_V4F64:
16227 case X86::CMOV_V4I64:
16228 case X86::CMOV_V16F32:
16229 case X86::CMOV_V8F64:
16230 case X86::CMOV_V8I64:
16231 case X86::CMOV_GR16:
16232 case X86::CMOV_GR32:
16233 case X86::CMOV_RFP32:
16234 case X86::CMOV_RFP64:
16235 case X86::CMOV_RFP80:
16236 return EmitLoweredSelect(MI, BB);
16238 case X86::FP32_TO_INT16_IN_MEM:
16239 case X86::FP32_TO_INT32_IN_MEM:
16240 case X86::FP32_TO_INT64_IN_MEM:
16241 case X86::FP64_TO_INT16_IN_MEM:
16242 case X86::FP64_TO_INT32_IN_MEM:
16243 case X86::FP64_TO_INT64_IN_MEM:
16244 case X86::FP80_TO_INT16_IN_MEM:
16245 case X86::FP80_TO_INT32_IN_MEM:
16246 case X86::FP80_TO_INT64_IN_MEM: {
16247 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16248 DebugLoc DL = MI->getDebugLoc();
16250 // Change the floating point control register to use "round towards zero"
16251 // mode when truncating to an integer value.
16252 MachineFunction *F = BB->getParent();
16253 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
16254 addFrameReference(BuildMI(*BB, MI, DL,
16255 TII->get(X86::FNSTCW16m)), CWFrameIdx);
16257 // Load the old value of the high byte of the control word...
16259 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
16260 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
16263 // Set the high part to be round to zero...
16264 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
16267 // Reload the modified control word now...
16268 addFrameReference(BuildMI(*BB, MI, DL,
16269 TII->get(X86::FLDCW16m)), CWFrameIdx);
16271 // Restore the memory image of control word to original value
16272 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
16275 // Get the X86 opcode to use.
16277 switch (MI->getOpcode()) {
16278 default: llvm_unreachable("illegal opcode!");
16279 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
16280 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
16281 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
16282 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
16283 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
16284 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
16285 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
16286 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
16287 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
16291 MachineOperand &Op = MI->getOperand(0);
16293 AM.BaseType = X86AddressMode::RegBase;
16294 AM.Base.Reg = Op.getReg();
16296 AM.BaseType = X86AddressMode::FrameIndexBase;
16297 AM.Base.FrameIndex = Op.getIndex();
16299 Op = MI->getOperand(1);
16301 AM.Scale = Op.getImm();
16302 Op = MI->getOperand(2);
16304 AM.IndexReg = Op.getImm();
16305 Op = MI->getOperand(3);
16306 if (Op.isGlobal()) {
16307 AM.GV = Op.getGlobal();
16309 AM.Disp = Op.getImm();
16311 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
16312 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
16314 // Reload the original control word now.
16315 addFrameReference(BuildMI(*BB, MI, DL,
16316 TII->get(X86::FLDCW16m)), CWFrameIdx);
16318 MI->eraseFromParent(); // The pseudo instruction is gone now.
16321 // String/text processing lowering.
16322 case X86::PCMPISTRM128REG:
16323 case X86::VPCMPISTRM128REG:
16324 case X86::PCMPISTRM128MEM:
16325 case X86::VPCMPISTRM128MEM:
16326 case X86::PCMPESTRM128REG:
16327 case X86::VPCMPESTRM128REG:
16328 case X86::PCMPESTRM128MEM:
16329 case X86::VPCMPESTRM128MEM:
16330 assert(Subtarget->hasSSE42() &&
16331 "Target must have SSE4.2 or AVX features enabled");
16332 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
16334 // String/text processing lowering.
16335 case X86::PCMPISTRIREG:
16336 case X86::VPCMPISTRIREG:
16337 case X86::PCMPISTRIMEM:
16338 case X86::VPCMPISTRIMEM:
16339 case X86::PCMPESTRIREG:
16340 case X86::VPCMPESTRIREG:
16341 case X86::PCMPESTRIMEM:
16342 case X86::VPCMPESTRIMEM:
16343 assert(Subtarget->hasSSE42() &&
16344 "Target must have SSE4.2 or AVX features enabled");
16345 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
16347 // Thread synchronization.
16349 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
16353 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
16355 // Atomic Lowering.
16356 case X86::ATOMAND8:
16357 case X86::ATOMAND16:
16358 case X86::ATOMAND32:
16359 case X86::ATOMAND64:
16362 case X86::ATOMOR16:
16363 case X86::ATOMOR32:
16364 case X86::ATOMOR64:
16366 case X86::ATOMXOR16:
16367 case X86::ATOMXOR8:
16368 case X86::ATOMXOR32:
16369 case X86::ATOMXOR64:
16371 case X86::ATOMNAND8:
16372 case X86::ATOMNAND16:
16373 case X86::ATOMNAND32:
16374 case X86::ATOMNAND64:
16376 case X86::ATOMMAX8:
16377 case X86::ATOMMAX16:
16378 case X86::ATOMMAX32:
16379 case X86::ATOMMAX64:
16381 case X86::ATOMMIN8:
16382 case X86::ATOMMIN16:
16383 case X86::ATOMMIN32:
16384 case X86::ATOMMIN64:
16386 case X86::ATOMUMAX8:
16387 case X86::ATOMUMAX16:
16388 case X86::ATOMUMAX32:
16389 case X86::ATOMUMAX64:
16391 case X86::ATOMUMIN8:
16392 case X86::ATOMUMIN16:
16393 case X86::ATOMUMIN32:
16394 case X86::ATOMUMIN64:
16395 return EmitAtomicLoadArith(MI, BB);
16397 // This group does 64-bit operations on a 32-bit host.
16398 case X86::ATOMAND6432:
16399 case X86::ATOMOR6432:
16400 case X86::ATOMXOR6432:
16401 case X86::ATOMNAND6432:
16402 case X86::ATOMADD6432:
16403 case X86::ATOMSUB6432:
16404 case X86::ATOMMAX6432:
16405 case X86::ATOMMIN6432:
16406 case X86::ATOMUMAX6432:
16407 case X86::ATOMUMIN6432:
16408 case X86::ATOMSWAP6432:
16409 return EmitAtomicLoadArith6432(MI, BB);
16411 case X86::VASTART_SAVE_XMM_REGS:
16412 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
16414 case X86::VAARG_64:
16415 return EmitVAARG64WithCustomInserter(MI, BB);
16417 case X86::EH_SjLj_SetJmp32:
16418 case X86::EH_SjLj_SetJmp64:
16419 return emitEHSjLjSetJmp(MI, BB);
16421 case X86::EH_SjLj_LongJmp32:
16422 case X86::EH_SjLj_LongJmp64:
16423 return emitEHSjLjLongJmp(MI, BB);
16425 case TargetOpcode::STACKMAP:
16426 case TargetOpcode::PATCHPOINT:
16427 return emitPatchPoint(MI, BB);
16429 case X86::VFMADDPDr213r:
16430 case X86::VFMADDPSr213r:
16431 case X86::VFMADDSDr213r:
16432 case X86::VFMADDSSr213r:
16433 case X86::VFMSUBPDr213r:
16434 case X86::VFMSUBPSr213r:
16435 case X86::VFMSUBSDr213r:
16436 case X86::VFMSUBSSr213r:
16437 case X86::VFNMADDPDr213r:
16438 case X86::VFNMADDPSr213r:
16439 case X86::VFNMADDSDr213r:
16440 case X86::VFNMADDSSr213r:
16441 case X86::VFNMSUBPDr213r:
16442 case X86::VFNMSUBPSr213r:
16443 case X86::VFNMSUBSDr213r:
16444 case X86::VFNMSUBSSr213r:
16445 case X86::VFMADDPDr213rY:
16446 case X86::VFMADDPSr213rY:
16447 case X86::VFMSUBPDr213rY:
16448 case X86::VFMSUBPSr213rY:
16449 case X86::VFNMADDPDr213rY:
16450 case X86::VFNMADDPSr213rY:
16451 case X86::VFNMSUBPDr213rY:
16452 case X86::VFNMSUBPSr213rY:
16453 return emitFMA3Instr(MI, BB);
16457 //===----------------------------------------------------------------------===//
16458 // X86 Optimization Hooks
16459 //===----------------------------------------------------------------------===//
16461 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
16464 const SelectionDAG &DAG,
16465 unsigned Depth) const {
16466 unsigned BitWidth = KnownZero.getBitWidth();
16467 unsigned Opc = Op.getOpcode();
16468 assert((Opc >= ISD::BUILTIN_OP_END ||
16469 Opc == ISD::INTRINSIC_WO_CHAIN ||
16470 Opc == ISD::INTRINSIC_W_CHAIN ||
16471 Opc == ISD::INTRINSIC_VOID) &&
16472 "Should use MaskedValueIsZero if you don't know whether Op"
16473 " is a target node!");
16475 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
16489 // These nodes' second result is a boolean.
16490 if (Op.getResNo() == 0)
16493 case X86ISD::SETCC:
16494 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
16496 case ISD::INTRINSIC_WO_CHAIN: {
16497 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16498 unsigned NumLoBits = 0;
16501 case Intrinsic::x86_sse_movmsk_ps:
16502 case Intrinsic::x86_avx_movmsk_ps_256:
16503 case Intrinsic::x86_sse2_movmsk_pd:
16504 case Intrinsic::x86_avx_movmsk_pd_256:
16505 case Intrinsic::x86_mmx_pmovmskb:
16506 case Intrinsic::x86_sse2_pmovmskb_128:
16507 case Intrinsic::x86_avx2_pmovmskb: {
16508 // High bits of movmskp{s|d}, pmovmskb are known zero.
16510 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16511 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
16512 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
16513 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
16514 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
16515 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
16516 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
16517 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
16519 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16528 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16529 unsigned Depth) const {
16530 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16531 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16532 return Op.getValueType().getScalarType().getSizeInBits();
16538 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16539 /// node is a GlobalAddress + offset.
16540 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16541 const GlobalValue* &GA,
16542 int64_t &Offset) const {
16543 if (N->getOpcode() == X86ISD::Wrapper) {
16544 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16545 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16546 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16550 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16553 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16554 /// same as extracting the high 128-bit part of 256-bit vector and then
16555 /// inserting the result into the low part of a new 256-bit vector
16556 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16557 EVT VT = SVOp->getValueType(0);
16558 unsigned NumElems = VT.getVectorNumElements();
16560 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16561 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16562 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16563 SVOp->getMaskElt(j) >= 0)
16569 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16570 /// same as extracting the low 128-bit part of 256-bit vector and then
16571 /// inserting the result into the high part of a new 256-bit vector
16572 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16573 EVT VT = SVOp->getValueType(0);
16574 unsigned NumElems = VT.getVectorNumElements();
16576 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16577 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16578 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16579 SVOp->getMaskElt(j) >= 0)
16585 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16586 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16587 TargetLowering::DAGCombinerInfo &DCI,
16588 const X86Subtarget* Subtarget) {
16590 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16591 SDValue V1 = SVOp->getOperand(0);
16592 SDValue V2 = SVOp->getOperand(1);
16593 EVT VT = SVOp->getValueType(0);
16594 unsigned NumElems = VT.getVectorNumElements();
16596 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16597 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16601 // V UNDEF BUILD_VECTOR UNDEF
16603 // CONCAT_VECTOR CONCAT_VECTOR
16606 // RESULT: V + zero extended
16608 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16609 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16610 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16613 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16616 // To match the shuffle mask, the first half of the mask should
16617 // be exactly the first vector, and all the rest a splat with the
16618 // first element of the second one.
16619 for (unsigned i = 0; i != NumElems/2; ++i)
16620 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16621 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16624 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16625 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16626 if (Ld->hasNUsesOfValue(1, 0)) {
16627 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16628 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16630 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16631 array_lengthof(Ops),
16633 Ld->getPointerInfo(),
16634 Ld->getAlignment(),
16635 false/*isVolatile*/, true/*ReadMem*/,
16636 false/*WriteMem*/);
16638 // Make sure the newly-created LOAD is in the same position as Ld in
16639 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16640 // and update uses of Ld's output chain to use the TokenFactor.
16641 if (Ld->hasAnyUseOfValue(1)) {
16642 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16643 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16644 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16645 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16646 SDValue(ResNode.getNode(), 1));
16649 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16653 // Emit a zeroed vector and insert the desired subvector on its
16655 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16656 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16657 return DCI.CombineTo(N, InsV);
16660 //===--------------------------------------------------------------------===//
16661 // Combine some shuffles into subvector extracts and inserts:
16664 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16665 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16666 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16667 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16668 return DCI.CombineTo(N, InsV);
16671 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16672 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16673 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16674 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16675 return DCI.CombineTo(N, InsV);
16681 /// PerformShuffleCombine - Performs several different shuffle combines.
16682 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16683 TargetLowering::DAGCombinerInfo &DCI,
16684 const X86Subtarget *Subtarget) {
16686 EVT VT = N->getValueType(0);
16688 // Don't create instructions with illegal types after legalize types has run.
16689 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16690 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16693 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16694 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16695 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16696 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16698 // Only handle 128 wide vector from here on.
16699 if (!VT.is128BitVector())
16702 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16703 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16704 // consecutive, non-overlapping, and in the right order.
16705 SmallVector<SDValue, 16> Elts;
16706 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16707 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16709 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
16712 /// PerformTruncateCombine - Converts truncate operation to
16713 /// a sequence of vector shuffle operations.
16714 /// It is possible when we truncate 256-bit vector to 128-bit vector
16715 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16716 TargetLowering::DAGCombinerInfo &DCI,
16717 const X86Subtarget *Subtarget) {
16721 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16722 /// specific shuffle of a load can be folded into a single element load.
16723 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16724 /// shuffles have been customed lowered so we need to handle those here.
16725 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16726 TargetLowering::DAGCombinerInfo &DCI) {
16727 if (DCI.isBeforeLegalizeOps())
16730 SDValue InVec = N->getOperand(0);
16731 SDValue EltNo = N->getOperand(1);
16733 if (!isa<ConstantSDNode>(EltNo))
16736 EVT VT = InVec.getValueType();
16738 bool HasShuffleIntoBitcast = false;
16739 if (InVec.getOpcode() == ISD::BITCAST) {
16740 // Don't duplicate a load with other uses.
16741 if (!InVec.hasOneUse())
16743 EVT BCVT = InVec.getOperand(0).getValueType();
16744 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16746 InVec = InVec.getOperand(0);
16747 HasShuffleIntoBitcast = true;
16750 if (!isTargetShuffle(InVec.getOpcode()))
16753 // Don't duplicate a load with other uses.
16754 if (!InVec.hasOneUse())
16757 SmallVector<int, 16> ShuffleMask;
16759 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16763 // Select the input vector, guarding against out of range extract vector.
16764 unsigned NumElems = VT.getVectorNumElements();
16765 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16766 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16767 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16768 : InVec.getOperand(1);
16770 // If inputs to shuffle are the same for both ops, then allow 2 uses
16771 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16773 if (LdNode.getOpcode() == ISD::BITCAST) {
16774 // Don't duplicate a load with other uses.
16775 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16778 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16779 LdNode = LdNode.getOperand(0);
16782 if (!ISD::isNormalLoad(LdNode.getNode()))
16785 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16787 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16790 if (HasShuffleIntoBitcast) {
16791 // If there's a bitcast before the shuffle, check if the load type and
16792 // alignment is valid.
16793 unsigned Align = LN0->getAlignment();
16794 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16795 unsigned NewAlign = TLI.getDataLayout()->
16796 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16798 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16802 // All checks match so transform back to vector_shuffle so that DAG combiner
16803 // can finish the job
16806 // Create shuffle node taking into account the case that its a unary shuffle
16807 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16808 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16809 InVec.getOperand(0), Shuffle,
16811 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16812 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16816 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16817 /// generation and convert it from being a bunch of shuffles and extracts
16818 /// to a simple store and scalar loads to extract the elements.
16819 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16820 TargetLowering::DAGCombinerInfo &DCI) {
16821 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16822 if (NewOp.getNode())
16825 SDValue InputVector = N->getOperand(0);
16827 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16828 // from mmx to v2i32 has a single usage.
16829 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16830 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16831 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16832 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16833 N->getValueType(0),
16834 InputVector.getNode()->getOperand(0));
16836 // Only operate on vectors of 4 elements, where the alternative shuffling
16837 // gets to be more expensive.
16838 if (InputVector.getValueType() != MVT::v4i32)
16841 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16842 // single use which is a sign-extend or zero-extend, and all elements are
16844 SmallVector<SDNode *, 4> Uses;
16845 unsigned ExtractedElements = 0;
16846 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16847 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16848 if (UI.getUse().getResNo() != InputVector.getResNo())
16851 SDNode *Extract = *UI;
16852 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16855 if (Extract->getValueType(0) != MVT::i32)
16857 if (!Extract->hasOneUse())
16859 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16860 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16862 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16865 // Record which element was extracted.
16866 ExtractedElements |=
16867 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16869 Uses.push_back(Extract);
16872 // If not all the elements were used, this may not be worthwhile.
16873 if (ExtractedElements != 15)
16876 // Ok, we've now decided to do the transformation.
16877 SDLoc dl(InputVector);
16879 // Store the value to a temporary stack slot.
16880 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16881 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16882 MachinePointerInfo(), false, false, 0);
16884 // Replace each use (extract) with a load of the appropriate element.
16885 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16886 UE = Uses.end(); UI != UE; ++UI) {
16887 SDNode *Extract = *UI;
16889 // cOMpute the element's address.
16890 SDValue Idx = Extract->getOperand(1);
16892 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16893 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16894 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16895 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16897 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16898 StackPtr, OffsetVal);
16900 // Load the scalar.
16901 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16902 ScalarAddr, MachinePointerInfo(),
16903 false, false, false, 0);
16905 // Replace the exact with the load.
16906 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16909 // The replacement was made in place; don't return anything.
16913 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16914 static std::pair<unsigned, bool>
16915 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16916 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16917 if (!VT.isVector())
16918 return std::make_pair(0, false);
16920 bool NeedSplit = false;
16921 switch (VT.getSimpleVT().SimpleTy) {
16922 default: return std::make_pair(0, false);
16926 if (!Subtarget->hasAVX2())
16928 if (!Subtarget->hasAVX())
16929 return std::make_pair(0, false);
16934 if (!Subtarget->hasSSE2())
16935 return std::make_pair(0, false);
16938 // SSE2 has only a small subset of the operations.
16939 bool hasUnsigned = Subtarget->hasSSE41() ||
16940 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16941 bool hasSigned = Subtarget->hasSSE41() ||
16942 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16944 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16947 // Check for x CC y ? x : y.
16948 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16949 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16954 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16957 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16960 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16963 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16965 // Check for x CC y ? y : x -- a min/max with reversed arms.
16966 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16967 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16972 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16975 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16978 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16981 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16985 return std::make_pair(Opc, NeedSplit);
16988 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16990 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16991 TargetLowering::DAGCombinerInfo &DCI,
16992 const X86Subtarget *Subtarget) {
16994 SDValue Cond = N->getOperand(0);
16995 // Get the LHS/RHS of the select.
16996 SDValue LHS = N->getOperand(1);
16997 SDValue RHS = N->getOperand(2);
16998 EVT VT = LHS.getValueType();
16999 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17001 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
17002 // instructions match the semantics of the common C idiom x<y?x:y but not
17003 // x<=y?x:y, because of how they handle negative zero (which can be
17004 // ignored in unsafe-math mode).
17005 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
17006 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
17007 (Subtarget->hasSSE2() ||
17008 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
17009 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17011 unsigned Opcode = 0;
17012 // Check for x CC y ? x : y.
17013 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17014 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17018 // Converting this to a min would handle NaNs incorrectly, and swapping
17019 // the operands would cause it to handle comparisons between positive
17020 // and negative zero incorrectly.
17021 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
17022 if (!DAG.getTarget().Options.UnsafeFPMath &&
17023 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
17025 std::swap(LHS, RHS);
17027 Opcode = X86ISD::FMIN;
17030 // Converting this to a min would handle comparisons between positive
17031 // and negative zero incorrectly.
17032 if (!DAG.getTarget().Options.UnsafeFPMath &&
17033 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
17035 Opcode = X86ISD::FMIN;
17038 // Converting this to a min would handle both negative zeros and NaNs
17039 // incorrectly, but we can swap the operands to fix both.
17040 std::swap(LHS, RHS);
17044 Opcode = X86ISD::FMIN;
17048 // Converting this to a max would handle comparisons between positive
17049 // and negative zero incorrectly.
17050 if (!DAG.getTarget().Options.UnsafeFPMath &&
17051 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
17053 Opcode = X86ISD::FMAX;
17056 // Converting this to a max would handle NaNs incorrectly, and swapping
17057 // the operands would cause it to handle comparisons between positive
17058 // and negative zero incorrectly.
17059 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
17060 if (!DAG.getTarget().Options.UnsafeFPMath &&
17061 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
17063 std::swap(LHS, RHS);
17065 Opcode = X86ISD::FMAX;
17068 // Converting this to a max would handle both negative zeros and NaNs
17069 // incorrectly, but we can swap the operands to fix both.
17070 std::swap(LHS, RHS);
17074 Opcode = X86ISD::FMAX;
17077 // Check for x CC y ? y : x -- a min/max with reversed arms.
17078 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
17079 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
17083 // Converting this to a min would handle comparisons between positive
17084 // and negative zero incorrectly, and swapping the operands would
17085 // cause it to handle NaNs incorrectly.
17086 if (!DAG.getTarget().Options.UnsafeFPMath &&
17087 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
17088 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17090 std::swap(LHS, RHS);
17092 Opcode = X86ISD::FMIN;
17095 // Converting this to a min would handle NaNs incorrectly.
17096 if (!DAG.getTarget().Options.UnsafeFPMath &&
17097 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
17099 Opcode = X86ISD::FMIN;
17102 // Converting this to a min would handle both negative zeros and NaNs
17103 // incorrectly, but we can swap the operands to fix both.
17104 std::swap(LHS, RHS);
17108 Opcode = X86ISD::FMIN;
17112 // Converting this to a max would handle NaNs incorrectly.
17113 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17115 Opcode = X86ISD::FMAX;
17118 // Converting this to a max would handle comparisons between positive
17119 // and negative zero incorrectly, and swapping the operands would
17120 // cause it to handle NaNs incorrectly.
17121 if (!DAG.getTarget().Options.UnsafeFPMath &&
17122 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
17123 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17125 std::swap(LHS, RHS);
17127 Opcode = X86ISD::FMAX;
17130 // Converting this to a max would handle both negative zeros and NaNs
17131 // incorrectly, but we can swap the operands to fix both.
17132 std::swap(LHS, RHS);
17136 Opcode = X86ISD::FMAX;
17142 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
17145 EVT CondVT = Cond.getValueType();
17146 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
17147 CondVT.getVectorElementType() == MVT::i1) {
17148 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
17149 // lowering on AVX-512. In this case we convert it to
17150 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
17151 // The same situation for all 128 and 256-bit vectors of i8 and i16
17152 EVT OpVT = LHS.getValueType();
17153 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
17154 (OpVT.getVectorElementType() == MVT::i8 ||
17155 OpVT.getVectorElementType() == MVT::i16)) {
17156 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
17157 DCI.AddToWorklist(Cond.getNode());
17158 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
17161 // If this is a select between two integer constants, try to do some
17163 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
17164 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
17165 // Don't do this for crazy integer types.
17166 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
17167 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
17168 // so that TrueC (the true value) is larger than FalseC.
17169 bool NeedsCondInvert = false;
17171 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
17172 // Efficiently invertible.
17173 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
17174 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
17175 isa<ConstantSDNode>(Cond.getOperand(1))))) {
17176 NeedsCondInvert = true;
17177 std::swap(TrueC, FalseC);
17180 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
17181 if (FalseC->getAPIntValue() == 0 &&
17182 TrueC->getAPIntValue().isPowerOf2()) {
17183 if (NeedsCondInvert) // Invert the condition if needed.
17184 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17185 DAG.getConstant(1, Cond.getValueType()));
17187 // Zero extend the condition if needed.
17188 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
17190 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17191 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
17192 DAG.getConstant(ShAmt, MVT::i8));
17195 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
17196 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17197 if (NeedsCondInvert) // Invert the condition if needed.
17198 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17199 DAG.getConstant(1, Cond.getValueType()));
17201 // Zero extend the condition if needed.
17202 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17203 FalseC->getValueType(0), Cond);
17204 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17205 SDValue(FalseC, 0));
17208 // Optimize cases that will turn into an LEA instruction. This requires
17209 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17210 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17211 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17212 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17214 bool isFastMultiplier = false;
17216 switch ((unsigned char)Diff) {
17218 case 1: // result = add base, cond
17219 case 2: // result = lea base( , cond*2)
17220 case 3: // result = lea base(cond, cond*2)
17221 case 4: // result = lea base( , cond*4)
17222 case 5: // result = lea base(cond, cond*4)
17223 case 8: // result = lea base( , cond*8)
17224 case 9: // result = lea base(cond, cond*8)
17225 isFastMultiplier = true;
17230 if (isFastMultiplier) {
17231 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17232 if (NeedsCondInvert) // Invert the condition if needed.
17233 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17234 DAG.getConstant(1, Cond.getValueType()));
17236 // Zero extend the condition if needed.
17237 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17239 // Scale the condition by the difference.
17241 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17242 DAG.getConstant(Diff, Cond.getValueType()));
17244 // Add the base if non-zero.
17245 if (FalseC->getAPIntValue() != 0)
17246 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17247 SDValue(FalseC, 0));
17254 // Canonicalize max and min:
17255 // (x > y) ? x : y -> (x >= y) ? x : y
17256 // (x < y) ? x : y -> (x <= y) ? x : y
17257 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
17258 // the need for an extra compare
17259 // against zero. e.g.
17260 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
17262 // testl %edi, %edi
17264 // cmovgl %edi, %eax
17268 // cmovsl %eax, %edi
17269 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
17270 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17271 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17272 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17277 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
17278 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
17279 Cond.getOperand(0), Cond.getOperand(1), NewCC);
17280 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
17285 // Early exit check
17286 if (!TLI.isTypeLegal(VT))
17289 // Match VSELECTs into subs with unsigned saturation.
17290 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17291 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
17292 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
17293 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
17294 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17296 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
17297 // left side invert the predicate to simplify logic below.
17299 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
17301 CC = ISD::getSetCCInverse(CC, true);
17302 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
17306 if (Other.getNode() && Other->getNumOperands() == 2 &&
17307 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
17308 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
17309 SDValue CondRHS = Cond->getOperand(1);
17311 // Look for a general sub with unsigned saturation first.
17312 // x >= y ? x-y : 0 --> subus x, y
17313 // x > y ? x-y : 0 --> subus x, y
17314 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
17315 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
17316 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17318 // If the RHS is a constant we have to reverse the const canonicalization.
17319 // x > C-1 ? x+-C : 0 --> subus x, C
17320 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
17321 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
17322 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17323 if (CondRHS.getConstantOperandVal(0) == -A-1)
17324 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
17325 DAG.getConstant(-A, VT));
17328 // Another special case: If C was a sign bit, the sub has been
17329 // canonicalized into a xor.
17330 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
17331 // it's safe to decanonicalize the xor?
17332 // x s< 0 ? x^C : 0 --> subus x, C
17333 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
17334 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
17335 isSplatVector(OpRHS.getNode())) {
17336 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17338 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17343 // Try to match a min/max vector operation.
17344 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
17345 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
17346 unsigned Opc = ret.first;
17347 bool NeedSplit = ret.second;
17349 if (Opc && NeedSplit) {
17350 unsigned NumElems = VT.getVectorNumElements();
17351 // Extract the LHS vectors
17352 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
17353 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
17355 // Extract the RHS vectors
17356 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
17357 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
17359 // Create min/max for each subvector
17360 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
17361 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
17363 // Merge the result
17364 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
17366 return DAG.getNode(Opc, DL, VT, LHS, RHS);
17369 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
17370 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17371 // Check if SETCC has already been promoted
17372 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
17373 // Check that condition value type matches vselect operand type
17376 assert(Cond.getValueType().isVector() &&
17377 "vector select expects a vector selector!");
17379 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
17380 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
17382 if (!TValIsAllOnes && !FValIsAllZeros) {
17383 // Try invert the condition if true value is not all 1s and false value
17385 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
17386 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
17388 if (TValIsAllZeros || FValIsAllOnes) {
17389 SDValue CC = Cond.getOperand(2);
17390 ISD::CondCode NewCC =
17391 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
17392 Cond.getOperand(0).getValueType().isInteger());
17393 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
17394 std::swap(LHS, RHS);
17395 TValIsAllOnes = FValIsAllOnes;
17396 FValIsAllZeros = TValIsAllZeros;
17400 if (TValIsAllOnes || FValIsAllZeros) {
17403 if (TValIsAllOnes && FValIsAllZeros)
17405 else if (TValIsAllOnes)
17406 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
17407 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
17408 else if (FValIsAllZeros)
17409 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
17410 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
17412 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
17416 // Try to fold this VSELECT into a MOVSS/MOVSD
17417 if (N->getOpcode() == ISD::VSELECT &&
17418 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
17419 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
17420 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
17421 bool CanFold = false;
17422 unsigned NumElems = Cond.getNumOperands();
17426 if (isZero(Cond.getOperand(0))) {
17429 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
17430 // fold (vselect <0,-1> -> (movsd A, B)
17431 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
17432 CanFold = isAllOnes(Cond.getOperand(i));
17433 } else if (isAllOnes(Cond.getOperand(0))) {
17437 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
17438 // fold (vselect <-1,0> -> (movsd B, A)
17439 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
17440 CanFold = isZero(Cond.getOperand(i));
17444 if (VT == MVT::v4i32 || VT == MVT::v4f32)
17445 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
17446 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
17449 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
17450 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
17451 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
17452 // (v2i64 (bitcast B)))))
17454 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
17455 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
17456 // (v2f64 (bitcast B)))))
17458 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
17459 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
17460 // (v2i64 (bitcast A)))))
17462 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
17463 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
17464 // (v2f64 (bitcast A)))))
17466 CanFold = (isZero(Cond.getOperand(0)) &&
17467 isZero(Cond.getOperand(1)) &&
17468 isAllOnes(Cond.getOperand(2)) &&
17469 isAllOnes(Cond.getOperand(3)));
17471 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
17472 isAllOnes(Cond.getOperand(1)) &&
17473 isZero(Cond.getOperand(2)) &&
17474 isZero(Cond.getOperand(3))) {
17476 std::swap(LHS, RHS);
17480 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
17481 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
17482 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
17483 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
17485 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
17491 // If we know that this node is legal then we know that it is going to be
17492 // matched by one of the SSE/AVX BLEND instructions. These instructions only
17493 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
17494 // to simplify previous instructions.
17495 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
17496 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
17497 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
17499 // Don't optimize vector selects that map to mask-registers.
17503 // Check all uses of that condition operand to check whether it will be
17504 // consumed by non-BLEND instructions, which may depend on all bits are set
17506 for (SDNode::use_iterator I = Cond->use_begin(),
17507 E = Cond->use_end(); I != E; ++I)
17508 if (I->getOpcode() != ISD::VSELECT)
17509 // TODO: Add other opcodes eventually lowered into BLEND.
17512 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
17513 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
17515 APInt KnownZero, KnownOne;
17516 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
17517 DCI.isBeforeLegalizeOps());
17518 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
17519 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
17520 DCI.CommitTargetLoweringOpt(TLO);
17526 // Check whether a boolean test is testing a boolean value generated by
17527 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
17530 // Simplify the following patterns:
17531 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
17532 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
17533 // to (Op EFLAGS Cond)
17535 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
17536 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
17537 // to (Op EFLAGS !Cond)
17539 // where Op could be BRCOND or CMOV.
17541 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
17542 // Quit if not CMP and SUB with its value result used.
17543 if (Cmp.getOpcode() != X86ISD::CMP &&
17544 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
17547 // Quit if not used as a boolean value.
17548 if (CC != X86::COND_E && CC != X86::COND_NE)
17551 // Check CMP operands. One of them should be 0 or 1 and the other should be
17552 // an SetCC or extended from it.
17553 SDValue Op1 = Cmp.getOperand(0);
17554 SDValue Op2 = Cmp.getOperand(1);
17557 const ConstantSDNode* C = 0;
17558 bool needOppositeCond = (CC == X86::COND_E);
17559 bool checkAgainstTrue = false; // Is it a comparison against 1?
17561 if ((C = dyn_cast<ConstantSDNode>(Op1)))
17563 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
17565 else // Quit if all operands are not constants.
17568 if (C->getZExtValue() == 1) {
17569 needOppositeCond = !needOppositeCond;
17570 checkAgainstTrue = true;
17571 } else if (C->getZExtValue() != 0)
17572 // Quit if the constant is neither 0 or 1.
17575 bool truncatedToBoolWithAnd = false;
17576 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17577 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17578 SetCC.getOpcode() == ISD::TRUNCATE ||
17579 SetCC.getOpcode() == ISD::AND) {
17580 if (SetCC.getOpcode() == ISD::AND) {
17582 ConstantSDNode *CS;
17583 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17584 CS->getZExtValue() == 1)
17586 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17587 CS->getZExtValue() == 1)
17591 SetCC = SetCC.getOperand(OpIdx);
17592 truncatedToBoolWithAnd = true;
17594 SetCC = SetCC.getOperand(0);
17597 switch (SetCC.getOpcode()) {
17598 case X86ISD::SETCC_CARRY:
17599 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17600 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17601 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17602 // truncated to i1 using 'and'.
17603 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17605 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17606 "Invalid use of SETCC_CARRY!");
17608 case X86ISD::SETCC:
17609 // Set the condition code or opposite one if necessary.
17610 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17611 if (needOppositeCond)
17612 CC = X86::GetOppositeBranchCondition(CC);
17613 return SetCC.getOperand(1);
17614 case X86ISD::CMOV: {
17615 // Check whether false/true value has canonical one, i.e. 0 or 1.
17616 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17617 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17618 // Quit if true value is not a constant.
17621 // Quit if false value is not a constant.
17623 SDValue Op = SetCC.getOperand(0);
17624 // Skip 'zext' or 'trunc' node.
17625 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17626 Op.getOpcode() == ISD::TRUNCATE)
17627 Op = Op.getOperand(0);
17628 // A special case for rdrand/rdseed, where 0 is set if false cond is
17630 if ((Op.getOpcode() != X86ISD::RDRAND &&
17631 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17634 // Quit if false value is not the constant 0 or 1.
17635 bool FValIsFalse = true;
17636 if (FVal && FVal->getZExtValue() != 0) {
17637 if (FVal->getZExtValue() != 1)
17639 // If FVal is 1, opposite cond is needed.
17640 needOppositeCond = !needOppositeCond;
17641 FValIsFalse = false;
17643 // Quit if TVal is not the constant opposite of FVal.
17644 if (FValIsFalse && TVal->getZExtValue() != 1)
17646 if (!FValIsFalse && TVal->getZExtValue() != 0)
17648 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17649 if (needOppositeCond)
17650 CC = X86::GetOppositeBranchCondition(CC);
17651 return SetCC.getOperand(3);
17658 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17659 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17660 TargetLowering::DAGCombinerInfo &DCI,
17661 const X86Subtarget *Subtarget) {
17664 // If the flag operand isn't dead, don't touch this CMOV.
17665 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17668 SDValue FalseOp = N->getOperand(0);
17669 SDValue TrueOp = N->getOperand(1);
17670 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17671 SDValue Cond = N->getOperand(3);
17673 if (CC == X86::COND_E || CC == X86::COND_NE) {
17674 switch (Cond.getOpcode()) {
17678 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17679 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17680 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17686 Flags = checkBoolTestSetCCCombine(Cond, CC);
17687 if (Flags.getNode() &&
17688 // Extra check as FCMOV only supports a subset of X86 cond.
17689 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17690 SDValue Ops[] = { FalseOp, TrueOp,
17691 DAG.getConstant(CC, MVT::i8), Flags };
17692 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17693 Ops, array_lengthof(Ops));
17696 // If this is a select between two integer constants, try to do some
17697 // optimizations. Note that the operands are ordered the opposite of SELECT
17699 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17700 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17701 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17702 // larger than FalseC (the false value).
17703 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17704 CC = X86::GetOppositeBranchCondition(CC);
17705 std::swap(TrueC, FalseC);
17706 std::swap(TrueOp, FalseOp);
17709 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17710 // This is efficient for any integer data type (including i8/i16) and
17712 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17713 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17714 DAG.getConstant(CC, MVT::i8), Cond);
17716 // Zero extend the condition if needed.
17717 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17719 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17720 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17721 DAG.getConstant(ShAmt, MVT::i8));
17722 if (N->getNumValues() == 2) // Dead flag value?
17723 return DCI.CombineTo(N, Cond, SDValue());
17727 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17728 // for any integer data type, including i8/i16.
17729 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17730 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17731 DAG.getConstant(CC, MVT::i8), Cond);
17733 // Zero extend the condition if needed.
17734 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17735 FalseC->getValueType(0), Cond);
17736 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17737 SDValue(FalseC, 0));
17739 if (N->getNumValues() == 2) // Dead flag value?
17740 return DCI.CombineTo(N, Cond, SDValue());
17744 // Optimize cases that will turn into an LEA instruction. This requires
17745 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17746 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17747 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17748 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17750 bool isFastMultiplier = false;
17752 switch ((unsigned char)Diff) {
17754 case 1: // result = add base, cond
17755 case 2: // result = lea base( , cond*2)
17756 case 3: // result = lea base(cond, cond*2)
17757 case 4: // result = lea base( , cond*4)
17758 case 5: // result = lea base(cond, cond*4)
17759 case 8: // result = lea base( , cond*8)
17760 case 9: // result = lea base(cond, cond*8)
17761 isFastMultiplier = true;
17766 if (isFastMultiplier) {
17767 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17768 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17769 DAG.getConstant(CC, MVT::i8), Cond);
17770 // Zero extend the condition if needed.
17771 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17773 // Scale the condition by the difference.
17775 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17776 DAG.getConstant(Diff, Cond.getValueType()));
17778 // Add the base if non-zero.
17779 if (FalseC->getAPIntValue() != 0)
17780 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17781 SDValue(FalseC, 0));
17782 if (N->getNumValues() == 2) // Dead flag value?
17783 return DCI.CombineTo(N, Cond, SDValue());
17790 // Handle these cases:
17791 // (select (x != c), e, c) -> select (x != c), e, x),
17792 // (select (x == c), c, e) -> select (x == c), x, e)
17793 // where the c is an integer constant, and the "select" is the combination
17794 // of CMOV and CMP.
17796 // The rationale for this change is that the conditional-move from a constant
17797 // needs two instructions, however, conditional-move from a register needs
17798 // only one instruction.
17800 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17801 // some instruction-combining opportunities. This opt needs to be
17802 // postponed as late as possible.
17804 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17805 // the DCI.xxxx conditions are provided to postpone the optimization as
17806 // late as possible.
17808 ConstantSDNode *CmpAgainst = 0;
17809 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17810 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17811 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17813 if (CC == X86::COND_NE &&
17814 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17815 CC = X86::GetOppositeBranchCondition(CC);
17816 std::swap(TrueOp, FalseOp);
17819 if (CC == X86::COND_E &&
17820 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17821 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17822 DAG.getConstant(CC, MVT::i8), Cond };
17823 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17824 array_lengthof(Ops));
17832 /// PerformMulCombine - Optimize a single multiply with constant into two
17833 /// in order to implement it with two cheaper instructions, e.g.
17834 /// LEA + SHL, LEA + LEA.
17835 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17836 TargetLowering::DAGCombinerInfo &DCI) {
17837 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17840 EVT VT = N->getValueType(0);
17841 if (VT != MVT::i64)
17844 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17847 uint64_t MulAmt = C->getZExtValue();
17848 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17851 uint64_t MulAmt1 = 0;
17852 uint64_t MulAmt2 = 0;
17853 if ((MulAmt % 9) == 0) {
17855 MulAmt2 = MulAmt / 9;
17856 } else if ((MulAmt % 5) == 0) {
17858 MulAmt2 = MulAmt / 5;
17859 } else if ((MulAmt % 3) == 0) {
17861 MulAmt2 = MulAmt / 3;
17864 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17867 if (isPowerOf2_64(MulAmt2) &&
17868 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17869 // If second multiplifer is pow2, issue it first. We want the multiply by
17870 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17872 std::swap(MulAmt1, MulAmt2);
17875 if (isPowerOf2_64(MulAmt1))
17876 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17877 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17879 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17880 DAG.getConstant(MulAmt1, VT));
17882 if (isPowerOf2_64(MulAmt2))
17883 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17884 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17886 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17887 DAG.getConstant(MulAmt2, VT));
17889 // Do not add new nodes to DAG combiner worklist.
17890 DCI.CombineTo(N, NewMul, false);
17895 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17896 SDValue N0 = N->getOperand(0);
17897 SDValue N1 = N->getOperand(1);
17898 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17899 EVT VT = N0.getValueType();
17901 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17902 // since the result of setcc_c is all zero's or all ones.
17903 if (VT.isInteger() && !VT.isVector() &&
17904 N1C && N0.getOpcode() == ISD::AND &&
17905 N0.getOperand(1).getOpcode() == ISD::Constant) {
17906 SDValue N00 = N0.getOperand(0);
17907 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17908 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17909 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17910 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17911 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17912 APInt ShAmt = N1C->getAPIntValue();
17913 Mask = Mask.shl(ShAmt);
17915 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17916 N00, DAG.getConstant(Mask, VT));
17920 // Hardware support for vector shifts is sparse which makes us scalarize the
17921 // vector operations in many cases. Also, on sandybridge ADD is faster than
17923 // (shl V, 1) -> add V,V
17924 if (isSplatVector(N1.getNode())) {
17925 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17926 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17927 // We shift all of the values by one. In many cases we do not have
17928 // hardware support for this operation. This is better expressed as an ADD
17930 if (N1C && (1 == N1C->getZExtValue())) {
17931 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17938 /// \brief Returns a vector of 0s if the node in input is a vector logical
17939 /// shift by a constant amount which is known to be bigger than or equal
17940 /// to the vector element size in bits.
17941 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17942 const X86Subtarget *Subtarget) {
17943 EVT VT = N->getValueType(0);
17945 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17946 (!Subtarget->hasInt256() ||
17947 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17950 SDValue Amt = N->getOperand(1);
17952 if (isSplatVector(Amt.getNode())) {
17953 SDValue SclrAmt = Amt->getOperand(0);
17954 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17955 APInt ShiftAmt = C->getAPIntValue();
17956 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17958 // SSE2/AVX2 logical shifts always return a vector of 0s
17959 // if the shift amount is bigger than or equal to
17960 // the element size. The constant shift amount will be
17961 // encoded as a 8-bit immediate.
17962 if (ShiftAmt.trunc(8).uge(MaxAmount))
17963 return getZeroVector(VT, Subtarget, DAG, DL);
17970 /// PerformShiftCombine - Combine shifts.
17971 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17972 TargetLowering::DAGCombinerInfo &DCI,
17973 const X86Subtarget *Subtarget) {
17974 if (N->getOpcode() == ISD::SHL) {
17975 SDValue V = PerformSHLCombine(N, DAG);
17976 if (V.getNode()) return V;
17979 if (N->getOpcode() != ISD::SRA) {
17980 // Try to fold this logical shift into a zero vector.
17981 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17982 if (V.getNode()) return V;
17988 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17989 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17990 // and friends. Likewise for OR -> CMPNEQSS.
17991 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17992 TargetLowering::DAGCombinerInfo &DCI,
17993 const X86Subtarget *Subtarget) {
17996 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17997 // we're requiring SSE2 for both.
17998 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17999 SDValue N0 = N->getOperand(0);
18000 SDValue N1 = N->getOperand(1);
18001 SDValue CMP0 = N0->getOperand(1);
18002 SDValue CMP1 = N1->getOperand(1);
18005 // The SETCCs should both refer to the same CMP.
18006 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
18009 SDValue CMP00 = CMP0->getOperand(0);
18010 SDValue CMP01 = CMP0->getOperand(1);
18011 EVT VT = CMP00.getValueType();
18013 if (VT == MVT::f32 || VT == MVT::f64) {
18014 bool ExpectingFlags = false;
18015 // Check for any users that want flags:
18016 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
18017 !ExpectingFlags && UI != UE; ++UI)
18018 switch (UI->getOpcode()) {
18023 ExpectingFlags = true;
18025 case ISD::CopyToReg:
18026 case ISD::SIGN_EXTEND:
18027 case ISD::ZERO_EXTEND:
18028 case ISD::ANY_EXTEND:
18032 if (!ExpectingFlags) {
18033 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
18034 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
18036 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
18037 X86::CondCode tmp = cc0;
18042 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
18043 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
18044 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
18045 // FIXME: need symbolic constants for these magic numbers.
18046 // See X86ATTInstPrinter.cpp:printSSECC().
18047 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
18048 if (Subtarget->hasAVX512()) {
18049 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
18050 CMP01, DAG.getConstant(x86cc, MVT::i8));
18051 if (N->getValueType(0) != MVT::i1)
18052 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
18056 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
18057 CMP00.getValueType(), CMP00, CMP01,
18058 DAG.getConstant(x86cc, MVT::i8));
18059 MVT IntVT = (is64BitFP ? MVT::i64 : MVT::i32);
18060 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
18062 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
18063 DAG.getConstant(1, IntVT));
18064 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
18065 return OneBitOfTruth;
18073 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
18074 /// so it can be folded inside ANDNP.
18075 static bool CanFoldXORWithAllOnes(const SDNode *N) {
18076 EVT VT = N->getValueType(0);
18078 // Match direct AllOnes for 128 and 256-bit vectors
18079 if (ISD::isBuildVectorAllOnes(N))
18082 // Look through a bit convert.
18083 if (N->getOpcode() == ISD::BITCAST)
18084 N = N->getOperand(0).getNode();
18086 // Sometimes the operand may come from a insert_subvector building a 256-bit
18088 if (VT.is256BitVector() &&
18089 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
18090 SDValue V1 = N->getOperand(0);
18091 SDValue V2 = N->getOperand(1);
18093 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
18094 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
18095 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
18096 ISD::isBuildVectorAllOnes(V2.getNode()))
18103 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
18104 // register. In most cases we actually compare or select YMM-sized registers
18105 // and mixing the two types creates horrible code. This method optimizes
18106 // some of the transition sequences.
18107 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
18108 TargetLowering::DAGCombinerInfo &DCI,
18109 const X86Subtarget *Subtarget) {
18110 EVT VT = N->getValueType(0);
18111 if (!VT.is256BitVector())
18114 assert((N->getOpcode() == ISD::ANY_EXTEND ||
18115 N->getOpcode() == ISD::ZERO_EXTEND ||
18116 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
18118 SDValue Narrow = N->getOperand(0);
18119 EVT NarrowVT = Narrow->getValueType(0);
18120 if (!NarrowVT.is128BitVector())
18123 if (Narrow->getOpcode() != ISD::XOR &&
18124 Narrow->getOpcode() != ISD::AND &&
18125 Narrow->getOpcode() != ISD::OR)
18128 SDValue N0 = Narrow->getOperand(0);
18129 SDValue N1 = Narrow->getOperand(1);
18132 // The Left side has to be a trunc.
18133 if (N0.getOpcode() != ISD::TRUNCATE)
18136 // The type of the truncated inputs.
18137 EVT WideVT = N0->getOperand(0)->getValueType(0);
18141 // The right side has to be a 'trunc' or a constant vector.
18142 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
18143 bool RHSConst = (isSplatVector(N1.getNode()) &&
18144 isa<ConstantSDNode>(N1->getOperand(0)));
18145 if (!RHSTrunc && !RHSConst)
18148 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18150 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
18153 // Set N0 and N1 to hold the inputs to the new wide operation.
18154 N0 = N0->getOperand(0);
18156 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
18157 N1->getOperand(0));
18158 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
18159 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
18160 } else if (RHSTrunc) {
18161 N1 = N1->getOperand(0);
18164 // Generate the wide operation.
18165 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
18166 unsigned Opcode = N->getOpcode();
18168 case ISD::ANY_EXTEND:
18170 case ISD::ZERO_EXTEND: {
18171 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
18172 APInt Mask = APInt::getAllOnesValue(InBits);
18173 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
18174 return DAG.getNode(ISD::AND, DL, VT,
18175 Op, DAG.getConstant(Mask, VT));
18177 case ISD::SIGN_EXTEND:
18178 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
18179 Op, DAG.getValueType(NarrowVT));
18181 llvm_unreachable("Unexpected opcode");
18185 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
18186 TargetLowering::DAGCombinerInfo &DCI,
18187 const X86Subtarget *Subtarget) {
18188 EVT VT = N->getValueType(0);
18189 if (DCI.isBeforeLegalizeOps())
18192 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
18196 // Create BEXTR and BZHI instructions
18197 // BZHI is X & ((1 << Y) - 1)
18198 // BEXTR is ((X >> imm) & (2**size-1))
18199 if (VT == MVT::i32 || VT == MVT::i64) {
18200 SDValue N0 = N->getOperand(0);
18201 SDValue N1 = N->getOperand(1);
18204 if (Subtarget->hasBMI2()) {
18205 // Check for (and (add (shl 1, Y), -1), X)
18206 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
18207 SDValue N00 = N0.getOperand(0);
18208 if (N00.getOpcode() == ISD::SHL) {
18209 SDValue N001 = N00.getOperand(1);
18210 assert(N001.getValueType() == MVT::i8 && "unexpected type");
18211 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
18212 if (C && C->getZExtValue() == 1)
18213 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
18217 // Check for (and X, (add (shl 1, Y), -1))
18218 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
18219 SDValue N10 = N1.getOperand(0);
18220 if (N10.getOpcode() == ISD::SHL) {
18221 SDValue N101 = N10.getOperand(1);
18222 assert(N101.getValueType() == MVT::i8 && "unexpected type");
18223 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
18224 if (C && C->getZExtValue() == 1)
18225 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
18230 // Check for BEXTR.
18231 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
18232 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
18233 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
18234 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18235 if (MaskNode && ShiftNode) {
18236 uint64_t Mask = MaskNode->getZExtValue();
18237 uint64_t Shift = ShiftNode->getZExtValue();
18238 if (isMask_64(Mask)) {
18239 uint64_t MaskSize = CountPopulation_64(Mask);
18240 if (Shift + MaskSize <= VT.getSizeInBits())
18241 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
18242 DAG.getConstant(Shift | (MaskSize << 8), VT));
18250 // Want to form ANDNP nodes:
18251 // 1) In the hopes of then easily combining them with OR and AND nodes
18252 // to form PBLEND/PSIGN.
18253 // 2) To match ANDN packed intrinsics
18254 if (VT != MVT::v2i64 && VT != MVT::v4i64)
18257 SDValue N0 = N->getOperand(0);
18258 SDValue N1 = N->getOperand(1);
18261 // Check LHS for vnot
18262 if (N0.getOpcode() == ISD::XOR &&
18263 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
18264 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
18265 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
18267 // Check RHS for vnot
18268 if (N1.getOpcode() == ISD::XOR &&
18269 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
18270 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
18271 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
18276 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
18277 TargetLowering::DAGCombinerInfo &DCI,
18278 const X86Subtarget *Subtarget) {
18279 if (DCI.isBeforeLegalizeOps())
18282 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
18286 SDValue N0 = N->getOperand(0);
18287 SDValue N1 = N->getOperand(1);
18288 EVT VT = N->getValueType(0);
18290 // look for psign/blend
18291 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
18292 if (!Subtarget->hasSSSE3() ||
18293 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
18296 // Canonicalize pandn to RHS
18297 if (N0.getOpcode() == X86ISD::ANDNP)
18299 // or (and (m, y), (pandn m, x))
18300 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
18301 SDValue Mask = N1.getOperand(0);
18302 SDValue X = N1.getOperand(1);
18304 if (N0.getOperand(0) == Mask)
18305 Y = N0.getOperand(1);
18306 if (N0.getOperand(1) == Mask)
18307 Y = N0.getOperand(0);
18309 // Check to see if the mask appeared in both the AND and ANDNP and
18313 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
18314 // Look through mask bitcast.
18315 if (Mask.getOpcode() == ISD::BITCAST)
18316 Mask = Mask.getOperand(0);
18317 if (X.getOpcode() == ISD::BITCAST)
18318 X = X.getOperand(0);
18319 if (Y.getOpcode() == ISD::BITCAST)
18320 Y = Y.getOperand(0);
18322 EVT MaskVT = Mask.getValueType();
18324 // Validate that the Mask operand is a vector sra node.
18325 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
18326 // there is no psrai.b
18327 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
18328 unsigned SraAmt = ~0;
18329 if (Mask.getOpcode() == ISD::SRA) {
18330 SDValue Amt = Mask.getOperand(1);
18331 if (isSplatVector(Amt.getNode())) {
18332 SDValue SclrAmt = Amt->getOperand(0);
18333 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
18334 SraAmt = C->getZExtValue();
18336 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
18337 SDValue SraC = Mask.getOperand(1);
18338 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
18340 if ((SraAmt + 1) != EltBits)
18345 // Now we know we at least have a plendvb with the mask val. See if
18346 // we can form a psignb/w/d.
18347 // psign = x.type == y.type == mask.type && y = sub(0, x);
18348 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
18349 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
18350 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
18351 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
18352 "Unsupported VT for PSIGN");
18353 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
18354 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18356 // PBLENDVB only available on SSE 4.1
18357 if (!Subtarget->hasSSE41())
18360 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
18362 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
18363 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
18364 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
18365 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
18366 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18370 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
18373 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
18374 MachineFunction &MF = DAG.getMachineFunction();
18375 bool OptForSize = MF.getFunction()->getAttributes().
18376 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
18378 // SHLD/SHRD instructions have lower register pressure, but on some
18379 // platforms they have higher latency than the equivalent
18380 // series of shifts/or that would otherwise be generated.
18381 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
18382 // have higher latencies and we are not optimizing for size.
18383 if (!OptForSize && Subtarget->isSHLDSlow())
18386 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
18388 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
18390 if (!N0.hasOneUse() || !N1.hasOneUse())
18393 SDValue ShAmt0 = N0.getOperand(1);
18394 if (ShAmt0.getValueType() != MVT::i8)
18396 SDValue ShAmt1 = N1.getOperand(1);
18397 if (ShAmt1.getValueType() != MVT::i8)
18399 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
18400 ShAmt0 = ShAmt0.getOperand(0);
18401 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
18402 ShAmt1 = ShAmt1.getOperand(0);
18405 unsigned Opc = X86ISD::SHLD;
18406 SDValue Op0 = N0.getOperand(0);
18407 SDValue Op1 = N1.getOperand(0);
18408 if (ShAmt0.getOpcode() == ISD::SUB) {
18409 Opc = X86ISD::SHRD;
18410 std::swap(Op0, Op1);
18411 std::swap(ShAmt0, ShAmt1);
18414 unsigned Bits = VT.getSizeInBits();
18415 if (ShAmt1.getOpcode() == ISD::SUB) {
18416 SDValue Sum = ShAmt1.getOperand(0);
18417 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
18418 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
18419 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
18420 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
18421 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
18422 return DAG.getNode(Opc, DL, VT,
18424 DAG.getNode(ISD::TRUNCATE, DL,
18427 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
18428 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
18430 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
18431 return DAG.getNode(Opc, DL, VT,
18432 N0.getOperand(0), N1.getOperand(0),
18433 DAG.getNode(ISD::TRUNCATE, DL,
18440 // Generate NEG and CMOV for integer abs.
18441 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
18442 EVT VT = N->getValueType(0);
18444 // Since X86 does not have CMOV for 8-bit integer, we don't convert
18445 // 8-bit integer abs to NEG and CMOV.
18446 if (VT.isInteger() && VT.getSizeInBits() == 8)
18449 SDValue N0 = N->getOperand(0);
18450 SDValue N1 = N->getOperand(1);
18453 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
18454 // and change it to SUB and CMOV.
18455 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
18456 N0.getOpcode() == ISD::ADD &&
18457 N0.getOperand(1) == N1 &&
18458 N1.getOpcode() == ISD::SRA &&
18459 N1.getOperand(0) == N0.getOperand(0))
18460 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
18461 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
18462 // Generate SUB & CMOV.
18463 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
18464 DAG.getConstant(0, VT), N0.getOperand(0));
18466 SDValue Ops[] = { N0.getOperand(0), Neg,
18467 DAG.getConstant(X86::COND_GE, MVT::i8),
18468 SDValue(Neg.getNode(), 1) };
18469 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
18470 Ops, array_lengthof(Ops));
18475 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
18476 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
18477 TargetLowering::DAGCombinerInfo &DCI,
18478 const X86Subtarget *Subtarget) {
18479 if (DCI.isBeforeLegalizeOps())
18482 if (Subtarget->hasCMov()) {
18483 SDValue RV = performIntegerAbsCombine(N, DAG);
18491 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
18492 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
18493 TargetLowering::DAGCombinerInfo &DCI,
18494 const X86Subtarget *Subtarget) {
18495 LoadSDNode *Ld = cast<LoadSDNode>(N);
18496 EVT RegVT = Ld->getValueType(0);
18497 EVT MemVT = Ld->getMemoryVT();
18499 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18500 unsigned RegSz = RegVT.getSizeInBits();
18502 // On Sandybridge unaligned 256bit loads are inefficient.
18503 ISD::LoadExtType Ext = Ld->getExtensionType();
18504 unsigned Alignment = Ld->getAlignment();
18505 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
18506 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
18507 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
18508 unsigned NumElems = RegVT.getVectorNumElements();
18512 SDValue Ptr = Ld->getBasePtr();
18513 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
18515 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18517 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18518 Ld->getPointerInfo(), Ld->isVolatile(),
18519 Ld->isNonTemporal(), Ld->isInvariant(),
18521 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18522 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18523 Ld->getPointerInfo(), Ld->isVolatile(),
18524 Ld->isNonTemporal(), Ld->isInvariant(),
18525 std::min(16U, Alignment));
18526 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18528 Load2.getValue(1));
18530 SDValue NewVec = DAG.getUNDEF(RegVT);
18531 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
18532 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
18533 return DCI.CombineTo(N, NewVec, TF, true);
18536 // If this is a vector EXT Load then attempt to optimize it using a
18537 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
18538 // expansion is still better than scalar code.
18539 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
18540 // emit a shuffle and a arithmetic shift.
18541 // TODO: It is possible to support ZExt by zeroing the undef values
18542 // during the shuffle phase or after the shuffle.
18543 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18544 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18545 assert(MemVT != RegVT && "Cannot extend to the same type");
18546 assert(MemVT.isVector() && "Must load a vector from memory");
18548 unsigned NumElems = RegVT.getVectorNumElements();
18549 unsigned MemSz = MemVT.getSizeInBits();
18550 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18552 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18555 // All sizes must be a power of two.
18556 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18559 // Attempt to load the original value using scalar loads.
18560 // Find the largest scalar type that divides the total loaded size.
18561 MVT SclrLoadTy = MVT::i8;
18562 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18563 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18564 MVT Tp = (MVT::SimpleValueType)tp;
18565 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18570 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18571 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18573 SclrLoadTy = MVT::f64;
18575 // Calculate the number of scalar loads that we need to perform
18576 // in order to load our vector from memory.
18577 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18578 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18581 unsigned loadRegZize = RegSz;
18582 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18585 // Represent our vector as a sequence of elements which are the
18586 // largest scalar that we can load.
18587 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18588 loadRegZize/SclrLoadTy.getSizeInBits());
18590 // Represent the data using the same element type that is stored in
18591 // memory. In practice, we ''widen'' MemVT.
18593 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18594 loadRegZize/MemVT.getScalarType().getSizeInBits());
18596 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18597 "Invalid vector type");
18599 // We can't shuffle using an illegal type.
18600 if (!TLI.isTypeLegal(WideVecVT))
18603 SmallVector<SDValue, 8> Chains;
18604 SDValue Ptr = Ld->getBasePtr();
18605 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18606 TLI.getPointerTy());
18607 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18609 for (unsigned i = 0; i < NumLoads; ++i) {
18610 // Perform a single load.
18611 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18612 Ptr, Ld->getPointerInfo(),
18613 Ld->isVolatile(), Ld->isNonTemporal(),
18614 Ld->isInvariant(), Ld->getAlignment());
18615 Chains.push_back(ScalarLoad.getValue(1));
18616 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18617 // another round of DAGCombining.
18619 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18621 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18622 ScalarLoad, DAG.getIntPtrConstant(i));
18624 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18627 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18630 // Bitcast the loaded value to a vector of the original element type, in
18631 // the size of the target vector type.
18632 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18633 unsigned SizeRatio = RegSz/MemSz;
18635 if (Ext == ISD::SEXTLOAD) {
18636 // If we have SSE4.1 we can directly emit a VSEXT node.
18637 if (Subtarget->hasSSE41()) {
18638 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18639 return DCI.CombineTo(N, Sext, TF, true);
18642 // Otherwise we'll shuffle the small elements in the high bits of the
18643 // larger type and perform an arithmetic shift. If the shift is not legal
18644 // it's better to scalarize.
18645 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18648 // Redistribute the loaded elements into the different locations.
18649 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18650 for (unsigned i = 0; i != NumElems; ++i)
18651 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18653 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18654 DAG.getUNDEF(WideVecVT),
18657 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18659 // Build the arithmetic shift.
18660 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18661 MemVT.getVectorElementType().getSizeInBits();
18662 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18663 DAG.getConstant(Amt, RegVT));
18665 return DCI.CombineTo(N, Shuff, TF, true);
18668 // Redistribute the loaded elements into the different locations.
18669 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18670 for (unsigned i = 0; i != NumElems; ++i)
18671 ShuffleVec[i*SizeRatio] = i;
18673 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18674 DAG.getUNDEF(WideVecVT),
18677 // Bitcast to the requested type.
18678 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18679 // Replace the original load with the new sequence
18680 // and return the new chain.
18681 return DCI.CombineTo(N, Shuff, TF, true);
18687 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18688 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18689 const X86Subtarget *Subtarget) {
18690 StoreSDNode *St = cast<StoreSDNode>(N);
18691 EVT VT = St->getValue().getValueType();
18692 EVT StVT = St->getMemoryVT();
18694 SDValue StoredVal = St->getOperand(1);
18695 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18697 // If we are saving a concatenation of two XMM registers, perform two stores.
18698 // On Sandy Bridge, 256-bit memory operations are executed by two
18699 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18700 // memory operation.
18701 unsigned Alignment = St->getAlignment();
18702 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18703 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18704 StVT == VT && !IsAligned) {
18705 unsigned NumElems = VT.getVectorNumElements();
18709 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18710 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18712 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18713 SDValue Ptr0 = St->getBasePtr();
18714 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18716 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18717 St->getPointerInfo(), St->isVolatile(),
18718 St->isNonTemporal(), Alignment);
18719 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18720 St->getPointerInfo(), St->isVolatile(),
18721 St->isNonTemporal(),
18722 std::min(16U, Alignment));
18723 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18726 // Optimize trunc store (of multiple scalars) to shuffle and store.
18727 // First, pack all of the elements in one place. Next, store to memory
18728 // in fewer chunks.
18729 if (St->isTruncatingStore() && VT.isVector()) {
18730 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18731 unsigned NumElems = VT.getVectorNumElements();
18732 assert(StVT != VT && "Cannot truncate to the same type");
18733 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18734 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18736 // From, To sizes and ElemCount must be pow of two
18737 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18738 // We are going to use the original vector elt for storing.
18739 // Accumulated smaller vector elements must be a multiple of the store size.
18740 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18742 unsigned SizeRatio = FromSz / ToSz;
18744 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18746 // Create a type on which we perform the shuffle
18747 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18748 StVT.getScalarType(), NumElems*SizeRatio);
18750 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18752 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18753 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18754 for (unsigned i = 0; i != NumElems; ++i)
18755 ShuffleVec[i] = i * SizeRatio;
18757 // Can't shuffle using an illegal type.
18758 if (!TLI.isTypeLegal(WideVecVT))
18761 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18762 DAG.getUNDEF(WideVecVT),
18764 // At this point all of the data is stored at the bottom of the
18765 // register. We now need to save it to mem.
18767 // Find the largest store unit
18768 MVT StoreType = MVT::i8;
18769 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18770 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18771 MVT Tp = (MVT::SimpleValueType)tp;
18772 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18776 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18777 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18778 (64 <= NumElems * ToSz))
18779 StoreType = MVT::f64;
18781 // Bitcast the original vector into a vector of store-size units
18782 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18783 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18784 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18785 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18786 SmallVector<SDValue, 8> Chains;
18787 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18788 TLI.getPointerTy());
18789 SDValue Ptr = St->getBasePtr();
18791 // Perform one or more big stores into memory.
18792 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18793 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18794 StoreType, ShuffWide,
18795 DAG.getIntPtrConstant(i));
18796 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18797 St->getPointerInfo(), St->isVolatile(),
18798 St->isNonTemporal(), St->getAlignment());
18799 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18800 Chains.push_back(Ch);
18803 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18807 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18808 // the FP state in cases where an emms may be missing.
18809 // A preferable solution to the general problem is to figure out the right
18810 // places to insert EMMS. This qualifies as a quick hack.
18812 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18813 if (VT.getSizeInBits() != 64)
18816 const Function *F = DAG.getMachineFunction().getFunction();
18817 bool NoImplicitFloatOps = F->getAttributes().
18818 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18819 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18820 && Subtarget->hasSSE2();
18821 if ((VT.isVector() ||
18822 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18823 isa<LoadSDNode>(St->getValue()) &&
18824 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18825 St->getChain().hasOneUse() && !St->isVolatile()) {
18826 SDNode* LdVal = St->getValue().getNode();
18827 LoadSDNode *Ld = 0;
18828 int TokenFactorIndex = -1;
18829 SmallVector<SDValue, 8> Ops;
18830 SDNode* ChainVal = St->getChain().getNode();
18831 // Must be a store of a load. We currently handle two cases: the load
18832 // is a direct child, and it's under an intervening TokenFactor. It is
18833 // possible to dig deeper under nested TokenFactors.
18834 if (ChainVal == LdVal)
18835 Ld = cast<LoadSDNode>(St->getChain());
18836 else if (St->getValue().hasOneUse() &&
18837 ChainVal->getOpcode() == ISD::TokenFactor) {
18838 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18839 if (ChainVal->getOperand(i).getNode() == LdVal) {
18840 TokenFactorIndex = i;
18841 Ld = cast<LoadSDNode>(St->getValue());
18843 Ops.push_back(ChainVal->getOperand(i));
18847 if (!Ld || !ISD::isNormalLoad(Ld))
18850 // If this is not the MMX case, i.e. we are just turning i64 load/store
18851 // into f64 load/store, avoid the transformation if there are multiple
18852 // uses of the loaded value.
18853 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18858 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18859 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18861 if (Subtarget->is64Bit() || F64IsLegal) {
18862 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18863 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18864 Ld->getPointerInfo(), Ld->isVolatile(),
18865 Ld->isNonTemporal(), Ld->isInvariant(),
18866 Ld->getAlignment());
18867 SDValue NewChain = NewLd.getValue(1);
18868 if (TokenFactorIndex != -1) {
18869 Ops.push_back(NewChain);
18870 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18873 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18874 St->getPointerInfo(),
18875 St->isVolatile(), St->isNonTemporal(),
18876 St->getAlignment());
18879 // Otherwise, lower to two pairs of 32-bit loads / stores.
18880 SDValue LoAddr = Ld->getBasePtr();
18881 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18882 DAG.getConstant(4, MVT::i32));
18884 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18885 Ld->getPointerInfo(),
18886 Ld->isVolatile(), Ld->isNonTemporal(),
18887 Ld->isInvariant(), Ld->getAlignment());
18888 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18889 Ld->getPointerInfo().getWithOffset(4),
18890 Ld->isVolatile(), Ld->isNonTemporal(),
18892 MinAlign(Ld->getAlignment(), 4));
18894 SDValue NewChain = LoLd.getValue(1);
18895 if (TokenFactorIndex != -1) {
18896 Ops.push_back(LoLd);
18897 Ops.push_back(HiLd);
18898 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18902 LoAddr = St->getBasePtr();
18903 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18904 DAG.getConstant(4, MVT::i32));
18906 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18907 St->getPointerInfo(),
18908 St->isVolatile(), St->isNonTemporal(),
18909 St->getAlignment());
18910 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18911 St->getPointerInfo().getWithOffset(4),
18913 St->isNonTemporal(),
18914 MinAlign(St->getAlignment(), 4));
18915 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18920 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18921 /// and return the operands for the horizontal operation in LHS and RHS. A
18922 /// horizontal operation performs the binary operation on successive elements
18923 /// of its first operand, then on successive elements of its second operand,
18924 /// returning the resulting values in a vector. For example, if
18925 /// A = < float a0, float a1, float a2, float a3 >
18927 /// B = < float b0, float b1, float b2, float b3 >
18928 /// then the result of doing a horizontal operation on A and B is
18929 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18930 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18931 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18932 /// set to A, RHS to B, and the routine returns 'true'.
18933 /// Note that the binary operation should have the property that if one of the
18934 /// operands is UNDEF then the result is UNDEF.
18935 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18936 // Look for the following pattern: if
18937 // A = < float a0, float a1, float a2, float a3 >
18938 // B = < float b0, float b1, float b2, float b3 >
18940 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18941 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18942 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18943 // which is A horizontal-op B.
18945 // At least one of the operands should be a vector shuffle.
18946 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18947 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18950 MVT VT = LHS.getSimpleValueType();
18952 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18953 "Unsupported vector type for horizontal add/sub");
18955 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18956 // operate independently on 128-bit lanes.
18957 unsigned NumElts = VT.getVectorNumElements();
18958 unsigned NumLanes = VT.getSizeInBits()/128;
18959 unsigned NumLaneElts = NumElts / NumLanes;
18960 assert((NumLaneElts % 2 == 0) &&
18961 "Vector type should have an even number of elements in each lane");
18962 unsigned HalfLaneElts = NumLaneElts/2;
18964 // View LHS in the form
18965 // LHS = VECTOR_SHUFFLE A, B, LMask
18966 // If LHS is not a shuffle then pretend it is the shuffle
18967 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18968 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18971 SmallVector<int, 16> LMask(NumElts);
18972 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18973 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18974 A = LHS.getOperand(0);
18975 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18976 B = LHS.getOperand(1);
18977 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18978 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18980 if (LHS.getOpcode() != ISD::UNDEF)
18982 for (unsigned i = 0; i != NumElts; ++i)
18986 // Likewise, view RHS in the form
18987 // RHS = VECTOR_SHUFFLE C, D, RMask
18989 SmallVector<int, 16> RMask(NumElts);
18990 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18991 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18992 C = RHS.getOperand(0);
18993 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18994 D = RHS.getOperand(1);
18995 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18996 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18998 if (RHS.getOpcode() != ISD::UNDEF)
19000 for (unsigned i = 0; i != NumElts; ++i)
19004 // Check that the shuffles are both shuffling the same vectors.
19005 if (!(A == C && B == D) && !(A == D && B == C))
19008 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
19009 if (!A.getNode() && !B.getNode())
19012 // If A and B occur in reverse order in RHS, then "swap" them (which means
19013 // rewriting the mask).
19015 CommuteVectorShuffleMask(RMask, NumElts);
19017 // At this point LHS and RHS are equivalent to
19018 // LHS = VECTOR_SHUFFLE A, B, LMask
19019 // RHS = VECTOR_SHUFFLE A, B, RMask
19020 // Check that the masks correspond to performing a horizontal operation.
19021 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
19022 for (unsigned i = 0; i != NumLaneElts; ++i) {
19023 int LIdx = LMask[i+l], RIdx = RMask[i+l];
19025 // Ignore any UNDEF components.
19026 if (LIdx < 0 || RIdx < 0 ||
19027 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
19028 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
19031 // Check that successive elements are being operated on. If not, this is
19032 // not a horizontal operation.
19033 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
19034 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
19035 if (!(LIdx == Index && RIdx == Index + 1) &&
19036 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
19041 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
19042 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
19046 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
19047 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
19048 const X86Subtarget *Subtarget) {
19049 EVT VT = N->getValueType(0);
19050 SDValue LHS = N->getOperand(0);
19051 SDValue RHS = N->getOperand(1);
19053 // Try to synthesize horizontal adds from adds of shuffles.
19054 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
19055 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
19056 isHorizontalBinOp(LHS, RHS, true))
19057 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
19061 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
19062 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
19063 const X86Subtarget *Subtarget) {
19064 EVT VT = N->getValueType(0);
19065 SDValue LHS = N->getOperand(0);
19066 SDValue RHS = N->getOperand(1);
19068 // Try to synthesize horizontal subs from subs of shuffles.
19069 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
19070 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
19071 isHorizontalBinOp(LHS, RHS, false))
19072 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
19076 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
19077 /// X86ISD::FXOR nodes.
19078 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
19079 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
19080 // F[X]OR(0.0, x) -> x
19081 // F[X]OR(x, 0.0) -> x
19082 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
19083 if (C->getValueAPF().isPosZero())
19084 return N->getOperand(1);
19085 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
19086 if (C->getValueAPF().isPosZero())
19087 return N->getOperand(0);
19091 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
19092 /// X86ISD::FMAX nodes.
19093 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
19094 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
19096 // Only perform optimizations if UnsafeMath is used.
19097 if (!DAG.getTarget().Options.UnsafeFPMath)
19100 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
19101 // into FMINC and FMAXC, which are Commutative operations.
19102 unsigned NewOp = 0;
19103 switch (N->getOpcode()) {
19104 default: llvm_unreachable("unknown opcode");
19105 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
19106 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
19109 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
19110 N->getOperand(0), N->getOperand(1));
19113 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
19114 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
19115 // FAND(0.0, x) -> 0.0
19116 // FAND(x, 0.0) -> 0.0
19117 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
19118 if (C->getValueAPF().isPosZero())
19119 return N->getOperand(0);
19120 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
19121 if (C->getValueAPF().isPosZero())
19122 return N->getOperand(1);
19126 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
19127 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
19128 // FANDN(x, 0.0) -> 0.0
19129 // FANDN(0.0, x) -> x
19130 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
19131 if (C->getValueAPF().isPosZero())
19132 return N->getOperand(1);
19133 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
19134 if (C->getValueAPF().isPosZero())
19135 return N->getOperand(1);
19139 static SDValue PerformBTCombine(SDNode *N,
19141 TargetLowering::DAGCombinerInfo &DCI) {
19142 // BT ignores high bits in the bit index operand.
19143 SDValue Op1 = N->getOperand(1);
19144 if (Op1.hasOneUse()) {
19145 unsigned BitWidth = Op1.getValueSizeInBits();
19146 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
19147 APInt KnownZero, KnownOne;
19148 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
19149 !DCI.isBeforeLegalizeOps());
19150 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19151 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
19152 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
19153 DCI.CommitTargetLoweringOpt(TLO);
19158 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
19159 SDValue Op = N->getOperand(0);
19160 if (Op.getOpcode() == ISD::BITCAST)
19161 Op = Op.getOperand(0);
19162 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
19163 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
19164 VT.getVectorElementType().getSizeInBits() ==
19165 OpVT.getVectorElementType().getSizeInBits()) {
19166 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
19171 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
19172 const X86Subtarget *Subtarget) {
19173 EVT VT = N->getValueType(0);
19174 if (!VT.isVector())
19177 SDValue N0 = N->getOperand(0);
19178 SDValue N1 = N->getOperand(1);
19179 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
19182 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
19183 // both SSE and AVX2 since there is no sign-extended shift right
19184 // operation on a vector with 64-bit elements.
19185 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
19186 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
19187 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
19188 N0.getOpcode() == ISD::SIGN_EXTEND)) {
19189 SDValue N00 = N0.getOperand(0);
19191 // EXTLOAD has a better solution on AVX2,
19192 // it may be replaced with X86ISD::VSEXT node.
19193 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
19194 if (!ISD::isNormalLoad(N00.getNode()))
19197 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
19198 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
19200 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
19206 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
19207 TargetLowering::DAGCombinerInfo &DCI,
19208 const X86Subtarget *Subtarget) {
19209 if (!DCI.isBeforeLegalizeOps())
19212 if (!Subtarget->hasFp256())
19215 EVT VT = N->getValueType(0);
19216 if (VT.isVector() && VT.getSizeInBits() == 256) {
19217 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
19225 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
19226 const X86Subtarget* Subtarget) {
19228 EVT VT = N->getValueType(0);
19230 // Let legalize expand this if it isn't a legal type yet.
19231 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19234 EVT ScalarVT = VT.getScalarType();
19235 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
19236 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
19239 SDValue A = N->getOperand(0);
19240 SDValue B = N->getOperand(1);
19241 SDValue C = N->getOperand(2);
19243 bool NegA = (A.getOpcode() == ISD::FNEG);
19244 bool NegB = (B.getOpcode() == ISD::FNEG);
19245 bool NegC = (C.getOpcode() == ISD::FNEG);
19247 // Negative multiplication when NegA xor NegB
19248 bool NegMul = (NegA != NegB);
19250 A = A.getOperand(0);
19252 B = B.getOperand(0);
19254 C = C.getOperand(0);
19258 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
19260 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
19262 return DAG.getNode(Opcode, dl, VT, A, B, C);
19265 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
19266 TargetLowering::DAGCombinerInfo &DCI,
19267 const X86Subtarget *Subtarget) {
19268 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
19269 // (and (i32 x86isd::setcc_carry), 1)
19270 // This eliminates the zext. This transformation is necessary because
19271 // ISD::SETCC is always legalized to i8.
19273 SDValue N0 = N->getOperand(0);
19274 EVT VT = N->getValueType(0);
19276 if (N0.getOpcode() == ISD::AND &&
19278 N0.getOperand(0).hasOneUse()) {
19279 SDValue N00 = N0.getOperand(0);
19280 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
19281 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
19282 if (!C || C->getZExtValue() != 1)
19284 return DAG.getNode(ISD::AND, dl, VT,
19285 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
19286 N00.getOperand(0), N00.getOperand(1)),
19287 DAG.getConstant(1, VT));
19291 if (N0.getOpcode() == ISD::TRUNCATE &&
19293 N0.getOperand(0).hasOneUse()) {
19294 SDValue N00 = N0.getOperand(0);
19295 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
19296 return DAG.getNode(ISD::AND, dl, VT,
19297 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
19298 N00.getOperand(0), N00.getOperand(1)),
19299 DAG.getConstant(1, VT));
19302 if (VT.is256BitVector()) {
19303 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
19311 // Optimize x == -y --> x+y == 0
19312 // x != -y --> x+y != 0
19313 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
19314 const X86Subtarget* Subtarget) {
19315 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
19316 SDValue LHS = N->getOperand(0);
19317 SDValue RHS = N->getOperand(1);
19318 EVT VT = N->getValueType(0);
19321 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
19322 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
19323 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
19324 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19325 LHS.getValueType(), RHS, LHS.getOperand(1));
19326 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19327 addV, DAG.getConstant(0, addV.getValueType()), CC);
19329 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
19330 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
19331 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
19332 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19333 RHS.getValueType(), LHS, RHS.getOperand(1));
19334 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19335 addV, DAG.getConstant(0, addV.getValueType()), CC);
19338 if (VT.getScalarType() == MVT::i1) {
19339 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
19340 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
19341 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
19342 if (!IsSEXT0 && !IsVZero0)
19344 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
19345 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
19346 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
19348 if (!IsSEXT1 && !IsVZero1)
19351 if (IsSEXT0 && IsVZero1) {
19352 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
19353 if (CC == ISD::SETEQ)
19354 return DAG.getNOT(DL, LHS.getOperand(0), VT);
19355 return LHS.getOperand(0);
19357 if (IsSEXT1 && IsVZero0) {
19358 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
19359 if (CC == ISD::SETEQ)
19360 return DAG.getNOT(DL, RHS.getOperand(0), VT);
19361 return RHS.getOperand(0);
19368 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
19369 // as "sbb reg,reg", since it can be extended without zext and produces
19370 // an all-ones bit which is more useful than 0/1 in some cases.
19371 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
19374 return DAG.getNode(ISD::AND, DL, VT,
19375 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19376 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
19377 DAG.getConstant(1, VT));
19378 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
19379 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
19380 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19381 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
19384 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
19385 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
19386 TargetLowering::DAGCombinerInfo &DCI,
19387 const X86Subtarget *Subtarget) {
19389 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
19390 SDValue EFLAGS = N->getOperand(1);
19392 if (CC == X86::COND_A) {
19393 // Try to convert COND_A into COND_B in an attempt to facilitate
19394 // materializing "setb reg".
19396 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
19397 // cannot take an immediate as its first operand.
19399 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
19400 EFLAGS.getValueType().isInteger() &&
19401 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
19402 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
19403 EFLAGS.getNode()->getVTList(),
19404 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
19405 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
19406 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
19410 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
19411 // a zext and produces an all-ones bit which is more useful than 0/1 in some
19413 if (CC == X86::COND_B)
19414 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
19418 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19419 if (Flags.getNode()) {
19420 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19421 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
19427 // Optimize branch condition evaluation.
19429 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
19430 TargetLowering::DAGCombinerInfo &DCI,
19431 const X86Subtarget *Subtarget) {
19433 SDValue Chain = N->getOperand(0);
19434 SDValue Dest = N->getOperand(1);
19435 SDValue EFLAGS = N->getOperand(3);
19436 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
19440 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19441 if (Flags.getNode()) {
19442 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19443 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
19450 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
19451 const X86TargetLowering *XTLI) {
19452 SDValue Op0 = N->getOperand(0);
19453 EVT InVT = Op0->getValueType(0);
19455 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
19456 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
19458 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
19459 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
19460 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
19463 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
19464 // a 32-bit target where SSE doesn't support i64->FP operations.
19465 if (Op0.getOpcode() == ISD::LOAD) {
19466 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
19467 EVT VT = Ld->getValueType(0);
19468 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
19469 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
19470 !XTLI->getSubtarget()->is64Bit() &&
19472 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
19473 Ld->getChain(), Op0, DAG);
19474 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
19481 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
19482 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
19483 X86TargetLowering::DAGCombinerInfo &DCI) {
19484 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
19485 // the result is either zero or one (depending on the input carry bit).
19486 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
19487 if (X86::isZeroNode(N->getOperand(0)) &&
19488 X86::isZeroNode(N->getOperand(1)) &&
19489 // We don't have a good way to replace an EFLAGS use, so only do this when
19491 SDValue(N, 1).use_empty()) {
19493 EVT VT = N->getValueType(0);
19494 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
19495 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
19496 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
19497 DAG.getConstant(X86::COND_B,MVT::i8),
19499 DAG.getConstant(1, VT));
19500 return DCI.CombineTo(N, Res1, CarryOut);
19506 // fold (add Y, (sete X, 0)) -> adc 0, Y
19507 // (add Y, (setne X, 0)) -> sbb -1, Y
19508 // (sub (sete X, 0), Y) -> sbb 0, Y
19509 // (sub (setne X, 0), Y) -> adc -1, Y
19510 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
19513 // Look through ZExts.
19514 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
19515 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
19518 SDValue SetCC = Ext.getOperand(0);
19519 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
19522 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
19523 if (CC != X86::COND_E && CC != X86::COND_NE)
19526 SDValue Cmp = SetCC.getOperand(1);
19527 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
19528 !X86::isZeroNode(Cmp.getOperand(1)) ||
19529 !Cmp.getOperand(0).getValueType().isInteger())
19532 SDValue CmpOp0 = Cmp.getOperand(0);
19533 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
19534 DAG.getConstant(1, CmpOp0.getValueType()));
19536 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
19537 if (CC == X86::COND_NE)
19538 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
19539 DL, OtherVal.getValueType(), OtherVal,
19540 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
19541 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
19542 DL, OtherVal.getValueType(), OtherVal,
19543 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
19546 /// PerformADDCombine - Do target-specific dag combines on integer adds.
19547 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
19548 const X86Subtarget *Subtarget) {
19549 EVT VT = N->getValueType(0);
19550 SDValue Op0 = N->getOperand(0);
19551 SDValue Op1 = N->getOperand(1);
19553 // Try to synthesize horizontal adds from adds of shuffles.
19554 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19555 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19556 isHorizontalBinOp(Op0, Op1, true))
19557 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
19559 return OptimizeConditionalInDecrement(N, DAG);
19562 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
19563 const X86Subtarget *Subtarget) {
19564 SDValue Op0 = N->getOperand(0);
19565 SDValue Op1 = N->getOperand(1);
19567 // X86 can't encode an immediate LHS of a sub. See if we can push the
19568 // negation into a preceding instruction.
19569 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
19570 // If the RHS of the sub is a XOR with one use and a constant, invert the
19571 // immediate. Then add one to the LHS of the sub so we can turn
19572 // X-Y -> X+~Y+1, saving one register.
19573 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
19574 isa<ConstantSDNode>(Op1.getOperand(1))) {
19575 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
19576 EVT VT = Op0.getValueType();
19577 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
19579 DAG.getConstant(~XorC, VT));
19580 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
19581 DAG.getConstant(C->getAPIntValue()+1, VT));
19585 // Try to synthesize horizontal adds from adds of shuffles.
19586 EVT VT = N->getValueType(0);
19587 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19588 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19589 isHorizontalBinOp(Op0, Op1, true))
19590 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19592 return OptimizeConditionalInDecrement(N, DAG);
19595 /// performVZEXTCombine - Performs build vector combines
19596 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19597 TargetLowering::DAGCombinerInfo &DCI,
19598 const X86Subtarget *Subtarget) {
19599 // (vzext (bitcast (vzext (x)) -> (vzext x)
19600 SDValue In = N->getOperand(0);
19601 while (In.getOpcode() == ISD::BITCAST)
19602 In = In.getOperand(0);
19604 if (In.getOpcode() != X86ISD::VZEXT)
19607 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19611 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19612 DAGCombinerInfo &DCI) const {
19613 SelectionDAG &DAG = DCI.DAG;
19614 switch (N->getOpcode()) {
19616 case ISD::EXTRACT_VECTOR_ELT:
19617 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19619 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19620 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19621 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19622 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19623 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19624 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19627 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19628 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19629 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19630 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19631 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19632 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19633 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19634 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19635 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19637 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19639 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19640 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19641 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19642 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19643 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19644 case ISD::ANY_EXTEND:
19645 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19646 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19647 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19648 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19649 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
19650 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19651 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19652 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19653 case X86ISD::SHUFP: // Handle all target specific shuffles
19654 case X86ISD::PALIGNR:
19655 case X86ISD::UNPCKH:
19656 case X86ISD::UNPCKL:
19657 case X86ISD::MOVHLPS:
19658 case X86ISD::MOVLHPS:
19659 case X86ISD::PSHUFD:
19660 case X86ISD::PSHUFHW:
19661 case X86ISD::PSHUFLW:
19662 case X86ISD::MOVSS:
19663 case X86ISD::MOVSD:
19664 case X86ISD::VPERMILP:
19665 case X86ISD::VPERM2X128:
19666 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19667 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19673 /// isTypeDesirableForOp - Return true if the target has native support for
19674 /// the specified value type and it is 'desirable' to use the type for the
19675 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19676 /// instruction encodings are longer and some i16 instructions are slow.
19677 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19678 if (!isTypeLegal(VT))
19680 if (VT != MVT::i16)
19687 case ISD::SIGN_EXTEND:
19688 case ISD::ZERO_EXTEND:
19689 case ISD::ANY_EXTEND:
19702 /// IsDesirableToPromoteOp - This method query the target whether it is
19703 /// beneficial for dag combiner to promote the specified node. If true, it
19704 /// should return the desired promotion type by reference.
19705 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19706 EVT VT = Op.getValueType();
19707 if (VT != MVT::i16)
19710 bool Promote = false;
19711 bool Commute = false;
19712 switch (Op.getOpcode()) {
19715 LoadSDNode *LD = cast<LoadSDNode>(Op);
19716 // If the non-extending load has a single use and it's not live out, then it
19717 // might be folded.
19718 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19719 Op.hasOneUse()*/) {
19720 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19721 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19722 // The only case where we'd want to promote LOAD (rather then it being
19723 // promoted as an operand is when it's only use is liveout.
19724 if (UI->getOpcode() != ISD::CopyToReg)
19731 case ISD::SIGN_EXTEND:
19732 case ISD::ZERO_EXTEND:
19733 case ISD::ANY_EXTEND:
19738 SDValue N0 = Op.getOperand(0);
19739 // Look out for (store (shl (load), x)).
19740 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19753 SDValue N0 = Op.getOperand(0);
19754 SDValue N1 = Op.getOperand(1);
19755 if (!Commute && MayFoldLoad(N1))
19757 // Avoid disabling potential load folding opportunities.
19758 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19760 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19770 //===----------------------------------------------------------------------===//
19771 // X86 Inline Assembly Support
19772 //===----------------------------------------------------------------------===//
19775 // Helper to match a string separated by whitespace.
19776 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19777 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19779 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19780 StringRef piece(*args[i]);
19781 if (!s.startswith(piece)) // Check if the piece matches.
19784 s = s.substr(piece.size());
19785 StringRef::size_type pos = s.find_first_not_of(" \t");
19786 if (pos == 0) // We matched a prefix.
19794 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19797 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
19799 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
19800 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
19801 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
19802 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
19804 if (AsmPieces.size() == 3)
19806 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
19813 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19814 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19816 std::string AsmStr = IA->getAsmString();
19818 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19819 if (!Ty || Ty->getBitWidth() % 16 != 0)
19822 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19823 SmallVector<StringRef, 4> AsmPieces;
19824 SplitString(AsmStr, AsmPieces, ";\n");
19826 switch (AsmPieces.size()) {
19827 default: return false;
19829 // FIXME: this should verify that we are targeting a 486 or better. If not,
19830 // we will turn this bswap into something that will be lowered to logical
19831 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19832 // lower so don't worry about this.
19834 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19835 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19836 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19837 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19838 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19839 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19840 // No need to check constraints, nothing other than the equivalent of
19841 // "=r,0" would be valid here.
19842 return IntrinsicLowering::LowerToByteSwap(CI);
19845 // rorw $$8, ${0:w} --> llvm.bswap.i16
19846 if (CI->getType()->isIntegerTy(16) &&
19847 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19848 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19849 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19851 const std::string &ConstraintsStr = IA->getConstraintString();
19852 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19853 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19854 if (clobbersFlagRegisters(AsmPieces))
19855 return IntrinsicLowering::LowerToByteSwap(CI);
19859 if (CI->getType()->isIntegerTy(32) &&
19860 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19861 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19862 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19863 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19865 const std::string &ConstraintsStr = IA->getConstraintString();
19866 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19867 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19868 if (clobbersFlagRegisters(AsmPieces))
19869 return IntrinsicLowering::LowerToByteSwap(CI);
19872 if (CI->getType()->isIntegerTy(64)) {
19873 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19874 if (Constraints.size() >= 2 &&
19875 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19876 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19877 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19878 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19879 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19880 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19881 return IntrinsicLowering::LowerToByteSwap(CI);
19889 /// getConstraintType - Given a constraint letter, return the type of
19890 /// constraint it is for this target.
19891 X86TargetLowering::ConstraintType
19892 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19893 if (Constraint.size() == 1) {
19894 switch (Constraint[0]) {
19905 return C_RegisterClass;
19929 return TargetLowering::getConstraintType(Constraint);
19932 /// Examine constraint type and operand type and determine a weight value.
19933 /// This object must already have been set up with the operand type
19934 /// and the current alternative constraint selected.
19935 TargetLowering::ConstraintWeight
19936 X86TargetLowering::getSingleConstraintMatchWeight(
19937 AsmOperandInfo &info, const char *constraint) const {
19938 ConstraintWeight weight = CW_Invalid;
19939 Value *CallOperandVal = info.CallOperandVal;
19940 // If we don't have a value, we can't do a match,
19941 // but allow it at the lowest weight.
19942 if (CallOperandVal == NULL)
19944 Type *type = CallOperandVal->getType();
19945 // Look at the constraint type.
19946 switch (*constraint) {
19948 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19959 if (CallOperandVal->getType()->isIntegerTy())
19960 weight = CW_SpecificReg;
19965 if (type->isFloatingPointTy())
19966 weight = CW_SpecificReg;
19969 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19970 weight = CW_SpecificReg;
19974 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19975 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19976 weight = CW_Register;
19979 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19980 if (C->getZExtValue() <= 31)
19981 weight = CW_Constant;
19985 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19986 if (C->getZExtValue() <= 63)
19987 weight = CW_Constant;
19991 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19992 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19993 weight = CW_Constant;
19997 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19998 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19999 weight = CW_Constant;
20003 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20004 if (C->getZExtValue() <= 3)
20005 weight = CW_Constant;
20009 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20010 if (C->getZExtValue() <= 0xff)
20011 weight = CW_Constant;
20016 if (dyn_cast<ConstantFP>(CallOperandVal)) {
20017 weight = CW_Constant;
20021 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20022 if ((C->getSExtValue() >= -0x80000000LL) &&
20023 (C->getSExtValue() <= 0x7fffffffLL))
20024 weight = CW_Constant;
20028 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
20029 if (C->getZExtValue() <= 0xffffffff)
20030 weight = CW_Constant;
20037 /// LowerXConstraint - try to replace an X constraint, which matches anything,
20038 /// with another that has more specific requirements based on the type of the
20039 /// corresponding operand.
20040 const char *X86TargetLowering::
20041 LowerXConstraint(EVT ConstraintVT) const {
20042 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
20043 // 'f' like normal targets.
20044 if (ConstraintVT.isFloatingPoint()) {
20045 if (Subtarget->hasSSE2())
20047 if (Subtarget->hasSSE1())
20051 return TargetLowering::LowerXConstraint(ConstraintVT);
20054 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
20055 /// vector. If it is invalid, don't add anything to Ops.
20056 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
20057 std::string &Constraint,
20058 std::vector<SDValue>&Ops,
20059 SelectionDAG &DAG) const {
20060 SDValue Result(0, 0);
20062 // Only support length 1 constraints for now.
20063 if (Constraint.length() > 1) return;
20065 char ConstraintLetter = Constraint[0];
20066 switch (ConstraintLetter) {
20069 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20070 if (C->getZExtValue() <= 31) {
20071 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20077 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20078 if (C->getZExtValue() <= 63) {
20079 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20085 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20086 if (isInt<8>(C->getSExtValue())) {
20087 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20093 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20094 if (C->getZExtValue() <= 255) {
20095 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20101 // 32-bit signed value
20102 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20103 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
20104 C->getSExtValue())) {
20105 // Widen to 64 bits here to get it sign extended.
20106 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
20109 // FIXME gcc accepts some relocatable values here too, but only in certain
20110 // memory models; it's complicated.
20115 // 32-bit unsigned value
20116 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20117 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
20118 C->getZExtValue())) {
20119 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20123 // FIXME gcc accepts some relocatable values here too, but only in certain
20124 // memory models; it's complicated.
20128 // Literal immediates are always ok.
20129 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
20130 // Widen to 64 bits here to get it sign extended.
20131 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
20135 // In any sort of PIC mode addresses need to be computed at runtime by
20136 // adding in a register or some sort of table lookup. These can't
20137 // be used as immediates.
20138 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
20141 // If we are in non-pic codegen mode, we allow the address of a global (with
20142 // an optional displacement) to be used with 'i'.
20143 GlobalAddressSDNode *GA = 0;
20144 int64_t Offset = 0;
20146 // Match either (GA), (GA+C), (GA+C1+C2), etc.
20148 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
20149 Offset += GA->getOffset();
20151 } else if (Op.getOpcode() == ISD::ADD) {
20152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
20153 Offset += C->getZExtValue();
20154 Op = Op.getOperand(0);
20157 } else if (Op.getOpcode() == ISD::SUB) {
20158 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
20159 Offset += -C->getZExtValue();
20160 Op = Op.getOperand(0);
20165 // Otherwise, this isn't something we can handle, reject it.
20169 const GlobalValue *GV = GA->getGlobal();
20170 // If we require an extra load to get this address, as in PIC mode, we
20171 // can't accept it.
20172 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
20173 getTargetMachine())))
20176 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
20177 GA->getValueType(0), Offset);
20182 if (Result.getNode()) {
20183 Ops.push_back(Result);
20186 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
20189 std::pair<unsigned, const TargetRegisterClass*>
20190 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
20192 // First, see if this is a constraint that directly corresponds to an LLVM
20194 if (Constraint.size() == 1) {
20195 // GCC Constraint Letters
20196 switch (Constraint[0]) {
20198 // TODO: Slight differences here in allocation order and leaving
20199 // RIP in the class. Do they matter any more here than they do
20200 // in the normal allocation?
20201 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
20202 if (Subtarget->is64Bit()) {
20203 if (VT == MVT::i32 || VT == MVT::f32)
20204 return std::make_pair(0U, &X86::GR32RegClass);
20205 if (VT == MVT::i16)
20206 return std::make_pair(0U, &X86::GR16RegClass);
20207 if (VT == MVT::i8 || VT == MVT::i1)
20208 return std::make_pair(0U, &X86::GR8RegClass);
20209 if (VT == MVT::i64 || VT == MVT::f64)
20210 return std::make_pair(0U, &X86::GR64RegClass);
20213 // 32-bit fallthrough
20214 case 'Q': // Q_REGS
20215 if (VT == MVT::i32 || VT == MVT::f32)
20216 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
20217 if (VT == MVT::i16)
20218 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
20219 if (VT == MVT::i8 || VT == MVT::i1)
20220 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
20221 if (VT == MVT::i64)
20222 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
20224 case 'r': // GENERAL_REGS
20225 case 'l': // INDEX_REGS
20226 if (VT == MVT::i8 || VT == MVT::i1)
20227 return std::make_pair(0U, &X86::GR8RegClass);
20228 if (VT == MVT::i16)
20229 return std::make_pair(0U, &X86::GR16RegClass);
20230 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
20231 return std::make_pair(0U, &X86::GR32RegClass);
20232 return std::make_pair(0U, &X86::GR64RegClass);
20233 case 'R': // LEGACY_REGS
20234 if (VT == MVT::i8 || VT == MVT::i1)
20235 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
20236 if (VT == MVT::i16)
20237 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
20238 if (VT == MVT::i32 || !Subtarget->is64Bit())
20239 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
20240 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
20241 case 'f': // FP Stack registers.
20242 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
20243 // value to the correct fpstack register class.
20244 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
20245 return std::make_pair(0U, &X86::RFP32RegClass);
20246 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
20247 return std::make_pair(0U, &X86::RFP64RegClass);
20248 return std::make_pair(0U, &X86::RFP80RegClass);
20249 case 'y': // MMX_REGS if MMX allowed.
20250 if (!Subtarget->hasMMX()) break;
20251 return std::make_pair(0U, &X86::VR64RegClass);
20252 case 'Y': // SSE_REGS if SSE2 allowed
20253 if (!Subtarget->hasSSE2()) break;
20255 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
20256 if (!Subtarget->hasSSE1()) break;
20258 switch (VT.SimpleTy) {
20260 // Scalar SSE types.
20263 return std::make_pair(0U, &X86::FR32RegClass);
20266 return std::make_pair(0U, &X86::FR64RegClass);
20274 return std::make_pair(0U, &X86::VR128RegClass);
20282 return std::make_pair(0U, &X86::VR256RegClass);
20287 return std::make_pair(0U, &X86::VR512RegClass);
20293 // Use the default implementation in TargetLowering to convert the register
20294 // constraint into a member of a register class.
20295 std::pair<unsigned, const TargetRegisterClass*> Res;
20296 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
20298 // Not found as a standard register?
20299 if (Res.second == 0) {
20300 // Map st(0) -> st(7) -> ST0
20301 if (Constraint.size() == 7 && Constraint[0] == '{' &&
20302 tolower(Constraint[1]) == 's' &&
20303 tolower(Constraint[2]) == 't' &&
20304 Constraint[3] == '(' &&
20305 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
20306 Constraint[5] == ')' &&
20307 Constraint[6] == '}') {
20309 Res.first = X86::ST0+Constraint[4]-'0';
20310 Res.second = &X86::RFP80RegClass;
20314 // GCC allows "st(0)" to be called just plain "st".
20315 if (StringRef("{st}").equals_lower(Constraint)) {
20316 Res.first = X86::ST0;
20317 Res.second = &X86::RFP80RegClass;
20322 if (StringRef("{flags}").equals_lower(Constraint)) {
20323 Res.first = X86::EFLAGS;
20324 Res.second = &X86::CCRRegClass;
20328 // 'A' means EAX + EDX.
20329 if (Constraint == "A") {
20330 Res.first = X86::EAX;
20331 Res.second = &X86::GR32_ADRegClass;
20337 // Otherwise, check to see if this is a register class of the wrong value
20338 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
20339 // turn into {ax},{dx}.
20340 if (Res.second->hasType(VT))
20341 return Res; // Correct type already, nothing to do.
20343 // All of the single-register GCC register classes map their values onto
20344 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
20345 // really want an 8-bit or 32-bit register, map to the appropriate register
20346 // class and return the appropriate register.
20347 if (Res.second == &X86::GR16RegClass) {
20348 if (VT == MVT::i8 || VT == MVT::i1) {
20349 unsigned DestReg = 0;
20350 switch (Res.first) {
20352 case X86::AX: DestReg = X86::AL; break;
20353 case X86::DX: DestReg = X86::DL; break;
20354 case X86::CX: DestReg = X86::CL; break;
20355 case X86::BX: DestReg = X86::BL; break;
20358 Res.first = DestReg;
20359 Res.second = &X86::GR8RegClass;
20361 } else if (VT == MVT::i32 || VT == MVT::f32) {
20362 unsigned DestReg = 0;
20363 switch (Res.first) {
20365 case X86::AX: DestReg = X86::EAX; break;
20366 case X86::DX: DestReg = X86::EDX; break;
20367 case X86::CX: DestReg = X86::ECX; break;
20368 case X86::BX: DestReg = X86::EBX; break;
20369 case X86::SI: DestReg = X86::ESI; break;
20370 case X86::DI: DestReg = X86::EDI; break;
20371 case X86::BP: DestReg = X86::EBP; break;
20372 case X86::SP: DestReg = X86::ESP; break;
20375 Res.first = DestReg;
20376 Res.second = &X86::GR32RegClass;
20378 } else if (VT == MVT::i64 || VT == MVT::f64) {
20379 unsigned DestReg = 0;
20380 switch (Res.first) {
20382 case X86::AX: DestReg = X86::RAX; break;
20383 case X86::DX: DestReg = X86::RDX; break;
20384 case X86::CX: DestReg = X86::RCX; break;
20385 case X86::BX: DestReg = X86::RBX; break;
20386 case X86::SI: DestReg = X86::RSI; break;
20387 case X86::DI: DestReg = X86::RDI; break;
20388 case X86::BP: DestReg = X86::RBP; break;
20389 case X86::SP: DestReg = X86::RSP; break;
20392 Res.first = DestReg;
20393 Res.second = &X86::GR64RegClass;
20396 } else if (Res.second == &X86::FR32RegClass ||
20397 Res.second == &X86::FR64RegClass ||
20398 Res.second == &X86::VR128RegClass ||
20399 Res.second == &X86::VR256RegClass ||
20400 Res.second == &X86::FR32XRegClass ||
20401 Res.second == &X86::FR64XRegClass ||
20402 Res.second == &X86::VR128XRegClass ||
20403 Res.second == &X86::VR256XRegClass ||
20404 Res.second == &X86::VR512RegClass) {
20405 // Handle references to XMM physical registers that got mapped into the
20406 // wrong class. This can happen with constraints like {xmm0} where the
20407 // target independent register mapper will just pick the first match it can
20408 // find, ignoring the required type.
20410 if (VT == MVT::f32 || VT == MVT::i32)
20411 Res.second = &X86::FR32RegClass;
20412 else if (VT == MVT::f64 || VT == MVT::i64)
20413 Res.second = &X86::FR64RegClass;
20414 else if (X86::VR128RegClass.hasType(VT))
20415 Res.second = &X86::VR128RegClass;
20416 else if (X86::VR256RegClass.hasType(VT))
20417 Res.second = &X86::VR256RegClass;
20418 else if (X86::VR512RegClass.hasType(VT))
20419 Res.second = &X86::VR512RegClass;