1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetOptions.h"
56 using namespace dwarf;
58 STATISTIC(NumTailCalls, "Number of tail calls");
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static SDValue Insert128BitVector(SDValue Result,
70 static SDValue Extract128BitVector(SDValue Vec,
75 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
76 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
77 /// simple subregister reference. Idx is an index in the 128 bits we
78 /// want. It need not be aligned to a 128-bit bounday. That makes
79 /// lowering EXTRACT_VECTOR_ELT operations easier.
80 static SDValue Extract128BitVector(SDValue Vec,
84 EVT VT = Vec.getValueType();
85 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
86 EVT ElVT = VT.getVectorElementType();
87 int Factor = VT.getSizeInBits()/128;
88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
89 VT.getVectorNumElements()/Factor);
91 // Extract from UNDEF is UNDEF.
92 if (Vec.getOpcode() == ISD::UNDEF)
93 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
95 if (isa<ConstantSDNode>(Idx)) {
96 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
98 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
99 // we can match to VEXTRACTF128.
100 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
102 // This is the index of the first element of the 128-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
107 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
117 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
118 /// sets things up to match to an AVX VINSERTF128 instruction or a
119 /// simple superregister reference. Idx is an index in the 128 bits
120 /// we want. It need not be aligned to a 128-bit bounday. That makes
121 /// lowering INSERT_VECTOR_ELT operations easier.
122 static SDValue Insert128BitVector(SDValue Result,
127 if (isa<ConstantSDNode>(Idx)) {
128 EVT VT = Vec.getValueType();
129 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
131 EVT ElVT = VT.getVectorElementType();
132 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
133 EVT ResultVT = Result.getValueType();
135 // Insert the relevant 128 bits.
136 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
138 // This is the index of the first element of the 128-bit chunk
140 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
143 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
144 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
152 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
153 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
154 bool is64Bit = Subtarget->is64Bit();
156 if (Subtarget->isTargetEnvMacho()) {
158 return new X8664_MachoTargetObjectFile();
159 return new TargetLoweringObjectFileMachO();
162 if (Subtarget->isTargetELF())
163 return new TargetLoweringObjectFileELF();
164 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
165 return new TargetLoweringObjectFileCOFF();
166 llvm_unreachable("unknown subtarget type");
169 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
170 : TargetLowering(TM, createTLOF(TM)) {
171 Subtarget = &TM.getSubtarget<X86Subtarget>();
172 X86ScalarSSEf64 = Subtarget->hasXMMInt();
173 X86ScalarSSEf32 = Subtarget->hasXMM();
174 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
176 RegInfo = TM.getRegisterInfo();
177 TD = getTargetData();
179 // Set up the TargetLowering object.
180 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
182 // X86 is weird, it always uses i8 for shift amounts and setcc results.
183 setBooleanContents(ZeroOrOneBooleanContent);
184 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
185 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
187 // For 64-bit since we have so many registers use the ILP scheduler, for
188 // 32-bit code use the register pressure specific scheduling.
189 if (Subtarget->is64Bit())
190 setSchedulingPreference(Sched::ILP);
192 setSchedulingPreference(Sched::RegPressure);
193 setStackPointerRegisterToSaveRestore(X86StackPtr);
195 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
196 // Setup Windows compiler runtime calls.
197 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
198 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
199 setLibcallName(RTLIB::SREM_I64, "_allrem");
200 setLibcallName(RTLIB::UREM_I64, "_aullrem");
201 setLibcallName(RTLIB::MUL_I64, "_allmul");
202 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
203 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
204 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
207 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
208 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
209 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
210 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
213 if (Subtarget->isTargetDarwin()) {
214 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
215 setUseUnderscoreSetJmp(false);
216 setUseUnderscoreLongJmp(false);
217 } else if (Subtarget->isTargetMingw()) {
218 // MS runtime is weird: it exports _setjmp, but longjmp!
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(false);
222 setUseUnderscoreSetJmp(true);
223 setUseUnderscoreLongJmp(true);
226 // Set up the register classes.
227 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
228 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
229 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
230 if (Subtarget->is64Bit())
231 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
233 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
235 // We don't accept any truncstore of integer registers.
236 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
237 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
238 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
239 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
240 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
241 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
243 // SETOEQ and SETUNE require checking two conditions.
244 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
247 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
248 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
249 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
251 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
253 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
254 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
257 if (Subtarget->is64Bit()) {
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
260 } else if (!UseSoftFloat) {
261 // We have an algorithm for SSE2->double, and we turn this into a
262 // 64-bit FILD followed by conditional FADD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
264 // We have an algorithm for SSE2, and we turn this into a 64-bit
265 // FILD for other targets.
266 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
269 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
271 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
275 // SSE has no i16 to fp conversion, only i32
276 if (X86ScalarSSEf32) {
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
278 // f32 and f64 cases are Legal, f80 case is not
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
286 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
289 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
290 // are Legal, f80 is custom lowered.
291 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
292 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
294 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
296 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
299 if (X86ScalarSSEf32) {
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
301 // f32 and f64 cases are Legal, f80 case is not
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
305 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
308 // Handle FP_TO_UINT by promoting the destination to a larger signed
310 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
311 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
314 if (Subtarget->is64Bit()) {
315 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
316 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
317 } else if (!UseSoftFloat) {
318 // Since AVX is a superset of SSE3, only check for SSE here.
319 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
320 // Expand FP_TO_UINT into a select.
321 // FIXME: We would like to use a Custom expander here eventually to do
322 // the optimal thing for SSE vs. the default expansion in the legalizer.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
325 // With SSE3 we can use fisttpll to convert to a signed i64; without
326 // SSE, we're stuck with a fistpll.
327 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
330 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
331 if (!X86ScalarSSEf64) {
332 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
333 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
334 if (Subtarget->is64Bit()) {
335 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
336 // Without SSE, i64->f64 goes through memory.
337 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
341 // Scalar integer divide and remainder are lowered to use operations that
342 // produce two results, to match the available instructions. This exposes
343 // the two-result form to trivial CSE, which is able to combine x/y and x%y
344 // into a single instruction.
346 // Scalar integer multiply-high is also lowered to use two-result
347 // operations, to match the available instructions. However, plain multiply
348 // (low) operations are left as Legal, as there are single-result
349 // instructions for this in x86. Using the two-result multiply instructions
350 // when both high and low results are needed must be arranged by dagcombine.
351 for (unsigned i = 0, e = 4; i != e; ++i) {
353 setOperationAction(ISD::MULHS, VT, Expand);
354 setOperationAction(ISD::MULHU, VT, Expand);
355 setOperationAction(ISD::SDIV, VT, Expand);
356 setOperationAction(ISD::UDIV, VT, Expand);
357 setOperationAction(ISD::SREM, VT, Expand);
358 setOperationAction(ISD::UREM, VT, Expand);
360 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
361 setOperationAction(ISD::ADDC, VT, Custom);
362 setOperationAction(ISD::ADDE, VT, Custom);
363 setOperationAction(ISD::SUBC, VT, Custom);
364 setOperationAction(ISD::SUBE, VT, Custom);
367 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
368 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
369 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
370 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
371 if (Subtarget->is64Bit())
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
376 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
377 setOperationAction(ISD::FREM , MVT::f32 , Expand);
378 setOperationAction(ISD::FREM , MVT::f64 , Expand);
379 setOperationAction(ISD::FREM , MVT::f80 , Expand);
380 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
382 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
383 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
384 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
385 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
386 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
387 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
388 if (Subtarget->is64Bit()) {
389 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
390 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
393 if (Subtarget->hasPOPCNT()) {
394 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
396 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
397 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
398 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
399 if (Subtarget->is64Bit())
400 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
403 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
404 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
406 // These should be promoted to a larger select which is supported.
407 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
408 // X86 wants to expand cmov itself.
409 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
410 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
411 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
413 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
414 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
416 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
417 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
419 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
420 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
421 if (Subtarget->is64Bit()) {
422 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
423 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
425 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
428 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
429 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
430 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
431 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
434 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
435 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
436 if (Subtarget->is64Bit()) {
437 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
438 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
439 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
440 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
443 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
444 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
447 if (Subtarget->is64Bit()) {
448 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
453 if (Subtarget->hasXMM())
454 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
456 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
457 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
459 // On X86 and X86-64, atomic operations are lowered to locked instructions.
460 // Locked instructions, in turn, have implicit fence semantics (all memory
461 // operations are flushed before issuing the locked instruction, and they
462 // are not buffered), so we can fold away the common pattern of
463 // fence-atomic-fence.
464 setShouldFoldAtomicFences(true);
466 // Expand certain atomics
467 for (unsigned i = 0, e = 4; i != e; ++i) {
469 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
470 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
471 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
474 if (!Subtarget->is64Bit()) {
475 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
477 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
478 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
479 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
480 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
481 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
482 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
485 if (Subtarget->hasCmpxchg16b()) {
486 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
489 // FIXME - use subtarget debug flags
490 if (!Subtarget->isTargetDarwin() &&
491 !Subtarget->isTargetELF() &&
492 !Subtarget->isTargetCygMing()) {
493 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
496 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
497 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
498 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
499 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
500 if (Subtarget->is64Bit()) {
501 setExceptionPointerRegister(X86::RAX);
502 setExceptionSelectorRegister(X86::RDX);
504 setExceptionPointerRegister(X86::EAX);
505 setExceptionSelectorRegister(X86::EDX);
507 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
508 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
510 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
511 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
513 setOperationAction(ISD::TRAP, MVT::Other, Legal);
515 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
516 setOperationAction(ISD::VASTART , MVT::Other, Custom);
517 setOperationAction(ISD::VAEND , MVT::Other, Expand);
518 if (Subtarget->is64Bit()) {
519 setOperationAction(ISD::VAARG , MVT::Other, Custom);
520 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
522 setOperationAction(ISD::VAARG , MVT::Other, Expand);
523 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
526 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
527 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
529 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
530 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
531 MVT::i64 : MVT::i32, Custom);
532 else if (EnableSegmentedStacks)
533 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
534 MVT::i64 : MVT::i32, Custom);
536 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
537 MVT::i64 : MVT::i32, Expand);
539 if (!UseSoftFloat && X86ScalarSSEf64) {
540 // f32 and f64 use SSE.
541 // Set up the FP register classes.
542 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
543 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
545 // Use ANDPD to simulate FABS.
546 setOperationAction(ISD::FABS , MVT::f64, Custom);
547 setOperationAction(ISD::FABS , MVT::f32, Custom);
549 // Use XORP to simulate FNEG.
550 setOperationAction(ISD::FNEG , MVT::f64, Custom);
551 setOperationAction(ISD::FNEG , MVT::f32, Custom);
553 // Use ANDPD and ORPD to simulate FCOPYSIGN.
554 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
555 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
557 // Lower this to FGETSIGNx86 plus an AND.
558 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
559 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
561 // We don't support sin/cos/fmod
562 setOperationAction(ISD::FSIN , MVT::f64, Expand);
563 setOperationAction(ISD::FCOS , MVT::f64, Expand);
564 setOperationAction(ISD::FSIN , MVT::f32, Expand);
565 setOperationAction(ISD::FCOS , MVT::f32, Expand);
567 // Expand FP immediates into loads from the stack, except for the special
569 addLegalFPImmediate(APFloat(+0.0)); // xorpd
570 addLegalFPImmediate(APFloat(+0.0f)); // xorps
571 } else if (!UseSoftFloat && X86ScalarSSEf32) {
572 // Use SSE for f32, x87 for f64.
573 // Set up the FP register classes.
574 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
575 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
577 // Use ANDPS to simulate FABS.
578 setOperationAction(ISD::FABS , MVT::f32, Custom);
580 // Use XORP to simulate FNEG.
581 setOperationAction(ISD::FNEG , MVT::f32, Custom);
583 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
585 // Use ANDPS and ORPS to simulate FCOPYSIGN.
586 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
587 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
589 // We don't support sin/cos/fmod
590 setOperationAction(ISD::FSIN , MVT::f32, Expand);
591 setOperationAction(ISD::FCOS , MVT::f32, Expand);
593 // Special cases we handle for FP constants.
594 addLegalFPImmediate(APFloat(+0.0f)); // xorps
595 addLegalFPImmediate(APFloat(+0.0)); // FLD0
596 addLegalFPImmediate(APFloat(+1.0)); // FLD1
597 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
598 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
601 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
602 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
604 } else if (!UseSoftFloat) {
605 // f32 and f64 in x87.
606 // Set up the FP register classes.
607 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
608 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
610 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
611 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
612 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
613 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
616 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
617 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
619 addLegalFPImmediate(APFloat(+0.0)); // FLD0
620 addLegalFPImmediate(APFloat(+1.0)); // FLD1
621 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
622 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
623 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
624 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
625 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
626 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
629 // We don't support FMA.
630 setOperationAction(ISD::FMA, MVT::f64, Expand);
631 setOperationAction(ISD::FMA, MVT::f32, Expand);
633 // Long double always uses X87.
635 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
636 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
637 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
639 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
640 addLegalFPImmediate(TmpFlt); // FLD0
642 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
645 APFloat TmpFlt2(+1.0);
646 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
648 addLegalFPImmediate(TmpFlt2); // FLD1
649 TmpFlt2.changeSign();
650 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
654 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
655 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
658 setOperationAction(ISD::FMA, MVT::f80, Expand);
661 // Always use a library call for pow.
662 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
663 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
664 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
666 setOperationAction(ISD::FLOG, MVT::f80, Expand);
667 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
668 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
669 setOperationAction(ISD::FEXP, MVT::f80, Expand);
670 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
672 // First set operation action for all vector types to either promote
673 // (for widening) or expand (for scalarization). Then we will selectively
674 // turn on ones that can be effectively codegen'd.
675 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
676 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
677 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
678 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
679 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
680 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
681 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
682 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
683 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
684 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
685 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
686 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
687 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
688 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
690 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
691 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
692 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
693 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
694 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
695 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
727 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
732 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
733 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
734 setTruncStoreAction((MVT::SimpleValueType)VT,
735 (MVT::SimpleValueType)InnerVT, Expand);
736 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
737 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
738 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
741 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
742 // with -msoft-float, disable use of MMX as well.
743 if (!UseSoftFloat && Subtarget->hasMMX()) {
744 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
745 // No operations on x86mmx supported, everything uses intrinsics.
748 // MMX-sized vectors (other than x86mmx) are expected to be expanded
749 // into smaller operations.
750 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
751 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
752 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
753 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
754 setOperationAction(ISD::AND, MVT::v8i8, Expand);
755 setOperationAction(ISD::AND, MVT::v4i16, Expand);
756 setOperationAction(ISD::AND, MVT::v2i32, Expand);
757 setOperationAction(ISD::AND, MVT::v1i64, Expand);
758 setOperationAction(ISD::OR, MVT::v8i8, Expand);
759 setOperationAction(ISD::OR, MVT::v4i16, Expand);
760 setOperationAction(ISD::OR, MVT::v2i32, Expand);
761 setOperationAction(ISD::OR, MVT::v1i64, Expand);
762 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
763 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
764 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
765 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
766 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
767 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
768 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
769 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
771 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
772 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
773 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
774 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
775 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
776 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
777 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
778 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
780 if (!UseSoftFloat && Subtarget->hasXMM()) {
781 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
783 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
785 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
786 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
788 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
789 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
790 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
791 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
792 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
793 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
794 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
797 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
798 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
800 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
801 // registers cannot be used even for integer operations.
802 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
803 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
804 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
805 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
807 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
808 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
809 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
810 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
811 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
812 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
813 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
814 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
815 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
816 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
817 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
818 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
819 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
820 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
821 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
822 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
824 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
825 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
826 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
827 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
829 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
830 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
831 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
833 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
835 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
836 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
837 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
838 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
839 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
841 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
842 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
843 EVT VT = (MVT::SimpleValueType)i;
844 // Do not attempt to custom lower non-power-of-2 vectors
845 if (!isPowerOf2_32(VT.getVectorNumElements()))
847 // Do not attempt to custom lower non-128-bit vectors
848 if (!VT.is128BitVector())
850 setOperationAction(ISD::BUILD_VECTOR,
851 VT.getSimpleVT().SimpleTy, Custom);
852 setOperationAction(ISD::VECTOR_SHUFFLE,
853 VT.getSimpleVT().SimpleTy, Custom);
854 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
855 VT.getSimpleVT().SimpleTy, Custom);
858 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
859 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
860 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
861 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
863 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
865 if (Subtarget->is64Bit()) {
866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
867 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
870 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
871 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
872 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
875 // Do not attempt to promote non-128-bit vectors
876 if (!VT.is128BitVector())
879 setOperationAction(ISD::AND, SVT, Promote);
880 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
881 setOperationAction(ISD::OR, SVT, Promote);
882 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
883 setOperationAction(ISD::XOR, SVT, Promote);
884 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
885 setOperationAction(ISD::LOAD, SVT, Promote);
886 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
887 setOperationAction(ISD::SELECT, SVT, Promote);
888 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
891 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
893 // Custom lower v2i64 and v2f64 selects.
894 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
895 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
896 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
897 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
899 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
900 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
903 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
904 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
905 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
906 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
907 setOperationAction(ISD::FRINT, MVT::f32, Legal);
908 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
909 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
910 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
911 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
912 setOperationAction(ISD::FRINT, MVT::f64, Legal);
913 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
915 // FIXME: Do we need to handle scalar-to-vector here?
916 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
918 // Can turn SHL into an integer multiply.
919 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
920 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
922 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
923 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
924 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
925 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
926 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
928 // i8 and i16 vectors are custom , because the source register and source
929 // source memory operand types are not the same width. f32 vectors are
930 // custom since the immediate controlling the insert encodes additional
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
933 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
934 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
935 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
937 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
938 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
939 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
940 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
942 if (Subtarget->is64Bit()) {
943 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
944 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
948 if (Subtarget->hasXMMInt()) {
949 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
950 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
951 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
952 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
954 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
955 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
956 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
958 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
959 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
962 if (Subtarget->hasSSE42() || Subtarget->hasAVX())
963 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
965 if (!UseSoftFloat && Subtarget->hasAVX()) {
966 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
967 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
968 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
969 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
970 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
971 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
973 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
974 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
975 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
977 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
978 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
979 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
980 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
981 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
982 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
984 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
991 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
992 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
993 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
995 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
996 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
997 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
998 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
999 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1000 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1002 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1003 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1004 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1005 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1007 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1008 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1009 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1010 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1012 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1013 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1015 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1016 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1017 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1018 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1020 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1021 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1022 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1024 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1025 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1026 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1027 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1029 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1030 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1031 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1032 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1034 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1035 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1036 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1037 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1039 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1040 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1041 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1042 // Don't lower v32i8 because there is no 128-bit byte mul
1044 // Custom lower several nodes for 256-bit types.
1045 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1046 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1047 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1050 // Extract subvector is special because the value type
1051 // (result) is 128-bit but the source is 256-bit wide.
1052 if (VT.is128BitVector())
1053 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1055 // Do not attempt to custom lower other non-256-bit vectors
1056 if (!VT.is256BitVector())
1059 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1060 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1061 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1062 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1063 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1064 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1067 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1068 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1069 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1072 // Do not attempt to promote non-256-bit vectors
1073 if (!VT.is256BitVector())
1076 setOperationAction(ISD::AND, SVT, Promote);
1077 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1078 setOperationAction(ISD::OR, SVT, Promote);
1079 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1080 setOperationAction(ISD::XOR, SVT, Promote);
1081 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1082 setOperationAction(ISD::LOAD, SVT, Promote);
1083 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1084 setOperationAction(ISD::SELECT, SVT, Promote);
1085 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1089 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1090 // of this type with custom code.
1091 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1092 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1093 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1096 // We want to custom lower some of our intrinsics.
1097 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1100 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1101 // handle type legalization for these operations here.
1103 // FIXME: We really should do custom legalization for addition and
1104 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1105 // than generic legalization for 64-bit multiplication-with-overflow, though.
1106 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1107 // Add/Sub/Mul with overflow operations are custom lowered.
1109 setOperationAction(ISD::SADDO, VT, Custom);
1110 setOperationAction(ISD::UADDO, VT, Custom);
1111 setOperationAction(ISD::SSUBO, VT, Custom);
1112 setOperationAction(ISD::USUBO, VT, Custom);
1113 setOperationAction(ISD::SMULO, VT, Custom);
1114 setOperationAction(ISD::UMULO, VT, Custom);
1117 // There are no 8-bit 3-address imul/mul instructions
1118 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1119 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1121 if (!Subtarget->is64Bit()) {
1122 // These libcalls are not available in 32-bit.
1123 setLibcallName(RTLIB::SHL_I128, 0);
1124 setLibcallName(RTLIB::SRL_I128, 0);
1125 setLibcallName(RTLIB::SRA_I128, 0);
1128 // We have target-specific dag combine patterns for the following nodes:
1129 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1130 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1131 setTargetDAGCombine(ISD::BUILD_VECTOR);
1132 setTargetDAGCombine(ISD::VSELECT);
1133 setTargetDAGCombine(ISD::SELECT);
1134 setTargetDAGCombine(ISD::SHL);
1135 setTargetDAGCombine(ISD::SRA);
1136 setTargetDAGCombine(ISD::SRL);
1137 setTargetDAGCombine(ISD::OR);
1138 setTargetDAGCombine(ISD::AND);
1139 setTargetDAGCombine(ISD::ADD);
1140 setTargetDAGCombine(ISD::SUB);
1141 setTargetDAGCombine(ISD::LOAD);
1142 setTargetDAGCombine(ISD::STORE);
1143 setTargetDAGCombine(ISD::ZERO_EXTEND);
1144 setTargetDAGCombine(ISD::SINT_TO_FP);
1145 if (Subtarget->is64Bit())
1146 setTargetDAGCombine(ISD::MUL);
1148 computeRegisterProperties();
1150 // On Darwin, -Os means optimize for size without hurting performance,
1151 // do not reduce the limit.
1152 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1153 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1154 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1155 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1156 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1157 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1158 setPrefLoopAlignment(16);
1159 benefitFromCodePlacementOpt = true;
1161 setPrefFunctionAlignment(4);
1165 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1166 if (!VT.isVector()) return MVT::i8;
1167 return VT.changeVectorElementTypeToInteger();
1171 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1172 /// the desired ByVal argument alignment.
1173 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1176 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1177 if (VTy->getBitWidth() == 128)
1179 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1180 unsigned EltAlign = 0;
1181 getMaxByValAlign(ATy->getElementType(), EltAlign);
1182 if (EltAlign > MaxAlign)
1183 MaxAlign = EltAlign;
1184 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1185 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1186 unsigned EltAlign = 0;
1187 getMaxByValAlign(STy->getElementType(i), EltAlign);
1188 if (EltAlign > MaxAlign)
1189 MaxAlign = EltAlign;
1197 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1198 /// function arguments in the caller parameter area. For X86, aggregates
1199 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1200 /// are at 4-byte boundaries.
1201 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1202 if (Subtarget->is64Bit()) {
1203 // Max of 8 and alignment of type.
1204 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1211 if (Subtarget->hasXMM())
1212 getMaxByValAlign(Ty, Align);
1216 /// getOptimalMemOpType - Returns the target specific optimal type for load
1217 /// and store operations as a result of memset, memcpy, and memmove
1218 /// lowering. If DstAlign is zero that means it's safe to destination
1219 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1220 /// means there isn't a need to check it against alignment requirement,
1221 /// probably because the source does not need to be loaded. If
1222 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1223 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1224 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1225 /// constant so it does not need to be loaded.
1226 /// It returns EVT::Other if the type should be determined using generic
1227 /// target-independent logic.
1229 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1230 unsigned DstAlign, unsigned SrcAlign,
1231 bool NonScalarIntSafe,
1233 MachineFunction &MF) const {
1234 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1235 // linux. This is because the stack realignment code can't handle certain
1236 // cases like PR2962. This should be removed when PR2962 is fixed.
1237 const Function *F = MF.getFunction();
1238 if (NonScalarIntSafe &&
1239 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1241 (Subtarget->isUnalignedMemAccessFast() ||
1242 ((DstAlign == 0 || DstAlign >= 16) &&
1243 (SrcAlign == 0 || SrcAlign >= 16))) &&
1244 Subtarget->getStackAlignment() >= 16) {
1245 if (Subtarget->hasAVX() &&
1246 Subtarget->getStackAlignment() >= 32)
1248 if (Subtarget->hasXMMInt())
1250 if (Subtarget->hasXMM())
1252 } else if (!MemcpyStrSrc && Size >= 8 &&
1253 !Subtarget->is64Bit() &&
1254 Subtarget->getStackAlignment() >= 8 &&
1255 Subtarget->hasXMMInt()) {
1256 // Do not use f64 to lower memcpy if source is string constant. It's
1257 // better to use i32 to avoid the loads.
1261 if (Subtarget->is64Bit() && Size >= 8)
1266 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1267 /// current function. The returned value is a member of the
1268 /// MachineJumpTableInfo::JTEntryKind enum.
1269 unsigned X86TargetLowering::getJumpTableEncoding() const {
1270 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1272 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1273 Subtarget->isPICStyleGOT())
1274 return MachineJumpTableInfo::EK_Custom32;
1276 // Otherwise, use the normal jump table encoding heuristics.
1277 return TargetLowering::getJumpTableEncoding();
1281 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1282 const MachineBasicBlock *MBB,
1283 unsigned uid,MCContext &Ctx) const{
1284 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1285 Subtarget->isPICStyleGOT());
1286 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1288 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1289 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1292 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1294 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1295 SelectionDAG &DAG) const {
1296 if (!Subtarget->is64Bit())
1297 // This doesn't have DebugLoc associated with it, but is not really the
1298 // same as a Register.
1299 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1303 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1304 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1306 const MCExpr *X86TargetLowering::
1307 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1308 MCContext &Ctx) const {
1309 // X86-64 uses RIP relative addressing based on the jump table label.
1310 if (Subtarget->isPICStyleRIPRel())
1311 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1313 // Otherwise, the reference is relative to the PIC base.
1314 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1317 // FIXME: Why this routine is here? Move to RegInfo!
1318 std::pair<const TargetRegisterClass*, uint8_t>
1319 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1320 const TargetRegisterClass *RRC = 0;
1322 switch (VT.getSimpleVT().SimpleTy) {
1324 return TargetLowering::findRepresentativeClass(VT);
1325 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1326 RRC = (Subtarget->is64Bit()
1327 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1330 RRC = X86::VR64RegisterClass;
1332 case MVT::f32: case MVT::f64:
1333 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1334 case MVT::v4f32: case MVT::v2f64:
1335 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1337 RRC = X86::VR128RegisterClass;
1340 return std::make_pair(RRC, Cost);
1343 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1344 unsigned &Offset) const {
1345 if (!Subtarget->isTargetLinux())
1348 if (Subtarget->is64Bit()) {
1349 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1351 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1364 //===----------------------------------------------------------------------===//
1365 // Return Value Calling Convention Implementation
1366 //===----------------------------------------------------------------------===//
1368 #include "X86GenCallingConv.inc"
1371 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1372 MachineFunction &MF, bool isVarArg,
1373 const SmallVectorImpl<ISD::OutputArg> &Outs,
1374 LLVMContext &Context) const {
1375 SmallVector<CCValAssign, 16> RVLocs;
1376 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1378 return CCInfo.CheckReturn(Outs, RetCC_X86);
1382 X86TargetLowering::LowerReturn(SDValue Chain,
1383 CallingConv::ID CallConv, bool isVarArg,
1384 const SmallVectorImpl<ISD::OutputArg> &Outs,
1385 const SmallVectorImpl<SDValue> &OutVals,
1386 DebugLoc dl, SelectionDAG &DAG) const {
1387 MachineFunction &MF = DAG.getMachineFunction();
1388 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1390 SmallVector<CCValAssign, 16> RVLocs;
1391 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1392 RVLocs, *DAG.getContext());
1393 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1395 // Add the regs to the liveout set for the function.
1396 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1397 for (unsigned i = 0; i != RVLocs.size(); ++i)
1398 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1399 MRI.addLiveOut(RVLocs[i].getLocReg());
1403 SmallVector<SDValue, 6> RetOps;
1404 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1405 // Operand #1 = Bytes To Pop
1406 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1409 // Copy the result values into the output registers.
1410 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1411 CCValAssign &VA = RVLocs[i];
1412 assert(VA.isRegLoc() && "Can only return in registers!");
1413 SDValue ValToCopy = OutVals[i];
1414 EVT ValVT = ValToCopy.getValueType();
1416 // If this is x86-64, and we disabled SSE, we can't return FP values,
1417 // or SSE or MMX vectors.
1418 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1419 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1420 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1421 report_fatal_error("SSE register return with SSE disabled");
1423 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1424 // llvm-gcc has never done it right and no one has noticed, so this
1425 // should be OK for now.
1426 if (ValVT == MVT::f64 &&
1427 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1428 report_fatal_error("SSE2 register return with SSE2 disabled");
1430 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1431 // the RET instruction and handled by the FP Stackifier.
1432 if (VA.getLocReg() == X86::ST0 ||
1433 VA.getLocReg() == X86::ST1) {
1434 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1435 // change the value to the FP stack register class.
1436 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1437 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1438 RetOps.push_back(ValToCopy);
1439 // Don't emit a copytoreg.
1443 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1444 // which is returned in RAX / RDX.
1445 if (Subtarget->is64Bit()) {
1446 if (ValVT == MVT::x86mmx) {
1447 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1448 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1449 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1451 // If we don't have SSE2 available, convert to v4f32 so the generated
1452 // register is legal.
1453 if (!Subtarget->hasXMMInt())
1454 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1459 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1460 Flag = Chain.getValue(1);
1463 // The x86-64 ABI for returning structs by value requires that we copy
1464 // the sret argument into %rax for the return. We saved the argument into
1465 // a virtual register in the entry block, so now we copy the value out
1467 if (Subtarget->is64Bit() &&
1468 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1469 MachineFunction &MF = DAG.getMachineFunction();
1470 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1471 unsigned Reg = FuncInfo->getSRetReturnReg();
1473 "SRetReturnReg should have been set in LowerFormalArguments().");
1474 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1476 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1477 Flag = Chain.getValue(1);
1479 // RAX now acts like a return value.
1480 MRI.addLiveOut(X86::RAX);
1483 RetOps[0] = Chain; // Update chain.
1485 // Add the flag if we have it.
1487 RetOps.push_back(Flag);
1489 return DAG.getNode(X86ISD::RET_FLAG, dl,
1490 MVT::Other, &RetOps[0], RetOps.size());
1493 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1494 if (N->getNumValues() != 1)
1496 if (!N->hasNUsesOfValue(1, 0))
1499 SDNode *Copy = *N->use_begin();
1500 if (Copy->getOpcode() != ISD::CopyToReg &&
1501 Copy->getOpcode() != ISD::FP_EXTEND)
1504 bool HasRet = false;
1505 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1507 if (UI->getOpcode() != X86ISD::RET_FLAG)
1516 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1517 ISD::NodeType ExtendKind) const {
1519 // TODO: Is this also valid on 32-bit?
1520 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1521 ReturnMVT = MVT::i8;
1523 ReturnMVT = MVT::i32;
1525 EVT MinVT = getRegisterType(Context, ReturnMVT);
1526 return VT.bitsLT(MinVT) ? MinVT : VT;
1529 /// LowerCallResult - Lower the result values of a call into the
1530 /// appropriate copies out of appropriate physical registers.
1533 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1534 CallingConv::ID CallConv, bool isVarArg,
1535 const SmallVectorImpl<ISD::InputArg> &Ins,
1536 DebugLoc dl, SelectionDAG &DAG,
1537 SmallVectorImpl<SDValue> &InVals) const {
1539 // Assign locations to each value returned by this call.
1540 SmallVector<CCValAssign, 16> RVLocs;
1541 bool Is64Bit = Subtarget->is64Bit();
1542 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1543 getTargetMachine(), RVLocs, *DAG.getContext());
1544 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1546 // Copy all of the result registers out of their specified physreg.
1547 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1548 CCValAssign &VA = RVLocs[i];
1549 EVT CopyVT = VA.getValVT();
1551 // If this is x86-64, and we disabled SSE, we can't return FP values
1552 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1553 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1554 report_fatal_error("SSE register return with SSE disabled");
1559 // If this is a call to a function that returns an fp value on the floating
1560 // point stack, we must guarantee the the value is popped from the stack, so
1561 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1562 // if the return value is not used. We use the FpPOP_RETVAL instruction
1564 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1565 // If we prefer to use the value in xmm registers, copy it out as f80 and
1566 // use a truncate to move it from fp stack reg to xmm reg.
1567 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1568 SDValue Ops[] = { Chain, InFlag };
1569 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1570 MVT::Other, MVT::Glue, Ops, 2), 1);
1571 Val = Chain.getValue(0);
1573 // Round the f80 to the right size, which also moves it to the appropriate
1575 if (CopyVT != VA.getValVT())
1576 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1577 // This truncation won't change the value.
1578 DAG.getIntPtrConstant(1));
1580 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1581 CopyVT, InFlag).getValue(1);
1582 Val = Chain.getValue(0);
1584 InFlag = Chain.getValue(2);
1585 InVals.push_back(Val);
1592 //===----------------------------------------------------------------------===//
1593 // C & StdCall & Fast Calling Convention implementation
1594 //===----------------------------------------------------------------------===//
1595 // StdCall calling convention seems to be standard for many Windows' API
1596 // routines and around. It differs from C calling convention just a little:
1597 // callee should clean up the stack, not caller. Symbols should be also
1598 // decorated in some fancy way :) It doesn't support any vector arguments.
1599 // For info on fast calling convention see Fast Calling Convention (tail call)
1600 // implementation LowerX86_32FastCCCallTo.
1602 /// CallIsStructReturn - Determines whether a call uses struct return
1604 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1608 return Outs[0].Flags.isSRet();
1611 /// ArgsAreStructReturn - Determines whether a function uses struct
1612 /// return semantics.
1614 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1618 return Ins[0].Flags.isSRet();
1621 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1622 /// by "Src" to address "Dst" with size and alignment information specified by
1623 /// the specific parameter attribute. The copy will be passed as a byval
1624 /// function parameter.
1626 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1627 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1629 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1631 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1632 /*isVolatile*/false, /*AlwaysInline=*/true,
1633 MachinePointerInfo(), MachinePointerInfo());
1636 /// IsTailCallConvention - Return true if the calling convention is one that
1637 /// supports tail call optimization.
1638 static bool IsTailCallConvention(CallingConv::ID CC) {
1639 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1642 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1643 if (!CI->isTailCall())
1647 CallingConv::ID CalleeCC = CS.getCallingConv();
1648 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1654 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1655 /// a tailcall target by changing its ABI.
1656 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1657 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1661 X86TargetLowering::LowerMemArgument(SDValue Chain,
1662 CallingConv::ID CallConv,
1663 const SmallVectorImpl<ISD::InputArg> &Ins,
1664 DebugLoc dl, SelectionDAG &DAG,
1665 const CCValAssign &VA,
1666 MachineFrameInfo *MFI,
1668 // Create the nodes corresponding to a load from this parameter slot.
1669 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1670 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1671 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1674 // If value is passed by pointer we have address passed instead of the value
1676 if (VA.getLocInfo() == CCValAssign::Indirect)
1677 ValVT = VA.getLocVT();
1679 ValVT = VA.getValVT();
1681 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1682 // changed with more analysis.
1683 // In case of tail call optimization mark all arguments mutable. Since they
1684 // could be overwritten by lowering of arguments in case of a tail call.
1685 if (Flags.isByVal()) {
1686 unsigned Bytes = Flags.getByValSize();
1687 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1688 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1689 return DAG.getFrameIndex(FI, getPointerTy());
1691 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1692 VA.getLocMemOffset(), isImmutable);
1693 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1694 return DAG.getLoad(ValVT, dl, Chain, FIN,
1695 MachinePointerInfo::getFixedStack(FI),
1701 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1702 CallingConv::ID CallConv,
1704 const SmallVectorImpl<ISD::InputArg> &Ins,
1707 SmallVectorImpl<SDValue> &InVals)
1709 MachineFunction &MF = DAG.getMachineFunction();
1710 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1712 const Function* Fn = MF.getFunction();
1713 if (Fn->hasExternalLinkage() &&
1714 Subtarget->isTargetCygMing() &&
1715 Fn->getName() == "main")
1716 FuncInfo->setForceFramePointer(true);
1718 MachineFrameInfo *MFI = MF.getFrameInfo();
1719 bool Is64Bit = Subtarget->is64Bit();
1720 bool IsWin64 = Subtarget->isTargetWin64();
1722 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1723 "Var args not supported with calling convention fastcc or ghc");
1725 // Assign locations to all of the incoming arguments.
1726 SmallVector<CCValAssign, 16> ArgLocs;
1727 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1728 ArgLocs, *DAG.getContext());
1730 // Allocate shadow area for Win64
1732 CCInfo.AllocateStack(32, 8);
1735 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1737 unsigned LastVal = ~0U;
1739 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1740 CCValAssign &VA = ArgLocs[i];
1741 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1743 assert(VA.getValNo() != LastVal &&
1744 "Don't support value assigned to multiple locs yet");
1745 LastVal = VA.getValNo();
1747 if (VA.isRegLoc()) {
1748 EVT RegVT = VA.getLocVT();
1749 TargetRegisterClass *RC = NULL;
1750 if (RegVT == MVT::i32)
1751 RC = X86::GR32RegisterClass;
1752 else if (Is64Bit && RegVT == MVT::i64)
1753 RC = X86::GR64RegisterClass;
1754 else if (RegVT == MVT::f32)
1755 RC = X86::FR32RegisterClass;
1756 else if (RegVT == MVT::f64)
1757 RC = X86::FR64RegisterClass;
1758 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1759 RC = X86::VR256RegisterClass;
1760 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1761 RC = X86::VR128RegisterClass;
1762 else if (RegVT == MVT::x86mmx)
1763 RC = X86::VR64RegisterClass;
1765 llvm_unreachable("Unknown argument type!");
1767 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1768 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1770 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1771 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1773 if (VA.getLocInfo() == CCValAssign::SExt)
1774 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1775 DAG.getValueType(VA.getValVT()));
1776 else if (VA.getLocInfo() == CCValAssign::ZExt)
1777 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1778 DAG.getValueType(VA.getValVT()));
1779 else if (VA.getLocInfo() == CCValAssign::BCvt)
1780 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1782 if (VA.isExtInLoc()) {
1783 // Handle MMX values passed in XMM regs.
1784 if (RegVT.isVector()) {
1785 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1788 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1791 assert(VA.isMemLoc());
1792 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1795 // If value is passed via pointer - do a load.
1796 if (VA.getLocInfo() == CCValAssign::Indirect)
1797 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1798 MachinePointerInfo(), false, false, 0);
1800 InVals.push_back(ArgValue);
1803 // The x86-64 ABI for returning structs by value requires that we copy
1804 // the sret argument into %rax for the return. Save the argument into
1805 // a virtual register so that we can access it from the return points.
1806 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1807 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1808 unsigned Reg = FuncInfo->getSRetReturnReg();
1810 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1811 FuncInfo->setSRetReturnReg(Reg);
1813 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1814 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1817 unsigned StackSize = CCInfo.getNextStackOffset();
1818 // Align stack specially for tail calls.
1819 if (FuncIsMadeTailCallSafe(CallConv))
1820 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1822 // If the function takes variable number of arguments, make a frame index for
1823 // the start of the first vararg value... for expansion of llvm.va_start.
1825 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1826 CallConv != CallingConv::X86_ThisCall)) {
1827 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1830 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1832 // FIXME: We should really autogenerate these arrays
1833 static const unsigned GPR64ArgRegsWin64[] = {
1834 X86::RCX, X86::RDX, X86::R8, X86::R9
1836 static const unsigned GPR64ArgRegs64Bit[] = {
1837 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1839 static const unsigned XMMArgRegs64Bit[] = {
1840 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1841 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1843 const unsigned *GPR64ArgRegs;
1844 unsigned NumXMMRegs = 0;
1847 // The XMM registers which might contain var arg parameters are shadowed
1848 // in their paired GPR. So we only need to save the GPR to their home
1850 TotalNumIntRegs = 4;
1851 GPR64ArgRegs = GPR64ArgRegsWin64;
1853 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1854 GPR64ArgRegs = GPR64ArgRegs64Bit;
1856 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1858 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1861 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1862 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1863 "SSE register cannot be used when SSE is disabled!");
1864 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1865 "SSE register cannot be used when SSE is disabled!");
1866 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1867 // Kernel mode asks for SSE to be disabled, so don't push them
1869 TotalNumXMMRegs = 0;
1872 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1873 // Get to the caller-allocated home save location. Add 8 to account
1874 // for the return address.
1875 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1876 FuncInfo->setRegSaveFrameIndex(
1877 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1878 // Fixup to set vararg frame on shadow area (4 x i64).
1880 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1882 // For X86-64, if there are vararg parameters that are passed via
1883 // registers, then we must store them to their spots on the stack so they
1884 // may be loaded by deferencing the result of va_next.
1885 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1886 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1887 FuncInfo->setRegSaveFrameIndex(
1888 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1892 // Store the integer parameter registers.
1893 SmallVector<SDValue, 8> MemOps;
1894 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1896 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1897 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1898 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1899 DAG.getIntPtrConstant(Offset));
1900 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1901 X86::GR64RegisterClass);
1902 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1904 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1905 MachinePointerInfo::getFixedStack(
1906 FuncInfo->getRegSaveFrameIndex(), Offset),
1908 MemOps.push_back(Store);
1912 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1913 // Now store the XMM (fp + vector) parameter registers.
1914 SmallVector<SDValue, 11> SaveXMMOps;
1915 SaveXMMOps.push_back(Chain);
1917 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1918 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1919 SaveXMMOps.push_back(ALVal);
1921 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1922 FuncInfo->getRegSaveFrameIndex()));
1923 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1924 FuncInfo->getVarArgsFPOffset()));
1926 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1927 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1928 X86::VR128RegisterClass);
1929 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1930 SaveXMMOps.push_back(Val);
1932 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1934 &SaveXMMOps[0], SaveXMMOps.size()));
1937 if (!MemOps.empty())
1938 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1939 &MemOps[0], MemOps.size());
1943 // Some CCs need callee pop.
1944 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
1945 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1947 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1948 // If this is an sret function, the return should pop the hidden pointer.
1949 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1950 FuncInfo->setBytesToPopOnReturn(4);
1954 // RegSaveFrameIndex is X86-64 only.
1955 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1956 if (CallConv == CallingConv::X86_FastCall ||
1957 CallConv == CallingConv::X86_ThisCall)
1958 // fastcc functions can't have varargs.
1959 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1962 FuncInfo->setArgumentStackSize(StackSize);
1968 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1969 SDValue StackPtr, SDValue Arg,
1970 DebugLoc dl, SelectionDAG &DAG,
1971 const CCValAssign &VA,
1972 ISD::ArgFlagsTy Flags) const {
1973 unsigned LocMemOffset = VA.getLocMemOffset();
1974 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1975 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1976 if (Flags.isByVal())
1977 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1979 return DAG.getStore(Chain, dl, Arg, PtrOff,
1980 MachinePointerInfo::getStack(LocMemOffset),
1984 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1985 /// optimization is performed and it is required.
1987 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1988 SDValue &OutRetAddr, SDValue Chain,
1989 bool IsTailCall, bool Is64Bit,
1990 int FPDiff, DebugLoc dl) const {
1991 // Adjust the Return address stack slot.
1992 EVT VT = getPointerTy();
1993 OutRetAddr = getReturnAddressFrameIndex(DAG);
1995 // Load the "old" Return address.
1996 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1998 return SDValue(OutRetAddr.getNode(), 1);
2001 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2002 /// optimization is performed and it is required (FPDiff!=0).
2004 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2005 SDValue Chain, SDValue RetAddrFrIdx,
2006 bool Is64Bit, int FPDiff, DebugLoc dl) {
2007 // Store the return address to the appropriate stack slot.
2008 if (!FPDiff) return Chain;
2009 // Calculate the new stack slot for the return address.
2010 int SlotSize = Is64Bit ? 8 : 4;
2011 int NewReturnAddrFI =
2012 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2013 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2014 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2015 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2016 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2022 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2023 CallingConv::ID CallConv, bool isVarArg,
2025 const SmallVectorImpl<ISD::OutputArg> &Outs,
2026 const SmallVectorImpl<SDValue> &OutVals,
2027 const SmallVectorImpl<ISD::InputArg> &Ins,
2028 DebugLoc dl, SelectionDAG &DAG,
2029 SmallVectorImpl<SDValue> &InVals) const {
2030 MachineFunction &MF = DAG.getMachineFunction();
2031 bool Is64Bit = Subtarget->is64Bit();
2032 bool IsWin64 = Subtarget->isTargetWin64();
2033 bool IsStructRet = CallIsStructReturn(Outs);
2034 bool IsSibcall = false;
2037 // Check if it's really possible to do a tail call.
2038 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2039 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2040 Outs, OutVals, Ins, DAG);
2042 // Sibcalls are automatically detected tailcalls which do not require
2044 if (!GuaranteedTailCallOpt && isTailCall)
2051 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2052 "Var args not supported with calling convention fastcc or ghc");
2054 // Analyze operands of the call, assigning locations to each operand.
2055 SmallVector<CCValAssign, 16> ArgLocs;
2056 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2057 ArgLocs, *DAG.getContext());
2059 // Allocate shadow area for Win64
2061 CCInfo.AllocateStack(32, 8);
2064 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2066 // Get a count of how many bytes are to be pushed on the stack.
2067 unsigned NumBytes = CCInfo.getNextStackOffset();
2069 // This is a sibcall. The memory operands are available in caller's
2070 // own caller's stack.
2072 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2073 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2076 if (isTailCall && !IsSibcall) {
2077 // Lower arguments at fp - stackoffset + fpdiff.
2078 unsigned NumBytesCallerPushed =
2079 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2080 FPDiff = NumBytesCallerPushed - NumBytes;
2082 // Set the delta of movement of the returnaddr stackslot.
2083 // But only set if delta is greater than previous delta.
2084 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2085 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2089 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2091 SDValue RetAddrFrIdx;
2092 // Load return address for tail calls.
2093 if (isTailCall && FPDiff)
2094 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2095 Is64Bit, FPDiff, dl);
2097 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2098 SmallVector<SDValue, 8> MemOpChains;
2101 // Walk the register/memloc assignments, inserting copies/loads. In the case
2102 // of tail call optimization arguments are handle later.
2103 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2104 CCValAssign &VA = ArgLocs[i];
2105 EVT RegVT = VA.getLocVT();
2106 SDValue Arg = OutVals[i];
2107 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2108 bool isByVal = Flags.isByVal();
2110 // Promote the value if needed.
2111 switch (VA.getLocInfo()) {
2112 default: llvm_unreachable("Unknown loc info!");
2113 case CCValAssign::Full: break;
2114 case CCValAssign::SExt:
2115 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2117 case CCValAssign::ZExt:
2118 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2120 case CCValAssign::AExt:
2121 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2122 // Special case: passing MMX values in XMM registers.
2123 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2124 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2125 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2127 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2129 case CCValAssign::BCvt:
2130 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2132 case CCValAssign::Indirect: {
2133 // Store the argument.
2134 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2135 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2136 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2137 MachinePointerInfo::getFixedStack(FI),
2144 if (VA.isRegLoc()) {
2145 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2146 if (isVarArg && IsWin64) {
2147 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2148 // shadow reg if callee is a varargs function.
2149 unsigned ShadowReg = 0;
2150 switch (VA.getLocReg()) {
2151 case X86::XMM0: ShadowReg = X86::RCX; break;
2152 case X86::XMM1: ShadowReg = X86::RDX; break;
2153 case X86::XMM2: ShadowReg = X86::R8; break;
2154 case X86::XMM3: ShadowReg = X86::R9; break;
2157 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2159 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2160 assert(VA.isMemLoc());
2161 if (StackPtr.getNode() == 0)
2162 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2163 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2164 dl, DAG, VA, Flags));
2168 if (!MemOpChains.empty())
2169 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2170 &MemOpChains[0], MemOpChains.size());
2172 // Build a sequence of copy-to-reg nodes chained together with token chain
2173 // and flag operands which copy the outgoing args into registers.
2175 // Tail call byval lowering might overwrite argument registers so in case of
2176 // tail call optimization the copies to registers are lowered later.
2178 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2179 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2180 RegsToPass[i].second, InFlag);
2181 InFlag = Chain.getValue(1);
2184 if (Subtarget->isPICStyleGOT()) {
2185 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2188 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2189 DAG.getNode(X86ISD::GlobalBaseReg,
2190 DebugLoc(), getPointerTy()),
2192 InFlag = Chain.getValue(1);
2194 // If we are tail calling and generating PIC/GOT style code load the
2195 // address of the callee into ECX. The value in ecx is used as target of
2196 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2197 // for tail calls on PIC/GOT architectures. Normally we would just put the
2198 // address of GOT into ebx and then call target@PLT. But for tail calls
2199 // ebx would be restored (since ebx is callee saved) before jumping to the
2202 // Note: The actual moving to ECX is done further down.
2203 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2204 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2205 !G->getGlobal()->hasProtectedVisibility())
2206 Callee = LowerGlobalAddress(Callee, DAG);
2207 else if (isa<ExternalSymbolSDNode>(Callee))
2208 Callee = LowerExternalSymbol(Callee, DAG);
2212 if (Is64Bit && isVarArg && !IsWin64) {
2213 // From AMD64 ABI document:
2214 // For calls that may call functions that use varargs or stdargs
2215 // (prototype-less calls or calls to functions containing ellipsis (...) in
2216 // the declaration) %al is used as hidden argument to specify the number
2217 // of SSE registers used. The contents of %al do not need to match exactly
2218 // the number of registers, but must be an ubound on the number of SSE
2219 // registers used and is in the range 0 - 8 inclusive.
2221 // Count the number of XMM registers allocated.
2222 static const unsigned XMMArgRegs[] = {
2223 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2224 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2226 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2227 assert((Subtarget->hasXMM() || !NumXMMRegs)
2228 && "SSE registers cannot be used when SSE is disabled");
2230 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2231 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2232 InFlag = Chain.getValue(1);
2236 // For tail calls lower the arguments to the 'real' stack slot.
2238 // Force all the incoming stack arguments to be loaded from the stack
2239 // before any new outgoing arguments are stored to the stack, because the
2240 // outgoing stack slots may alias the incoming argument stack slots, and
2241 // the alias isn't otherwise explicit. This is slightly more conservative
2242 // than necessary, because it means that each store effectively depends
2243 // on every argument instead of just those arguments it would clobber.
2244 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2246 SmallVector<SDValue, 8> MemOpChains2;
2249 // Do not flag preceding copytoreg stuff together with the following stuff.
2251 if (GuaranteedTailCallOpt) {
2252 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2253 CCValAssign &VA = ArgLocs[i];
2256 assert(VA.isMemLoc());
2257 SDValue Arg = OutVals[i];
2258 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2259 // Create frame index.
2260 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2261 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2262 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2263 FIN = DAG.getFrameIndex(FI, getPointerTy());
2265 if (Flags.isByVal()) {
2266 // Copy relative to framepointer.
2267 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2268 if (StackPtr.getNode() == 0)
2269 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2271 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2273 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2277 // Store relative to framepointer.
2278 MemOpChains2.push_back(
2279 DAG.getStore(ArgChain, dl, Arg, FIN,
2280 MachinePointerInfo::getFixedStack(FI),
2286 if (!MemOpChains2.empty())
2287 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2288 &MemOpChains2[0], MemOpChains2.size());
2290 // Copy arguments to their registers.
2291 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2292 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2293 RegsToPass[i].second, InFlag);
2294 InFlag = Chain.getValue(1);
2298 // Store the return address to the appropriate stack slot.
2299 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2303 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2304 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2305 // In the 64-bit large code model, we have to make all calls
2306 // through a register, since the call instruction's 32-bit
2307 // pc-relative offset may not be large enough to hold the whole
2309 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2310 // If the callee is a GlobalAddress node (quite common, every direct call
2311 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2314 // We should use extra load for direct calls to dllimported functions in
2316 const GlobalValue *GV = G->getGlobal();
2317 if (!GV->hasDLLImportLinkage()) {
2318 unsigned char OpFlags = 0;
2319 bool ExtraLoad = false;
2320 unsigned WrapperKind = ISD::DELETED_NODE;
2322 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2323 // external symbols most go through the PLT in PIC mode. If the symbol
2324 // has hidden or protected visibility, or if it is static or local, then
2325 // we don't need to use the PLT - we can directly call it.
2326 if (Subtarget->isTargetELF() &&
2327 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2328 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2329 OpFlags = X86II::MO_PLT;
2330 } else if (Subtarget->isPICStyleStubAny() &&
2331 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2332 (!Subtarget->getTargetTriple().isMacOSX() ||
2333 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2334 // PC-relative references to external symbols should go through $stub,
2335 // unless we're building with the leopard linker or later, which
2336 // automatically synthesizes these stubs.
2337 OpFlags = X86II::MO_DARWIN_STUB;
2338 } else if (Subtarget->isPICStyleRIPRel() &&
2339 isa<Function>(GV) &&
2340 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2341 // If the function is marked as non-lazy, generate an indirect call
2342 // which loads from the GOT directly. This avoids runtime overhead
2343 // at the cost of eager binding (and one extra byte of encoding).
2344 OpFlags = X86II::MO_GOTPCREL;
2345 WrapperKind = X86ISD::WrapperRIP;
2349 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2350 G->getOffset(), OpFlags);
2352 // Add a wrapper if needed.
2353 if (WrapperKind != ISD::DELETED_NODE)
2354 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2355 // Add extra indirection if needed.
2357 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2358 MachinePointerInfo::getGOT(),
2361 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2362 unsigned char OpFlags = 0;
2364 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2365 // external symbols should go through the PLT.
2366 if (Subtarget->isTargetELF() &&
2367 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2368 OpFlags = X86II::MO_PLT;
2369 } else if (Subtarget->isPICStyleStubAny() &&
2370 (!Subtarget->getTargetTriple().isMacOSX() ||
2371 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2372 // PC-relative references to external symbols should go through $stub,
2373 // unless we're building with the leopard linker or later, which
2374 // automatically synthesizes these stubs.
2375 OpFlags = X86II::MO_DARWIN_STUB;
2378 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2382 // Returns a chain & a flag for retval copy to use.
2383 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2384 SmallVector<SDValue, 8> Ops;
2386 if (!IsSibcall && isTailCall) {
2387 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2388 DAG.getIntPtrConstant(0, true), InFlag);
2389 InFlag = Chain.getValue(1);
2392 Ops.push_back(Chain);
2393 Ops.push_back(Callee);
2396 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2398 // Add argument registers to the end of the list so that they are known live
2400 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2401 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2402 RegsToPass[i].second.getValueType()));
2404 // Add an implicit use GOT pointer in EBX.
2405 if (!isTailCall && Subtarget->isPICStyleGOT())
2406 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2408 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2409 if (Is64Bit && isVarArg && !IsWin64)
2410 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2412 if (InFlag.getNode())
2413 Ops.push_back(InFlag);
2417 //// If this is the first return lowered for this function, add the regs
2418 //// to the liveout set for the function.
2419 // This isn't right, although it's probably harmless on x86; liveouts
2420 // should be computed from returns not tail calls. Consider a void
2421 // function making a tail call to a function returning int.
2422 return DAG.getNode(X86ISD::TC_RETURN, dl,
2423 NodeTys, &Ops[0], Ops.size());
2426 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2427 InFlag = Chain.getValue(1);
2429 // Create the CALLSEQ_END node.
2430 unsigned NumBytesForCalleeToPush;
2431 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2432 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2433 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2434 // If this is a call to a struct-return function, the callee
2435 // pops the hidden struct pointer, so we have to push it back.
2436 // This is common for Darwin/X86, Linux & Mingw32 targets.
2437 NumBytesForCalleeToPush = 4;
2439 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2441 // Returns a flag for retval copy to use.
2443 Chain = DAG.getCALLSEQ_END(Chain,
2444 DAG.getIntPtrConstant(NumBytes, true),
2445 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2448 InFlag = Chain.getValue(1);
2451 // Handle result values, copying them out of physregs into vregs that we
2453 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2454 Ins, dl, DAG, InVals);
2458 //===----------------------------------------------------------------------===//
2459 // Fast Calling Convention (tail call) implementation
2460 //===----------------------------------------------------------------------===//
2462 // Like std call, callee cleans arguments, convention except that ECX is
2463 // reserved for storing the tail called function address. Only 2 registers are
2464 // free for argument passing (inreg). Tail call optimization is performed
2466 // * tailcallopt is enabled
2467 // * caller/callee are fastcc
2468 // On X86_64 architecture with GOT-style position independent code only local
2469 // (within module) calls are supported at the moment.
2470 // To keep the stack aligned according to platform abi the function
2471 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2472 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2473 // If a tail called function callee has more arguments than the caller the
2474 // caller needs to make sure that there is room to move the RETADDR to. This is
2475 // achieved by reserving an area the size of the argument delta right after the
2476 // original REtADDR, but before the saved framepointer or the spilled registers
2477 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2489 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2490 /// for a 16 byte align requirement.
2492 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2493 SelectionDAG& DAG) const {
2494 MachineFunction &MF = DAG.getMachineFunction();
2495 const TargetMachine &TM = MF.getTarget();
2496 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2497 unsigned StackAlignment = TFI.getStackAlignment();
2498 uint64_t AlignMask = StackAlignment - 1;
2499 int64_t Offset = StackSize;
2500 uint64_t SlotSize = TD->getPointerSize();
2501 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2502 // Number smaller than 12 so just add the difference.
2503 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2505 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2506 Offset = ((~AlignMask) & Offset) + StackAlignment +
2507 (StackAlignment-SlotSize);
2512 /// MatchingStackOffset - Return true if the given stack call argument is
2513 /// already available in the same position (relatively) of the caller's
2514 /// incoming argument stack.
2516 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2517 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2518 const X86InstrInfo *TII) {
2519 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2521 if (Arg.getOpcode() == ISD::CopyFromReg) {
2522 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2523 if (!TargetRegisterInfo::isVirtualRegister(VR))
2525 MachineInstr *Def = MRI->getVRegDef(VR);
2528 if (!Flags.isByVal()) {
2529 if (!TII->isLoadFromStackSlot(Def, FI))
2532 unsigned Opcode = Def->getOpcode();
2533 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2534 Def->getOperand(1).isFI()) {
2535 FI = Def->getOperand(1).getIndex();
2536 Bytes = Flags.getByValSize();
2540 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2541 if (Flags.isByVal())
2542 // ByVal argument is passed in as a pointer but it's now being
2543 // dereferenced. e.g.
2544 // define @foo(%struct.X* %A) {
2545 // tail call @bar(%struct.X* byval %A)
2548 SDValue Ptr = Ld->getBasePtr();
2549 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2552 FI = FINode->getIndex();
2553 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2554 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2555 FI = FINode->getIndex();
2556 Bytes = Flags.getByValSize();
2560 assert(FI != INT_MAX);
2561 if (!MFI->isFixedObjectIndex(FI))
2563 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2566 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2567 /// for tail call optimization. Targets which want to do tail call
2568 /// optimization should implement this function.
2570 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2571 CallingConv::ID CalleeCC,
2573 bool isCalleeStructRet,
2574 bool isCallerStructRet,
2575 const SmallVectorImpl<ISD::OutputArg> &Outs,
2576 const SmallVectorImpl<SDValue> &OutVals,
2577 const SmallVectorImpl<ISD::InputArg> &Ins,
2578 SelectionDAG& DAG) const {
2579 if (!IsTailCallConvention(CalleeCC) &&
2580 CalleeCC != CallingConv::C)
2583 // If -tailcallopt is specified, make fastcc functions tail-callable.
2584 const MachineFunction &MF = DAG.getMachineFunction();
2585 const Function *CallerF = DAG.getMachineFunction().getFunction();
2586 CallingConv::ID CallerCC = CallerF->getCallingConv();
2587 bool CCMatch = CallerCC == CalleeCC;
2589 if (GuaranteedTailCallOpt) {
2590 if (IsTailCallConvention(CalleeCC) && CCMatch)
2595 // Look for obvious safe cases to perform tail call optimization that do not
2596 // require ABI changes. This is what gcc calls sibcall.
2598 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2599 // emit a special epilogue.
2600 if (RegInfo->needsStackRealignment(MF))
2603 // Also avoid sibcall optimization if either caller or callee uses struct
2604 // return semantics.
2605 if (isCalleeStructRet || isCallerStructRet)
2608 // An stdcall caller is expected to clean up its arguments; the callee
2609 // isn't going to do that.
2610 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2613 // Do not sibcall optimize vararg calls unless all arguments are passed via
2615 if (isVarArg && !Outs.empty()) {
2617 // Optimizing for varargs on Win64 is unlikely to be safe without
2618 // additional testing.
2619 if (Subtarget->isTargetWin64())
2622 SmallVector<CCValAssign, 16> ArgLocs;
2623 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2624 getTargetMachine(), ArgLocs, *DAG.getContext());
2626 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2627 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2628 if (!ArgLocs[i].isRegLoc())
2632 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2633 // Therefore if it's not used by the call it is not safe to optimize this into
2635 bool Unused = false;
2636 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2643 SmallVector<CCValAssign, 16> RVLocs;
2644 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2645 getTargetMachine(), RVLocs, *DAG.getContext());
2646 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2647 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2648 CCValAssign &VA = RVLocs[i];
2649 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2654 // If the calling conventions do not match, then we'd better make sure the
2655 // results are returned in the same way as what the caller expects.
2657 SmallVector<CCValAssign, 16> RVLocs1;
2658 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2659 getTargetMachine(), RVLocs1, *DAG.getContext());
2660 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2662 SmallVector<CCValAssign, 16> RVLocs2;
2663 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2664 getTargetMachine(), RVLocs2, *DAG.getContext());
2665 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2667 if (RVLocs1.size() != RVLocs2.size())
2669 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2670 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2672 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2674 if (RVLocs1[i].isRegLoc()) {
2675 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2678 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2684 // If the callee takes no arguments then go on to check the results of the
2686 if (!Outs.empty()) {
2687 // Check if stack adjustment is needed. For now, do not do this if any
2688 // argument is passed on the stack.
2689 SmallVector<CCValAssign, 16> ArgLocs;
2690 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2691 getTargetMachine(), ArgLocs, *DAG.getContext());
2693 // Allocate shadow area for Win64
2694 if (Subtarget->isTargetWin64()) {
2695 CCInfo.AllocateStack(32, 8);
2698 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2699 if (CCInfo.getNextStackOffset()) {
2700 MachineFunction &MF = DAG.getMachineFunction();
2701 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2704 // Check if the arguments are already laid out in the right way as
2705 // the caller's fixed stack objects.
2706 MachineFrameInfo *MFI = MF.getFrameInfo();
2707 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2708 const X86InstrInfo *TII =
2709 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2710 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2711 CCValAssign &VA = ArgLocs[i];
2712 SDValue Arg = OutVals[i];
2713 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2714 if (VA.getLocInfo() == CCValAssign::Indirect)
2716 if (!VA.isRegLoc()) {
2717 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2724 // If the tailcall address may be in a register, then make sure it's
2725 // possible to register allocate for it. In 32-bit, the call address can
2726 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2727 // callee-saved registers are restored. These happen to be the same
2728 // registers used to pass 'inreg' arguments so watch out for those.
2729 if (!Subtarget->is64Bit() &&
2730 !isa<GlobalAddressSDNode>(Callee) &&
2731 !isa<ExternalSymbolSDNode>(Callee)) {
2732 unsigned NumInRegs = 0;
2733 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2734 CCValAssign &VA = ArgLocs[i];
2737 unsigned Reg = VA.getLocReg();
2740 case X86::EAX: case X86::EDX: case X86::ECX:
2741 if (++NumInRegs == 3)
2753 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2754 return X86::createFastISel(funcInfo);
2758 //===----------------------------------------------------------------------===//
2759 // Other Lowering Hooks
2760 //===----------------------------------------------------------------------===//
2762 static bool MayFoldLoad(SDValue Op) {
2763 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2766 static bool MayFoldIntoStore(SDValue Op) {
2767 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2770 static bool isTargetShuffle(unsigned Opcode) {
2772 default: return false;
2773 case X86ISD::PSHUFD:
2774 case X86ISD::PSHUFHW:
2775 case X86ISD::PSHUFLW:
2776 case X86ISD::SHUFPD:
2777 case X86ISD::PALIGN:
2778 case X86ISD::SHUFPS:
2779 case X86ISD::MOVLHPS:
2780 case X86ISD::MOVLHPD:
2781 case X86ISD::MOVHLPS:
2782 case X86ISD::MOVLPS:
2783 case X86ISD::MOVLPD:
2784 case X86ISD::MOVSHDUP:
2785 case X86ISD::MOVSLDUP:
2786 case X86ISD::MOVDDUP:
2789 case X86ISD::UNPCKLPS:
2790 case X86ISD::UNPCKLPD:
2791 case X86ISD::VUNPCKLPSY:
2792 case X86ISD::VUNPCKLPDY:
2793 case X86ISD::PUNPCKLWD:
2794 case X86ISD::PUNPCKLBW:
2795 case X86ISD::PUNPCKLDQ:
2796 case X86ISD::PUNPCKLQDQ:
2797 case X86ISD::UNPCKHPS:
2798 case X86ISD::UNPCKHPD:
2799 case X86ISD::VUNPCKHPSY:
2800 case X86ISD::VUNPCKHPDY:
2801 case X86ISD::PUNPCKHWD:
2802 case X86ISD::PUNPCKHBW:
2803 case X86ISD::PUNPCKHDQ:
2804 case X86ISD::PUNPCKHQDQ:
2805 case X86ISD::VPERMILPS:
2806 case X86ISD::VPERMILPSY:
2807 case X86ISD::VPERMILPD:
2808 case X86ISD::VPERMILPDY:
2809 case X86ISD::VPERM2F128:
2815 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2816 SDValue V1, SelectionDAG &DAG) {
2818 default: llvm_unreachable("Unknown x86 shuffle node");
2819 case X86ISD::MOVSHDUP:
2820 case X86ISD::MOVSLDUP:
2821 case X86ISD::MOVDDUP:
2822 return DAG.getNode(Opc, dl, VT, V1);
2828 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2829 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2831 default: llvm_unreachable("Unknown x86 shuffle node");
2832 case X86ISD::PSHUFD:
2833 case X86ISD::PSHUFHW:
2834 case X86ISD::PSHUFLW:
2835 case X86ISD::VPERMILPS:
2836 case X86ISD::VPERMILPSY:
2837 case X86ISD::VPERMILPD:
2838 case X86ISD::VPERMILPDY:
2839 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2845 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2846 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2848 default: llvm_unreachable("Unknown x86 shuffle node");
2849 case X86ISD::PALIGN:
2850 case X86ISD::SHUFPD:
2851 case X86ISD::SHUFPS:
2852 case X86ISD::VPERM2F128:
2853 return DAG.getNode(Opc, dl, VT, V1, V2,
2854 DAG.getConstant(TargetMask, MVT::i8));
2859 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2860 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2862 default: llvm_unreachable("Unknown x86 shuffle node");
2863 case X86ISD::MOVLHPS:
2864 case X86ISD::MOVLHPD:
2865 case X86ISD::MOVHLPS:
2866 case X86ISD::MOVLPS:
2867 case X86ISD::MOVLPD:
2870 case X86ISD::UNPCKLPS:
2871 case X86ISD::UNPCKLPD:
2872 case X86ISD::VUNPCKLPSY:
2873 case X86ISD::VUNPCKLPDY:
2874 case X86ISD::PUNPCKLWD:
2875 case X86ISD::PUNPCKLBW:
2876 case X86ISD::PUNPCKLDQ:
2877 case X86ISD::PUNPCKLQDQ:
2878 case X86ISD::UNPCKHPS:
2879 case X86ISD::UNPCKHPD:
2880 case X86ISD::VUNPCKHPSY:
2881 case X86ISD::VUNPCKHPDY:
2882 case X86ISD::PUNPCKHWD:
2883 case X86ISD::PUNPCKHBW:
2884 case X86ISD::PUNPCKHDQ:
2885 case X86ISD::PUNPCKHQDQ:
2886 return DAG.getNode(Opc, dl, VT, V1, V2);
2891 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2892 MachineFunction &MF = DAG.getMachineFunction();
2893 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2894 int ReturnAddrIndex = FuncInfo->getRAIndex();
2896 if (ReturnAddrIndex == 0) {
2897 // Set up a frame object for the return address.
2898 uint64_t SlotSize = TD->getPointerSize();
2899 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2901 FuncInfo->setRAIndex(ReturnAddrIndex);
2904 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2908 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2909 bool hasSymbolicDisplacement) {
2910 // Offset should fit into 32 bit immediate field.
2911 if (!isInt<32>(Offset))
2914 // If we don't have a symbolic displacement - we don't have any extra
2916 if (!hasSymbolicDisplacement)
2919 // FIXME: Some tweaks might be needed for medium code model.
2920 if (M != CodeModel::Small && M != CodeModel::Kernel)
2923 // For small code model we assume that latest object is 16MB before end of 31
2924 // bits boundary. We may also accept pretty large negative constants knowing
2925 // that all objects are in the positive half of address space.
2926 if (M == CodeModel::Small && Offset < 16*1024*1024)
2929 // For kernel code model we know that all object resist in the negative half
2930 // of 32bits address space. We may not accept negative offsets, since they may
2931 // be just off and we may accept pretty large positive ones.
2932 if (M == CodeModel::Kernel && Offset > 0)
2938 /// isCalleePop - Determines whether the callee is required to pop its
2939 /// own arguments. Callee pop is necessary to support tail calls.
2940 bool X86::isCalleePop(CallingConv::ID CallingConv,
2941 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2945 switch (CallingConv) {
2948 case CallingConv::X86_StdCall:
2950 case CallingConv::X86_FastCall:
2952 case CallingConv::X86_ThisCall:
2954 case CallingConv::Fast:
2956 case CallingConv::GHC:
2961 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2962 /// specific condition code, returning the condition code and the LHS/RHS of the
2963 /// comparison to make.
2964 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2965 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2967 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2968 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2969 // X > -1 -> X == 0, jump !sign.
2970 RHS = DAG.getConstant(0, RHS.getValueType());
2971 return X86::COND_NS;
2972 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2973 // X < 0 -> X == 0, jump on sign.
2975 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2977 RHS = DAG.getConstant(0, RHS.getValueType());
2978 return X86::COND_LE;
2982 switch (SetCCOpcode) {
2983 default: llvm_unreachable("Invalid integer condition!");
2984 case ISD::SETEQ: return X86::COND_E;
2985 case ISD::SETGT: return X86::COND_G;
2986 case ISD::SETGE: return X86::COND_GE;
2987 case ISD::SETLT: return X86::COND_L;
2988 case ISD::SETLE: return X86::COND_LE;
2989 case ISD::SETNE: return X86::COND_NE;
2990 case ISD::SETULT: return X86::COND_B;
2991 case ISD::SETUGT: return X86::COND_A;
2992 case ISD::SETULE: return X86::COND_BE;
2993 case ISD::SETUGE: return X86::COND_AE;
2997 // First determine if it is required or is profitable to flip the operands.
2999 // If LHS is a foldable load, but RHS is not, flip the condition.
3000 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3001 !ISD::isNON_EXTLoad(RHS.getNode())) {
3002 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3003 std::swap(LHS, RHS);
3006 switch (SetCCOpcode) {
3012 std::swap(LHS, RHS);
3016 // On a floating point condition, the flags are set as follows:
3018 // 0 | 0 | 0 | X > Y
3019 // 0 | 0 | 1 | X < Y
3020 // 1 | 0 | 0 | X == Y
3021 // 1 | 1 | 1 | unordered
3022 switch (SetCCOpcode) {
3023 default: llvm_unreachable("Condcode should be pre-legalized away");
3025 case ISD::SETEQ: return X86::COND_E;
3026 case ISD::SETOLT: // flipped
3028 case ISD::SETGT: return X86::COND_A;
3029 case ISD::SETOLE: // flipped
3031 case ISD::SETGE: return X86::COND_AE;
3032 case ISD::SETUGT: // flipped
3034 case ISD::SETLT: return X86::COND_B;
3035 case ISD::SETUGE: // flipped
3037 case ISD::SETLE: return X86::COND_BE;
3039 case ISD::SETNE: return X86::COND_NE;
3040 case ISD::SETUO: return X86::COND_P;
3041 case ISD::SETO: return X86::COND_NP;
3043 case ISD::SETUNE: return X86::COND_INVALID;
3047 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3048 /// code. Current x86 isa includes the following FP cmov instructions:
3049 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3050 static bool hasFPCMov(unsigned X86CC) {
3066 /// isFPImmLegal - Returns true if the target can instruction select the
3067 /// specified FP immediate natively. If false, the legalizer will
3068 /// materialize the FP immediate as a load from a constant pool.
3069 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3070 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3071 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3077 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3078 /// the specified range (L, H].
3079 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3080 return (Val < 0) || (Val >= Low && Val < Hi);
3083 /// isUndefOrInRange - Return true if every element in Mask, begining
3084 /// from position Pos and ending in Pos+Size, falls within the specified
3085 /// range (L, L+Pos]. or is undef.
3086 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3087 int Pos, int Size, int Low, int Hi) {
3088 for (int i = Pos, e = Pos+Size; i != e; ++i)
3089 if (!isUndefOrInRange(Mask[i], Low, Hi))
3094 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3095 /// specified value.
3096 static bool isUndefOrEqual(int Val, int CmpVal) {
3097 if (Val < 0 || Val == CmpVal)
3102 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3103 /// from position Pos and ending in Pos+Size, falls within the specified
3104 /// sequential range (L, L+Pos]. or is undef.
3105 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3106 int Pos, int Size, int Low) {
3107 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3108 if (!isUndefOrEqual(Mask[i], Low))
3113 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3114 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3115 /// the second operand.
3116 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3117 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3118 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3119 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3120 return (Mask[0] < 2 && Mask[1] < 2);
3124 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3125 SmallVector<int, 8> M;
3127 return ::isPSHUFDMask(M, N->getValueType(0));
3130 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3131 /// is suitable for input to PSHUFHW.
3132 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3133 if (VT != MVT::v8i16)
3136 // Lower quadword copied in order or undef.
3137 for (int i = 0; i != 4; ++i)
3138 if (Mask[i] >= 0 && Mask[i] != i)
3141 // Upper quadword shuffled.
3142 for (int i = 4; i != 8; ++i)
3143 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3149 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3150 SmallVector<int, 8> M;
3152 return ::isPSHUFHWMask(M, N->getValueType(0));
3155 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3156 /// is suitable for input to PSHUFLW.
3157 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3158 if (VT != MVT::v8i16)
3161 // Upper quadword copied in order.
3162 for (int i = 4; i != 8; ++i)
3163 if (Mask[i] >= 0 && Mask[i] != i)
3166 // Lower quadword shuffled.
3167 for (int i = 0; i != 4; ++i)
3174 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3175 SmallVector<int, 8> M;
3177 return ::isPSHUFLWMask(M, N->getValueType(0));
3180 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3181 /// is suitable for input to PALIGNR.
3182 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3183 bool hasSSSE3OrAVX) {
3184 int i, e = VT.getVectorNumElements();
3185 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64)
3188 // Do not handle v2i64 / v2f64 shuffles with palignr.
3189 if (e < 4 || !hasSSSE3OrAVX)
3192 for (i = 0; i != e; ++i)
3196 // All undef, not a palignr.
3200 // Make sure we're shifting in the right direction.
3204 int s = Mask[i] - i;
3206 // Check the rest of the elements to see if they are consecutive.
3207 for (++i; i != e; ++i) {
3209 if (m >= 0 && m != s+i)
3215 /// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand
3216 /// specifies a shuffle of elements that is suitable for input to 256-bit
3218 static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3219 const X86Subtarget *Subtarget) {
3220 int NumElems = VT.getVectorNumElements();
3222 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3228 // VSHUFPSY divides the resulting vector into 4 chunks.
3229 // The sources are also splitted into 4 chunks, and each destination
3230 // chunk must come from a different source chunk.
3232 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3233 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3235 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3236 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3238 int QuarterSize = NumElems/4;
3239 int HalfSize = QuarterSize*2;
3240 for (int i = 0; i < QuarterSize; ++i)
3241 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3243 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3244 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3247 // The mask of the second half must be the same as the first but with
3248 // the appropriate offsets. This works in the same way as VPERMILPS
3249 // works with masks.
3250 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) {
3251 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3253 int FstHalfIdx = i-HalfSize;
3254 if (Mask[FstHalfIdx] < 0)
3256 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3259 for (int i = QuarterSize*3; i < NumElems; ++i) {
3260 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3262 int FstHalfIdx = i-HalfSize;
3263 if (Mask[FstHalfIdx] < 0)
3265 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3273 /// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle
3274 /// the specified VECTOR_MASK mask with VSHUFPSY instruction.
3275 static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) {
3276 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3277 EVT VT = SVOp->getValueType(0);
3278 int NumElems = VT.getVectorNumElements();
3280 assert(NumElems == 8 && VT.getSizeInBits() == 256 &&
3281 "Only supports v8i32 and v8f32 types");
3283 int HalfSize = NumElems/2;
3285 for (int i = 0; i != NumElems ; ++i) {
3286 if (SVOp->getMaskElt(i) < 0)
3288 // The mask of the first half must be equal to the second one.
3289 unsigned Shamt = (i%HalfSize)*2;
3290 unsigned Elt = SVOp->getMaskElt(i) % HalfSize;
3291 Mask |= Elt << Shamt;
3297 /// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand
3298 /// specifies a shuffle of elements that is suitable for input to 256-bit
3299 /// VSHUFPDY. This shuffle doesn't have the same restriction as the PS
3300 /// version and the mask of the second half isn't binded with the first
3302 static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3303 const X86Subtarget *Subtarget) {
3304 int NumElems = VT.getVectorNumElements();
3306 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3312 // VSHUFPSY divides the resulting vector into 4 chunks.
3313 // The sources are also splitted into 4 chunks, and each destination
3314 // chunk must come from a different source chunk.
3316 // SRC1 => X3 X2 X1 X0
3317 // SRC2 => Y3 Y2 Y1 Y0
3319 // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0
3321 int QuarterSize = NumElems/4;
3322 int HalfSize = QuarterSize*2;
3323 for (int i = 0; i < QuarterSize; ++i)
3324 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3326 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3327 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3329 for (int i = QuarterSize*2; i < QuarterSize*3; ++i)
3330 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3332 for (int i = QuarterSize*3; i < NumElems; ++i)
3333 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3339 /// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle
3340 /// the specified VECTOR_MASK mask with VSHUFPDY instruction.
3341 static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) {
3342 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3343 EVT VT = SVOp->getValueType(0);
3344 int NumElems = VT.getVectorNumElements();
3346 assert(NumElems == 4 && VT.getSizeInBits() == 256 &&
3347 "Only supports v4i64 and v4f64 types");
3349 int HalfSize = NumElems/2;
3351 for (int i = 0; i != NumElems ; ++i) {
3352 if (SVOp->getMaskElt(i) < 0)
3354 int Elt = SVOp->getMaskElt(i) % HalfSize;
3361 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3362 /// specifies a shuffle of elements that is suitable for input to 128-bit
3363 /// SHUFPS and SHUFPD.
3364 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3365 int NumElems = VT.getVectorNumElements();
3367 if (VT.getSizeInBits() != 128)
3370 if (NumElems != 2 && NumElems != 4)
3373 int Half = NumElems / 2;
3374 for (int i = 0; i < Half; ++i)
3375 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3377 for (int i = Half; i < NumElems; ++i)
3378 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3384 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3385 SmallVector<int, 8> M;
3387 return ::isSHUFPMask(M, N->getValueType(0));
3390 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3391 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3392 /// half elements to come from vector 1 (which would equal the dest.) and
3393 /// the upper half to come from vector 2.
3394 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3395 int NumElems = VT.getVectorNumElements();
3397 if (NumElems != 2 && NumElems != 4)
3400 int Half = NumElems / 2;
3401 for (int i = 0; i < Half; ++i)
3402 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3404 for (int i = Half; i < NumElems; ++i)
3405 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3410 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3411 SmallVector<int, 8> M;
3413 return isCommutedSHUFPMask(M, N->getValueType(0));
3416 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3417 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3418 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3419 EVT VT = N->getValueType(0);
3420 unsigned NumElems = VT.getVectorNumElements();
3422 if (VT.getSizeInBits() != 128)
3428 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3429 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3430 isUndefOrEqual(N->getMaskElt(1), 7) &&
3431 isUndefOrEqual(N->getMaskElt(2), 2) &&
3432 isUndefOrEqual(N->getMaskElt(3), 3);
3435 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3436 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3438 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3439 EVT VT = N->getValueType(0);
3440 unsigned NumElems = VT.getVectorNumElements();
3442 if (VT.getSizeInBits() != 128)
3448 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3449 isUndefOrEqual(N->getMaskElt(1), 3) &&
3450 isUndefOrEqual(N->getMaskElt(2), 2) &&
3451 isUndefOrEqual(N->getMaskElt(3), 3);
3454 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3455 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3456 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3457 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3459 if (NumElems != 2 && NumElems != 4)
3462 for (unsigned i = 0; i < NumElems/2; ++i)
3463 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3466 for (unsigned i = NumElems/2; i < NumElems; ++i)
3467 if (!isUndefOrEqual(N->getMaskElt(i), i))
3473 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3474 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3475 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3476 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3478 if ((NumElems != 2 && NumElems != 4)
3479 || N->getValueType(0).getSizeInBits() > 128)
3482 for (unsigned i = 0; i < NumElems/2; ++i)
3483 if (!isUndefOrEqual(N->getMaskElt(i), i))
3486 for (unsigned i = 0; i < NumElems/2; ++i)
3487 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3493 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3494 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3495 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3496 bool V2IsSplat = false) {
3497 int NumElts = VT.getVectorNumElements();
3499 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3500 "Unsupported vector type for unpckh");
3502 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3505 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3506 // independently on 128-bit lanes.
3507 unsigned NumLanes = VT.getSizeInBits()/128;
3508 unsigned NumLaneElts = NumElts/NumLanes;
3511 unsigned End = NumLaneElts;
3512 for (unsigned s = 0; s < NumLanes; ++s) {
3513 for (unsigned i = Start, j = s * NumLaneElts;
3517 int BitI1 = Mask[i+1];
3518 if (!isUndefOrEqual(BitI, j))
3521 if (!isUndefOrEqual(BitI1, NumElts))
3524 if (!isUndefOrEqual(BitI1, j + NumElts))
3528 // Process the next 128 bits.
3529 Start += NumLaneElts;
3536 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3537 SmallVector<int, 8> M;
3539 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3542 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3543 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3544 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3545 bool V2IsSplat = false) {
3546 int NumElts = VT.getVectorNumElements();
3548 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3549 "Unsupported vector type for unpckh");
3551 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3554 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3555 // independently on 128-bit lanes.
3556 unsigned NumLanes = VT.getSizeInBits()/128;
3557 unsigned NumLaneElts = NumElts/NumLanes;
3560 unsigned End = NumLaneElts;
3561 for (unsigned l = 0; l != NumLanes; ++l) {
3562 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3563 i != End; i += 2, ++j) {
3565 int BitI1 = Mask[i+1];
3566 if (!isUndefOrEqual(BitI, j))
3569 if (isUndefOrEqual(BitI1, NumElts))
3572 if (!isUndefOrEqual(BitI1, j+NumElts))
3576 // Process the next 128 bits.
3577 Start += NumLaneElts;
3583 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3584 SmallVector<int, 8> M;
3586 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3589 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3590 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3592 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3593 int NumElems = VT.getVectorNumElements();
3594 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3597 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3598 // FIXME: Need a better way to get rid of this, there's no latency difference
3599 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3600 // the former later. We should also remove the "_undef" special mask.
3601 if (NumElems == 4 && VT.getSizeInBits() == 256)
3604 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3605 // independently on 128-bit lanes.
3606 unsigned NumLanes = VT.getSizeInBits() / 128;
3607 unsigned NumLaneElts = NumElems / NumLanes;
3609 for (unsigned s = 0; s < NumLanes; ++s) {
3610 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3611 i != NumLaneElts * (s + 1);
3614 int BitI1 = Mask[i+1];
3616 if (!isUndefOrEqual(BitI, j))
3618 if (!isUndefOrEqual(BitI1, j))
3626 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3627 SmallVector<int, 8> M;
3629 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3632 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3633 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3635 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3636 int NumElems = VT.getVectorNumElements();
3637 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3640 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3642 int BitI1 = Mask[i+1];
3643 if (!isUndefOrEqual(BitI, j))
3645 if (!isUndefOrEqual(BitI1, j))
3651 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3652 SmallVector<int, 8> M;
3654 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3657 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3658 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3659 /// MOVSD, and MOVD, i.e. setting the lowest element.
3660 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3661 if (VT.getVectorElementType().getSizeInBits() < 32)
3664 int NumElts = VT.getVectorNumElements();
3666 if (!isUndefOrEqual(Mask[0], NumElts))
3669 for (int i = 1; i < NumElts; ++i)
3670 if (!isUndefOrEqual(Mask[i], i))
3676 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3677 SmallVector<int, 8> M;
3679 return ::isMOVLMask(M, N->getValueType(0));
3682 /// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered
3683 /// as permutations between 128-bit chunks or halves. As an example: this
3685 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3686 /// The first half comes from the second half of V1 and the second half from the
3687 /// the second half of V2.
3688 static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3689 const X86Subtarget *Subtarget) {
3690 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3693 // The shuffle result is divided into half A and half B. In total the two
3694 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3695 // B must come from C, D, E or F.
3696 int HalfSize = VT.getVectorNumElements()/2;
3697 bool MatchA = false, MatchB = false;
3699 // Check if A comes from one of C, D, E, F.
3700 for (int Half = 0; Half < 4; ++Half) {
3701 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3707 // Check if B comes from one of C, D, E, F.
3708 for (int Half = 0; Half < 4; ++Half) {
3709 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3715 return MatchA && MatchB;
3718 /// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle
3719 /// the specified VECTOR_MASK mask with VPERM2F128 instructions.
3720 static unsigned getShuffleVPERM2F128Immediate(SDNode *N) {
3721 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3722 EVT VT = SVOp->getValueType(0);
3724 int HalfSize = VT.getVectorNumElements()/2;
3726 int FstHalf = 0, SndHalf = 0;
3727 for (int i = 0; i < HalfSize; ++i) {
3728 if (SVOp->getMaskElt(i) > 0) {
3729 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3733 for (int i = HalfSize; i < HalfSize*2; ++i) {
3734 if (SVOp->getMaskElt(i) > 0) {
3735 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3740 return (FstHalf | (SndHalf << 4));
3743 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3744 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3745 /// Note that VPERMIL mask matching is different depending whether theunderlying
3746 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3747 /// to the same elements of the low, but to the higher half of the source.
3748 /// In VPERMILPD the two lanes could be shuffled independently of each other
3749 /// with the same restriction that lanes can't be crossed.
3750 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
3751 const X86Subtarget *Subtarget) {
3752 int NumElts = VT.getVectorNumElements();
3753 int NumLanes = VT.getSizeInBits()/128;
3755 if (!Subtarget->hasAVX())
3758 // Match any permutation of 128-bit vector with 64-bit types
3759 if (NumLanes == 1 && NumElts != 2)
3762 // Only match 256-bit with 32 types
3763 if (VT.getSizeInBits() == 256 && NumElts != 4)
3766 // The mask on the high lane is independent of the low. Both can match
3767 // any element in inside its own lane, but can't cross.
3768 int LaneSize = NumElts/NumLanes;
3769 for (int l = 0; l < NumLanes; ++l)
3770 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3771 int LaneStart = l*LaneSize;
3772 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize))
3779 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3780 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*.
3781 /// Note that VPERMIL mask matching is different depending whether theunderlying
3782 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3783 /// to the same elements of the low, but to the higher half of the source.
3784 /// In VPERMILPD the two lanes could be shuffled independently of each other
3785 /// with the same restriction that lanes can't be crossed.
3786 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
3787 const X86Subtarget *Subtarget) {
3788 unsigned NumElts = VT.getVectorNumElements();
3789 unsigned NumLanes = VT.getSizeInBits()/128;
3791 if (!Subtarget->hasAVX())
3794 // Match any permutation of 128-bit vector with 32-bit types
3795 if (NumLanes == 1 && NumElts != 4)
3798 // Only match 256-bit with 32 types
3799 if (VT.getSizeInBits() == 256 && NumElts != 8)
3802 // The mask on the high lane should be the same as the low. Actually,
3803 // they can differ if any of the corresponding index in a lane is undef
3804 // and the other stays in range.
3805 int LaneSize = NumElts/NumLanes;
3806 for (int i = 0; i < LaneSize; ++i) {
3807 int HighElt = i+LaneSize;
3808 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts);
3809 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize);
3811 if (!HighValid || !LowValid)
3813 if (Mask[i] < 0 || Mask[HighElt] < 0)
3815 if (Mask[HighElt]-Mask[i] != LaneSize)
3822 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle
3823 /// the specified VECTOR_MASK mask with VPERMILPS* instructions.
3824 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) {
3825 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3826 EVT VT = SVOp->getValueType(0);
3828 int NumElts = VT.getVectorNumElements();
3829 int NumLanes = VT.getSizeInBits()/128;
3830 int LaneSize = NumElts/NumLanes;
3832 // Although the mask is equal for both lanes do it twice to get the cases
3833 // where a mask will match because the same mask element is undef on the
3834 // first half but valid on the second. This would get pathological cases
3835 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3837 for (int l = 0; l < NumLanes; ++l) {
3838 for (int i = 0; i < LaneSize; ++i) {
3839 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize));
3842 if (MaskElt >= LaneSize)
3843 MaskElt -= LaneSize;
3844 Mask |= MaskElt << (i*2);
3851 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle
3852 /// the specified VECTOR_MASK mask with VPERMILPD* instructions.
3853 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) {
3854 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3855 EVT VT = SVOp->getValueType(0);
3857 int NumElts = VT.getVectorNumElements();
3858 int NumLanes = VT.getSizeInBits()/128;
3861 int LaneSize = NumElts/NumLanes;
3862 for (int l = 0; l < NumLanes; ++l)
3863 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3864 int MaskElt = SVOp->getMaskElt(i);
3867 Mask |= (MaskElt-l*LaneSize) << i;
3873 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3874 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3875 /// element of vector 2 and the other elements to come from vector 1 in order.
3876 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3877 bool V2IsSplat = false, bool V2IsUndef = false) {
3878 int NumOps = VT.getVectorNumElements();
3879 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3882 if (!isUndefOrEqual(Mask[0], 0))
3885 for (int i = 1; i < NumOps; ++i)
3886 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3887 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3888 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3894 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3895 bool V2IsUndef = false) {
3896 SmallVector<int, 8> M;
3898 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3901 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3902 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3903 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3904 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3905 const X86Subtarget *Subtarget) {
3906 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3909 // The second vector must be undef
3910 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3913 EVT VT = N->getValueType(0);
3914 unsigned NumElems = VT.getVectorNumElements();
3916 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3917 (VT.getSizeInBits() == 256 && NumElems != 8))
3920 // "i+1" is the value the indexed mask element must have
3921 for (unsigned i = 0; i < NumElems; i += 2)
3922 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3923 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3929 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3930 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3931 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3932 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3933 const X86Subtarget *Subtarget) {
3934 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3937 // The second vector must be undef
3938 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3941 EVT VT = N->getValueType(0);
3942 unsigned NumElems = VT.getVectorNumElements();
3944 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3945 (VT.getSizeInBits() == 256 && NumElems != 8))
3948 // "i" is the value the indexed mask element must have
3949 for (unsigned i = 0; i < NumElems; i += 2)
3950 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3951 !isUndefOrEqual(N->getMaskElt(i+1), i))
3957 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3958 /// specifies a shuffle of elements that is suitable for input to 256-bit
3959 /// version of MOVDDUP.
3960 static bool isMOVDDUPYMask(ShuffleVectorSDNode *N,
3961 const X86Subtarget *Subtarget) {
3962 EVT VT = N->getValueType(0);
3963 int NumElts = VT.getVectorNumElements();
3964 bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF;
3966 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 ||
3967 !V2IsUndef || NumElts != 4)
3970 for (int i = 0; i != NumElts/2; ++i)
3971 if (!isUndefOrEqual(N->getMaskElt(i), 0))
3973 for (int i = NumElts/2; i != NumElts; ++i)
3974 if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2))
3979 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3980 /// specifies a shuffle of elements that is suitable for input to 128-bit
3981 /// version of MOVDDUP.
3982 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3983 EVT VT = N->getValueType(0);
3985 if (VT.getSizeInBits() != 128)
3988 int e = VT.getVectorNumElements() / 2;
3989 for (int i = 0; i < e; ++i)
3990 if (!isUndefOrEqual(N->getMaskElt(i), i))
3992 for (int i = 0; i < e; ++i)
3993 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3998 /// isVEXTRACTF128Index - Return true if the specified
3999 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4000 /// suitable for input to VEXTRACTF128.
4001 bool X86::isVEXTRACTF128Index(SDNode *N) {
4002 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4005 // The index should be aligned on a 128-bit boundary.
4007 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4009 unsigned VL = N->getValueType(0).getVectorNumElements();
4010 unsigned VBits = N->getValueType(0).getSizeInBits();
4011 unsigned ElSize = VBits / VL;
4012 bool Result = (Index * ElSize) % 128 == 0;
4017 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
4018 /// operand specifies a subvector insert that is suitable for input to
4020 bool X86::isVINSERTF128Index(SDNode *N) {
4021 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4024 // The index should be aligned on a 128-bit boundary.
4026 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4028 unsigned VL = N->getValueType(0).getVectorNumElements();
4029 unsigned VBits = N->getValueType(0).getSizeInBits();
4030 unsigned ElSize = VBits / VL;
4031 bool Result = (Index * ElSize) % 128 == 0;
4036 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4037 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4038 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
4039 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4040 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
4042 unsigned Shift = (NumOperands == 4) ? 2 : 1;
4044 for (int i = 0; i < NumOperands; ++i) {
4045 int Val = SVOp->getMaskElt(NumOperands-i-1);
4046 if (Val < 0) Val = 0;
4047 if (Val >= NumOperands) Val -= NumOperands;
4049 if (i != NumOperands - 1)
4055 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4056 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4057 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
4058 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4060 // 8 nodes, but we only care about the last 4.
4061 for (unsigned i = 7; i >= 4; --i) {
4062 int Val = SVOp->getMaskElt(i);
4071 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4072 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4073 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
4074 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4076 // 8 nodes, but we only care about the first 4.
4077 for (int i = 3; i >= 0; --i) {
4078 int Val = SVOp->getMaskElt(i);
4087 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4088 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4089 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
4090 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4091 EVT VVT = N->getValueType(0);
4092 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
4096 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
4097 Val = SVOp->getMaskElt(i);
4101 assert(Val - i > 0 && "PALIGNR imm should be positive");
4102 return (Val - i) * EltSize;
4105 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4106 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4108 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4109 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4110 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4113 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4115 EVT VecVT = N->getOperand(0).getValueType();
4116 EVT ElVT = VecVT.getVectorElementType();
4118 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4119 return Index / NumElemsPerChunk;
4122 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4123 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4125 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4126 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4127 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4130 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4132 EVT VecVT = N->getValueType(0);
4133 EVT ElVT = VecVT.getVectorElementType();
4135 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4136 return Index / NumElemsPerChunk;
4139 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4141 bool X86::isZeroNode(SDValue Elt) {
4142 return ((isa<ConstantSDNode>(Elt) &&
4143 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4144 (isa<ConstantFPSDNode>(Elt) &&
4145 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4148 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4149 /// their permute mask.
4150 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4151 SelectionDAG &DAG) {
4152 EVT VT = SVOp->getValueType(0);
4153 unsigned NumElems = VT.getVectorNumElements();
4154 SmallVector<int, 8> MaskVec;
4156 for (unsigned i = 0; i != NumElems; ++i) {
4157 int idx = SVOp->getMaskElt(i);
4159 MaskVec.push_back(idx);
4160 else if (idx < (int)NumElems)
4161 MaskVec.push_back(idx + NumElems);
4163 MaskVec.push_back(idx - NumElems);
4165 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4166 SVOp->getOperand(0), &MaskVec[0]);
4169 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4170 /// the two vector operands have swapped position.
4171 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
4172 unsigned NumElems = VT.getVectorNumElements();
4173 for (unsigned i = 0; i != NumElems; ++i) {
4177 else if (idx < (int)NumElems)
4178 Mask[i] = idx + NumElems;
4180 Mask[i] = idx - NumElems;
4184 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4185 /// match movhlps. The lower half elements should come from upper half of
4186 /// V1 (and in order), and the upper half elements should come from the upper
4187 /// half of V2 (and in order).
4188 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4189 EVT VT = Op->getValueType(0);
4190 if (VT.getSizeInBits() != 128)
4192 if (VT.getVectorNumElements() != 4)
4194 for (unsigned i = 0, e = 2; i != e; ++i)
4195 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4197 for (unsigned i = 2; i != 4; ++i)
4198 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4203 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4204 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4206 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4207 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4209 N = N->getOperand(0).getNode();
4210 if (!ISD::isNON_EXTLoad(N))
4213 *LD = cast<LoadSDNode>(N);
4217 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4218 /// match movlp{s|d}. The lower half elements should come from lower half of
4219 /// V1 (and in order), and the upper half elements should come from the upper
4220 /// half of V2 (and in order). And since V1 will become the source of the
4221 /// MOVLP, it must be either a vector load or a scalar load to vector.
4222 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4223 ShuffleVectorSDNode *Op) {
4224 EVT VT = Op->getValueType(0);
4225 if (VT.getSizeInBits() != 128)
4228 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4230 // Is V2 is a vector load, don't do this transformation. We will try to use
4231 // load folding shufps op.
4232 if (ISD::isNON_EXTLoad(V2))
4235 unsigned NumElems = VT.getVectorNumElements();
4237 if (NumElems != 2 && NumElems != 4)
4239 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4240 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4242 for (unsigned i = NumElems/2; i != NumElems; ++i)
4243 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4248 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4250 static bool isSplatVector(SDNode *N) {
4251 if (N->getOpcode() != ISD::BUILD_VECTOR)
4254 SDValue SplatValue = N->getOperand(0);
4255 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4256 if (N->getOperand(i) != SplatValue)
4261 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4262 /// to an zero vector.
4263 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4264 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4265 SDValue V1 = N->getOperand(0);
4266 SDValue V2 = N->getOperand(1);
4267 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4268 for (unsigned i = 0; i != NumElems; ++i) {
4269 int Idx = N->getMaskElt(i);
4270 if (Idx >= (int)NumElems) {
4271 unsigned Opc = V2.getOpcode();
4272 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4274 if (Opc != ISD::BUILD_VECTOR ||
4275 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4277 } else if (Idx >= 0) {
4278 unsigned Opc = V1.getOpcode();
4279 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4281 if (Opc != ISD::BUILD_VECTOR ||
4282 !X86::isZeroNode(V1.getOperand(Idx)))
4289 /// getZeroVector - Returns a vector of specified type with all zero elements.
4291 static SDValue getZeroVector(EVT VT, bool HasXMMInt, SelectionDAG &DAG,
4293 assert(VT.isVector() && "Expected a vector type");
4295 // Always build SSE zero vectors as <4 x i32> bitcasted
4296 // to their dest type. This ensures they get CSE'd.
4298 if (VT.getSizeInBits() == 128) { // SSE
4299 if (HasXMMInt) { // SSE2
4300 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4301 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4303 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4304 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4306 } else if (VT.getSizeInBits() == 256) { // AVX
4307 // 256-bit logic and arithmetic instructions in AVX are
4308 // all floating-point, no support for integer ops. Default
4309 // to emitting fp zeroed vectors then.
4310 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4311 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4312 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4314 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4317 /// getOnesVector - Returns a vector of specified type with all bits set.
4318 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two
4319 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
4320 /// original type, ensuring they get CSE'd.
4321 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4322 assert(VT.isVector() && "Expected a vector type");
4323 assert((VT.is128BitVector() || VT.is256BitVector())
4324 && "Expected a 128-bit or 256-bit vector type");
4326 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4327 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
4328 Cst, Cst, Cst, Cst);
4330 if (VT.is256BitVector()) {
4331 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4332 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4333 Vec = Insert128BitVector(InsV, Vec,
4334 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4337 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4340 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4341 /// that point to V2 points to its first element.
4342 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4343 EVT VT = SVOp->getValueType(0);
4344 unsigned NumElems = VT.getVectorNumElements();
4346 bool Changed = false;
4347 SmallVector<int, 8> MaskVec;
4348 SVOp->getMask(MaskVec);
4350 for (unsigned i = 0; i != NumElems; ++i) {
4351 if (MaskVec[i] > (int)NumElems) {
4352 MaskVec[i] = NumElems;
4357 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4358 SVOp->getOperand(1), &MaskVec[0]);
4359 return SDValue(SVOp, 0);
4362 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4363 /// operation of specified width.
4364 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4366 unsigned NumElems = VT.getVectorNumElements();
4367 SmallVector<int, 8> Mask;
4368 Mask.push_back(NumElems);
4369 for (unsigned i = 1; i != NumElems; ++i)
4371 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4374 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4375 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4377 unsigned NumElems = VT.getVectorNumElements();
4378 SmallVector<int, 8> Mask;
4379 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4381 Mask.push_back(i + NumElems);
4383 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4386 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4387 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4389 unsigned NumElems = VT.getVectorNumElements();
4390 unsigned Half = NumElems/2;
4391 SmallVector<int, 8> Mask;
4392 for (unsigned i = 0; i != Half; ++i) {
4393 Mask.push_back(i + Half);
4394 Mask.push_back(i + NumElems + Half);
4396 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4399 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4400 // a generic shuffle instruction because the target has no such instructions.
4401 // Generate shuffles which repeat i16 and i8 several times until they can be
4402 // represented by v4f32 and then be manipulated by target suported shuffles.
4403 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4404 EVT VT = V.getValueType();
4405 int NumElems = VT.getVectorNumElements();
4406 DebugLoc dl = V.getDebugLoc();
4408 while (NumElems > 4) {
4409 if (EltNo < NumElems/2) {
4410 V = getUnpackl(DAG, dl, VT, V, V);
4412 V = getUnpackh(DAG, dl, VT, V, V);
4413 EltNo -= NumElems/2;
4420 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4421 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4422 EVT VT = V.getValueType();
4423 DebugLoc dl = V.getDebugLoc();
4424 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4425 && "Vector size not supported");
4427 if (VT.getSizeInBits() == 128) {
4428 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4429 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4430 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4433 // To use VPERMILPS to splat scalars, the second half of indicies must
4434 // refer to the higher part, which is a duplication of the lower one,
4435 // because VPERMILPS can only handle in-lane permutations.
4436 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4437 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4439 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4440 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4444 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4447 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4448 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4449 EVT SrcVT = SV->getValueType(0);
4450 SDValue V1 = SV->getOperand(0);
4451 DebugLoc dl = SV->getDebugLoc();
4453 int EltNo = SV->getSplatIndex();
4454 int NumElems = SrcVT.getVectorNumElements();
4455 unsigned Size = SrcVT.getSizeInBits();
4457 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4458 "Unknown how to promote splat for type");
4460 // Extract the 128-bit part containing the splat element and update
4461 // the splat element index when it refers to the higher register.
4463 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4464 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4466 EltNo -= NumElems/2;
4469 // All i16 and i8 vector types can't be used directly by a generic shuffle
4470 // instruction because the target has no such instruction. Generate shuffles
4471 // which repeat i16 and i8 several times until they fit in i32, and then can
4472 // be manipulated by target suported shuffles.
4473 EVT EltVT = SrcVT.getVectorElementType();
4474 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4475 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4477 // Recreate the 256-bit vector and place the same 128-bit vector
4478 // into the low and high part. This is necessary because we want
4479 // to use VPERM* to shuffle the vectors
4481 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4482 DAG.getConstant(0, MVT::i32), DAG, dl);
4483 V1 = Insert128BitVector(InsV, V1,
4484 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4487 return getLegalSplat(DAG, V1, EltNo);
4490 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4491 /// vector of zero or undef vector. This produces a shuffle where the low
4492 /// element of V2 is swizzled into the zero/undef vector, landing at element
4493 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4494 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4495 bool isZero, bool HasXMMInt,
4496 SelectionDAG &DAG) {
4497 EVT VT = V2.getValueType();
4499 ? getZeroVector(VT, HasXMMInt, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4500 unsigned NumElems = VT.getVectorNumElements();
4501 SmallVector<int, 16> MaskVec;
4502 for (unsigned i = 0; i != NumElems; ++i)
4503 // If this is the insertion idx, put the low elt of V2 here.
4504 MaskVec.push_back(i == Idx ? NumElems : i);
4505 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4508 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4509 /// element of the result of the vector shuffle.
4510 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4513 return SDValue(); // Limit search depth.
4515 SDValue V = SDValue(N, 0);
4516 EVT VT = V.getValueType();
4517 unsigned Opcode = V.getOpcode();
4519 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4520 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4521 Index = SV->getMaskElt(Index);
4524 return DAG.getUNDEF(VT.getVectorElementType());
4526 int NumElems = VT.getVectorNumElements();
4527 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4528 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4531 // Recurse into target specific vector shuffles to find scalars.
4532 if (isTargetShuffle(Opcode)) {
4533 int NumElems = VT.getVectorNumElements();
4534 SmallVector<unsigned, 16> ShuffleMask;
4538 case X86ISD::SHUFPS:
4539 case X86ISD::SHUFPD:
4540 ImmN = N->getOperand(N->getNumOperands()-1);
4541 DecodeSHUFPSMask(NumElems,
4542 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4545 case X86ISD::PUNPCKHBW:
4546 case X86ISD::PUNPCKHWD:
4547 case X86ISD::PUNPCKHDQ:
4548 case X86ISD::PUNPCKHQDQ:
4549 DecodePUNPCKHMask(NumElems, ShuffleMask);
4551 case X86ISD::UNPCKHPS:
4552 case X86ISD::UNPCKHPD:
4553 case X86ISD::VUNPCKHPSY:
4554 case X86ISD::VUNPCKHPDY:
4555 DecodeUNPCKHPMask(NumElems, ShuffleMask);
4557 case X86ISD::PUNPCKLBW:
4558 case X86ISD::PUNPCKLWD:
4559 case X86ISD::PUNPCKLDQ:
4560 case X86ISD::PUNPCKLQDQ:
4561 DecodePUNPCKLMask(VT, ShuffleMask);
4563 case X86ISD::UNPCKLPS:
4564 case X86ISD::UNPCKLPD:
4565 case X86ISD::VUNPCKLPSY:
4566 case X86ISD::VUNPCKLPDY:
4567 DecodeUNPCKLPMask(VT, ShuffleMask);
4569 case X86ISD::MOVHLPS:
4570 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4572 case X86ISD::MOVLHPS:
4573 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4575 case X86ISD::PSHUFD:
4576 ImmN = N->getOperand(N->getNumOperands()-1);
4577 DecodePSHUFMask(NumElems,
4578 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4581 case X86ISD::PSHUFHW:
4582 ImmN = N->getOperand(N->getNumOperands()-1);
4583 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4586 case X86ISD::PSHUFLW:
4587 ImmN = N->getOperand(N->getNumOperands()-1);
4588 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4592 case X86ISD::MOVSD: {
4593 // The index 0 always comes from the first element of the second source,
4594 // this is why MOVSS and MOVSD are used in the first place. The other
4595 // elements come from the other positions of the first source vector.
4596 unsigned OpNum = (Index == 0) ? 1 : 0;
4597 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4600 case X86ISD::VPERMILPS:
4601 ImmN = N->getOperand(N->getNumOperands()-1);
4602 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4605 case X86ISD::VPERMILPSY:
4606 ImmN = N->getOperand(N->getNumOperands()-1);
4607 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4610 case X86ISD::VPERMILPD:
4611 ImmN = N->getOperand(N->getNumOperands()-1);
4612 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4615 case X86ISD::VPERMILPDY:
4616 ImmN = N->getOperand(N->getNumOperands()-1);
4617 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4620 case X86ISD::VPERM2F128:
4621 ImmN = N->getOperand(N->getNumOperands()-1);
4622 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4625 case X86ISD::MOVDDUP:
4626 case X86ISD::MOVLHPD:
4627 case X86ISD::MOVLPD:
4628 case X86ISD::MOVLPS:
4629 case X86ISD::MOVSHDUP:
4630 case X86ISD::MOVSLDUP:
4631 case X86ISD::PALIGN:
4632 return SDValue(); // Not yet implemented.
4634 assert(0 && "unknown target shuffle node");
4638 Index = ShuffleMask[Index];
4640 return DAG.getUNDEF(VT.getVectorElementType());
4642 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4643 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4647 // Actual nodes that may contain scalar elements
4648 if (Opcode == ISD::BITCAST) {
4649 V = V.getOperand(0);
4650 EVT SrcVT = V.getValueType();
4651 unsigned NumElems = VT.getVectorNumElements();
4653 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4657 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4658 return (Index == 0) ? V.getOperand(0)
4659 : DAG.getUNDEF(VT.getVectorElementType());
4661 if (V.getOpcode() == ISD::BUILD_VECTOR)
4662 return V.getOperand(Index);
4667 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4668 /// shuffle operation which come from a consecutively from a zero. The
4669 /// search can start in two different directions, from left or right.
4671 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4672 bool ZerosFromLeft, SelectionDAG &DAG) {
4675 while (i < NumElems) {
4676 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4677 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4678 if (!(Elt.getNode() &&
4679 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4687 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4688 /// MaskE correspond consecutively to elements from one of the vector operands,
4689 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4691 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4692 int OpIdx, int NumElems, unsigned &OpNum) {
4693 bool SeenV1 = false;
4694 bool SeenV2 = false;
4696 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4697 int Idx = SVOp->getMaskElt(i);
4698 // Ignore undef indicies
4707 // Only accept consecutive elements from the same vector
4708 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4712 OpNum = SeenV1 ? 0 : 1;
4716 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4717 /// logical left shift of a vector.
4718 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4719 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4720 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4721 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4722 false /* check zeros from right */, DAG);
4728 // Considering the elements in the mask that are not consecutive zeros,
4729 // check if they consecutively come from only one of the source vectors.
4731 // V1 = {X, A, B, C} 0
4733 // vector_shuffle V1, V2 <1, 2, 3, X>
4735 if (!isShuffleMaskConsecutive(SVOp,
4736 0, // Mask Start Index
4737 NumElems-NumZeros-1, // Mask End Index
4738 NumZeros, // Where to start looking in the src vector
4739 NumElems, // Number of elements in vector
4740 OpSrc)) // Which source operand ?
4745 ShVal = SVOp->getOperand(OpSrc);
4749 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4750 /// logical left shift of a vector.
4751 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4752 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4753 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4754 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4755 true /* check zeros from left */, DAG);
4761 // Considering the elements in the mask that are not consecutive zeros,
4762 // check if they consecutively come from only one of the source vectors.
4764 // 0 { A, B, X, X } = V2
4766 // vector_shuffle V1, V2 <X, X, 4, 5>
4768 if (!isShuffleMaskConsecutive(SVOp,
4769 NumZeros, // Mask Start Index
4770 NumElems-1, // Mask End Index
4771 0, // Where to start looking in the src vector
4772 NumElems, // Number of elements in vector
4773 OpSrc)) // Which source operand ?
4778 ShVal = SVOp->getOperand(OpSrc);
4782 /// isVectorShift - Returns true if the shuffle can be implemented as a
4783 /// logical left or right shift of a vector.
4784 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4785 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4786 // Although the logic below support any bitwidth size, there are no
4787 // shift instructions which handle more than 128-bit vectors.
4788 if (SVOp->getValueType(0).getSizeInBits() > 128)
4791 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4792 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4798 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4800 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4801 unsigned NumNonZero, unsigned NumZero,
4803 const TargetLowering &TLI) {
4807 DebugLoc dl = Op.getDebugLoc();
4810 for (unsigned i = 0; i < 16; ++i) {
4811 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4812 if (ThisIsNonZero && First) {
4814 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4816 V = DAG.getUNDEF(MVT::v8i16);
4821 SDValue ThisElt(0, 0), LastElt(0, 0);
4822 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4823 if (LastIsNonZero) {
4824 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4825 MVT::i16, Op.getOperand(i-1));
4827 if (ThisIsNonZero) {
4828 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4829 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4830 ThisElt, DAG.getConstant(8, MVT::i8));
4832 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4836 if (ThisElt.getNode())
4837 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4838 DAG.getIntPtrConstant(i/2));
4842 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4845 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4847 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4848 unsigned NumNonZero, unsigned NumZero,
4850 const TargetLowering &TLI) {
4854 DebugLoc dl = Op.getDebugLoc();
4857 for (unsigned i = 0; i < 8; ++i) {
4858 bool isNonZero = (NonZeros & (1 << i)) != 0;
4862 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4864 V = DAG.getUNDEF(MVT::v8i16);
4867 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4868 MVT::v8i16, V, Op.getOperand(i),
4869 DAG.getIntPtrConstant(i));
4876 /// getVShift - Return a vector logical shift node.
4878 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4879 unsigned NumBits, SelectionDAG &DAG,
4880 const TargetLowering &TLI, DebugLoc dl) {
4881 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4882 EVT ShVT = MVT::v2i64;
4883 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4884 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4885 return DAG.getNode(ISD::BITCAST, dl, VT,
4886 DAG.getNode(Opc, dl, ShVT, SrcOp,
4887 DAG.getConstant(NumBits,
4888 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4892 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4893 SelectionDAG &DAG) const {
4895 // Check if the scalar load can be widened into a vector load. And if
4896 // the address is "base + cst" see if the cst can be "absorbed" into
4897 // the shuffle mask.
4898 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4899 SDValue Ptr = LD->getBasePtr();
4900 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4902 EVT PVT = LD->getValueType(0);
4903 if (PVT != MVT::i32 && PVT != MVT::f32)
4908 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4909 FI = FINode->getIndex();
4911 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4912 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4913 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4914 Offset = Ptr.getConstantOperandVal(1);
4915 Ptr = Ptr.getOperand(0);
4920 // FIXME: 256-bit vector instructions don't require a strict alignment,
4921 // improve this code to support it better.
4922 unsigned RequiredAlign = VT.getSizeInBits()/8;
4923 SDValue Chain = LD->getChain();
4924 // Make sure the stack object alignment is at least 16 or 32.
4925 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4926 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4927 if (MFI->isFixedObjectIndex(FI)) {
4928 // Can't change the alignment. FIXME: It's possible to compute
4929 // the exact stack offset and reference FI + adjust offset instead.
4930 // If someone *really* cares about this. That's the way to implement it.
4933 MFI->setObjectAlignment(FI, RequiredAlign);
4937 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4938 // Ptr + (Offset & ~15).
4941 if ((Offset % RequiredAlign) & 3)
4943 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4945 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4946 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4948 int EltNo = (Offset - StartOffset) >> 2;
4949 int NumElems = VT.getVectorNumElements();
4951 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4952 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4953 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4954 LD->getPointerInfo().getWithOffset(StartOffset),
4957 // Canonicalize it to a v4i32 or v8i32 shuffle.
4958 SmallVector<int, 8> Mask;
4959 for (int i = 0; i < NumElems; ++i)
4960 Mask.push_back(EltNo);
4962 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4963 return DAG.getNode(ISD::BITCAST, dl, NVT,
4964 DAG.getVectorShuffle(CanonVT, dl, V1,
4965 DAG.getUNDEF(CanonVT),&Mask[0]));
4971 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4972 /// vector of type 'VT', see if the elements can be replaced by a single large
4973 /// load which has the same value as a build_vector whose operands are 'elts'.
4975 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4977 /// FIXME: we'd also like to handle the case where the last elements are zero
4978 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4979 /// There's even a handy isZeroNode for that purpose.
4980 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4981 DebugLoc &DL, SelectionDAG &DAG) {
4982 EVT EltVT = VT.getVectorElementType();
4983 unsigned NumElems = Elts.size();
4985 LoadSDNode *LDBase = NULL;
4986 unsigned LastLoadedElt = -1U;
4988 // For each element in the initializer, see if we've found a load or an undef.
4989 // If we don't find an initial load element, or later load elements are
4990 // non-consecutive, bail out.
4991 for (unsigned i = 0; i < NumElems; ++i) {
4992 SDValue Elt = Elts[i];
4994 if (!Elt.getNode() ||
4995 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4998 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5000 LDBase = cast<LoadSDNode>(Elt.getNode());
5004 if (Elt.getOpcode() == ISD::UNDEF)
5007 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5008 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5013 // If we have found an entire vector of loads and undefs, then return a large
5014 // load of the entire vector width starting at the base pointer. If we found
5015 // consecutive loads for the low half, generate a vzext_load node.
5016 if (LastLoadedElt == NumElems - 1) {
5017 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5018 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5019 LDBase->getPointerInfo(),
5020 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
5021 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5022 LDBase->getPointerInfo(),
5023 LDBase->isVolatile(), LDBase->isNonTemporal(),
5024 LDBase->getAlignment());
5025 } else if (NumElems == 4 && LastLoadedElt == 1 &&
5026 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5027 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5028 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5030 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
5031 LDBase->getPointerInfo(),
5032 LDBase->getAlignment(),
5033 false/*isVolatile*/, true/*ReadMem*/,
5035 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5041 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5042 DebugLoc dl = Op.getDebugLoc();
5044 EVT VT = Op.getValueType();
5045 EVT ExtVT = VT.getVectorElementType();
5046 unsigned NumElems = Op.getNumOperands();
5048 // Vectors containing all zeros can be matched by pxor and xorps later
5049 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5050 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5051 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5052 if (Op.getValueType() == MVT::v4i32 ||
5053 Op.getValueType() == MVT::v8i32)
5056 return getZeroVector(Op.getValueType(), Subtarget->hasXMMInt(), DAG, dl);
5059 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5060 // vectors or broken into v4i32 operations on 256-bit vectors.
5061 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5062 if (Op.getValueType() == MVT::v4i32)
5065 return getOnesVector(Op.getValueType(), DAG, dl);
5068 unsigned EVTBits = ExtVT.getSizeInBits();
5070 unsigned NumZero = 0;
5071 unsigned NumNonZero = 0;
5072 unsigned NonZeros = 0;
5073 bool IsAllConstants = true;
5074 SmallSet<SDValue, 8> Values;
5075 for (unsigned i = 0; i < NumElems; ++i) {
5076 SDValue Elt = Op.getOperand(i);
5077 if (Elt.getOpcode() == ISD::UNDEF)
5080 if (Elt.getOpcode() != ISD::Constant &&
5081 Elt.getOpcode() != ISD::ConstantFP)
5082 IsAllConstants = false;
5083 if (X86::isZeroNode(Elt))
5086 NonZeros |= (1 << i);
5091 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5092 if (NumNonZero == 0)
5093 return DAG.getUNDEF(VT);
5095 // Special case for single non-zero, non-undef, element.
5096 if (NumNonZero == 1) {
5097 unsigned Idx = CountTrailingZeros_32(NonZeros);
5098 SDValue Item = Op.getOperand(Idx);
5100 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5101 // the value are obviously zero, truncate the value to i32 and do the
5102 // insertion that way. Only do this if the value is non-constant or if the
5103 // value is a constant being inserted into element 0. It is cheaper to do
5104 // a constant pool load than it is to do a movd + shuffle.
5105 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5106 (!IsAllConstants || Idx == 0)) {
5107 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5109 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5110 EVT VecVT = MVT::v4i32;
5111 unsigned VecElts = 4;
5113 // Truncate the value (which may itself be a constant) to i32, and
5114 // convert it to a vector with movd (S2V+shuffle to zero extend).
5115 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5116 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5117 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5118 Subtarget->hasXMMInt(), DAG);
5120 // Now we have our 32-bit value zero extended in the low element of
5121 // a vector. If Idx != 0, swizzle it into place.
5123 SmallVector<int, 4> Mask;
5124 Mask.push_back(Idx);
5125 for (unsigned i = 1; i != VecElts; ++i)
5127 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5128 DAG.getUNDEF(Item.getValueType()),
5131 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5135 // If we have a constant or non-constant insertion into the low element of
5136 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5137 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5138 // depending on what the source datatype is.
5141 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5142 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5143 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5144 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5145 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5146 return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(),
5148 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5149 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5150 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5151 EVT MiddleVT = MVT::v4i32;
5152 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
5153 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5154 Subtarget->hasXMMInt(), DAG);
5155 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5159 // Is it a vector logical left shift?
5160 if (NumElems == 2 && Idx == 1 &&
5161 X86::isZeroNode(Op.getOperand(0)) &&
5162 !X86::isZeroNode(Op.getOperand(1))) {
5163 unsigned NumBits = VT.getSizeInBits();
5164 return getVShift(true, VT,
5165 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5166 VT, Op.getOperand(1)),
5167 NumBits/2, DAG, *this, dl);
5170 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5173 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5174 // is a non-constant being inserted into an element other than the low one,
5175 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5176 // movd/movss) to move this into the low element, then shuffle it into
5178 if (EVTBits == 32) {
5179 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5181 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5182 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
5183 Subtarget->hasXMMInt(), DAG);
5184 SmallVector<int, 8> MaskVec;
5185 for (unsigned i = 0; i < NumElems; i++)
5186 MaskVec.push_back(i == Idx ? 0 : 1);
5187 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5191 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5192 if (Values.size() == 1) {
5193 if (EVTBits == 32) {
5194 // Instead of a shuffle like this:
5195 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5196 // Check if it's possible to issue this instead.
5197 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5198 unsigned Idx = CountTrailingZeros_32(NonZeros);
5199 SDValue Item = Op.getOperand(Idx);
5200 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5201 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5206 // A vector full of immediates; various special cases are already
5207 // handled, so this is best done with a single constant-pool load.
5211 // For AVX-length vectors, build the individual 128-bit pieces and use
5212 // shuffles to put them in place.
5213 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5214 SmallVector<SDValue, 32> V;
5215 for (unsigned i = 0; i < NumElems; ++i)
5216 V.push_back(Op.getOperand(i));
5218 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5220 // Build both the lower and upper subvector.
5221 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5222 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5225 // Recreate the wider vector with the lower and upper part.
5226 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5227 DAG.getConstant(0, MVT::i32), DAG, dl);
5228 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5232 // Let legalizer expand 2-wide build_vectors.
5233 if (EVTBits == 64) {
5234 if (NumNonZero == 1) {
5235 // One half is zero or undef.
5236 unsigned Idx = CountTrailingZeros_32(NonZeros);
5237 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5238 Op.getOperand(Idx));
5239 return getShuffleVectorZeroOrUndef(V2, Idx, true,
5240 Subtarget->hasXMMInt(), DAG);
5245 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5246 if (EVTBits == 8 && NumElems == 16) {
5247 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5249 if (V.getNode()) return V;
5252 if (EVTBits == 16 && NumElems == 8) {
5253 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5255 if (V.getNode()) return V;
5258 // If element VT is == 32 bits, turn it into a number of shuffles.
5259 SmallVector<SDValue, 8> V;
5261 if (NumElems == 4 && NumZero > 0) {
5262 for (unsigned i = 0; i < 4; ++i) {
5263 bool isZero = !(NonZeros & (1 << i));
5265 V[i] = getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl);
5267 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5270 for (unsigned i = 0; i < 2; ++i) {
5271 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5274 V[i] = V[i*2]; // Must be a zero vector.
5277 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5280 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5283 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5288 SmallVector<int, 8> MaskVec;
5289 bool Reverse = (NonZeros & 0x3) == 2;
5290 for (unsigned i = 0; i < 2; ++i)
5291 MaskVec.push_back(Reverse ? 1-i : i);
5292 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5293 for (unsigned i = 0; i < 2; ++i)
5294 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5295 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5298 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5299 // Check for a build vector of consecutive loads.
5300 for (unsigned i = 0; i < NumElems; ++i)
5301 V[i] = Op.getOperand(i);
5303 // Check for elements which are consecutive loads.
5304 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5308 // For SSE 4.1, use insertps to put the high elements into the low element.
5309 if (getSubtarget()->hasSSE41() || getSubtarget()->hasAVX()) {
5311 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5312 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5314 Result = DAG.getUNDEF(VT);
5316 for (unsigned i = 1; i < NumElems; ++i) {
5317 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5318 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5319 Op.getOperand(i), DAG.getIntPtrConstant(i));
5324 // Otherwise, expand into a number of unpckl*, start by extending each of
5325 // our (non-undef) elements to the full vector width with the element in the
5326 // bottom slot of the vector (which generates no code for SSE).
5327 for (unsigned i = 0; i < NumElems; ++i) {
5328 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5329 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5331 V[i] = DAG.getUNDEF(VT);
5334 // Next, we iteratively mix elements, e.g. for v4f32:
5335 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5336 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5337 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5338 unsigned EltStride = NumElems >> 1;
5339 while (EltStride != 0) {
5340 for (unsigned i = 0; i < EltStride; ++i) {
5341 // If V[i+EltStride] is undef and this is the first round of mixing,
5342 // then it is safe to just drop this shuffle: V[i] is already in the
5343 // right place, the one element (since it's the first round) being
5344 // inserted as undef can be dropped. This isn't safe for successive
5345 // rounds because they will permute elements within both vectors.
5346 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5347 EltStride == NumElems/2)
5350 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5359 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5360 // them in a MMX register. This is better than doing a stack convert.
5361 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5362 DebugLoc dl = Op.getDebugLoc();
5363 EVT ResVT = Op.getValueType();
5365 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5366 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5368 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5369 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5370 InVec = Op.getOperand(1);
5371 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5372 unsigned NumElts = ResVT.getVectorNumElements();
5373 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5374 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5375 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5377 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5378 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5379 Mask[0] = 0; Mask[1] = 2;
5380 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5382 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5385 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5386 // to create 256-bit vectors from two other 128-bit ones.
5387 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5388 DebugLoc dl = Op.getDebugLoc();
5389 EVT ResVT = Op.getValueType();
5391 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5393 SDValue V1 = Op.getOperand(0);
5394 SDValue V2 = Op.getOperand(1);
5395 unsigned NumElems = ResVT.getVectorNumElements();
5397 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5398 DAG.getConstant(0, MVT::i32), DAG, dl);
5399 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5404 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5405 EVT ResVT = Op.getValueType();
5407 assert(Op.getNumOperands() == 2);
5408 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5409 "Unsupported CONCAT_VECTORS for value type");
5411 // We support concatenate two MMX registers and place them in a MMX register.
5412 // This is better than doing a stack convert.
5413 if (ResVT.is128BitVector())
5414 return LowerMMXCONCAT_VECTORS(Op, DAG);
5416 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5417 // from two other 128-bit ones.
5418 return LowerAVXCONCAT_VECTORS(Op, DAG);
5421 // v8i16 shuffles - Prefer shuffles in the following order:
5422 // 1. [all] pshuflw, pshufhw, optional move
5423 // 2. [ssse3] 1 x pshufb
5424 // 3. [ssse3] 2 x pshufb + 1 x por
5425 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5427 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5428 SelectionDAG &DAG) const {
5429 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5430 SDValue V1 = SVOp->getOperand(0);
5431 SDValue V2 = SVOp->getOperand(1);
5432 DebugLoc dl = SVOp->getDebugLoc();
5433 SmallVector<int, 8> MaskVals;
5435 // Determine if more than 1 of the words in each of the low and high quadwords
5436 // of the result come from the same quadword of one of the two inputs. Undef
5437 // mask values count as coming from any quadword, for better codegen.
5438 SmallVector<unsigned, 4> LoQuad(4);
5439 SmallVector<unsigned, 4> HiQuad(4);
5440 BitVector InputQuads(4);
5441 for (unsigned i = 0; i < 8; ++i) {
5442 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
5443 int EltIdx = SVOp->getMaskElt(i);
5444 MaskVals.push_back(EltIdx);
5453 InputQuads.set(EltIdx / 4);
5456 int BestLoQuad = -1;
5457 unsigned MaxQuad = 1;
5458 for (unsigned i = 0; i < 4; ++i) {
5459 if (LoQuad[i] > MaxQuad) {
5461 MaxQuad = LoQuad[i];
5465 int BestHiQuad = -1;
5467 for (unsigned i = 0; i < 4; ++i) {
5468 if (HiQuad[i] > MaxQuad) {
5470 MaxQuad = HiQuad[i];
5474 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5475 // of the two input vectors, shuffle them into one input vector so only a
5476 // single pshufb instruction is necessary. If There are more than 2 input
5477 // quads, disable the next transformation since it does not help SSSE3.
5478 bool V1Used = InputQuads[0] || InputQuads[1];
5479 bool V2Used = InputQuads[2] || InputQuads[3];
5480 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) {
5481 if (InputQuads.count() == 2 && V1Used && V2Used) {
5482 BestLoQuad = InputQuads.find_first();
5483 BestHiQuad = InputQuads.find_next(BestLoQuad);
5485 if (InputQuads.count() > 2) {
5491 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5492 // the shuffle mask. If a quad is scored as -1, that means that it contains
5493 // words from all 4 input quadwords.
5495 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5496 SmallVector<int, 8> MaskV;
5497 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5498 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5499 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5500 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5501 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5502 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5504 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5505 // source words for the shuffle, to aid later transformations.
5506 bool AllWordsInNewV = true;
5507 bool InOrder[2] = { true, true };
5508 for (unsigned i = 0; i != 8; ++i) {
5509 int idx = MaskVals[i];
5511 InOrder[i/4] = false;
5512 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5514 AllWordsInNewV = false;
5518 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5519 if (AllWordsInNewV) {
5520 for (int i = 0; i != 8; ++i) {
5521 int idx = MaskVals[i];
5524 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5525 if ((idx != i) && idx < 4)
5527 if ((idx != i) && idx > 3)
5536 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5537 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5538 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5539 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5540 unsigned TargetMask = 0;
5541 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5542 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5543 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5544 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5545 V1 = NewV.getOperand(0);
5546 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5550 // If we have SSSE3, and all words of the result are from 1 input vector,
5551 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5552 // is present, fall back to case 4.
5553 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) {
5554 SmallVector<SDValue,16> pshufbMask;
5556 // If we have elements from both input vectors, set the high bit of the
5557 // shuffle mask element to zero out elements that come from V2 in the V1
5558 // mask, and elements that come from V1 in the V2 mask, so that the two
5559 // results can be OR'd together.
5560 bool TwoInputs = V1Used && V2Used;
5561 for (unsigned i = 0; i != 8; ++i) {
5562 int EltIdx = MaskVals[i] * 2;
5563 if (TwoInputs && (EltIdx >= 16)) {
5564 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5565 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5568 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5569 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5571 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5572 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5573 DAG.getNode(ISD::BUILD_VECTOR, dl,
5574 MVT::v16i8, &pshufbMask[0], 16));
5576 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5578 // Calculate the shuffle mask for the second input, shuffle it, and
5579 // OR it with the first shuffled input.
5581 for (unsigned i = 0; i != 8; ++i) {
5582 int EltIdx = MaskVals[i] * 2;
5584 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5585 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5588 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5589 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5591 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5592 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5593 DAG.getNode(ISD::BUILD_VECTOR, dl,
5594 MVT::v16i8, &pshufbMask[0], 16));
5595 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5596 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5599 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5600 // and update MaskVals with new element order.
5601 BitVector InOrder(8);
5602 if (BestLoQuad >= 0) {
5603 SmallVector<int, 8> MaskV;
5604 for (int i = 0; i != 4; ++i) {
5605 int idx = MaskVals[i];
5607 MaskV.push_back(-1);
5609 } else if ((idx / 4) == BestLoQuad) {
5610 MaskV.push_back(idx & 3);
5613 MaskV.push_back(-1);
5616 for (unsigned i = 4; i != 8; ++i)
5618 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5621 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE &&
5622 (Subtarget->hasSSSE3() || Subtarget->hasAVX()))
5623 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5625 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5629 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5630 // and update MaskVals with the new element order.
5631 if (BestHiQuad >= 0) {
5632 SmallVector<int, 8> MaskV;
5633 for (unsigned i = 0; i != 4; ++i)
5635 for (unsigned i = 4; i != 8; ++i) {
5636 int idx = MaskVals[i];
5638 MaskV.push_back(-1);
5640 } else if ((idx / 4) == BestHiQuad) {
5641 MaskV.push_back((idx & 3) + 4);
5644 MaskV.push_back(-1);
5647 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5650 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE &&
5651 (Subtarget->hasSSSE3() || Subtarget->hasAVX()))
5652 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5654 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5658 // In case BestHi & BestLo were both -1, which means each quadword has a word
5659 // from each of the four input quadwords, calculate the InOrder bitvector now
5660 // before falling through to the insert/extract cleanup.
5661 if (BestLoQuad == -1 && BestHiQuad == -1) {
5663 for (int i = 0; i != 8; ++i)
5664 if (MaskVals[i] < 0 || MaskVals[i] == i)
5668 // The other elements are put in the right place using pextrw and pinsrw.
5669 for (unsigned i = 0; i != 8; ++i) {
5672 int EltIdx = MaskVals[i];
5675 SDValue ExtOp = (EltIdx < 8)
5676 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5677 DAG.getIntPtrConstant(EltIdx))
5678 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5679 DAG.getIntPtrConstant(EltIdx - 8));
5680 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5681 DAG.getIntPtrConstant(i));
5686 // v16i8 shuffles - Prefer shuffles in the following order:
5687 // 1. [ssse3] 1 x pshufb
5688 // 2. [ssse3] 2 x pshufb + 1 x por
5689 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5691 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5693 const X86TargetLowering &TLI) {
5694 SDValue V1 = SVOp->getOperand(0);
5695 SDValue V2 = SVOp->getOperand(1);
5696 DebugLoc dl = SVOp->getDebugLoc();
5697 SmallVector<int, 16> MaskVals;
5698 SVOp->getMask(MaskVals);
5700 // If we have SSSE3, case 1 is generated when all result bytes come from
5701 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5702 // present, fall back to case 3.
5703 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5706 for (unsigned i = 0; i < 16; ++i) {
5707 int EltIdx = MaskVals[i];
5716 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5717 if (TLI.getSubtarget()->hasSSSE3() || TLI.getSubtarget()->hasAVX()) {
5718 SmallVector<SDValue,16> pshufbMask;
5720 // If all result elements are from one input vector, then only translate
5721 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5723 // Otherwise, we have elements from both input vectors, and must zero out
5724 // elements that come from V2 in the first mask, and V1 in the second mask
5725 // so that we can OR them together.
5726 bool TwoInputs = !(V1Only || V2Only);
5727 for (unsigned i = 0; i != 16; ++i) {
5728 int EltIdx = MaskVals[i];
5729 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5730 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5733 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5735 // If all the elements are from V2, assign it to V1 and return after
5736 // building the first pshufb.
5739 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5740 DAG.getNode(ISD::BUILD_VECTOR, dl,
5741 MVT::v16i8, &pshufbMask[0], 16));
5745 // Calculate the shuffle mask for the second input, shuffle it, and
5746 // OR it with the first shuffled input.
5748 for (unsigned i = 0; i != 16; ++i) {
5749 int EltIdx = MaskVals[i];
5751 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5754 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5756 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5757 DAG.getNode(ISD::BUILD_VECTOR, dl,
5758 MVT::v16i8, &pshufbMask[0], 16));
5759 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5762 // No SSSE3 - Calculate in place words and then fix all out of place words
5763 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5764 // the 16 different words that comprise the two doublequadword input vectors.
5765 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5766 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5767 SDValue NewV = V2Only ? V2 : V1;
5768 for (int i = 0; i != 8; ++i) {
5769 int Elt0 = MaskVals[i*2];
5770 int Elt1 = MaskVals[i*2+1];
5772 // This word of the result is all undef, skip it.
5773 if (Elt0 < 0 && Elt1 < 0)
5776 // This word of the result is already in the correct place, skip it.
5777 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5779 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5782 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5783 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5786 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5787 // using a single extract together, load it and store it.
5788 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5789 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5790 DAG.getIntPtrConstant(Elt1 / 2));
5791 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5792 DAG.getIntPtrConstant(i));
5796 // If Elt1 is defined, extract it from the appropriate source. If the
5797 // source byte is not also odd, shift the extracted word left 8 bits
5798 // otherwise clear the bottom 8 bits if we need to do an or.
5800 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5801 DAG.getIntPtrConstant(Elt1 / 2));
5802 if ((Elt1 & 1) == 0)
5803 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5805 TLI.getShiftAmountTy(InsElt.getValueType())));
5807 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5808 DAG.getConstant(0xFF00, MVT::i16));
5810 // If Elt0 is defined, extract it from the appropriate source. If the
5811 // source byte is not also even, shift the extracted word right 8 bits. If
5812 // Elt1 was also defined, OR the extracted values together before
5813 // inserting them in the result.
5815 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5816 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5817 if ((Elt0 & 1) != 0)
5818 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5820 TLI.getShiftAmountTy(InsElt0.getValueType())));
5822 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5823 DAG.getConstant(0x00FF, MVT::i16));
5824 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5827 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5828 DAG.getIntPtrConstant(i));
5830 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5833 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5834 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5835 /// done when every pair / quad of shuffle mask elements point to elements in
5836 /// the right sequence. e.g.
5837 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5839 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5840 SelectionDAG &DAG, DebugLoc dl) {
5841 EVT VT = SVOp->getValueType(0);
5842 SDValue V1 = SVOp->getOperand(0);
5843 SDValue V2 = SVOp->getOperand(1);
5844 unsigned NumElems = VT.getVectorNumElements();
5845 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5847 switch (VT.getSimpleVT().SimpleTy) {
5848 default: assert(false && "Unexpected!");
5849 case MVT::v4f32: NewVT = MVT::v2f64; break;
5850 case MVT::v4i32: NewVT = MVT::v2i64; break;
5851 case MVT::v8i16: NewVT = MVT::v4i32; break;
5852 case MVT::v16i8: NewVT = MVT::v4i32; break;
5855 int Scale = NumElems / NewWidth;
5856 SmallVector<int, 8> MaskVec;
5857 for (unsigned i = 0; i < NumElems; i += Scale) {
5859 for (int j = 0; j < Scale; ++j) {
5860 int EltIdx = SVOp->getMaskElt(i+j);
5864 StartIdx = EltIdx - (EltIdx % Scale);
5865 if (EltIdx != StartIdx + j)
5869 MaskVec.push_back(-1);
5871 MaskVec.push_back(StartIdx / Scale);
5874 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5875 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5876 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5879 /// getVZextMovL - Return a zero-extending vector move low node.
5881 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5882 SDValue SrcOp, SelectionDAG &DAG,
5883 const X86Subtarget *Subtarget, DebugLoc dl) {
5884 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5885 LoadSDNode *LD = NULL;
5886 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5887 LD = dyn_cast<LoadSDNode>(SrcOp);
5889 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5891 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5892 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5893 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5894 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5895 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5897 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5898 return DAG.getNode(ISD::BITCAST, dl, VT,
5899 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5900 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5908 return DAG.getNode(ISD::BITCAST, dl, VT,
5909 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5910 DAG.getNode(ISD::BITCAST, dl,
5914 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5915 /// shuffle node referes to only one lane in the sources.
5916 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5917 EVT VT = SVOp->getValueType(0);
5918 int NumElems = VT.getVectorNumElements();
5919 int HalfSize = NumElems/2;
5920 SmallVector<int, 16> M;
5922 bool MatchA = false, MatchB = false;
5924 for (int l = 0; l < NumElems*2; l += HalfSize) {
5925 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5931 for (int l = 0; l < NumElems*2; l += HalfSize) {
5932 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5938 return MatchA && MatchB;
5941 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5942 /// which could not be matched by any known target speficic shuffle
5944 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5945 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5946 // If each half of a vector shuffle node referes to only one lane in the
5947 // source vectors, extract each used 128-bit lane and shuffle them using
5948 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5949 // the work to the legalizer.
5950 DebugLoc dl = SVOp->getDebugLoc();
5951 EVT VT = SVOp->getValueType(0);
5952 int NumElems = VT.getVectorNumElements();
5953 int HalfSize = NumElems/2;
5955 // Extract the reference for each half
5956 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5957 int FstVecOpNum = 0, SndVecOpNum = 0;
5958 for (int i = 0; i < HalfSize; ++i) {
5959 int Elt = SVOp->getMaskElt(i);
5960 if (SVOp->getMaskElt(i) < 0)
5962 FstVecOpNum = Elt/NumElems;
5963 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5966 for (int i = HalfSize; i < NumElems; ++i) {
5967 int Elt = SVOp->getMaskElt(i);
5968 if (SVOp->getMaskElt(i) < 0)
5970 SndVecOpNum = Elt/NumElems;
5971 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5975 // Extract the subvectors
5976 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5977 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5978 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5979 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5981 // Generate 128-bit shuffles
5982 SmallVector<int, 16> MaskV1, MaskV2;
5983 for (int i = 0; i < HalfSize; ++i) {
5984 int Elt = SVOp->getMaskElt(i);
5985 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5987 for (int i = HalfSize; i < NumElems; ++i) {
5988 int Elt = SVOp->getMaskElt(i);
5989 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5992 EVT NVT = V1.getValueType();
5993 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5994 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5996 // Concatenate the result back
5997 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5998 DAG.getConstant(0, MVT::i32), DAG, dl);
5999 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
6006 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6007 /// 4 elements, and match them with several different shuffle types.
6009 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6010 SDValue V1 = SVOp->getOperand(0);
6011 SDValue V2 = SVOp->getOperand(1);
6012 DebugLoc dl = SVOp->getDebugLoc();
6013 EVT VT = SVOp->getValueType(0);
6015 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6017 SmallVector<std::pair<int, int>, 8> Locs;
6019 SmallVector<int, 8> Mask1(4U, -1);
6020 SmallVector<int, 8> PermMask;
6021 SVOp->getMask(PermMask);
6025 for (unsigned i = 0; i != 4; ++i) {
6026 int Idx = PermMask[i];
6028 Locs[i] = std::make_pair(-1, -1);
6030 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6032 Locs[i] = std::make_pair(0, NumLo);
6036 Locs[i] = std::make_pair(1, NumHi);
6038 Mask1[2+NumHi] = Idx;
6044 if (NumLo <= 2 && NumHi <= 2) {
6045 // If no more than two elements come from either vector. This can be
6046 // implemented with two shuffles. First shuffle gather the elements.
6047 // The second shuffle, which takes the first shuffle as both of its
6048 // vector operands, put the elements into the right order.
6049 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6051 SmallVector<int, 8> Mask2(4U, -1);
6053 for (unsigned i = 0; i != 4; ++i) {
6054 if (Locs[i].first == -1)
6057 unsigned Idx = (i < 2) ? 0 : 4;
6058 Idx += Locs[i].first * 2 + Locs[i].second;
6063 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6064 } else if (NumLo == 3 || NumHi == 3) {
6065 // Otherwise, we must have three elements from one vector, call it X, and
6066 // one element from the other, call it Y. First, use a shufps to build an
6067 // intermediate vector with the one element from Y and the element from X
6068 // that will be in the same half in the final destination (the indexes don't
6069 // matter). Then, use a shufps to build the final vector, taking the half
6070 // containing the element from Y from the intermediate, and the other half
6073 // Normalize it so the 3 elements come from V1.
6074 CommuteVectorShuffleMask(PermMask, VT);
6078 // Find the element from V2.
6080 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6081 int Val = PermMask[HiIndex];
6088 Mask1[0] = PermMask[HiIndex];
6090 Mask1[2] = PermMask[HiIndex^1];
6092 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6095 Mask1[0] = PermMask[0];
6096 Mask1[1] = PermMask[1];
6097 Mask1[2] = HiIndex & 1 ? 6 : 4;
6098 Mask1[3] = HiIndex & 1 ? 4 : 6;
6099 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6101 Mask1[0] = HiIndex & 1 ? 2 : 0;
6102 Mask1[1] = HiIndex & 1 ? 0 : 2;
6103 Mask1[2] = PermMask[2];
6104 Mask1[3] = PermMask[3];
6109 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6113 // Break it into (shuffle shuffle_hi, shuffle_lo).
6116 SmallVector<int,8> LoMask(4U, -1);
6117 SmallVector<int,8> HiMask(4U, -1);
6119 SmallVector<int,8> *MaskPtr = &LoMask;
6120 unsigned MaskIdx = 0;
6123 for (unsigned i = 0; i != 4; ++i) {
6130 int Idx = PermMask[i];
6132 Locs[i] = std::make_pair(-1, -1);
6133 } else if (Idx < 4) {
6134 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6135 (*MaskPtr)[LoIdx] = Idx;
6138 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6139 (*MaskPtr)[HiIdx] = Idx;
6144 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6145 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6146 SmallVector<int, 8> MaskOps;
6147 for (unsigned i = 0; i != 4; ++i) {
6148 if (Locs[i].first == -1) {
6149 MaskOps.push_back(-1);
6151 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6152 MaskOps.push_back(Idx);
6155 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6158 static bool MayFoldVectorLoad(SDValue V) {
6159 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6160 V = V.getOperand(0);
6161 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6162 V = V.getOperand(0);
6168 // FIXME: the version above should always be used. Since there's
6169 // a bug where several vector shuffles can't be folded because the
6170 // DAG is not updated during lowering and a node claims to have two
6171 // uses while it only has one, use this version, and let isel match
6172 // another instruction if the load really happens to have more than
6173 // one use. Remove this version after this bug get fixed.
6174 // rdar://8434668, PR8156
6175 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6176 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6177 V = V.getOperand(0);
6178 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6179 V = V.getOperand(0);
6180 if (ISD::isNormalLoad(V.getNode()))
6185 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6186 /// a vector extract, and if both can be later optimized into a single load.
6187 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6188 /// here because otherwise a target specific shuffle node is going to be
6189 /// emitted for this shuffle, and the optimization not done.
6190 /// FIXME: This is probably not the best approach, but fix the problem
6191 /// until the right path is decided.
6193 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6194 const TargetLowering &TLI) {
6195 EVT VT = V.getValueType();
6196 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6198 // Be sure that the vector shuffle is present in a pattern like this:
6199 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6203 SDNode *N = *V.getNode()->use_begin();
6204 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6207 SDValue EltNo = N->getOperand(1);
6208 if (!isa<ConstantSDNode>(EltNo))
6211 // If the bit convert changed the number of elements, it is unsafe
6212 // to examine the mask.
6213 bool HasShuffleIntoBitcast = false;
6214 if (V.getOpcode() == ISD::BITCAST) {
6215 EVT SrcVT = V.getOperand(0).getValueType();
6216 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6218 V = V.getOperand(0);
6219 HasShuffleIntoBitcast = true;
6222 // Select the input vector, guarding against out of range extract vector.
6223 unsigned NumElems = VT.getVectorNumElements();
6224 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6225 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6226 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6228 // Skip one more bit_convert if necessary
6229 if (V.getOpcode() == ISD::BITCAST)
6230 V = V.getOperand(0);
6232 if (ISD::isNormalLoad(V.getNode())) {
6233 // Is the original load suitable?
6234 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6236 // FIXME: avoid the multi-use bug that is preventing lots of
6237 // of foldings to be detected, this is still wrong of course, but
6238 // give the temporary desired behavior, and if it happens that
6239 // the load has real more uses, during isel it will not fold, and
6240 // will generate poor code.
6241 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
6244 if (!HasShuffleIntoBitcast)
6247 // If there's a bitcast before the shuffle, check if the load type and
6248 // alignment is valid.
6249 unsigned Align = LN0->getAlignment();
6251 TLI.getTargetData()->getABITypeAlignment(
6252 VT.getTypeForEVT(*DAG.getContext()));
6254 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6262 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6263 EVT VT = Op.getValueType();
6265 // Canonizalize to v2f64.
6266 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6267 return DAG.getNode(ISD::BITCAST, dl, VT,
6268 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6273 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6275 SDValue V1 = Op.getOperand(0);
6276 SDValue V2 = Op.getOperand(1);
6277 EVT VT = Op.getValueType();
6279 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6281 if (HasXMMInt && VT == MVT::v2f64)
6282 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6284 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6285 return DAG.getNode(ISD::BITCAST, dl, VT,
6286 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6287 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6288 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6292 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6293 SDValue V1 = Op.getOperand(0);
6294 SDValue V2 = Op.getOperand(1);
6295 EVT VT = Op.getValueType();
6297 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6298 "unsupported shuffle type");
6300 if (V2.getOpcode() == ISD::UNDEF)
6304 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6307 static inline unsigned getSHUFPOpcode(EVT VT) {
6308 switch(VT.getSimpleVT().SimpleTy) {
6309 case MVT::v8i32: // Use fp unit for int unpack.
6311 case MVT::v4i32: // Use fp unit for int unpack.
6312 case MVT::v4f32: return X86ISD::SHUFPS;
6313 case MVT::v4i64: // Use fp unit for int unpack.
6315 case MVT::v2i64: // Use fp unit for int unpack.
6316 case MVT::v2f64: return X86ISD::SHUFPD;
6318 llvm_unreachable("Unknown type for shufp*");
6324 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasXMMInt) {
6325 SDValue V1 = Op.getOperand(0);
6326 SDValue V2 = Op.getOperand(1);
6327 EVT VT = Op.getValueType();
6328 unsigned NumElems = VT.getVectorNumElements();
6330 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6331 // operand of these instructions is only memory, so check if there's a
6332 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6334 bool CanFoldLoad = false;
6336 // Trivial case, when V2 comes from a load.
6337 if (MayFoldVectorLoad(V2))
6340 // When V1 is a load, it can be folded later into a store in isel, example:
6341 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6343 // (MOVLPSmr addr:$src1, VR128:$src2)
6344 // So, recognize this potential and also use MOVLPS or MOVLPD
6345 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6348 // Both of them can't be memory operations though.
6349 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
6350 CanFoldLoad = false;
6353 if (HasXMMInt && NumElems == 2)
6354 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6357 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6360 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6361 // movl and movlp will both match v2i64, but v2i64 is never matched by
6362 // movl earlier because we make it strict to avoid messing with the movlp load
6363 // folding logic (see the code above getMOVLP call). Match it here then,
6364 // this is horrible, but will stay like this until we move all shuffle
6365 // matching to x86 specific nodes. Note that for the 1st condition all
6366 // types are matched with movsd.
6368 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6369 // as to remove this logic from here, as much as possible
6370 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6371 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6372 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6375 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6377 // Invert the operand order and use SHUFPS to match it.
6378 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1,
6379 X86::getShuffleSHUFImmediate(SVOp), DAG);
6382 static inline unsigned getUNPCKLOpcode(EVT VT) {
6383 switch(VT.getSimpleVT().SimpleTy) {
6384 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
6385 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
6386 case MVT::v4f32: return X86ISD::UNPCKLPS;
6387 case MVT::v2f64: return X86ISD::UNPCKLPD;
6388 case MVT::v8i32: // Use fp unit for int unpack.
6389 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
6390 case MVT::v4i64: // Use fp unit for int unpack.
6391 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
6392 case MVT::v16i8: return X86ISD::PUNPCKLBW;
6393 case MVT::v8i16: return X86ISD::PUNPCKLWD;
6395 llvm_unreachable("Unknown type for unpckl");
6400 static inline unsigned getUNPCKHOpcode(EVT VT) {
6401 switch(VT.getSimpleVT().SimpleTy) {
6402 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
6403 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
6404 case MVT::v4f32: return X86ISD::UNPCKHPS;
6405 case MVT::v2f64: return X86ISD::UNPCKHPD;
6406 case MVT::v8i32: // Use fp unit for int unpack.
6407 case MVT::v8f32: return X86ISD::VUNPCKHPSY;
6408 case MVT::v4i64: // Use fp unit for int unpack.
6409 case MVT::v4f64: return X86ISD::VUNPCKHPDY;
6410 case MVT::v16i8: return X86ISD::PUNPCKHBW;
6411 case MVT::v8i16: return X86ISD::PUNPCKHWD;
6413 llvm_unreachable("Unknown type for unpckh");
6418 static inline unsigned getVPERMILOpcode(EVT VT) {
6419 switch(VT.getSimpleVT().SimpleTy) {
6421 case MVT::v4f32: return X86ISD::VPERMILPS;
6423 case MVT::v2f64: return X86ISD::VPERMILPD;
6425 case MVT::v8f32: return X86ISD::VPERMILPSY;
6427 case MVT::v4f64: return X86ISD::VPERMILPDY;
6429 llvm_unreachable("Unknown type for vpermil");
6434 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
6435 /// a vbroadcast node. The nodes are suitable whenever we can fold a load coming
6436 /// from a 32 or 64 bit scalar. Update Op to the desired load to be folded.
6437 static bool isVectorBroadcast(SDValue &Op) {
6438 EVT VT = Op.getValueType();
6439 bool Is256 = VT.getSizeInBits() == 256;
6441 assert((VT.getSizeInBits() == 128 || Is256) &&
6442 "Unsupported type for vbroadcast node");
6445 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6446 V = V.getOperand(0);
6448 if (Is256 && !(V.hasOneUse() &&
6449 V.getOpcode() == ISD::INSERT_SUBVECTOR &&
6450 V.getOperand(0).getOpcode() == ISD::UNDEF))
6454 V = V.getOperand(1);
6459 // Check the source scalar_to_vector type. 256-bit broadcasts are
6460 // supported for 32/64-bit sizes, while 128-bit ones are only supported
6461 // for 32-bit scalars.
6462 if (V.getOpcode() != ISD::SCALAR_TO_VECTOR)
6465 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits();
6466 if (ScalarSize != 32 && ScalarSize != 64)
6468 if (!Is256 && ScalarSize == 64)
6471 V = V.getOperand(0);
6472 if (!MayFoldLoad(V))
6475 // Return the load node
6481 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6482 const TargetLowering &TLI,
6483 const X86Subtarget *Subtarget) {
6484 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6485 EVT VT = Op.getValueType();
6486 DebugLoc dl = Op.getDebugLoc();
6487 SDValue V1 = Op.getOperand(0);
6488 SDValue V2 = Op.getOperand(1);
6490 if (isZeroShuffle(SVOp))
6491 return getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl);
6493 // Handle splat operations
6494 if (SVOp->isSplat()) {
6495 unsigned NumElem = VT.getVectorNumElements();
6496 int Size = VT.getSizeInBits();
6497 // Special case, this is the only place now where it's allowed to return
6498 // a vector_shuffle operation without using a target specific node, because
6499 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6500 // this be moved to DAGCombine instead?
6501 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6504 // Use vbroadcast whenever the splat comes from a foldable load
6505 if (Subtarget->hasAVX() && isVectorBroadcast(V1))
6506 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1);
6508 // Handle splats by matching through known shuffle masks
6509 if ((Size == 128 && NumElem <= 4) ||
6510 (Size == 256 && NumElem < 8))
6513 // All remaning splats are promoted to target supported vector shuffles.
6514 return PromoteSplat(SVOp, DAG);
6517 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6519 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6520 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6521 if (NewOp.getNode())
6522 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6523 } else if ((VT == MVT::v4i32 ||
6524 (VT == MVT::v4f32 && Subtarget->hasXMMInt()))) {
6525 // FIXME: Figure out a cleaner way to do this.
6526 // Try to make use of movq to zero out the top part.
6527 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6528 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6529 if (NewOp.getNode()) {
6530 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6531 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6532 DAG, Subtarget, dl);
6534 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6535 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6536 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6537 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6538 DAG, Subtarget, dl);
6545 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6546 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6547 SDValue V1 = Op.getOperand(0);
6548 SDValue V2 = Op.getOperand(1);
6549 EVT VT = Op.getValueType();
6550 DebugLoc dl = Op.getDebugLoc();
6551 unsigned NumElems = VT.getVectorNumElements();
6552 bool isMMX = VT.getSizeInBits() == 64;
6553 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6554 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6555 bool V1IsSplat = false;
6556 bool V2IsSplat = false;
6557 bool HasXMMInt = Subtarget->hasXMMInt();
6558 MachineFunction &MF = DAG.getMachineFunction();
6559 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6561 // Shuffle operations on MMX not supported.
6565 // Vector shuffle lowering takes 3 steps:
6567 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6568 // narrowing and commutation of operands should be handled.
6569 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6571 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6572 // so the shuffle can be broken into other shuffles and the legalizer can
6573 // try the lowering again.
6575 // The general ideia is that no vector_shuffle operation should be left to
6576 // be matched during isel, all of them must be converted to a target specific
6579 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6580 // narrowing and commutation of operands should be handled. The actual code
6581 // doesn't include all of those, work in progress...
6582 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6583 if (NewOp.getNode())
6586 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6587 // unpckh_undef). Only use pshufd if speed is more important than size.
6588 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
6589 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6590 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
6591 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6593 if (X86::isMOVDDUPMask(SVOp) &&
6594 (Subtarget->hasSSE3() || Subtarget->hasAVX()) &&
6595 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6596 return getMOVDDup(Op, dl, V1, DAG);
6598 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6599 return getMOVHighToLow(Op, dl, DAG);
6601 // Use to match splats
6602 if (HasXMMInt && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
6603 (VT == MVT::v2f64 || VT == MVT::v2i64))
6604 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6606 if (X86::isPSHUFDMask(SVOp)) {
6607 // The actual implementation will match the mask in the if above and then
6608 // during isel it can match several different instructions, not only pshufd
6609 // as its name says, sad but true, emulate the behavior for now...
6610 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6611 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6613 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6615 if (HasXMMInt && (VT == MVT::v4f32 || VT == MVT::v4i32))
6616 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6618 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1,
6622 // Check if this can be converted into a logical shift.
6623 bool isLeft = false;
6626 bool isShift = getSubtarget()->hasXMMInt() &&
6627 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6628 if (isShift && ShVal.hasOneUse()) {
6629 // If the shifted value has multiple uses, it may be cheaper to use
6630 // v_set0 + movlhps or movhlps, etc.
6631 EVT EltVT = VT.getVectorElementType();
6632 ShAmt *= EltVT.getSizeInBits();
6633 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6636 if (X86::isMOVLMask(SVOp)) {
6639 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6640 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6641 if (!X86::isMOVLPMask(SVOp)) {
6642 if (HasXMMInt && (VT == MVT::v2i64 || VT == MVT::v2f64))
6643 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6645 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6646 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6650 // FIXME: fold these into legal mask.
6651 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
6652 return getMOVLowToHigh(Op, dl, DAG, HasXMMInt);
6654 if (X86::isMOVHLPSMask(SVOp))
6655 return getMOVHighToLow(Op, dl, DAG);
6657 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6658 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6660 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6661 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6663 if (X86::isMOVLPMask(SVOp))
6664 return getMOVLP(Op, dl, DAG, HasXMMInt);
6666 if (ShouldXformToMOVHLPS(SVOp) ||
6667 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6668 return CommuteVectorShuffle(SVOp, DAG);
6671 // No better options. Use a vshl / vsrl.
6672 EVT EltVT = VT.getVectorElementType();
6673 ShAmt *= EltVT.getSizeInBits();
6674 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6677 bool Commuted = false;
6678 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6679 // 1,1,1,1 -> v8i16 though.
6680 V1IsSplat = isSplatVector(V1.getNode());
6681 V2IsSplat = isSplatVector(V2.getNode());
6683 // Canonicalize the splat or undef, if present, to be on the RHS.
6684 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
6685 Op = CommuteVectorShuffle(SVOp, DAG);
6686 SVOp = cast<ShuffleVectorSDNode>(Op);
6687 V1 = SVOp->getOperand(0);
6688 V2 = SVOp->getOperand(1);
6689 std::swap(V1IsSplat, V2IsSplat);
6690 std::swap(V1IsUndef, V2IsUndef);
6694 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
6695 // Shuffling low element of v1 into undef, just return v1.
6698 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6699 // the instruction selector will not match, so get a canonical MOVL with
6700 // swapped operands to undo the commute.
6701 return getMOVL(DAG, dl, VT, V2, V1);
6704 if (X86::isUNPCKLMask(SVOp))
6705 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
6707 if (X86::isUNPCKHMask(SVOp))
6708 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
6711 // Normalize mask so all entries that point to V2 points to its first
6712 // element then try to match unpck{h|l} again. If match, return a
6713 // new vector_shuffle with the corrected mask.
6714 SDValue NewMask = NormalizeMask(SVOp, DAG);
6715 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6716 if (NSVOp != SVOp) {
6717 if (X86::isUNPCKLMask(NSVOp, true)) {
6719 } else if (X86::isUNPCKHMask(NSVOp, true)) {
6726 // Commute is back and try unpck* again.
6727 // FIXME: this seems wrong.
6728 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6729 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6731 if (X86::isUNPCKLMask(NewSVOp))
6732 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
6734 if (X86::isUNPCKHMask(NewSVOp))
6735 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
6738 // Normalize the node to match x86 shuffle ops if needed
6739 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
6740 return CommuteVectorShuffle(SVOp, DAG);
6742 // The checks below are all present in isShuffleMaskLegal, but they are
6743 // inlined here right now to enable us to directly emit target specific
6744 // nodes, and remove one by one until they don't return Op anymore.
6745 SmallVector<int, 16> M;
6748 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX()))
6749 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6750 X86::getShufflePALIGNRImmediate(SVOp),
6753 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6754 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6755 if (VT == MVT::v2f64)
6756 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
6757 if (VT == MVT::v2i64)
6758 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
6761 if (isPSHUFHWMask(M, VT))
6762 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6763 X86::getShufflePSHUFHWImmediate(SVOp),
6766 if (isPSHUFLWMask(M, VT))
6767 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6768 X86::getShufflePSHUFLWImmediate(SVOp),
6771 if (isSHUFPMask(M, VT))
6772 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6773 X86::getShuffleSHUFImmediate(SVOp), DAG);
6775 if (X86::isUNPCKL_v_undef_Mask(SVOp))
6776 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6777 if (X86::isUNPCKH_v_undef_Mask(SVOp))
6778 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6780 //===--------------------------------------------------------------------===//
6781 // Generate target specific nodes for 128 or 256-bit shuffles only
6782 // supported in the AVX instruction set.
6785 // Handle VMOVDDUPY permutations
6786 if (isMOVDDUPYMask(SVOp, Subtarget))
6787 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6789 // Handle VPERMILPS* permutations
6790 if (isVPERMILPSMask(M, VT, Subtarget))
6791 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6792 getShuffleVPERMILPSImmediate(SVOp), DAG);
6794 // Handle VPERMILPD* permutations
6795 if (isVPERMILPDMask(M, VT, Subtarget))
6796 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6797 getShuffleVPERMILPDImmediate(SVOp), DAG);
6799 // Handle VPERM2F128 permutations
6800 if (isVPERM2F128Mask(M, VT, Subtarget))
6801 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2,
6802 getShuffleVPERM2F128Immediate(SVOp), DAG);
6804 // Handle VSHUFPSY permutations
6805 if (isVSHUFPSYMask(M, VT, Subtarget))
6806 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6807 getShuffleVSHUFPSYImmediate(SVOp), DAG);
6809 // Handle VSHUFPDY permutations
6810 if (isVSHUFPDYMask(M, VT, Subtarget))
6811 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6812 getShuffleVSHUFPDYImmediate(SVOp), DAG);
6814 //===--------------------------------------------------------------------===//
6815 // Since no target specific shuffle was selected for this generic one,
6816 // lower it into other known shuffles. FIXME: this isn't true yet, but
6817 // this is the plan.
6820 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6821 if (VT == MVT::v8i16) {
6822 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6823 if (NewOp.getNode())
6827 if (VT == MVT::v16i8) {
6828 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6829 if (NewOp.getNode())
6833 // Handle all 128-bit wide vectors with 4 elements, and match them with
6834 // several different shuffle types.
6835 if (NumElems == 4 && VT.getSizeInBits() == 128)
6836 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6838 // Handle general 256-bit shuffles
6839 if (VT.is256BitVector())
6840 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6846 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6847 SelectionDAG &DAG) const {
6848 EVT VT = Op.getValueType();
6849 DebugLoc dl = Op.getDebugLoc();
6851 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6854 if (VT.getSizeInBits() == 8) {
6855 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6856 Op.getOperand(0), Op.getOperand(1));
6857 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6858 DAG.getValueType(VT));
6859 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6860 } else if (VT.getSizeInBits() == 16) {
6861 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6862 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6864 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6865 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6866 DAG.getNode(ISD::BITCAST, dl,
6870 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6871 Op.getOperand(0), Op.getOperand(1));
6872 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6873 DAG.getValueType(VT));
6874 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6875 } else if (VT == MVT::f32) {
6876 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6877 // the result back to FR32 register. It's only worth matching if the
6878 // result has a single use which is a store or a bitcast to i32. And in
6879 // the case of a store, it's not worth it if the index is a constant 0,
6880 // because a MOVSSmr can be used instead, which is smaller and faster.
6881 if (!Op.hasOneUse())
6883 SDNode *User = *Op.getNode()->use_begin();
6884 if ((User->getOpcode() != ISD::STORE ||
6885 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6886 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6887 (User->getOpcode() != ISD::BITCAST ||
6888 User->getValueType(0) != MVT::i32))
6890 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6891 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6894 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6895 } else if (VT == MVT::i32) {
6896 // ExtractPS works with constant index.
6897 if (isa<ConstantSDNode>(Op.getOperand(1)))
6905 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6906 SelectionDAG &DAG) const {
6907 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6910 SDValue Vec = Op.getOperand(0);
6911 EVT VecVT = Vec.getValueType();
6913 // If this is a 256-bit vector result, first extract the 128-bit vector and
6914 // then extract the element from the 128-bit vector.
6915 if (VecVT.getSizeInBits() == 256) {
6916 DebugLoc dl = Op.getNode()->getDebugLoc();
6917 unsigned NumElems = VecVT.getVectorNumElements();
6918 SDValue Idx = Op.getOperand(1);
6919 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6921 // Get the 128-bit vector.
6922 bool Upper = IdxVal >= NumElems/2;
6923 Vec = Extract128BitVector(Vec,
6924 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6926 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6927 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6930 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6932 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
6933 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6938 EVT VT = Op.getValueType();
6939 DebugLoc dl = Op.getDebugLoc();
6940 // TODO: handle v16i8.
6941 if (VT.getSizeInBits() == 16) {
6942 SDValue Vec = Op.getOperand(0);
6943 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6945 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6946 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6947 DAG.getNode(ISD::BITCAST, dl,
6950 // Transform it so it match pextrw which produces a 32-bit result.
6951 EVT EltVT = MVT::i32;
6952 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6953 Op.getOperand(0), Op.getOperand(1));
6954 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6955 DAG.getValueType(VT));
6956 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6957 } else if (VT.getSizeInBits() == 32) {
6958 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6962 // SHUFPS the element to the lowest double word, then movss.
6963 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6964 EVT VVT = Op.getOperand(0).getValueType();
6965 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6966 DAG.getUNDEF(VVT), Mask);
6967 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6968 DAG.getIntPtrConstant(0));
6969 } else if (VT.getSizeInBits() == 64) {
6970 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6971 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6972 // to match extract_elt for f64.
6973 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6977 // UNPCKHPD the element to the lowest double word, then movsd.
6978 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6979 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6980 int Mask[2] = { 1, -1 };
6981 EVT VVT = Op.getOperand(0).getValueType();
6982 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6983 DAG.getUNDEF(VVT), Mask);
6984 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6985 DAG.getIntPtrConstant(0));
6992 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6993 SelectionDAG &DAG) const {
6994 EVT VT = Op.getValueType();
6995 EVT EltVT = VT.getVectorElementType();
6996 DebugLoc dl = Op.getDebugLoc();
6998 SDValue N0 = Op.getOperand(0);
6999 SDValue N1 = Op.getOperand(1);
7000 SDValue N2 = Op.getOperand(2);
7002 if (VT.getSizeInBits() == 256)
7005 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7006 isa<ConstantSDNode>(N2)) {
7008 if (VT == MVT::v8i16)
7009 Opc = X86ISD::PINSRW;
7010 else if (VT == MVT::v16i8)
7011 Opc = X86ISD::PINSRB;
7013 Opc = X86ISD::PINSRB;
7015 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7017 if (N1.getValueType() != MVT::i32)
7018 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7019 if (N2.getValueType() != MVT::i32)
7020 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7021 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7022 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7023 // Bits [7:6] of the constant are the source select. This will always be
7024 // zero here. The DAG Combiner may combine an extract_elt index into these
7025 // bits. For example (insert (extract, 3), 2) could be matched by putting
7026 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7027 // Bits [5:4] of the constant are the destination select. This is the
7028 // value of the incoming immediate.
7029 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7030 // combine either bitwise AND or insert of float 0.0 to set these bits.
7031 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7032 // Create this as a scalar to vector..
7033 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7034 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7035 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
7036 // PINSR* works with constant index.
7043 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7044 EVT VT = Op.getValueType();
7045 EVT EltVT = VT.getVectorElementType();
7047 DebugLoc dl = Op.getDebugLoc();
7048 SDValue N0 = Op.getOperand(0);
7049 SDValue N1 = Op.getOperand(1);
7050 SDValue N2 = Op.getOperand(2);
7052 // If this is a 256-bit vector result, first extract the 128-bit vector,
7053 // insert the element into the extracted half and then place it back.
7054 if (VT.getSizeInBits() == 256) {
7055 if (!isa<ConstantSDNode>(N2))
7058 // Get the desired 128-bit vector half.
7059 unsigned NumElems = VT.getVectorNumElements();
7060 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7061 bool Upper = IdxVal >= NumElems/2;
7062 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
7063 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
7065 // Insert the element into the desired half.
7066 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
7067 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
7069 // Insert the changed part back to the 256-bit vector
7070 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
7073 if (Subtarget->hasSSE41() || Subtarget->hasAVX())
7074 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7076 if (EltVT == MVT::i8)
7079 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7080 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7081 // as its second argument.
7082 if (N1.getValueType() != MVT::i32)
7083 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7084 if (N2.getValueType() != MVT::i32)
7085 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7086 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7092 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7093 LLVMContext *Context = DAG.getContext();
7094 DebugLoc dl = Op.getDebugLoc();
7095 EVT OpVT = Op.getValueType();
7097 // If this is a 256-bit vector result, first insert into a 128-bit
7098 // vector and then insert into the 256-bit vector.
7099 if (OpVT.getSizeInBits() > 128) {
7100 // Insert into a 128-bit vector.
7101 EVT VT128 = EVT::getVectorVT(*Context,
7102 OpVT.getVectorElementType(),
7103 OpVT.getVectorNumElements() / 2);
7105 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7107 // Insert the 128-bit vector.
7108 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
7109 DAG.getConstant(0, MVT::i32),
7113 if (Op.getValueType() == MVT::v1i64 &&
7114 Op.getOperand(0).getValueType() == MVT::i64)
7115 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7117 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7118 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7119 "Expected an SSE type!");
7120 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7121 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7124 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7125 // a simple subregister reference or explicit instructions to grab
7126 // upper bits of a vector.
7128 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7129 if (Subtarget->hasAVX()) {
7130 DebugLoc dl = Op.getNode()->getDebugLoc();
7131 SDValue Vec = Op.getNode()->getOperand(0);
7132 SDValue Idx = Op.getNode()->getOperand(1);
7134 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7135 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7136 return Extract128BitVector(Vec, Idx, DAG, dl);
7142 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7143 // simple superregister reference or explicit instructions to insert
7144 // the upper bits of a vector.
7146 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7147 if (Subtarget->hasAVX()) {
7148 DebugLoc dl = Op.getNode()->getDebugLoc();
7149 SDValue Vec = Op.getNode()->getOperand(0);
7150 SDValue SubVec = Op.getNode()->getOperand(1);
7151 SDValue Idx = Op.getNode()->getOperand(2);
7153 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7154 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7155 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7161 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7162 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7163 // one of the above mentioned nodes. It has to be wrapped because otherwise
7164 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7165 // be used to form addressing mode. These wrapped nodes will be selected
7168 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7169 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7171 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7173 unsigned char OpFlag = 0;
7174 unsigned WrapperKind = X86ISD::Wrapper;
7175 CodeModel::Model M = getTargetMachine().getCodeModel();
7177 if (Subtarget->isPICStyleRIPRel() &&
7178 (M == CodeModel::Small || M == CodeModel::Kernel))
7179 WrapperKind = X86ISD::WrapperRIP;
7180 else if (Subtarget->isPICStyleGOT())
7181 OpFlag = X86II::MO_GOTOFF;
7182 else if (Subtarget->isPICStyleStubPIC())
7183 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7185 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7187 CP->getOffset(), OpFlag);
7188 DebugLoc DL = CP->getDebugLoc();
7189 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7190 // With PIC, the address is actually $g + Offset.
7192 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7193 DAG.getNode(X86ISD::GlobalBaseReg,
7194 DebugLoc(), getPointerTy()),
7201 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7202 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7204 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7206 unsigned char OpFlag = 0;
7207 unsigned WrapperKind = X86ISD::Wrapper;
7208 CodeModel::Model M = getTargetMachine().getCodeModel();
7210 if (Subtarget->isPICStyleRIPRel() &&
7211 (M == CodeModel::Small || M == CodeModel::Kernel))
7212 WrapperKind = X86ISD::WrapperRIP;
7213 else if (Subtarget->isPICStyleGOT())
7214 OpFlag = X86II::MO_GOTOFF;
7215 else if (Subtarget->isPICStyleStubPIC())
7216 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7218 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7220 DebugLoc DL = JT->getDebugLoc();
7221 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7223 // With PIC, the address is actually $g + Offset.
7225 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7226 DAG.getNode(X86ISD::GlobalBaseReg,
7227 DebugLoc(), getPointerTy()),
7234 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7235 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7237 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7239 unsigned char OpFlag = 0;
7240 unsigned WrapperKind = X86ISD::Wrapper;
7241 CodeModel::Model M = getTargetMachine().getCodeModel();
7243 if (Subtarget->isPICStyleRIPRel() &&
7244 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7245 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7246 OpFlag = X86II::MO_GOTPCREL;
7247 WrapperKind = X86ISD::WrapperRIP;
7248 } else if (Subtarget->isPICStyleGOT()) {
7249 OpFlag = X86II::MO_GOT;
7250 } else if (Subtarget->isPICStyleStubPIC()) {
7251 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7252 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7253 OpFlag = X86II::MO_DARWIN_NONLAZY;
7256 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7258 DebugLoc DL = Op.getDebugLoc();
7259 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7262 // With PIC, the address is actually $g + Offset.
7263 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7264 !Subtarget->is64Bit()) {
7265 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7266 DAG.getNode(X86ISD::GlobalBaseReg,
7267 DebugLoc(), getPointerTy()),
7271 // For symbols that require a load from a stub to get the address, emit the
7273 if (isGlobalStubReference(OpFlag))
7274 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7275 MachinePointerInfo::getGOT(), false, false, 0);
7281 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7282 // Create the TargetBlockAddressAddress node.
7283 unsigned char OpFlags =
7284 Subtarget->ClassifyBlockAddressReference();
7285 CodeModel::Model M = getTargetMachine().getCodeModel();
7286 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7287 DebugLoc dl = Op.getDebugLoc();
7288 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7289 /*isTarget=*/true, OpFlags);
7291 if (Subtarget->isPICStyleRIPRel() &&
7292 (M == CodeModel::Small || M == CodeModel::Kernel))
7293 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7295 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7297 // With PIC, the address is actually $g + Offset.
7298 if (isGlobalRelativeToPICBase(OpFlags)) {
7299 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7300 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7308 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7310 SelectionDAG &DAG) const {
7311 // Create the TargetGlobalAddress node, folding in the constant
7312 // offset if it is legal.
7313 unsigned char OpFlags =
7314 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7315 CodeModel::Model M = getTargetMachine().getCodeModel();
7317 if (OpFlags == X86II::MO_NO_FLAG &&
7318 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7319 // A direct static reference to a global.
7320 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7323 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7326 if (Subtarget->isPICStyleRIPRel() &&
7327 (M == CodeModel::Small || M == CodeModel::Kernel))
7328 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7330 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7332 // With PIC, the address is actually $g + Offset.
7333 if (isGlobalRelativeToPICBase(OpFlags)) {
7334 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7335 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7339 // For globals that require a load from a stub to get the address, emit the
7341 if (isGlobalStubReference(OpFlags))
7342 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7343 MachinePointerInfo::getGOT(), false, false, 0);
7345 // If there was a non-zero offset that we didn't fold, create an explicit
7348 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7349 DAG.getConstant(Offset, getPointerTy()));
7355 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7356 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7357 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7358 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7362 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7363 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7364 unsigned char OperandFlags) {
7365 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7366 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7367 DebugLoc dl = GA->getDebugLoc();
7368 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7369 GA->getValueType(0),
7373 SDValue Ops[] = { Chain, TGA, *InFlag };
7374 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7376 SDValue Ops[] = { Chain, TGA };
7377 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7380 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7381 MFI->setAdjustsStack(true);
7383 SDValue Flag = Chain.getValue(1);
7384 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7387 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7389 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7392 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7393 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7394 DAG.getNode(X86ISD::GlobalBaseReg,
7395 DebugLoc(), PtrVT), InFlag);
7396 InFlag = Chain.getValue(1);
7398 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7401 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7403 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7405 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7406 X86::RAX, X86II::MO_TLSGD);
7409 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7410 // "local exec" model.
7411 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7412 const EVT PtrVT, TLSModel::Model model,
7414 DebugLoc dl = GA->getDebugLoc();
7416 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7417 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7418 is64Bit ? 257 : 256));
7420 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7421 DAG.getIntPtrConstant(0),
7422 MachinePointerInfo(Ptr), false, false, 0);
7424 unsigned char OperandFlags = 0;
7425 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7427 unsigned WrapperKind = X86ISD::Wrapper;
7428 if (model == TLSModel::LocalExec) {
7429 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7430 } else if (is64Bit) {
7431 assert(model == TLSModel::InitialExec);
7432 OperandFlags = X86II::MO_GOTTPOFF;
7433 WrapperKind = X86ISD::WrapperRIP;
7435 assert(model == TLSModel::InitialExec);
7436 OperandFlags = X86II::MO_INDNTPOFF;
7439 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7441 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7442 GA->getValueType(0),
7443 GA->getOffset(), OperandFlags);
7444 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7446 if (model == TLSModel::InitialExec)
7447 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7448 MachinePointerInfo::getGOT(), false, false, 0);
7450 // The address of the thread local variable is the add of the thread
7451 // pointer with the offset of the variable.
7452 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7456 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7458 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7459 const GlobalValue *GV = GA->getGlobal();
7461 if (Subtarget->isTargetELF()) {
7462 // TODO: implement the "local dynamic" model
7463 // TODO: implement the "initial exec"model for pic executables
7465 // If GV is an alias then use the aliasee for determining
7466 // thread-localness.
7467 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7468 GV = GA->resolveAliasedGlobal(false);
7470 TLSModel::Model model
7471 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7474 case TLSModel::GeneralDynamic:
7475 case TLSModel::LocalDynamic: // not implemented
7476 if (Subtarget->is64Bit())
7477 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7478 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7480 case TLSModel::InitialExec:
7481 case TLSModel::LocalExec:
7482 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7483 Subtarget->is64Bit());
7485 } else if (Subtarget->isTargetDarwin()) {
7486 // Darwin only has one model of TLS. Lower to that.
7487 unsigned char OpFlag = 0;
7488 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7489 X86ISD::WrapperRIP : X86ISD::Wrapper;
7491 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7493 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7494 !Subtarget->is64Bit();
7496 OpFlag = X86II::MO_TLVP_PIC_BASE;
7498 OpFlag = X86II::MO_TLVP;
7499 DebugLoc DL = Op.getDebugLoc();
7500 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7501 GA->getValueType(0),
7502 GA->getOffset(), OpFlag);
7503 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7505 // With PIC32, the address is actually $g + Offset.
7507 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7508 DAG.getNode(X86ISD::GlobalBaseReg,
7509 DebugLoc(), getPointerTy()),
7512 // Lowering the machine isd will make sure everything is in the right
7514 SDValue Chain = DAG.getEntryNode();
7515 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7516 SDValue Args[] = { Chain, Offset };
7517 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7519 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7520 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7521 MFI->setAdjustsStack(true);
7523 // And our return value (tls address) is in the standard call return value
7525 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7526 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
7530 "TLS not implemented for this target.");
7532 llvm_unreachable("Unreachable");
7537 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7538 /// take a 2 x i32 value to shift plus a shift amount.
7539 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7540 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7541 EVT VT = Op.getValueType();
7542 unsigned VTBits = VT.getSizeInBits();
7543 DebugLoc dl = Op.getDebugLoc();
7544 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7545 SDValue ShOpLo = Op.getOperand(0);
7546 SDValue ShOpHi = Op.getOperand(1);
7547 SDValue ShAmt = Op.getOperand(2);
7548 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7549 DAG.getConstant(VTBits - 1, MVT::i8))
7550 : DAG.getConstant(0, VT);
7553 if (Op.getOpcode() == ISD::SHL_PARTS) {
7554 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7555 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7557 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7558 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7561 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7562 DAG.getConstant(VTBits, MVT::i8));
7563 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7564 AndNode, DAG.getConstant(0, MVT::i8));
7567 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7568 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7569 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7571 if (Op.getOpcode() == ISD::SHL_PARTS) {
7572 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7573 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7575 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7576 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7579 SDValue Ops[2] = { Lo, Hi };
7580 return DAG.getMergeValues(Ops, 2, dl);
7583 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7584 SelectionDAG &DAG) const {
7585 EVT SrcVT = Op.getOperand(0).getValueType();
7587 if (SrcVT.isVector())
7590 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7591 "Unknown SINT_TO_FP to lower!");
7593 // These are really Legal; return the operand so the caller accepts it as
7595 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7597 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7598 Subtarget->is64Bit()) {
7602 DebugLoc dl = Op.getDebugLoc();
7603 unsigned Size = SrcVT.getSizeInBits()/8;
7604 MachineFunction &MF = DAG.getMachineFunction();
7605 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7606 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7607 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7609 MachinePointerInfo::getFixedStack(SSFI),
7611 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7614 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7616 SelectionDAG &DAG) const {
7618 DebugLoc DL = Op.getDebugLoc();
7620 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7622 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7624 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7626 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7628 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7629 MachineMemOperand *MMO;
7631 int SSFI = FI->getIndex();
7633 DAG.getMachineFunction()
7634 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7635 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7637 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7638 StackSlot = StackSlot.getOperand(1);
7640 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7641 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7643 Tys, Ops, array_lengthof(Ops),
7647 Chain = Result.getValue(1);
7648 SDValue InFlag = Result.getValue(2);
7650 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7651 // shouldn't be necessary except that RFP cannot be live across
7652 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7653 MachineFunction &MF = DAG.getMachineFunction();
7654 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7655 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7656 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7657 Tys = DAG.getVTList(MVT::Other);
7659 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7661 MachineMemOperand *MMO =
7662 DAG.getMachineFunction()
7663 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7664 MachineMemOperand::MOStore, SSFISize, SSFISize);
7666 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7667 Ops, array_lengthof(Ops),
7668 Op.getValueType(), MMO);
7669 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7670 MachinePointerInfo::getFixedStack(SSFI),
7677 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7678 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7679 SelectionDAG &DAG) const {
7680 // This algorithm is not obvious. Here it is in C code, more or less:
7682 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7683 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7684 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7686 // Copy ints to xmm registers.
7687 __m128i xh = _mm_cvtsi32_si128( hi );
7688 __m128i xl = _mm_cvtsi32_si128( lo );
7690 // Combine into low half of a single xmm register.
7691 __m128i x = _mm_unpacklo_epi32( xh, xl );
7695 // Merge in appropriate exponents to give the integer bits the right
7697 x = _mm_unpacklo_epi32( x, exp );
7699 // Subtract away the biases to deal with the IEEE-754 double precision
7701 d = _mm_sub_pd( (__m128d) x, bias );
7703 // All conversions up to here are exact. The correctly rounded result is
7704 // calculated using the current rounding mode using the following
7706 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7707 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7708 // store doesn't really need to be here (except
7709 // maybe to zero the other double)
7714 DebugLoc dl = Op.getDebugLoc();
7715 LLVMContext *Context = DAG.getContext();
7717 // Build some magic constants.
7718 std::vector<Constant*> CV0;
7719 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7720 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7721 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7722 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7723 Constant *C0 = ConstantVector::get(CV0);
7724 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7726 std::vector<Constant*> CV1;
7728 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7730 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7731 Constant *C1 = ConstantVector::get(CV1);
7732 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7734 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7735 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7737 DAG.getIntPtrConstant(1)));
7738 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7739 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7741 DAG.getIntPtrConstant(0)));
7742 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7743 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7744 MachinePointerInfo::getConstantPool(),
7746 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7747 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7748 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7749 MachinePointerInfo::getConstantPool(),
7751 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7753 // Add the halves; easiest way is to swap them into another reg first.
7754 int ShufMask[2] = { 1, -1 };
7755 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7756 DAG.getUNDEF(MVT::v2f64), ShufMask);
7757 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7758 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7759 DAG.getIntPtrConstant(0));
7762 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7763 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7764 SelectionDAG &DAG) const {
7765 DebugLoc dl = Op.getDebugLoc();
7766 // FP constant to bias correct the final result.
7767 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7770 // Load the 32-bit value into an XMM register.
7771 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7774 // Zero out the upper parts of the register.
7775 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasXMMInt(),
7778 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7779 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7780 DAG.getIntPtrConstant(0));
7782 // Or the load with the bias.
7783 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7784 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7785 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7787 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7788 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7789 MVT::v2f64, Bias)));
7790 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7791 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7792 DAG.getIntPtrConstant(0));
7794 // Subtract the bias.
7795 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7797 // Handle final rounding.
7798 EVT DestVT = Op.getValueType();
7800 if (DestVT.bitsLT(MVT::f64)) {
7801 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7802 DAG.getIntPtrConstant(0));
7803 } else if (DestVT.bitsGT(MVT::f64)) {
7804 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7807 // Handle final rounding.
7811 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7812 SelectionDAG &DAG) const {
7813 SDValue N0 = Op.getOperand(0);
7814 DebugLoc dl = Op.getDebugLoc();
7816 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7817 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7818 // the optimization here.
7819 if (DAG.SignBitIsZero(N0))
7820 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7822 EVT SrcVT = N0.getValueType();
7823 EVT DstVT = Op.getValueType();
7824 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7825 return LowerUINT_TO_FP_i64(Op, DAG);
7826 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7827 return LowerUINT_TO_FP_i32(Op, DAG);
7829 // Make a 64-bit buffer, and use it to build an FILD.
7830 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7831 if (SrcVT == MVT::i32) {
7832 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7833 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7834 getPointerTy(), StackSlot, WordOff);
7835 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7836 StackSlot, MachinePointerInfo(),
7838 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7839 OffsetSlot, MachinePointerInfo(),
7841 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7845 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7846 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7847 StackSlot, MachinePointerInfo(),
7849 // For i64 source, we need to add the appropriate power of 2 if the input
7850 // was negative. This is the same as the optimization in
7851 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7852 // we must be careful to do the computation in x87 extended precision, not
7853 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7854 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7855 MachineMemOperand *MMO =
7856 DAG.getMachineFunction()
7857 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7858 MachineMemOperand::MOLoad, 8, 8);
7860 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7861 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7862 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7865 APInt FF(32, 0x5F800000ULL);
7867 // Check whether the sign bit is set.
7868 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7869 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7872 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7873 SDValue FudgePtr = DAG.getConstantPool(
7874 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7877 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7878 SDValue Zero = DAG.getIntPtrConstant(0);
7879 SDValue Four = DAG.getIntPtrConstant(4);
7880 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7882 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7884 // Load the value out, extending it from f32 to f80.
7885 // FIXME: Avoid the extend by constructing the right constant pool?
7886 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7887 FudgePtr, MachinePointerInfo::getConstantPool(),
7888 MVT::f32, false, false, 4);
7889 // Extend everything to 80 bits to force it to be done on x87.
7890 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7891 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7894 std::pair<SDValue,SDValue> X86TargetLowering::
7895 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7896 DebugLoc DL = Op.getDebugLoc();
7898 EVT DstTy = Op.getValueType();
7901 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7905 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7906 DstTy.getSimpleVT() >= MVT::i16 &&
7907 "Unknown FP_TO_SINT to lower!");
7909 // These are really Legal.
7910 if (DstTy == MVT::i32 &&
7911 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7912 return std::make_pair(SDValue(), SDValue());
7913 if (Subtarget->is64Bit() &&
7914 DstTy == MVT::i64 &&
7915 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7916 return std::make_pair(SDValue(), SDValue());
7918 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7920 MachineFunction &MF = DAG.getMachineFunction();
7921 unsigned MemSize = DstTy.getSizeInBits()/8;
7922 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7923 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7928 switch (DstTy.getSimpleVT().SimpleTy) {
7929 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7930 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7931 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7932 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7935 SDValue Chain = DAG.getEntryNode();
7936 SDValue Value = Op.getOperand(0);
7937 EVT TheVT = Op.getOperand(0).getValueType();
7938 if (isScalarFPTypeInSSEReg(TheVT)) {
7939 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7940 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7941 MachinePointerInfo::getFixedStack(SSFI),
7943 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7945 Chain, StackSlot, DAG.getValueType(TheVT)
7948 MachineMemOperand *MMO =
7949 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7950 MachineMemOperand::MOLoad, MemSize, MemSize);
7951 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7953 Chain = Value.getValue(1);
7954 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7955 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7958 MachineMemOperand *MMO =
7959 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7960 MachineMemOperand::MOStore, MemSize, MemSize);
7962 // Build the FP_TO_INT*_IN_MEM
7963 SDValue Ops[] = { Chain, Value, StackSlot };
7964 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7965 Ops, 3, DstTy, MMO);
7967 return std::make_pair(FIST, StackSlot);
7970 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7971 SelectionDAG &DAG) const {
7972 if (Op.getValueType().isVector())
7975 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7976 SDValue FIST = Vals.first, StackSlot = Vals.second;
7977 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7978 if (FIST.getNode() == 0) return Op;
7981 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7982 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7985 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7986 SelectionDAG &DAG) const {
7987 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7988 SDValue FIST = Vals.first, StackSlot = Vals.second;
7989 assert(FIST.getNode() && "Unexpected failure");
7992 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7993 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7996 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7997 SelectionDAG &DAG) const {
7998 LLVMContext *Context = DAG.getContext();
7999 DebugLoc dl = Op.getDebugLoc();
8000 EVT VT = Op.getValueType();
8003 EltVT = VT.getVectorElementType();
8004 std::vector<Constant*> CV;
8005 if (EltVT == MVT::f64) {
8006 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
8010 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
8016 Constant *C = ConstantVector::get(CV);
8017 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8018 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8019 MachinePointerInfo::getConstantPool(),
8021 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8024 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8025 LLVMContext *Context = DAG.getContext();
8026 DebugLoc dl = Op.getDebugLoc();
8027 EVT VT = Op.getValueType();
8030 EltVT = VT.getVectorElementType();
8031 std::vector<Constant*> CV;
8032 if (EltVT == MVT::f64) {
8033 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8037 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8043 Constant *C = ConstantVector::get(CV);
8044 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8045 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8046 MachinePointerInfo::getConstantPool(),
8048 if (VT.isVector()) {
8049 return DAG.getNode(ISD::BITCAST, dl, VT,
8050 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
8051 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8053 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
8055 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8059 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8060 LLVMContext *Context = DAG.getContext();
8061 SDValue Op0 = Op.getOperand(0);
8062 SDValue Op1 = Op.getOperand(1);
8063 DebugLoc dl = Op.getDebugLoc();
8064 EVT VT = Op.getValueType();
8065 EVT SrcVT = Op1.getValueType();
8067 // If second operand is smaller, extend it first.
8068 if (SrcVT.bitsLT(VT)) {
8069 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8072 // And if it is bigger, shrink it first.
8073 if (SrcVT.bitsGT(VT)) {
8074 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8078 // At this point the operands and the result should have the same
8079 // type, and that won't be f80 since that is not custom lowered.
8081 // First get the sign bit of second operand.
8082 std::vector<Constant*> CV;
8083 if (SrcVT == MVT::f64) {
8084 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8085 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8087 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8088 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8089 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8090 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8092 Constant *C = ConstantVector::get(CV);
8093 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8094 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8095 MachinePointerInfo::getConstantPool(),
8097 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8099 // Shift sign bit right or left if the two operands have different types.
8100 if (SrcVT.bitsGT(VT)) {
8101 // Op0 is MVT::f32, Op1 is MVT::f64.
8102 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8103 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8104 DAG.getConstant(32, MVT::i32));
8105 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8106 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8107 DAG.getIntPtrConstant(0));
8110 // Clear first operand sign bit.
8112 if (VT == MVT::f64) {
8113 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8114 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8116 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8117 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8118 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8119 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8121 C = ConstantVector::get(CV);
8122 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8123 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8124 MachinePointerInfo::getConstantPool(),
8126 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8128 // Or the value with the sign bit.
8129 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8132 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8133 SDValue N0 = Op.getOperand(0);
8134 DebugLoc dl = Op.getDebugLoc();
8135 EVT VT = Op.getValueType();
8137 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8138 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8139 DAG.getConstant(1, VT));
8140 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8143 /// Emit nodes that will be selected as "test Op0,Op0", or something
8145 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8146 SelectionDAG &DAG) const {
8147 DebugLoc dl = Op.getDebugLoc();
8149 // CF and OF aren't always set the way we want. Determine which
8150 // of these we need.
8151 bool NeedCF = false;
8152 bool NeedOF = false;
8155 case X86::COND_A: case X86::COND_AE:
8156 case X86::COND_B: case X86::COND_BE:
8159 case X86::COND_G: case X86::COND_GE:
8160 case X86::COND_L: case X86::COND_LE:
8161 case X86::COND_O: case X86::COND_NO:
8166 // See if we can use the EFLAGS value from the operand instead of
8167 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8168 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8169 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8170 // Emit a CMP with 0, which is the TEST pattern.
8171 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8172 DAG.getConstant(0, Op.getValueType()));
8174 unsigned Opcode = 0;
8175 unsigned NumOperands = 0;
8176 switch (Op.getNode()->getOpcode()) {
8178 // Due to an isel shortcoming, be conservative if this add is likely to be
8179 // selected as part of a load-modify-store instruction. When the root node
8180 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8181 // uses of other nodes in the match, such as the ADD in this case. This
8182 // leads to the ADD being left around and reselected, with the result being
8183 // two adds in the output. Alas, even if none our users are stores, that
8184 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8185 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8186 // climbing the DAG back to the root, and it doesn't seem to be worth the
8188 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8189 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8190 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
8193 if (ConstantSDNode *C =
8194 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8195 // An add of one will be selected as an INC.
8196 if (C->getAPIntValue() == 1) {
8197 Opcode = X86ISD::INC;
8202 // An add of negative one (subtract of one) will be selected as a DEC.
8203 if (C->getAPIntValue().isAllOnesValue()) {
8204 Opcode = X86ISD::DEC;
8210 // Otherwise use a regular EFLAGS-setting add.
8211 Opcode = X86ISD::ADD;
8215 // If the primary and result isn't used, don't bother using X86ISD::AND,
8216 // because a TEST instruction will be better.
8217 bool NonFlagUse = false;
8218 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8219 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8221 unsigned UOpNo = UI.getOperandNo();
8222 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8223 // Look pass truncate.
8224 UOpNo = User->use_begin().getOperandNo();
8225 User = *User->use_begin();
8228 if (User->getOpcode() != ISD::BRCOND &&
8229 User->getOpcode() != ISD::SETCC &&
8230 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8243 // Due to the ISEL shortcoming noted above, be conservative if this op is
8244 // likely to be selected as part of a load-modify-store instruction.
8245 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8246 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8247 if (UI->getOpcode() == ISD::STORE)
8250 // Otherwise use a regular EFLAGS-setting instruction.
8251 switch (Op.getNode()->getOpcode()) {
8252 default: llvm_unreachable("unexpected operator!");
8253 case ISD::SUB: Opcode = X86ISD::SUB; break;
8254 case ISD::OR: Opcode = X86ISD::OR; break;
8255 case ISD::XOR: Opcode = X86ISD::XOR; break;
8256 case ISD::AND: Opcode = X86ISD::AND; break;
8268 return SDValue(Op.getNode(), 1);
8275 // Emit a CMP with 0, which is the TEST pattern.
8276 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8277 DAG.getConstant(0, Op.getValueType()));
8279 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8280 SmallVector<SDValue, 4> Ops;
8281 for (unsigned i = 0; i != NumOperands; ++i)
8282 Ops.push_back(Op.getOperand(i));
8284 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8285 DAG.ReplaceAllUsesWith(Op, New);
8286 return SDValue(New.getNode(), 1);
8289 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8291 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8292 SelectionDAG &DAG) const {
8293 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8294 if (C->getAPIntValue() == 0)
8295 return EmitTest(Op0, X86CC, DAG);
8297 DebugLoc dl = Op0.getDebugLoc();
8298 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8301 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8302 /// if it's possible.
8303 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8304 DebugLoc dl, SelectionDAG &DAG) const {
8305 SDValue Op0 = And.getOperand(0);
8306 SDValue Op1 = And.getOperand(1);
8307 if (Op0.getOpcode() == ISD::TRUNCATE)
8308 Op0 = Op0.getOperand(0);
8309 if (Op1.getOpcode() == ISD::TRUNCATE)
8310 Op1 = Op1.getOperand(0);
8313 if (Op1.getOpcode() == ISD::SHL)
8314 std::swap(Op0, Op1);
8315 if (Op0.getOpcode() == ISD::SHL) {
8316 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8317 if (And00C->getZExtValue() == 1) {
8318 // If we looked past a truncate, check that it's only truncating away
8320 unsigned BitWidth = Op0.getValueSizeInBits();
8321 unsigned AndBitWidth = And.getValueSizeInBits();
8322 if (BitWidth > AndBitWidth) {
8323 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8324 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8325 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8329 RHS = Op0.getOperand(1);
8331 } else if (Op1.getOpcode() == ISD::Constant) {
8332 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8333 SDValue AndLHS = Op0;
8334 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
8335 LHS = AndLHS.getOperand(0);
8336 RHS = AndLHS.getOperand(1);
8340 if (LHS.getNode()) {
8341 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8342 // instruction. Since the shift amount is in-range-or-undefined, we know
8343 // that doing a bittest on the i32 value is ok. We extend to i32 because
8344 // the encoding for the i16 version is larger than the i32 version.
8345 // Also promote i16 to i32 for performance / code size reason.
8346 if (LHS.getValueType() == MVT::i8 ||
8347 LHS.getValueType() == MVT::i16)
8348 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8350 // If the operand types disagree, extend the shift amount to match. Since
8351 // BT ignores high bits (like shifts) we can use anyextend.
8352 if (LHS.getValueType() != RHS.getValueType())
8353 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8355 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8356 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8357 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8358 DAG.getConstant(Cond, MVT::i8), BT);
8364 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8366 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8368 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8369 SDValue Op0 = Op.getOperand(0);
8370 SDValue Op1 = Op.getOperand(1);
8371 DebugLoc dl = Op.getDebugLoc();
8372 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8374 // Optimize to BT if possible.
8375 // Lower (X & (1 << N)) == 0 to BT(X, N).
8376 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8377 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8378 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8379 Op1.getOpcode() == ISD::Constant &&
8380 cast<ConstantSDNode>(Op1)->isNullValue() &&
8381 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8382 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8383 if (NewSetCC.getNode())
8387 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8389 if (Op1.getOpcode() == ISD::Constant &&
8390 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8391 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8392 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8394 // If the input is a setcc, then reuse the input setcc or use a new one with
8395 // the inverted condition.
8396 if (Op0.getOpcode() == X86ISD::SETCC) {
8397 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8398 bool Invert = (CC == ISD::SETNE) ^
8399 cast<ConstantSDNode>(Op1)->isNullValue();
8400 if (!Invert) return Op0;
8402 CCode = X86::GetOppositeBranchCondition(CCode);
8403 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8404 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8408 bool isFP = Op1.getValueType().isFloatingPoint();
8409 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8410 if (X86CC == X86::COND_INVALID)
8413 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8414 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8415 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8418 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8419 // ones, and then concatenate the result back.
8420 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8421 EVT VT = Op.getValueType();
8423 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8424 "Unsupported value type for operation");
8426 int NumElems = VT.getVectorNumElements();
8427 DebugLoc dl = Op.getDebugLoc();
8428 SDValue CC = Op.getOperand(2);
8429 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8430 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8432 // Extract the LHS vectors
8433 SDValue LHS = Op.getOperand(0);
8434 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8435 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8437 // Extract the RHS vectors
8438 SDValue RHS = Op.getOperand(1);
8439 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8440 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8442 // Issue the operation on the smaller types and concatenate the result back
8443 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8444 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8445 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8446 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8447 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8451 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8453 SDValue Op0 = Op.getOperand(0);
8454 SDValue Op1 = Op.getOperand(1);
8455 SDValue CC = Op.getOperand(2);
8456 EVT VT = Op.getValueType();
8457 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8458 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8459 DebugLoc dl = Op.getDebugLoc();
8463 EVT EltVT = Op0.getValueType().getVectorElementType();
8464 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8466 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8469 // SSE Condition code mapping:
8478 switch (SetCCOpcode) {
8481 case ISD::SETEQ: SSECC = 0; break;
8483 case ISD::SETGT: Swap = true; // Fallthrough
8485 case ISD::SETOLT: SSECC = 1; break;
8487 case ISD::SETGE: Swap = true; // Fallthrough
8489 case ISD::SETOLE: SSECC = 2; break;
8490 case ISD::SETUO: SSECC = 3; break;
8492 case ISD::SETNE: SSECC = 4; break;
8493 case ISD::SETULE: Swap = true;
8494 case ISD::SETUGE: SSECC = 5; break;
8495 case ISD::SETULT: Swap = true;
8496 case ISD::SETUGT: SSECC = 6; break;
8497 case ISD::SETO: SSECC = 7; break;
8500 std::swap(Op0, Op1);
8502 // In the two special cases we can't handle, emit two comparisons.
8504 if (SetCCOpcode == ISD::SETUEQ) {
8506 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8507 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8508 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8510 else if (SetCCOpcode == ISD::SETONE) {
8512 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8513 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8514 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8516 llvm_unreachable("Illegal FP comparison");
8518 // Handle all other FP comparisons here.
8519 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8522 // Break 256-bit integer vector compare into smaller ones.
8523 if (!isFP && VT.getSizeInBits() == 256)
8524 return Lower256IntVSETCC(Op, DAG);
8526 // We are handling one of the integer comparisons here. Since SSE only has
8527 // GT and EQ comparisons for integer, swapping operands and multiple
8528 // operations may be required for some comparisons.
8529 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8530 bool Swap = false, Invert = false, FlipSigns = false;
8532 switch (VT.getSimpleVT().SimpleTy) {
8534 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8535 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8536 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8537 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8540 switch (SetCCOpcode) {
8542 case ISD::SETNE: Invert = true;
8543 case ISD::SETEQ: Opc = EQOpc; break;
8544 case ISD::SETLT: Swap = true;
8545 case ISD::SETGT: Opc = GTOpc; break;
8546 case ISD::SETGE: Swap = true;
8547 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8548 case ISD::SETULT: Swap = true;
8549 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8550 case ISD::SETUGE: Swap = true;
8551 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8554 std::swap(Op0, Op1);
8556 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8557 // bits of the inputs before performing those operations.
8559 EVT EltVT = VT.getVectorElementType();
8560 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8562 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8563 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8565 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8566 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8569 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8571 // If the logical-not of the result is required, perform that now.
8573 Result = DAG.getNOT(dl, Result, VT);
8578 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8579 static bool isX86LogicalCmp(SDValue Op) {
8580 unsigned Opc = Op.getNode()->getOpcode();
8581 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8583 if (Op.getResNo() == 1 &&
8584 (Opc == X86ISD::ADD ||
8585 Opc == X86ISD::SUB ||
8586 Opc == X86ISD::ADC ||
8587 Opc == X86ISD::SBB ||
8588 Opc == X86ISD::SMUL ||
8589 Opc == X86ISD::UMUL ||
8590 Opc == X86ISD::INC ||
8591 Opc == X86ISD::DEC ||
8592 Opc == X86ISD::OR ||
8593 Opc == X86ISD::XOR ||
8594 Opc == X86ISD::AND))
8597 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8603 static bool isZero(SDValue V) {
8604 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8605 return C && C->isNullValue();
8608 static bool isAllOnes(SDValue V) {
8609 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8610 return C && C->isAllOnesValue();
8613 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8614 bool addTest = true;
8615 SDValue Cond = Op.getOperand(0);
8616 SDValue Op1 = Op.getOperand(1);
8617 SDValue Op2 = Op.getOperand(2);
8618 DebugLoc DL = Op.getDebugLoc();
8621 if (Cond.getOpcode() == ISD::SETCC) {
8622 SDValue NewCond = LowerSETCC(Cond, DAG);
8623 if (NewCond.getNode())
8627 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8628 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8629 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8630 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8631 if (Cond.getOpcode() == X86ISD::SETCC &&
8632 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8633 isZero(Cond.getOperand(1).getOperand(1))) {
8634 SDValue Cmp = Cond.getOperand(1);
8636 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8638 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8639 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8640 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8642 SDValue CmpOp0 = Cmp.getOperand(0);
8643 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8644 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8646 SDValue Res = // Res = 0 or -1.
8647 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8648 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8650 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8651 Res = DAG.getNOT(DL, Res, Res.getValueType());
8653 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8654 if (N2C == 0 || !N2C->isNullValue())
8655 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8660 // Look past (and (setcc_carry (cmp ...)), 1).
8661 if (Cond.getOpcode() == ISD::AND &&
8662 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8663 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8664 if (C && C->getAPIntValue() == 1)
8665 Cond = Cond.getOperand(0);
8668 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8669 // setting operand in place of the X86ISD::SETCC.
8670 if (Cond.getOpcode() == X86ISD::SETCC ||
8671 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8672 CC = Cond.getOperand(0);
8674 SDValue Cmp = Cond.getOperand(1);
8675 unsigned Opc = Cmp.getOpcode();
8676 EVT VT = Op.getValueType();
8678 bool IllegalFPCMov = false;
8679 if (VT.isFloatingPoint() && !VT.isVector() &&
8680 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8681 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8683 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8684 Opc == X86ISD::BT) { // FIXME
8691 // Look pass the truncate.
8692 if (Cond.getOpcode() == ISD::TRUNCATE)
8693 Cond = Cond.getOperand(0);
8695 // We know the result of AND is compared against zero. Try to match
8697 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8698 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8699 if (NewSetCC.getNode()) {
8700 CC = NewSetCC.getOperand(0);
8701 Cond = NewSetCC.getOperand(1);
8708 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8709 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8712 // a < b ? -1 : 0 -> RES = ~setcc_carry
8713 // a < b ? 0 : -1 -> RES = setcc_carry
8714 // a >= b ? -1 : 0 -> RES = setcc_carry
8715 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8716 if (Cond.getOpcode() == X86ISD::CMP) {
8717 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8719 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8720 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8721 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8722 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8723 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8724 return DAG.getNOT(DL, Res, Res.getValueType());
8729 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8730 // condition is true.
8731 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8732 SDValue Ops[] = { Op2, Op1, CC, Cond };
8733 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8736 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8737 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8738 // from the AND / OR.
8739 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8740 Opc = Op.getOpcode();
8741 if (Opc != ISD::OR && Opc != ISD::AND)
8743 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8744 Op.getOperand(0).hasOneUse() &&
8745 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8746 Op.getOperand(1).hasOneUse());
8749 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8750 // 1 and that the SETCC node has a single use.
8751 static bool isXor1OfSetCC(SDValue Op) {
8752 if (Op.getOpcode() != ISD::XOR)
8754 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8755 if (N1C && N1C->getAPIntValue() == 1) {
8756 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8757 Op.getOperand(0).hasOneUse();
8762 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8763 bool addTest = true;
8764 SDValue Chain = Op.getOperand(0);
8765 SDValue Cond = Op.getOperand(1);
8766 SDValue Dest = Op.getOperand(2);
8767 DebugLoc dl = Op.getDebugLoc();
8770 if (Cond.getOpcode() == ISD::SETCC) {
8771 SDValue NewCond = LowerSETCC(Cond, DAG);
8772 if (NewCond.getNode())
8776 // FIXME: LowerXALUO doesn't handle these!!
8777 else if (Cond.getOpcode() == X86ISD::ADD ||
8778 Cond.getOpcode() == X86ISD::SUB ||
8779 Cond.getOpcode() == X86ISD::SMUL ||
8780 Cond.getOpcode() == X86ISD::UMUL)
8781 Cond = LowerXALUO(Cond, DAG);
8784 // Look pass (and (setcc_carry (cmp ...)), 1).
8785 if (Cond.getOpcode() == ISD::AND &&
8786 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8787 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8788 if (C && C->getAPIntValue() == 1)
8789 Cond = Cond.getOperand(0);
8792 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8793 // setting operand in place of the X86ISD::SETCC.
8794 if (Cond.getOpcode() == X86ISD::SETCC ||
8795 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8796 CC = Cond.getOperand(0);
8798 SDValue Cmp = Cond.getOperand(1);
8799 unsigned Opc = Cmp.getOpcode();
8800 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8801 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8805 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8809 // These can only come from an arithmetic instruction with overflow,
8810 // e.g. SADDO, UADDO.
8811 Cond = Cond.getNode()->getOperand(1);
8818 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8819 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8820 if (CondOpc == ISD::OR) {
8821 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8822 // two branches instead of an explicit OR instruction with a
8824 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8825 isX86LogicalCmp(Cmp)) {
8826 CC = Cond.getOperand(0).getOperand(0);
8827 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8828 Chain, Dest, CC, Cmp);
8829 CC = Cond.getOperand(1).getOperand(0);
8833 } else { // ISD::AND
8834 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8835 // two branches instead of an explicit AND instruction with a
8836 // separate test. However, we only do this if this block doesn't
8837 // have a fall-through edge, because this requires an explicit
8838 // jmp when the condition is false.
8839 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8840 isX86LogicalCmp(Cmp) &&
8841 Op.getNode()->hasOneUse()) {
8842 X86::CondCode CCode =
8843 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8844 CCode = X86::GetOppositeBranchCondition(CCode);
8845 CC = DAG.getConstant(CCode, MVT::i8);
8846 SDNode *User = *Op.getNode()->use_begin();
8847 // Look for an unconditional branch following this conditional branch.
8848 // We need this because we need to reverse the successors in order
8849 // to implement FCMP_OEQ.
8850 if (User->getOpcode() == ISD::BR) {
8851 SDValue FalseBB = User->getOperand(1);
8853 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8854 assert(NewBR == User);
8858 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8859 Chain, Dest, CC, Cmp);
8860 X86::CondCode CCode =
8861 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8862 CCode = X86::GetOppositeBranchCondition(CCode);
8863 CC = DAG.getConstant(CCode, MVT::i8);
8869 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8870 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8871 // It should be transformed during dag combiner except when the condition
8872 // is set by a arithmetics with overflow node.
8873 X86::CondCode CCode =
8874 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8875 CCode = X86::GetOppositeBranchCondition(CCode);
8876 CC = DAG.getConstant(CCode, MVT::i8);
8877 Cond = Cond.getOperand(0).getOperand(1);
8883 // Look pass the truncate.
8884 if (Cond.getOpcode() == ISD::TRUNCATE)
8885 Cond = Cond.getOperand(0);
8887 // We know the result of AND is compared against zero. Try to match
8889 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8890 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8891 if (NewSetCC.getNode()) {
8892 CC = NewSetCC.getOperand(0);
8893 Cond = NewSetCC.getOperand(1);
8900 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8901 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8903 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8904 Chain, Dest, CC, Cond);
8908 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8909 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8910 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8911 // that the guard pages used by the OS virtual memory manager are allocated in
8912 // correct sequence.
8914 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8915 SelectionDAG &DAG) const {
8916 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8917 EnableSegmentedStacks) &&
8918 "This should be used only on Windows targets or when segmented stacks "
8920 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8921 DebugLoc dl = Op.getDebugLoc();
8924 SDValue Chain = Op.getOperand(0);
8925 SDValue Size = Op.getOperand(1);
8926 // FIXME: Ensure alignment here
8928 bool Is64Bit = Subtarget->is64Bit();
8929 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8931 if (EnableSegmentedStacks) {
8932 MachineFunction &MF = DAG.getMachineFunction();
8933 MachineRegisterInfo &MRI = MF.getRegInfo();
8936 // The 64 bit implementation of segmented stacks needs to clobber both r10
8937 // r11. This makes it impossible to use it along with nested parameters.
8938 const Function *F = MF.getFunction();
8940 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8942 if (I->hasNestAttr())
8943 report_fatal_error("Cannot use segmented stacks with functions that "
8944 "have nested arguments.");
8947 const TargetRegisterClass *AddrRegClass =
8948 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8949 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8950 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8951 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8952 DAG.getRegister(Vreg, SPTy));
8953 SDValue Ops1[2] = { Value, Chain };
8954 return DAG.getMergeValues(Ops1, 2, dl);
8957 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8959 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8960 Flag = Chain.getValue(1);
8961 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8963 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8964 Flag = Chain.getValue(1);
8966 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8968 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8969 return DAG.getMergeValues(Ops1, 2, dl);
8973 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8974 MachineFunction &MF = DAG.getMachineFunction();
8975 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8977 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8978 DebugLoc DL = Op.getDebugLoc();
8980 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8981 // vastart just stores the address of the VarArgsFrameIndex slot into the
8982 // memory location argument.
8983 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8985 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8986 MachinePointerInfo(SV), false, false, 0);
8990 // gp_offset (0 - 6 * 8)
8991 // fp_offset (48 - 48 + 8 * 16)
8992 // overflow_arg_area (point to parameters coming in memory).
8994 SmallVector<SDValue, 8> MemOps;
8995 SDValue FIN = Op.getOperand(1);
8997 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8998 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9000 FIN, MachinePointerInfo(SV), false, false, 0);
9001 MemOps.push_back(Store);
9004 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9005 FIN, DAG.getIntPtrConstant(4));
9006 Store = DAG.getStore(Op.getOperand(0), DL,
9007 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9009 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9010 MemOps.push_back(Store);
9012 // Store ptr to overflow_arg_area
9013 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9014 FIN, DAG.getIntPtrConstant(4));
9015 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9017 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9018 MachinePointerInfo(SV, 8),
9020 MemOps.push_back(Store);
9022 // Store ptr to reg_save_area.
9023 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9024 FIN, DAG.getIntPtrConstant(8));
9025 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9027 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9028 MachinePointerInfo(SV, 16), false, false, 0);
9029 MemOps.push_back(Store);
9030 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9031 &MemOps[0], MemOps.size());
9034 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9035 assert(Subtarget->is64Bit() &&
9036 "LowerVAARG only handles 64-bit va_arg!");
9037 assert((Subtarget->isTargetLinux() ||
9038 Subtarget->isTargetDarwin()) &&
9039 "Unhandled target in LowerVAARG");
9040 assert(Op.getNode()->getNumOperands() == 4);
9041 SDValue Chain = Op.getOperand(0);
9042 SDValue SrcPtr = Op.getOperand(1);
9043 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9044 unsigned Align = Op.getConstantOperandVal(3);
9045 DebugLoc dl = Op.getDebugLoc();
9047 EVT ArgVT = Op.getNode()->getValueType(0);
9048 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9049 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9052 // Decide which area this value should be read from.
9053 // TODO: Implement the AMD64 ABI in its entirety. This simple
9054 // selection mechanism works only for the basic types.
9055 if (ArgVT == MVT::f80) {
9056 llvm_unreachable("va_arg for f80 not yet implemented");
9057 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9058 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9059 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9060 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9062 llvm_unreachable("Unhandled argument type in LowerVAARG");
9066 // Sanity Check: Make sure using fp_offset makes sense.
9067 assert(!UseSoftFloat &&
9068 !(DAG.getMachineFunction()
9069 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9070 Subtarget->hasXMM());
9073 // Insert VAARG_64 node into the DAG
9074 // VAARG_64 returns two values: Variable Argument Address, Chain
9075 SmallVector<SDValue, 11> InstOps;
9076 InstOps.push_back(Chain);
9077 InstOps.push_back(SrcPtr);
9078 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9079 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9080 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9081 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9082 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9083 VTs, &InstOps[0], InstOps.size(),
9085 MachinePointerInfo(SV),
9090 Chain = VAARG.getValue(1);
9092 // Load the next argument and return it
9093 return DAG.getLoad(ArgVT, dl,
9096 MachinePointerInfo(),
9100 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9101 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9102 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9103 SDValue Chain = Op.getOperand(0);
9104 SDValue DstPtr = Op.getOperand(1);
9105 SDValue SrcPtr = Op.getOperand(2);
9106 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9107 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9108 DebugLoc DL = Op.getDebugLoc();
9110 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9111 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9113 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9117 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9118 DebugLoc dl = Op.getDebugLoc();
9119 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9121 default: return SDValue(); // Don't custom lower most intrinsics.
9122 // Comparison intrinsics.
9123 case Intrinsic::x86_sse_comieq_ss:
9124 case Intrinsic::x86_sse_comilt_ss:
9125 case Intrinsic::x86_sse_comile_ss:
9126 case Intrinsic::x86_sse_comigt_ss:
9127 case Intrinsic::x86_sse_comige_ss:
9128 case Intrinsic::x86_sse_comineq_ss:
9129 case Intrinsic::x86_sse_ucomieq_ss:
9130 case Intrinsic::x86_sse_ucomilt_ss:
9131 case Intrinsic::x86_sse_ucomile_ss:
9132 case Intrinsic::x86_sse_ucomigt_ss:
9133 case Intrinsic::x86_sse_ucomige_ss:
9134 case Intrinsic::x86_sse_ucomineq_ss:
9135 case Intrinsic::x86_sse2_comieq_sd:
9136 case Intrinsic::x86_sse2_comilt_sd:
9137 case Intrinsic::x86_sse2_comile_sd:
9138 case Intrinsic::x86_sse2_comigt_sd:
9139 case Intrinsic::x86_sse2_comige_sd:
9140 case Intrinsic::x86_sse2_comineq_sd:
9141 case Intrinsic::x86_sse2_ucomieq_sd:
9142 case Intrinsic::x86_sse2_ucomilt_sd:
9143 case Intrinsic::x86_sse2_ucomile_sd:
9144 case Intrinsic::x86_sse2_ucomigt_sd:
9145 case Intrinsic::x86_sse2_ucomige_sd:
9146 case Intrinsic::x86_sse2_ucomineq_sd: {
9148 ISD::CondCode CC = ISD::SETCC_INVALID;
9151 case Intrinsic::x86_sse_comieq_ss:
9152 case Intrinsic::x86_sse2_comieq_sd:
9156 case Intrinsic::x86_sse_comilt_ss:
9157 case Intrinsic::x86_sse2_comilt_sd:
9161 case Intrinsic::x86_sse_comile_ss:
9162 case Intrinsic::x86_sse2_comile_sd:
9166 case Intrinsic::x86_sse_comigt_ss:
9167 case Intrinsic::x86_sse2_comigt_sd:
9171 case Intrinsic::x86_sse_comige_ss:
9172 case Intrinsic::x86_sse2_comige_sd:
9176 case Intrinsic::x86_sse_comineq_ss:
9177 case Intrinsic::x86_sse2_comineq_sd:
9181 case Intrinsic::x86_sse_ucomieq_ss:
9182 case Intrinsic::x86_sse2_ucomieq_sd:
9183 Opc = X86ISD::UCOMI;
9186 case Intrinsic::x86_sse_ucomilt_ss:
9187 case Intrinsic::x86_sse2_ucomilt_sd:
9188 Opc = X86ISD::UCOMI;
9191 case Intrinsic::x86_sse_ucomile_ss:
9192 case Intrinsic::x86_sse2_ucomile_sd:
9193 Opc = X86ISD::UCOMI;
9196 case Intrinsic::x86_sse_ucomigt_ss:
9197 case Intrinsic::x86_sse2_ucomigt_sd:
9198 Opc = X86ISD::UCOMI;
9201 case Intrinsic::x86_sse_ucomige_ss:
9202 case Intrinsic::x86_sse2_ucomige_sd:
9203 Opc = X86ISD::UCOMI;
9206 case Intrinsic::x86_sse_ucomineq_ss:
9207 case Intrinsic::x86_sse2_ucomineq_sd:
9208 Opc = X86ISD::UCOMI;
9213 SDValue LHS = Op.getOperand(1);
9214 SDValue RHS = Op.getOperand(2);
9215 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9216 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9217 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9218 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9219 DAG.getConstant(X86CC, MVT::i8), Cond);
9220 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9222 // ptest and testp intrinsics. The intrinsic these come from are designed to
9223 // return an integer value, not just an instruction so lower it to the ptest
9224 // or testp pattern and a setcc for the result.
9225 case Intrinsic::x86_sse41_ptestz:
9226 case Intrinsic::x86_sse41_ptestc:
9227 case Intrinsic::x86_sse41_ptestnzc:
9228 case Intrinsic::x86_avx_ptestz_256:
9229 case Intrinsic::x86_avx_ptestc_256:
9230 case Intrinsic::x86_avx_ptestnzc_256:
9231 case Intrinsic::x86_avx_vtestz_ps:
9232 case Intrinsic::x86_avx_vtestc_ps:
9233 case Intrinsic::x86_avx_vtestnzc_ps:
9234 case Intrinsic::x86_avx_vtestz_pd:
9235 case Intrinsic::x86_avx_vtestc_pd:
9236 case Intrinsic::x86_avx_vtestnzc_pd:
9237 case Intrinsic::x86_avx_vtestz_ps_256:
9238 case Intrinsic::x86_avx_vtestc_ps_256:
9239 case Intrinsic::x86_avx_vtestnzc_ps_256:
9240 case Intrinsic::x86_avx_vtestz_pd_256:
9241 case Intrinsic::x86_avx_vtestc_pd_256:
9242 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9243 bool IsTestPacked = false;
9246 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9247 case Intrinsic::x86_avx_vtestz_ps:
9248 case Intrinsic::x86_avx_vtestz_pd:
9249 case Intrinsic::x86_avx_vtestz_ps_256:
9250 case Intrinsic::x86_avx_vtestz_pd_256:
9251 IsTestPacked = true; // Fallthrough
9252 case Intrinsic::x86_sse41_ptestz:
9253 case Intrinsic::x86_avx_ptestz_256:
9255 X86CC = X86::COND_E;
9257 case Intrinsic::x86_avx_vtestc_ps:
9258 case Intrinsic::x86_avx_vtestc_pd:
9259 case Intrinsic::x86_avx_vtestc_ps_256:
9260 case Intrinsic::x86_avx_vtestc_pd_256:
9261 IsTestPacked = true; // Fallthrough
9262 case Intrinsic::x86_sse41_ptestc:
9263 case Intrinsic::x86_avx_ptestc_256:
9265 X86CC = X86::COND_B;
9267 case Intrinsic::x86_avx_vtestnzc_ps:
9268 case Intrinsic::x86_avx_vtestnzc_pd:
9269 case Intrinsic::x86_avx_vtestnzc_ps_256:
9270 case Intrinsic::x86_avx_vtestnzc_pd_256:
9271 IsTestPacked = true; // Fallthrough
9272 case Intrinsic::x86_sse41_ptestnzc:
9273 case Intrinsic::x86_avx_ptestnzc_256:
9275 X86CC = X86::COND_A;
9279 SDValue LHS = Op.getOperand(1);
9280 SDValue RHS = Op.getOperand(2);
9281 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9282 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9283 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9284 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9285 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9288 // Fix vector shift instructions where the last operand is a non-immediate
9290 case Intrinsic::x86_sse2_pslli_w:
9291 case Intrinsic::x86_sse2_pslli_d:
9292 case Intrinsic::x86_sse2_pslli_q:
9293 case Intrinsic::x86_sse2_psrli_w:
9294 case Intrinsic::x86_sse2_psrli_d:
9295 case Intrinsic::x86_sse2_psrli_q:
9296 case Intrinsic::x86_sse2_psrai_w:
9297 case Intrinsic::x86_sse2_psrai_d:
9298 case Intrinsic::x86_mmx_pslli_w:
9299 case Intrinsic::x86_mmx_pslli_d:
9300 case Intrinsic::x86_mmx_pslli_q:
9301 case Intrinsic::x86_mmx_psrli_w:
9302 case Intrinsic::x86_mmx_psrli_d:
9303 case Intrinsic::x86_mmx_psrli_q:
9304 case Intrinsic::x86_mmx_psrai_w:
9305 case Intrinsic::x86_mmx_psrai_d: {
9306 SDValue ShAmt = Op.getOperand(2);
9307 if (isa<ConstantSDNode>(ShAmt))
9310 unsigned NewIntNo = 0;
9311 EVT ShAmtVT = MVT::v4i32;
9313 case Intrinsic::x86_sse2_pslli_w:
9314 NewIntNo = Intrinsic::x86_sse2_psll_w;
9316 case Intrinsic::x86_sse2_pslli_d:
9317 NewIntNo = Intrinsic::x86_sse2_psll_d;
9319 case Intrinsic::x86_sse2_pslli_q:
9320 NewIntNo = Intrinsic::x86_sse2_psll_q;
9322 case Intrinsic::x86_sse2_psrli_w:
9323 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9325 case Intrinsic::x86_sse2_psrli_d:
9326 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9328 case Intrinsic::x86_sse2_psrli_q:
9329 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9331 case Intrinsic::x86_sse2_psrai_w:
9332 NewIntNo = Intrinsic::x86_sse2_psra_w;
9334 case Intrinsic::x86_sse2_psrai_d:
9335 NewIntNo = Intrinsic::x86_sse2_psra_d;
9338 ShAmtVT = MVT::v2i32;
9340 case Intrinsic::x86_mmx_pslli_w:
9341 NewIntNo = Intrinsic::x86_mmx_psll_w;
9343 case Intrinsic::x86_mmx_pslli_d:
9344 NewIntNo = Intrinsic::x86_mmx_psll_d;
9346 case Intrinsic::x86_mmx_pslli_q:
9347 NewIntNo = Intrinsic::x86_mmx_psll_q;
9349 case Intrinsic::x86_mmx_psrli_w:
9350 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9352 case Intrinsic::x86_mmx_psrli_d:
9353 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9355 case Intrinsic::x86_mmx_psrli_q:
9356 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9358 case Intrinsic::x86_mmx_psrai_w:
9359 NewIntNo = Intrinsic::x86_mmx_psra_w;
9361 case Intrinsic::x86_mmx_psrai_d:
9362 NewIntNo = Intrinsic::x86_mmx_psra_d;
9364 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9370 // The vector shift intrinsics with scalars uses 32b shift amounts but
9371 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9375 ShOps[1] = DAG.getConstant(0, MVT::i32);
9376 if (ShAmtVT == MVT::v4i32) {
9377 ShOps[2] = DAG.getUNDEF(MVT::i32);
9378 ShOps[3] = DAG.getUNDEF(MVT::i32);
9379 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9381 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9382 // FIXME this must be lowered to get rid of the invalid type.
9385 EVT VT = Op.getValueType();
9386 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9387 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9388 DAG.getConstant(NewIntNo, MVT::i32),
9389 Op.getOperand(1), ShAmt);
9394 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9395 SelectionDAG &DAG) const {
9396 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9397 MFI->setReturnAddressIsTaken(true);
9399 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9400 DebugLoc dl = Op.getDebugLoc();
9403 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9405 DAG.getConstant(TD->getPointerSize(),
9406 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9407 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9408 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9410 MachinePointerInfo(), false, false, 0);
9413 // Just load the return address.
9414 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9415 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9416 RetAddrFI, MachinePointerInfo(), false, false, 0);
9419 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9420 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9421 MFI->setFrameAddressIsTaken(true);
9423 EVT VT = Op.getValueType();
9424 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9425 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9426 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9427 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9429 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9430 MachinePointerInfo(),
9435 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9436 SelectionDAG &DAG) const {
9437 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9440 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9441 MachineFunction &MF = DAG.getMachineFunction();
9442 SDValue Chain = Op.getOperand(0);
9443 SDValue Offset = Op.getOperand(1);
9444 SDValue Handler = Op.getOperand(2);
9445 DebugLoc dl = Op.getDebugLoc();
9447 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9448 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9450 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9452 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9453 DAG.getIntPtrConstant(TD->getPointerSize()));
9454 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9455 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9457 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9458 MF.getRegInfo().addLiveOut(StoreAddrReg);
9460 return DAG.getNode(X86ISD::EH_RETURN, dl,
9462 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9465 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9466 SelectionDAG &DAG) const {
9467 return Op.getOperand(0);
9470 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9471 SelectionDAG &DAG) const {
9472 SDValue Root = Op.getOperand(0);
9473 SDValue Trmp = Op.getOperand(1); // trampoline
9474 SDValue FPtr = Op.getOperand(2); // nested function
9475 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9476 DebugLoc dl = Op.getDebugLoc();
9478 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9480 if (Subtarget->is64Bit()) {
9481 SDValue OutChains[6];
9483 // Large code-model.
9484 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9485 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9487 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9488 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9490 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9492 // Load the pointer to the nested function into R11.
9493 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9494 SDValue Addr = Trmp;
9495 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9496 Addr, MachinePointerInfo(TrmpAddr),
9499 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9500 DAG.getConstant(2, MVT::i64));
9501 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9502 MachinePointerInfo(TrmpAddr, 2),
9505 // Load the 'nest' parameter value into R10.
9506 // R10 is specified in X86CallingConv.td
9507 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9508 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9509 DAG.getConstant(10, MVT::i64));
9510 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9511 Addr, MachinePointerInfo(TrmpAddr, 10),
9514 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9515 DAG.getConstant(12, MVT::i64));
9516 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9517 MachinePointerInfo(TrmpAddr, 12),
9520 // Jump to the nested function.
9521 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9522 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9523 DAG.getConstant(20, MVT::i64));
9524 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9525 Addr, MachinePointerInfo(TrmpAddr, 20),
9528 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9529 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9530 DAG.getConstant(22, MVT::i64));
9531 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9532 MachinePointerInfo(TrmpAddr, 22),
9535 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9537 const Function *Func =
9538 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9539 CallingConv::ID CC = Func->getCallingConv();
9544 llvm_unreachable("Unsupported calling convention");
9545 case CallingConv::C:
9546 case CallingConv::X86_StdCall: {
9547 // Pass 'nest' parameter in ECX.
9548 // Must be kept in sync with X86CallingConv.td
9551 // Check that ECX wasn't needed by an 'inreg' parameter.
9552 FunctionType *FTy = Func->getFunctionType();
9553 const AttrListPtr &Attrs = Func->getAttributes();
9555 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9556 unsigned InRegCount = 0;
9559 for (FunctionType::param_iterator I = FTy->param_begin(),
9560 E = FTy->param_end(); I != E; ++I, ++Idx)
9561 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9562 // FIXME: should only count parameters that are lowered to integers.
9563 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9565 if (InRegCount > 2) {
9566 report_fatal_error("Nest register in use - reduce number of inreg"
9572 case CallingConv::X86_FastCall:
9573 case CallingConv::X86_ThisCall:
9574 case CallingConv::Fast:
9575 // Pass 'nest' parameter in EAX.
9576 // Must be kept in sync with X86CallingConv.td
9581 SDValue OutChains[4];
9584 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9585 DAG.getConstant(10, MVT::i32));
9586 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9588 // This is storing the opcode for MOV32ri.
9589 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9590 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9591 OutChains[0] = DAG.getStore(Root, dl,
9592 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9593 Trmp, MachinePointerInfo(TrmpAddr),
9596 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9597 DAG.getConstant(1, MVT::i32));
9598 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9599 MachinePointerInfo(TrmpAddr, 1),
9602 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9603 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9604 DAG.getConstant(5, MVT::i32));
9605 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9606 MachinePointerInfo(TrmpAddr, 5),
9609 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9610 DAG.getConstant(6, MVT::i32));
9611 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9612 MachinePointerInfo(TrmpAddr, 6),
9615 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9619 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9620 SelectionDAG &DAG) const {
9622 The rounding mode is in bits 11:10 of FPSR, and has the following
9629 FLT_ROUNDS, on the other hand, expects the following:
9636 To perform the conversion, we do:
9637 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9640 MachineFunction &MF = DAG.getMachineFunction();
9641 const TargetMachine &TM = MF.getTarget();
9642 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9643 unsigned StackAlignment = TFI.getStackAlignment();
9644 EVT VT = Op.getValueType();
9645 DebugLoc DL = Op.getDebugLoc();
9647 // Save FP Control Word to stack slot
9648 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9649 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9652 MachineMemOperand *MMO =
9653 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9654 MachineMemOperand::MOStore, 2, 2);
9656 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9657 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9658 DAG.getVTList(MVT::Other),
9659 Ops, 2, MVT::i16, MMO);
9661 // Load FP Control Word from stack slot
9662 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9663 MachinePointerInfo(), false, false, 0);
9665 // Transform as necessary
9667 DAG.getNode(ISD::SRL, DL, MVT::i16,
9668 DAG.getNode(ISD::AND, DL, MVT::i16,
9669 CWD, DAG.getConstant(0x800, MVT::i16)),
9670 DAG.getConstant(11, MVT::i8));
9672 DAG.getNode(ISD::SRL, DL, MVT::i16,
9673 DAG.getNode(ISD::AND, DL, MVT::i16,
9674 CWD, DAG.getConstant(0x400, MVT::i16)),
9675 DAG.getConstant(9, MVT::i8));
9678 DAG.getNode(ISD::AND, DL, MVT::i16,
9679 DAG.getNode(ISD::ADD, DL, MVT::i16,
9680 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9681 DAG.getConstant(1, MVT::i16)),
9682 DAG.getConstant(3, MVT::i16));
9685 return DAG.getNode((VT.getSizeInBits() < 16 ?
9686 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9689 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9690 EVT VT = Op.getValueType();
9692 unsigned NumBits = VT.getSizeInBits();
9693 DebugLoc dl = Op.getDebugLoc();
9695 Op = Op.getOperand(0);
9696 if (VT == MVT::i8) {
9697 // Zero extend to i32 since there is not an i8 bsr.
9699 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9702 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9703 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9704 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9706 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9709 DAG.getConstant(NumBits+NumBits-1, OpVT),
9710 DAG.getConstant(X86::COND_E, MVT::i8),
9713 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9715 // Finally xor with NumBits-1.
9716 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9719 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9723 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9724 EVT VT = Op.getValueType();
9726 unsigned NumBits = VT.getSizeInBits();
9727 DebugLoc dl = Op.getDebugLoc();
9729 Op = Op.getOperand(0);
9730 if (VT == MVT::i8) {
9732 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9735 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9736 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9737 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9739 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9742 DAG.getConstant(NumBits, OpVT),
9743 DAG.getConstant(X86::COND_E, MVT::i8),
9746 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9749 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9753 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9754 // ones, and then concatenate the result back.
9755 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9756 EVT VT = Op.getValueType();
9758 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9759 "Unsupported value type for operation");
9761 int NumElems = VT.getVectorNumElements();
9762 DebugLoc dl = Op.getDebugLoc();
9763 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9764 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9766 // Extract the LHS vectors
9767 SDValue LHS = Op.getOperand(0);
9768 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9769 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9771 // Extract the RHS vectors
9772 SDValue RHS = Op.getOperand(1);
9773 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9774 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9776 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9777 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9779 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9780 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9781 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9784 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9785 assert(Op.getValueType().getSizeInBits() == 256 &&
9786 Op.getValueType().isInteger() &&
9787 "Only handle AVX 256-bit vector integer operation");
9788 return Lower256IntArith(Op, DAG);
9791 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9792 assert(Op.getValueType().getSizeInBits() == 256 &&
9793 Op.getValueType().isInteger() &&
9794 "Only handle AVX 256-bit vector integer operation");
9795 return Lower256IntArith(Op, DAG);
9798 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9799 EVT VT = Op.getValueType();
9801 // Decompose 256-bit ops into smaller 128-bit ops.
9802 if (VT.getSizeInBits() == 256)
9803 return Lower256IntArith(Op, DAG);
9805 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9806 DebugLoc dl = Op.getDebugLoc();
9808 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9809 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9810 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9811 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9812 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9814 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9815 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9816 // return AloBlo + AloBhi + AhiBlo;
9818 SDValue A = Op.getOperand(0);
9819 SDValue B = Op.getOperand(1);
9821 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9822 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9823 A, DAG.getConstant(32, MVT::i32));
9824 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9825 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9826 B, DAG.getConstant(32, MVT::i32));
9827 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9828 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9830 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9831 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9833 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9834 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9836 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9837 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9838 AloBhi, DAG.getConstant(32, MVT::i32));
9839 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9840 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9841 AhiBlo, DAG.getConstant(32, MVT::i32));
9842 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9843 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9847 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9849 EVT VT = Op.getValueType();
9850 DebugLoc dl = Op.getDebugLoc();
9851 SDValue R = Op.getOperand(0);
9852 SDValue Amt = Op.getOperand(1);
9853 LLVMContext *Context = DAG.getContext();
9855 if (!Subtarget->hasXMMInt())
9858 // Decompose 256-bit shifts into smaller 128-bit shifts.
9859 if (VT.getSizeInBits() == 256) {
9860 int NumElems = VT.getVectorNumElements();
9861 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9862 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9864 // Extract the two vectors
9865 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
9866 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
9869 // Recreate the shift amount vectors
9871 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
9872 // Constant shift amount
9873 SmallVector<SDValue, 4> Amt1Csts;
9874 SmallVector<SDValue, 4> Amt2Csts;
9875 for (int i = 0; i < NumElems/2; ++i)
9876 Amt1Csts.push_back(Amt->getOperand(i));
9877 for (int i = NumElems/2; i < NumElems; ++i)
9878 Amt2Csts.push_back(Amt->getOperand(i));
9880 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9881 &Amt1Csts[0], NumElems/2);
9882 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9883 &Amt2Csts[0], NumElems/2);
9885 // Variable shift amount
9886 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
9887 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
9891 // Issue new vector shifts for the smaller types
9892 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
9893 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
9895 // Concatenate the result back
9896 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
9899 // Optimize shl/srl/sra with constant shift amount.
9900 if (isSplatVector(Amt.getNode())) {
9901 SDValue SclrAmt = Amt->getOperand(0);
9902 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9903 uint64_t ShiftAmt = C->getZExtValue();
9905 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
9906 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9907 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9908 R, DAG.getConstant(ShiftAmt, MVT::i32));
9910 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
9911 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9912 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9913 R, DAG.getConstant(ShiftAmt, MVT::i32));
9915 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
9916 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9917 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9918 R, DAG.getConstant(ShiftAmt, MVT::i32));
9920 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
9921 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9922 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9923 R, DAG.getConstant(ShiftAmt, MVT::i32));
9925 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
9926 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9927 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9928 R, DAG.getConstant(ShiftAmt, MVT::i32));
9930 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
9931 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9932 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9933 R, DAG.getConstant(ShiftAmt, MVT::i32));
9935 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
9936 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9937 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9938 R, DAG.getConstant(ShiftAmt, MVT::i32));
9940 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9941 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9942 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9943 R, DAG.getConstant(ShiftAmt, MVT::i32));
9947 // Lower SHL with variable shift amount.
9948 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
9949 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9950 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9951 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
9953 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
9955 std::vector<Constant*> CV(4, CI);
9956 Constant *C = ConstantVector::get(CV);
9957 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9958 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9959 MachinePointerInfo::getConstantPool(),
9962 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
9963 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
9964 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
9965 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
9967 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
9969 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9970 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9971 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
9973 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
9974 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
9976 std::vector<Constant*> CVM1(16, CM1);
9977 std::vector<Constant*> CVM2(16, CM2);
9978 Constant *C = ConstantVector::get(CVM1);
9979 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9980 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9981 MachinePointerInfo::getConstantPool(),
9984 // r = pblendv(r, psllw(r & (char16)15, 4), a);
9985 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9986 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9987 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9988 DAG.getConstant(4, MVT::i32));
9989 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
9991 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9993 C = ConstantVector::get(CVM2);
9994 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9995 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9996 MachinePointerInfo::getConstantPool(),
9999 // r = pblendv(r, psllw(r & (char16)63, 2), a);
10000 M = DAG.getNode(ISD::AND, dl, VT, R, M);
10001 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10002 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10003 DAG.getConstant(2, MVT::i32));
10004 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
10006 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10008 // return pblendv(r, r+r, a);
10009 R = DAG.getNode(ISD::VSELECT, dl, VT, Op,
10010 R, DAG.getNode(ISD::ADD, dl, VT, R, R));
10016 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10017 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10018 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10019 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10020 // has only one use.
10021 SDNode *N = Op.getNode();
10022 SDValue LHS = N->getOperand(0);
10023 SDValue RHS = N->getOperand(1);
10024 unsigned BaseOp = 0;
10026 DebugLoc DL = Op.getDebugLoc();
10027 switch (Op.getOpcode()) {
10028 default: llvm_unreachable("Unknown ovf instruction!");
10030 // A subtract of one will be selected as a INC. Note that INC doesn't
10031 // set CF, so we can't do this for UADDO.
10032 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10034 BaseOp = X86ISD::INC;
10035 Cond = X86::COND_O;
10038 BaseOp = X86ISD::ADD;
10039 Cond = X86::COND_O;
10042 BaseOp = X86ISD::ADD;
10043 Cond = X86::COND_B;
10046 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10047 // set CF, so we can't do this for USUBO.
10048 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10050 BaseOp = X86ISD::DEC;
10051 Cond = X86::COND_O;
10054 BaseOp = X86ISD::SUB;
10055 Cond = X86::COND_O;
10058 BaseOp = X86ISD::SUB;
10059 Cond = X86::COND_B;
10062 BaseOp = X86ISD::SMUL;
10063 Cond = X86::COND_O;
10065 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10066 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10068 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10071 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10072 DAG.getConstant(X86::COND_O, MVT::i32),
10073 SDValue(Sum.getNode(), 2));
10075 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10079 // Also sets EFLAGS.
10080 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10081 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10084 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10085 DAG.getConstant(Cond, MVT::i32),
10086 SDValue(Sum.getNode(), 1));
10088 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10091 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
10092 DebugLoc dl = Op.getDebugLoc();
10093 SDNode* Node = Op.getNode();
10094 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
10095 EVT VT = Node->getValueType(0);
10096 if (Subtarget->hasXMMInt() && VT.isVector()) {
10097 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10098 ExtraVT.getScalarType().getSizeInBits();
10099 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10101 unsigned SHLIntrinsicsID = 0;
10102 unsigned SRAIntrinsicsID = 0;
10103 switch (VT.getSimpleVT().SimpleTy) {
10107 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q;
10108 SRAIntrinsicsID = 0;
10112 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10113 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10117 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10118 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10123 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10124 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10125 Node->getOperand(0), ShAmt);
10127 // In case of 1 bit sext, no need to shr
10128 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
10130 if (SRAIntrinsicsID) {
10131 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10132 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10142 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10143 DebugLoc dl = Op.getDebugLoc();
10145 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10146 // There isn't any reason to disable it if the target processor supports it.
10147 if (!Subtarget->hasXMMInt() && !Subtarget->is64Bit()) {
10148 SDValue Chain = Op.getOperand(0);
10149 SDValue Zero = DAG.getConstant(0, MVT::i32);
10151 DAG.getRegister(X86::ESP, MVT::i32), // Base
10152 DAG.getTargetConstant(1, MVT::i8), // Scale
10153 DAG.getRegister(0, MVT::i32), // Index
10154 DAG.getTargetConstant(0, MVT::i32), // Disp
10155 DAG.getRegister(0, MVT::i32), // Segment.
10160 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10161 array_lengthof(Ops));
10162 return SDValue(Res, 0);
10165 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10167 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10169 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10170 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10171 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10172 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10174 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10175 if (!Op1 && !Op2 && !Op3 && Op4)
10176 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10178 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10179 if (Op1 && !Op2 && !Op3 && !Op4)
10180 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10182 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10184 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10187 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10188 SelectionDAG &DAG) const {
10189 DebugLoc dl = Op.getDebugLoc();
10190 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10191 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10192 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10193 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10195 // The only fence that needs an instruction is a sequentially-consistent
10196 // cross-thread fence.
10197 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10198 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10199 // no-sse2). There isn't any reason to disable it if the target processor
10201 if (Subtarget->hasXMMInt() || Subtarget->is64Bit())
10202 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10204 SDValue Chain = Op.getOperand(0);
10205 SDValue Zero = DAG.getConstant(0, MVT::i32);
10207 DAG.getRegister(X86::ESP, MVT::i32), // Base
10208 DAG.getTargetConstant(1, MVT::i8), // Scale
10209 DAG.getRegister(0, MVT::i32), // Index
10210 DAG.getTargetConstant(0, MVT::i32), // Disp
10211 DAG.getRegister(0, MVT::i32), // Segment.
10216 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10217 array_lengthof(Ops));
10218 return SDValue(Res, 0);
10221 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10222 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10226 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10227 EVT T = Op.getValueType();
10228 DebugLoc DL = Op.getDebugLoc();
10231 switch(T.getSimpleVT().SimpleTy) {
10233 assert(false && "Invalid value type!");
10234 case MVT::i8: Reg = X86::AL; size = 1; break;
10235 case MVT::i16: Reg = X86::AX; size = 2; break;
10236 case MVT::i32: Reg = X86::EAX; size = 4; break;
10238 assert(Subtarget->is64Bit() && "Node not type legal!");
10239 Reg = X86::RAX; size = 8;
10242 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10243 Op.getOperand(2), SDValue());
10244 SDValue Ops[] = { cpIn.getValue(0),
10247 DAG.getTargetConstant(size, MVT::i8),
10248 cpIn.getValue(1) };
10249 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10250 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10251 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10254 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10258 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10259 SelectionDAG &DAG) const {
10260 assert(Subtarget->is64Bit() && "Result not type legalized?");
10261 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10262 SDValue TheChain = Op.getOperand(0);
10263 DebugLoc dl = Op.getDebugLoc();
10264 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10265 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10266 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10268 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10269 DAG.getConstant(32, MVT::i8));
10271 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10274 return DAG.getMergeValues(Ops, 2, dl);
10277 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10278 SelectionDAG &DAG) const {
10279 EVT SrcVT = Op.getOperand(0).getValueType();
10280 EVT DstVT = Op.getValueType();
10281 assert(Subtarget->is64Bit() && !Subtarget->hasXMMInt() &&
10282 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10283 assert((DstVT == MVT::i64 ||
10284 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10285 "Unexpected custom BITCAST");
10286 // i64 <=> MMX conversions are Legal.
10287 if (SrcVT==MVT::i64 && DstVT.isVector())
10289 if (DstVT==MVT::i64 && SrcVT.isVector())
10291 // MMX <=> MMX conversions are Legal.
10292 if (SrcVT.isVector() && DstVT.isVector())
10294 // All other conversions need to be expanded.
10298 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10299 SDNode *Node = Op.getNode();
10300 DebugLoc dl = Node->getDebugLoc();
10301 EVT T = Node->getValueType(0);
10302 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10303 DAG.getConstant(0, T), Node->getOperand(2));
10304 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10305 cast<AtomicSDNode>(Node)->getMemoryVT(),
10306 Node->getOperand(0),
10307 Node->getOperand(1), negOp,
10308 cast<AtomicSDNode>(Node)->getSrcValue(),
10309 cast<AtomicSDNode>(Node)->getAlignment(),
10310 cast<AtomicSDNode>(Node)->getOrdering(),
10311 cast<AtomicSDNode>(Node)->getSynchScope());
10314 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10315 SDNode *Node = Op.getNode();
10316 DebugLoc dl = Node->getDebugLoc();
10317 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10319 // Convert seq_cst store -> xchg
10320 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10321 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10322 // (The only way to get a 16-byte store is cmpxchg16b)
10323 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10324 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10325 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10326 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10327 cast<AtomicSDNode>(Node)->getMemoryVT(),
10328 Node->getOperand(0),
10329 Node->getOperand(1), Node->getOperand(2),
10330 cast<AtomicSDNode>(Node)->getMemOperand(),
10331 cast<AtomicSDNode>(Node)->getOrdering(),
10332 cast<AtomicSDNode>(Node)->getSynchScope());
10333 return Swap.getValue(1);
10335 // Other atomic stores have a simple pattern.
10339 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10340 EVT VT = Op.getNode()->getValueType(0);
10342 // Let legalize expand this if it isn't a legal type yet.
10343 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10346 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10349 bool ExtraOp = false;
10350 switch (Op.getOpcode()) {
10351 default: assert(0 && "Invalid code");
10352 case ISD::ADDC: Opc = X86ISD::ADD; break;
10353 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10354 case ISD::SUBC: Opc = X86ISD::SUB; break;
10355 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10359 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10361 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10362 Op.getOperand(1), Op.getOperand(2));
10365 /// LowerOperation - Provide custom lowering hooks for some operations.
10367 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10368 switch (Op.getOpcode()) {
10369 default: llvm_unreachable("Should not custom lower this!");
10370 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10371 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10372 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10373 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10374 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10375 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10376 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10377 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10378 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10379 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10380 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10381 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10382 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10383 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10384 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10385 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10386 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10387 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10388 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10389 case ISD::SHL_PARTS:
10390 case ISD::SRA_PARTS:
10391 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10392 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10393 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10394 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10395 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10396 case ISD::FABS: return LowerFABS(Op, DAG);
10397 case ISD::FNEG: return LowerFNEG(Op, DAG);
10398 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10399 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10400 case ISD::SETCC: return LowerSETCC(Op, DAG);
10401 case ISD::SELECT: return LowerSELECT(Op, DAG);
10402 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10403 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10404 case ISD::VASTART: return LowerVASTART(Op, DAG);
10405 case ISD::VAARG: return LowerVAARG(Op, DAG);
10406 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10407 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10408 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10409 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10410 case ISD::FRAME_TO_ARGS_OFFSET:
10411 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10412 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10413 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10414 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10415 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10416 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10417 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10418 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10419 case ISD::MUL: return LowerMUL(Op, DAG);
10422 case ISD::SHL: return LowerShift(Op, DAG);
10428 case ISD::UMULO: return LowerXALUO(Op, DAG);
10429 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10430 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10434 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10435 case ISD::ADD: return LowerADD(Op, DAG);
10436 case ISD::SUB: return LowerSUB(Op, DAG);
10440 static void ReplaceATOMIC_LOAD(SDNode *Node,
10441 SmallVectorImpl<SDValue> &Results,
10442 SelectionDAG &DAG) {
10443 DebugLoc dl = Node->getDebugLoc();
10444 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10446 // Convert wide load -> cmpxchg8b/cmpxchg16b
10447 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10448 // (The only way to get a 16-byte load is cmpxchg16b)
10449 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10450 SDValue Zero = DAG.getConstant(0, VT);
10451 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10452 Node->getOperand(0),
10453 Node->getOperand(1), Zero, Zero,
10454 cast<AtomicSDNode>(Node)->getMemOperand(),
10455 cast<AtomicSDNode>(Node)->getOrdering(),
10456 cast<AtomicSDNode>(Node)->getSynchScope());
10457 Results.push_back(Swap.getValue(0));
10458 Results.push_back(Swap.getValue(1));
10461 void X86TargetLowering::
10462 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10463 SelectionDAG &DAG, unsigned NewOp) const {
10464 EVT T = Node->getValueType(0);
10465 DebugLoc dl = Node->getDebugLoc();
10466 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
10468 SDValue Chain = Node->getOperand(0);
10469 SDValue In1 = Node->getOperand(1);
10470 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10471 Node->getOperand(2), DAG.getIntPtrConstant(0));
10472 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10473 Node->getOperand(2), DAG.getIntPtrConstant(1));
10474 SDValue Ops[] = { Chain, In1, In2L, In2H };
10475 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10477 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10478 cast<MemSDNode>(Node)->getMemOperand());
10479 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10480 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10481 Results.push_back(Result.getValue(2));
10484 /// ReplaceNodeResults - Replace a node with an illegal result type
10485 /// with a new node built out of custom code.
10486 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10487 SmallVectorImpl<SDValue>&Results,
10488 SelectionDAG &DAG) const {
10489 DebugLoc dl = N->getDebugLoc();
10490 switch (N->getOpcode()) {
10492 assert(false && "Do not know how to custom type legalize this operation!");
10494 case ISD::SIGN_EXTEND_INREG:
10499 // We don't want to expand or promote these.
10501 case ISD::FP_TO_SINT: {
10502 std::pair<SDValue,SDValue> Vals =
10503 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10504 SDValue FIST = Vals.first, StackSlot = Vals.second;
10505 if (FIST.getNode() != 0) {
10506 EVT VT = N->getValueType(0);
10507 // Return a load from the stack slot.
10508 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10509 MachinePointerInfo(), false, false, 0));
10513 case ISD::READCYCLECOUNTER: {
10514 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10515 SDValue TheChain = N->getOperand(0);
10516 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10517 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10519 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10521 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10522 SDValue Ops[] = { eax, edx };
10523 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10524 Results.push_back(edx.getValue(1));
10527 case ISD::ATOMIC_CMP_SWAP: {
10528 EVT T = N->getValueType(0);
10529 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10530 bool Regs64bit = T == MVT::i128;
10531 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10532 SDValue cpInL, cpInH;
10533 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10534 DAG.getConstant(0, HalfT));
10535 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10536 DAG.getConstant(1, HalfT));
10537 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10538 Regs64bit ? X86::RAX : X86::EAX,
10540 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10541 Regs64bit ? X86::RDX : X86::EDX,
10542 cpInH, cpInL.getValue(1));
10543 SDValue swapInL, swapInH;
10544 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10545 DAG.getConstant(0, HalfT));
10546 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10547 DAG.getConstant(1, HalfT));
10548 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10549 Regs64bit ? X86::RBX : X86::EBX,
10550 swapInL, cpInH.getValue(1));
10551 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10552 Regs64bit ? X86::RCX : X86::ECX,
10553 swapInH, swapInL.getValue(1));
10554 SDValue Ops[] = { swapInH.getValue(0),
10556 swapInH.getValue(1) };
10557 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10558 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10559 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10560 X86ISD::LCMPXCHG8_DAG;
10561 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10563 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10564 Regs64bit ? X86::RAX : X86::EAX,
10565 HalfT, Result.getValue(1));
10566 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10567 Regs64bit ? X86::RDX : X86::EDX,
10568 HalfT, cpOutL.getValue(2));
10569 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10570 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10571 Results.push_back(cpOutH.getValue(1));
10574 case ISD::ATOMIC_LOAD_ADD:
10575 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10577 case ISD::ATOMIC_LOAD_AND:
10578 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10580 case ISD::ATOMIC_LOAD_NAND:
10581 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10583 case ISD::ATOMIC_LOAD_OR:
10584 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10586 case ISD::ATOMIC_LOAD_SUB:
10587 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10589 case ISD::ATOMIC_LOAD_XOR:
10590 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10592 case ISD::ATOMIC_SWAP:
10593 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10595 case ISD::ATOMIC_LOAD:
10596 ReplaceATOMIC_LOAD(N, Results, DAG);
10600 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10602 default: return NULL;
10603 case X86ISD::BSF: return "X86ISD::BSF";
10604 case X86ISD::BSR: return "X86ISD::BSR";
10605 case X86ISD::SHLD: return "X86ISD::SHLD";
10606 case X86ISD::SHRD: return "X86ISD::SHRD";
10607 case X86ISD::FAND: return "X86ISD::FAND";
10608 case X86ISD::FOR: return "X86ISD::FOR";
10609 case X86ISD::FXOR: return "X86ISD::FXOR";
10610 case X86ISD::FSRL: return "X86ISD::FSRL";
10611 case X86ISD::FILD: return "X86ISD::FILD";
10612 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10613 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10614 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10615 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10616 case X86ISD::FLD: return "X86ISD::FLD";
10617 case X86ISD::FST: return "X86ISD::FST";
10618 case X86ISD::CALL: return "X86ISD::CALL";
10619 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10620 case X86ISD::BT: return "X86ISD::BT";
10621 case X86ISD::CMP: return "X86ISD::CMP";
10622 case X86ISD::COMI: return "X86ISD::COMI";
10623 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10624 case X86ISD::SETCC: return "X86ISD::SETCC";
10625 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10626 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10627 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10628 case X86ISD::CMOV: return "X86ISD::CMOV";
10629 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10630 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10631 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10632 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10633 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10634 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10635 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10636 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10637 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10638 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10639 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10640 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10641 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10642 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10643 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
10644 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
10645 case X86ISD::PSIGND: return "X86ISD::PSIGND";
10646 case X86ISD::FMAX: return "X86ISD::FMAX";
10647 case X86ISD::FMIN: return "X86ISD::FMIN";
10648 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10649 case X86ISD::FRCP: return "X86ISD::FRCP";
10650 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10651 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10652 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10653 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10654 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10655 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10656 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10657 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10658 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10659 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10660 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10661 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10662 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10663 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10664 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10665 case X86ISD::VSHL: return "X86ISD::VSHL";
10666 case X86ISD::VSRL: return "X86ISD::VSRL";
10667 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10668 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10669 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10670 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10671 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10672 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10673 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10674 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10675 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10676 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10677 case X86ISD::ADD: return "X86ISD::ADD";
10678 case X86ISD::SUB: return "X86ISD::SUB";
10679 case X86ISD::ADC: return "X86ISD::ADC";
10680 case X86ISD::SBB: return "X86ISD::SBB";
10681 case X86ISD::SMUL: return "X86ISD::SMUL";
10682 case X86ISD::UMUL: return "X86ISD::UMUL";
10683 case X86ISD::INC: return "X86ISD::INC";
10684 case X86ISD::DEC: return "X86ISD::DEC";
10685 case X86ISD::OR: return "X86ISD::OR";
10686 case X86ISD::XOR: return "X86ISD::XOR";
10687 case X86ISD::AND: return "X86ISD::AND";
10688 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10689 case X86ISD::PTEST: return "X86ISD::PTEST";
10690 case X86ISD::TESTP: return "X86ISD::TESTP";
10691 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10692 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10693 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10694 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10695 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10696 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10697 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10698 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10699 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10700 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10701 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10702 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
10703 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10704 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10705 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10706 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10707 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10708 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10709 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10710 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10711 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10712 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
10713 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
10714 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
10715 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
10716 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
10717 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
10718 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
10719 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
10720 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
10721 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
10722 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
10723 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
10724 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
10725 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10726 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
10727 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
10728 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
10729 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
10730 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
10731 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10732 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10733 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10734 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10735 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
10739 // isLegalAddressingMode - Return true if the addressing mode represented
10740 // by AM is legal for this target, for a load/store of the specified type.
10741 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10743 // X86 supports extremely general addressing modes.
10744 CodeModel::Model M = getTargetMachine().getCodeModel();
10745 Reloc::Model R = getTargetMachine().getRelocationModel();
10747 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10748 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10753 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10755 // If a reference to this global requires an extra load, we can't fold it.
10756 if (isGlobalStubReference(GVFlags))
10759 // If BaseGV requires a register for the PIC base, we cannot also have a
10760 // BaseReg specified.
10761 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
10764 // If lower 4G is not available, then we must use rip-relative addressing.
10765 if ((M != CodeModel::Small || R != Reloc::Static) &&
10766 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
10770 switch (AM.Scale) {
10776 // These scales always work.
10781 // These scales are formed with basereg+scalereg. Only accept if there is
10786 default: // Other stuff never works.
10794 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
10795 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10797 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
10798 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
10799 if (NumBits1 <= NumBits2)
10804 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
10805 if (!VT1.isInteger() || !VT2.isInteger())
10807 unsigned NumBits1 = VT1.getSizeInBits();
10808 unsigned NumBits2 = VT2.getSizeInBits();
10809 if (NumBits1 <= NumBits2)
10814 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
10815 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10816 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
10819 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
10820 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10821 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
10824 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
10825 // i16 instructions are longer (0x66 prefix) and potentially slower.
10826 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
10829 /// isShuffleMaskLegal - Targets can use this to indicate that they only
10830 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
10831 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
10832 /// are assumed to be legal.
10834 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
10836 // Very little shuffling can be done for 64-bit vectors right now.
10837 if (VT.getSizeInBits() == 64)
10838 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX());
10840 // FIXME: pshufb, blends, shifts.
10841 return (VT.getVectorNumElements() == 2 ||
10842 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
10843 isMOVLMask(M, VT) ||
10844 isSHUFPMask(M, VT) ||
10845 isPSHUFDMask(M, VT) ||
10846 isPSHUFHWMask(M, VT) ||
10847 isPSHUFLWMask(M, VT) ||
10848 isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX()) ||
10849 isUNPCKLMask(M, VT) ||
10850 isUNPCKHMask(M, VT) ||
10851 isUNPCKL_v_undef_Mask(M, VT) ||
10852 isUNPCKH_v_undef_Mask(M, VT));
10856 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
10858 unsigned NumElts = VT.getVectorNumElements();
10859 // FIXME: This collection of masks seems suspect.
10862 if (NumElts == 4 && VT.getSizeInBits() == 128) {
10863 return (isMOVLMask(Mask, VT) ||
10864 isCommutedMOVLMask(Mask, VT, true) ||
10865 isSHUFPMask(Mask, VT) ||
10866 isCommutedSHUFPMask(Mask, VT));
10871 //===----------------------------------------------------------------------===//
10872 // X86 Scheduler Hooks
10873 //===----------------------------------------------------------------------===//
10875 // private utility function
10876 MachineBasicBlock *
10877 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
10878 MachineBasicBlock *MBB,
10885 TargetRegisterClass *RC,
10886 bool invSrc) const {
10887 // For the atomic bitwise operator, we generate
10890 // ld t1 = [bitinstr.addr]
10891 // op t2 = t1, [bitinstr.val]
10893 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10895 // fallthrough -->nextMBB
10896 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10897 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10898 MachineFunction::iterator MBBIter = MBB;
10901 /// First build the CFG
10902 MachineFunction *F = MBB->getParent();
10903 MachineBasicBlock *thisMBB = MBB;
10904 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10905 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10906 F->insert(MBBIter, newMBB);
10907 F->insert(MBBIter, nextMBB);
10909 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10910 nextMBB->splice(nextMBB->begin(), thisMBB,
10911 llvm::next(MachineBasicBlock::iterator(bInstr)),
10913 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10915 // Update thisMBB to fall through to newMBB
10916 thisMBB->addSuccessor(newMBB);
10918 // newMBB jumps to itself and fall through to nextMBB
10919 newMBB->addSuccessor(nextMBB);
10920 newMBB->addSuccessor(newMBB);
10922 // Insert instructions into newMBB based on incoming instruction
10923 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10924 "unexpected number of operands");
10925 DebugLoc dl = bInstr->getDebugLoc();
10926 MachineOperand& destOper = bInstr->getOperand(0);
10927 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10928 int numArgs = bInstr->getNumOperands() - 1;
10929 for (int i=0; i < numArgs; ++i)
10930 argOpers[i] = &bInstr->getOperand(i+1);
10932 // x86 address has 4 operands: base, index, scale, and displacement
10933 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10934 int valArgIndx = lastAddrIndx + 1;
10936 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10937 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
10938 for (int i=0; i <= lastAddrIndx; ++i)
10939 (*MIB).addOperand(*argOpers[i]);
10941 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
10943 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
10948 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10949 assert((argOpers[valArgIndx]->isReg() ||
10950 argOpers[valArgIndx]->isImm()) &&
10951 "invalid operand");
10952 if (argOpers[valArgIndx]->isReg())
10953 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
10955 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
10957 (*MIB).addOperand(*argOpers[valArgIndx]);
10959 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
10962 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
10963 for (int i=0; i <= lastAddrIndx; ++i)
10964 (*MIB).addOperand(*argOpers[i]);
10966 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10967 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10968 bInstr->memoperands_end());
10970 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10971 MIB.addReg(EAXreg);
10974 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10976 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10980 // private utility function: 64 bit atomics on 32 bit host.
10981 MachineBasicBlock *
10982 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
10983 MachineBasicBlock *MBB,
10988 bool invSrc) const {
10989 // For the atomic bitwise operator, we generate
10990 // thisMBB (instructions are in pairs, except cmpxchg8b)
10991 // ld t1,t2 = [bitinstr.addr]
10993 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
10994 // op t5, t6 <- out1, out2, [bitinstr.val]
10995 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
10996 // mov ECX, EBX <- t5, t6
10997 // mov EAX, EDX <- t1, t2
10998 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
10999 // mov t3, t4 <- EAX, EDX
11001 // result in out1, out2
11002 // fallthrough -->nextMBB
11004 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11005 const unsigned LoadOpc = X86::MOV32rm;
11006 const unsigned NotOpc = X86::NOT32r;
11007 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11008 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11009 MachineFunction::iterator MBBIter = MBB;
11012 /// First build the CFG
11013 MachineFunction *F = MBB->getParent();
11014 MachineBasicBlock *thisMBB = MBB;
11015 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11016 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11017 F->insert(MBBIter, newMBB);
11018 F->insert(MBBIter, nextMBB);
11020 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11021 nextMBB->splice(nextMBB->begin(), thisMBB,
11022 llvm::next(MachineBasicBlock::iterator(bInstr)),
11024 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11026 // Update thisMBB to fall through to newMBB
11027 thisMBB->addSuccessor(newMBB);
11029 // newMBB jumps to itself and fall through to nextMBB
11030 newMBB->addSuccessor(nextMBB);
11031 newMBB->addSuccessor(newMBB);
11033 DebugLoc dl = bInstr->getDebugLoc();
11034 // Insert instructions into newMBB based on incoming instruction
11035 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11036 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11037 "unexpected number of operands");
11038 MachineOperand& dest1Oper = bInstr->getOperand(0);
11039 MachineOperand& dest2Oper = bInstr->getOperand(1);
11040 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11041 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11042 argOpers[i] = &bInstr->getOperand(i+2);
11044 // We use some of the operands multiple times, so conservatively just
11045 // clear any kill flags that might be present.
11046 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11047 argOpers[i]->setIsKill(false);
11050 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11051 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11053 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11054 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11055 for (int i=0; i <= lastAddrIndx; ++i)
11056 (*MIB).addOperand(*argOpers[i]);
11057 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11058 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11059 // add 4 to displacement.
11060 for (int i=0; i <= lastAddrIndx-2; ++i)
11061 (*MIB).addOperand(*argOpers[i]);
11062 MachineOperand newOp3 = *(argOpers[3]);
11063 if (newOp3.isImm())
11064 newOp3.setImm(newOp3.getImm()+4);
11066 newOp3.setOffset(newOp3.getOffset()+4);
11067 (*MIB).addOperand(newOp3);
11068 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11070 // t3/4 are defined later, at the bottom of the loop
11071 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11072 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11073 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11074 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11075 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11076 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11078 // The subsequent operations should be using the destination registers of
11079 //the PHI instructions.
11081 t1 = F->getRegInfo().createVirtualRegister(RC);
11082 t2 = F->getRegInfo().createVirtualRegister(RC);
11083 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11084 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11086 t1 = dest1Oper.getReg();
11087 t2 = dest2Oper.getReg();
11090 int valArgIndx = lastAddrIndx + 1;
11091 assert((argOpers[valArgIndx]->isReg() ||
11092 argOpers[valArgIndx]->isImm()) &&
11093 "invalid operand");
11094 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11095 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11096 if (argOpers[valArgIndx]->isReg())
11097 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11099 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11100 if (regOpcL != X86::MOV32rr)
11102 (*MIB).addOperand(*argOpers[valArgIndx]);
11103 assert(argOpers[valArgIndx + 1]->isReg() ==
11104 argOpers[valArgIndx]->isReg());
11105 assert(argOpers[valArgIndx + 1]->isImm() ==
11106 argOpers[valArgIndx]->isImm());
11107 if (argOpers[valArgIndx + 1]->isReg())
11108 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11110 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11111 if (regOpcH != X86::MOV32rr)
11113 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11115 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11117 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11120 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11122 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11125 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11126 for (int i=0; i <= lastAddrIndx; ++i)
11127 (*MIB).addOperand(*argOpers[i]);
11129 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11130 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11131 bInstr->memoperands_end());
11133 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11134 MIB.addReg(X86::EAX);
11135 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11136 MIB.addReg(X86::EDX);
11139 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11141 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11145 // private utility function
11146 MachineBasicBlock *
11147 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11148 MachineBasicBlock *MBB,
11149 unsigned cmovOpc) const {
11150 // For the atomic min/max operator, we generate
11153 // ld t1 = [min/max.addr]
11154 // mov t2 = [min/max.val]
11156 // cmov[cond] t2 = t1
11158 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11160 // fallthrough -->nextMBB
11162 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11163 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11164 MachineFunction::iterator MBBIter = MBB;
11167 /// First build the CFG
11168 MachineFunction *F = MBB->getParent();
11169 MachineBasicBlock *thisMBB = MBB;
11170 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11171 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11172 F->insert(MBBIter, newMBB);
11173 F->insert(MBBIter, nextMBB);
11175 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11176 nextMBB->splice(nextMBB->begin(), thisMBB,
11177 llvm::next(MachineBasicBlock::iterator(mInstr)),
11179 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11181 // Update thisMBB to fall through to newMBB
11182 thisMBB->addSuccessor(newMBB);
11184 // newMBB jumps to newMBB and fall through to nextMBB
11185 newMBB->addSuccessor(nextMBB);
11186 newMBB->addSuccessor(newMBB);
11188 DebugLoc dl = mInstr->getDebugLoc();
11189 // Insert instructions into newMBB based on incoming instruction
11190 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11191 "unexpected number of operands");
11192 MachineOperand& destOper = mInstr->getOperand(0);
11193 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11194 int numArgs = mInstr->getNumOperands() - 1;
11195 for (int i=0; i < numArgs; ++i)
11196 argOpers[i] = &mInstr->getOperand(i+1);
11198 // x86 address has 4 operands: base, index, scale, and displacement
11199 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11200 int valArgIndx = lastAddrIndx + 1;
11202 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11203 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11204 for (int i=0; i <= lastAddrIndx; ++i)
11205 (*MIB).addOperand(*argOpers[i]);
11207 // We only support register and immediate values
11208 assert((argOpers[valArgIndx]->isReg() ||
11209 argOpers[valArgIndx]->isImm()) &&
11210 "invalid operand");
11212 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11213 if (argOpers[valArgIndx]->isReg())
11214 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11216 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11217 (*MIB).addOperand(*argOpers[valArgIndx]);
11219 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11222 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11227 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11228 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11232 // Cmp and exchange if none has modified the memory location
11233 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11234 for (int i=0; i <= lastAddrIndx; ++i)
11235 (*MIB).addOperand(*argOpers[i]);
11237 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11238 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11239 mInstr->memoperands_end());
11241 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11242 MIB.addReg(X86::EAX);
11245 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11247 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11251 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11252 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11253 // in the .td file.
11254 MachineBasicBlock *
11255 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11256 unsigned numArgs, bool memArg) const {
11257 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
11258 "Target must have SSE4.2 or AVX features enabled");
11260 DebugLoc dl = MI->getDebugLoc();
11261 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11263 if (!Subtarget->hasAVX()) {
11265 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11267 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11270 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11272 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11275 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11276 for (unsigned i = 0; i < numArgs; ++i) {
11277 MachineOperand &Op = MI->getOperand(i+1);
11278 if (!(Op.isReg() && Op.isImplicit()))
11279 MIB.addOperand(Op);
11281 BuildMI(*BB, MI, dl,
11282 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11283 MI->getOperand(0).getReg())
11284 .addReg(X86::XMM0);
11286 MI->eraseFromParent();
11290 MachineBasicBlock *
11291 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11292 DebugLoc dl = MI->getDebugLoc();
11293 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11295 // Address into RAX/EAX, other two args into ECX, EDX.
11296 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11297 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11298 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11299 for (int i = 0; i < X86::AddrNumOperands; ++i)
11300 MIB.addOperand(MI->getOperand(i));
11302 unsigned ValOps = X86::AddrNumOperands;
11303 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11304 .addReg(MI->getOperand(ValOps).getReg());
11305 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11306 .addReg(MI->getOperand(ValOps+1).getReg());
11308 // The instruction doesn't actually take any operands though.
11309 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11311 MI->eraseFromParent(); // The pseudo is gone now.
11315 MachineBasicBlock *
11316 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11317 DebugLoc dl = MI->getDebugLoc();
11318 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11320 // First arg in ECX, the second in EAX.
11321 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11322 .addReg(MI->getOperand(0).getReg());
11323 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11324 .addReg(MI->getOperand(1).getReg());
11326 // The instruction doesn't actually take any operands though.
11327 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11329 MI->eraseFromParent(); // The pseudo is gone now.
11333 MachineBasicBlock *
11334 X86TargetLowering::EmitVAARG64WithCustomInserter(
11336 MachineBasicBlock *MBB) const {
11337 // Emit va_arg instruction on X86-64.
11339 // Operands to this pseudo-instruction:
11340 // 0 ) Output : destination address (reg)
11341 // 1-5) Input : va_list address (addr, i64mem)
11342 // 6 ) ArgSize : Size (in bytes) of vararg type
11343 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11344 // 8 ) Align : Alignment of type
11345 // 9 ) EFLAGS (implicit-def)
11347 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11348 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11350 unsigned DestReg = MI->getOperand(0).getReg();
11351 MachineOperand &Base = MI->getOperand(1);
11352 MachineOperand &Scale = MI->getOperand(2);
11353 MachineOperand &Index = MI->getOperand(3);
11354 MachineOperand &Disp = MI->getOperand(4);
11355 MachineOperand &Segment = MI->getOperand(5);
11356 unsigned ArgSize = MI->getOperand(6).getImm();
11357 unsigned ArgMode = MI->getOperand(7).getImm();
11358 unsigned Align = MI->getOperand(8).getImm();
11360 // Memory Reference
11361 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11362 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11363 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11365 // Machine Information
11366 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11367 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11368 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11369 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11370 DebugLoc DL = MI->getDebugLoc();
11372 // struct va_list {
11375 // i64 overflow_area (address)
11376 // i64 reg_save_area (address)
11378 // sizeof(va_list) = 24
11379 // alignment(va_list) = 8
11381 unsigned TotalNumIntRegs = 6;
11382 unsigned TotalNumXMMRegs = 8;
11383 bool UseGPOffset = (ArgMode == 1);
11384 bool UseFPOffset = (ArgMode == 2);
11385 unsigned MaxOffset = TotalNumIntRegs * 8 +
11386 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11388 /* Align ArgSize to a multiple of 8 */
11389 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11390 bool NeedsAlign = (Align > 8);
11392 MachineBasicBlock *thisMBB = MBB;
11393 MachineBasicBlock *overflowMBB;
11394 MachineBasicBlock *offsetMBB;
11395 MachineBasicBlock *endMBB;
11397 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11398 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11399 unsigned OffsetReg = 0;
11401 if (!UseGPOffset && !UseFPOffset) {
11402 // If we only pull from the overflow region, we don't create a branch.
11403 // We don't need to alter control flow.
11404 OffsetDestReg = 0; // unused
11405 OverflowDestReg = DestReg;
11408 overflowMBB = thisMBB;
11411 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11412 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11413 // If not, pull from overflow_area. (branch to overflowMBB)
11418 // offsetMBB overflowMBB
11423 // Registers for the PHI in endMBB
11424 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11425 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11427 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11428 MachineFunction *MF = MBB->getParent();
11429 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11430 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11431 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11433 MachineFunction::iterator MBBIter = MBB;
11436 // Insert the new basic blocks
11437 MF->insert(MBBIter, offsetMBB);
11438 MF->insert(MBBIter, overflowMBB);
11439 MF->insert(MBBIter, endMBB);
11441 // Transfer the remainder of MBB and its successor edges to endMBB.
11442 endMBB->splice(endMBB->begin(), thisMBB,
11443 llvm::next(MachineBasicBlock::iterator(MI)),
11445 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11447 // Make offsetMBB and overflowMBB successors of thisMBB
11448 thisMBB->addSuccessor(offsetMBB);
11449 thisMBB->addSuccessor(overflowMBB);
11451 // endMBB is a successor of both offsetMBB and overflowMBB
11452 offsetMBB->addSuccessor(endMBB);
11453 overflowMBB->addSuccessor(endMBB);
11455 // Load the offset value into a register
11456 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11457 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11461 .addDisp(Disp, UseFPOffset ? 4 : 0)
11462 .addOperand(Segment)
11463 .setMemRefs(MMOBegin, MMOEnd);
11465 // Check if there is enough room left to pull this argument.
11466 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11468 .addImm(MaxOffset + 8 - ArgSizeA8);
11470 // Branch to "overflowMBB" if offset >= max
11471 // Fall through to "offsetMBB" otherwise
11472 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11473 .addMBB(overflowMBB);
11476 // In offsetMBB, emit code to use the reg_save_area.
11478 assert(OffsetReg != 0);
11480 // Read the reg_save_area address.
11481 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11482 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11487 .addOperand(Segment)
11488 .setMemRefs(MMOBegin, MMOEnd);
11490 // Zero-extend the offset
11491 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11492 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11495 .addImm(X86::sub_32bit);
11497 // Add the offset to the reg_save_area to get the final address.
11498 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11499 .addReg(OffsetReg64)
11500 .addReg(RegSaveReg);
11502 // Compute the offset for the next argument
11503 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11504 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11506 .addImm(UseFPOffset ? 16 : 8);
11508 // Store it back into the va_list.
11509 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11513 .addDisp(Disp, UseFPOffset ? 4 : 0)
11514 .addOperand(Segment)
11515 .addReg(NextOffsetReg)
11516 .setMemRefs(MMOBegin, MMOEnd);
11519 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11524 // Emit code to use overflow area
11527 // Load the overflow_area address into a register.
11528 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11529 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11534 .addOperand(Segment)
11535 .setMemRefs(MMOBegin, MMOEnd);
11537 // If we need to align it, do so. Otherwise, just copy the address
11538 // to OverflowDestReg.
11540 // Align the overflow address
11541 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11542 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11544 // aligned_addr = (addr + (align-1)) & ~(align-1)
11545 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11546 .addReg(OverflowAddrReg)
11549 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11551 .addImm(~(uint64_t)(Align-1));
11553 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11554 .addReg(OverflowAddrReg);
11557 // Compute the next overflow address after this argument.
11558 // (the overflow address should be kept 8-byte aligned)
11559 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11560 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11561 .addReg(OverflowDestReg)
11562 .addImm(ArgSizeA8);
11564 // Store the new overflow address.
11565 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11570 .addOperand(Segment)
11571 .addReg(NextAddrReg)
11572 .setMemRefs(MMOBegin, MMOEnd);
11574 // If we branched, emit the PHI to the front of endMBB.
11576 BuildMI(*endMBB, endMBB->begin(), DL,
11577 TII->get(X86::PHI), DestReg)
11578 .addReg(OffsetDestReg).addMBB(offsetMBB)
11579 .addReg(OverflowDestReg).addMBB(overflowMBB);
11582 // Erase the pseudo instruction
11583 MI->eraseFromParent();
11588 MachineBasicBlock *
11589 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11591 MachineBasicBlock *MBB) const {
11592 // Emit code to save XMM registers to the stack. The ABI says that the
11593 // number of registers to save is given in %al, so it's theoretically
11594 // possible to do an indirect jump trick to avoid saving all of them,
11595 // however this code takes a simpler approach and just executes all
11596 // of the stores if %al is non-zero. It's less code, and it's probably
11597 // easier on the hardware branch predictor, and stores aren't all that
11598 // expensive anyway.
11600 // Create the new basic blocks. One block contains all the XMM stores,
11601 // and one block is the final destination regardless of whether any
11602 // stores were performed.
11603 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11604 MachineFunction *F = MBB->getParent();
11605 MachineFunction::iterator MBBIter = MBB;
11607 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11608 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11609 F->insert(MBBIter, XMMSaveMBB);
11610 F->insert(MBBIter, EndMBB);
11612 // Transfer the remainder of MBB and its successor edges to EndMBB.
11613 EndMBB->splice(EndMBB->begin(), MBB,
11614 llvm::next(MachineBasicBlock::iterator(MI)),
11616 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11618 // The original block will now fall through to the XMM save block.
11619 MBB->addSuccessor(XMMSaveMBB);
11620 // The XMMSaveMBB will fall through to the end block.
11621 XMMSaveMBB->addSuccessor(EndMBB);
11623 // Now add the instructions.
11624 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11625 DebugLoc DL = MI->getDebugLoc();
11627 unsigned CountReg = MI->getOperand(0).getReg();
11628 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11629 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11631 if (!Subtarget->isTargetWin64()) {
11632 // If %al is 0, branch around the XMM save block.
11633 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11634 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11635 MBB->addSuccessor(EndMBB);
11638 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11639 // In the XMM save block, save all the XMM argument registers.
11640 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11641 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11642 MachineMemOperand *MMO =
11643 F->getMachineMemOperand(
11644 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11645 MachineMemOperand::MOStore,
11646 /*Size=*/16, /*Align=*/16);
11647 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11648 .addFrameIndex(RegSaveFrameIndex)
11649 .addImm(/*Scale=*/1)
11650 .addReg(/*IndexReg=*/0)
11651 .addImm(/*Disp=*/Offset)
11652 .addReg(/*Segment=*/0)
11653 .addReg(MI->getOperand(i).getReg())
11654 .addMemOperand(MMO);
11657 MI->eraseFromParent(); // The pseudo instruction is gone now.
11662 MachineBasicBlock *
11663 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11664 MachineBasicBlock *BB) const {
11665 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11666 DebugLoc DL = MI->getDebugLoc();
11668 // To "insert" a SELECT_CC instruction, we actually have to insert the
11669 // diamond control-flow pattern. The incoming instruction knows the
11670 // destination vreg to set, the condition code register to branch on, the
11671 // true/false values to select between, and a branch opcode to use.
11672 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11673 MachineFunction::iterator It = BB;
11679 // cmpTY ccX, r1, r2
11681 // fallthrough --> copy0MBB
11682 MachineBasicBlock *thisMBB = BB;
11683 MachineFunction *F = BB->getParent();
11684 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11685 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11686 F->insert(It, copy0MBB);
11687 F->insert(It, sinkMBB);
11689 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11690 // live into the sink and copy blocks.
11691 if (!MI->killsRegister(X86::EFLAGS)) {
11692 copy0MBB->addLiveIn(X86::EFLAGS);
11693 sinkMBB->addLiveIn(X86::EFLAGS);
11696 // Transfer the remainder of BB and its successor edges to sinkMBB.
11697 sinkMBB->splice(sinkMBB->begin(), BB,
11698 llvm::next(MachineBasicBlock::iterator(MI)),
11700 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11702 // Add the true and fallthrough blocks as its successors.
11703 BB->addSuccessor(copy0MBB);
11704 BB->addSuccessor(sinkMBB);
11706 // Create the conditional branch instruction.
11708 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11709 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11712 // %FalseValue = ...
11713 // # fallthrough to sinkMBB
11714 copy0MBB->addSuccessor(sinkMBB);
11717 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11719 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11720 TII->get(X86::PHI), MI->getOperand(0).getReg())
11721 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11722 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11724 MI->eraseFromParent(); // The pseudo instruction is gone now.
11728 MachineBasicBlock *
11729 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
11730 bool Is64Bit) const {
11731 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11732 DebugLoc DL = MI->getDebugLoc();
11733 MachineFunction *MF = BB->getParent();
11734 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11736 assert(EnableSegmentedStacks);
11738 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
11739 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
11742 // ... [Till the alloca]
11743 // If stacklet is not large enough, jump to mallocMBB
11746 // Allocate by subtracting from RSP
11747 // Jump to continueMBB
11750 // Allocate by call to runtime
11754 // [rest of original BB]
11757 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11758 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11759 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11761 MachineRegisterInfo &MRI = MF->getRegInfo();
11762 const TargetRegisterClass *AddrRegClass =
11763 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
11765 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
11766 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
11767 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
11768 sizeVReg = MI->getOperand(1).getReg(),
11769 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
11771 MachineFunction::iterator MBBIter = BB;
11774 MF->insert(MBBIter, bumpMBB);
11775 MF->insert(MBBIter, mallocMBB);
11776 MF->insert(MBBIter, continueMBB);
11778 continueMBB->splice(continueMBB->begin(), BB, llvm::next
11779 (MachineBasicBlock::iterator(MI)), BB->end());
11780 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
11782 // Add code to the main basic block to check if the stack limit has been hit,
11783 // and if so, jump to mallocMBB otherwise to bumpMBB.
11784 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
11785 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), tmpSPVReg)
11786 .addReg(tmpSPVReg).addReg(sizeVReg);
11787 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
11788 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg)
11789 .addReg(tmpSPVReg);
11790 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
11792 // bumpMBB simply decreases the stack pointer, since we know the current
11793 // stacklet has enough space.
11794 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
11795 .addReg(tmpSPVReg);
11796 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
11797 .addReg(tmpSPVReg);
11798 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
11800 // Calls into a routine in libgcc to allocate more space from the heap.
11802 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
11804 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
11805 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
11807 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
11809 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
11810 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
11811 .addExternalSymbol("__morestack_allocate_stack_space");
11815 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
11818 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
11819 .addReg(Is64Bit ? X86::RAX : X86::EAX);
11820 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
11822 // Set up the CFG correctly.
11823 BB->addSuccessor(bumpMBB);
11824 BB->addSuccessor(mallocMBB);
11825 mallocMBB->addSuccessor(continueMBB);
11826 bumpMBB->addSuccessor(continueMBB);
11828 // Take care of the PHI nodes.
11829 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
11830 MI->getOperand(0).getReg())
11831 .addReg(mallocPtrVReg).addMBB(mallocMBB)
11832 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
11834 // Delete the original pseudo instruction.
11835 MI->eraseFromParent();
11838 return continueMBB;
11841 MachineBasicBlock *
11842 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
11843 MachineBasicBlock *BB) const {
11844 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11845 DebugLoc DL = MI->getDebugLoc();
11847 assert(!Subtarget->isTargetEnvMacho());
11849 // The lowering is pretty easy: we're just emitting the call to _alloca. The
11850 // non-trivial part is impdef of ESP.
11852 if (Subtarget->isTargetWin64()) {
11853 if (Subtarget->isTargetCygMing()) {
11854 // ___chkstk(Mingw64):
11855 // Clobbers R10, R11, RAX and EFLAGS.
11857 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11858 .addExternalSymbol("___chkstk")
11859 .addReg(X86::RAX, RegState::Implicit)
11860 .addReg(X86::RSP, RegState::Implicit)
11861 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
11862 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
11863 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11865 // __chkstk(MSVCRT): does not update stack pointer.
11866 // Clobbers R10, R11 and EFLAGS.
11867 // FIXME: RAX(allocated size) might be reused and not killed.
11868 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11869 .addExternalSymbol("__chkstk")
11870 .addReg(X86::RAX, RegState::Implicit)
11871 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11872 // RAX has the offset to subtracted from RSP.
11873 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
11878 const char *StackProbeSymbol =
11879 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
11881 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
11882 .addExternalSymbol(StackProbeSymbol)
11883 .addReg(X86::EAX, RegState::Implicit)
11884 .addReg(X86::ESP, RegState::Implicit)
11885 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
11886 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
11887 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11890 MI->eraseFromParent(); // The pseudo instruction is gone now.
11894 MachineBasicBlock *
11895 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
11896 MachineBasicBlock *BB) const {
11897 // This is pretty easy. We're taking the value that we received from
11898 // our load from the relocation, sticking it in either RDI (x86-64)
11899 // or EAX and doing an indirect call. The return value will then
11900 // be in the normal return register.
11901 const X86InstrInfo *TII
11902 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
11903 DebugLoc DL = MI->getDebugLoc();
11904 MachineFunction *F = BB->getParent();
11906 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
11907 assert(MI->getOperand(3).isGlobal() && "This should be a global");
11909 if (Subtarget->is64Bit()) {
11910 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11911 TII->get(X86::MOV64rm), X86::RDI)
11913 .addImm(0).addReg(0)
11914 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11915 MI->getOperand(3).getTargetFlags())
11917 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
11918 addDirectMem(MIB, X86::RDI);
11919 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
11920 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11921 TII->get(X86::MOV32rm), X86::EAX)
11923 .addImm(0).addReg(0)
11924 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11925 MI->getOperand(3).getTargetFlags())
11927 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11928 addDirectMem(MIB, X86::EAX);
11930 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11931 TII->get(X86::MOV32rm), X86::EAX)
11932 .addReg(TII->getGlobalBaseReg(F))
11933 .addImm(0).addReg(0)
11934 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11935 MI->getOperand(3).getTargetFlags())
11937 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11938 addDirectMem(MIB, X86::EAX);
11941 MI->eraseFromParent(); // The pseudo instruction is gone now.
11945 MachineBasicBlock *
11946 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
11947 MachineBasicBlock *BB) const {
11948 switch (MI->getOpcode()) {
11949 default: assert(0 && "Unexpected instr type to insert");
11950 case X86::TAILJMPd64:
11951 case X86::TAILJMPr64:
11952 case X86::TAILJMPm64:
11953 assert(0 && "TAILJMP64 would not be touched here.");
11954 case X86::TCRETURNdi64:
11955 case X86::TCRETURNri64:
11956 case X86::TCRETURNmi64:
11957 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
11958 // On AMD64, additional defs should be added before register allocation.
11959 if (!Subtarget->isTargetWin64()) {
11960 MI->addRegisterDefined(X86::RSI);
11961 MI->addRegisterDefined(X86::RDI);
11962 MI->addRegisterDefined(X86::XMM6);
11963 MI->addRegisterDefined(X86::XMM7);
11964 MI->addRegisterDefined(X86::XMM8);
11965 MI->addRegisterDefined(X86::XMM9);
11966 MI->addRegisterDefined(X86::XMM10);
11967 MI->addRegisterDefined(X86::XMM11);
11968 MI->addRegisterDefined(X86::XMM12);
11969 MI->addRegisterDefined(X86::XMM13);
11970 MI->addRegisterDefined(X86::XMM14);
11971 MI->addRegisterDefined(X86::XMM15);
11974 case X86::WIN_ALLOCA:
11975 return EmitLoweredWinAlloca(MI, BB);
11976 case X86::SEG_ALLOCA_32:
11977 return EmitLoweredSegAlloca(MI, BB, false);
11978 case X86::SEG_ALLOCA_64:
11979 return EmitLoweredSegAlloca(MI, BB, true);
11980 case X86::TLSCall_32:
11981 case X86::TLSCall_64:
11982 return EmitLoweredTLSCall(MI, BB);
11983 case X86::CMOV_GR8:
11984 case X86::CMOV_FR32:
11985 case X86::CMOV_FR64:
11986 case X86::CMOV_V4F32:
11987 case X86::CMOV_V2F64:
11988 case X86::CMOV_V2I64:
11989 case X86::CMOV_V8F32:
11990 case X86::CMOV_V4F64:
11991 case X86::CMOV_V4I64:
11992 case X86::CMOV_GR16:
11993 case X86::CMOV_GR32:
11994 case X86::CMOV_RFP32:
11995 case X86::CMOV_RFP64:
11996 case X86::CMOV_RFP80:
11997 return EmitLoweredSelect(MI, BB);
11999 case X86::FP32_TO_INT16_IN_MEM:
12000 case X86::FP32_TO_INT32_IN_MEM:
12001 case X86::FP32_TO_INT64_IN_MEM:
12002 case X86::FP64_TO_INT16_IN_MEM:
12003 case X86::FP64_TO_INT32_IN_MEM:
12004 case X86::FP64_TO_INT64_IN_MEM:
12005 case X86::FP80_TO_INT16_IN_MEM:
12006 case X86::FP80_TO_INT32_IN_MEM:
12007 case X86::FP80_TO_INT64_IN_MEM: {
12008 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12009 DebugLoc DL = MI->getDebugLoc();
12011 // Change the floating point control register to use "round towards zero"
12012 // mode when truncating to an integer value.
12013 MachineFunction *F = BB->getParent();
12014 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12015 addFrameReference(BuildMI(*BB, MI, DL,
12016 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12018 // Load the old value of the high byte of the control word...
12020 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12021 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12024 // Set the high part to be round to zero...
12025 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12028 // Reload the modified control word now...
12029 addFrameReference(BuildMI(*BB, MI, DL,
12030 TII->get(X86::FLDCW16m)), CWFrameIdx);
12032 // Restore the memory image of control word to original value
12033 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12036 // Get the X86 opcode to use.
12038 switch (MI->getOpcode()) {
12039 default: llvm_unreachable("illegal opcode!");
12040 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12041 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12042 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12043 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12044 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12045 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12046 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12047 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12048 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12052 MachineOperand &Op = MI->getOperand(0);
12054 AM.BaseType = X86AddressMode::RegBase;
12055 AM.Base.Reg = Op.getReg();
12057 AM.BaseType = X86AddressMode::FrameIndexBase;
12058 AM.Base.FrameIndex = Op.getIndex();
12060 Op = MI->getOperand(1);
12062 AM.Scale = Op.getImm();
12063 Op = MI->getOperand(2);
12065 AM.IndexReg = Op.getImm();
12066 Op = MI->getOperand(3);
12067 if (Op.isGlobal()) {
12068 AM.GV = Op.getGlobal();
12070 AM.Disp = Op.getImm();
12072 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12073 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12075 // Reload the original control word now.
12076 addFrameReference(BuildMI(*BB, MI, DL,
12077 TII->get(X86::FLDCW16m)), CWFrameIdx);
12079 MI->eraseFromParent(); // The pseudo instruction is gone now.
12082 // String/text processing lowering.
12083 case X86::PCMPISTRM128REG:
12084 case X86::VPCMPISTRM128REG:
12085 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12086 case X86::PCMPISTRM128MEM:
12087 case X86::VPCMPISTRM128MEM:
12088 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12089 case X86::PCMPESTRM128REG:
12090 case X86::VPCMPESTRM128REG:
12091 return EmitPCMP(MI, BB, 5, false /* in mem */);
12092 case X86::PCMPESTRM128MEM:
12093 case X86::VPCMPESTRM128MEM:
12094 return EmitPCMP(MI, BB, 5, true /* in mem */);
12096 // Thread synchronization.
12098 return EmitMonitor(MI, BB);
12100 return EmitMwait(MI, BB);
12102 // Atomic Lowering.
12103 case X86::ATOMAND32:
12104 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12105 X86::AND32ri, X86::MOV32rm,
12107 X86::NOT32r, X86::EAX,
12108 X86::GR32RegisterClass);
12109 case X86::ATOMOR32:
12110 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12111 X86::OR32ri, X86::MOV32rm,
12113 X86::NOT32r, X86::EAX,
12114 X86::GR32RegisterClass);
12115 case X86::ATOMXOR32:
12116 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12117 X86::XOR32ri, X86::MOV32rm,
12119 X86::NOT32r, X86::EAX,
12120 X86::GR32RegisterClass);
12121 case X86::ATOMNAND32:
12122 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12123 X86::AND32ri, X86::MOV32rm,
12125 X86::NOT32r, X86::EAX,
12126 X86::GR32RegisterClass, true);
12127 case X86::ATOMMIN32:
12128 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12129 case X86::ATOMMAX32:
12130 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12131 case X86::ATOMUMIN32:
12132 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12133 case X86::ATOMUMAX32:
12134 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12136 case X86::ATOMAND16:
12137 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12138 X86::AND16ri, X86::MOV16rm,
12140 X86::NOT16r, X86::AX,
12141 X86::GR16RegisterClass);
12142 case X86::ATOMOR16:
12143 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12144 X86::OR16ri, X86::MOV16rm,
12146 X86::NOT16r, X86::AX,
12147 X86::GR16RegisterClass);
12148 case X86::ATOMXOR16:
12149 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12150 X86::XOR16ri, X86::MOV16rm,
12152 X86::NOT16r, X86::AX,
12153 X86::GR16RegisterClass);
12154 case X86::ATOMNAND16:
12155 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12156 X86::AND16ri, X86::MOV16rm,
12158 X86::NOT16r, X86::AX,
12159 X86::GR16RegisterClass, true);
12160 case X86::ATOMMIN16:
12161 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12162 case X86::ATOMMAX16:
12163 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12164 case X86::ATOMUMIN16:
12165 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12166 case X86::ATOMUMAX16:
12167 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12169 case X86::ATOMAND8:
12170 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12171 X86::AND8ri, X86::MOV8rm,
12173 X86::NOT8r, X86::AL,
12174 X86::GR8RegisterClass);
12176 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12177 X86::OR8ri, X86::MOV8rm,
12179 X86::NOT8r, X86::AL,
12180 X86::GR8RegisterClass);
12181 case X86::ATOMXOR8:
12182 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12183 X86::XOR8ri, X86::MOV8rm,
12185 X86::NOT8r, X86::AL,
12186 X86::GR8RegisterClass);
12187 case X86::ATOMNAND8:
12188 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12189 X86::AND8ri, X86::MOV8rm,
12191 X86::NOT8r, X86::AL,
12192 X86::GR8RegisterClass, true);
12193 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12194 // This group is for 64-bit host.
12195 case X86::ATOMAND64:
12196 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12197 X86::AND64ri32, X86::MOV64rm,
12199 X86::NOT64r, X86::RAX,
12200 X86::GR64RegisterClass);
12201 case X86::ATOMOR64:
12202 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12203 X86::OR64ri32, X86::MOV64rm,
12205 X86::NOT64r, X86::RAX,
12206 X86::GR64RegisterClass);
12207 case X86::ATOMXOR64:
12208 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12209 X86::XOR64ri32, X86::MOV64rm,
12211 X86::NOT64r, X86::RAX,
12212 X86::GR64RegisterClass);
12213 case X86::ATOMNAND64:
12214 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12215 X86::AND64ri32, X86::MOV64rm,
12217 X86::NOT64r, X86::RAX,
12218 X86::GR64RegisterClass, true);
12219 case X86::ATOMMIN64:
12220 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12221 case X86::ATOMMAX64:
12222 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12223 case X86::ATOMUMIN64:
12224 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12225 case X86::ATOMUMAX64:
12226 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12228 // This group does 64-bit operations on a 32-bit host.
12229 case X86::ATOMAND6432:
12230 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12231 X86::AND32rr, X86::AND32rr,
12232 X86::AND32ri, X86::AND32ri,
12234 case X86::ATOMOR6432:
12235 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12236 X86::OR32rr, X86::OR32rr,
12237 X86::OR32ri, X86::OR32ri,
12239 case X86::ATOMXOR6432:
12240 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12241 X86::XOR32rr, X86::XOR32rr,
12242 X86::XOR32ri, X86::XOR32ri,
12244 case X86::ATOMNAND6432:
12245 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12246 X86::AND32rr, X86::AND32rr,
12247 X86::AND32ri, X86::AND32ri,
12249 case X86::ATOMADD6432:
12250 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12251 X86::ADD32rr, X86::ADC32rr,
12252 X86::ADD32ri, X86::ADC32ri,
12254 case X86::ATOMSUB6432:
12255 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12256 X86::SUB32rr, X86::SBB32rr,
12257 X86::SUB32ri, X86::SBB32ri,
12259 case X86::ATOMSWAP6432:
12260 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12261 X86::MOV32rr, X86::MOV32rr,
12262 X86::MOV32ri, X86::MOV32ri,
12264 case X86::VASTART_SAVE_XMM_REGS:
12265 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12267 case X86::VAARG_64:
12268 return EmitVAARG64WithCustomInserter(MI, BB);
12272 //===----------------------------------------------------------------------===//
12273 // X86 Optimization Hooks
12274 //===----------------------------------------------------------------------===//
12276 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12280 const SelectionDAG &DAG,
12281 unsigned Depth) const {
12282 unsigned Opc = Op.getOpcode();
12283 assert((Opc >= ISD::BUILTIN_OP_END ||
12284 Opc == ISD::INTRINSIC_WO_CHAIN ||
12285 Opc == ISD::INTRINSIC_W_CHAIN ||
12286 Opc == ISD::INTRINSIC_VOID) &&
12287 "Should use MaskedValueIsZero if you don't know whether Op"
12288 " is a target node!");
12290 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12304 // These nodes' second result is a boolean.
12305 if (Op.getResNo() == 0)
12308 case X86ISD::SETCC:
12309 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12310 Mask.getBitWidth() - 1);
12315 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12316 unsigned Depth) const {
12317 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12318 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12319 return Op.getValueType().getScalarType().getSizeInBits();
12325 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12326 /// node is a GlobalAddress + offset.
12327 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12328 const GlobalValue* &GA,
12329 int64_t &Offset) const {
12330 if (N->getOpcode() == X86ISD::Wrapper) {
12331 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12332 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12333 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12337 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12340 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12341 /// same as extracting the high 128-bit part of 256-bit vector and then
12342 /// inserting the result into the low part of a new 256-bit vector
12343 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12344 EVT VT = SVOp->getValueType(0);
12345 int NumElems = VT.getVectorNumElements();
12347 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12348 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12349 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12350 SVOp->getMaskElt(j) >= 0)
12356 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12357 /// same as extracting the low 128-bit part of 256-bit vector and then
12358 /// inserting the result into the high part of a new 256-bit vector
12359 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12360 EVT VT = SVOp->getValueType(0);
12361 int NumElems = VT.getVectorNumElements();
12363 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12364 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12365 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12366 SVOp->getMaskElt(j) >= 0)
12372 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12373 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12374 TargetLowering::DAGCombinerInfo &DCI) {
12375 DebugLoc dl = N->getDebugLoc();
12376 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12377 SDValue V1 = SVOp->getOperand(0);
12378 SDValue V2 = SVOp->getOperand(1);
12379 EVT VT = SVOp->getValueType(0);
12380 int NumElems = VT.getVectorNumElements();
12382 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12383 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12387 // V UNDEF BUILD_VECTOR UNDEF
12389 // CONCAT_VECTOR CONCAT_VECTOR
12392 // RESULT: V + zero extended
12394 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12395 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12396 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12399 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12402 // To match the shuffle mask, the first half of the mask should
12403 // be exactly the first vector, and all the rest a splat with the
12404 // first element of the second one.
12405 for (int i = 0; i < NumElems/2; ++i)
12406 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12407 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12410 // Emit a zeroed vector and insert the desired subvector on its
12412 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
12413 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12414 DAG.getConstant(0, MVT::i32), DAG, dl);
12415 return DCI.CombineTo(N, InsV);
12418 //===--------------------------------------------------------------------===//
12419 // Combine some shuffles into subvector extracts and inserts:
12422 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12423 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12424 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12426 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12427 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12428 return DCI.CombineTo(N, InsV);
12431 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12432 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12433 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12434 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12435 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12436 return DCI.CombineTo(N, InsV);
12442 /// PerformShuffleCombine - Performs several different shuffle combines.
12443 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12444 TargetLowering::DAGCombinerInfo &DCI,
12445 const X86Subtarget *Subtarget) {
12446 DebugLoc dl = N->getDebugLoc();
12447 EVT VT = N->getValueType(0);
12449 // Don't create instructions with illegal types after legalize types has run.
12450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12451 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12454 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12455 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12456 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12457 return PerformShuffleCombine256(N, DAG, DCI);
12459 // Only handle 128 wide vector from here on.
12460 if (VT.getSizeInBits() != 128)
12463 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12464 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12465 // consecutive, non-overlapping, and in the right order.
12466 SmallVector<SDValue, 16> Elts;
12467 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12468 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12470 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12473 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12474 /// generation and convert it from being a bunch of shuffles and extracts
12475 /// to a simple store and scalar loads to extract the elements.
12476 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12477 const TargetLowering &TLI) {
12478 SDValue InputVector = N->getOperand(0);
12480 // Only operate on vectors of 4 elements, where the alternative shuffling
12481 // gets to be more expensive.
12482 if (InputVector.getValueType() != MVT::v4i32)
12485 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12486 // single use which is a sign-extend or zero-extend, and all elements are
12488 SmallVector<SDNode *, 4> Uses;
12489 unsigned ExtractedElements = 0;
12490 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12491 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12492 if (UI.getUse().getResNo() != InputVector.getResNo())
12495 SDNode *Extract = *UI;
12496 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12499 if (Extract->getValueType(0) != MVT::i32)
12501 if (!Extract->hasOneUse())
12503 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12504 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12506 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12509 // Record which element was extracted.
12510 ExtractedElements |=
12511 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12513 Uses.push_back(Extract);
12516 // If not all the elements were used, this may not be worthwhile.
12517 if (ExtractedElements != 15)
12520 // Ok, we've now decided to do the transformation.
12521 DebugLoc dl = InputVector.getDebugLoc();
12523 // Store the value to a temporary stack slot.
12524 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12525 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12526 MachinePointerInfo(), false, false, 0);
12528 // Replace each use (extract) with a load of the appropriate element.
12529 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12530 UE = Uses.end(); UI != UE; ++UI) {
12531 SDNode *Extract = *UI;
12533 // cOMpute the element's address.
12534 SDValue Idx = Extract->getOperand(1);
12536 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12537 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12538 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12540 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12541 StackPtr, OffsetVal);
12543 // Load the scalar.
12544 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12545 ScalarAddr, MachinePointerInfo(),
12548 // Replace the exact with the load.
12549 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12552 // The replacement was made in place; don't return anything.
12556 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
12558 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12559 const X86Subtarget *Subtarget) {
12560 DebugLoc DL = N->getDebugLoc();
12561 SDValue Cond = N->getOperand(0);
12562 // Get the LHS/RHS of the select.
12563 SDValue LHS = N->getOperand(1);
12564 SDValue RHS = N->getOperand(2);
12565 EVT VT = LHS.getValueType();
12567 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12568 // instructions match the semantics of the common C idiom x<y?x:y but not
12569 // x<=y?x:y, because of how they handle negative zero (which can be
12570 // ignored in unsafe-math mode).
12571 if (Subtarget->hasXMM() &&
12572 Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
12573 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
12574 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12576 unsigned Opcode = 0;
12577 // Check for x CC y ? x : y.
12578 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12579 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12583 // Converting this to a min would handle NaNs incorrectly, and swapping
12584 // the operands would cause it to handle comparisons between positive
12585 // and negative zero incorrectly.
12586 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12587 if (!UnsafeFPMath &&
12588 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12590 std::swap(LHS, RHS);
12592 Opcode = X86ISD::FMIN;
12595 // Converting this to a min would handle comparisons between positive
12596 // and negative zero incorrectly.
12597 if (!UnsafeFPMath &&
12598 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12600 Opcode = X86ISD::FMIN;
12603 // Converting this to a min would handle both negative zeros and NaNs
12604 // incorrectly, but we can swap the operands to fix both.
12605 std::swap(LHS, RHS);
12609 Opcode = X86ISD::FMIN;
12613 // Converting this to a max would handle comparisons between positive
12614 // and negative zero incorrectly.
12615 if (!UnsafeFPMath &&
12616 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12618 Opcode = X86ISD::FMAX;
12621 // Converting this to a max would handle NaNs incorrectly, and swapping
12622 // the operands would cause it to handle comparisons between positive
12623 // and negative zero incorrectly.
12624 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12625 if (!UnsafeFPMath &&
12626 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12628 std::swap(LHS, RHS);
12630 Opcode = X86ISD::FMAX;
12633 // Converting this to a max would handle both negative zeros and NaNs
12634 // incorrectly, but we can swap the operands to fix both.
12635 std::swap(LHS, RHS);
12639 Opcode = X86ISD::FMAX;
12642 // Check for x CC y ? y : x -- a min/max with reversed arms.
12643 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12644 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12648 // Converting this to a min would handle comparisons between positive
12649 // and negative zero incorrectly, and swapping the operands would
12650 // cause it to handle NaNs incorrectly.
12651 if (!UnsafeFPMath &&
12652 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12653 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12655 std::swap(LHS, RHS);
12657 Opcode = X86ISD::FMIN;
12660 // Converting this to a min would handle NaNs incorrectly.
12661 if (!UnsafeFPMath &&
12662 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12664 Opcode = X86ISD::FMIN;
12667 // Converting this to a min would handle both negative zeros and NaNs
12668 // incorrectly, but we can swap the operands to fix both.
12669 std::swap(LHS, RHS);
12673 Opcode = X86ISD::FMIN;
12677 // Converting this to a max would handle NaNs incorrectly.
12678 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12680 Opcode = X86ISD::FMAX;
12683 // Converting this to a max would handle comparisons between positive
12684 // and negative zero incorrectly, and swapping the operands would
12685 // cause it to handle NaNs incorrectly.
12686 if (!UnsafeFPMath &&
12687 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12688 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12690 std::swap(LHS, RHS);
12692 Opcode = X86ISD::FMAX;
12695 // Converting this to a max would handle both negative zeros and NaNs
12696 // incorrectly, but we can swap the operands to fix both.
12697 std::swap(LHS, RHS);
12701 Opcode = X86ISD::FMAX;
12707 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
12710 // If this is a select between two integer constants, try to do some
12712 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
12713 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
12714 // Don't do this for crazy integer types.
12715 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
12716 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
12717 // so that TrueC (the true value) is larger than FalseC.
12718 bool NeedsCondInvert = false;
12720 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
12721 // Efficiently invertible.
12722 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
12723 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
12724 isa<ConstantSDNode>(Cond.getOperand(1))))) {
12725 NeedsCondInvert = true;
12726 std::swap(TrueC, FalseC);
12729 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
12730 if (FalseC->getAPIntValue() == 0 &&
12731 TrueC->getAPIntValue().isPowerOf2()) {
12732 if (NeedsCondInvert) // Invert the condition if needed.
12733 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12734 DAG.getConstant(1, Cond.getValueType()));
12736 // Zero extend the condition if needed.
12737 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
12739 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12740 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
12741 DAG.getConstant(ShAmt, MVT::i8));
12744 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
12745 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12746 if (NeedsCondInvert) // Invert the condition if needed.
12747 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12748 DAG.getConstant(1, Cond.getValueType()));
12750 // Zero extend the condition if needed.
12751 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12752 FalseC->getValueType(0), Cond);
12753 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12754 SDValue(FalseC, 0));
12757 // Optimize cases that will turn into an LEA instruction. This requires
12758 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12759 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12760 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12761 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12763 bool isFastMultiplier = false;
12765 switch ((unsigned char)Diff) {
12767 case 1: // result = add base, cond
12768 case 2: // result = lea base( , cond*2)
12769 case 3: // result = lea base(cond, cond*2)
12770 case 4: // result = lea base( , cond*4)
12771 case 5: // result = lea base(cond, cond*4)
12772 case 8: // result = lea base( , cond*8)
12773 case 9: // result = lea base(cond, cond*8)
12774 isFastMultiplier = true;
12779 if (isFastMultiplier) {
12780 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12781 if (NeedsCondInvert) // Invert the condition if needed.
12782 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12783 DAG.getConstant(1, Cond.getValueType()));
12785 // Zero extend the condition if needed.
12786 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12788 // Scale the condition by the difference.
12790 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12791 DAG.getConstant(Diff, Cond.getValueType()));
12793 // Add the base if non-zero.
12794 if (FalseC->getAPIntValue() != 0)
12795 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12796 SDValue(FalseC, 0));
12806 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
12807 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
12808 TargetLowering::DAGCombinerInfo &DCI) {
12809 DebugLoc DL = N->getDebugLoc();
12811 // If the flag operand isn't dead, don't touch this CMOV.
12812 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
12815 SDValue FalseOp = N->getOperand(0);
12816 SDValue TrueOp = N->getOperand(1);
12817 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
12818 SDValue Cond = N->getOperand(3);
12819 if (CC == X86::COND_E || CC == X86::COND_NE) {
12820 switch (Cond.getOpcode()) {
12824 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
12825 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
12826 return (CC == X86::COND_E) ? FalseOp : TrueOp;
12830 // If this is a select between two integer constants, try to do some
12831 // optimizations. Note that the operands are ordered the opposite of SELECT
12833 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
12834 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
12835 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
12836 // larger than FalseC (the false value).
12837 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
12838 CC = X86::GetOppositeBranchCondition(CC);
12839 std::swap(TrueC, FalseC);
12842 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
12843 // This is efficient for any integer data type (including i8/i16) and
12845 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
12846 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12847 DAG.getConstant(CC, MVT::i8), Cond);
12849 // Zero extend the condition if needed.
12850 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
12852 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12853 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
12854 DAG.getConstant(ShAmt, MVT::i8));
12855 if (N->getNumValues() == 2) // Dead flag value?
12856 return DCI.CombineTo(N, Cond, SDValue());
12860 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
12861 // for any integer data type, including i8/i16.
12862 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12863 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12864 DAG.getConstant(CC, MVT::i8), Cond);
12866 // Zero extend the condition if needed.
12867 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12868 FalseC->getValueType(0), Cond);
12869 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12870 SDValue(FalseC, 0));
12872 if (N->getNumValues() == 2) // Dead flag value?
12873 return DCI.CombineTo(N, Cond, SDValue());
12877 // Optimize cases that will turn into an LEA instruction. This requires
12878 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12879 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12880 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12881 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12883 bool isFastMultiplier = false;
12885 switch ((unsigned char)Diff) {
12887 case 1: // result = add base, cond
12888 case 2: // result = lea base( , cond*2)
12889 case 3: // result = lea base(cond, cond*2)
12890 case 4: // result = lea base( , cond*4)
12891 case 5: // result = lea base(cond, cond*4)
12892 case 8: // result = lea base( , cond*8)
12893 case 9: // result = lea base(cond, cond*8)
12894 isFastMultiplier = true;
12899 if (isFastMultiplier) {
12900 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12901 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12902 DAG.getConstant(CC, MVT::i8), Cond);
12903 // Zero extend the condition if needed.
12904 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12906 // Scale the condition by the difference.
12908 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12909 DAG.getConstant(Diff, Cond.getValueType()));
12911 // Add the base if non-zero.
12912 if (FalseC->getAPIntValue() != 0)
12913 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12914 SDValue(FalseC, 0));
12915 if (N->getNumValues() == 2) // Dead flag value?
12916 return DCI.CombineTo(N, Cond, SDValue());
12926 /// PerformMulCombine - Optimize a single multiply with constant into two
12927 /// in order to implement it with two cheaper instructions, e.g.
12928 /// LEA + SHL, LEA + LEA.
12929 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
12930 TargetLowering::DAGCombinerInfo &DCI) {
12931 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
12934 EVT VT = N->getValueType(0);
12935 if (VT != MVT::i64)
12938 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
12941 uint64_t MulAmt = C->getZExtValue();
12942 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
12945 uint64_t MulAmt1 = 0;
12946 uint64_t MulAmt2 = 0;
12947 if ((MulAmt % 9) == 0) {
12949 MulAmt2 = MulAmt / 9;
12950 } else if ((MulAmt % 5) == 0) {
12952 MulAmt2 = MulAmt / 5;
12953 } else if ((MulAmt % 3) == 0) {
12955 MulAmt2 = MulAmt / 3;
12958 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
12959 DebugLoc DL = N->getDebugLoc();
12961 if (isPowerOf2_64(MulAmt2) &&
12962 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
12963 // If second multiplifer is pow2, issue it first. We want the multiply by
12964 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
12966 std::swap(MulAmt1, MulAmt2);
12969 if (isPowerOf2_64(MulAmt1))
12970 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
12971 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
12973 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
12974 DAG.getConstant(MulAmt1, VT));
12976 if (isPowerOf2_64(MulAmt2))
12977 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
12978 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
12980 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
12981 DAG.getConstant(MulAmt2, VT));
12983 // Do not add new nodes to DAG combiner worklist.
12984 DCI.CombineTo(N, NewMul, false);
12989 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
12990 SDValue N0 = N->getOperand(0);
12991 SDValue N1 = N->getOperand(1);
12992 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
12993 EVT VT = N0.getValueType();
12995 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
12996 // since the result of setcc_c is all zero's or all ones.
12997 if (N1C && N0.getOpcode() == ISD::AND &&
12998 N0.getOperand(1).getOpcode() == ISD::Constant) {
12999 SDValue N00 = N0.getOperand(0);
13000 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13001 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13002 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13003 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13004 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13005 APInt ShAmt = N1C->getAPIntValue();
13006 Mask = Mask.shl(ShAmt);
13008 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13009 N00, DAG.getConstant(Mask, VT));
13016 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13018 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13019 const X86Subtarget *Subtarget) {
13020 EVT VT = N->getValueType(0);
13021 if (!VT.isVector() && VT.isInteger() &&
13022 N->getOpcode() == ISD::SHL)
13023 return PerformSHLCombine(N, DAG);
13025 // On X86 with SSE2 support, we can transform this to a vector shift if
13026 // all elements are shifted by the same amount. We can't do this in legalize
13027 // because the a constant vector is typically transformed to a constant pool
13028 // so we have no knowledge of the shift amount.
13029 if (!Subtarget->hasXMMInt())
13032 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
13035 SDValue ShAmtOp = N->getOperand(1);
13036 EVT EltVT = VT.getVectorElementType();
13037 DebugLoc DL = N->getDebugLoc();
13038 SDValue BaseShAmt = SDValue();
13039 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13040 unsigned NumElts = VT.getVectorNumElements();
13042 for (; i != NumElts; ++i) {
13043 SDValue Arg = ShAmtOp.getOperand(i);
13044 if (Arg.getOpcode() == ISD::UNDEF) continue;
13048 for (; i != NumElts; ++i) {
13049 SDValue Arg = ShAmtOp.getOperand(i);
13050 if (Arg.getOpcode() == ISD::UNDEF) continue;
13051 if (Arg != BaseShAmt) {
13055 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13056 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13057 SDValue InVec = ShAmtOp.getOperand(0);
13058 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13059 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13061 for (; i != NumElts; ++i) {
13062 SDValue Arg = InVec.getOperand(i);
13063 if (Arg.getOpcode() == ISD::UNDEF) continue;
13067 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13068 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13069 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13070 if (C->getZExtValue() == SplatIdx)
13071 BaseShAmt = InVec.getOperand(1);
13074 if (BaseShAmt.getNode() == 0)
13075 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13076 DAG.getIntPtrConstant(0));
13080 // The shift amount is an i32.
13081 if (EltVT.bitsGT(MVT::i32))
13082 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13083 else if (EltVT.bitsLT(MVT::i32))
13084 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13086 // The shift amount is identical so we can do a vector shift.
13087 SDValue ValOp = N->getOperand(0);
13088 switch (N->getOpcode()) {
13090 llvm_unreachable("Unknown shift opcode!");
13093 if (VT == MVT::v2i64)
13094 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13095 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
13097 if (VT == MVT::v4i32)
13098 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13099 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
13101 if (VT == MVT::v8i16)
13102 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13103 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
13107 if (VT == MVT::v4i32)
13108 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13109 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
13111 if (VT == MVT::v8i16)
13112 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13113 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
13117 if (VT == MVT::v2i64)
13118 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13119 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
13121 if (VT == MVT::v4i32)
13122 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13123 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
13125 if (VT == MVT::v8i16)
13126 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13127 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
13135 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13136 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13137 // and friends. Likewise for OR -> CMPNEQSS.
13138 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13139 TargetLowering::DAGCombinerInfo &DCI,
13140 const X86Subtarget *Subtarget) {
13143 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13144 // we're requiring SSE2 for both.
13145 if (Subtarget->hasXMMInt() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13146 SDValue N0 = N->getOperand(0);
13147 SDValue N1 = N->getOperand(1);
13148 SDValue CMP0 = N0->getOperand(1);
13149 SDValue CMP1 = N1->getOperand(1);
13150 DebugLoc DL = N->getDebugLoc();
13152 // The SETCCs should both refer to the same CMP.
13153 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13156 SDValue CMP00 = CMP0->getOperand(0);
13157 SDValue CMP01 = CMP0->getOperand(1);
13158 EVT VT = CMP00.getValueType();
13160 if (VT == MVT::f32 || VT == MVT::f64) {
13161 bool ExpectingFlags = false;
13162 // Check for any users that want flags:
13163 for (SDNode::use_iterator UI = N->use_begin(),
13165 !ExpectingFlags && UI != UE; ++UI)
13166 switch (UI->getOpcode()) {
13171 ExpectingFlags = true;
13173 case ISD::CopyToReg:
13174 case ISD::SIGN_EXTEND:
13175 case ISD::ZERO_EXTEND:
13176 case ISD::ANY_EXTEND:
13180 if (!ExpectingFlags) {
13181 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13182 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13184 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13185 X86::CondCode tmp = cc0;
13190 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13191 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13192 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13193 X86ISD::NodeType NTOperator = is64BitFP ?
13194 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13195 // FIXME: need symbolic constants for these magic numbers.
13196 // See X86ATTInstPrinter.cpp:printSSECC().
13197 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13198 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13199 DAG.getConstant(x86cc, MVT::i8));
13200 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13202 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13203 DAG.getConstant(1, MVT::i32));
13204 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13205 return OneBitOfTruth;
13213 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13214 /// so it can be folded inside ANDNP.
13215 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13216 EVT VT = N->getValueType(0);
13218 // Match direct AllOnes for 128 and 256-bit vectors
13219 if (ISD::isBuildVectorAllOnes(N))
13222 // Look through a bit convert.
13223 if (N->getOpcode() == ISD::BITCAST)
13224 N = N->getOperand(0).getNode();
13226 // Sometimes the operand may come from a insert_subvector building a 256-bit
13228 if (VT.getSizeInBits() == 256 &&
13229 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13230 SDValue V1 = N->getOperand(0);
13231 SDValue V2 = N->getOperand(1);
13233 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13234 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13235 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13236 ISD::isBuildVectorAllOnes(V2.getNode()))
13243 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13244 TargetLowering::DAGCombinerInfo &DCI,
13245 const X86Subtarget *Subtarget) {
13246 if (DCI.isBeforeLegalizeOps())
13249 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13253 // Want to form ANDNP nodes:
13254 // 1) In the hopes of then easily combining them with OR and AND nodes
13255 // to form PBLEND/PSIGN.
13256 // 2) To match ANDN packed intrinsics
13257 EVT VT = N->getValueType(0);
13258 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13261 SDValue N0 = N->getOperand(0);
13262 SDValue N1 = N->getOperand(1);
13263 DebugLoc DL = N->getDebugLoc();
13265 // Check LHS for vnot
13266 if (N0.getOpcode() == ISD::XOR &&
13267 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13268 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13269 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13271 // Check RHS for vnot
13272 if (N1.getOpcode() == ISD::XOR &&
13273 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13274 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13275 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13280 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13281 TargetLowering::DAGCombinerInfo &DCI,
13282 const X86Subtarget *Subtarget) {
13283 if (DCI.isBeforeLegalizeOps())
13286 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13290 EVT VT = N->getValueType(0);
13291 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
13294 SDValue N0 = N->getOperand(0);
13295 SDValue N1 = N->getOperand(1);
13297 // look for psign/blend
13298 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) {
13299 if (VT == MVT::v2i64) {
13300 // Canonicalize pandn to RHS
13301 if (N0.getOpcode() == X86ISD::ANDNP)
13303 // or (and (m, x), (pandn m, y))
13304 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13305 SDValue Mask = N1.getOperand(0);
13306 SDValue X = N1.getOperand(1);
13308 if (N0.getOperand(0) == Mask)
13309 Y = N0.getOperand(1);
13310 if (N0.getOperand(1) == Mask)
13311 Y = N0.getOperand(0);
13313 // Check to see if the mask appeared in both the AND and ANDNP and
13317 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13318 if (Mask.getOpcode() != ISD::BITCAST ||
13319 X.getOpcode() != ISD::BITCAST ||
13320 Y.getOpcode() != ISD::BITCAST)
13323 // Look through mask bitcast.
13324 Mask = Mask.getOperand(0);
13325 EVT MaskVT = Mask.getValueType();
13327 // Validate that the Mask operand is a vector sra node. The sra node
13328 // will be an intrinsic.
13329 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13332 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13333 // there is no psrai.b
13334 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13335 case Intrinsic::x86_sse2_psrai_w:
13336 case Intrinsic::x86_sse2_psrai_d:
13338 default: return SDValue();
13341 // Check that the SRA is all signbits.
13342 SDValue SraC = Mask.getOperand(2);
13343 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13344 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13345 if ((SraAmt + 1) != EltBits)
13348 DebugLoc DL = N->getDebugLoc();
13350 // Now we know we at least have a plendvb with the mask val. See if
13351 // we can form a psignb/w/d.
13352 // psign = x.type == y.type == mask.type && y = sub(0, x);
13353 X = X.getOperand(0);
13354 Y = Y.getOperand(0);
13355 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13356 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13357 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
13360 case 8: Opc = X86ISD::PSIGNB; break;
13361 case 16: Opc = X86ISD::PSIGNW; break;
13362 case 32: Opc = X86ISD::PSIGND; break;
13366 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
13367 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
13370 // PBLENDVB only available on SSE 4.1
13371 if (!(Subtarget->hasSSE41() || Subtarget->hasAVX()))
13374 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
13375 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
13376 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
13377 Mask = DAG.getNode(ISD::VSELECT, DL, MVT::v16i8, Mask, X, Y);
13378 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
13383 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13384 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13386 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13388 if (!N0.hasOneUse() || !N1.hasOneUse())
13391 SDValue ShAmt0 = N0.getOperand(1);
13392 if (ShAmt0.getValueType() != MVT::i8)
13394 SDValue ShAmt1 = N1.getOperand(1);
13395 if (ShAmt1.getValueType() != MVT::i8)
13397 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13398 ShAmt0 = ShAmt0.getOperand(0);
13399 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13400 ShAmt1 = ShAmt1.getOperand(0);
13402 DebugLoc DL = N->getDebugLoc();
13403 unsigned Opc = X86ISD::SHLD;
13404 SDValue Op0 = N0.getOperand(0);
13405 SDValue Op1 = N1.getOperand(0);
13406 if (ShAmt0.getOpcode() == ISD::SUB) {
13407 Opc = X86ISD::SHRD;
13408 std::swap(Op0, Op1);
13409 std::swap(ShAmt0, ShAmt1);
13412 unsigned Bits = VT.getSizeInBits();
13413 if (ShAmt1.getOpcode() == ISD::SUB) {
13414 SDValue Sum = ShAmt1.getOperand(0);
13415 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13416 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13417 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13418 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13419 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13420 return DAG.getNode(Opc, DL, VT,
13422 DAG.getNode(ISD::TRUNCATE, DL,
13425 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13426 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13428 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13429 return DAG.getNode(Opc, DL, VT,
13430 N0.getOperand(0), N1.getOperand(0),
13431 DAG.getNode(ISD::TRUNCATE, DL,
13438 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
13439 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
13440 const X86Subtarget *Subtarget) {
13441 LoadSDNode *Ld = cast<LoadSDNode>(N);
13442 EVT RegVT = Ld->getValueType(0);
13443 EVT MemVT = Ld->getMemoryVT();
13444 DebugLoc dl = Ld->getDebugLoc();
13445 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13447 ISD::LoadExtType Ext = Ld->getExtensionType();
13449 // If this is a vector EXT Load then attempt to optimize it using a
13450 // shuffle. We need SSE4 for the shuffles.
13451 // TODO: It is possible to support ZExt by zeroing the undef values
13452 // during the shuffle phase or after the shuffle.
13453 if (RegVT.isVector() && Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
13454 assert(MemVT != RegVT && "Cannot extend to the same type");
13455 assert(MemVT.isVector() && "Must load a vector from memory");
13457 unsigned NumElems = RegVT.getVectorNumElements();
13458 unsigned RegSz = RegVT.getSizeInBits();
13459 unsigned MemSz = MemVT.getSizeInBits();
13460 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13461 // All sizes must be a power of two
13462 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
13464 // Attempt to load the original value using a single load op.
13465 // Find a scalar type which is equal to the loaded word size.
13466 MVT SclrLoadTy = MVT::i8;
13467 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13468 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13469 MVT Tp = (MVT::SimpleValueType)tp;
13470 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
13476 // Proceed if a load word is found.
13477 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
13479 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
13480 RegSz/SclrLoadTy.getSizeInBits());
13482 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13483 RegSz/MemVT.getScalarType().getSizeInBits());
13484 // Can't shuffle using an illegal type.
13485 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13487 // Perform a single load.
13488 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
13490 Ld->getPointerInfo(), Ld->isVolatile(),
13491 Ld->isNonTemporal(), Ld->getAlignment());
13493 // Insert the word loaded into a vector.
13494 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13495 LoadUnitVecVT, ScalarLoad);
13497 // Bitcast the loaded value to a vector of the original element type, in
13498 // the size of the target vector type.
13499 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, ScalarInVector);
13500 unsigned SizeRatio = RegSz/MemSz;
13502 // Redistribute the loaded elements into the different locations.
13503 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13504 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
13506 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13507 DAG.getUNDEF(SlicedVec.getValueType()),
13508 ShuffleVec.data());
13510 // Bitcast to the requested type.
13511 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13512 // Replace the original load with the new sequence
13513 // and return the new chain.
13514 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
13515 return SDValue(ScalarLoad.getNode(), 1);
13521 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13522 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13523 const X86Subtarget *Subtarget) {
13524 StoreSDNode *St = cast<StoreSDNode>(N);
13525 EVT VT = St->getValue().getValueType();
13526 EVT StVT = St->getMemoryVT();
13527 DebugLoc dl = St->getDebugLoc();
13528 SDValue StoredVal = St->getOperand(1);
13529 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13531 // If we are saving a concatination of two XMM registers, perform two stores.
13532 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13533 // 128-bit ones. If in the future the cost becomes only one memory access the
13534 // first version would be better.
13535 if (VT.getSizeInBits() == 256 &&
13536 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
13537 StoredVal.getNumOperands() == 2) {
13539 SDValue Value0 = StoredVal.getOperand(0);
13540 SDValue Value1 = StoredVal.getOperand(1);
13542 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
13543 SDValue Ptr0 = St->getBasePtr();
13544 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
13546 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
13547 St->getPointerInfo(), St->isVolatile(),
13548 St->isNonTemporal(), St->getAlignment());
13549 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
13550 St->getPointerInfo(), St->isVolatile(),
13551 St->isNonTemporal(), St->getAlignment());
13552 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
13555 // Optimize trunc store (of multiple scalars) to shuffle and store.
13556 // First, pack all of the elements in one place. Next, store to memory
13557 // in fewer chunks.
13558 if (St->isTruncatingStore() && VT.isVector()) {
13559 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13560 unsigned NumElems = VT.getVectorNumElements();
13561 assert(StVT != VT && "Cannot truncate to the same type");
13562 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
13563 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
13565 // From, To sizes and ElemCount must be pow of two
13566 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
13567 // We are going to use the original vector elt for storing.
13568 // Accumulated smaller vector elements must be a multiple of the store size.
13569 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
13571 unsigned SizeRatio = FromSz / ToSz;
13573 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
13575 // Create a type on which we perform the shuffle
13576 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
13577 StVT.getScalarType(), NumElems*SizeRatio);
13579 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
13581 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
13582 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13583 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
13585 // Can't shuffle using an illegal type
13586 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13588 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
13589 DAG.getUNDEF(WideVec.getValueType()),
13590 ShuffleVec.data());
13591 // At this point all of the data is stored at the bottom of the
13592 // register. We now need to save it to mem.
13594 // Find the largest store unit
13595 MVT StoreType = MVT::i8;
13596 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13597 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13598 MVT Tp = (MVT::SimpleValueType)tp;
13599 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
13603 // Bitcast the original vector into a vector of store-size units
13604 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
13605 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
13606 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
13607 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
13608 SmallVector<SDValue, 8> Chains;
13609 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
13610 TLI.getPointerTy());
13611 SDValue Ptr = St->getBasePtr();
13613 // Perform one or more big stores into memory.
13614 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
13615 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
13616 StoreType, ShuffWide,
13617 DAG.getIntPtrConstant(i));
13618 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
13619 St->getPointerInfo(), St->isVolatile(),
13620 St->isNonTemporal(), St->getAlignment());
13621 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13622 Chains.push_back(Ch);
13625 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
13630 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
13631 // the FP state in cases where an emms may be missing.
13632 // A preferable solution to the general problem is to figure out the right
13633 // places to insert EMMS. This qualifies as a quick hack.
13635 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
13636 if (VT.getSizeInBits() != 64)
13639 const Function *F = DAG.getMachineFunction().getFunction();
13640 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
13641 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
13642 && Subtarget->hasXMMInt();
13643 if ((VT.isVector() ||
13644 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
13645 isa<LoadSDNode>(St->getValue()) &&
13646 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
13647 St->getChain().hasOneUse() && !St->isVolatile()) {
13648 SDNode* LdVal = St->getValue().getNode();
13649 LoadSDNode *Ld = 0;
13650 int TokenFactorIndex = -1;
13651 SmallVector<SDValue, 8> Ops;
13652 SDNode* ChainVal = St->getChain().getNode();
13653 // Must be a store of a load. We currently handle two cases: the load
13654 // is a direct child, and it's under an intervening TokenFactor. It is
13655 // possible to dig deeper under nested TokenFactors.
13656 if (ChainVal == LdVal)
13657 Ld = cast<LoadSDNode>(St->getChain());
13658 else if (St->getValue().hasOneUse() &&
13659 ChainVal->getOpcode() == ISD::TokenFactor) {
13660 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
13661 if (ChainVal->getOperand(i).getNode() == LdVal) {
13662 TokenFactorIndex = i;
13663 Ld = cast<LoadSDNode>(St->getValue());
13665 Ops.push_back(ChainVal->getOperand(i));
13669 if (!Ld || !ISD::isNormalLoad(Ld))
13672 // If this is not the MMX case, i.e. we are just turning i64 load/store
13673 // into f64 load/store, avoid the transformation if there are multiple
13674 // uses of the loaded value.
13675 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
13678 DebugLoc LdDL = Ld->getDebugLoc();
13679 DebugLoc StDL = N->getDebugLoc();
13680 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
13681 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
13683 if (Subtarget->is64Bit() || F64IsLegal) {
13684 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
13685 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
13686 Ld->getPointerInfo(), Ld->isVolatile(),
13687 Ld->isNonTemporal(), Ld->getAlignment());
13688 SDValue NewChain = NewLd.getValue(1);
13689 if (TokenFactorIndex != -1) {
13690 Ops.push_back(NewChain);
13691 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13694 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
13695 St->getPointerInfo(),
13696 St->isVolatile(), St->isNonTemporal(),
13697 St->getAlignment());
13700 // Otherwise, lower to two pairs of 32-bit loads / stores.
13701 SDValue LoAddr = Ld->getBasePtr();
13702 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
13703 DAG.getConstant(4, MVT::i32));
13705 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
13706 Ld->getPointerInfo(),
13707 Ld->isVolatile(), Ld->isNonTemporal(),
13708 Ld->getAlignment());
13709 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
13710 Ld->getPointerInfo().getWithOffset(4),
13711 Ld->isVolatile(), Ld->isNonTemporal(),
13712 MinAlign(Ld->getAlignment(), 4));
13714 SDValue NewChain = LoLd.getValue(1);
13715 if (TokenFactorIndex != -1) {
13716 Ops.push_back(LoLd);
13717 Ops.push_back(HiLd);
13718 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13722 LoAddr = St->getBasePtr();
13723 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
13724 DAG.getConstant(4, MVT::i32));
13726 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
13727 St->getPointerInfo(),
13728 St->isVolatile(), St->isNonTemporal(),
13729 St->getAlignment());
13730 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
13731 St->getPointerInfo().getWithOffset(4),
13733 St->isNonTemporal(),
13734 MinAlign(St->getAlignment(), 4));
13735 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
13740 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
13741 /// X86ISD::FXOR nodes.
13742 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
13743 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
13744 // F[X]OR(0.0, x) -> x
13745 // F[X]OR(x, 0.0) -> x
13746 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13747 if (C->getValueAPF().isPosZero())
13748 return N->getOperand(1);
13749 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13750 if (C->getValueAPF().isPosZero())
13751 return N->getOperand(0);
13755 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
13756 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
13757 // FAND(0.0, x) -> 0.0
13758 // FAND(x, 0.0) -> 0.0
13759 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13760 if (C->getValueAPF().isPosZero())
13761 return N->getOperand(0);
13762 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13763 if (C->getValueAPF().isPosZero())
13764 return N->getOperand(1);
13768 static SDValue PerformBTCombine(SDNode *N,
13770 TargetLowering::DAGCombinerInfo &DCI) {
13771 // BT ignores high bits in the bit index operand.
13772 SDValue Op1 = N->getOperand(1);
13773 if (Op1.hasOneUse()) {
13774 unsigned BitWidth = Op1.getValueSizeInBits();
13775 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
13776 APInt KnownZero, KnownOne;
13777 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
13778 !DCI.isBeforeLegalizeOps());
13779 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13780 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
13781 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
13782 DCI.CommitTargetLoweringOpt(TLO);
13787 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
13788 SDValue Op = N->getOperand(0);
13789 if (Op.getOpcode() == ISD::BITCAST)
13790 Op = Op.getOperand(0);
13791 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
13792 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
13793 VT.getVectorElementType().getSizeInBits() ==
13794 OpVT.getVectorElementType().getSizeInBits()) {
13795 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
13800 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
13801 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
13802 // (and (i32 x86isd::setcc_carry), 1)
13803 // This eliminates the zext. This transformation is necessary because
13804 // ISD::SETCC is always legalized to i8.
13805 DebugLoc dl = N->getDebugLoc();
13806 SDValue N0 = N->getOperand(0);
13807 EVT VT = N->getValueType(0);
13808 if (N0.getOpcode() == ISD::AND &&
13810 N0.getOperand(0).hasOneUse()) {
13811 SDValue N00 = N0.getOperand(0);
13812 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
13814 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
13815 if (!C || C->getZExtValue() != 1)
13817 return DAG.getNode(ISD::AND, dl, VT,
13818 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
13819 N00.getOperand(0), N00.getOperand(1)),
13820 DAG.getConstant(1, VT));
13826 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
13827 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
13828 unsigned X86CC = N->getConstantOperandVal(0);
13829 SDValue EFLAG = N->getOperand(1);
13830 DebugLoc DL = N->getDebugLoc();
13832 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
13833 // a zext and produces an all-ones bit which is more useful than 0/1 in some
13835 if (X86CC == X86::COND_B)
13836 return DAG.getNode(ISD::AND, DL, MVT::i8,
13837 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
13838 DAG.getConstant(X86CC, MVT::i8), EFLAG),
13839 DAG.getConstant(1, MVT::i8));
13844 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
13845 const X86TargetLowering *XTLI) {
13846 SDValue Op0 = N->getOperand(0);
13847 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
13848 // a 32-bit target where SSE doesn't support i64->FP operations.
13849 if (Op0.getOpcode() == ISD::LOAD) {
13850 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
13851 EVT VT = Ld->getValueType(0);
13852 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
13853 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
13854 !XTLI->getSubtarget()->is64Bit() &&
13855 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13856 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
13857 Ld->getChain(), Op0, DAG);
13858 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
13865 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
13866 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
13867 X86TargetLowering::DAGCombinerInfo &DCI) {
13868 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
13869 // the result is either zero or one (depending on the input carry bit).
13870 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
13871 if (X86::isZeroNode(N->getOperand(0)) &&
13872 X86::isZeroNode(N->getOperand(1)) &&
13873 // We don't have a good way to replace an EFLAGS use, so only do this when
13875 SDValue(N, 1).use_empty()) {
13876 DebugLoc DL = N->getDebugLoc();
13877 EVT VT = N->getValueType(0);
13878 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
13879 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
13880 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
13881 DAG.getConstant(X86::COND_B,MVT::i8),
13883 DAG.getConstant(1, VT));
13884 return DCI.CombineTo(N, Res1, CarryOut);
13890 // fold (add Y, (sete X, 0)) -> adc 0, Y
13891 // (add Y, (setne X, 0)) -> sbb -1, Y
13892 // (sub (sete X, 0), Y) -> sbb 0, Y
13893 // (sub (setne X, 0), Y) -> adc -1, Y
13894 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
13895 DebugLoc DL = N->getDebugLoc();
13897 // Look through ZExts.
13898 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
13899 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
13902 SDValue SetCC = Ext.getOperand(0);
13903 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
13906 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
13907 if (CC != X86::COND_E && CC != X86::COND_NE)
13910 SDValue Cmp = SetCC.getOperand(1);
13911 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
13912 !X86::isZeroNode(Cmp.getOperand(1)) ||
13913 !Cmp.getOperand(0).getValueType().isInteger())
13916 SDValue CmpOp0 = Cmp.getOperand(0);
13917 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
13918 DAG.getConstant(1, CmpOp0.getValueType()));
13920 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
13921 if (CC == X86::COND_NE)
13922 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
13923 DL, OtherVal.getValueType(), OtherVal,
13924 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
13925 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
13926 DL, OtherVal.getValueType(), OtherVal,
13927 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
13930 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
13931 SDValue Op0 = N->getOperand(0);
13932 SDValue Op1 = N->getOperand(1);
13934 // X86 can't encode an immediate LHS of a sub. See if we can push the
13935 // negation into a preceding instruction.
13936 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
13937 // If the RHS of the sub is a XOR with one use and a constant, invert the
13938 // immediate. Then add one to the LHS of the sub so we can turn
13939 // X-Y -> X+~Y+1, saving one register.
13940 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
13941 isa<ConstantSDNode>(Op1.getOperand(1))) {
13942 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
13943 EVT VT = Op0.getValueType();
13944 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
13946 DAG.getConstant(~XorC, VT));
13947 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
13948 DAG.getConstant(C->getAPIntValue()+1, VT));
13952 return OptimizeConditionalInDecrement(N, DAG);
13955 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
13956 DAGCombinerInfo &DCI) const {
13957 SelectionDAG &DAG = DCI.DAG;
13958 switch (N->getOpcode()) {
13960 case ISD::EXTRACT_VECTOR_ELT:
13961 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
13963 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
13964 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
13965 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
13966 case ISD::SUB: return PerformSubCombine(N, DAG);
13967 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
13968 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
13971 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
13972 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
13973 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
13974 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
13975 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
13976 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
13978 case X86ISD::FOR: return PerformFORCombine(N, DAG);
13979 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
13980 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
13981 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
13982 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
13983 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
13984 case X86ISD::SHUFPS: // Handle all target specific shuffles
13985 case X86ISD::SHUFPD:
13986 case X86ISD::PALIGN:
13987 case X86ISD::PUNPCKHBW:
13988 case X86ISD::PUNPCKHWD:
13989 case X86ISD::PUNPCKHDQ:
13990 case X86ISD::PUNPCKHQDQ:
13991 case X86ISD::UNPCKHPS:
13992 case X86ISD::UNPCKHPD:
13993 case X86ISD::VUNPCKHPSY:
13994 case X86ISD::VUNPCKHPDY:
13995 case X86ISD::PUNPCKLBW:
13996 case X86ISD::PUNPCKLWD:
13997 case X86ISD::PUNPCKLDQ:
13998 case X86ISD::PUNPCKLQDQ:
13999 case X86ISD::UNPCKLPS:
14000 case X86ISD::UNPCKLPD:
14001 case X86ISD::VUNPCKLPSY:
14002 case X86ISD::VUNPCKLPDY:
14003 case X86ISD::MOVHLPS:
14004 case X86ISD::MOVLHPS:
14005 case X86ISD::PSHUFD:
14006 case X86ISD::PSHUFHW:
14007 case X86ISD::PSHUFLW:
14008 case X86ISD::MOVSS:
14009 case X86ISD::MOVSD:
14010 case X86ISD::VPERMILPS:
14011 case X86ISD::VPERMILPSY:
14012 case X86ISD::VPERMILPD:
14013 case X86ISD::VPERMILPDY:
14014 case X86ISD::VPERM2F128:
14015 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14021 /// isTypeDesirableForOp - Return true if the target has native support for
14022 /// the specified value type and it is 'desirable' to use the type for the
14023 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14024 /// instruction encodings are longer and some i16 instructions are slow.
14025 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14026 if (!isTypeLegal(VT))
14028 if (VT != MVT::i16)
14035 case ISD::SIGN_EXTEND:
14036 case ISD::ZERO_EXTEND:
14037 case ISD::ANY_EXTEND:
14050 /// IsDesirableToPromoteOp - This method query the target whether it is
14051 /// beneficial for dag combiner to promote the specified node. If true, it
14052 /// should return the desired promotion type by reference.
14053 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14054 EVT VT = Op.getValueType();
14055 if (VT != MVT::i16)
14058 bool Promote = false;
14059 bool Commute = false;
14060 switch (Op.getOpcode()) {
14063 LoadSDNode *LD = cast<LoadSDNode>(Op);
14064 // If the non-extending load has a single use and it's not live out, then it
14065 // might be folded.
14066 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14067 Op.hasOneUse()*/) {
14068 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14069 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14070 // The only case where we'd want to promote LOAD (rather then it being
14071 // promoted as an operand is when it's only use is liveout.
14072 if (UI->getOpcode() != ISD::CopyToReg)
14079 case ISD::SIGN_EXTEND:
14080 case ISD::ZERO_EXTEND:
14081 case ISD::ANY_EXTEND:
14086 SDValue N0 = Op.getOperand(0);
14087 // Look out for (store (shl (load), x)).
14088 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
14101 SDValue N0 = Op.getOperand(0);
14102 SDValue N1 = Op.getOperand(1);
14103 if (!Commute && MayFoldLoad(N1))
14105 // Avoid disabling potential load folding opportunities.
14106 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14108 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14118 //===----------------------------------------------------------------------===//
14119 // X86 Inline Assembly Support
14120 //===----------------------------------------------------------------------===//
14122 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
14123 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
14125 std::string AsmStr = IA->getAsmString();
14127 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
14128 SmallVector<StringRef, 4> AsmPieces;
14129 SplitString(AsmStr, AsmPieces, ";\n");
14131 switch (AsmPieces.size()) {
14132 default: return false;
14134 AsmStr = AsmPieces[0];
14136 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
14138 // FIXME: this should verify that we are targeting a 486 or better. If not,
14139 // we will turn this bswap into something that will be lowered to logical ops
14140 // instead of emitting the bswap asm. For now, we don't support 486 or lower
14141 // so don't worry about this.
14143 if (AsmPieces.size() == 2 &&
14144 (AsmPieces[0] == "bswap" ||
14145 AsmPieces[0] == "bswapq" ||
14146 AsmPieces[0] == "bswapl") &&
14147 (AsmPieces[1] == "$0" ||
14148 AsmPieces[1] == "${0:q}")) {
14149 // No need to check constraints, nothing other than the equivalent of
14150 // "=r,0" would be valid here.
14151 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14152 if (!Ty || Ty->getBitWidth() % 16 != 0)
14154 return IntrinsicLowering::LowerToByteSwap(CI);
14156 // rorw $$8, ${0:w} --> llvm.bswap.i16
14157 if (CI->getType()->isIntegerTy(16) &&
14158 AsmPieces.size() == 3 &&
14159 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
14160 AsmPieces[1] == "$$8," &&
14161 AsmPieces[2] == "${0:w}" &&
14162 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
14164 const std::string &ConstraintsStr = IA->getConstraintString();
14165 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14166 std::sort(AsmPieces.begin(), AsmPieces.end());
14167 if (AsmPieces.size() == 4 &&
14168 AsmPieces[0] == "~{cc}" &&
14169 AsmPieces[1] == "~{dirflag}" &&
14170 AsmPieces[2] == "~{flags}" &&
14171 AsmPieces[3] == "~{fpsr}") {
14172 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14173 if (!Ty || Ty->getBitWidth() % 16 != 0)
14175 return IntrinsicLowering::LowerToByteSwap(CI);
14180 if (CI->getType()->isIntegerTy(32) &&
14181 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
14182 SmallVector<StringRef, 4> Words;
14183 SplitString(AsmPieces[0], Words, " \t,");
14184 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
14185 Words[2] == "${0:w}") {
14187 SplitString(AsmPieces[1], Words, " \t,");
14188 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
14189 Words[2] == "$0") {
14191 SplitString(AsmPieces[2], Words, " \t,");
14192 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
14193 Words[2] == "${0:w}") {
14195 const std::string &ConstraintsStr = IA->getConstraintString();
14196 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14197 std::sort(AsmPieces.begin(), AsmPieces.end());
14198 if (AsmPieces.size() == 4 &&
14199 AsmPieces[0] == "~{cc}" &&
14200 AsmPieces[1] == "~{dirflag}" &&
14201 AsmPieces[2] == "~{flags}" &&
14202 AsmPieces[3] == "~{fpsr}") {
14203 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14204 if (!Ty || Ty->getBitWidth() % 16 != 0)
14206 return IntrinsicLowering::LowerToByteSwap(CI);
14213 if (CI->getType()->isIntegerTy(64)) {
14214 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
14215 if (Constraints.size() >= 2 &&
14216 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
14217 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
14218 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14219 SmallVector<StringRef, 4> Words;
14220 SplitString(AsmPieces[0], Words, " \t");
14221 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
14223 SplitString(AsmPieces[1], Words, " \t");
14224 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
14226 SplitString(AsmPieces[2], Words, " \t,");
14227 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
14228 Words[2] == "%edx") {
14229 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14230 if (!Ty || Ty->getBitWidth() % 16 != 0)
14232 return IntrinsicLowering::LowerToByteSwap(CI);
14245 /// getConstraintType - Given a constraint letter, return the type of
14246 /// constraint it is for this target.
14247 X86TargetLowering::ConstraintType
14248 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
14249 if (Constraint.size() == 1) {
14250 switch (Constraint[0]) {
14261 return C_RegisterClass;
14285 return TargetLowering::getConstraintType(Constraint);
14288 /// Examine constraint type and operand type and determine a weight value.
14289 /// This object must already have been set up with the operand type
14290 /// and the current alternative constraint selected.
14291 TargetLowering::ConstraintWeight
14292 X86TargetLowering::getSingleConstraintMatchWeight(
14293 AsmOperandInfo &info, const char *constraint) const {
14294 ConstraintWeight weight = CW_Invalid;
14295 Value *CallOperandVal = info.CallOperandVal;
14296 // If we don't have a value, we can't do a match,
14297 // but allow it at the lowest weight.
14298 if (CallOperandVal == NULL)
14300 Type *type = CallOperandVal->getType();
14301 // Look at the constraint type.
14302 switch (*constraint) {
14304 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14315 if (CallOperandVal->getType()->isIntegerTy())
14316 weight = CW_SpecificReg;
14321 if (type->isFloatingPointTy())
14322 weight = CW_SpecificReg;
14325 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14326 weight = CW_SpecificReg;
14330 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
14331 weight = CW_Register;
14334 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14335 if (C->getZExtValue() <= 31)
14336 weight = CW_Constant;
14340 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14341 if (C->getZExtValue() <= 63)
14342 weight = CW_Constant;
14346 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14347 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14348 weight = CW_Constant;
14352 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14353 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14354 weight = CW_Constant;
14358 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14359 if (C->getZExtValue() <= 3)
14360 weight = CW_Constant;
14364 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14365 if (C->getZExtValue() <= 0xff)
14366 weight = CW_Constant;
14371 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14372 weight = CW_Constant;
14376 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14377 if ((C->getSExtValue() >= -0x80000000LL) &&
14378 (C->getSExtValue() <= 0x7fffffffLL))
14379 weight = CW_Constant;
14383 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14384 if (C->getZExtValue() <= 0xffffffff)
14385 weight = CW_Constant;
14392 /// LowerXConstraint - try to replace an X constraint, which matches anything,
14393 /// with another that has more specific requirements based on the type of the
14394 /// corresponding operand.
14395 const char *X86TargetLowering::
14396 LowerXConstraint(EVT ConstraintVT) const {
14397 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
14398 // 'f' like normal targets.
14399 if (ConstraintVT.isFloatingPoint()) {
14400 if (Subtarget->hasXMMInt())
14402 if (Subtarget->hasXMM())
14406 return TargetLowering::LowerXConstraint(ConstraintVT);
14409 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
14410 /// vector. If it is invalid, don't add anything to Ops.
14411 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
14412 std::string &Constraint,
14413 std::vector<SDValue>&Ops,
14414 SelectionDAG &DAG) const {
14415 SDValue Result(0, 0);
14417 // Only support length 1 constraints for now.
14418 if (Constraint.length() > 1) return;
14420 char ConstraintLetter = Constraint[0];
14421 switch (ConstraintLetter) {
14424 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14425 if (C->getZExtValue() <= 31) {
14426 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14432 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14433 if (C->getZExtValue() <= 63) {
14434 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14440 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14441 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
14442 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14448 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14449 if (C->getZExtValue() <= 255) {
14450 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14456 // 32-bit signed value
14457 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14458 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14459 C->getSExtValue())) {
14460 // Widen to 64 bits here to get it sign extended.
14461 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
14464 // FIXME gcc accepts some relocatable values here too, but only in certain
14465 // memory models; it's complicated.
14470 // 32-bit unsigned value
14471 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14472 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14473 C->getZExtValue())) {
14474 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14478 // FIXME gcc accepts some relocatable values here too, but only in certain
14479 // memory models; it's complicated.
14483 // Literal immediates are always ok.
14484 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
14485 // Widen to 64 bits here to get it sign extended.
14486 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
14490 // In any sort of PIC mode addresses need to be computed at runtime by
14491 // adding in a register or some sort of table lookup. These can't
14492 // be used as immediates.
14493 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
14496 // If we are in non-pic codegen mode, we allow the address of a global (with
14497 // an optional displacement) to be used with 'i'.
14498 GlobalAddressSDNode *GA = 0;
14499 int64_t Offset = 0;
14501 // Match either (GA), (GA+C), (GA+C1+C2), etc.
14503 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
14504 Offset += GA->getOffset();
14506 } else if (Op.getOpcode() == ISD::ADD) {
14507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14508 Offset += C->getZExtValue();
14509 Op = Op.getOperand(0);
14512 } else if (Op.getOpcode() == ISD::SUB) {
14513 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14514 Offset += -C->getZExtValue();
14515 Op = Op.getOperand(0);
14520 // Otherwise, this isn't something we can handle, reject it.
14524 const GlobalValue *GV = GA->getGlobal();
14525 // If we require an extra load to get this address, as in PIC mode, we
14526 // can't accept it.
14527 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
14528 getTargetMachine())))
14531 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
14532 GA->getValueType(0), Offset);
14537 if (Result.getNode()) {
14538 Ops.push_back(Result);
14541 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
14544 std::pair<unsigned, const TargetRegisterClass*>
14545 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
14547 // First, see if this is a constraint that directly corresponds to an LLVM
14549 if (Constraint.size() == 1) {
14550 // GCC Constraint Letters
14551 switch (Constraint[0]) {
14553 // TODO: Slight differences here in allocation order and leaving
14554 // RIP in the class. Do they matter any more here than they do
14555 // in the normal allocation?
14556 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
14557 if (Subtarget->is64Bit()) {
14558 if (VT == MVT::i32 || VT == MVT::f32)
14559 return std::make_pair(0U, X86::GR32RegisterClass);
14560 else if (VT == MVT::i16)
14561 return std::make_pair(0U, X86::GR16RegisterClass);
14562 else if (VT == MVT::i8 || VT == MVT::i1)
14563 return std::make_pair(0U, X86::GR8RegisterClass);
14564 else if (VT == MVT::i64 || VT == MVT::f64)
14565 return std::make_pair(0U, X86::GR64RegisterClass);
14568 // 32-bit fallthrough
14569 case 'Q': // Q_REGS
14570 if (VT == MVT::i32 || VT == MVT::f32)
14571 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
14572 else if (VT == MVT::i16)
14573 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
14574 else if (VT == MVT::i8 || VT == MVT::i1)
14575 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
14576 else if (VT == MVT::i64)
14577 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
14579 case 'r': // GENERAL_REGS
14580 case 'l': // INDEX_REGS
14581 if (VT == MVT::i8 || VT == MVT::i1)
14582 return std::make_pair(0U, X86::GR8RegisterClass);
14583 if (VT == MVT::i16)
14584 return std::make_pair(0U, X86::GR16RegisterClass);
14585 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
14586 return std::make_pair(0U, X86::GR32RegisterClass);
14587 return std::make_pair(0U, X86::GR64RegisterClass);
14588 case 'R': // LEGACY_REGS
14589 if (VT == MVT::i8 || VT == MVT::i1)
14590 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
14591 if (VT == MVT::i16)
14592 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
14593 if (VT == MVT::i32 || !Subtarget->is64Bit())
14594 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
14595 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
14596 case 'f': // FP Stack registers.
14597 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
14598 // value to the correct fpstack register class.
14599 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
14600 return std::make_pair(0U, X86::RFP32RegisterClass);
14601 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
14602 return std::make_pair(0U, X86::RFP64RegisterClass);
14603 return std::make_pair(0U, X86::RFP80RegisterClass);
14604 case 'y': // MMX_REGS if MMX allowed.
14605 if (!Subtarget->hasMMX()) break;
14606 return std::make_pair(0U, X86::VR64RegisterClass);
14607 case 'Y': // SSE_REGS if SSE2 allowed
14608 if (!Subtarget->hasXMMInt()) break;
14610 case 'x': // SSE_REGS if SSE1 allowed
14611 if (!Subtarget->hasXMM()) break;
14613 switch (VT.getSimpleVT().SimpleTy) {
14615 // Scalar SSE types.
14618 return std::make_pair(0U, X86::FR32RegisterClass);
14621 return std::make_pair(0U, X86::FR64RegisterClass);
14629 return std::make_pair(0U, X86::VR128RegisterClass);
14635 // Use the default implementation in TargetLowering to convert the register
14636 // constraint into a member of a register class.
14637 std::pair<unsigned, const TargetRegisterClass*> Res;
14638 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
14640 // Not found as a standard register?
14641 if (Res.second == 0) {
14642 // Map st(0) -> st(7) -> ST0
14643 if (Constraint.size() == 7 && Constraint[0] == '{' &&
14644 tolower(Constraint[1]) == 's' &&
14645 tolower(Constraint[2]) == 't' &&
14646 Constraint[3] == '(' &&
14647 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
14648 Constraint[5] == ')' &&
14649 Constraint[6] == '}') {
14651 Res.first = X86::ST0+Constraint[4]-'0';
14652 Res.second = X86::RFP80RegisterClass;
14656 // GCC allows "st(0)" to be called just plain "st".
14657 if (StringRef("{st}").equals_lower(Constraint)) {
14658 Res.first = X86::ST0;
14659 Res.second = X86::RFP80RegisterClass;
14664 if (StringRef("{flags}").equals_lower(Constraint)) {
14665 Res.first = X86::EFLAGS;
14666 Res.second = X86::CCRRegisterClass;
14670 // 'A' means EAX + EDX.
14671 if (Constraint == "A") {
14672 Res.first = X86::EAX;
14673 Res.second = X86::GR32_ADRegisterClass;
14679 // Otherwise, check to see if this is a register class of the wrong value
14680 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
14681 // turn into {ax},{dx}.
14682 if (Res.second->hasType(VT))
14683 return Res; // Correct type already, nothing to do.
14685 // All of the single-register GCC register classes map their values onto
14686 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
14687 // really want an 8-bit or 32-bit register, map to the appropriate register
14688 // class and return the appropriate register.
14689 if (Res.second == X86::GR16RegisterClass) {
14690 if (VT == MVT::i8) {
14691 unsigned DestReg = 0;
14692 switch (Res.first) {
14694 case X86::AX: DestReg = X86::AL; break;
14695 case X86::DX: DestReg = X86::DL; break;
14696 case X86::CX: DestReg = X86::CL; break;
14697 case X86::BX: DestReg = X86::BL; break;
14700 Res.first = DestReg;
14701 Res.second = X86::GR8RegisterClass;
14703 } else if (VT == MVT::i32) {
14704 unsigned DestReg = 0;
14705 switch (Res.first) {
14707 case X86::AX: DestReg = X86::EAX; break;
14708 case X86::DX: DestReg = X86::EDX; break;
14709 case X86::CX: DestReg = X86::ECX; break;
14710 case X86::BX: DestReg = X86::EBX; break;
14711 case X86::SI: DestReg = X86::ESI; break;
14712 case X86::DI: DestReg = X86::EDI; break;
14713 case X86::BP: DestReg = X86::EBP; break;
14714 case X86::SP: DestReg = X86::ESP; break;
14717 Res.first = DestReg;
14718 Res.second = X86::GR32RegisterClass;
14720 } else if (VT == MVT::i64) {
14721 unsigned DestReg = 0;
14722 switch (Res.first) {
14724 case X86::AX: DestReg = X86::RAX; break;
14725 case X86::DX: DestReg = X86::RDX; break;
14726 case X86::CX: DestReg = X86::RCX; break;
14727 case X86::BX: DestReg = X86::RBX; break;
14728 case X86::SI: DestReg = X86::RSI; break;
14729 case X86::DI: DestReg = X86::RDI; break;
14730 case X86::BP: DestReg = X86::RBP; break;
14731 case X86::SP: DestReg = X86::RSP; break;
14734 Res.first = DestReg;
14735 Res.second = X86::GR64RegisterClass;
14738 } else if (Res.second == X86::FR32RegisterClass ||
14739 Res.second == X86::FR64RegisterClass ||
14740 Res.second == X86::VR128RegisterClass) {
14741 // Handle references to XMM physical registers that got mapped into the
14742 // wrong class. This can happen with constraints like {xmm0} where the
14743 // target independent register mapper will just pick the first match it can
14744 // find, ignoring the required type.
14745 if (VT == MVT::f32)
14746 Res.second = X86::FR32RegisterClass;
14747 else if (VT == MVT::f64)
14748 Res.second = X86::FR64RegisterClass;
14749 else if (X86::VR128RegisterClass->hasType(VT))
14750 Res.second = X86::VR128RegisterClass;