1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
117 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
118 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
119 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
120 /// instructions or a simple subregister reference. Idx is an index in the
121 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
122 /// lowering EXTRACT_VECTOR_ELT operations easier.
123 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
124 SelectionDAG &DAG, SDLoc dl) {
125 assert((Vec.getValueType().is256BitVector() ||
126 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
127 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
130 /// Generate a DAG to grab 256-bits from a 512-bit vector.
131 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
132 SelectionDAG &DAG, SDLoc dl) {
133 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
137 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
138 unsigned IdxVal, SelectionDAG &DAG,
139 SDLoc dl, unsigned vectorWidth) {
140 assert((vectorWidth == 128 || vectorWidth == 256) &&
141 "Unsupported vector width");
142 // Inserting UNDEF is Result
143 if (Vec.getOpcode() == ISD::UNDEF)
145 EVT VT = Vec.getValueType();
146 EVT ElVT = VT.getVectorElementType();
147 EVT ResultVT = Result.getValueType();
149 // Insert the relevant vectorWidth bits.
150 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
152 // This is the index of the first element of the vectorWidth-bit chunk
154 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
157 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
158 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
161 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
162 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
163 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
164 /// simple superregister reference. Idx is an index in the 128 bits
165 /// we want. It need not be aligned to a 128-bit boundary. That makes
166 /// lowering INSERT_VECTOR_ELT operations easier.
167 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
168 SelectionDAG &DAG,SDLoc dl) {
169 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
170 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
173 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
174 SelectionDAG &DAG, SDLoc dl) {
175 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
176 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
179 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
180 /// instructions. This is used because creating CONCAT_VECTOR nodes of
181 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
182 /// large BUILD_VECTORS.
183 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
184 unsigned NumElems, SelectionDAG &DAG,
186 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
187 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
190 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
197 // FIXME: This should stop caching the target machine as soon as
198 // we can remove resetOperationActions et al.
199 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
200 : TargetLowering(TM) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird. It always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit, since we have so many registers, use the ILP scheduler.
234 // For 32-bit, use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2.
247 if (TM.getOptLevel() >= CodeGenOpt::Default) {
248 if (Subtarget->hasSlowDivide32())
249 addBypassSlowDiv(32, 8);
250 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
251 addBypassSlowDiv(64, 16);
254 if (Subtarget->isTargetKnownWindowsMSVC()) {
255 // Setup Windows compiler runtime calls.
256 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
257 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
258 setLibcallName(RTLIB::SREM_I64, "_allrem");
259 setLibcallName(RTLIB::UREM_I64, "_aullrem");
260 setLibcallName(RTLIB::MUL_I64, "_allmul");
261 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
267 // The _ftol2 runtime function has an unusual calling conv, which
268 // is modeled by a special pseudo-instruction.
269 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
270 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
271 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
272 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
275 if (Subtarget->isTargetDarwin()) {
276 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
277 setUseUnderscoreSetJmp(false);
278 setUseUnderscoreLongJmp(false);
279 } else if (Subtarget->isTargetWindowsGNU()) {
280 // MS runtime is weird: it exports _setjmp, but longjmp!
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(false);
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(true);
288 // Set up the register classes.
289 addRegisterClass(MVT::i8, &X86::GR8RegClass);
290 addRegisterClass(MVT::i16, &X86::GR16RegClass);
291 addRegisterClass(MVT::i32, &X86::GR32RegClass);
292 if (Subtarget->is64Bit())
293 addRegisterClass(MVT::i64, &X86::GR64RegClass);
295 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
297 // We don't accept any truncstore of integer registers.
298 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
302 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
303 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
305 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
307 // SETOEQ and SETUNE require checking two conditions.
308 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
311 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
315 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
317 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 } else if (!TM.Options.UseSoftFloat) {
325 // We have an algorithm for SSE2->double, and we turn this into a
326 // 64-bit FILD followed by conditional FADD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 // We have an algorithm for SSE2, and we turn this into a 64-bit
329 // FILD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
333 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
335 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
336 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
338 if (!TM.Options.UseSoftFloat) {
339 // SSE has no i16 to fp conversion, only i32
340 if (X86ScalarSSEf32) {
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
342 // f32 and f64 cases are Legal, f80 case is not
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
353 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
354 // are Legal, f80 is custom lowered.
355 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
356 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
358 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
360 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
361 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
363 if (X86ScalarSSEf32) {
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
365 // f32 and f64 cases are Legal, f80 case is not
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 // Handle FP_TO_UINT by promoting the destination to a larger signed
374 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
378 if (Subtarget->is64Bit()) {
379 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
381 } else if (!TM.Options.UseSoftFloat) {
382 // Since AVX is a superset of SSE3, only check for SSE here.
383 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
384 // Expand FP_TO_UINT into a select.
385 // FIXME: We would like to use a Custom expander here eventually to do
386 // the optimal thing for SSE vs. the default expansion in the legalizer.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
389 // With SSE3 we can use fisttpll to convert to a signed i64; without
390 // SSE, we're stuck with a fistpll.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
394 if (isTargetFTOL()) {
395 // Use the _ftol2 runtime function, which has a pseudo-instruction
396 // to handle its weird calling convention.
397 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
400 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
401 if (!X86ScalarSSEf64) {
402 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
403 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
406 // Without SSE, i64->f64 goes through memory.
407 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
411 // Scalar integer divide and remainder are lowered to use operations that
412 // produce two results, to match the available instructions. This exposes
413 // the two-result form to trivial CSE, which is able to combine x/y and x%y
414 // into a single instruction.
416 // Scalar integer multiply-high is also lowered to use two-result
417 // operations, to match the available instructions. However, plain multiply
418 // (low) operations are left as Legal, as there are single-result
419 // instructions for this in x86. Using the two-result multiply instructions
420 // when both high and low results are needed must be arranged by dagcombine.
421 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
423 setOperationAction(ISD::MULHS, VT, Expand);
424 setOperationAction(ISD::MULHU, VT, Expand);
425 setOperationAction(ISD::SDIV, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::SREM, VT, Expand);
428 setOperationAction(ISD::UREM, VT, Expand);
430 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
431 setOperationAction(ISD::ADDC, VT, Custom);
432 setOperationAction(ISD::ADDE, VT, Custom);
433 setOperationAction(ISD::SUBC, VT, Custom);
434 setOperationAction(ISD::SUBE, VT, Custom);
437 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
438 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
439 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
441 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
443 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
444 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
446 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
447 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
448 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
453 if (Subtarget->is64Bit())
454 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
455 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
456 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
458 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
459 setOperationAction(ISD::FREM , MVT::f32 , Expand);
460 setOperationAction(ISD::FREM , MVT::f64 , Expand);
461 setOperationAction(ISD::FREM , MVT::f80 , Expand);
462 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
464 // Promote the i8 variants and force them on up to i32 which has a shorter
466 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
467 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
468 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
469 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
470 if (Subtarget->hasBMI()) {
471 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
476 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
477 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
482 if (Subtarget->hasLZCNT()) {
483 // When promoting the i8 variants, force them to i32 for a shorter
485 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
486 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
488 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
491 if (Subtarget->is64Bit())
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
494 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
495 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
496 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
500 if (Subtarget->is64Bit()) {
501 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
506 // Special handling for half-precision floating point conversions.
507 // If we don't have F16C support, then lower half float conversions
508 // into library calls.
509 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
510 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
511 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
514 // There's never any support for operations beyond MVT::f32.
515 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
516 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
517 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
518 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
520 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
521 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
522 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
523 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
525 if (Subtarget->hasPOPCNT()) {
526 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
528 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
529 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
530 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
531 if (Subtarget->is64Bit())
532 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
535 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
537 if (!Subtarget->hasMOVBE())
538 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
540 // These should be promoted to a larger select which is supported.
541 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
542 // X86 wants to expand cmov itself.
543 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
544 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
545 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
546 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
547 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
548 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
549 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
550 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
552 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
555 if (Subtarget->is64Bit()) {
556 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
559 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
560 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
561 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
562 // support continuation, user-level threading, and etc.. As a result, no
563 // other SjLj exception interfaces are implemented and please don't build
564 // your own exception handling based on them.
565 // LLVM/Clang supports zero-cost DWARF exception handling.
566 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
567 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
570 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
571 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
572 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
573 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
574 if (Subtarget->is64Bit())
575 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
576 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
577 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
578 if (Subtarget->is64Bit()) {
579 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
580 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
581 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
582 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
583 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
585 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
586 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
587 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
588 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
589 if (Subtarget->is64Bit()) {
590 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
595 if (Subtarget->hasSSE1())
596 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
598 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
600 // Expand certain atomics
601 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
603 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
604 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
605 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
608 if (Subtarget->hasCmpxchg16b()) {
609 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
612 // FIXME - use subtarget debug flags
613 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
614 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
615 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
618 if (Subtarget->is64Bit()) {
619 setExceptionPointerRegister(X86::RAX);
620 setExceptionSelectorRegister(X86::RDX);
622 setExceptionPointerRegister(X86::EAX);
623 setExceptionSelectorRegister(X86::EDX);
625 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
626 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
628 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
629 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
631 setOperationAction(ISD::TRAP, MVT::Other, Legal);
632 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
634 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
635 setOperationAction(ISD::VASTART , MVT::Other, Custom);
636 setOperationAction(ISD::VAEND , MVT::Other, Expand);
637 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
638 // TargetInfo::X86_64ABIBuiltinVaList
639 setOperationAction(ISD::VAARG , MVT::Other, Custom);
640 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
642 // TargetInfo::CharPtrBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Expand);
644 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
647 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
648 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
650 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
652 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
653 // f32 and f64 use SSE.
654 // Set up the FP register classes.
655 addRegisterClass(MVT::f32, &X86::FR32RegClass);
656 addRegisterClass(MVT::f64, &X86::FR64RegClass);
658 // Use ANDPD to simulate FABS.
659 setOperationAction(ISD::FABS , MVT::f64, Custom);
660 setOperationAction(ISD::FABS , MVT::f32, Custom);
662 // Use XORP to simulate FNEG.
663 setOperationAction(ISD::FNEG , MVT::f64, Custom);
664 setOperationAction(ISD::FNEG , MVT::f32, Custom);
666 // Use ANDPD and ORPD to simulate FCOPYSIGN.
667 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
668 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
670 // Lower this to FGETSIGNx86 plus an AND.
671 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
672 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
674 // We don't support sin/cos/fmod
675 setOperationAction(ISD::FSIN , MVT::f64, Expand);
676 setOperationAction(ISD::FCOS , MVT::f64, Expand);
677 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
678 setOperationAction(ISD::FSIN , MVT::f32, Expand);
679 setOperationAction(ISD::FCOS , MVT::f32, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
682 // Expand FP immediates into loads from the stack, except for the special
684 addLegalFPImmediate(APFloat(+0.0)); // xorpd
685 addLegalFPImmediate(APFloat(+0.0f)); // xorps
686 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
687 // Use SSE for f32, x87 for f64.
688 // Set up the FP register classes.
689 addRegisterClass(MVT::f32, &X86::FR32RegClass);
690 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
692 // Use ANDPS to simulate FABS.
693 setOperationAction(ISD::FABS , MVT::f32, Custom);
695 // Use XORP to simulate FNEG.
696 setOperationAction(ISD::FNEG , MVT::f32, Custom);
698 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
700 // Use ANDPS and ORPS to simulate FCOPYSIGN.
701 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
702 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
704 // We don't support sin/cos/fmod
705 setOperationAction(ISD::FSIN , MVT::f32, Expand);
706 setOperationAction(ISD::FCOS , MVT::f32, Expand);
707 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
709 // Special cases we handle for FP constants.
710 addLegalFPImmediate(APFloat(+0.0f)); // xorps
711 addLegalFPImmediate(APFloat(+0.0)); // FLD0
712 addLegalFPImmediate(APFloat(+1.0)); // FLD1
713 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
714 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
716 if (!TM.Options.UnsafeFPMath) {
717 setOperationAction(ISD::FSIN , MVT::f64, Expand);
718 setOperationAction(ISD::FCOS , MVT::f64, Expand);
719 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
721 } else if (!TM.Options.UseSoftFloat) {
722 // f32 and f64 in x87.
723 // Set up the FP register classes.
724 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
725 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
727 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
728 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
729 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
730 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FSIN , MVT::f32, Expand);
735 setOperationAction(ISD::FCOS , MVT::f64, Expand);
736 setOperationAction(ISD::FCOS , MVT::f32, Expand);
737 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
738 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
740 addLegalFPImmediate(APFloat(+0.0)); // FLD0
741 addLegalFPImmediate(APFloat(+1.0)); // FLD1
742 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
743 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
744 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
750 // We don't support FMA.
751 setOperationAction(ISD::FMA, MVT::f64, Expand);
752 setOperationAction(ISD::FMA, MVT::f32, Expand);
754 // Long double always uses X87.
755 if (!TM.Options.UseSoftFloat) {
756 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
757 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
758 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
760 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
761 addLegalFPImmediate(TmpFlt); // FLD0
763 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
766 APFloat TmpFlt2(+1.0);
767 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
769 addLegalFPImmediate(TmpFlt2); // FLD1
770 TmpFlt2.changeSign();
771 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
774 if (!TM.Options.UnsafeFPMath) {
775 setOperationAction(ISD::FSIN , MVT::f80, Expand);
776 setOperationAction(ISD::FCOS , MVT::f80, Expand);
777 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
780 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
781 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
782 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
783 setOperationAction(ISD::FRINT, MVT::f80, Expand);
784 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
785 setOperationAction(ISD::FMA, MVT::f80, Expand);
788 // Always use a library call for pow.
789 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
790 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
791 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
793 setOperationAction(ISD::FLOG, MVT::f80, Expand);
794 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
795 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
796 setOperationAction(ISD::FEXP, MVT::f80, Expand);
797 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
798 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
799 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
801 // First set operation action for all vector types to either promote
802 // (for widening) or expand (for scalarization). Then we will selectively
803 // turn on ones that can be effectively codegen'd.
804 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 setOperationAction(ISD::ADD , VT, Expand);
808 setOperationAction(ISD::SUB , VT, Expand);
809 setOperationAction(ISD::FADD, VT, Expand);
810 setOperationAction(ISD::FNEG, VT, Expand);
811 setOperationAction(ISD::FSUB, VT, Expand);
812 setOperationAction(ISD::MUL , VT, Expand);
813 setOperationAction(ISD::FMUL, VT, Expand);
814 setOperationAction(ISD::SDIV, VT, Expand);
815 setOperationAction(ISD::UDIV, VT, Expand);
816 setOperationAction(ISD::FDIV, VT, Expand);
817 setOperationAction(ISD::SREM, VT, Expand);
818 setOperationAction(ISD::UREM, VT, Expand);
819 setOperationAction(ISD::LOAD, VT, Expand);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
823 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
824 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::FABS, VT, Expand);
826 setOperationAction(ISD::FSIN, VT, Expand);
827 setOperationAction(ISD::FSINCOS, VT, Expand);
828 setOperationAction(ISD::FCOS, VT, Expand);
829 setOperationAction(ISD::FSINCOS, VT, Expand);
830 setOperationAction(ISD::FREM, VT, Expand);
831 setOperationAction(ISD::FMA, VT, Expand);
832 setOperationAction(ISD::FPOWI, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
835 setOperationAction(ISD::FFLOOR, VT, Expand);
836 setOperationAction(ISD::FCEIL, VT, Expand);
837 setOperationAction(ISD::FTRUNC, VT, Expand);
838 setOperationAction(ISD::FRINT, VT, Expand);
839 setOperationAction(ISD::FNEARBYINT, VT, Expand);
840 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
841 setOperationAction(ISD::MULHS, VT, Expand);
842 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
843 setOperationAction(ISD::MULHU, VT, Expand);
844 setOperationAction(ISD::SDIVREM, VT, Expand);
845 setOperationAction(ISD::UDIVREM, VT, Expand);
846 setOperationAction(ISD::FPOW, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
850 setOperationAction(ISD::CTLZ, VT, Expand);
851 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
852 setOperationAction(ISD::SHL, VT, Expand);
853 setOperationAction(ISD::SRA, VT, Expand);
854 setOperationAction(ISD::SRL, VT, Expand);
855 setOperationAction(ISD::ROTL, VT, Expand);
856 setOperationAction(ISD::ROTR, VT, Expand);
857 setOperationAction(ISD::BSWAP, VT, Expand);
858 setOperationAction(ISD::SETCC, VT, Expand);
859 setOperationAction(ISD::FLOG, VT, Expand);
860 setOperationAction(ISD::FLOG2, VT, Expand);
861 setOperationAction(ISD::FLOG10, VT, Expand);
862 setOperationAction(ISD::FEXP, VT, Expand);
863 setOperationAction(ISD::FEXP2, VT, Expand);
864 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
865 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
866 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
867 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
869 setOperationAction(ISD::TRUNCATE, VT, Expand);
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
871 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
872 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
873 setOperationAction(ISD::VSELECT, VT, Expand);
874 setOperationAction(ISD::SELECT_CC, VT, Expand);
875 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
876 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
877 setTruncStoreAction(VT,
878 (MVT::SimpleValueType)InnerVT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
882 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
883 // we have to deal with them whether we ask for Expansion or not. Setting
884 // Expand causes its own optimisation problems though, so leave them legal.
885 if (VT.getVectorElementType() == MVT::i1)
886 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
889 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
890 // with -msoft-float, disable use of MMX as well.
891 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
892 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
893 // No operations on x86mmx supported, everything uses intrinsics.
896 // MMX-sized vectors (other than x86mmx) are expected to be expanded
897 // into smaller operations.
898 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
899 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
900 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
901 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
902 setOperationAction(ISD::AND, MVT::v8i8, Expand);
903 setOperationAction(ISD::AND, MVT::v4i16, Expand);
904 setOperationAction(ISD::AND, MVT::v2i32, Expand);
905 setOperationAction(ISD::AND, MVT::v1i64, Expand);
906 setOperationAction(ISD::OR, MVT::v8i8, Expand);
907 setOperationAction(ISD::OR, MVT::v4i16, Expand);
908 setOperationAction(ISD::OR, MVT::v2i32, Expand);
909 setOperationAction(ISD::OR, MVT::v1i64, Expand);
910 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
911 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
912 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
913 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
914 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
919 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
920 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
921 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
922 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
923 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
924 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
925 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
929 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
931 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
932 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
933 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
934 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
935 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
936 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
937 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
938 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
939 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
940 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
942 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
943 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
946 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
947 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
949 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
950 // registers cannot be used even for integer operations.
951 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
952 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
953 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
954 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
956 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
957 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
958 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
959 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
960 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
961 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
962 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
963 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
964 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
965 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
966 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
967 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
968 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
969 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
971 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
972 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
973 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
974 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
975 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
976 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
977 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
979 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
980 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
981 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
982 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
984 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
990 // Only provide customized ctpop vector bit twiddling for vector types we
991 // know to perform better than using the popcnt instructions on each vector
992 // element. If popcnt isn't supported, always provide the custom version.
993 if (!Subtarget->hasPOPCNT()) {
994 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
995 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
998 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
999 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1000 MVT VT = (MVT::SimpleValueType)i;
1001 // Do not attempt to custom lower non-power-of-2 vectors
1002 if (!isPowerOf2_32(VT.getVectorNumElements()))
1004 // Do not attempt to custom lower non-128-bit vectors
1005 if (!VT.is128BitVector())
1007 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1008 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1009 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1012 // We support custom legalizing of sext and anyext loads for specific
1013 // memory vector types which we can load as a scalar (or sequence of
1014 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1015 // loads these must work with a single scalar load.
1016 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1017 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1018 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1022 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1026 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1027 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1028 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1029 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1030 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1031 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1033 if (Subtarget->is64Bit()) {
1034 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1035 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1038 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1039 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1040 MVT VT = (MVT::SimpleValueType)i;
1042 // Do not attempt to promote non-128-bit vectors
1043 if (!VT.is128BitVector())
1046 setOperationAction(ISD::AND, VT, Promote);
1047 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1048 setOperationAction(ISD::OR, VT, Promote);
1049 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1050 setOperationAction(ISD::XOR, VT, Promote);
1051 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1052 setOperationAction(ISD::LOAD, VT, Promote);
1053 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1054 setOperationAction(ISD::SELECT, VT, Promote);
1055 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1058 // Custom lower v2i64 and v2f64 selects.
1059 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1060 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1061 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1064 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1065 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1067 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1068 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1069 // As there is no 64-bit GPR available, we need build a special custom
1070 // sequence to convert from v2i32 to v2f32.
1071 if (!Subtarget->is64Bit())
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1074 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1075 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1077 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1079 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1080 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1081 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1084 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1085 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1086 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1087 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1088 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1089 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1090 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1096 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1098 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1099 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1100 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1107 // FIXME: Do we need to handle scalar-to-vector here?
1108 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1110 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1111 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1112 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1113 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1114 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1115 // There is no BLENDI for byte vectors. We don't need to custom lower
1116 // some vselects for now.
1117 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1119 // SSE41 brings specific instructions for doing vector sign extend even in
1120 // cases where we don't have SRA.
1121 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1122 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1123 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1125 // i8 and i16 vectors are custom because the source register and source
1126 // source memory operand types are not the same width. f32 vectors are
1127 // custom since the immediate controlling the insert encodes additional
1129 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1130 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1131 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1132 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1134 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1139 // FIXME: these should be Legal, but that's only for the case where
1140 // the index is constant. For now custom expand to deal with that.
1141 if (Subtarget->is64Bit()) {
1142 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1147 if (Subtarget->hasSSE2()) {
1148 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1149 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1151 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1152 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1154 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1155 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1157 // In the customized shift lowering, the legal cases in AVX2 will be
1159 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1160 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1162 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1163 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1165 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1168 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1169 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1171 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1172 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1173 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1174 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1176 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1177 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1178 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1180 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1191 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1193 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1204 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1206 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1207 // even though v8i16 is a legal type.
1208 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1209 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1210 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1212 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1213 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1214 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1216 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1217 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1219 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1221 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1225 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1233 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1235 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1236 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1237 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1239 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1240 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1241 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1242 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1246 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1247 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1248 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1249 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1250 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1251 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1252 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1253 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1254 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1255 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1257 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1258 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1259 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1260 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1261 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1262 setOperationAction(ISD::FMA, MVT::f32, Legal);
1263 setOperationAction(ISD::FMA, MVT::f64, Legal);
1266 if (Subtarget->hasInt256()) {
1267 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1268 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1269 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1270 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1272 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1273 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1274 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1275 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1277 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1278 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1279 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1280 // Don't lower v32i8 because there is no 128-bit byte mul
1282 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1283 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1284 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1285 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1287 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1288 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1290 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1291 // when we have a 256bit-wide blend with immediate.
1292 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1294 // Only provide customized ctpop vector bit twiddling for vector types we
1295 // know to perform better than using the popcnt instructions on each
1296 // vector element. If popcnt isn't supported, always provide the custom
1298 if (!Subtarget->hasPOPCNT())
1299 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1301 // Custom CTPOP always performs better on natively supported v8i32
1302 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1304 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1305 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1306 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1307 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1309 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1310 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1311 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1312 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1314 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1315 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1317 // Don't lower v32i8 because there is no 128-bit byte mul
1320 // In the customized shift lowering, the legal cases in AVX2 will be
1322 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1323 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1325 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1326 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1328 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1330 // Custom lower several nodes for 256-bit types.
1331 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1332 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1333 MVT VT = (MVT::SimpleValueType)i;
1335 if (VT.getScalarSizeInBits() >= 32) {
1336 setOperationAction(ISD::MLOAD, VT, Legal);
1337 setOperationAction(ISD::MSTORE, VT, Legal);
1339 // Extract subvector is special because the value type
1340 // (result) is 128-bit but the source is 256-bit wide.
1341 if (VT.is128BitVector()) {
1342 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1344 // Do not attempt to custom lower other non-256-bit vectors
1345 if (!VT.is256BitVector())
1348 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1349 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1350 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1351 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1352 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1353 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1354 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1357 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1358 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1359 MVT VT = (MVT::SimpleValueType)i;
1361 // Do not attempt to promote non-256-bit vectors
1362 if (!VT.is256BitVector())
1365 setOperationAction(ISD::AND, VT, Promote);
1366 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1367 setOperationAction(ISD::OR, VT, Promote);
1368 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1369 setOperationAction(ISD::XOR, VT, Promote);
1370 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1371 setOperationAction(ISD::LOAD, VT, Promote);
1372 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1373 setOperationAction(ISD::SELECT, VT, Promote);
1374 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1378 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1379 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1380 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1381 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1382 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1384 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1385 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1386 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1388 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1389 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1390 setOperationAction(ISD::XOR, MVT::i1, Legal);
1391 setOperationAction(ISD::OR, MVT::i1, Legal);
1392 setOperationAction(ISD::AND, MVT::i1, Legal);
1393 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1394 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1395 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1396 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1397 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1398 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1400 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1401 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1402 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1404 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1405 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1407 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1408 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1409 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1410 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1411 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1412 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1413 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1414 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1416 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1417 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1418 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1420 if (Subtarget->is64Bit()) {
1421 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1422 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1427 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1428 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1429 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1430 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1431 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1432 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1433 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1434 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1435 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1436 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1437 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1438 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1439 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1441 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1442 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1443 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1444 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1445 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1446 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1447 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1448 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1450 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1451 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1452 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1453 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1460 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1462 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1463 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1465 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1468 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1470 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1472 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1477 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1478 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1480 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1481 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1483 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1485 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1486 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1488 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1491 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1492 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1494 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1495 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1496 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1497 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1498 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1499 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1501 if (Subtarget->hasCDI()) {
1502 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1503 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1506 // Custom lower several nodes.
1507 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1508 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1509 MVT VT = (MVT::SimpleValueType)i;
1511 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1512 // Extract subvector is special because the value type
1513 // (result) is 256/128-bit but the source is 512-bit wide.
1514 if (VT.is128BitVector() || VT.is256BitVector()) {
1515 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1517 if (VT.getVectorElementType() == MVT::i1)
1518 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1520 // Do not attempt to custom lower other non-512-bit vectors
1521 if (!VT.is512BitVector())
1524 if ( EltSize >= 32) {
1525 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1526 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1527 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1528 setOperationAction(ISD::VSELECT, VT, Legal);
1529 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1530 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1531 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1532 setOperationAction(ISD::MLOAD, VT, Legal);
1533 setOperationAction(ISD::MSTORE, VT, Legal);
1536 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1537 MVT VT = (MVT::SimpleValueType)i;
1539 // Do not attempt to promote non-256-bit vectors.
1540 if (!VT.is512BitVector())
1543 setOperationAction(ISD::SELECT, VT, Promote);
1544 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1548 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1549 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1550 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1552 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1553 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1555 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1556 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1557 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1558 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1559 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1560 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1561 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1562 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1563 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1565 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1566 const MVT VT = (MVT::SimpleValueType)i;
1568 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1570 // Do not attempt to promote non-256-bit vectors.
1571 if (!VT.is512BitVector())
1575 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1576 setOperationAction(ISD::VSELECT, VT, Legal);
1581 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1582 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1583 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1585 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1586 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1587 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1589 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1590 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1591 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1592 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1593 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1594 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1597 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1598 // of this type with custom code.
1599 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1600 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1601 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1605 // We want to custom lower some of our intrinsics.
1606 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1607 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1608 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1609 if (!Subtarget->is64Bit())
1610 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1612 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1613 // handle type legalization for these operations here.
1615 // FIXME: We really should do custom legalization for addition and
1616 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1617 // than generic legalization for 64-bit multiplication-with-overflow, though.
1618 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1619 // Add/Sub/Mul with overflow operations are custom lowered.
1621 setOperationAction(ISD::SADDO, VT, Custom);
1622 setOperationAction(ISD::UADDO, VT, Custom);
1623 setOperationAction(ISD::SSUBO, VT, Custom);
1624 setOperationAction(ISD::USUBO, VT, Custom);
1625 setOperationAction(ISD::SMULO, VT, Custom);
1626 setOperationAction(ISD::UMULO, VT, Custom);
1630 if (!Subtarget->is64Bit()) {
1631 // These libcalls are not available in 32-bit.
1632 setLibcallName(RTLIB::SHL_I128, nullptr);
1633 setLibcallName(RTLIB::SRL_I128, nullptr);
1634 setLibcallName(RTLIB::SRA_I128, nullptr);
1637 // Combine sin / cos into one node or libcall if possible.
1638 if (Subtarget->hasSinCos()) {
1639 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1640 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1641 if (Subtarget->isTargetDarwin()) {
1642 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1643 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1644 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1645 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1649 if (Subtarget->isTargetWin64()) {
1650 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1651 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1652 setOperationAction(ISD::SREM, MVT::i128, Custom);
1653 setOperationAction(ISD::UREM, MVT::i128, Custom);
1654 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1655 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1658 // We have target-specific dag combine patterns for the following nodes:
1659 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1660 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1661 setTargetDAGCombine(ISD::VSELECT);
1662 setTargetDAGCombine(ISD::SELECT);
1663 setTargetDAGCombine(ISD::SHL);
1664 setTargetDAGCombine(ISD::SRA);
1665 setTargetDAGCombine(ISD::SRL);
1666 setTargetDAGCombine(ISD::OR);
1667 setTargetDAGCombine(ISD::AND);
1668 setTargetDAGCombine(ISD::ADD);
1669 setTargetDAGCombine(ISD::FADD);
1670 setTargetDAGCombine(ISD::FSUB);
1671 setTargetDAGCombine(ISD::FMA);
1672 setTargetDAGCombine(ISD::SUB);
1673 setTargetDAGCombine(ISD::LOAD);
1674 setTargetDAGCombine(ISD::STORE);
1675 setTargetDAGCombine(ISD::ZERO_EXTEND);
1676 setTargetDAGCombine(ISD::ANY_EXTEND);
1677 setTargetDAGCombine(ISD::SIGN_EXTEND);
1678 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1679 setTargetDAGCombine(ISD::TRUNCATE);
1680 setTargetDAGCombine(ISD::SINT_TO_FP);
1681 setTargetDAGCombine(ISD::SETCC);
1682 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1683 setTargetDAGCombine(ISD::BUILD_VECTOR);
1684 if (Subtarget->is64Bit())
1685 setTargetDAGCombine(ISD::MUL);
1686 setTargetDAGCombine(ISD::XOR);
1688 computeRegisterProperties();
1690 // On Darwin, -Os means optimize for size without hurting performance,
1691 // do not reduce the limit.
1692 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1693 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1694 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1695 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1696 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1697 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1698 setPrefLoopAlignment(4); // 2^4 bytes.
1700 // Predictable cmov don't hurt on atom because it's in-order.
1701 PredictableSelectIsExpensive = !Subtarget->isAtom();
1702 EnableExtLdPromotion = true;
1703 setPrefFunctionAlignment(4); // 2^4 bytes.
1705 verifyIntrinsicTables();
1708 // This has so far only been implemented for 64-bit MachO.
1709 bool X86TargetLowering::useLoadStackGuardNode() const {
1710 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1713 TargetLoweringBase::LegalizeTypeAction
1714 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1715 if (ExperimentalVectorWideningLegalization &&
1716 VT.getVectorNumElements() != 1 &&
1717 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1718 return TypeWidenVector;
1720 return TargetLoweringBase::getPreferredVectorAction(VT);
1723 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1725 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1727 const unsigned NumElts = VT.getVectorNumElements();
1728 const EVT EltVT = VT.getVectorElementType();
1729 if (VT.is512BitVector()) {
1730 if (Subtarget->hasAVX512())
1731 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1732 EltVT == MVT::f32 || EltVT == MVT::f64)
1734 case 8: return MVT::v8i1;
1735 case 16: return MVT::v16i1;
1737 if (Subtarget->hasBWI())
1738 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1740 case 32: return MVT::v32i1;
1741 case 64: return MVT::v64i1;
1745 if (VT.is256BitVector() || VT.is128BitVector()) {
1746 if (Subtarget->hasVLX())
1747 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1748 EltVT == MVT::f32 || EltVT == MVT::f64)
1750 case 2: return MVT::v2i1;
1751 case 4: return MVT::v4i1;
1752 case 8: return MVT::v8i1;
1754 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1755 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1757 case 8: return MVT::v8i1;
1758 case 16: return MVT::v16i1;
1759 case 32: return MVT::v32i1;
1763 return VT.changeVectorElementTypeToInteger();
1766 /// Helper for getByValTypeAlignment to determine
1767 /// the desired ByVal argument alignment.
1768 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1771 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1772 if (VTy->getBitWidth() == 128)
1774 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1775 unsigned EltAlign = 0;
1776 getMaxByValAlign(ATy->getElementType(), EltAlign);
1777 if (EltAlign > MaxAlign)
1778 MaxAlign = EltAlign;
1779 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1780 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1781 unsigned EltAlign = 0;
1782 getMaxByValAlign(STy->getElementType(i), EltAlign);
1783 if (EltAlign > MaxAlign)
1784 MaxAlign = EltAlign;
1791 /// Return the desired alignment for ByVal aggregate
1792 /// function arguments in the caller parameter area. For X86, aggregates
1793 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1794 /// are at 4-byte boundaries.
1795 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1796 if (Subtarget->is64Bit()) {
1797 // Max of 8 and alignment of type.
1798 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1805 if (Subtarget->hasSSE1())
1806 getMaxByValAlign(Ty, Align);
1810 /// Returns the target specific optimal type for load
1811 /// and store operations as a result of memset, memcpy, and memmove
1812 /// lowering. If DstAlign is zero that means it's safe to destination
1813 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1814 /// means there isn't a need to check it against alignment requirement,
1815 /// probably because the source does not need to be loaded. If 'IsMemset' is
1816 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1817 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1818 /// source is constant so it does not need to be loaded.
1819 /// It returns EVT::Other if the type should be determined using generic
1820 /// target-independent logic.
1822 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1823 unsigned DstAlign, unsigned SrcAlign,
1824 bool IsMemset, bool ZeroMemset,
1826 MachineFunction &MF) const {
1827 const Function *F = MF.getFunction();
1828 if ((!IsMemset || ZeroMemset) &&
1829 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1830 Attribute::NoImplicitFloat)) {
1832 (Subtarget->isUnalignedMemAccessFast() ||
1833 ((DstAlign == 0 || DstAlign >= 16) &&
1834 (SrcAlign == 0 || SrcAlign >= 16)))) {
1836 if (Subtarget->hasInt256())
1838 if (Subtarget->hasFp256())
1841 if (Subtarget->hasSSE2())
1843 if (Subtarget->hasSSE1())
1845 } else if (!MemcpyStrSrc && Size >= 8 &&
1846 !Subtarget->is64Bit() &&
1847 Subtarget->hasSSE2()) {
1848 // Do not use f64 to lower memcpy if source is string constant. It's
1849 // better to use i32 to avoid the loads.
1853 if (Subtarget->is64Bit() && Size >= 8)
1858 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1860 return X86ScalarSSEf32;
1861 else if (VT == MVT::f64)
1862 return X86ScalarSSEf64;
1867 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1872 *Fast = Subtarget->isUnalignedMemAccessFast();
1876 /// Return the entry encoding for a jump table in the
1877 /// current function. The returned value is a member of the
1878 /// MachineJumpTableInfo::JTEntryKind enum.
1879 unsigned X86TargetLowering::getJumpTableEncoding() const {
1880 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1882 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1883 Subtarget->isPICStyleGOT())
1884 return MachineJumpTableInfo::EK_Custom32;
1886 // Otherwise, use the normal jump table encoding heuristics.
1887 return TargetLowering::getJumpTableEncoding();
1891 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1892 const MachineBasicBlock *MBB,
1893 unsigned uid,MCContext &Ctx) const{
1894 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1895 Subtarget->isPICStyleGOT());
1896 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1898 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1899 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1902 /// Returns relocation base for the given PIC jumptable.
1903 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1904 SelectionDAG &DAG) const {
1905 if (!Subtarget->is64Bit())
1906 // This doesn't have SDLoc associated with it, but is not really the
1907 // same as a Register.
1908 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1912 /// This returns the relocation base for the given PIC jumptable,
1913 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1914 const MCExpr *X86TargetLowering::
1915 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1916 MCContext &Ctx) const {
1917 // X86-64 uses RIP relative addressing based on the jump table label.
1918 if (Subtarget->isPICStyleRIPRel())
1919 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1921 // Otherwise, the reference is relative to the PIC base.
1922 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1925 // FIXME: Why this routine is here? Move to RegInfo!
1926 std::pair<const TargetRegisterClass*, uint8_t>
1927 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1928 const TargetRegisterClass *RRC = nullptr;
1930 switch (VT.SimpleTy) {
1932 return TargetLowering::findRepresentativeClass(VT);
1933 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1934 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1937 RRC = &X86::VR64RegClass;
1939 case MVT::f32: case MVT::f64:
1940 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1941 case MVT::v4f32: case MVT::v2f64:
1942 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1944 RRC = &X86::VR128RegClass;
1947 return std::make_pair(RRC, Cost);
1950 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1951 unsigned &Offset) const {
1952 if (!Subtarget->isTargetLinux())
1955 if (Subtarget->is64Bit()) {
1956 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1958 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1970 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1971 unsigned DestAS) const {
1972 assert(SrcAS != DestAS && "Expected different address spaces!");
1974 return SrcAS < 256 && DestAS < 256;
1977 //===----------------------------------------------------------------------===//
1978 // Return Value Calling Convention Implementation
1979 //===----------------------------------------------------------------------===//
1981 #include "X86GenCallingConv.inc"
1984 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1985 MachineFunction &MF, bool isVarArg,
1986 const SmallVectorImpl<ISD::OutputArg> &Outs,
1987 LLVMContext &Context) const {
1988 SmallVector<CCValAssign, 16> RVLocs;
1989 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1990 return CCInfo.CheckReturn(Outs, RetCC_X86);
1993 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1994 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1999 X86TargetLowering::LowerReturn(SDValue Chain,
2000 CallingConv::ID CallConv, bool isVarArg,
2001 const SmallVectorImpl<ISD::OutputArg> &Outs,
2002 const SmallVectorImpl<SDValue> &OutVals,
2003 SDLoc dl, SelectionDAG &DAG) const {
2004 MachineFunction &MF = DAG.getMachineFunction();
2005 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2007 SmallVector<CCValAssign, 16> RVLocs;
2008 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2009 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2012 SmallVector<SDValue, 6> RetOps;
2013 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2014 // Operand #1 = Bytes To Pop
2015 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2018 // Copy the result values into the output registers.
2019 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2020 CCValAssign &VA = RVLocs[i];
2021 assert(VA.isRegLoc() && "Can only return in registers!");
2022 SDValue ValToCopy = OutVals[i];
2023 EVT ValVT = ValToCopy.getValueType();
2025 // Promote values to the appropriate types.
2026 if (VA.getLocInfo() == CCValAssign::SExt)
2027 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2028 else if (VA.getLocInfo() == CCValAssign::ZExt)
2029 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2030 else if (VA.getLocInfo() == CCValAssign::AExt)
2031 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2032 else if (VA.getLocInfo() == CCValAssign::BCvt)
2033 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2035 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2036 "Unexpected FP-extend for return value.");
2038 // If this is x86-64, and we disabled SSE, we can't return FP values,
2039 // or SSE or MMX vectors.
2040 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2041 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2042 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2043 report_fatal_error("SSE register return with SSE disabled");
2045 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2046 // llvm-gcc has never done it right and no one has noticed, so this
2047 // should be OK for now.
2048 if (ValVT == MVT::f64 &&
2049 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2050 report_fatal_error("SSE2 register return with SSE2 disabled");
2052 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2053 // the RET instruction and handled by the FP Stackifier.
2054 if (VA.getLocReg() == X86::FP0 ||
2055 VA.getLocReg() == X86::FP1) {
2056 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2057 // change the value to the FP stack register class.
2058 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2059 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2060 RetOps.push_back(ValToCopy);
2061 // Don't emit a copytoreg.
2065 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2066 // which is returned in RAX / RDX.
2067 if (Subtarget->is64Bit()) {
2068 if (ValVT == MVT::x86mmx) {
2069 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2070 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2071 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2073 // If we don't have SSE2 available, convert to v4f32 so the generated
2074 // register is legal.
2075 if (!Subtarget->hasSSE2())
2076 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2081 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2082 Flag = Chain.getValue(1);
2083 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2086 // The x86-64 ABIs require that for returning structs by value we copy
2087 // the sret argument into %rax/%eax (depending on ABI) for the return.
2088 // Win32 requires us to put the sret argument to %eax as well.
2089 // We saved the argument into a virtual register in the entry block,
2090 // so now we copy the value out and into %rax/%eax.
2091 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2092 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2093 MachineFunction &MF = DAG.getMachineFunction();
2094 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2095 unsigned Reg = FuncInfo->getSRetReturnReg();
2097 "SRetReturnReg should have been set in LowerFormalArguments().");
2098 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2101 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2102 X86::RAX : X86::EAX;
2103 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2104 Flag = Chain.getValue(1);
2106 // RAX/EAX now acts like a return value.
2107 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2110 RetOps[0] = Chain; // Update chain.
2112 // Add the flag if we have it.
2114 RetOps.push_back(Flag);
2116 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2119 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2120 if (N->getNumValues() != 1)
2122 if (!N->hasNUsesOfValue(1, 0))
2125 SDValue TCChain = Chain;
2126 SDNode *Copy = *N->use_begin();
2127 if (Copy->getOpcode() == ISD::CopyToReg) {
2128 // If the copy has a glue operand, we conservatively assume it isn't safe to
2129 // perform a tail call.
2130 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2132 TCChain = Copy->getOperand(0);
2133 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2136 bool HasRet = false;
2137 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2139 if (UI->getOpcode() != X86ISD::RET_FLAG)
2141 // If we are returning more than one value, we can definitely
2142 // not make a tail call see PR19530
2143 if (UI->getNumOperands() > 4)
2145 if (UI->getNumOperands() == 4 &&
2146 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2159 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2160 ISD::NodeType ExtendKind) const {
2162 // TODO: Is this also valid on 32-bit?
2163 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2164 ReturnMVT = MVT::i8;
2166 ReturnMVT = MVT::i32;
2168 EVT MinVT = getRegisterType(Context, ReturnMVT);
2169 return VT.bitsLT(MinVT) ? MinVT : VT;
2172 /// Lower the result values of a call into the
2173 /// appropriate copies out of appropriate physical registers.
2176 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2177 CallingConv::ID CallConv, bool isVarArg,
2178 const SmallVectorImpl<ISD::InputArg> &Ins,
2179 SDLoc dl, SelectionDAG &DAG,
2180 SmallVectorImpl<SDValue> &InVals) const {
2182 // Assign locations to each value returned by this call.
2183 SmallVector<CCValAssign, 16> RVLocs;
2184 bool Is64Bit = Subtarget->is64Bit();
2185 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2187 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2189 // Copy all of the result registers out of their specified physreg.
2190 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2191 CCValAssign &VA = RVLocs[i];
2192 EVT CopyVT = VA.getValVT();
2194 // If this is x86-64, and we disabled SSE, we can't return FP values
2195 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2196 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2197 report_fatal_error("SSE register return with SSE disabled");
2200 // If we prefer to use the value in xmm registers, copy it out as f80 and
2201 // use a truncate to move it from fp stack reg to xmm reg.
2202 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2203 isScalarFPTypeInSSEReg(VA.getValVT()))
2206 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2207 CopyVT, InFlag).getValue(1);
2208 SDValue Val = Chain.getValue(0);
2210 if (CopyVT != VA.getValVT())
2211 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2212 // This truncation won't change the value.
2213 DAG.getIntPtrConstant(1));
2215 InFlag = Chain.getValue(2);
2216 InVals.push_back(Val);
2222 //===----------------------------------------------------------------------===//
2223 // C & StdCall & Fast Calling Convention implementation
2224 //===----------------------------------------------------------------------===//
2225 // StdCall calling convention seems to be standard for many Windows' API
2226 // routines and around. It differs from C calling convention just a little:
2227 // callee should clean up the stack, not caller. Symbols should be also
2228 // decorated in some fancy way :) It doesn't support any vector arguments.
2229 // For info on fast calling convention see Fast Calling Convention (tail call)
2230 // implementation LowerX86_32FastCCCallTo.
2232 /// CallIsStructReturn - Determines whether a call uses struct return
2234 enum StructReturnType {
2239 static StructReturnType
2240 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2242 return NotStructReturn;
2244 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2245 if (!Flags.isSRet())
2246 return NotStructReturn;
2247 if (Flags.isInReg())
2248 return RegStructReturn;
2249 return StackStructReturn;
2252 /// Determines whether a function uses struct return semantics.
2253 static StructReturnType
2254 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2256 return NotStructReturn;
2258 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2259 if (!Flags.isSRet())
2260 return NotStructReturn;
2261 if (Flags.isInReg())
2262 return RegStructReturn;
2263 return StackStructReturn;
2266 /// Make a copy of an aggregate at address specified by "Src" to address
2267 /// "Dst" with size and alignment information specified by the specific
2268 /// parameter attribute. The copy will be passed as a byval function parameter.
2270 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2271 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2273 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2275 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2276 /*isVolatile*/false, /*AlwaysInline=*/true,
2277 MachinePointerInfo(), MachinePointerInfo());
2280 /// Return true if the calling convention is one that
2281 /// supports tail call optimization.
2282 static bool IsTailCallConvention(CallingConv::ID CC) {
2283 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2284 CC == CallingConv::HiPE);
2287 /// \brief Return true if the calling convention is a C calling convention.
2288 static bool IsCCallConvention(CallingConv::ID CC) {
2289 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2290 CC == CallingConv::X86_64_SysV);
2293 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2294 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2298 CallingConv::ID CalleeCC = CS.getCallingConv();
2299 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2305 /// Return true if the function is being made into
2306 /// a tailcall target by changing its ABI.
2307 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2308 bool GuaranteedTailCallOpt) {
2309 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2313 X86TargetLowering::LowerMemArgument(SDValue Chain,
2314 CallingConv::ID CallConv,
2315 const SmallVectorImpl<ISD::InputArg> &Ins,
2316 SDLoc dl, SelectionDAG &DAG,
2317 const CCValAssign &VA,
2318 MachineFrameInfo *MFI,
2320 // Create the nodes corresponding to a load from this parameter slot.
2321 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2322 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2323 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2324 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2327 // If value is passed by pointer we have address passed instead of the value
2329 if (VA.getLocInfo() == CCValAssign::Indirect)
2330 ValVT = VA.getLocVT();
2332 ValVT = VA.getValVT();
2334 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2335 // changed with more analysis.
2336 // In case of tail call optimization mark all arguments mutable. Since they
2337 // could be overwritten by lowering of arguments in case of a tail call.
2338 if (Flags.isByVal()) {
2339 unsigned Bytes = Flags.getByValSize();
2340 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2341 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2342 return DAG.getFrameIndex(FI, getPointerTy());
2344 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2345 VA.getLocMemOffset(), isImmutable);
2346 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2347 return DAG.getLoad(ValVT, dl, Chain, FIN,
2348 MachinePointerInfo::getFixedStack(FI),
2349 false, false, false, 0);
2353 // FIXME: Get this from tablegen.
2354 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2355 const X86Subtarget *Subtarget) {
2356 assert(Subtarget->is64Bit());
2358 if (Subtarget->isCallingConvWin64(CallConv)) {
2359 static const MCPhysReg GPR64ArgRegsWin64[] = {
2360 X86::RCX, X86::RDX, X86::R8, X86::R9
2362 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2365 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2366 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2368 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2371 // FIXME: Get this from tablegen.
2372 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2373 CallingConv::ID CallConv,
2374 const X86Subtarget *Subtarget) {
2375 assert(Subtarget->is64Bit());
2376 if (Subtarget->isCallingConvWin64(CallConv)) {
2377 // The XMM registers which might contain var arg parameters are shadowed
2378 // in their paired GPR. So we only need to save the GPR to their home
2380 // TODO: __vectorcall will change this.
2384 const Function *Fn = MF.getFunction();
2385 bool NoImplicitFloatOps = Fn->getAttributes().
2386 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2387 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2388 "SSE register cannot be used when SSE is disabled!");
2389 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2390 !Subtarget->hasSSE1())
2391 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2395 static const MCPhysReg XMMArgRegs64Bit[] = {
2396 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2397 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2399 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2403 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2404 CallingConv::ID CallConv,
2406 const SmallVectorImpl<ISD::InputArg> &Ins,
2409 SmallVectorImpl<SDValue> &InVals)
2411 MachineFunction &MF = DAG.getMachineFunction();
2412 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2414 const Function* Fn = MF.getFunction();
2415 if (Fn->hasExternalLinkage() &&
2416 Subtarget->isTargetCygMing() &&
2417 Fn->getName() == "main")
2418 FuncInfo->setForceFramePointer(true);
2420 MachineFrameInfo *MFI = MF.getFrameInfo();
2421 bool Is64Bit = Subtarget->is64Bit();
2422 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2424 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2425 "Var args not supported with calling convention fastcc, ghc or hipe");
2427 // Assign locations to all of the incoming arguments.
2428 SmallVector<CCValAssign, 16> ArgLocs;
2429 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2431 // Allocate shadow area for Win64
2433 CCInfo.AllocateStack(32, 8);
2435 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2437 unsigned LastVal = ~0U;
2439 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2440 CCValAssign &VA = ArgLocs[i];
2441 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2443 assert(VA.getValNo() != LastVal &&
2444 "Don't support value assigned to multiple locs yet");
2446 LastVal = VA.getValNo();
2448 if (VA.isRegLoc()) {
2449 EVT RegVT = VA.getLocVT();
2450 const TargetRegisterClass *RC;
2451 if (RegVT == MVT::i32)
2452 RC = &X86::GR32RegClass;
2453 else if (Is64Bit && RegVT == MVT::i64)
2454 RC = &X86::GR64RegClass;
2455 else if (RegVT == MVT::f32)
2456 RC = &X86::FR32RegClass;
2457 else if (RegVT == MVT::f64)
2458 RC = &X86::FR64RegClass;
2459 else if (RegVT.is512BitVector())
2460 RC = &X86::VR512RegClass;
2461 else if (RegVT.is256BitVector())
2462 RC = &X86::VR256RegClass;
2463 else if (RegVT.is128BitVector())
2464 RC = &X86::VR128RegClass;
2465 else if (RegVT == MVT::x86mmx)
2466 RC = &X86::VR64RegClass;
2467 else if (RegVT == MVT::i1)
2468 RC = &X86::VK1RegClass;
2469 else if (RegVT == MVT::v8i1)
2470 RC = &X86::VK8RegClass;
2471 else if (RegVT == MVT::v16i1)
2472 RC = &X86::VK16RegClass;
2473 else if (RegVT == MVT::v32i1)
2474 RC = &X86::VK32RegClass;
2475 else if (RegVT == MVT::v64i1)
2476 RC = &X86::VK64RegClass;
2478 llvm_unreachable("Unknown argument type!");
2480 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2481 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2483 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2484 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2486 if (VA.getLocInfo() == CCValAssign::SExt)
2487 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2488 DAG.getValueType(VA.getValVT()));
2489 else if (VA.getLocInfo() == CCValAssign::ZExt)
2490 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2491 DAG.getValueType(VA.getValVT()));
2492 else if (VA.getLocInfo() == CCValAssign::BCvt)
2493 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2495 if (VA.isExtInLoc()) {
2496 // Handle MMX values passed in XMM regs.
2497 if (RegVT.isVector())
2498 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2500 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2503 assert(VA.isMemLoc());
2504 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2507 // If value is passed via pointer - do a load.
2508 if (VA.getLocInfo() == CCValAssign::Indirect)
2509 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2510 MachinePointerInfo(), false, false, false, 0);
2512 InVals.push_back(ArgValue);
2515 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2516 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2517 // The x86-64 ABIs require that for returning structs by value we copy
2518 // the sret argument into %rax/%eax (depending on ABI) for the return.
2519 // Win32 requires us to put the sret argument to %eax as well.
2520 // Save the argument into a virtual register so that we can access it
2521 // from the return points.
2522 if (Ins[i].Flags.isSRet()) {
2523 unsigned Reg = FuncInfo->getSRetReturnReg();
2525 MVT PtrTy = getPointerTy();
2526 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2527 FuncInfo->setSRetReturnReg(Reg);
2529 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2530 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2536 unsigned StackSize = CCInfo.getNextStackOffset();
2537 // Align stack specially for tail calls.
2538 if (FuncIsMadeTailCallSafe(CallConv,
2539 MF.getTarget().Options.GuaranteedTailCallOpt))
2540 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2542 // If the function takes variable number of arguments, make a frame index for
2543 // the start of the first vararg value... for expansion of llvm.va_start. We
2544 // can skip this if there are no va_start calls.
2545 if (MFI->hasVAStart() &&
2546 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2547 CallConv != CallingConv::X86_ThisCall))) {
2548 FuncInfo->setVarArgsFrameIndex(
2549 MFI->CreateFixedObject(1, StackSize, true));
2552 // Figure out if XMM registers are in use.
2553 assert(!(MF.getTarget().Options.UseSoftFloat &&
2554 Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
2555 Attribute::NoImplicitFloat)) &&
2556 "SSE register cannot be used when SSE is disabled!");
2558 // 64-bit calling conventions support varargs and register parameters, so we
2559 // have to do extra work to spill them in the prologue.
2560 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2561 // Find the first unallocated argument registers.
2562 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2563 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2564 unsigned NumIntRegs =
2565 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2566 unsigned NumXMMRegs =
2567 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2568 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2569 "SSE register cannot be used when SSE is disabled!");
2571 // Gather all the live in physical registers.
2572 SmallVector<SDValue, 6> LiveGPRs;
2573 SmallVector<SDValue, 8> LiveXMMRegs;
2575 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2576 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2578 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2580 if (!ArgXMMs.empty()) {
2581 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2582 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2583 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2584 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2585 LiveXMMRegs.push_back(
2586 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2591 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2592 // Get to the caller-allocated home save location. Add 8 to account
2593 // for the return address.
2594 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2595 FuncInfo->setRegSaveFrameIndex(
2596 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2597 // Fixup to set vararg frame on shadow area (4 x i64).
2599 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2601 // For X86-64, if there are vararg parameters that are passed via
2602 // registers, then we must store them to their spots on the stack so
2603 // they may be loaded by deferencing the result of va_next.
2604 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2605 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2606 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2607 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2610 // Store the integer parameter registers.
2611 SmallVector<SDValue, 8> MemOps;
2612 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2614 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2615 for (SDValue Val : LiveGPRs) {
2616 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2617 DAG.getIntPtrConstant(Offset));
2619 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2620 MachinePointerInfo::getFixedStack(
2621 FuncInfo->getRegSaveFrameIndex(), Offset),
2623 MemOps.push_back(Store);
2627 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2628 // Now store the XMM (fp + vector) parameter registers.
2629 SmallVector<SDValue, 12> SaveXMMOps;
2630 SaveXMMOps.push_back(Chain);
2631 SaveXMMOps.push_back(ALVal);
2632 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2633 FuncInfo->getRegSaveFrameIndex()));
2634 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2635 FuncInfo->getVarArgsFPOffset()));
2636 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2638 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2639 MVT::Other, SaveXMMOps));
2642 if (!MemOps.empty())
2643 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2646 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2647 // Find the largest legal vector type.
2648 MVT VecVT = MVT::Other;
2649 // FIXME: Only some x86_32 calling conventions support AVX512.
2650 if (Subtarget->hasAVX512() &&
2651 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2652 CallConv == CallingConv::Intel_OCL_BI)))
2653 VecVT = MVT::v16f32;
2654 else if (Subtarget->hasAVX())
2656 else if (Subtarget->hasSSE2())
2659 // We forward some GPRs and some vector types.
2660 SmallVector<MVT, 2> RegParmTypes;
2661 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2662 RegParmTypes.push_back(IntVT);
2663 if (VecVT != MVT::Other)
2664 RegParmTypes.push_back(VecVT);
2666 // Compute the set of forwarded registers. The rest are scratch.
2667 SmallVectorImpl<ForwardedRegister> &Forwards =
2668 FuncInfo->getForwardedMustTailRegParms();
2669 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2671 // Conservatively forward AL on x86_64, since it might be used for varargs.
2672 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2673 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2674 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2677 // Copy all forwards from physical to virtual registers.
2678 for (ForwardedRegister &F : Forwards) {
2679 // FIXME: Can we use a less constrained schedule?
2680 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2681 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2682 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2686 // Some CCs need callee pop.
2687 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2688 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2689 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2691 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2692 // If this is an sret function, the return should pop the hidden pointer.
2693 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2694 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2695 argsAreStructReturn(Ins) == StackStructReturn)
2696 FuncInfo->setBytesToPopOnReturn(4);
2700 // RegSaveFrameIndex is X86-64 only.
2701 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2702 if (CallConv == CallingConv::X86_FastCall ||
2703 CallConv == CallingConv::X86_ThisCall)
2704 // fastcc functions can't have varargs.
2705 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2708 FuncInfo->setArgumentStackSize(StackSize);
2714 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2715 SDValue StackPtr, SDValue Arg,
2716 SDLoc dl, SelectionDAG &DAG,
2717 const CCValAssign &VA,
2718 ISD::ArgFlagsTy Flags) const {
2719 unsigned LocMemOffset = VA.getLocMemOffset();
2720 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2721 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2722 if (Flags.isByVal())
2723 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2725 return DAG.getStore(Chain, dl, Arg, PtrOff,
2726 MachinePointerInfo::getStack(LocMemOffset),
2730 /// Emit a load of return address if tail call
2731 /// optimization is performed and it is required.
2733 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2734 SDValue &OutRetAddr, SDValue Chain,
2735 bool IsTailCall, bool Is64Bit,
2736 int FPDiff, SDLoc dl) const {
2737 // Adjust the Return address stack slot.
2738 EVT VT = getPointerTy();
2739 OutRetAddr = getReturnAddressFrameIndex(DAG);
2741 // Load the "old" Return address.
2742 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2743 false, false, false, 0);
2744 return SDValue(OutRetAddr.getNode(), 1);
2747 /// Emit a store of the return address if tail call
2748 /// optimization is performed and it is required (FPDiff!=0).
2749 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2750 SDValue Chain, SDValue RetAddrFrIdx,
2751 EVT PtrVT, unsigned SlotSize,
2752 int FPDiff, SDLoc dl) {
2753 // Store the return address to the appropriate stack slot.
2754 if (!FPDiff) return Chain;
2755 // Calculate the new stack slot for the return address.
2756 int NewReturnAddrFI =
2757 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2759 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2760 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2761 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2767 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2768 SmallVectorImpl<SDValue> &InVals) const {
2769 SelectionDAG &DAG = CLI.DAG;
2771 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2772 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2773 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2774 SDValue Chain = CLI.Chain;
2775 SDValue Callee = CLI.Callee;
2776 CallingConv::ID CallConv = CLI.CallConv;
2777 bool &isTailCall = CLI.IsTailCall;
2778 bool isVarArg = CLI.IsVarArg;
2780 MachineFunction &MF = DAG.getMachineFunction();
2781 bool Is64Bit = Subtarget->is64Bit();
2782 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2783 StructReturnType SR = callIsStructReturn(Outs);
2784 bool IsSibcall = false;
2785 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2787 if (MF.getTarget().Options.DisableTailCalls)
2790 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2792 // Force this to be a tail call. The verifier rules are enough to ensure
2793 // that we can lower this successfully without moving the return address
2796 } else if (isTailCall) {
2797 // Check if it's really possible to do a tail call.
2798 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2799 isVarArg, SR != NotStructReturn,
2800 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2801 Outs, OutVals, Ins, DAG);
2803 // Sibcalls are automatically detected tailcalls which do not require
2805 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2812 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2813 "Var args not supported with calling convention fastcc, ghc or hipe");
2815 // Analyze operands of the call, assigning locations to each operand.
2816 SmallVector<CCValAssign, 16> ArgLocs;
2817 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2819 // Allocate shadow area for Win64
2821 CCInfo.AllocateStack(32, 8);
2823 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2825 // Get a count of how many bytes are to be pushed on the stack.
2826 unsigned NumBytes = CCInfo.getNextStackOffset();
2828 // This is a sibcall. The memory operands are available in caller's
2829 // own caller's stack.
2831 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2832 IsTailCallConvention(CallConv))
2833 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2836 if (isTailCall && !IsSibcall && !IsMustTail) {
2837 // Lower arguments at fp - stackoffset + fpdiff.
2838 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2840 FPDiff = NumBytesCallerPushed - NumBytes;
2842 // Set the delta of movement of the returnaddr stackslot.
2843 // But only set if delta is greater than previous delta.
2844 if (FPDiff < X86Info->getTCReturnAddrDelta())
2845 X86Info->setTCReturnAddrDelta(FPDiff);
2848 unsigned NumBytesToPush = NumBytes;
2849 unsigned NumBytesToPop = NumBytes;
2851 // If we have an inalloca argument, all stack space has already been allocated
2852 // for us and be right at the top of the stack. We don't support multiple
2853 // arguments passed in memory when using inalloca.
2854 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2856 if (!ArgLocs.back().isMemLoc())
2857 report_fatal_error("cannot use inalloca attribute on a register "
2859 if (ArgLocs.back().getLocMemOffset() != 0)
2860 report_fatal_error("any parameter with the inalloca attribute must be "
2861 "the only memory argument");
2865 Chain = DAG.getCALLSEQ_START(
2866 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2868 SDValue RetAddrFrIdx;
2869 // Load return address for tail calls.
2870 if (isTailCall && FPDiff)
2871 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2872 Is64Bit, FPDiff, dl);
2874 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2875 SmallVector<SDValue, 8> MemOpChains;
2878 // Walk the register/memloc assignments, inserting copies/loads. In the case
2879 // of tail call optimization arguments are handle later.
2880 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2881 DAG.getSubtarget().getRegisterInfo());
2882 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2883 // Skip inalloca arguments, they have already been written.
2884 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2885 if (Flags.isInAlloca())
2888 CCValAssign &VA = ArgLocs[i];
2889 EVT RegVT = VA.getLocVT();
2890 SDValue Arg = OutVals[i];
2891 bool isByVal = Flags.isByVal();
2893 // Promote the value if needed.
2894 switch (VA.getLocInfo()) {
2895 default: llvm_unreachable("Unknown loc info!");
2896 case CCValAssign::Full: break;
2897 case CCValAssign::SExt:
2898 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2900 case CCValAssign::ZExt:
2901 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2903 case CCValAssign::AExt:
2904 if (RegVT.is128BitVector()) {
2905 // Special case: passing MMX values in XMM registers.
2906 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2907 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2908 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2910 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2912 case CCValAssign::BCvt:
2913 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2915 case CCValAssign::Indirect: {
2916 // Store the argument.
2917 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2918 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2919 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2920 MachinePointerInfo::getFixedStack(FI),
2927 if (VA.isRegLoc()) {
2928 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2929 if (isVarArg && IsWin64) {
2930 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2931 // shadow reg if callee is a varargs function.
2932 unsigned ShadowReg = 0;
2933 switch (VA.getLocReg()) {
2934 case X86::XMM0: ShadowReg = X86::RCX; break;
2935 case X86::XMM1: ShadowReg = X86::RDX; break;
2936 case X86::XMM2: ShadowReg = X86::R8; break;
2937 case X86::XMM3: ShadowReg = X86::R9; break;
2940 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2942 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2943 assert(VA.isMemLoc());
2944 if (!StackPtr.getNode())
2945 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2947 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2948 dl, DAG, VA, Flags));
2952 if (!MemOpChains.empty())
2953 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2955 if (Subtarget->isPICStyleGOT()) {
2956 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2959 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2960 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2962 // If we are tail calling and generating PIC/GOT style code load the
2963 // address of the callee into ECX. The value in ecx is used as target of
2964 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2965 // for tail calls on PIC/GOT architectures. Normally we would just put the
2966 // address of GOT into ebx and then call target@PLT. But for tail calls
2967 // ebx would be restored (since ebx is callee saved) before jumping to the
2970 // Note: The actual moving to ECX is done further down.
2971 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2972 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2973 !G->getGlobal()->hasProtectedVisibility())
2974 Callee = LowerGlobalAddress(Callee, DAG);
2975 else if (isa<ExternalSymbolSDNode>(Callee))
2976 Callee = LowerExternalSymbol(Callee, DAG);
2980 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2981 // From AMD64 ABI document:
2982 // For calls that may call functions that use varargs or stdargs
2983 // (prototype-less calls or calls to functions containing ellipsis (...) in
2984 // the declaration) %al is used as hidden argument to specify the number
2985 // of SSE registers used. The contents of %al do not need to match exactly
2986 // the number of registers, but must be an ubound on the number of SSE
2987 // registers used and is in the range 0 - 8 inclusive.
2989 // Count the number of XMM registers allocated.
2990 static const MCPhysReg XMMArgRegs[] = {
2991 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2992 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2994 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2995 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2996 && "SSE registers cannot be used when SSE is disabled");
2998 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2999 DAG.getConstant(NumXMMRegs, MVT::i8)));
3002 if (isVarArg && IsMustTail) {
3003 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3004 for (const auto &F : Forwards) {
3005 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3006 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3010 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3011 // don't need this because the eligibility check rejects calls that require
3012 // shuffling arguments passed in memory.
3013 if (!IsSibcall && isTailCall) {
3014 // Force all the incoming stack arguments to be loaded from the stack
3015 // before any new outgoing arguments are stored to the stack, because the
3016 // outgoing stack slots may alias the incoming argument stack slots, and
3017 // the alias isn't otherwise explicit. This is slightly more conservative
3018 // than necessary, because it means that each store effectively depends
3019 // on every argument instead of just those arguments it would clobber.
3020 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3022 SmallVector<SDValue, 8> MemOpChains2;
3025 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3026 CCValAssign &VA = ArgLocs[i];
3029 assert(VA.isMemLoc());
3030 SDValue Arg = OutVals[i];
3031 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3032 // Skip inalloca arguments. They don't require any work.
3033 if (Flags.isInAlloca())
3035 // Create frame index.
3036 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3037 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3038 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3039 FIN = DAG.getFrameIndex(FI, getPointerTy());
3041 if (Flags.isByVal()) {
3042 // Copy relative to framepointer.
3043 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3044 if (!StackPtr.getNode())
3045 StackPtr = DAG.getCopyFromReg(Chain, dl,
3046 RegInfo->getStackRegister(),
3048 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3050 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3054 // Store relative to framepointer.
3055 MemOpChains2.push_back(
3056 DAG.getStore(ArgChain, dl, Arg, FIN,
3057 MachinePointerInfo::getFixedStack(FI),
3062 if (!MemOpChains2.empty())
3063 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3065 // Store the return address to the appropriate stack slot.
3066 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3067 getPointerTy(), RegInfo->getSlotSize(),
3071 // Build a sequence of copy-to-reg nodes chained together with token chain
3072 // and flag operands which copy the outgoing args into registers.
3074 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3075 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3076 RegsToPass[i].second, InFlag);
3077 InFlag = Chain.getValue(1);
3080 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3081 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3082 // In the 64-bit large code model, we have to make all calls
3083 // through a register, since the call instruction's 32-bit
3084 // pc-relative offset may not be large enough to hold the whole
3086 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3087 // If the callee is a GlobalAddress node (quite common, every direct call
3088 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3091 // We should use extra load for direct calls to dllimported functions in
3093 const GlobalValue *GV = G->getGlobal();
3094 if (!GV->hasDLLImportStorageClass()) {
3095 unsigned char OpFlags = 0;
3096 bool ExtraLoad = false;
3097 unsigned WrapperKind = ISD::DELETED_NODE;
3099 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3100 // external symbols most go through the PLT in PIC mode. If the symbol
3101 // has hidden or protected visibility, or if it is static or local, then
3102 // we don't need to use the PLT - we can directly call it.
3103 if (Subtarget->isTargetELF() &&
3104 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3105 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3106 OpFlags = X86II::MO_PLT;
3107 } else if (Subtarget->isPICStyleStubAny() &&
3108 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3109 (!Subtarget->getTargetTriple().isMacOSX() ||
3110 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3111 // PC-relative references to external symbols should go through $stub,
3112 // unless we're building with the leopard linker or later, which
3113 // automatically synthesizes these stubs.
3114 OpFlags = X86II::MO_DARWIN_STUB;
3115 } else if (Subtarget->isPICStyleRIPRel() &&
3116 isa<Function>(GV) &&
3117 cast<Function>(GV)->getAttributes().
3118 hasAttribute(AttributeSet::FunctionIndex,
3119 Attribute::NonLazyBind)) {
3120 // If the function is marked as non-lazy, generate an indirect call
3121 // which loads from the GOT directly. This avoids runtime overhead
3122 // at the cost of eager binding (and one extra byte of encoding).
3123 OpFlags = X86II::MO_GOTPCREL;
3124 WrapperKind = X86ISD::WrapperRIP;
3128 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3129 G->getOffset(), OpFlags);
3131 // Add a wrapper if needed.
3132 if (WrapperKind != ISD::DELETED_NODE)
3133 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3134 // Add extra indirection if needed.
3136 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3137 MachinePointerInfo::getGOT(),
3138 false, false, false, 0);
3140 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3141 unsigned char OpFlags = 0;
3143 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3144 // external symbols should go through the PLT.
3145 if (Subtarget->isTargetELF() &&
3146 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3147 OpFlags = X86II::MO_PLT;
3148 } else if (Subtarget->isPICStyleStubAny() &&
3149 (!Subtarget->getTargetTriple().isMacOSX() ||
3150 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3151 // PC-relative references to external symbols should go through $stub,
3152 // unless we're building with the leopard linker or later, which
3153 // automatically synthesizes these stubs.
3154 OpFlags = X86II::MO_DARWIN_STUB;
3157 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3159 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3160 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3161 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3164 // Returns a chain & a flag for retval copy to use.
3165 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3166 SmallVector<SDValue, 8> Ops;
3168 if (!IsSibcall && isTailCall) {
3169 Chain = DAG.getCALLSEQ_END(Chain,
3170 DAG.getIntPtrConstant(NumBytesToPop, true),
3171 DAG.getIntPtrConstant(0, true), InFlag, dl);
3172 InFlag = Chain.getValue(1);
3175 Ops.push_back(Chain);
3176 Ops.push_back(Callee);
3179 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3181 // Add argument registers to the end of the list so that they are known live
3183 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3184 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3185 RegsToPass[i].second.getValueType()));
3187 // Add a register mask operand representing the call-preserved registers.
3188 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3189 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3190 assert(Mask && "Missing call preserved mask for calling convention");
3191 Ops.push_back(DAG.getRegisterMask(Mask));
3193 if (InFlag.getNode())
3194 Ops.push_back(InFlag);
3198 //// If this is the first return lowered for this function, add the regs
3199 //// to the liveout set for the function.
3200 // This isn't right, although it's probably harmless on x86; liveouts
3201 // should be computed from returns not tail calls. Consider a void
3202 // function making a tail call to a function returning int.
3203 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3206 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3207 InFlag = Chain.getValue(1);
3209 // Create the CALLSEQ_END node.
3210 unsigned NumBytesForCalleeToPop;
3211 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3212 DAG.getTarget().Options.GuaranteedTailCallOpt))
3213 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3214 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3215 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3216 SR == StackStructReturn)
3217 // If this is a call to a struct-return function, the callee
3218 // pops the hidden struct pointer, so we have to push it back.
3219 // This is common for Darwin/X86, Linux & Mingw32 targets.
3220 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3221 NumBytesForCalleeToPop = 4;
3223 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3225 // Returns a flag for retval copy to use.
3227 Chain = DAG.getCALLSEQ_END(Chain,
3228 DAG.getIntPtrConstant(NumBytesToPop, true),
3229 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3232 InFlag = Chain.getValue(1);
3235 // Handle result values, copying them out of physregs into vregs that we
3237 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3238 Ins, dl, DAG, InVals);
3241 //===----------------------------------------------------------------------===//
3242 // Fast Calling Convention (tail call) implementation
3243 //===----------------------------------------------------------------------===//
3245 // Like std call, callee cleans arguments, convention except that ECX is
3246 // reserved for storing the tail called function address. Only 2 registers are
3247 // free for argument passing (inreg). Tail call optimization is performed
3249 // * tailcallopt is enabled
3250 // * caller/callee are fastcc
3251 // On X86_64 architecture with GOT-style position independent code only local
3252 // (within module) calls are supported at the moment.
3253 // To keep the stack aligned according to platform abi the function
3254 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3255 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3256 // If a tail called function callee has more arguments than the caller the
3257 // caller needs to make sure that there is room to move the RETADDR to. This is
3258 // achieved by reserving an area the size of the argument delta right after the
3259 // original RETADDR, but before the saved framepointer or the spilled registers
3260 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3272 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3273 /// for a 16 byte align requirement.
3275 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3276 SelectionDAG& DAG) const {
3277 MachineFunction &MF = DAG.getMachineFunction();
3278 const TargetMachine &TM = MF.getTarget();
3279 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3280 TM.getSubtargetImpl()->getRegisterInfo());
3281 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3282 unsigned StackAlignment = TFI.getStackAlignment();
3283 uint64_t AlignMask = StackAlignment - 1;
3284 int64_t Offset = StackSize;
3285 unsigned SlotSize = RegInfo->getSlotSize();
3286 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3287 // Number smaller than 12 so just add the difference.
3288 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3290 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3291 Offset = ((~AlignMask) & Offset) + StackAlignment +
3292 (StackAlignment-SlotSize);
3297 /// MatchingStackOffset - Return true if the given stack call argument is
3298 /// already available in the same position (relatively) of the caller's
3299 /// incoming argument stack.
3301 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3302 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3303 const X86InstrInfo *TII) {
3304 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3306 if (Arg.getOpcode() == ISD::CopyFromReg) {
3307 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3308 if (!TargetRegisterInfo::isVirtualRegister(VR))
3310 MachineInstr *Def = MRI->getVRegDef(VR);
3313 if (!Flags.isByVal()) {
3314 if (!TII->isLoadFromStackSlot(Def, FI))
3317 unsigned Opcode = Def->getOpcode();
3318 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3319 Def->getOperand(1).isFI()) {
3320 FI = Def->getOperand(1).getIndex();
3321 Bytes = Flags.getByValSize();
3325 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3326 if (Flags.isByVal())
3327 // ByVal argument is passed in as a pointer but it's now being
3328 // dereferenced. e.g.
3329 // define @foo(%struct.X* %A) {
3330 // tail call @bar(%struct.X* byval %A)
3333 SDValue Ptr = Ld->getBasePtr();
3334 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3337 FI = FINode->getIndex();
3338 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3339 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3340 FI = FINode->getIndex();
3341 Bytes = Flags.getByValSize();
3345 assert(FI != INT_MAX);
3346 if (!MFI->isFixedObjectIndex(FI))
3348 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3351 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3352 /// for tail call optimization. Targets which want to do tail call
3353 /// optimization should implement this function.
3355 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3356 CallingConv::ID CalleeCC,
3358 bool isCalleeStructRet,
3359 bool isCallerStructRet,
3361 const SmallVectorImpl<ISD::OutputArg> &Outs,
3362 const SmallVectorImpl<SDValue> &OutVals,
3363 const SmallVectorImpl<ISD::InputArg> &Ins,
3364 SelectionDAG &DAG) const {
3365 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3368 // If -tailcallopt is specified, make fastcc functions tail-callable.
3369 const MachineFunction &MF = DAG.getMachineFunction();
3370 const Function *CallerF = MF.getFunction();
3372 // If the function return type is x86_fp80 and the callee return type is not,
3373 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3374 // perform a tailcall optimization here.
3375 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3378 CallingConv::ID CallerCC = CallerF->getCallingConv();
3379 bool CCMatch = CallerCC == CalleeCC;
3380 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3381 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3383 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3384 if (IsTailCallConvention(CalleeCC) && CCMatch)
3389 // Look for obvious safe cases to perform tail call optimization that do not
3390 // require ABI changes. This is what gcc calls sibcall.
3392 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3393 // emit a special epilogue.
3394 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3395 DAG.getSubtarget().getRegisterInfo());
3396 if (RegInfo->needsStackRealignment(MF))
3399 // Also avoid sibcall optimization if either caller or callee uses struct
3400 // return semantics.
3401 if (isCalleeStructRet || isCallerStructRet)
3404 // An stdcall/thiscall caller is expected to clean up its arguments; the
3405 // callee isn't going to do that.
3406 // FIXME: this is more restrictive than needed. We could produce a tailcall
3407 // when the stack adjustment matches. For example, with a thiscall that takes
3408 // only one argument.
3409 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3410 CallerCC == CallingConv::X86_ThisCall))
3413 // Do not sibcall optimize vararg calls unless all arguments are passed via
3415 if (isVarArg && !Outs.empty()) {
3417 // Optimizing for varargs on Win64 is unlikely to be safe without
3418 // additional testing.
3419 if (IsCalleeWin64 || IsCallerWin64)
3422 SmallVector<CCValAssign, 16> ArgLocs;
3423 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3426 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3427 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3428 if (!ArgLocs[i].isRegLoc())
3432 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3433 // stack. Therefore, if it's not used by the call it is not safe to optimize
3434 // this into a sibcall.
3435 bool Unused = false;
3436 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3443 SmallVector<CCValAssign, 16> RVLocs;
3444 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3446 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3447 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3448 CCValAssign &VA = RVLocs[i];
3449 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3454 // If the calling conventions do not match, then we'd better make sure the
3455 // results are returned in the same way as what the caller expects.
3457 SmallVector<CCValAssign, 16> RVLocs1;
3458 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3460 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3462 SmallVector<CCValAssign, 16> RVLocs2;
3463 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3465 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3467 if (RVLocs1.size() != RVLocs2.size())
3469 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3470 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3472 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3474 if (RVLocs1[i].isRegLoc()) {
3475 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3478 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3484 // If the callee takes no arguments then go on to check the results of the
3486 if (!Outs.empty()) {
3487 // Check if stack adjustment is needed. For now, do not do this if any
3488 // argument is passed on the stack.
3489 SmallVector<CCValAssign, 16> ArgLocs;
3490 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3493 // Allocate shadow area for Win64
3495 CCInfo.AllocateStack(32, 8);
3497 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3498 if (CCInfo.getNextStackOffset()) {
3499 MachineFunction &MF = DAG.getMachineFunction();
3500 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3503 // Check if the arguments are already laid out in the right way as
3504 // the caller's fixed stack objects.
3505 MachineFrameInfo *MFI = MF.getFrameInfo();
3506 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3507 const X86InstrInfo *TII =
3508 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3509 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3510 CCValAssign &VA = ArgLocs[i];
3511 SDValue Arg = OutVals[i];
3512 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3513 if (VA.getLocInfo() == CCValAssign::Indirect)
3515 if (!VA.isRegLoc()) {
3516 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3523 // If the tailcall address may be in a register, then make sure it's
3524 // possible to register allocate for it. In 32-bit, the call address can
3525 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3526 // callee-saved registers are restored. These happen to be the same
3527 // registers used to pass 'inreg' arguments so watch out for those.
3528 if (!Subtarget->is64Bit() &&
3529 ((!isa<GlobalAddressSDNode>(Callee) &&
3530 !isa<ExternalSymbolSDNode>(Callee)) ||
3531 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3532 unsigned NumInRegs = 0;
3533 // In PIC we need an extra register to formulate the address computation
3535 unsigned MaxInRegs =
3536 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3538 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3539 CCValAssign &VA = ArgLocs[i];
3542 unsigned Reg = VA.getLocReg();
3545 case X86::EAX: case X86::EDX: case X86::ECX:
3546 if (++NumInRegs == MaxInRegs)
3558 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3559 const TargetLibraryInfo *libInfo) const {
3560 return X86::createFastISel(funcInfo, libInfo);
3563 //===----------------------------------------------------------------------===//
3564 // Other Lowering Hooks
3565 //===----------------------------------------------------------------------===//
3567 static bool MayFoldLoad(SDValue Op) {
3568 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3571 static bool MayFoldIntoStore(SDValue Op) {
3572 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3575 static bool isTargetShuffle(unsigned Opcode) {
3577 default: return false;
3578 case X86ISD::BLENDI:
3579 case X86ISD::PSHUFB:
3580 case X86ISD::PSHUFD:
3581 case X86ISD::PSHUFHW:
3582 case X86ISD::PSHUFLW:
3584 case X86ISD::PALIGNR:
3585 case X86ISD::MOVLHPS:
3586 case X86ISD::MOVLHPD:
3587 case X86ISD::MOVHLPS:
3588 case X86ISD::MOVLPS:
3589 case X86ISD::MOVLPD:
3590 case X86ISD::MOVSHDUP:
3591 case X86ISD::MOVSLDUP:
3592 case X86ISD::MOVDDUP:
3595 case X86ISD::UNPCKL:
3596 case X86ISD::UNPCKH:
3597 case X86ISD::VPERMILPI:
3598 case X86ISD::VPERM2X128:
3599 case X86ISD::VPERMI:
3604 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3605 SDValue V1, SelectionDAG &DAG) {
3607 default: llvm_unreachable("Unknown x86 shuffle node");
3608 case X86ISD::MOVSHDUP:
3609 case X86ISD::MOVSLDUP:
3610 case X86ISD::MOVDDUP:
3611 return DAG.getNode(Opc, dl, VT, V1);
3615 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3616 SDValue V1, unsigned TargetMask,
3617 SelectionDAG &DAG) {
3619 default: llvm_unreachable("Unknown x86 shuffle node");
3620 case X86ISD::PSHUFD:
3621 case X86ISD::PSHUFHW:
3622 case X86ISD::PSHUFLW:
3623 case X86ISD::VPERMILPI:
3624 case X86ISD::VPERMI:
3625 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3629 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3630 SDValue V1, SDValue V2, unsigned TargetMask,
3631 SelectionDAG &DAG) {
3633 default: llvm_unreachable("Unknown x86 shuffle node");
3634 case X86ISD::PALIGNR:
3635 case X86ISD::VALIGN:
3637 case X86ISD::VPERM2X128:
3638 return DAG.getNode(Opc, dl, VT, V1, V2,
3639 DAG.getConstant(TargetMask, MVT::i8));
3643 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3644 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3646 default: llvm_unreachable("Unknown x86 shuffle node");
3647 case X86ISD::MOVLHPS:
3648 case X86ISD::MOVLHPD:
3649 case X86ISD::MOVHLPS:
3650 case X86ISD::MOVLPS:
3651 case X86ISD::MOVLPD:
3654 case X86ISD::UNPCKL:
3655 case X86ISD::UNPCKH:
3656 return DAG.getNode(Opc, dl, VT, V1, V2);
3660 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3661 MachineFunction &MF = DAG.getMachineFunction();
3662 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3663 DAG.getSubtarget().getRegisterInfo());
3664 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3665 int ReturnAddrIndex = FuncInfo->getRAIndex();
3667 if (ReturnAddrIndex == 0) {
3668 // Set up a frame object for the return address.
3669 unsigned SlotSize = RegInfo->getSlotSize();
3670 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3673 FuncInfo->setRAIndex(ReturnAddrIndex);
3676 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3679 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3680 bool hasSymbolicDisplacement) {
3681 // Offset should fit into 32 bit immediate field.
3682 if (!isInt<32>(Offset))
3685 // If we don't have a symbolic displacement - we don't have any extra
3687 if (!hasSymbolicDisplacement)
3690 // FIXME: Some tweaks might be needed for medium code model.
3691 if (M != CodeModel::Small && M != CodeModel::Kernel)
3694 // For small code model we assume that latest object is 16MB before end of 31
3695 // bits boundary. We may also accept pretty large negative constants knowing
3696 // that all objects are in the positive half of address space.
3697 if (M == CodeModel::Small && Offset < 16*1024*1024)
3700 // For kernel code model we know that all object resist in the negative half
3701 // of 32bits address space. We may not accept negative offsets, since they may
3702 // be just off and we may accept pretty large positive ones.
3703 if (M == CodeModel::Kernel && Offset >= 0)
3709 /// isCalleePop - Determines whether the callee is required to pop its
3710 /// own arguments. Callee pop is necessary to support tail calls.
3711 bool X86::isCalleePop(CallingConv::ID CallingConv,
3712 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3713 switch (CallingConv) {
3716 case CallingConv::X86_StdCall:
3717 case CallingConv::X86_FastCall:
3718 case CallingConv::X86_ThisCall:
3720 case CallingConv::Fast:
3721 case CallingConv::GHC:
3722 case CallingConv::HiPE:
3729 /// \brief Return true if the condition is an unsigned comparison operation.
3730 static bool isX86CCUnsigned(unsigned X86CC) {
3732 default: llvm_unreachable("Invalid integer condition!");
3733 case X86::COND_E: return true;
3734 case X86::COND_G: return false;
3735 case X86::COND_GE: return false;
3736 case X86::COND_L: return false;
3737 case X86::COND_LE: return false;
3738 case X86::COND_NE: return true;
3739 case X86::COND_B: return true;
3740 case X86::COND_A: return true;
3741 case X86::COND_BE: return true;
3742 case X86::COND_AE: return true;
3744 llvm_unreachable("covered switch fell through?!");
3747 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3748 /// specific condition code, returning the condition code and the LHS/RHS of the
3749 /// comparison to make.
3750 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3751 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3753 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3754 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3755 // X > -1 -> X == 0, jump !sign.
3756 RHS = DAG.getConstant(0, RHS.getValueType());
3757 return X86::COND_NS;
3759 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3760 // X < 0 -> X == 0, jump on sign.
3763 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3765 RHS = DAG.getConstant(0, RHS.getValueType());
3766 return X86::COND_LE;
3770 switch (SetCCOpcode) {
3771 default: llvm_unreachable("Invalid integer condition!");
3772 case ISD::SETEQ: return X86::COND_E;
3773 case ISD::SETGT: return X86::COND_G;
3774 case ISD::SETGE: return X86::COND_GE;
3775 case ISD::SETLT: return X86::COND_L;
3776 case ISD::SETLE: return X86::COND_LE;
3777 case ISD::SETNE: return X86::COND_NE;
3778 case ISD::SETULT: return X86::COND_B;
3779 case ISD::SETUGT: return X86::COND_A;
3780 case ISD::SETULE: return X86::COND_BE;
3781 case ISD::SETUGE: return X86::COND_AE;
3785 // First determine if it is required or is profitable to flip the operands.
3787 // If LHS is a foldable load, but RHS is not, flip the condition.
3788 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3789 !ISD::isNON_EXTLoad(RHS.getNode())) {
3790 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3791 std::swap(LHS, RHS);
3794 switch (SetCCOpcode) {
3800 std::swap(LHS, RHS);
3804 // On a floating point condition, the flags are set as follows:
3806 // 0 | 0 | 0 | X > Y
3807 // 0 | 0 | 1 | X < Y
3808 // 1 | 0 | 0 | X == Y
3809 // 1 | 1 | 1 | unordered
3810 switch (SetCCOpcode) {
3811 default: llvm_unreachable("Condcode should be pre-legalized away");
3813 case ISD::SETEQ: return X86::COND_E;
3814 case ISD::SETOLT: // flipped
3816 case ISD::SETGT: return X86::COND_A;
3817 case ISD::SETOLE: // flipped
3819 case ISD::SETGE: return X86::COND_AE;
3820 case ISD::SETUGT: // flipped
3822 case ISD::SETLT: return X86::COND_B;
3823 case ISD::SETUGE: // flipped
3825 case ISD::SETLE: return X86::COND_BE;
3827 case ISD::SETNE: return X86::COND_NE;
3828 case ISD::SETUO: return X86::COND_P;
3829 case ISD::SETO: return X86::COND_NP;
3831 case ISD::SETUNE: return X86::COND_INVALID;
3835 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3836 /// code. Current x86 isa includes the following FP cmov instructions:
3837 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3838 static bool hasFPCMov(unsigned X86CC) {
3854 /// isFPImmLegal - Returns true if the target can instruction select the
3855 /// specified FP immediate natively. If false, the legalizer will
3856 /// materialize the FP immediate as a load from a constant pool.
3857 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3858 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3859 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3865 /// \brief Returns true if it is beneficial to convert a load of a constant
3866 /// to just the constant itself.
3867 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3869 assert(Ty->isIntegerTy());
3871 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3872 if (BitSize == 0 || BitSize > 64)
3877 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3878 unsigned Index) const {
3879 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3882 return (Index == 0 || Index == ResVT.getVectorNumElements());
3885 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3886 // Speculate cttz only if we can directly use TZCNT.
3887 return Subtarget->hasBMI();
3890 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3891 // Speculate ctlz only if we can directly use LZCNT.
3892 return Subtarget->hasLZCNT();
3895 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3896 /// the specified range (L, H].
3897 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3898 return (Val < 0) || (Val >= Low && Val < Hi);
3901 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3902 /// specified value.
3903 static bool isUndefOrEqual(int Val, int CmpVal) {
3904 return (Val < 0 || Val == CmpVal);
3907 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3908 /// from position Pos and ending in Pos+Size, falls within the specified
3909 /// sequential range (Low, Low+Size]. or is undef.
3910 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3911 unsigned Pos, unsigned Size, int Low) {
3912 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3913 if (!isUndefOrEqual(Mask[i], Low))
3918 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3919 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3920 /// operand - by default will match for first operand.
3921 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3922 bool TestSecondOperand = false) {
3923 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3924 VT != MVT::v2f64 && VT != MVT::v2i64)
3927 unsigned NumElems = VT.getVectorNumElements();
3928 unsigned Lo = TestSecondOperand ? NumElems : 0;
3929 unsigned Hi = Lo + NumElems;
3931 for (unsigned i = 0; i < NumElems; ++i)
3932 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3938 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3939 /// is suitable for input to PSHUFHW.
3940 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3941 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3944 // Lower quadword copied in order or undef.
3945 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3948 // Upper quadword shuffled.
3949 for (unsigned i = 4; i != 8; ++i)
3950 if (!isUndefOrInRange(Mask[i], 4, 8))
3953 if (VT == MVT::v16i16) {
3954 // Lower quadword copied in order or undef.
3955 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3958 // Upper quadword shuffled.
3959 for (unsigned i = 12; i != 16; ++i)
3960 if (!isUndefOrInRange(Mask[i], 12, 16))
3967 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3968 /// is suitable for input to PSHUFLW.
3969 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3970 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3973 // Upper quadword copied in order.
3974 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3977 // Lower quadword shuffled.
3978 for (unsigned i = 0; i != 4; ++i)
3979 if (!isUndefOrInRange(Mask[i], 0, 4))
3982 if (VT == MVT::v16i16) {
3983 // Upper quadword copied in order.
3984 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3987 // Lower quadword shuffled.
3988 for (unsigned i = 8; i != 12; ++i)
3989 if (!isUndefOrInRange(Mask[i], 8, 12))
3996 /// \brief Return true if the mask specifies a shuffle of elements that is
3997 /// suitable for input to intralane (palignr) or interlane (valign) vector
3999 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
4000 unsigned NumElts = VT.getVectorNumElements();
4001 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
4002 unsigned NumLaneElts = NumElts/NumLanes;
4004 // Do not handle 64-bit element shuffles with palignr.
4005 if (NumLaneElts == 2)
4008 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
4010 for (i = 0; i != NumLaneElts; ++i) {
4015 // Lane is all undef, go to next lane
4016 if (i == NumLaneElts)
4019 int Start = Mask[i+l];
4021 // Make sure its in this lane in one of the sources
4022 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
4023 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
4026 // If not lane 0, then we must match lane 0
4027 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
4030 // Correct second source to be contiguous with first source
4031 if (Start >= (int)NumElts)
4032 Start -= NumElts - NumLaneElts;
4034 // Make sure we're shifting in the right direction.
4035 if (Start <= (int)(i+l))
4040 // Check the rest of the elements to see if they are consecutive.
4041 for (++i; i != NumLaneElts; ++i) {
4042 int Idx = Mask[i+l];
4044 // Make sure its in this lane
4045 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4046 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4049 // If not lane 0, then we must match lane 0
4050 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4053 if (Idx >= (int)NumElts)
4054 Idx -= NumElts - NumLaneElts;
4056 if (!isUndefOrEqual(Idx, Start+i))
4065 /// \brief Return true if the node specifies a shuffle of elements that is
4066 /// suitable for input to PALIGNR.
4067 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4068 const X86Subtarget *Subtarget) {
4069 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4070 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4071 VT.is512BitVector())
4072 // FIXME: Add AVX512BW.
4075 return isAlignrMask(Mask, VT, false);
4078 /// \brief Return true if the node specifies a shuffle of elements that is
4079 /// suitable for input to VALIGN.
4080 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4081 const X86Subtarget *Subtarget) {
4082 // FIXME: Add AVX512VL.
4083 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4085 return isAlignrMask(Mask, VT, true);
4088 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4089 /// the two vector operands have swapped position.
4090 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4091 unsigned NumElems) {
4092 for (unsigned i = 0; i != NumElems; ++i) {
4096 else if (idx < (int)NumElems)
4097 Mask[i] = idx + NumElems;
4099 Mask[i] = idx - NumElems;
4103 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4104 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4105 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4106 /// reverse of what x86 shuffles want.
4107 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4109 unsigned NumElems = VT.getVectorNumElements();
4110 unsigned NumLanes = VT.getSizeInBits()/128;
4111 unsigned NumLaneElems = NumElems/NumLanes;
4113 if (NumLaneElems != 2 && NumLaneElems != 4)
4116 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4117 bool symetricMaskRequired =
4118 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4120 // VSHUFPSY divides the resulting vector into 4 chunks.
4121 // The sources are also splitted into 4 chunks, and each destination
4122 // chunk must come from a different source chunk.
4124 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4125 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4127 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4128 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4130 // VSHUFPDY divides the resulting vector into 4 chunks.
4131 // The sources are also splitted into 4 chunks, and each destination
4132 // chunk must come from a different source chunk.
4134 // SRC1 => X3 X2 X1 X0
4135 // SRC2 => Y3 Y2 Y1 Y0
4137 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4139 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4140 unsigned HalfLaneElems = NumLaneElems/2;
4141 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4142 for (unsigned i = 0; i != NumLaneElems; ++i) {
4143 int Idx = Mask[i+l];
4144 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4145 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4147 // For VSHUFPSY, the mask of the second half must be the same as the
4148 // first but with the appropriate offsets. This works in the same way as
4149 // VPERMILPS works with masks.
4150 if (!symetricMaskRequired || Idx < 0)
4152 if (MaskVal[i] < 0) {
4153 MaskVal[i] = Idx - l;
4156 if ((signed)(Idx - l) != MaskVal[i])
4164 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4165 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4166 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4167 if (!VT.is128BitVector())
4170 unsigned NumElems = VT.getVectorNumElements();
4175 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4176 return isUndefOrEqual(Mask[0], 6) &&
4177 isUndefOrEqual(Mask[1], 7) &&
4178 isUndefOrEqual(Mask[2], 2) &&
4179 isUndefOrEqual(Mask[3], 3);
4182 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4183 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4185 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4186 if (!VT.is128BitVector())
4189 unsigned NumElems = VT.getVectorNumElements();
4194 return isUndefOrEqual(Mask[0], 2) &&
4195 isUndefOrEqual(Mask[1], 3) &&
4196 isUndefOrEqual(Mask[2], 2) &&
4197 isUndefOrEqual(Mask[3], 3);
4200 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4201 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4202 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4203 if (!VT.is128BitVector())
4206 unsigned NumElems = VT.getVectorNumElements();
4208 if (NumElems != 2 && NumElems != 4)
4211 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4212 if (!isUndefOrEqual(Mask[i], i + NumElems))
4215 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4216 if (!isUndefOrEqual(Mask[i], i))
4222 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4223 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4224 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4225 if (!VT.is128BitVector())
4228 unsigned NumElems = VT.getVectorNumElements();
4230 if (NumElems != 2 && NumElems != 4)
4233 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4234 if (!isUndefOrEqual(Mask[i], i))
4237 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4238 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4244 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4245 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4246 /// i. e: If all but one element come from the same vector.
4247 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4248 // TODO: Deal with AVX's VINSERTPS
4249 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4252 unsigned CorrectPosV1 = 0;
4253 unsigned CorrectPosV2 = 0;
4254 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4255 if (Mask[i] == -1) {
4263 else if (Mask[i] == i + 4)
4267 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4268 // We have 3 elements (undefs count as elements from any vector) from one
4269 // vector, and one from another.
4276 // Some special combinations that can be optimized.
4279 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4280 SelectionDAG &DAG) {
4281 MVT VT = SVOp->getSimpleValueType(0);
4284 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4287 ArrayRef<int> Mask = SVOp->getMask();
4289 // These are the special masks that may be optimized.
4290 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4291 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4292 bool MatchEvenMask = true;
4293 bool MatchOddMask = true;
4294 for (int i=0; i<8; ++i) {
4295 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4296 MatchEvenMask = false;
4297 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4298 MatchOddMask = false;
4301 if (!MatchEvenMask && !MatchOddMask)
4304 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4306 SDValue Op0 = SVOp->getOperand(0);
4307 SDValue Op1 = SVOp->getOperand(1);
4309 if (MatchEvenMask) {
4310 // Shift the second operand right to 32 bits.
4311 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4312 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4314 // Shift the first operand left to 32 bits.
4315 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4316 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4318 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4319 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4322 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4323 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4324 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4325 bool HasInt256, bool V2IsSplat = false) {
4327 assert(VT.getSizeInBits() >= 128 &&
4328 "Unsupported vector type for unpckl");
4330 unsigned NumElts = VT.getVectorNumElements();
4331 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4332 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4335 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4336 "Unsupported vector type for unpckh");
4338 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4339 unsigned NumLanes = VT.getSizeInBits()/128;
4340 unsigned NumLaneElts = NumElts/NumLanes;
4342 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4343 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4344 int BitI = Mask[l+i];
4345 int BitI1 = Mask[l+i+1];
4346 if (!isUndefOrEqual(BitI, j))
4349 if (!isUndefOrEqual(BitI1, NumElts))
4352 if (!isUndefOrEqual(BitI1, j + NumElts))
4361 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4362 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4363 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4364 bool HasInt256, bool V2IsSplat = false) {
4365 assert(VT.getSizeInBits() >= 128 &&
4366 "Unsupported vector type for unpckh");
4368 unsigned NumElts = VT.getVectorNumElements();
4369 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4370 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4373 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4374 "Unsupported vector type for unpckh");
4376 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4377 unsigned NumLanes = VT.getSizeInBits()/128;
4378 unsigned NumLaneElts = NumElts/NumLanes;
4380 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4381 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4382 int BitI = Mask[l+i];
4383 int BitI1 = Mask[l+i+1];
4384 if (!isUndefOrEqual(BitI, j))
4387 if (isUndefOrEqual(BitI1, NumElts))
4390 if (!isUndefOrEqual(BitI1, j+NumElts))
4398 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4399 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4401 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4402 unsigned NumElts = VT.getVectorNumElements();
4403 bool Is256BitVec = VT.is256BitVector();
4405 if (VT.is512BitVector())
4407 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4408 "Unsupported vector type for unpckh");
4410 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4411 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4414 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4415 // FIXME: Need a better way to get rid of this, there's no latency difference
4416 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4417 // the former later. We should also remove the "_undef" special mask.
4418 if (NumElts == 4 && Is256BitVec)
4421 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4422 // independently on 128-bit lanes.
4423 unsigned NumLanes = VT.getSizeInBits()/128;
4424 unsigned NumLaneElts = NumElts/NumLanes;
4426 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4427 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4428 int BitI = Mask[l+i];
4429 int BitI1 = Mask[l+i+1];
4431 if (!isUndefOrEqual(BitI, j))
4433 if (!isUndefOrEqual(BitI1, j))
4441 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4442 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4444 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4445 unsigned NumElts = VT.getVectorNumElements();
4447 if (VT.is512BitVector())
4450 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4451 "Unsupported vector type for unpckh");
4453 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4454 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4457 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4458 // independently on 128-bit lanes.
4459 unsigned NumLanes = VT.getSizeInBits()/128;
4460 unsigned NumLaneElts = NumElts/NumLanes;
4462 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4463 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4464 int BitI = Mask[l+i];
4465 int BitI1 = Mask[l+i+1];
4466 if (!isUndefOrEqual(BitI, j))
4468 if (!isUndefOrEqual(BitI1, j))
4475 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4476 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4477 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4478 if (!VT.is512BitVector())
4481 unsigned NumElts = VT.getVectorNumElements();
4482 unsigned HalfSize = NumElts/2;
4483 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4484 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4489 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4490 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4498 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4499 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4500 /// MOVSD, and MOVD, i.e. setting the lowest element.
4501 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4502 if (VT.getVectorElementType().getSizeInBits() < 32)
4504 if (!VT.is128BitVector())
4507 unsigned NumElts = VT.getVectorNumElements();
4509 if (!isUndefOrEqual(Mask[0], NumElts))
4512 for (unsigned i = 1; i != NumElts; ++i)
4513 if (!isUndefOrEqual(Mask[i], i))
4519 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4520 /// as permutations between 128-bit chunks or halves. As an example: this
4522 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4523 /// The first half comes from the second half of V1 and the second half from the
4524 /// the second half of V2.
4525 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4526 if (!HasFp256 || !VT.is256BitVector())
4529 // The shuffle result is divided into half A and half B. In total the two
4530 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4531 // B must come from C, D, E or F.
4532 unsigned HalfSize = VT.getVectorNumElements()/2;
4533 bool MatchA = false, MatchB = false;
4535 // Check if A comes from one of C, D, E, F.
4536 for (unsigned Half = 0; Half != 4; ++Half) {
4537 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4543 // Check if B comes from one of C, D, E, F.
4544 for (unsigned Half = 0; Half != 4; ++Half) {
4545 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4551 return MatchA && MatchB;
4554 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4555 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4556 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4557 MVT VT = SVOp->getSimpleValueType(0);
4559 unsigned HalfSize = VT.getVectorNumElements()/2;
4561 unsigned FstHalf = 0, SndHalf = 0;
4562 for (unsigned i = 0; i < HalfSize; ++i) {
4563 if (SVOp->getMaskElt(i) > 0) {
4564 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4568 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4569 if (SVOp->getMaskElt(i) > 0) {
4570 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4575 return (FstHalf | (SndHalf << 4));
4578 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4579 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4580 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4584 unsigned NumElts = VT.getVectorNumElements();
4586 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4587 for (unsigned i = 0; i != NumElts; ++i) {
4590 Imm8 |= Mask[i] << (i*2);
4595 unsigned LaneSize = 4;
4596 SmallVector<int, 4> MaskVal(LaneSize, -1);
4598 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4599 for (unsigned i = 0; i != LaneSize; ++i) {
4600 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4604 if (MaskVal[i] < 0) {
4605 MaskVal[i] = Mask[i+l] - l;
4606 Imm8 |= MaskVal[i] << (i*2);
4609 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4616 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4617 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4618 /// Note that VPERMIL mask matching is different depending whether theunderlying
4619 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4620 /// to the same elements of the low, but to the higher half of the source.
4621 /// In VPERMILPD the two lanes could be shuffled independently of each other
4622 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4623 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4624 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4625 if (VT.getSizeInBits() < 256 || EltSize < 32)
4627 bool symetricMaskRequired = (EltSize == 32);
4628 unsigned NumElts = VT.getVectorNumElements();
4630 unsigned NumLanes = VT.getSizeInBits()/128;
4631 unsigned LaneSize = NumElts/NumLanes;
4632 // 2 or 4 elements in one lane
4634 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4635 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4636 for (unsigned i = 0; i != LaneSize; ++i) {
4637 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4639 if (symetricMaskRequired) {
4640 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4641 ExpectedMaskVal[i] = Mask[i+l] - l;
4644 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4652 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4653 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4654 /// element of vector 2 and the other elements to come from vector 1 in order.
4655 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4656 bool V2IsSplat = false, bool V2IsUndef = false) {
4657 if (!VT.is128BitVector())
4660 unsigned NumOps = VT.getVectorNumElements();
4661 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4664 if (!isUndefOrEqual(Mask[0], 0))
4667 for (unsigned i = 1; i != NumOps; ++i)
4668 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4669 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4670 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4676 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4677 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4678 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4679 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4680 const X86Subtarget *Subtarget) {
4681 if (!Subtarget->hasSSE3())
4684 unsigned NumElems = VT.getVectorNumElements();
4686 if ((VT.is128BitVector() && NumElems != 4) ||
4687 (VT.is256BitVector() && NumElems != 8) ||
4688 (VT.is512BitVector() && NumElems != 16))
4691 // "i+1" is the value the indexed mask element must have
4692 for (unsigned i = 0; i != NumElems; i += 2)
4693 if (!isUndefOrEqual(Mask[i], i+1) ||
4694 !isUndefOrEqual(Mask[i+1], i+1))
4700 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4701 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4702 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4703 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4704 const X86Subtarget *Subtarget) {
4705 if (!Subtarget->hasSSE3())
4708 unsigned NumElems = VT.getVectorNumElements();
4710 if ((VT.is128BitVector() && NumElems != 4) ||
4711 (VT.is256BitVector() && NumElems != 8) ||
4712 (VT.is512BitVector() && NumElems != 16))
4715 // "i" is the value the indexed mask element must have
4716 for (unsigned i = 0; i != NumElems; i += 2)
4717 if (!isUndefOrEqual(Mask[i], i) ||
4718 !isUndefOrEqual(Mask[i+1], i))
4724 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4725 /// specifies a shuffle of elements that is suitable for input to 256-bit
4726 /// version of MOVDDUP.
4727 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4728 if (!HasFp256 || !VT.is256BitVector())
4731 unsigned NumElts = VT.getVectorNumElements();
4735 for (unsigned i = 0; i != NumElts/2; ++i)
4736 if (!isUndefOrEqual(Mask[i], 0))
4738 for (unsigned i = NumElts/2; i != NumElts; ++i)
4739 if (!isUndefOrEqual(Mask[i], NumElts/2))
4744 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4745 /// specifies a shuffle of elements that is suitable for input to 128-bit
4746 /// version of MOVDDUP.
4747 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4748 if (!VT.is128BitVector())
4751 unsigned e = VT.getVectorNumElements() / 2;
4752 for (unsigned i = 0; i != e; ++i)
4753 if (!isUndefOrEqual(Mask[i], i))
4755 for (unsigned i = 0; i != e; ++i)
4756 if (!isUndefOrEqual(Mask[e+i], i))
4761 /// isVEXTRACTIndex - Return true if the specified
4762 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4763 /// suitable for instruction that extract 128 or 256 bit vectors
4764 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4765 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4766 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4769 // The index should be aligned on a vecWidth-bit boundary.
4771 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4773 MVT VT = N->getSimpleValueType(0);
4774 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4775 bool Result = (Index * ElSize) % vecWidth == 0;
4780 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4781 /// operand specifies a subvector insert that is suitable for input to
4782 /// insertion of 128 or 256-bit subvectors
4783 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4784 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4785 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4787 // The index should be aligned on a vecWidth-bit boundary.
4789 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4791 MVT VT = N->getSimpleValueType(0);
4792 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4793 bool Result = (Index * ElSize) % vecWidth == 0;
4798 bool X86::isVINSERT128Index(SDNode *N) {
4799 return isVINSERTIndex(N, 128);
4802 bool X86::isVINSERT256Index(SDNode *N) {
4803 return isVINSERTIndex(N, 256);
4806 bool X86::isVEXTRACT128Index(SDNode *N) {
4807 return isVEXTRACTIndex(N, 128);
4810 bool X86::isVEXTRACT256Index(SDNode *N) {
4811 return isVEXTRACTIndex(N, 256);
4814 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4815 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4816 /// Handles 128-bit and 256-bit.
4817 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4818 MVT VT = N->getSimpleValueType(0);
4820 assert((VT.getSizeInBits() >= 128) &&
4821 "Unsupported vector type for PSHUF/SHUFP");
4823 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4824 // independently on 128-bit lanes.
4825 unsigned NumElts = VT.getVectorNumElements();
4826 unsigned NumLanes = VT.getSizeInBits()/128;
4827 unsigned NumLaneElts = NumElts/NumLanes;
4829 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4830 "Only supports 2, 4 or 8 elements per lane");
4832 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4834 for (unsigned i = 0; i != NumElts; ++i) {
4835 int Elt = N->getMaskElt(i);
4836 if (Elt < 0) continue;
4837 Elt &= NumLaneElts - 1;
4838 unsigned ShAmt = (i << Shift) % 8;
4839 Mask |= Elt << ShAmt;
4845 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4846 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4847 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4848 MVT VT = N->getSimpleValueType(0);
4850 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4851 "Unsupported vector type for PSHUFHW");
4853 unsigned NumElts = VT.getVectorNumElements();
4856 for (unsigned l = 0; l != NumElts; l += 8) {
4857 // 8 nodes per lane, but we only care about the last 4.
4858 for (unsigned i = 0; i < 4; ++i) {
4859 int Elt = N->getMaskElt(l+i+4);
4860 if (Elt < 0) continue;
4861 Elt &= 0x3; // only 2-bits.
4862 Mask |= Elt << (i * 2);
4869 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4870 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4871 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4872 MVT VT = N->getSimpleValueType(0);
4874 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4875 "Unsupported vector type for PSHUFHW");
4877 unsigned NumElts = VT.getVectorNumElements();
4880 for (unsigned l = 0; l != NumElts; l += 8) {
4881 // 8 nodes per lane, but we only care about the first 4.
4882 for (unsigned i = 0; i < 4; ++i) {
4883 int Elt = N->getMaskElt(l+i);
4884 if (Elt < 0) continue;
4885 Elt &= 0x3; // only 2-bits
4886 Mask |= Elt << (i * 2);
4893 /// \brief Return the appropriate immediate to shuffle the specified
4894 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4895 /// VALIGN (if Interlane is true) instructions.
4896 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4898 MVT VT = SVOp->getSimpleValueType(0);
4899 unsigned EltSize = InterLane ? 1 :
4900 VT.getVectorElementType().getSizeInBits() >> 3;
4902 unsigned NumElts = VT.getVectorNumElements();
4903 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4904 unsigned NumLaneElts = NumElts/NumLanes;
4908 for (i = 0; i != NumElts; ++i) {
4909 Val = SVOp->getMaskElt(i);
4913 if (Val >= (int)NumElts)
4914 Val -= NumElts - NumLaneElts;
4916 assert(Val - i > 0 && "PALIGNR imm should be positive");
4917 return (Val - i) * EltSize;
4920 /// \brief Return the appropriate immediate to shuffle the specified
4921 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4922 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4923 return getShuffleAlignrImmediate(SVOp, false);
4926 /// \brief Return the appropriate immediate to shuffle the specified
4927 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4928 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4929 return getShuffleAlignrImmediate(SVOp, true);
4933 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4934 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4935 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4936 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4939 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4941 MVT VecVT = N->getOperand(0).getSimpleValueType();
4942 MVT ElVT = VecVT.getVectorElementType();
4944 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4945 return Index / NumElemsPerChunk;
4948 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4949 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4950 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4951 llvm_unreachable("Illegal insert subvector for VINSERT");
4954 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4956 MVT VecVT = N->getSimpleValueType(0);
4957 MVT ElVT = VecVT.getVectorElementType();
4959 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4960 return Index / NumElemsPerChunk;
4963 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4964 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4965 /// and VINSERTI128 instructions.
4966 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4967 return getExtractVEXTRACTImmediate(N, 128);
4970 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4971 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4972 /// and VINSERTI64x4 instructions.
4973 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4974 return getExtractVEXTRACTImmediate(N, 256);
4977 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4978 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4979 /// and VINSERTI128 instructions.
4980 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4981 return getInsertVINSERTImmediate(N, 128);
4984 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4985 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4986 /// and VINSERTI64x4 instructions.
4987 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4988 return getInsertVINSERTImmediate(N, 256);
4991 /// isZero - Returns true if Elt is a constant integer zero
4992 static bool isZero(SDValue V) {
4993 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4994 return C && C->isNullValue();
4997 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4999 bool X86::isZeroNode(SDValue Elt) {
5002 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
5003 return CFP->getValueAPF().isPosZero();
5007 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
5008 /// match movhlps. The lower half elements should come from upper half of
5009 /// V1 (and in order), and the upper half elements should come from the upper
5010 /// half of V2 (and in order).
5011 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
5012 if (!VT.is128BitVector())
5014 if (VT.getVectorNumElements() != 4)
5016 for (unsigned i = 0, e = 2; i != e; ++i)
5017 if (!isUndefOrEqual(Mask[i], i+2))
5019 for (unsigned i = 2; i != 4; ++i)
5020 if (!isUndefOrEqual(Mask[i], i+4))
5025 /// isScalarLoadToVector - Returns true if the node is a scalar load that
5026 /// is promoted to a vector. It also returns the LoadSDNode by reference if
5028 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
5029 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
5031 N = N->getOperand(0).getNode();
5032 if (!ISD::isNON_EXTLoad(N))
5035 *LD = cast<LoadSDNode>(N);
5039 // Test whether the given value is a vector value which will be legalized
5041 static bool WillBeConstantPoolLoad(SDNode *N) {
5042 if (N->getOpcode() != ISD::BUILD_VECTOR)
5045 // Check for any non-constant elements.
5046 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5047 switch (N->getOperand(i).getNode()->getOpcode()) {
5049 case ISD::ConstantFP:
5056 // Vectors of all-zeros and all-ones are materialized with special
5057 // instructions rather than being loaded.
5058 return !ISD::isBuildVectorAllZeros(N) &&
5059 !ISD::isBuildVectorAllOnes(N);
5062 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5063 /// match movlp{s|d}. The lower half elements should come from lower half of
5064 /// V1 (and in order), and the upper half elements should come from the upper
5065 /// half of V2 (and in order). And since V1 will become the source of the
5066 /// MOVLP, it must be either a vector load or a scalar load to vector.
5067 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5068 ArrayRef<int> Mask, MVT VT) {
5069 if (!VT.is128BitVector())
5072 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5074 // Is V2 is a vector load, don't do this transformation. We will try to use
5075 // load folding shufps op.
5076 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5079 unsigned NumElems = VT.getVectorNumElements();
5081 if (NumElems != 2 && NumElems != 4)
5083 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5084 if (!isUndefOrEqual(Mask[i], i))
5086 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5087 if (!isUndefOrEqual(Mask[i], i+NumElems))
5092 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5093 /// to an zero vector.
5094 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5095 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5096 SDValue V1 = N->getOperand(0);
5097 SDValue V2 = N->getOperand(1);
5098 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5099 for (unsigned i = 0; i != NumElems; ++i) {
5100 int Idx = N->getMaskElt(i);
5101 if (Idx >= (int)NumElems) {
5102 unsigned Opc = V2.getOpcode();
5103 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5105 if (Opc != ISD::BUILD_VECTOR ||
5106 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5108 } else if (Idx >= 0) {
5109 unsigned Opc = V1.getOpcode();
5110 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5112 if (Opc != ISD::BUILD_VECTOR ||
5113 !X86::isZeroNode(V1.getOperand(Idx)))
5120 /// getZeroVector - Returns a vector of specified type with all zero elements.
5122 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5123 SelectionDAG &DAG, SDLoc dl) {
5124 assert(VT.isVector() && "Expected a vector type");
5126 // Always build SSE zero vectors as <4 x i32> bitcasted
5127 // to their dest type. This ensures they get CSE'd.
5129 if (VT.is128BitVector()) { // SSE
5130 if (Subtarget->hasSSE2()) { // SSE2
5131 SDValue Cst = DAG.getConstant(0, MVT::i32);
5132 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5134 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5135 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5137 } else if (VT.is256BitVector()) { // AVX
5138 if (Subtarget->hasInt256()) { // AVX2
5139 SDValue Cst = DAG.getConstant(0, MVT::i32);
5140 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5141 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5143 // 256-bit logic and arithmetic instructions in AVX are all
5144 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5145 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5146 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5147 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5149 } else if (VT.is512BitVector()) { // AVX-512
5150 SDValue Cst = DAG.getConstant(0, MVT::i32);
5151 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5152 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5153 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5154 } else if (VT.getScalarType() == MVT::i1) {
5155 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5156 SDValue Cst = DAG.getConstant(0, MVT::i1);
5157 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5158 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5160 llvm_unreachable("Unexpected vector type");
5162 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5165 /// getOnesVector - Returns a vector of specified type with all bits set.
5166 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5167 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5168 /// Then bitcast to their original type, ensuring they get CSE'd.
5169 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5171 assert(VT.isVector() && "Expected a vector type");
5173 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5175 if (VT.is256BitVector()) {
5176 if (HasInt256) { // AVX2
5177 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5178 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5180 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5181 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5183 } else if (VT.is128BitVector()) {
5184 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5186 llvm_unreachable("Unexpected vector type");
5188 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5191 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5192 /// that point to V2 points to its first element.
5193 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5194 for (unsigned i = 0; i != NumElems; ++i) {
5195 if (Mask[i] > (int)NumElems) {
5201 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5202 /// operation of specified width.
5203 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5205 unsigned NumElems = VT.getVectorNumElements();
5206 SmallVector<int, 8> Mask;
5207 Mask.push_back(NumElems);
5208 for (unsigned i = 1; i != NumElems; ++i)
5210 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5213 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5214 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5216 unsigned NumElems = VT.getVectorNumElements();
5217 SmallVector<int, 8> Mask;
5218 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5220 Mask.push_back(i + NumElems);
5222 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5225 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5226 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5228 unsigned NumElems = VT.getVectorNumElements();
5229 SmallVector<int, 8> Mask;
5230 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5231 Mask.push_back(i + Half);
5232 Mask.push_back(i + NumElems + Half);
5234 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5237 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5238 // a generic shuffle instruction because the target has no such instructions.
5239 // Generate shuffles which repeat i16 and i8 several times until they can be
5240 // represented by v4f32 and then be manipulated by target suported shuffles.
5241 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5242 MVT VT = V.getSimpleValueType();
5243 int NumElems = VT.getVectorNumElements();
5246 while (NumElems > 4) {
5247 if (EltNo < NumElems/2) {
5248 V = getUnpackl(DAG, dl, VT, V, V);
5250 V = getUnpackh(DAG, dl, VT, V, V);
5251 EltNo -= NumElems/2;
5258 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5259 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5260 MVT VT = V.getSimpleValueType();
5263 if (VT.is128BitVector()) {
5264 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5265 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5266 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5268 } else if (VT.is256BitVector()) {
5269 // To use VPERMILPS to splat scalars, the second half of indicies must
5270 // refer to the higher part, which is a duplication of the lower one,
5271 // because VPERMILPS can only handle in-lane permutations.
5272 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5273 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5275 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5276 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5279 llvm_unreachable("Vector size not supported");
5281 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5284 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5285 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5286 MVT SrcVT = SV->getSimpleValueType(0);
5287 SDValue V1 = SV->getOperand(0);
5290 int EltNo = SV->getSplatIndex();
5291 int NumElems = SrcVT.getVectorNumElements();
5292 bool Is256BitVec = SrcVT.is256BitVector();
5294 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5295 "Unknown how to promote splat for type");
5297 // Extract the 128-bit part containing the splat element and update
5298 // the splat element index when it refers to the higher register.
5300 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5301 if (EltNo >= NumElems/2)
5302 EltNo -= NumElems/2;
5305 // All i16 and i8 vector types can't be used directly by a generic shuffle
5306 // instruction because the target has no such instruction. Generate shuffles
5307 // which repeat i16 and i8 several times until they fit in i32, and then can
5308 // be manipulated by target suported shuffles.
5309 MVT EltVT = SrcVT.getVectorElementType();
5310 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5311 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5313 // Recreate the 256-bit vector and place the same 128-bit vector
5314 // into the low and high part. This is necessary because we want
5315 // to use VPERM* to shuffle the vectors
5317 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5320 return getLegalSplat(DAG, V1, EltNo);
5323 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5324 /// vector of zero or undef vector. This produces a shuffle where the low
5325 /// element of V2 is swizzled into the zero/undef vector, landing at element
5326 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5327 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5329 const X86Subtarget *Subtarget,
5330 SelectionDAG &DAG) {
5331 MVT VT = V2.getSimpleValueType();
5333 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5334 unsigned NumElems = VT.getVectorNumElements();
5335 SmallVector<int, 16> MaskVec;
5336 for (unsigned i = 0; i != NumElems; ++i)
5337 // If this is the insertion idx, put the low elt of V2 here.
5338 MaskVec.push_back(i == Idx ? NumElems : i);
5339 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5342 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5343 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5344 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5345 /// shuffles which use a single input multiple times, and in those cases it will
5346 /// adjust the mask to only have indices within that single input.
5347 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5348 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5349 unsigned NumElems = VT.getVectorNumElements();
5353 bool IsFakeUnary = false;
5354 switch(N->getOpcode()) {
5355 case X86ISD::BLENDI:
5356 ImmN = N->getOperand(N->getNumOperands()-1);
5357 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5360 ImmN = N->getOperand(N->getNumOperands()-1);
5361 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5362 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5364 case X86ISD::UNPCKH:
5365 DecodeUNPCKHMask(VT, Mask);
5366 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5368 case X86ISD::UNPCKL:
5369 DecodeUNPCKLMask(VT, Mask);
5370 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5372 case X86ISD::MOVHLPS:
5373 DecodeMOVHLPSMask(NumElems, Mask);
5374 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5376 case X86ISD::MOVLHPS:
5377 DecodeMOVLHPSMask(NumElems, Mask);
5378 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5380 case X86ISD::PALIGNR:
5381 ImmN = N->getOperand(N->getNumOperands()-1);
5382 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5384 case X86ISD::PSHUFD:
5385 case X86ISD::VPERMILPI:
5386 ImmN = N->getOperand(N->getNumOperands()-1);
5387 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5390 case X86ISD::PSHUFHW:
5391 ImmN = N->getOperand(N->getNumOperands()-1);
5392 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5395 case X86ISD::PSHUFLW:
5396 ImmN = N->getOperand(N->getNumOperands()-1);
5397 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5400 case X86ISD::PSHUFB: {
5402 SDValue MaskNode = N->getOperand(1);
5403 while (MaskNode->getOpcode() == ISD::BITCAST)
5404 MaskNode = MaskNode->getOperand(0);
5406 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5407 // If we have a build-vector, then things are easy.
5408 EVT VT = MaskNode.getValueType();
5409 assert(VT.isVector() &&
5410 "Can't produce a non-vector with a build_vector!");
5411 if (!VT.isInteger())
5414 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5416 SmallVector<uint64_t, 32> RawMask;
5417 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5418 SDValue Op = MaskNode->getOperand(i);
5419 if (Op->getOpcode() == ISD::UNDEF) {
5420 RawMask.push_back((uint64_t)SM_SentinelUndef);
5423 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5426 APInt MaskElement = CN->getAPIntValue();
5428 // We now have to decode the element which could be any integer size and
5429 // extract each byte of it.
5430 for (int j = 0; j < NumBytesPerElement; ++j) {
5431 // Note that this is x86 and so always little endian: the low byte is
5432 // the first byte of the mask.
5433 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5434 MaskElement = MaskElement.lshr(8);
5437 DecodePSHUFBMask(RawMask, Mask);
5441 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5445 SDValue Ptr = MaskLoad->getBasePtr();
5446 if (Ptr->getOpcode() == X86ISD::Wrapper)
5447 Ptr = Ptr->getOperand(0);
5449 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5450 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5453 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5454 // FIXME: Support AVX-512 here.
5455 Type *Ty = C->getType();
5456 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5457 Ty->getVectorNumElements() != 32))
5460 DecodePSHUFBMask(C, Mask);
5466 case X86ISD::VPERMI:
5467 ImmN = N->getOperand(N->getNumOperands()-1);
5468 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5472 case X86ISD::MOVSD: {
5473 // The index 0 always comes from the first element of the second source,
5474 // this is why MOVSS and MOVSD are used in the first place. The other
5475 // elements come from the other positions of the first source vector
5476 Mask.push_back(NumElems);
5477 for (unsigned i = 1; i != NumElems; ++i) {
5482 case X86ISD::VPERM2X128:
5483 ImmN = N->getOperand(N->getNumOperands()-1);
5484 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5485 if (Mask.empty()) return false;
5487 case X86ISD::MOVSLDUP:
5488 DecodeMOVSLDUPMask(VT, Mask);
5490 case X86ISD::MOVSHDUP:
5491 DecodeMOVSHDUPMask(VT, Mask);
5493 case X86ISD::MOVDDUP:
5494 case X86ISD::MOVLHPD:
5495 case X86ISD::MOVLPD:
5496 case X86ISD::MOVLPS:
5497 // Not yet implemented
5499 default: llvm_unreachable("unknown target shuffle node");
5502 // If we have a fake unary shuffle, the shuffle mask is spread across two
5503 // inputs that are actually the same node. Re-map the mask to always point
5504 // into the first input.
5507 if (M >= (int)Mask.size())
5513 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5514 /// element of the result of the vector shuffle.
5515 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5518 return SDValue(); // Limit search depth.
5520 SDValue V = SDValue(N, 0);
5521 EVT VT = V.getValueType();
5522 unsigned Opcode = V.getOpcode();
5524 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5525 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5526 int Elt = SV->getMaskElt(Index);
5529 return DAG.getUNDEF(VT.getVectorElementType());
5531 unsigned NumElems = VT.getVectorNumElements();
5532 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5533 : SV->getOperand(1);
5534 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5537 // Recurse into target specific vector shuffles to find scalars.
5538 if (isTargetShuffle(Opcode)) {
5539 MVT ShufVT = V.getSimpleValueType();
5540 unsigned NumElems = ShufVT.getVectorNumElements();
5541 SmallVector<int, 16> ShuffleMask;
5544 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5547 int Elt = ShuffleMask[Index];
5549 return DAG.getUNDEF(ShufVT.getVectorElementType());
5551 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5553 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5557 // Actual nodes that may contain scalar elements
5558 if (Opcode == ISD::BITCAST) {
5559 V = V.getOperand(0);
5560 EVT SrcVT = V.getValueType();
5561 unsigned NumElems = VT.getVectorNumElements();
5563 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5567 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5568 return (Index == 0) ? V.getOperand(0)
5569 : DAG.getUNDEF(VT.getVectorElementType());
5571 if (V.getOpcode() == ISD::BUILD_VECTOR)
5572 return V.getOperand(Index);
5577 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5578 /// shuffle operation which come from a consecutively from a zero. The
5579 /// search can start in two different directions, from left or right.
5580 /// We count undefs as zeros until PreferredNum is reached.
5581 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5582 unsigned NumElems, bool ZerosFromLeft,
5584 unsigned PreferredNum = -1U) {
5585 unsigned NumZeros = 0;
5586 for (unsigned i = 0; i != NumElems; ++i) {
5587 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5588 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5592 if (X86::isZeroNode(Elt))
5594 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5595 NumZeros = std::min(NumZeros + 1, PreferredNum);
5603 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5604 /// correspond consecutively to elements from one of the vector operands,
5605 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5607 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5608 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5609 unsigned NumElems, unsigned &OpNum) {
5610 bool SeenV1 = false;
5611 bool SeenV2 = false;
5613 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5614 int Idx = SVOp->getMaskElt(i);
5615 // Ignore undef indicies
5619 if (Idx < (int)NumElems)
5624 // Only accept consecutive elements from the same vector
5625 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5629 OpNum = SeenV1 ? 0 : 1;
5633 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5634 /// logical left shift of a vector.
5635 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5636 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5638 SVOp->getSimpleValueType(0).getVectorNumElements();
5639 unsigned NumZeros = getNumOfConsecutiveZeros(
5640 SVOp, NumElems, false /* check zeros from right */, DAG,
5641 SVOp->getMaskElt(0));
5647 // Considering the elements in the mask that are not consecutive zeros,
5648 // check if they consecutively come from only one of the source vectors.
5650 // V1 = {X, A, B, C} 0
5652 // vector_shuffle V1, V2 <1, 2, 3, X>
5654 if (!isShuffleMaskConsecutive(SVOp,
5655 0, // Mask Start Index
5656 NumElems-NumZeros, // Mask End Index(exclusive)
5657 NumZeros, // Where to start looking in the src vector
5658 NumElems, // Number of elements in vector
5659 OpSrc)) // Which source operand ?
5664 ShVal = SVOp->getOperand(OpSrc);
5668 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5669 /// logical left shift of a vector.
5670 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5671 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5673 SVOp->getSimpleValueType(0).getVectorNumElements();
5674 unsigned NumZeros = getNumOfConsecutiveZeros(
5675 SVOp, NumElems, true /* check zeros from left */, DAG,
5676 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5682 // Considering the elements in the mask that are not consecutive zeros,
5683 // check if they consecutively come from only one of the source vectors.
5685 // 0 { A, B, X, X } = V2
5687 // vector_shuffle V1, V2 <X, X, 4, 5>
5689 if (!isShuffleMaskConsecutive(SVOp,
5690 NumZeros, // Mask Start Index
5691 NumElems, // Mask End Index(exclusive)
5692 0, // Where to start looking in the src vector
5693 NumElems, // Number of elements in vector
5694 OpSrc)) // Which source operand ?
5699 ShVal = SVOp->getOperand(OpSrc);
5703 /// isVectorShift - Returns true if the shuffle can be implemented as a
5704 /// logical left or right shift of a vector.
5705 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5706 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5707 // Although the logic below support any bitwidth size, there are no
5708 // shift instructions which handle more than 128-bit vectors.
5709 if (!SVOp->getSimpleValueType(0).is128BitVector())
5712 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5713 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5719 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5721 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5722 unsigned NumNonZero, unsigned NumZero,
5724 const X86Subtarget* Subtarget,
5725 const TargetLowering &TLI) {
5732 for (unsigned i = 0; i < 16; ++i) {
5733 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5734 if (ThisIsNonZero && First) {
5736 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5738 V = DAG.getUNDEF(MVT::v8i16);
5743 SDValue ThisElt, LastElt;
5744 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5745 if (LastIsNonZero) {
5746 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5747 MVT::i16, Op.getOperand(i-1));
5749 if (ThisIsNonZero) {
5750 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5751 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5752 ThisElt, DAG.getConstant(8, MVT::i8));
5754 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5758 if (ThisElt.getNode())
5759 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5760 DAG.getIntPtrConstant(i/2));
5764 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5767 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5769 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5770 unsigned NumNonZero, unsigned NumZero,
5772 const X86Subtarget* Subtarget,
5773 const TargetLowering &TLI) {
5780 for (unsigned i = 0; i < 8; ++i) {
5781 bool isNonZero = (NonZeros & (1 << i)) != 0;
5785 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5787 V = DAG.getUNDEF(MVT::v8i16);
5790 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5791 MVT::v8i16, V, Op.getOperand(i),
5792 DAG.getIntPtrConstant(i));
5799 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5800 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5801 const X86Subtarget *Subtarget,
5802 const TargetLowering &TLI) {
5803 // Find all zeroable elements.
5805 for (int i=0; i < 4; ++i) {
5806 SDValue Elt = Op->getOperand(i);
5807 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5809 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5810 [](bool M) { return !M; }) > 1 &&
5811 "We expect at least two non-zero elements!");
5813 // We only know how to deal with build_vector nodes where elements are either
5814 // zeroable or extract_vector_elt with constant index.
5815 SDValue FirstNonZero;
5816 unsigned FirstNonZeroIdx;
5817 for (unsigned i=0; i < 4; ++i) {
5820 SDValue Elt = Op->getOperand(i);
5821 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5822 !isa<ConstantSDNode>(Elt.getOperand(1)))
5824 // Make sure that this node is extracting from a 128-bit vector.
5825 MVT VT = Elt.getOperand(0).getSimpleValueType();
5826 if (!VT.is128BitVector())
5828 if (!FirstNonZero.getNode()) {
5830 FirstNonZeroIdx = i;
5834 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5835 SDValue V1 = FirstNonZero.getOperand(0);
5836 MVT VT = V1.getSimpleValueType();
5838 // See if this build_vector can be lowered as a blend with zero.
5840 unsigned EltMaskIdx, EltIdx;
5842 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5843 if (Zeroable[EltIdx]) {
5844 // The zero vector will be on the right hand side.
5845 Mask[EltIdx] = EltIdx+4;
5849 Elt = Op->getOperand(EltIdx);
5850 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5851 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5852 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5854 Mask[EltIdx] = EltIdx;
5858 // Let the shuffle legalizer deal with blend operations.
5859 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5860 if (V1.getSimpleValueType() != VT)
5861 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5862 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5865 // See if we can lower this build_vector to a INSERTPS.
5866 if (!Subtarget->hasSSE41())
5869 SDValue V2 = Elt.getOperand(0);
5870 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5873 bool CanFold = true;
5874 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5878 SDValue Current = Op->getOperand(i);
5879 SDValue SrcVector = Current->getOperand(0);
5882 CanFold = SrcVector == V1 &&
5883 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5889 assert(V1.getNode() && "Expected at least two non-zero elements!");
5890 if (V1.getSimpleValueType() != MVT::v4f32)
5891 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5892 if (V2.getSimpleValueType() != MVT::v4f32)
5893 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5895 // Ok, we can emit an INSERTPS instruction.
5897 for (int i = 0; i < 4; ++i)
5901 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5902 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5903 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5904 DAG.getIntPtrConstant(InsertPSMask));
5905 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5908 /// getVShift - Return a vector logical shift node.
5910 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5911 unsigned NumBits, SelectionDAG &DAG,
5912 const TargetLowering &TLI, SDLoc dl) {
5913 assert(VT.is128BitVector() && "Unknown type for VShift");
5914 EVT ShVT = MVT::v2i64;
5915 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5916 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5917 return DAG.getNode(ISD::BITCAST, dl, VT,
5918 DAG.getNode(Opc, dl, ShVT, SrcOp,
5919 DAG.getConstant(NumBits,
5920 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5924 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5926 // Check if the scalar load can be widened into a vector load. And if
5927 // the address is "base + cst" see if the cst can be "absorbed" into
5928 // the shuffle mask.
5929 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5930 SDValue Ptr = LD->getBasePtr();
5931 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5933 EVT PVT = LD->getValueType(0);
5934 if (PVT != MVT::i32 && PVT != MVT::f32)
5939 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5940 FI = FINode->getIndex();
5942 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5943 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5944 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5945 Offset = Ptr.getConstantOperandVal(1);
5946 Ptr = Ptr.getOperand(0);
5951 // FIXME: 256-bit vector instructions don't require a strict alignment,
5952 // improve this code to support it better.
5953 unsigned RequiredAlign = VT.getSizeInBits()/8;
5954 SDValue Chain = LD->getChain();
5955 // Make sure the stack object alignment is at least 16 or 32.
5956 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5957 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5958 if (MFI->isFixedObjectIndex(FI)) {
5959 // Can't change the alignment. FIXME: It's possible to compute
5960 // the exact stack offset and reference FI + adjust offset instead.
5961 // If someone *really* cares about this. That's the way to implement it.
5964 MFI->setObjectAlignment(FI, RequiredAlign);
5968 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5969 // Ptr + (Offset & ~15).
5972 if ((Offset % RequiredAlign) & 3)
5974 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5976 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5977 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5979 int EltNo = (Offset - StartOffset) >> 2;
5980 unsigned NumElems = VT.getVectorNumElements();
5982 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5983 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5984 LD->getPointerInfo().getWithOffset(StartOffset),
5985 false, false, false, 0);
5987 SmallVector<int, 8> Mask;
5988 for (unsigned i = 0; i != NumElems; ++i)
5989 Mask.push_back(EltNo);
5991 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5997 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5998 /// vector of type 'VT', see if the elements can be replaced by a single large
5999 /// load which has the same value as a build_vector whose operands are 'elts'.
6001 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
6003 /// FIXME: we'd also like to handle the case where the last elements are zero
6004 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
6005 /// There's even a handy isZeroNode for that purpose.
6006 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
6007 SDLoc &DL, SelectionDAG &DAG,
6008 bool isAfterLegalize) {
6009 EVT EltVT = VT.getVectorElementType();
6010 unsigned NumElems = Elts.size();
6012 LoadSDNode *LDBase = nullptr;
6013 unsigned LastLoadedElt = -1U;
6015 // For each element in the initializer, see if we've found a load or an undef.
6016 // If we don't find an initial load element, or later load elements are
6017 // non-consecutive, bail out.
6018 for (unsigned i = 0; i < NumElems; ++i) {
6019 SDValue Elt = Elts[i];
6021 if (!Elt.getNode() ||
6022 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
6025 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
6027 LDBase = cast<LoadSDNode>(Elt.getNode());
6031 if (Elt.getOpcode() == ISD::UNDEF)
6034 LoadSDNode *LD = cast<LoadSDNode>(Elt);
6035 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
6040 // If we have found an entire vector of loads and undefs, then return a large
6041 // load of the entire vector width starting at the base pointer. If we found
6042 // consecutive loads for the low half, generate a vzext_load node.
6043 if (LastLoadedElt == NumElems - 1) {
6045 if (isAfterLegalize &&
6046 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6049 SDValue NewLd = SDValue();
6051 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6052 LDBase->getPointerInfo(), LDBase->isVolatile(),
6053 LDBase->isNonTemporal(), LDBase->isInvariant(),
6054 LDBase->getAlignment());
6056 if (LDBase->hasAnyUseOfValue(1)) {
6057 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6059 SDValue(NewLd.getNode(), 1));
6060 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6061 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6062 SDValue(NewLd.getNode(), 1));
6068 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6069 //of a v4i32 / v4f32. It's probably worth generalizing.
6070 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6071 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6072 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6073 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6075 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6076 LDBase->getPointerInfo(),
6077 LDBase->getAlignment(),
6078 false/*isVolatile*/, true/*ReadMem*/,
6081 // Make sure the newly-created LOAD is in the same position as LDBase in
6082 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6083 // update uses of LDBase's output chain to use the TokenFactor.
6084 if (LDBase->hasAnyUseOfValue(1)) {
6085 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6086 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6087 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6088 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6089 SDValue(ResNode.getNode(), 1));
6092 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6097 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6098 /// to generate a splat value for the following cases:
6099 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6100 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6101 /// a scalar load, or a constant.
6102 /// The VBROADCAST node is returned when a pattern is found,
6103 /// or SDValue() otherwise.
6104 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6105 SelectionDAG &DAG) {
6106 // VBROADCAST requires AVX.
6107 // TODO: Splats could be generated for non-AVX CPUs using SSE
6108 // instructions, but there's less potential gain for only 128-bit vectors.
6109 if (!Subtarget->hasAVX())
6112 MVT VT = Op.getSimpleValueType();
6115 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6116 "Unsupported vector type for broadcast.");
6121 switch (Op.getOpcode()) {
6123 // Unknown pattern found.
6126 case ISD::BUILD_VECTOR: {
6127 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6128 BitVector UndefElements;
6129 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6131 // We need a splat of a single value to use broadcast, and it doesn't
6132 // make any sense if the value is only in one element of the vector.
6133 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6137 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6138 Ld.getOpcode() == ISD::ConstantFP);
6140 // Make sure that all of the users of a non-constant load are from the
6141 // BUILD_VECTOR node.
6142 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6147 case ISD::VECTOR_SHUFFLE: {
6148 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6150 // Shuffles must have a splat mask where the first element is
6152 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6155 SDValue Sc = Op.getOperand(0);
6156 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6157 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6159 if (!Subtarget->hasInt256())
6162 // Use the register form of the broadcast instruction available on AVX2.
6163 if (VT.getSizeInBits() >= 256)
6164 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6165 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6168 Ld = Sc.getOperand(0);
6169 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6170 Ld.getOpcode() == ISD::ConstantFP);
6172 // The scalar_to_vector node and the suspected
6173 // load node must have exactly one user.
6174 // Constants may have multiple users.
6176 // AVX-512 has register version of the broadcast
6177 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6178 Ld.getValueType().getSizeInBits() >= 32;
6179 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6186 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6187 bool IsGE256 = (VT.getSizeInBits() >= 256);
6189 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6190 // instruction to save 8 or more bytes of constant pool data.
6191 // TODO: If multiple splats are generated to load the same constant,
6192 // it may be detrimental to overall size. There needs to be a way to detect
6193 // that condition to know if this is truly a size win.
6194 const Function *F = DAG.getMachineFunction().getFunction();
6195 bool OptForSize = F->getAttributes().
6196 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6198 // Handle broadcasting a single constant scalar from the constant pool
6200 // On Sandybridge (no AVX2), it is still better to load a constant vector
6201 // from the constant pool and not to broadcast it from a scalar.
6202 // But override that restriction when optimizing for size.
6203 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6204 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6205 EVT CVT = Ld.getValueType();
6206 assert(!CVT.isVector() && "Must not broadcast a vector type");
6208 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6209 // For size optimization, also splat v2f64 and v2i64, and for size opt
6210 // with AVX2, also splat i8 and i16.
6211 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6212 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6213 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6214 const Constant *C = nullptr;
6215 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6216 C = CI->getConstantIntValue();
6217 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6218 C = CF->getConstantFPValue();
6220 assert(C && "Invalid constant type");
6222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6223 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6224 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6225 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6226 MachinePointerInfo::getConstantPool(),
6227 false, false, false, Alignment);
6229 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6233 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6235 // Handle AVX2 in-register broadcasts.
6236 if (!IsLoad && Subtarget->hasInt256() &&
6237 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6238 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6240 // The scalar source must be a normal load.
6244 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6245 (Subtarget->hasVLX() && ScalarSize == 64))
6246 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6248 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6249 // double since there is no vbroadcastsd xmm
6250 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6251 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6252 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6255 // Unsupported broadcast.
6259 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6260 /// underlying vector and index.
6262 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6264 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6266 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6267 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6270 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6272 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6274 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6275 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6278 // In this case the vector is the extract_subvector expression and the index
6279 // is 2, as specified by the shuffle.
6280 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6281 SDValue ShuffleVec = SVOp->getOperand(0);
6282 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6283 assert(ShuffleVecVT.getVectorElementType() ==
6284 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6286 int ShuffleIdx = SVOp->getMaskElt(Idx);
6287 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6288 ExtractedFromVec = ShuffleVec;
6294 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6295 MVT VT = Op.getSimpleValueType();
6297 // Skip if insert_vec_elt is not supported.
6298 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6299 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6303 unsigned NumElems = Op.getNumOperands();
6307 SmallVector<unsigned, 4> InsertIndices;
6308 SmallVector<int, 8> Mask(NumElems, -1);
6310 for (unsigned i = 0; i != NumElems; ++i) {
6311 unsigned Opc = Op.getOperand(i).getOpcode();
6313 if (Opc == ISD::UNDEF)
6316 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6317 // Quit if more than 1 elements need inserting.
6318 if (InsertIndices.size() > 1)
6321 InsertIndices.push_back(i);
6325 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6326 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6327 // Quit if non-constant index.
6328 if (!isa<ConstantSDNode>(ExtIdx))
6330 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6332 // Quit if extracted from vector of different type.
6333 if (ExtractedFromVec.getValueType() != VT)
6336 if (!VecIn1.getNode())
6337 VecIn1 = ExtractedFromVec;
6338 else if (VecIn1 != ExtractedFromVec) {
6339 if (!VecIn2.getNode())
6340 VecIn2 = ExtractedFromVec;
6341 else if (VecIn2 != ExtractedFromVec)
6342 // Quit if more than 2 vectors to shuffle
6346 if (ExtractedFromVec == VecIn1)
6348 else if (ExtractedFromVec == VecIn2)
6349 Mask[i] = Idx + NumElems;
6352 if (!VecIn1.getNode())
6355 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6356 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6357 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6358 unsigned Idx = InsertIndices[i];
6359 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6360 DAG.getIntPtrConstant(Idx));
6366 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6368 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6370 MVT VT = Op.getSimpleValueType();
6371 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6372 "Unexpected type in LowerBUILD_VECTORvXi1!");
6375 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6376 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6377 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6378 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6381 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6382 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6383 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6384 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6387 bool AllContants = true;
6388 uint64_t Immediate = 0;
6389 int NonConstIdx = -1;
6390 bool IsSplat = true;
6391 unsigned NumNonConsts = 0;
6392 unsigned NumConsts = 0;
6393 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6394 SDValue In = Op.getOperand(idx);
6395 if (In.getOpcode() == ISD::UNDEF)
6397 if (!isa<ConstantSDNode>(In)) {
6398 AllContants = false;
6403 if (cast<ConstantSDNode>(In)->getZExtValue())
6404 Immediate |= (1ULL << idx);
6406 if (In != Op.getOperand(0))
6411 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6412 DAG.getConstant(Immediate, MVT::i16));
6413 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6414 DAG.getIntPtrConstant(0));
6417 if (NumNonConsts == 1 && NonConstIdx != 0) {
6420 SDValue VecAsImm = DAG.getConstant(Immediate,
6421 MVT::getIntegerVT(VT.getSizeInBits()));
6422 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6425 DstVec = DAG.getUNDEF(VT);
6426 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6427 Op.getOperand(NonConstIdx),
6428 DAG.getIntPtrConstant(NonConstIdx));
6430 if (!IsSplat && (NonConstIdx != 0))
6431 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6432 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6435 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6436 DAG.getConstant(-1, SelectVT),
6437 DAG.getConstant(0, SelectVT));
6439 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6440 DAG.getConstant((Immediate | 1), SelectVT),
6441 DAG.getConstant(Immediate, SelectVT));
6442 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6445 /// \brief Return true if \p N implements a horizontal binop and return the
6446 /// operands for the horizontal binop into V0 and V1.
6448 /// This is a helper function of PerformBUILD_VECTORCombine.
6449 /// This function checks that the build_vector \p N in input implements a
6450 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6451 /// operation to match.
6452 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6453 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6454 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6457 /// This function only analyzes elements of \p N whose indices are
6458 /// in range [BaseIdx, LastIdx).
6459 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6461 unsigned BaseIdx, unsigned LastIdx,
6462 SDValue &V0, SDValue &V1) {
6463 EVT VT = N->getValueType(0);
6465 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6466 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6467 "Invalid Vector in input!");
6469 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6470 bool CanFold = true;
6471 unsigned ExpectedVExtractIdx = BaseIdx;
6472 unsigned NumElts = LastIdx - BaseIdx;
6473 V0 = DAG.getUNDEF(VT);
6474 V1 = DAG.getUNDEF(VT);
6476 // Check if N implements a horizontal binop.
6477 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6478 SDValue Op = N->getOperand(i + BaseIdx);
6481 if (Op->getOpcode() == ISD::UNDEF) {
6482 // Update the expected vector extract index.
6483 if (i * 2 == NumElts)
6484 ExpectedVExtractIdx = BaseIdx;
6485 ExpectedVExtractIdx += 2;
6489 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6494 SDValue Op0 = Op.getOperand(0);
6495 SDValue Op1 = Op.getOperand(1);
6497 // Try to match the following pattern:
6498 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6499 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6500 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6501 Op0.getOperand(0) == Op1.getOperand(0) &&
6502 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6503 isa<ConstantSDNode>(Op1.getOperand(1)));
6507 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6508 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6510 if (i * 2 < NumElts) {
6511 if (V0.getOpcode() == ISD::UNDEF)
6512 V0 = Op0.getOperand(0);
6514 if (V1.getOpcode() == ISD::UNDEF)
6515 V1 = Op0.getOperand(0);
6516 if (i * 2 == NumElts)
6517 ExpectedVExtractIdx = BaseIdx;
6520 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6521 if (I0 == ExpectedVExtractIdx)
6522 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6523 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6524 // Try to match the following dag sequence:
6525 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6526 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6530 ExpectedVExtractIdx += 2;
6536 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6537 /// a concat_vector.
6539 /// This is a helper function of PerformBUILD_VECTORCombine.
6540 /// This function expects two 256-bit vectors called V0 and V1.
6541 /// At first, each vector is split into two separate 128-bit vectors.
6542 /// Then, the resulting 128-bit vectors are used to implement two
6543 /// horizontal binary operations.
6545 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6547 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6548 /// the two new horizontal binop.
6549 /// When Mode is set, the first horizontal binop dag node would take as input
6550 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6551 /// horizontal binop dag node would take as input the lower 128-bit of V1
6552 /// and the upper 128-bit of V1.
6554 /// HADD V0_LO, V0_HI
6555 /// HADD V1_LO, V1_HI
6557 /// Otherwise, the first horizontal binop dag node takes as input the lower
6558 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6559 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6561 /// HADD V0_LO, V1_LO
6562 /// HADD V0_HI, V1_HI
6564 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6565 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6566 /// the upper 128-bits of the result.
6567 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6568 SDLoc DL, SelectionDAG &DAG,
6569 unsigned X86Opcode, bool Mode,
6570 bool isUndefLO, bool isUndefHI) {
6571 EVT VT = V0.getValueType();
6572 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6573 "Invalid nodes in input!");
6575 unsigned NumElts = VT.getVectorNumElements();
6576 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6577 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6578 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6579 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6580 EVT NewVT = V0_LO.getValueType();
6582 SDValue LO = DAG.getUNDEF(NewVT);
6583 SDValue HI = DAG.getUNDEF(NewVT);
6586 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6587 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6588 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6589 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6590 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6592 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6593 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6594 V1_LO->getOpcode() != ISD::UNDEF))
6595 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6597 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6598 V1_HI->getOpcode() != ISD::UNDEF))
6599 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6602 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6605 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6606 /// sequence of 'vadd + vsub + blendi'.
6607 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6608 const X86Subtarget *Subtarget) {
6610 EVT VT = BV->getValueType(0);
6611 unsigned NumElts = VT.getVectorNumElements();
6612 SDValue InVec0 = DAG.getUNDEF(VT);
6613 SDValue InVec1 = DAG.getUNDEF(VT);
6615 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6616 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6618 // Odd-numbered elements in the input build vector are obtained from
6619 // adding two integer/float elements.
6620 // Even-numbered elements in the input build vector are obtained from
6621 // subtracting two integer/float elements.
6622 unsigned ExpectedOpcode = ISD::FSUB;
6623 unsigned NextExpectedOpcode = ISD::FADD;
6624 bool AddFound = false;
6625 bool SubFound = false;
6627 for (unsigned i = 0, e = NumElts; i != e; i++) {
6628 SDValue Op = BV->getOperand(i);
6630 // Skip 'undef' values.
6631 unsigned Opcode = Op.getOpcode();
6632 if (Opcode == ISD::UNDEF) {
6633 std::swap(ExpectedOpcode, NextExpectedOpcode);
6637 // Early exit if we found an unexpected opcode.
6638 if (Opcode != ExpectedOpcode)
6641 SDValue Op0 = Op.getOperand(0);
6642 SDValue Op1 = Op.getOperand(1);
6644 // Try to match the following pattern:
6645 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6646 // Early exit if we cannot match that sequence.
6647 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6648 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6649 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6650 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6651 Op0.getOperand(1) != Op1.getOperand(1))
6654 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6658 // We found a valid add/sub node. Update the information accordingly.
6664 // Update InVec0 and InVec1.
6665 if (InVec0.getOpcode() == ISD::UNDEF)
6666 InVec0 = Op0.getOperand(0);
6667 if (InVec1.getOpcode() == ISD::UNDEF)
6668 InVec1 = Op1.getOperand(0);
6670 // Make sure that operands in input to each add/sub node always
6671 // come from a same pair of vectors.
6672 if (InVec0 != Op0.getOperand(0)) {
6673 if (ExpectedOpcode == ISD::FSUB)
6676 // FADD is commutable. Try to commute the operands
6677 // and then test again.
6678 std::swap(Op0, Op1);
6679 if (InVec0 != Op0.getOperand(0))
6683 if (InVec1 != Op1.getOperand(0))
6686 // Update the pair of expected opcodes.
6687 std::swap(ExpectedOpcode, NextExpectedOpcode);
6690 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6691 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6692 InVec1.getOpcode() != ISD::UNDEF)
6693 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6698 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6699 const X86Subtarget *Subtarget) {
6701 EVT VT = N->getValueType(0);
6702 unsigned NumElts = VT.getVectorNumElements();
6703 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6704 SDValue InVec0, InVec1;
6706 // Try to match an ADDSUB.
6707 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6708 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6709 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6710 if (Value.getNode())
6714 // Try to match horizontal ADD/SUB.
6715 unsigned NumUndefsLO = 0;
6716 unsigned NumUndefsHI = 0;
6717 unsigned Half = NumElts/2;
6719 // Count the number of UNDEF operands in the build_vector in input.
6720 for (unsigned i = 0, e = Half; i != e; ++i)
6721 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6724 for (unsigned i = Half, e = NumElts; i != e; ++i)
6725 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6728 // Early exit if this is either a build_vector of all UNDEFs or all the
6729 // operands but one are UNDEF.
6730 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6733 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6734 // Try to match an SSE3 float HADD/HSUB.
6735 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6736 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6738 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6739 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6740 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6741 // Try to match an SSSE3 integer HADD/HSUB.
6742 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6743 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6745 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6746 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6749 if (!Subtarget->hasAVX())
6752 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6753 // Try to match an AVX horizontal add/sub of packed single/double
6754 // precision floating point values from 256-bit vectors.
6755 SDValue InVec2, InVec3;
6756 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6757 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6758 ((InVec0.getOpcode() == ISD::UNDEF ||
6759 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6760 ((InVec1.getOpcode() == ISD::UNDEF ||
6761 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6762 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6764 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6765 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6766 ((InVec0.getOpcode() == ISD::UNDEF ||
6767 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6768 ((InVec1.getOpcode() == ISD::UNDEF ||
6769 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6770 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6771 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6772 // Try to match an AVX2 horizontal add/sub of signed integers.
6773 SDValue InVec2, InVec3;
6775 bool CanFold = true;
6777 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6778 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6779 ((InVec0.getOpcode() == ISD::UNDEF ||
6780 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6781 ((InVec1.getOpcode() == ISD::UNDEF ||
6782 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6783 X86Opcode = X86ISD::HADD;
6784 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6785 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6786 ((InVec0.getOpcode() == ISD::UNDEF ||
6787 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6788 ((InVec1.getOpcode() == ISD::UNDEF ||
6789 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6790 X86Opcode = X86ISD::HSUB;
6795 // Fold this build_vector into a single horizontal add/sub.
6796 // Do this only if the target has AVX2.
6797 if (Subtarget->hasAVX2())
6798 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6800 // Do not try to expand this build_vector into a pair of horizontal
6801 // add/sub if we can emit a pair of scalar add/sub.
6802 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6805 // Convert this build_vector into a pair of horizontal binop followed by
6807 bool isUndefLO = NumUndefsLO == Half;
6808 bool isUndefHI = NumUndefsHI == Half;
6809 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6810 isUndefLO, isUndefHI);
6814 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6815 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6817 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6818 X86Opcode = X86ISD::HADD;
6819 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6820 X86Opcode = X86ISD::HSUB;
6821 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6822 X86Opcode = X86ISD::FHADD;
6823 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6824 X86Opcode = X86ISD::FHSUB;
6828 // Don't try to expand this build_vector into a pair of horizontal add/sub
6829 // if we can simply emit a pair of scalar add/sub.
6830 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6833 // Convert this build_vector into two horizontal add/sub followed by
6835 bool isUndefLO = NumUndefsLO == Half;
6836 bool isUndefHI = NumUndefsHI == Half;
6837 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6838 isUndefLO, isUndefHI);
6845 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6848 MVT VT = Op.getSimpleValueType();
6849 MVT ExtVT = VT.getVectorElementType();
6850 unsigned NumElems = Op.getNumOperands();
6852 // Generate vectors for predicate vectors.
6853 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6854 return LowerBUILD_VECTORvXi1(Op, DAG);
6856 // Vectors containing all zeros can be matched by pxor and xorps later
6857 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6858 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6859 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6860 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6863 return getZeroVector(VT, Subtarget, DAG, dl);
6866 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6867 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6868 // vpcmpeqd on 256-bit vectors.
6869 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6870 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6873 if (!VT.is512BitVector())
6874 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6877 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6878 if (Broadcast.getNode())
6881 unsigned EVTBits = ExtVT.getSizeInBits();
6883 unsigned NumZero = 0;
6884 unsigned NumNonZero = 0;
6885 unsigned NonZeros = 0;
6886 bool IsAllConstants = true;
6887 SmallSet<SDValue, 8> Values;
6888 for (unsigned i = 0; i < NumElems; ++i) {
6889 SDValue Elt = Op.getOperand(i);
6890 if (Elt.getOpcode() == ISD::UNDEF)
6893 if (Elt.getOpcode() != ISD::Constant &&
6894 Elt.getOpcode() != ISD::ConstantFP)
6895 IsAllConstants = false;
6896 if (X86::isZeroNode(Elt))
6899 NonZeros |= (1 << i);
6904 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6905 if (NumNonZero == 0)
6906 return DAG.getUNDEF(VT);
6908 // Special case for single non-zero, non-undef, element.
6909 if (NumNonZero == 1) {
6910 unsigned Idx = countTrailingZeros(NonZeros);
6911 SDValue Item = Op.getOperand(Idx);
6913 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6914 // the value are obviously zero, truncate the value to i32 and do the
6915 // insertion that way. Only do this if the value is non-constant or if the
6916 // value is a constant being inserted into element 0. It is cheaper to do
6917 // a constant pool load than it is to do a movd + shuffle.
6918 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6919 (!IsAllConstants || Idx == 0)) {
6920 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6922 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6923 EVT VecVT = MVT::v4i32;
6924 unsigned VecElts = 4;
6926 // Truncate the value (which may itself be a constant) to i32, and
6927 // convert it to a vector with movd (S2V+shuffle to zero extend).
6928 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6929 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6931 // If using the new shuffle lowering, just directly insert this.
6932 if (ExperimentalVectorShuffleLowering)
6934 ISD::BITCAST, dl, VT,
6935 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6937 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6939 // Now we have our 32-bit value zero extended in the low element of
6940 // a vector. If Idx != 0, swizzle it into place.
6942 SmallVector<int, 4> Mask;
6943 Mask.push_back(Idx);
6944 for (unsigned i = 1; i != VecElts; ++i)
6946 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6949 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6953 // If we have a constant or non-constant insertion into the low element of
6954 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6955 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6956 // depending on what the source datatype is.
6959 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6961 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6962 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6963 if (VT.is256BitVector() || VT.is512BitVector()) {
6964 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6965 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6966 Item, DAG.getIntPtrConstant(0));
6968 assert(VT.is128BitVector() && "Expected an SSE value type!");
6969 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6970 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6971 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6974 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6975 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6976 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6977 if (VT.is256BitVector()) {
6978 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6979 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6981 assert(VT.is128BitVector() && "Expected an SSE value type!");
6982 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6984 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6988 // Is it a vector logical left shift?
6989 if (NumElems == 2 && Idx == 1 &&
6990 X86::isZeroNode(Op.getOperand(0)) &&
6991 !X86::isZeroNode(Op.getOperand(1))) {
6992 unsigned NumBits = VT.getSizeInBits();
6993 return getVShift(true, VT,
6994 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6995 VT, Op.getOperand(1)),
6996 NumBits/2, DAG, *this, dl);
6999 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
7002 // Otherwise, if this is a vector with i32 or f32 elements, and the element
7003 // is a non-constant being inserted into an element other than the low one,
7004 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
7005 // movd/movss) to move this into the low element, then shuffle it into
7007 if (EVTBits == 32) {
7008 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
7010 // If using the new shuffle lowering, just directly insert this.
7011 if (ExperimentalVectorShuffleLowering)
7012 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
7014 // Turn it into a shuffle of zero and zero-extended scalar to vector.
7015 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
7016 SmallVector<int, 8> MaskVec;
7017 for (unsigned i = 0; i != NumElems; ++i)
7018 MaskVec.push_back(i == Idx ? 0 : 1);
7019 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
7023 // Splat is obviously ok. Let legalizer expand it to a shuffle.
7024 if (Values.size() == 1) {
7025 if (EVTBits == 32) {
7026 // Instead of a shuffle like this:
7027 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
7028 // Check if it's possible to issue this instead.
7029 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
7030 unsigned Idx = countTrailingZeros(NonZeros);
7031 SDValue Item = Op.getOperand(Idx);
7032 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
7033 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
7038 // A vector full of immediates; various special cases are already
7039 // handled, so this is best done with a single constant-pool load.
7043 // For AVX-length vectors, see if we can use a vector load to get all of the
7044 // elements, otherwise build the individual 128-bit pieces and use
7045 // shuffles to put them in place.
7046 if (VT.is256BitVector() || VT.is512BitVector()) {
7047 SmallVector<SDValue, 64> V;
7048 for (unsigned i = 0; i != NumElems; ++i)
7049 V.push_back(Op.getOperand(i));
7051 // Check for a build vector of consecutive loads.
7052 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7055 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7057 // Build both the lower and upper subvector.
7058 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7059 makeArrayRef(&V[0], NumElems/2));
7060 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7061 makeArrayRef(&V[NumElems / 2], NumElems/2));
7063 // Recreate the wider vector with the lower and upper part.
7064 if (VT.is256BitVector())
7065 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7066 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7069 // Let legalizer expand 2-wide build_vectors.
7070 if (EVTBits == 64) {
7071 if (NumNonZero == 1) {
7072 // One half is zero or undef.
7073 unsigned Idx = countTrailingZeros(NonZeros);
7074 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7075 Op.getOperand(Idx));
7076 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7081 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7082 if (EVTBits == 8 && NumElems == 16) {
7083 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7085 if (V.getNode()) return V;
7088 if (EVTBits == 16 && NumElems == 8) {
7089 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7091 if (V.getNode()) return V;
7094 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7095 if (EVTBits == 32 && NumElems == 4) {
7096 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7101 // If element VT is == 32 bits, turn it into a number of shuffles.
7102 SmallVector<SDValue, 8> V(NumElems);
7103 if (NumElems == 4 && NumZero > 0) {
7104 for (unsigned i = 0; i < 4; ++i) {
7105 bool isZero = !(NonZeros & (1 << i));
7107 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7109 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7112 for (unsigned i = 0; i < 2; ++i) {
7113 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7116 V[i] = V[i*2]; // Must be a zero vector.
7119 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7122 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7125 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7130 bool Reverse1 = (NonZeros & 0x3) == 2;
7131 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7135 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7136 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7138 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7141 if (Values.size() > 1 && VT.is128BitVector()) {
7142 // Check for a build vector of consecutive loads.
7143 for (unsigned i = 0; i < NumElems; ++i)
7144 V[i] = Op.getOperand(i);
7146 // Check for elements which are consecutive loads.
7147 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7151 // Check for a build vector from mostly shuffle plus few inserting.
7152 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7156 // For SSE 4.1, use insertps to put the high elements into the low element.
7157 if (getSubtarget()->hasSSE41()) {
7159 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7160 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7162 Result = DAG.getUNDEF(VT);
7164 for (unsigned i = 1; i < NumElems; ++i) {
7165 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7166 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7167 Op.getOperand(i), DAG.getIntPtrConstant(i));
7172 // Otherwise, expand into a number of unpckl*, start by extending each of
7173 // our (non-undef) elements to the full vector width with the element in the
7174 // bottom slot of the vector (which generates no code for SSE).
7175 for (unsigned i = 0; i < NumElems; ++i) {
7176 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7177 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7179 V[i] = DAG.getUNDEF(VT);
7182 // Next, we iteratively mix elements, e.g. for v4f32:
7183 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7184 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7185 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7186 unsigned EltStride = NumElems >> 1;
7187 while (EltStride != 0) {
7188 for (unsigned i = 0; i < EltStride; ++i) {
7189 // If V[i+EltStride] is undef and this is the first round of mixing,
7190 // then it is safe to just drop this shuffle: V[i] is already in the
7191 // right place, the one element (since it's the first round) being
7192 // inserted as undef can be dropped. This isn't safe for successive
7193 // rounds because they will permute elements within both vectors.
7194 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7195 EltStride == NumElems/2)
7198 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7207 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7208 // to create 256-bit vectors from two other 128-bit ones.
7209 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7211 MVT ResVT = Op.getSimpleValueType();
7213 assert((ResVT.is256BitVector() ||
7214 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7216 SDValue V1 = Op.getOperand(0);
7217 SDValue V2 = Op.getOperand(1);
7218 unsigned NumElems = ResVT.getVectorNumElements();
7219 if(ResVT.is256BitVector())
7220 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7222 if (Op.getNumOperands() == 4) {
7223 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7224 ResVT.getVectorNumElements()/2);
7225 SDValue V3 = Op.getOperand(2);
7226 SDValue V4 = Op.getOperand(3);
7227 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7228 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7230 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7233 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7234 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7235 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7236 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7237 Op.getNumOperands() == 4)));
7239 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7240 // from two other 128-bit ones.
7242 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7243 return LowerAVXCONCAT_VECTORS(Op, DAG);
7247 //===----------------------------------------------------------------------===//
7248 // Vector shuffle lowering
7250 // This is an experimental code path for lowering vector shuffles on x86. It is
7251 // designed to handle arbitrary vector shuffles and blends, gracefully
7252 // degrading performance as necessary. It works hard to recognize idiomatic
7253 // shuffles and lower them to optimal instruction patterns without leaving
7254 // a framework that allows reasonably efficient handling of all vector shuffle
7256 //===----------------------------------------------------------------------===//
7258 /// \brief Tiny helper function to identify a no-op mask.
7260 /// This is a somewhat boring predicate function. It checks whether the mask
7261 /// array input, which is assumed to be a single-input shuffle mask of the kind
7262 /// used by the X86 shuffle instructions (not a fully general
7263 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7264 /// in-place shuffle are 'no-op's.
7265 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7266 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7267 if (Mask[i] != -1 && Mask[i] != i)
7272 /// \brief Helper function to classify a mask as a single-input mask.
7274 /// This isn't a generic single-input test because in the vector shuffle
7275 /// lowering we canonicalize single inputs to be the first input operand. This
7276 /// means we can more quickly test for a single input by only checking whether
7277 /// an input from the second operand exists. We also assume that the size of
7278 /// mask corresponds to the size of the input vectors which isn't true in the
7279 /// fully general case.
7280 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7282 if (M >= (int)Mask.size())
7287 /// \brief Test whether there are elements crossing 128-bit lanes in this
7290 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7291 /// and we routinely test for these.
7292 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7293 int LaneSize = 128 / VT.getScalarSizeInBits();
7294 int Size = Mask.size();
7295 for (int i = 0; i < Size; ++i)
7296 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7301 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7303 /// This checks a shuffle mask to see if it is performing the same
7304 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7305 /// that it is also not lane-crossing. It may however involve a blend from the
7306 /// same lane of a second vector.
7308 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7309 /// non-trivial to compute in the face of undef lanes. The representation is
7310 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7311 /// entries from both V1 and V2 inputs to the wider mask.
7313 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7314 SmallVectorImpl<int> &RepeatedMask) {
7315 int LaneSize = 128 / VT.getScalarSizeInBits();
7316 RepeatedMask.resize(LaneSize, -1);
7317 int Size = Mask.size();
7318 for (int i = 0; i < Size; ++i) {
7321 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7322 // This entry crosses lanes, so there is no way to model this shuffle.
7325 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7326 if (RepeatedMask[i % LaneSize] == -1)
7327 // This is the first non-undef entry in this slot of a 128-bit lane.
7328 RepeatedMask[i % LaneSize] =
7329 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7330 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7331 // Found a mismatch with the repeated mask.
7337 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7338 // 2013 will allow us to use it as a non-type template parameter.
7341 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7343 /// See its documentation for details.
7344 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7345 if (Mask.size() != Args.size())
7347 for (int i = 0, e = Mask.size(); i < e; ++i) {
7348 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7349 if (Mask[i] != -1 && Mask[i] != *Args[i])
7357 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7360 /// This is a fast way to test a shuffle mask against a fixed pattern:
7362 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7364 /// It returns true if the mask is exactly as wide as the argument list, and
7365 /// each element of the mask is either -1 (signifying undef) or the value given
7366 /// in the argument.
7367 static const VariadicFunction1<
7368 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7370 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7372 /// This helper function produces an 8-bit shuffle immediate corresponding to
7373 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7374 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7377 /// NB: We rely heavily on "undef" masks preserving the input lane.
7378 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7379 SelectionDAG &DAG) {
7380 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7381 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7382 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7383 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7384 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7387 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7388 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7389 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7390 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7391 return DAG.getConstant(Imm, MVT::i8);
7394 /// \brief Try to emit a blend instruction for a shuffle.
7396 /// This doesn't do any checks for the availability of instructions for blending
7397 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7398 /// be matched in the backend with the type given. What it does check for is
7399 /// that the shuffle mask is in fact a blend.
7400 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7401 SDValue V2, ArrayRef<int> Mask,
7402 const X86Subtarget *Subtarget,
7403 SelectionDAG &DAG) {
7405 unsigned BlendMask = 0;
7406 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7407 if (Mask[i] >= Size) {
7408 if (Mask[i] != i + Size)
7409 return SDValue(); // Shuffled V2 input!
7410 BlendMask |= 1u << i;
7413 if (Mask[i] >= 0 && Mask[i] != i)
7414 return SDValue(); // Shuffled V1 input!
7416 switch (VT.SimpleTy) {
7421 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7422 DAG.getConstant(BlendMask, MVT::i8));
7426 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7430 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7431 // that instruction.
7432 if (Subtarget->hasAVX2()) {
7433 // Scale the blend by the number of 32-bit dwords per element.
7434 int Scale = VT.getScalarSizeInBits() / 32;
7436 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7437 if (Mask[i] >= Size)
7438 for (int j = 0; j < Scale; ++j)
7439 BlendMask |= 1u << (i * Scale + j);
7441 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7442 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7443 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7444 return DAG.getNode(ISD::BITCAST, DL, VT,
7445 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7446 DAG.getConstant(BlendMask, MVT::i8)));
7450 // For integer shuffles we need to expand the mask and cast the inputs to
7451 // v8i16s prior to blending.
7452 int Scale = 8 / VT.getVectorNumElements();
7454 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7455 if (Mask[i] >= Size)
7456 for (int j = 0; j < Scale; ++j)
7457 BlendMask |= 1u << (i * Scale + j);
7459 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7460 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7461 return DAG.getNode(ISD::BITCAST, DL, VT,
7462 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7463 DAG.getConstant(BlendMask, MVT::i8)));
7467 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7468 SmallVector<int, 8> RepeatedMask;
7469 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7470 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7471 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7473 for (int i = 0; i < 8; ++i)
7474 if (RepeatedMask[i] >= 16)
7475 BlendMask |= 1u << i;
7476 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7477 DAG.getConstant(BlendMask, MVT::i8));
7482 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7483 // Scale the blend by the number of bytes per element.
7484 int Scale = VT.getScalarSizeInBits() / 8;
7485 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7487 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7488 // mix of LLVM's code generator and the x86 backend. We tell the code
7489 // generator that boolean values in the elements of an x86 vector register
7490 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7491 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7492 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7493 // of the element (the remaining are ignored) and 0 in that high bit would
7494 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7495 // the LLVM model for boolean values in vector elements gets the relevant
7496 // bit set, it is set backwards and over constrained relative to x86's
7498 SDValue VSELECTMask[32];
7499 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7500 for (int j = 0; j < Scale; ++j)
7501 VSELECTMask[Scale * i + j] =
7502 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7503 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7505 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7506 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7508 ISD::BITCAST, DL, VT,
7509 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7510 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7515 llvm_unreachable("Not a supported integer vector type!");
7519 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7520 /// unblended shuffles followed by an unshuffled blend.
7522 /// This matches the extremely common pattern for handling combined
7523 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7525 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7529 SelectionDAG &DAG) {
7530 // Shuffle the input elements into the desired positions in V1 and V2 and
7531 // blend them together.
7532 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7533 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7534 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7535 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7536 if (Mask[i] >= 0 && Mask[i] < Size) {
7537 V1Mask[i] = Mask[i];
7539 } else if (Mask[i] >= Size) {
7540 V2Mask[i] = Mask[i] - Size;
7541 BlendMask[i] = i + Size;
7544 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7545 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7546 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7549 /// \brief Try to lower a vector shuffle as a byte rotation.
7551 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7552 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7553 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7554 /// try to generically lower a vector shuffle through such an pattern. It
7555 /// does not check for the profitability of lowering either as PALIGNR or
7556 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7557 /// This matches shuffle vectors that look like:
7559 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7561 /// Essentially it concatenates V1 and V2, shifts right by some number of
7562 /// elements, and takes the low elements as the result. Note that while this is
7563 /// specified as a *right shift* because x86 is little-endian, it is a *left
7564 /// rotate* of the vector lanes.
7566 /// Note that this only handles 128-bit vector widths currently.
7567 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7570 const X86Subtarget *Subtarget,
7571 SelectionDAG &DAG) {
7572 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7574 // We need to detect various ways of spelling a rotation:
7575 // [11, 12, 13, 14, 15, 0, 1, 2]
7576 // [-1, 12, 13, 14, -1, -1, 1, -1]
7577 // [-1, -1, -1, -1, -1, -1, 1, 2]
7578 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7579 // [-1, 4, 5, 6, -1, -1, 9, -1]
7580 // [-1, 4, 5, 6, -1, -1, -1, -1]
7583 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7586 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7588 // Based on the mod-Size value of this mask element determine where
7589 // a rotated vector would have started.
7590 int StartIdx = i - (Mask[i] % Size);
7592 // The identity rotation isn't interesting, stop.
7595 // If we found the tail of a vector the rotation must be the missing
7596 // front. If we found the head of a vector, it must be how much of the head.
7597 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7600 Rotation = CandidateRotation;
7601 else if (Rotation != CandidateRotation)
7602 // The rotations don't match, so we can't match this mask.
7605 // Compute which value this mask is pointing at.
7606 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7608 // Compute which of the two target values this index should be assigned to.
7609 // This reflects whether the high elements are remaining or the low elements
7611 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7613 // Either set up this value if we've not encountered it before, or check
7614 // that it remains consistent.
7617 else if (TargetV != MaskV)
7618 // This may be a rotation, but it pulls from the inputs in some
7619 // unsupported interleaving.
7623 // Check that we successfully analyzed the mask, and normalize the results.
7624 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7625 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7631 assert(VT.getSizeInBits() == 128 &&
7632 "Rotate-based lowering only supports 128-bit lowering!");
7633 assert(Mask.size() <= 16 &&
7634 "Can shuffle at most 16 bytes in a 128-bit vector!");
7636 // The actual rotate instruction rotates bytes, so we need to scale the
7637 // rotation based on how many bytes are in the vector.
7638 int Scale = 16 / Mask.size();
7640 // SSSE3 targets can use the palignr instruction
7641 if (Subtarget->hasSSSE3()) {
7642 // Cast the inputs to v16i8 to match PALIGNR.
7643 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7644 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7646 return DAG.getNode(ISD::BITCAST, DL, VT,
7647 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7648 DAG.getConstant(Rotation * Scale, MVT::i8)));
7651 // Default SSE2 implementation
7652 int LoByteShift = 16 - Rotation * Scale;
7653 int HiByteShift = Rotation * Scale;
7655 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7656 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7657 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7659 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7660 DAG.getConstant(8 * LoByteShift, MVT::i8));
7661 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7662 DAG.getConstant(8 * HiByteShift, MVT::i8));
7663 return DAG.getNode(ISD::BITCAST, DL, VT,
7664 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7667 /// \brief Compute whether each element of a shuffle is zeroable.
7669 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7670 /// Either it is an undef element in the shuffle mask, the element of the input
7671 /// referenced is undef, or the element of the input referenced is known to be
7672 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7673 /// as many lanes with this technique as possible to simplify the remaining
7675 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7676 SDValue V1, SDValue V2) {
7677 SmallBitVector Zeroable(Mask.size(), false);
7679 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7680 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7682 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7684 // Handle the easy cases.
7685 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7690 // If this is an index into a build_vector node, dig out the input value and
7692 SDValue V = M < Size ? V1 : V2;
7693 if (V.getOpcode() != ISD::BUILD_VECTOR)
7696 SDValue Input = V.getOperand(M % Size);
7697 // The UNDEF opcode check really should be dead code here, but not quite
7698 // worth asserting on (it isn't invalid, just unexpected).
7699 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7706 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7708 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7709 /// byte-shift instructions. The mask must consist of a shifted sequential
7710 /// shuffle from one of the input vectors and zeroable elements for the
7711 /// remaining 'shifted in' elements.
7713 /// Note that this only handles 128-bit vector widths currently.
7714 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7715 SDValue V2, ArrayRef<int> Mask,
7716 SelectionDAG &DAG) {
7717 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7719 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7721 int Size = Mask.size();
7722 int Scale = 16 / Size;
7724 for (int Shift = 1; Shift < Size; Shift++) {
7725 int ByteShift = Shift * Scale;
7727 // PSRLDQ : (little-endian) right byte shift
7728 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7729 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7730 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7731 bool ZeroableRight = true;
7732 for (int i = Size - Shift; i < Size; i++) {
7733 ZeroableRight &= Zeroable[i];
7736 if (ZeroableRight) {
7737 bool ValidShiftRight1 =
7738 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Shift);
7739 bool ValidShiftRight2 =
7740 isSequentialOrUndefInRange(Mask, 0, Size - Shift, Size + Shift);
7742 if (ValidShiftRight1 || ValidShiftRight2) {
7743 // Cast the inputs to v2i64 to match PSRLDQ.
7744 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7745 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7746 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7747 DAG.getConstant(ByteShift * 8, MVT::i8));
7748 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7752 // PSLLDQ : (little-endian) left byte shift
7753 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7754 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7755 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7756 bool ZeroableLeft = true;
7757 for (int i = 0; i < Shift; i++) {
7758 ZeroableLeft &= Zeroable[i];
7762 bool ValidShiftLeft1 =
7763 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, 0);
7764 bool ValidShiftLeft2 =
7765 isSequentialOrUndefInRange(Mask, Shift, Size - Shift, Size);
7767 if (ValidShiftLeft1 || ValidShiftLeft2) {
7768 // Cast the inputs to v2i64 to match PSLLDQ.
7769 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7770 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7771 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7772 DAG.getConstant(ByteShift * 8, MVT::i8));
7773 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7781 /// \brief Lower a vector shuffle as a zero or any extension.
7783 /// Given a specific number of elements, element bit width, and extension
7784 /// stride, produce either a zero or any extension based on the available
7785 /// features of the subtarget.
7786 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7787 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7788 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7789 assert(Scale > 1 && "Need a scale to extend.");
7790 int EltBits = VT.getSizeInBits() / NumElements;
7791 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7792 "Only 8, 16, and 32 bit elements can be extended.");
7793 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7795 // Found a valid zext mask! Try various lowering strategies based on the
7796 // input type and available ISA extensions.
7797 if (Subtarget->hasSSE41()) {
7798 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7799 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7800 NumElements / Scale);
7801 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7802 return DAG.getNode(ISD::BITCAST, DL, VT,
7803 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7806 // For any extends we can cheat for larger element sizes and use shuffle
7807 // instructions that can fold with a load and/or copy.
7808 if (AnyExt && EltBits == 32) {
7809 int PSHUFDMask[4] = {0, -1, 1, -1};
7811 ISD::BITCAST, DL, VT,
7812 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7813 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7814 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7816 if (AnyExt && EltBits == 16 && Scale > 2) {
7817 int PSHUFDMask[4] = {0, -1, 0, -1};
7818 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7819 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7820 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7821 int PSHUFHWMask[4] = {1, -1, -1, -1};
7823 ISD::BITCAST, DL, VT,
7824 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7825 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7826 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7829 // If this would require more than 2 unpack instructions to expand, use
7830 // pshufb when available. We can only use more than 2 unpack instructions
7831 // when zero extending i8 elements which also makes it easier to use pshufb.
7832 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7833 assert(NumElements == 16 && "Unexpected byte vector width!");
7834 SDValue PSHUFBMask[16];
7835 for (int i = 0; i < 16; ++i)
7837 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7838 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7839 return DAG.getNode(ISD::BITCAST, DL, VT,
7840 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7841 DAG.getNode(ISD::BUILD_VECTOR, DL,
7842 MVT::v16i8, PSHUFBMask)));
7845 // Otherwise emit a sequence of unpacks.
7847 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7848 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7849 : getZeroVector(InputVT, Subtarget, DAG, DL);
7850 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7851 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7855 } while (Scale > 1);
7856 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7859 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7861 /// This routine will try to do everything in its power to cleverly lower
7862 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7863 /// check for the profitability of this lowering, it tries to aggressively
7864 /// match this pattern. It will use all of the micro-architectural details it
7865 /// can to emit an efficient lowering. It handles both blends with all-zero
7866 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7867 /// masking out later).
7869 /// The reason we have dedicated lowering for zext-style shuffles is that they
7870 /// are both incredibly common and often quite performance sensitive.
7871 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7872 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7873 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7874 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7876 int Bits = VT.getSizeInBits();
7877 int NumElements = Mask.size();
7879 // Define a helper function to check a particular ext-scale and lower to it if
7881 auto Lower = [&](int Scale) -> SDValue {
7884 for (int i = 0; i < NumElements; ++i) {
7886 continue; // Valid anywhere but doesn't tell us anything.
7887 if (i % Scale != 0) {
7888 // Each of the extend elements needs to be zeroable.
7892 // We no lorger are in the anyext case.
7897 // Each of the base elements needs to be consecutive indices into the
7898 // same input vector.
7899 SDValue V = Mask[i] < NumElements ? V1 : V2;
7902 else if (InputV != V)
7903 return SDValue(); // Flip-flopping inputs.
7905 if (Mask[i] % NumElements != i / Scale)
7906 return SDValue(); // Non-consecutive strided elemenst.
7909 // If we fail to find an input, we have a zero-shuffle which should always
7910 // have already been handled.
7911 // FIXME: Maybe handle this here in case during blending we end up with one?
7915 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7916 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7919 // The widest scale possible for extending is to a 64-bit integer.
7920 assert(Bits % 64 == 0 &&
7921 "The number of bits in a vector must be divisible by 64 on x86!");
7922 int NumExtElements = Bits / 64;
7924 // Each iteration, try extending the elements half as much, but into twice as
7926 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7927 assert(NumElements % NumExtElements == 0 &&
7928 "The input vector size must be divisble by the extended size.");
7929 if (SDValue V = Lower(NumElements / NumExtElements))
7933 // No viable ext lowering found.
7937 /// \brief Try to get a scalar value for a specific element of a vector.
7939 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7940 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7941 SelectionDAG &DAG) {
7942 MVT VT = V.getSimpleValueType();
7943 MVT EltVT = VT.getVectorElementType();
7944 while (V.getOpcode() == ISD::BITCAST)
7945 V = V.getOperand(0);
7946 // If the bitcasts shift the element size, we can't extract an equivalent
7948 MVT NewVT = V.getSimpleValueType();
7949 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7952 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7953 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7954 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7959 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7961 /// This is particularly important because the set of instructions varies
7962 /// significantly based on whether the operand is a load or not.
7963 static bool isShuffleFoldableLoad(SDValue V) {
7964 while (V.getOpcode() == ISD::BITCAST)
7965 V = V.getOperand(0);
7967 return ISD::isNON_EXTLoad(V.getNode());
7970 /// \brief Try to lower insertion of a single element into a zero vector.
7972 /// This is a common pattern that we have especially efficient patterns to lower
7973 /// across all subtarget feature sets.
7974 static SDValue lowerVectorShuffleAsElementInsertion(
7975 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7976 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7977 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7979 MVT EltVT = VT.getVectorElementType();
7981 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7982 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7984 bool IsV1Zeroable = true;
7985 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7986 if (i != V2Index && !Zeroable[i]) {
7987 IsV1Zeroable = false;
7991 // Check for a single input from a SCALAR_TO_VECTOR node.
7992 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7993 // all the smarts here sunk into that routine. However, the current
7994 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7995 // vector shuffle lowering is dead.
7996 if (SDValue V2S = getScalarValueForVectorElement(
7997 V2, Mask[V2Index] - Mask.size(), DAG)) {
7998 // We need to zext the scalar if it is smaller than an i32.
7999 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
8000 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
8001 // Using zext to expand a narrow element won't work for non-zero
8006 // Zero-extend directly to i32.
8008 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
8010 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
8011 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
8012 EltVT == MVT::i16) {
8013 // Either not inserting from the low element of the input or the input
8014 // element size is too small to use VZEXT_MOVL to clear the high bits.
8018 if (!IsV1Zeroable) {
8019 // If V1 can't be treated as a zero vector we have fewer options to lower
8020 // this. We can't support integer vectors or non-zero targets cheaply, and
8021 // the V1 elements can't be permuted in any way.
8022 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
8023 if (!VT.isFloatingPoint() || V2Index != 0)
8025 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8026 V1Mask[V2Index] = -1;
8027 if (!isNoopShuffleMask(V1Mask))
8029 // This is essentially a special case blend operation, but if we have
8030 // general purpose blend operations, they are always faster. Bail and let
8031 // the rest of the lowering handle these as blends.
8032 if (Subtarget->hasSSE41())
8035 // Otherwise, use MOVSD or MOVSS.
8036 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8037 "Only two types of floating point element types to handle!");
8038 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8042 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8044 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8047 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8048 // the desired position. Otherwise it is more efficient to do a vector
8049 // shift left. We know that we can do a vector shift left because all
8050 // the inputs are zero.
8051 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8052 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8053 V2Shuffle[V2Index] = 0;
8054 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8056 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8058 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8060 V2Index * EltVT.getSizeInBits(),
8061 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8062 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8068 /// \brief Try to lower broadcast of a single element.
8070 /// For convenience, this code also bundles all of the subtarget feature set
8071 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8072 /// a convenient way to factor it out.
8073 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8075 const X86Subtarget *Subtarget,
8076 SelectionDAG &DAG) {
8077 if (!Subtarget->hasAVX())
8079 if (VT.isInteger() && !Subtarget->hasAVX2())
8082 // Check that the mask is a broadcast.
8083 int BroadcastIdx = -1;
8085 if (M >= 0 && BroadcastIdx == -1)
8087 else if (M >= 0 && M != BroadcastIdx)
8090 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8091 "a sorted mask where the broadcast "
8094 // Go up the chain of (vector) values to try and find a scalar load that
8095 // we can combine with the broadcast.
8097 switch (V.getOpcode()) {
8098 case ISD::CONCAT_VECTORS: {
8099 int OperandSize = Mask.size() / V.getNumOperands();
8100 V = V.getOperand(BroadcastIdx / OperandSize);
8101 BroadcastIdx %= OperandSize;
8105 case ISD::INSERT_SUBVECTOR: {
8106 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8107 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8111 int BeginIdx = (int)ConstantIdx->getZExtValue();
8113 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8114 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8115 BroadcastIdx -= BeginIdx;
8126 // Check if this is a broadcast of a scalar. We special case lowering
8127 // for scalars so that we can more effectively fold with loads.
8128 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8129 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8130 V = V.getOperand(BroadcastIdx);
8132 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8134 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8136 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8137 // We can't broadcast from a vector register w/o AVX2, and we can only
8138 // broadcast from the zero-element of a vector register.
8142 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8145 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8147 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8148 /// support for floating point shuffles but not integer shuffles. These
8149 /// instructions will incur a domain crossing penalty on some chips though so
8150 /// it is better to avoid lowering through this for integer vectors where
8152 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8153 const X86Subtarget *Subtarget,
8154 SelectionDAG &DAG) {
8156 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8157 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8158 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8159 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8160 ArrayRef<int> Mask = SVOp->getMask();
8161 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8163 if (isSingleInputShuffleMask(Mask)) {
8164 // Straight shuffle of a single input vector. Simulate this by using the
8165 // single input as both of the "inputs" to this instruction..
8166 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8168 if (Subtarget->hasAVX()) {
8169 // If we have AVX, we can use VPERMILPS which will allow folding a load
8170 // into the shuffle.
8171 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8172 DAG.getConstant(SHUFPDMask, MVT::i8));
8175 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8176 DAG.getConstant(SHUFPDMask, MVT::i8));
8178 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8179 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8181 // Use dedicated unpack instructions for masks that match their pattern.
8182 if (isShuffleEquivalent(Mask, 0, 2))
8183 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8184 if (isShuffleEquivalent(Mask, 1, 3))
8185 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8187 // If we have a single input, insert that into V1 if we can do so cheaply.
8188 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8189 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8190 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8192 // Try inverting the insertion since for v2 masks it is easy to do and we
8193 // can't reliably sort the mask one way or the other.
8194 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8195 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8196 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8197 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8201 // Try to use one of the special instruction patterns to handle two common
8202 // blend patterns if a zero-blend above didn't work.
8203 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8204 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8205 // We can either use a special instruction to load over the low double or
8206 // to move just the low double.
8208 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8210 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8212 if (Subtarget->hasSSE41())
8213 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8217 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8218 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8219 DAG.getConstant(SHUFPDMask, MVT::i8));
8222 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8224 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8225 /// the integer unit to minimize domain crossing penalties. However, for blends
8226 /// it falls back to the floating point shuffle operation with appropriate bit
8228 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8229 const X86Subtarget *Subtarget,
8230 SelectionDAG &DAG) {
8232 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8233 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8234 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8235 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8236 ArrayRef<int> Mask = SVOp->getMask();
8237 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8239 if (isSingleInputShuffleMask(Mask)) {
8240 // Check for being able to broadcast a single element.
8241 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8242 Mask, Subtarget, DAG))
8245 // Straight shuffle of a single input vector. For everything from SSE2
8246 // onward this has a single fast instruction with no scary immediates.
8247 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8248 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8249 int WidenedMask[4] = {
8250 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8251 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8253 ISD::BITCAST, DL, MVT::v2i64,
8254 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8255 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8258 // Try to use byte shift instructions.
8259 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8260 DL, MVT::v2i64, V1, V2, Mask, DAG))
8263 // If we have a single input from V2 insert that into V1 if we can do so
8265 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8266 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8267 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8269 // Try inverting the insertion since for v2 masks it is easy to do and we
8270 // can't reliably sort the mask one way or the other.
8271 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8272 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8273 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8274 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8278 // Use dedicated unpack instructions for masks that match their pattern.
8279 if (isShuffleEquivalent(Mask, 0, 2))
8280 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8281 if (isShuffleEquivalent(Mask, 1, 3))
8282 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8284 if (Subtarget->hasSSE41())
8285 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8289 // Try to use byte rotation instructions.
8290 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8291 if (Subtarget->hasSSSE3())
8292 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8293 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8296 // We implement this with SHUFPD which is pretty lame because it will likely
8297 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8298 // However, all the alternatives are still more cycles and newer chips don't
8299 // have this problem. It would be really nice if x86 had better shuffles here.
8300 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8301 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8302 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8303 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8306 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8308 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8309 /// It makes no assumptions about whether this is the *best* lowering, it simply
8311 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8312 ArrayRef<int> Mask, SDValue V1,
8313 SDValue V2, SelectionDAG &DAG) {
8314 SDValue LowV = V1, HighV = V2;
8315 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8318 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8320 if (NumV2Elements == 1) {
8322 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8325 // Compute the index adjacent to V2Index and in the same half by toggling
8327 int V2AdjIndex = V2Index ^ 1;
8329 if (Mask[V2AdjIndex] == -1) {
8330 // Handles all the cases where we have a single V2 element and an undef.
8331 // This will only ever happen in the high lanes because we commute the
8332 // vector otherwise.
8334 std::swap(LowV, HighV);
8335 NewMask[V2Index] -= 4;
8337 // Handle the case where the V2 element ends up adjacent to a V1 element.
8338 // To make this work, blend them together as the first step.
8339 int V1Index = V2AdjIndex;
8340 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8341 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8342 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8344 // Now proceed to reconstruct the final blend as we have the necessary
8345 // high or low half formed.
8352 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8353 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8355 } else if (NumV2Elements == 2) {
8356 if (Mask[0] < 4 && Mask[1] < 4) {
8357 // Handle the easy case where we have V1 in the low lanes and V2 in the
8361 } else if (Mask[2] < 4 && Mask[3] < 4) {
8362 // We also handle the reversed case because this utility may get called
8363 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8364 // arrange things in the right direction.
8370 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8371 // trying to place elements directly, just blend them and set up the final
8372 // shuffle to place them.
8374 // The first two blend mask elements are for V1, the second two are for
8376 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8377 Mask[2] < 4 ? Mask[2] : Mask[3],
8378 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8379 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8380 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8381 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8383 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8386 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8387 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8388 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8389 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8392 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8393 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8396 /// \brief Lower 4-lane 32-bit floating point shuffles.
8398 /// Uses instructions exclusively from the floating point unit to minimize
8399 /// domain crossing penalties, as these are sufficient to implement all v4f32
8401 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8402 const X86Subtarget *Subtarget,
8403 SelectionDAG &DAG) {
8405 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8406 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8407 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8408 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8409 ArrayRef<int> Mask = SVOp->getMask();
8410 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8413 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8415 if (NumV2Elements == 0) {
8416 // Check for being able to broadcast a single element.
8417 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8418 Mask, Subtarget, DAG))
8421 if (Subtarget->hasAVX()) {
8422 // If we have AVX, we can use VPERMILPS which will allow folding a load
8423 // into the shuffle.
8424 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8425 getV4X86ShuffleImm8ForMask(Mask, DAG));
8428 // Otherwise, use a straight shuffle of a single input vector. We pass the
8429 // input vector to both operands to simulate this with a SHUFPS.
8430 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8431 getV4X86ShuffleImm8ForMask(Mask, DAG));
8434 // Use dedicated unpack instructions for masks that match their pattern.
8435 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8436 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8437 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8438 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8440 // There are special ways we can lower some single-element blends. However, we
8441 // have custom ways we can lower more complex single-element blends below that
8442 // we defer to if both this and BLENDPS fail to match, so restrict this to
8443 // when the V2 input is targeting element 0 of the mask -- that is the fast
8445 if (NumV2Elements == 1 && Mask[0] >= 4)
8446 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8447 Mask, Subtarget, DAG))
8450 if (Subtarget->hasSSE41())
8451 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8455 // Check for whether we can use INSERTPS to perform the blend. We only use
8456 // INSERTPS when the V1 elements are already in the correct locations
8457 // because otherwise we can just always use two SHUFPS instructions which
8458 // are much smaller to encode than a SHUFPS and an INSERTPS.
8459 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8461 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8464 // When using INSERTPS we can zero any lane of the destination. Collect
8465 // the zero inputs into a mask and drop them from the lanes of V1 which
8466 // actually need to be present as inputs to the INSERTPS.
8467 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8469 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8470 bool InsertNeedsShuffle = false;
8472 for (int i = 0; i < 4; ++i)
8476 } else if (Mask[i] != i) {
8477 InsertNeedsShuffle = true;
8482 // We don't want to use INSERTPS or other insertion techniques if it will
8483 // require shuffling anyways.
8484 if (!InsertNeedsShuffle) {
8485 // If all of V1 is zeroable, replace it with undef.
8486 if ((ZMask | 1 << V2Index) == 0xF)
8487 V1 = DAG.getUNDEF(MVT::v4f32);
8489 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8490 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8492 // Insert the V2 element into the desired position.
8493 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8494 DAG.getConstant(InsertPSMask, MVT::i8));
8498 // Otherwise fall back to a SHUFPS lowering strategy.
8499 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8502 /// \brief Lower 4-lane i32 vector shuffles.
8504 /// We try to handle these with integer-domain shuffles where we can, but for
8505 /// blends we use the floating point domain blend instructions.
8506 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8507 const X86Subtarget *Subtarget,
8508 SelectionDAG &DAG) {
8510 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8511 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8512 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8513 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8514 ArrayRef<int> Mask = SVOp->getMask();
8515 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8517 // Whenever we can lower this as a zext, that instruction is strictly faster
8518 // than any alternative. It also allows us to fold memory operands into the
8519 // shuffle in many cases.
8520 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8521 Mask, Subtarget, DAG))
8525 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8527 if (NumV2Elements == 0) {
8528 // Check for being able to broadcast a single element.
8529 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8530 Mask, Subtarget, DAG))
8533 // Straight shuffle of a single input vector. For everything from SSE2
8534 // onward this has a single fast instruction with no scary immediates.
8535 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8536 // but we aren't actually going to use the UNPCK instruction because doing
8537 // so prevents folding a load into this instruction or making a copy.
8538 const int UnpackLoMask[] = {0, 0, 1, 1};
8539 const int UnpackHiMask[] = {2, 2, 3, 3};
8540 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8541 Mask = UnpackLoMask;
8542 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8543 Mask = UnpackHiMask;
8545 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8546 getV4X86ShuffleImm8ForMask(Mask, DAG));
8549 // Try to use byte shift instructions.
8550 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8551 DL, MVT::v4i32, V1, V2, Mask, DAG))
8554 // There are special ways we can lower some single-element blends.
8555 if (NumV2Elements == 1)
8556 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8557 Mask, Subtarget, DAG))
8560 // Use dedicated unpack instructions for masks that match their pattern.
8561 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8562 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8563 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8564 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8566 if (Subtarget->hasSSE41())
8567 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8571 // Try to use byte rotation instructions.
8572 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8573 if (Subtarget->hasSSSE3())
8574 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8575 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8578 // We implement this with SHUFPS because it can blend from two vectors.
8579 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8580 // up the inputs, bypassing domain shift penalties that we would encur if we
8581 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8583 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8584 DAG.getVectorShuffle(
8586 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8587 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8590 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8591 /// shuffle lowering, and the most complex part.
8593 /// The lowering strategy is to try to form pairs of input lanes which are
8594 /// targeted at the same half of the final vector, and then use a dword shuffle
8595 /// to place them onto the right half, and finally unpack the paired lanes into
8596 /// their final position.
8598 /// The exact breakdown of how to form these dword pairs and align them on the
8599 /// correct sides is really tricky. See the comments within the function for
8600 /// more of the details.
8601 static SDValue lowerV8I16SingleInputVectorShuffle(
8602 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8603 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8604 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8605 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8606 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8608 SmallVector<int, 4> LoInputs;
8609 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8610 [](int M) { return M >= 0; });
8611 std::sort(LoInputs.begin(), LoInputs.end());
8612 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8613 SmallVector<int, 4> HiInputs;
8614 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8615 [](int M) { return M >= 0; });
8616 std::sort(HiInputs.begin(), HiInputs.end());
8617 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8619 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8620 int NumHToL = LoInputs.size() - NumLToL;
8622 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8623 int NumHToH = HiInputs.size() - NumLToH;
8624 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8625 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8626 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8627 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8629 // Check for being able to broadcast a single element.
8630 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8631 Mask, Subtarget, DAG))
8634 // Try to use byte shift instructions.
8635 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8636 DL, MVT::v8i16, V, V, Mask, DAG))
8639 // Use dedicated unpack instructions for masks that match their pattern.
8640 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8641 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8642 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8643 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8645 // Try to use byte rotation instructions.
8646 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8647 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8650 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8651 // such inputs we can swap two of the dwords across the half mark and end up
8652 // with <=2 inputs to each half in each half. Once there, we can fall through
8653 // to the generic code below. For example:
8655 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8656 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8658 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8659 // and an existing 2-into-2 on the other half. In this case we may have to
8660 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8661 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8662 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8663 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8664 // half than the one we target for fixing) will be fixed when we re-enter this
8665 // path. We will also combine away any sequence of PSHUFD instructions that
8666 // result into a single instruction. Here is an example of the tricky case:
8668 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8669 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8671 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8673 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8674 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8676 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8677 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8679 // The result is fine to be handled by the generic logic.
8680 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8681 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8682 int AOffset, int BOffset) {
8683 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8684 "Must call this with A having 3 or 1 inputs from the A half.");
8685 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8686 "Must call this with B having 1 or 3 inputs from the B half.");
8687 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8688 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8690 // Compute the index of dword with only one word among the three inputs in
8691 // a half by taking the sum of the half with three inputs and subtracting
8692 // the sum of the actual three inputs. The difference is the remaining
8695 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8696 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8697 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8698 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8699 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8700 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8701 int TripleNonInputIdx =
8702 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8703 TripleDWord = TripleNonInputIdx / 2;
8705 // We use xor with one to compute the adjacent DWord to whichever one the
8707 OneInputDWord = (OneInput / 2) ^ 1;
8709 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8710 // and BToA inputs. If there is also such a problem with the BToB and AToB
8711 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8712 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8713 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8714 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8715 // Compute how many inputs will be flipped by swapping these DWords. We
8717 // to balance this to ensure we don't form a 3-1 shuffle in the other
8719 int NumFlippedAToBInputs =
8720 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8721 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8722 int NumFlippedBToBInputs =
8723 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8724 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8725 if ((NumFlippedAToBInputs == 1 &&
8726 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8727 (NumFlippedBToBInputs == 1 &&
8728 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8729 // We choose whether to fix the A half or B half based on whether that
8730 // half has zero flipped inputs. At zero, we may not be able to fix it
8731 // with that half. We also bias towards fixing the B half because that
8732 // will more commonly be the high half, and we have to bias one way.
8733 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8734 ArrayRef<int> Inputs) {
8735 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8736 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8737 PinnedIdx ^ 1) != Inputs.end();
8738 // Determine whether the free index is in the flipped dword or the
8739 // unflipped dword based on where the pinned index is. We use this bit
8740 // in an xor to conditionally select the adjacent dword.
8741 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8742 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8743 FixFreeIdx) != Inputs.end();
8744 if (IsFixIdxInput == IsFixFreeIdxInput)
8746 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8747 FixFreeIdx) != Inputs.end();
8748 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8749 "We need to be changing the number of flipped inputs!");
8750 int PSHUFHalfMask[] = {0, 1, 2, 3};
8751 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8752 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8754 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8757 if (M != -1 && M == FixIdx)
8759 else if (M != -1 && M == FixFreeIdx)
8762 if (NumFlippedBToBInputs != 0) {
8764 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8765 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8767 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8769 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8770 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8775 int PSHUFDMask[] = {0, 1, 2, 3};
8776 PSHUFDMask[ADWord] = BDWord;
8777 PSHUFDMask[BDWord] = ADWord;
8778 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8779 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8780 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8781 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8783 // Adjust the mask to match the new locations of A and B.
8785 if (M != -1 && M/2 == ADWord)
8786 M = 2 * BDWord + M % 2;
8787 else if (M != -1 && M/2 == BDWord)
8788 M = 2 * ADWord + M % 2;
8790 // Recurse back into this routine to re-compute state now that this isn't
8791 // a 3 and 1 problem.
8792 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8795 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8796 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8797 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8798 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8800 // At this point there are at most two inputs to the low and high halves from
8801 // each half. That means the inputs can always be grouped into dwords and
8802 // those dwords can then be moved to the correct half with a dword shuffle.
8803 // We use at most one low and one high word shuffle to collect these paired
8804 // inputs into dwords, and finally a dword shuffle to place them.
8805 int PSHUFLMask[4] = {-1, -1, -1, -1};
8806 int PSHUFHMask[4] = {-1, -1, -1, -1};
8807 int PSHUFDMask[4] = {-1, -1, -1, -1};
8809 // First fix the masks for all the inputs that are staying in their
8810 // original halves. This will then dictate the targets of the cross-half
8812 auto fixInPlaceInputs =
8813 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8814 MutableArrayRef<int> SourceHalfMask,
8815 MutableArrayRef<int> HalfMask, int HalfOffset) {
8816 if (InPlaceInputs.empty())
8818 if (InPlaceInputs.size() == 1) {
8819 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8820 InPlaceInputs[0] - HalfOffset;
8821 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8824 if (IncomingInputs.empty()) {
8825 // Just fix all of the in place inputs.
8826 for (int Input : InPlaceInputs) {
8827 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8828 PSHUFDMask[Input / 2] = Input / 2;
8833 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8834 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8835 InPlaceInputs[0] - HalfOffset;
8836 // Put the second input next to the first so that they are packed into
8837 // a dword. We find the adjacent index by toggling the low bit.
8838 int AdjIndex = InPlaceInputs[0] ^ 1;
8839 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8840 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8841 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8843 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8844 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8846 // Now gather the cross-half inputs and place them into a free dword of
8847 // their target half.
8848 // FIXME: This operation could almost certainly be simplified dramatically to
8849 // look more like the 3-1 fixing operation.
8850 auto moveInputsToRightHalf = [&PSHUFDMask](
8851 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8852 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8853 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8855 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8856 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8858 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8860 int LowWord = Word & ~1;
8861 int HighWord = Word | 1;
8862 return isWordClobbered(SourceHalfMask, LowWord) ||
8863 isWordClobbered(SourceHalfMask, HighWord);
8866 if (IncomingInputs.empty())
8869 if (ExistingInputs.empty()) {
8870 // Map any dwords with inputs from them into the right half.
8871 for (int Input : IncomingInputs) {
8872 // If the source half mask maps over the inputs, turn those into
8873 // swaps and use the swapped lane.
8874 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8875 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8876 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8877 Input - SourceOffset;
8878 // We have to swap the uses in our half mask in one sweep.
8879 for (int &M : HalfMask)
8880 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8882 else if (M == Input)
8883 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8885 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8886 Input - SourceOffset &&
8887 "Previous placement doesn't match!");
8889 // Note that this correctly re-maps both when we do a swap and when
8890 // we observe the other side of the swap above. We rely on that to
8891 // avoid swapping the members of the input list directly.
8892 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8895 // Map the input's dword into the correct half.
8896 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8897 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8899 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8901 "Previous placement doesn't match!");
8904 // And just directly shift any other-half mask elements to be same-half
8905 // as we will have mirrored the dword containing the element into the
8906 // same position within that half.
8907 for (int &M : HalfMask)
8908 if (M >= SourceOffset && M < SourceOffset + 4) {
8909 M = M - SourceOffset + DestOffset;
8910 assert(M >= 0 && "This should never wrap below zero!");
8915 // Ensure we have the input in a viable dword of its current half. This
8916 // is particularly tricky because the original position may be clobbered
8917 // by inputs being moved and *staying* in that half.
8918 if (IncomingInputs.size() == 1) {
8919 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8920 int InputFixed = std::find(std::begin(SourceHalfMask),
8921 std::end(SourceHalfMask), -1) -
8922 std::begin(SourceHalfMask) + SourceOffset;
8923 SourceHalfMask[InputFixed - SourceOffset] =
8924 IncomingInputs[0] - SourceOffset;
8925 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8927 IncomingInputs[0] = InputFixed;
8929 } else if (IncomingInputs.size() == 2) {
8930 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8931 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8932 // We have two non-adjacent or clobbered inputs we need to extract from
8933 // the source half. To do this, we need to map them into some adjacent
8934 // dword slot in the source mask.
8935 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8936 IncomingInputs[1] - SourceOffset};
8938 // If there is a free slot in the source half mask adjacent to one of
8939 // the inputs, place the other input in it. We use (Index XOR 1) to
8940 // compute an adjacent index.
8941 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8942 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8943 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8944 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8945 InputsFixed[1] = InputsFixed[0] ^ 1;
8946 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8947 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8948 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8949 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8950 InputsFixed[0] = InputsFixed[1] ^ 1;
8951 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8952 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8953 // The two inputs are in the same DWord but it is clobbered and the
8954 // adjacent DWord isn't used at all. Move both inputs to the free
8956 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8957 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8958 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8959 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8961 // The only way we hit this point is if there is no clobbering
8962 // (because there are no off-half inputs to this half) and there is no
8963 // free slot adjacent to one of the inputs. In this case, we have to
8964 // swap an input with a non-input.
8965 for (int i = 0; i < 4; ++i)
8966 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8967 "We can't handle any clobbers here!");
8968 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8969 "Cannot have adjacent inputs here!");
8971 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8972 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8974 // We also have to update the final source mask in this case because
8975 // it may need to undo the above swap.
8976 for (int &M : FinalSourceHalfMask)
8977 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8978 M = InputsFixed[1] + SourceOffset;
8979 else if (M == InputsFixed[1] + SourceOffset)
8980 M = (InputsFixed[0] ^ 1) + SourceOffset;
8982 InputsFixed[1] = InputsFixed[0] ^ 1;
8985 // Point everything at the fixed inputs.
8986 for (int &M : HalfMask)
8987 if (M == IncomingInputs[0])
8988 M = InputsFixed[0] + SourceOffset;
8989 else if (M == IncomingInputs[1])
8990 M = InputsFixed[1] + SourceOffset;
8992 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8993 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8996 llvm_unreachable("Unhandled input size!");
8999 // Now hoist the DWord down to the right half.
9000 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9001 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9002 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9003 for (int &M : HalfMask)
9004 for (int Input : IncomingInputs)
9006 M = FreeDWord * 2 + Input % 2;
9008 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9009 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9010 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9011 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9013 // Now enact all the shuffles we've computed to move the inputs into their
9015 if (!isNoopShuffleMask(PSHUFLMask))
9016 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9017 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
9018 if (!isNoopShuffleMask(PSHUFHMask))
9019 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9020 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
9021 if (!isNoopShuffleMask(PSHUFDMask))
9022 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9023 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
9024 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
9025 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9027 // At this point, each half should contain all its inputs, and we can then
9028 // just shuffle them into their final position.
9029 assert(std::count_if(LoMask.begin(), LoMask.end(),
9030 [](int M) { return M >= 4; }) == 0 &&
9031 "Failed to lift all the high half inputs to the low mask!");
9032 assert(std::count_if(HiMask.begin(), HiMask.end(),
9033 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9034 "Failed to lift all the low half inputs to the high mask!");
9036 // Do a half shuffle for the low mask.
9037 if (!isNoopShuffleMask(LoMask))
9038 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9039 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9041 // Do a half shuffle with the high mask after shifting its values down.
9042 for (int &M : HiMask)
9045 if (!isNoopShuffleMask(HiMask))
9046 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9047 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9052 /// \brief Detect whether the mask pattern should be lowered through
9055 /// This essentially tests whether viewing the mask as an interleaving of two
9056 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9057 /// lowering it through interleaving is a significantly better strategy.
9058 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9059 int NumEvenInputs[2] = {0, 0};
9060 int NumOddInputs[2] = {0, 0};
9061 int NumLoInputs[2] = {0, 0};
9062 int NumHiInputs[2] = {0, 0};
9063 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9067 int InputIdx = Mask[i] >= Size;
9070 ++NumLoInputs[InputIdx];
9072 ++NumHiInputs[InputIdx];
9075 ++NumEvenInputs[InputIdx];
9077 ++NumOddInputs[InputIdx];
9080 // The minimum number of cross-input results for both the interleaved and
9081 // split cases. If interleaving results in fewer cross-input results, return
9083 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9084 NumEvenInputs[0] + NumOddInputs[1]);
9085 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9086 NumLoInputs[0] + NumHiInputs[1]);
9087 return InterleavedCrosses < SplitCrosses;
9090 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9092 /// This strategy only works when the inputs from each vector fit into a single
9093 /// half of that vector, and generally there are not so many inputs as to leave
9094 /// the in-place shuffles required highly constrained (and thus expensive). It
9095 /// shifts all the inputs into a single side of both input vectors and then
9096 /// uses an unpack to interleave these inputs in a single vector. At that
9097 /// point, we will fall back on the generic single input shuffle lowering.
9098 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9100 MutableArrayRef<int> Mask,
9101 const X86Subtarget *Subtarget,
9102 SelectionDAG &DAG) {
9103 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9104 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9105 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9106 for (int i = 0; i < 8; ++i)
9107 if (Mask[i] >= 0 && Mask[i] < 4)
9108 LoV1Inputs.push_back(i);
9109 else if (Mask[i] >= 4 && Mask[i] < 8)
9110 HiV1Inputs.push_back(i);
9111 else if (Mask[i] >= 8 && Mask[i] < 12)
9112 LoV2Inputs.push_back(i);
9113 else if (Mask[i] >= 12)
9114 HiV2Inputs.push_back(i);
9116 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9117 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9120 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9121 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9122 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9124 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9125 HiV1Inputs.size() + HiV2Inputs.size();
9127 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9128 ArrayRef<int> HiInputs, bool MoveToLo,
9130 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9131 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9132 if (BadInputs.empty())
9135 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9136 int MoveOffset = MoveToLo ? 0 : 4;
9138 if (GoodInputs.empty()) {
9139 for (int BadInput : BadInputs) {
9140 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9141 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9144 if (GoodInputs.size() == 2) {
9145 // If the low inputs are spread across two dwords, pack them into
9147 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9148 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9149 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9150 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9152 // Otherwise pin the good inputs.
9153 for (int GoodInput : GoodInputs)
9154 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9157 if (BadInputs.size() == 2) {
9158 // If we have two bad inputs then there may be either one or two good
9159 // inputs fixed in place. Find a fixed input, and then find the *other*
9160 // two adjacent indices by using modular arithmetic.
9162 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9163 [](int M) { return M >= 0; }) -
9164 std::begin(MoveMask);
9166 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9167 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9168 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9169 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9170 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9171 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9172 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9174 assert(BadInputs.size() == 1 && "All sizes handled");
9175 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9176 std::end(MoveMask), -1) -
9177 std::begin(MoveMask);
9178 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9179 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9183 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9186 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9188 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9191 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9192 // cross-half traffic in the final shuffle.
9194 // Munge the mask to be a single-input mask after the unpack merges the
9198 M = 2 * (M % 4) + (M / 8);
9200 return DAG.getVectorShuffle(
9201 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9202 DL, MVT::v8i16, V1, V2),
9203 DAG.getUNDEF(MVT::v8i16), Mask);
9206 /// \brief Generic lowering of 8-lane i16 shuffles.
9208 /// This handles both single-input shuffles and combined shuffle/blends with
9209 /// two inputs. The single input shuffles are immediately delegated to
9210 /// a dedicated lowering routine.
9212 /// The blends are lowered in one of three fundamental ways. If there are few
9213 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9214 /// of the input is significantly cheaper when lowered as an interleaving of
9215 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9216 /// halves of the inputs separately (making them have relatively few inputs)
9217 /// and then concatenate them.
9218 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9219 const X86Subtarget *Subtarget,
9220 SelectionDAG &DAG) {
9222 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9223 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9224 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9225 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9226 ArrayRef<int> OrigMask = SVOp->getMask();
9227 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9228 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9229 MutableArrayRef<int> Mask(MaskStorage);
9231 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9233 // Whenever we can lower this as a zext, that instruction is strictly faster
9234 // than any alternative.
9235 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9236 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9239 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9240 auto isV2 = [](int M) { return M >= 8; };
9242 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9243 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9245 if (NumV2Inputs == 0)
9246 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9248 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9249 "to be V1-input shuffles.");
9251 // Try to use byte shift instructions.
9252 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9253 DL, MVT::v8i16, V1, V2, Mask, DAG))
9256 // There are special ways we can lower some single-element blends.
9257 if (NumV2Inputs == 1)
9258 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9259 Mask, Subtarget, DAG))
9262 // Use dedicated unpack instructions for masks that match their pattern.
9263 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9264 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9265 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9266 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9268 if (Subtarget->hasSSE41())
9269 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9273 // Try to use byte rotation instructions.
9274 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9275 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9278 if (NumV1Inputs + NumV2Inputs <= 4)
9279 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9281 // Check whether an interleaving lowering is likely to be more efficient.
9282 // This isn't perfect but it is a strong heuristic that tends to work well on
9283 // the kinds of shuffles that show up in practice.
9285 // FIXME: Handle 1x, 2x, and 4x interleaving.
9286 if (shouldLowerAsInterleaving(Mask)) {
9287 // FIXME: Figure out whether we should pack these into the low or high
9290 int EMask[8], OMask[8];
9291 for (int i = 0; i < 4; ++i) {
9292 EMask[i] = Mask[2*i];
9293 OMask[i] = Mask[2*i + 1];
9298 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9299 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9301 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9304 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9305 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9307 for (int i = 0; i < 4; ++i) {
9308 LoBlendMask[i] = Mask[i];
9309 HiBlendMask[i] = Mask[i + 4];
9312 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9313 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9314 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9315 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9317 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9318 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9321 /// \brief Check whether a compaction lowering can be done by dropping even
9322 /// elements and compute how many times even elements must be dropped.
9324 /// This handles shuffles which take every Nth element where N is a power of
9325 /// two. Example shuffle masks:
9327 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9328 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9329 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9330 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9331 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9332 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9334 /// Any of these lanes can of course be undef.
9336 /// This routine only supports N <= 3.
9337 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9340 /// \returns N above, or the number of times even elements must be dropped if
9341 /// there is such a number. Otherwise returns zero.
9342 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9343 // Figure out whether we're looping over two inputs or just one.
9344 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9346 // The modulus for the shuffle vector entries is based on whether this is
9347 // a single input or not.
9348 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9349 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9350 "We should only be called with masks with a power-of-2 size!");
9352 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9354 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9355 // and 2^3 simultaneously. This is because we may have ambiguity with
9356 // partially undef inputs.
9357 bool ViableForN[3] = {true, true, true};
9359 for (int i = 0, e = Mask.size(); i < e; ++i) {
9360 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9365 bool IsAnyViable = false;
9366 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9367 if (ViableForN[j]) {
9370 // The shuffle mask must be equal to (i * 2^N) % M.
9371 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9374 ViableForN[j] = false;
9376 // Early exit if we exhaust the possible powers of two.
9381 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9385 // Return 0 as there is no viable power of two.
9389 /// \brief Generic lowering of v16i8 shuffles.
9391 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9392 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9393 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9394 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9396 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9397 const X86Subtarget *Subtarget,
9398 SelectionDAG &DAG) {
9400 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9401 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9402 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9403 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9404 ArrayRef<int> OrigMask = SVOp->getMask();
9405 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9407 // Try to use byte shift instructions.
9408 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9409 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9412 // Try to use byte rotation instructions.
9413 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9414 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9417 // Try to use a zext lowering.
9418 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9419 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9422 int MaskStorage[16] = {
9423 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9424 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9425 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9426 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9427 MutableArrayRef<int> Mask(MaskStorage);
9428 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9429 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9432 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9434 // For single-input shuffles, there are some nicer lowering tricks we can use.
9435 if (NumV2Elements == 0) {
9436 // Check for being able to broadcast a single element.
9437 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9438 Mask, Subtarget, DAG))
9441 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9442 // Notably, this handles splat and partial-splat shuffles more efficiently.
9443 // However, it only makes sense if the pre-duplication shuffle simplifies
9444 // things significantly. Currently, this means we need to be able to
9445 // express the pre-duplication shuffle as an i16 shuffle.
9447 // FIXME: We should check for other patterns which can be widened into an
9448 // i16 shuffle as well.
9449 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9450 for (int i = 0; i < 16; i += 2)
9451 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9456 auto tryToWidenViaDuplication = [&]() -> SDValue {
9457 if (!canWidenViaDuplication(Mask))
9459 SmallVector<int, 4> LoInputs;
9460 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9461 [](int M) { return M >= 0 && M < 8; });
9462 std::sort(LoInputs.begin(), LoInputs.end());
9463 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9465 SmallVector<int, 4> HiInputs;
9466 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9467 [](int M) { return M >= 8; });
9468 std::sort(HiInputs.begin(), HiInputs.end());
9469 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9472 bool TargetLo = LoInputs.size() >= HiInputs.size();
9473 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9474 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9476 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9477 SmallDenseMap<int, int, 8> LaneMap;
9478 for (int I : InPlaceInputs) {
9479 PreDupI16Shuffle[I/2] = I/2;
9482 int j = TargetLo ? 0 : 4, je = j + 4;
9483 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9484 // Check if j is already a shuffle of this input. This happens when
9485 // there are two adjacent bytes after we move the low one.
9486 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9487 // If we haven't yet mapped the input, search for a slot into which
9489 while (j < je && PreDupI16Shuffle[j] != -1)
9493 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9496 // Map this input with the i16 shuffle.
9497 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9500 // Update the lane map based on the mapping we ended up with.
9501 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9504 ISD::BITCAST, DL, MVT::v16i8,
9505 DAG.getVectorShuffle(MVT::v8i16, DL,
9506 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9507 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9509 // Unpack the bytes to form the i16s that will be shuffled into place.
9510 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9511 MVT::v16i8, V1, V1);
9513 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9514 for (int i = 0; i < 16; ++i)
9515 if (Mask[i] != -1) {
9516 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9517 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9518 if (PostDupI16Shuffle[i / 2] == -1)
9519 PostDupI16Shuffle[i / 2] = MappedMask;
9521 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9522 "Conflicting entrties in the original shuffle!");
9525 ISD::BITCAST, DL, MVT::v16i8,
9526 DAG.getVectorShuffle(MVT::v8i16, DL,
9527 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9528 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9530 if (SDValue V = tryToWidenViaDuplication())
9534 // Check whether an interleaving lowering is likely to be more efficient.
9535 // This isn't perfect but it is a strong heuristic that tends to work well on
9536 // the kinds of shuffles that show up in practice.
9538 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9539 if (shouldLowerAsInterleaving(Mask)) {
9540 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9541 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9543 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9544 return (M >= 8 && M < 16) || M >= 24;
9546 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9547 -1, -1, -1, -1, -1, -1, -1, -1};
9548 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9549 -1, -1, -1, -1, -1, -1, -1, -1};
9550 bool UnpackLo = NumLoHalf >= NumHiHalf;
9551 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9552 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9553 for (int i = 0; i < 8; ++i) {
9554 TargetEMask[i] = Mask[2 * i];
9555 TargetOMask[i] = Mask[2 * i + 1];
9558 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9559 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9561 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9562 MVT::v16i8, Evens, Odds);
9565 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9566 // with PSHUFB. It is important to do this before we attempt to generate any
9567 // blends but after all of the single-input lowerings. If the single input
9568 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9569 // want to preserve that and we can DAG combine any longer sequences into
9570 // a PSHUFB in the end. But once we start blending from multiple inputs,
9571 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9572 // and there are *very* few patterns that would actually be faster than the
9573 // PSHUFB approach because of its ability to zero lanes.
9575 // FIXME: The only exceptions to the above are blends which are exact
9576 // interleavings with direct instructions supporting them. We currently don't
9577 // handle those well here.
9578 if (Subtarget->hasSSSE3()) {
9581 for (int i = 0; i < 16; ++i)
9582 if (Mask[i] == -1) {
9583 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9585 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9587 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9589 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9590 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9591 if (isSingleInputShuffleMask(Mask))
9592 return V1; // Single inputs are easy.
9594 // Otherwise, blend the two.
9595 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9596 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9597 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9600 // There are special ways we can lower some single-element blends.
9601 if (NumV2Elements == 1)
9602 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9603 Mask, Subtarget, DAG))
9606 // Check whether a compaction lowering can be done. This handles shuffles
9607 // which take every Nth element for some even N. See the helper function for
9610 // We special case these as they can be particularly efficiently handled with
9611 // the PACKUSB instruction on x86 and they show up in common patterns of
9612 // rearranging bytes to truncate wide elements.
9613 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9614 // NumEvenDrops is the power of two stride of the elements. Another way of
9615 // thinking about it is that we need to drop the even elements this many
9616 // times to get the original input.
9617 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9619 // First we need to zero all the dropped bytes.
9620 assert(NumEvenDrops <= 3 &&
9621 "No support for dropping even elements more than 3 times.");
9622 // We use the mask type to pick which bytes are preserved based on how many
9623 // elements are dropped.
9624 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9625 SDValue ByteClearMask =
9626 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9627 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9628 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9630 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9632 // Now pack things back together.
9633 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9634 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9635 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9636 for (int i = 1; i < NumEvenDrops; ++i) {
9637 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9638 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9644 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9645 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9646 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9647 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9649 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9650 MutableArrayRef<int> V1HalfBlendMask,
9651 MutableArrayRef<int> V2HalfBlendMask) {
9652 for (int i = 0; i < 8; ++i)
9653 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9654 V1HalfBlendMask[i] = HalfMask[i];
9656 } else if (HalfMask[i] >= 16) {
9657 V2HalfBlendMask[i] = HalfMask[i] - 16;
9658 HalfMask[i] = i + 8;
9661 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9662 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9664 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9666 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9667 MutableArrayRef<int> HiBlendMask) {
9669 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9670 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9672 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9673 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9674 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9675 [](int M) { return M >= 0 && M % 2 == 1; })) {
9676 // Use a mask to drop the high bytes.
9677 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9678 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9679 DAG.getConstant(0x00FF, MVT::v8i16));
9681 // This will be a single vector shuffle instead of a blend so nuke V2.
9682 V2 = DAG.getUNDEF(MVT::v8i16);
9684 // Squash the masks to point directly into V1.
9685 for (int &M : LoBlendMask)
9688 for (int &M : HiBlendMask)
9692 // Otherwise just unpack the low half of V into V1 and the high half into
9693 // V2 so that we can blend them as i16s.
9694 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9695 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9696 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9697 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9700 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9701 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9702 return std::make_pair(BlendedLo, BlendedHi);
9704 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9705 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9706 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9708 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9709 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9711 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9714 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9716 /// This routine breaks down the specific type of 128-bit shuffle and
9717 /// dispatches to the lowering routines accordingly.
9718 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9719 MVT VT, const X86Subtarget *Subtarget,
9720 SelectionDAG &DAG) {
9721 switch (VT.SimpleTy) {
9723 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9725 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9727 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9729 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9731 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9733 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9736 llvm_unreachable("Unimplemented!");
9740 /// \brief Helper function to test whether a shuffle mask could be
9741 /// simplified by widening the elements being shuffled.
9743 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9744 /// leaves it in an unspecified state.
9746 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9747 /// shuffle masks. The latter have the special property of a '-2' representing
9748 /// a zero-ed lane of a vector.
9749 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9750 SmallVectorImpl<int> &WidenedMask) {
9751 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9752 // If both elements are undef, its trivial.
9753 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9754 WidenedMask.push_back(SM_SentinelUndef);
9758 // Check for an undef mask and a mask value properly aligned to fit with
9759 // a pair of values. If we find such a case, use the non-undef mask's value.
9760 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9761 WidenedMask.push_back(Mask[i + 1] / 2);
9764 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9765 WidenedMask.push_back(Mask[i] / 2);
9769 // When zeroing, we need to spread the zeroing across both lanes to widen.
9770 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9771 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9772 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9773 WidenedMask.push_back(SM_SentinelZero);
9779 // Finally check if the two mask values are adjacent and aligned with
9781 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9782 WidenedMask.push_back(Mask[i] / 2);
9786 // Otherwise we can't safely widen the elements used in this shuffle.
9789 assert(WidenedMask.size() == Mask.size() / 2 &&
9790 "Incorrect size of mask after widening the elements!");
9795 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9797 /// This routine just extracts two subvectors, shuffles them independently, and
9798 /// then concatenates them back together. This should work effectively with all
9799 /// AVX vector shuffle types.
9800 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9801 SDValue V2, ArrayRef<int> Mask,
9802 SelectionDAG &DAG) {
9803 assert(VT.getSizeInBits() >= 256 &&
9804 "Only for 256-bit or wider vector shuffles!");
9805 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9806 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9808 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9809 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9811 int NumElements = VT.getVectorNumElements();
9812 int SplitNumElements = NumElements / 2;
9813 MVT ScalarVT = VT.getScalarType();
9814 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9816 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9817 DAG.getIntPtrConstant(0));
9818 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9819 DAG.getIntPtrConstant(SplitNumElements));
9820 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9821 DAG.getIntPtrConstant(0));
9822 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9823 DAG.getIntPtrConstant(SplitNumElements));
9825 // Now create two 4-way blends of these half-width vectors.
9826 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9827 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9828 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9829 for (int i = 0; i < SplitNumElements; ++i) {
9830 int M = HalfMask[i];
9831 if (M >= NumElements) {
9832 if (M >= NumElements + SplitNumElements)
9836 V2BlendMask.push_back(M - NumElements);
9837 V1BlendMask.push_back(-1);
9838 BlendMask.push_back(SplitNumElements + i);
9839 } else if (M >= 0) {
9840 if (M >= SplitNumElements)
9844 V2BlendMask.push_back(-1);
9845 V1BlendMask.push_back(M);
9846 BlendMask.push_back(i);
9848 V2BlendMask.push_back(-1);
9849 V1BlendMask.push_back(-1);
9850 BlendMask.push_back(-1);
9854 // Because the lowering happens after all combining takes place, we need to
9855 // manually combine these blend masks as much as possible so that we create
9856 // a minimal number of high-level vector shuffle nodes.
9858 // First try just blending the halves of V1 or V2.
9859 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9860 return DAG.getUNDEF(SplitVT);
9861 if (!UseLoV2 && !UseHiV2)
9862 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9863 if (!UseLoV1 && !UseHiV1)
9864 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9866 SDValue V1Blend, V2Blend;
9867 if (UseLoV1 && UseHiV1) {
9869 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9871 // We only use half of V1 so map the usage down into the final blend mask.
9872 V1Blend = UseLoV1 ? LoV1 : HiV1;
9873 for (int i = 0; i < SplitNumElements; ++i)
9874 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9875 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9877 if (UseLoV2 && UseHiV2) {
9879 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9881 // We only use half of V2 so map the usage down into the final blend mask.
9882 V2Blend = UseLoV2 ? LoV2 : HiV2;
9883 for (int i = 0; i < SplitNumElements; ++i)
9884 if (BlendMask[i] >= SplitNumElements)
9885 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9887 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9889 SDValue Lo = HalfBlend(LoMask);
9890 SDValue Hi = HalfBlend(HiMask);
9891 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9894 /// \brief Either split a vector in halves or decompose the shuffles and the
9897 /// This is provided as a good fallback for many lowerings of non-single-input
9898 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9899 /// between splitting the shuffle into 128-bit components and stitching those
9900 /// back together vs. extracting the single-input shuffles and blending those
9902 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9903 SDValue V2, ArrayRef<int> Mask,
9904 SelectionDAG &DAG) {
9905 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9906 "lower single-input shuffles as it "
9907 "could then recurse on itself.");
9908 int Size = Mask.size();
9910 // If this can be modeled as a broadcast of two elements followed by a blend,
9911 // prefer that lowering. This is especially important because broadcasts can
9912 // often fold with memory operands.
9913 auto DoBothBroadcast = [&] {
9914 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9917 if (V2BroadcastIdx == -1)
9918 V2BroadcastIdx = M - Size;
9919 else if (M - Size != V2BroadcastIdx)
9921 } else if (M >= 0) {
9922 if (V1BroadcastIdx == -1)
9924 else if (M != V1BroadcastIdx)
9929 if (DoBothBroadcast())
9930 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9933 // If the inputs all stem from a single 128-bit lane of each input, then we
9934 // split them rather than blending because the split will decompose to
9935 // unusually few instructions.
9936 int LaneCount = VT.getSizeInBits() / 128;
9937 int LaneSize = Size / LaneCount;
9938 SmallBitVector LaneInputs[2];
9939 LaneInputs[0].resize(LaneCount, false);
9940 LaneInputs[1].resize(LaneCount, false);
9941 for (int i = 0; i < Size; ++i)
9943 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9944 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9945 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9947 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9948 // that the decomposed single-input shuffles don't end up here.
9949 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9952 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9953 /// a permutation and blend of those lanes.
9955 /// This essentially blends the out-of-lane inputs to each lane into the lane
9956 /// from a permuted copy of the vector. This lowering strategy results in four
9957 /// instructions in the worst case for a single-input cross lane shuffle which
9958 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9959 /// of. Special cases for each particular shuffle pattern should be handled
9960 /// prior to trying this lowering.
9961 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9962 SDValue V1, SDValue V2,
9964 SelectionDAG &DAG) {
9965 // FIXME: This should probably be generalized for 512-bit vectors as well.
9966 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9967 int LaneSize = Mask.size() / 2;
9969 // If there are only inputs from one 128-bit lane, splitting will in fact be
9970 // less expensive. The flags track wether the given lane contains an element
9971 // that crosses to another lane.
9972 bool LaneCrossing[2] = {false, false};
9973 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9974 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9975 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9976 if (!LaneCrossing[0] || !LaneCrossing[1])
9977 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9979 if (isSingleInputShuffleMask(Mask)) {
9980 SmallVector<int, 32> FlippedBlendMask;
9981 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9982 FlippedBlendMask.push_back(
9983 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9985 : Mask[i] % LaneSize +
9986 (i / LaneSize) * LaneSize + Size));
9988 // Flip the vector, and blend the results which should now be in-lane. The
9989 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9990 // 5 for the high source. The value 3 selects the high half of source 2 and
9991 // the value 2 selects the low half of source 2. We only use source 2 to
9992 // allow folding it into a memory operand.
9993 unsigned PERMMask = 3 | 2 << 4;
9994 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9995 V1, DAG.getConstant(PERMMask, MVT::i8));
9996 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9999 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10000 // will be handled by the above logic and a blend of the results, much like
10001 // other patterns in AVX.
10002 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10005 /// \brief Handle lowering 2-lane 128-bit shuffles.
10006 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10007 SDValue V2, ArrayRef<int> Mask,
10008 const X86Subtarget *Subtarget,
10009 SelectionDAG &DAG) {
10010 // Blends are faster and handle all the non-lane-crossing cases.
10011 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10015 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10016 VT.getVectorNumElements() / 2);
10017 // Check for patterns which can be matched with a single insert of a 128-bit
10019 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
10020 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
10021 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10022 DAG.getIntPtrConstant(0));
10023 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10024 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
10025 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10027 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
10028 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10029 DAG.getIntPtrConstant(0));
10030 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
10031 DAG.getIntPtrConstant(2));
10032 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10035 // Otherwise form a 128-bit permutation.
10036 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
10037 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10038 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10039 DAG.getConstant(PermMask, MVT::i8));
10042 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10043 /// shuffling each lane.
10045 /// This will only succeed when the result of fixing the 128-bit lanes results
10046 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10047 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10048 /// the lane crosses early and then use simpler shuffles within each lane.
10050 /// FIXME: It might be worthwhile at some point to support this without
10051 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10052 /// in x86 only floating point has interesting non-repeating shuffles, and even
10053 /// those are still *marginally* more expensive.
10054 static SDValue lowerVectorShuffleByMerging128BitLanes(
10055 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10056 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10057 assert(!isSingleInputShuffleMask(Mask) &&
10058 "This is only useful with multiple inputs.");
10060 int Size = Mask.size();
10061 int LaneSize = 128 / VT.getScalarSizeInBits();
10062 int NumLanes = Size / LaneSize;
10063 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10065 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10066 // check whether the in-128-bit lane shuffles share a repeating pattern.
10067 SmallVector<int, 4> Lanes;
10068 Lanes.resize(NumLanes, -1);
10069 SmallVector<int, 4> InLaneMask;
10070 InLaneMask.resize(LaneSize, -1);
10071 for (int i = 0; i < Size; ++i) {
10075 int j = i / LaneSize;
10077 if (Lanes[j] < 0) {
10078 // First entry we've seen for this lane.
10079 Lanes[j] = Mask[i] / LaneSize;
10080 } else if (Lanes[j] != Mask[i] / LaneSize) {
10081 // This doesn't match the lane selected previously!
10085 // Check that within each lane we have a consistent shuffle mask.
10086 int k = i % LaneSize;
10087 if (InLaneMask[k] < 0) {
10088 InLaneMask[k] = Mask[i] % LaneSize;
10089 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10090 // This doesn't fit a repeating in-lane mask.
10095 // First shuffle the lanes into place.
10096 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10097 VT.getSizeInBits() / 64);
10098 SmallVector<int, 8> LaneMask;
10099 LaneMask.resize(NumLanes * 2, -1);
10100 for (int i = 0; i < NumLanes; ++i)
10101 if (Lanes[i] >= 0) {
10102 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10103 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10106 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10107 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10108 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10110 // Cast it back to the type we actually want.
10111 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10113 // Now do a simple shuffle that isn't lane crossing.
10114 SmallVector<int, 8> NewMask;
10115 NewMask.resize(Size, -1);
10116 for (int i = 0; i < Size; ++i)
10118 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10119 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10120 "Must not introduce lane crosses at this point!");
10122 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10125 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10128 /// This returns true if the elements from a particular input are already in the
10129 /// slot required by the given mask and require no permutation.
10130 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10131 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10132 int Size = Mask.size();
10133 for (int i = 0; i < Size; ++i)
10134 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10140 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10142 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10143 /// isn't available.
10144 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10145 const X86Subtarget *Subtarget,
10146 SelectionDAG &DAG) {
10148 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10149 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10150 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10151 ArrayRef<int> Mask = SVOp->getMask();
10152 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10154 SmallVector<int, 4> WidenedMask;
10155 if (canWidenShuffleElements(Mask, WidenedMask))
10156 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10159 if (isSingleInputShuffleMask(Mask)) {
10160 // Check for being able to broadcast a single element.
10161 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10162 Mask, Subtarget, DAG))
10165 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10166 // Non-half-crossing single input shuffles can be lowerid with an
10167 // interleaved permutation.
10168 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10169 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10170 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10171 DAG.getConstant(VPERMILPMask, MVT::i8));
10174 // With AVX2 we have direct support for this permutation.
10175 if (Subtarget->hasAVX2())
10176 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10177 getV4X86ShuffleImm8ForMask(Mask, DAG));
10179 // Otherwise, fall back.
10180 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10184 // X86 has dedicated unpack instructions that can handle specific blend
10185 // operations: UNPCKH and UNPCKL.
10186 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10187 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10188 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10189 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10191 // If we have a single input to the zero element, insert that into V1 if we
10192 // can do so cheaply.
10193 int NumV2Elements =
10194 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10195 if (NumV2Elements == 1 && Mask[0] >= 4)
10196 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10197 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10200 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10204 // Check if the blend happens to exactly fit that of SHUFPD.
10205 if ((Mask[0] == -1 || Mask[0] < 2) &&
10206 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10207 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10208 (Mask[3] == -1 || Mask[3] >= 6)) {
10209 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10210 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10211 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10212 DAG.getConstant(SHUFPDMask, MVT::i8));
10214 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10215 (Mask[1] == -1 || Mask[1] < 2) &&
10216 (Mask[2] == -1 || Mask[2] >= 6) &&
10217 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10218 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10219 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10220 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10221 DAG.getConstant(SHUFPDMask, MVT::i8));
10224 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10225 // shuffle. However, if we have AVX2 and either inputs are already in place,
10226 // we will be able to shuffle even across lanes the other input in a single
10227 // instruction so skip this pattern.
10228 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10229 isShuffleMaskInputInPlace(1, Mask))))
10230 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10231 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10234 // If we have AVX2 then we always want to lower with a blend because an v4 we
10235 // can fully permute the elements.
10236 if (Subtarget->hasAVX2())
10237 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10240 // Otherwise fall back on generic lowering.
10241 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10244 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10246 /// This routine is only called when we have AVX2 and thus a reasonable
10247 /// instruction set for v4i64 shuffling..
10248 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10249 const X86Subtarget *Subtarget,
10250 SelectionDAG &DAG) {
10252 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10253 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10254 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10255 ArrayRef<int> Mask = SVOp->getMask();
10256 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10257 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10259 SmallVector<int, 4> WidenedMask;
10260 if (canWidenShuffleElements(Mask, WidenedMask))
10261 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10264 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10268 // Check for being able to broadcast a single element.
10269 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10270 Mask, Subtarget, DAG))
10273 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10274 // use lower latency instructions that will operate on both 128-bit lanes.
10275 SmallVector<int, 2> RepeatedMask;
10276 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10277 if (isSingleInputShuffleMask(Mask)) {
10278 int PSHUFDMask[] = {-1, -1, -1, -1};
10279 for (int i = 0; i < 2; ++i)
10280 if (RepeatedMask[i] >= 0) {
10281 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10282 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10284 return DAG.getNode(
10285 ISD::BITCAST, DL, MVT::v4i64,
10286 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10287 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10288 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10291 // Use dedicated unpack instructions for masks that match their pattern.
10292 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10293 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10294 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10295 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10298 // AVX2 provides a direct instruction for permuting a single input across
10300 if (isSingleInputShuffleMask(Mask))
10301 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10302 getV4X86ShuffleImm8ForMask(Mask, DAG));
10304 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10305 // shuffle. However, if we have AVX2 and either inputs are already in place,
10306 // we will be able to shuffle even across lanes the other input in a single
10307 // instruction so skip this pattern.
10308 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10309 isShuffleMaskInputInPlace(1, Mask))))
10310 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10311 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10314 // Otherwise fall back on generic blend lowering.
10315 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10319 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10321 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10322 /// isn't available.
10323 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10324 const X86Subtarget *Subtarget,
10325 SelectionDAG &DAG) {
10327 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10328 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10329 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10330 ArrayRef<int> Mask = SVOp->getMask();
10331 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10333 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10337 // Check for being able to broadcast a single element.
10338 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10339 Mask, Subtarget, DAG))
10342 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10343 // options to efficiently lower the shuffle.
10344 SmallVector<int, 4> RepeatedMask;
10345 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10346 assert(RepeatedMask.size() == 4 &&
10347 "Repeated masks must be half the mask width!");
10348 if (isSingleInputShuffleMask(Mask))
10349 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10350 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10352 // Use dedicated unpack instructions for masks that match their pattern.
10353 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10354 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10355 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10356 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10358 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10359 // have already handled any direct blends. We also need to squash the
10360 // repeated mask into a simulated v4f32 mask.
10361 for (int i = 0; i < 4; ++i)
10362 if (RepeatedMask[i] >= 8)
10363 RepeatedMask[i] -= 4;
10364 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10367 // If we have a single input shuffle with different shuffle patterns in the
10368 // two 128-bit lanes use the variable mask to VPERMILPS.
10369 if (isSingleInputShuffleMask(Mask)) {
10370 SDValue VPermMask[8];
10371 for (int i = 0; i < 8; ++i)
10372 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10373 : DAG.getConstant(Mask[i], MVT::i32);
10374 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10375 return DAG.getNode(
10376 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10377 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10379 if (Subtarget->hasAVX2())
10380 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10381 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10382 DAG.getNode(ISD::BUILD_VECTOR, DL,
10383 MVT::v8i32, VPermMask)),
10386 // Otherwise, fall back.
10387 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10391 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10393 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10394 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10397 // If we have AVX2 then we always want to lower with a blend because at v8 we
10398 // can fully permute the elements.
10399 if (Subtarget->hasAVX2())
10400 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10403 // Otherwise fall back on generic lowering.
10404 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10407 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10409 /// This routine is only called when we have AVX2 and thus a reasonable
10410 /// instruction set for v8i32 shuffling..
10411 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10412 const X86Subtarget *Subtarget,
10413 SelectionDAG &DAG) {
10415 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10416 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10417 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10418 ArrayRef<int> Mask = SVOp->getMask();
10419 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10420 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10422 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10426 // Check for being able to broadcast a single element.
10427 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10428 Mask, Subtarget, DAG))
10431 // If the shuffle mask is repeated in each 128-bit lane we can use more
10432 // efficient instructions that mirror the shuffles across the two 128-bit
10434 SmallVector<int, 4> RepeatedMask;
10435 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10436 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10437 if (isSingleInputShuffleMask(Mask))
10438 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10439 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10441 // Use dedicated unpack instructions for masks that match their pattern.
10442 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10443 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10444 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10445 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10448 // If the shuffle patterns aren't repeated but it is a single input, directly
10449 // generate a cross-lane VPERMD instruction.
10450 if (isSingleInputShuffleMask(Mask)) {
10451 SDValue VPermMask[8];
10452 for (int i = 0; i < 8; ++i)
10453 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10454 : DAG.getConstant(Mask[i], MVT::i32);
10455 return DAG.getNode(
10456 X86ISD::VPERMV, DL, MVT::v8i32,
10457 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10460 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10462 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10463 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10466 // Otherwise fall back on generic blend lowering.
10467 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10471 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10473 /// This routine is only called when we have AVX2 and thus a reasonable
10474 /// instruction set for v16i16 shuffling..
10475 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10476 const X86Subtarget *Subtarget,
10477 SelectionDAG &DAG) {
10479 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10480 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10481 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10482 ArrayRef<int> Mask = SVOp->getMask();
10483 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10484 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10486 // Check for being able to broadcast a single element.
10487 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10488 Mask, Subtarget, DAG))
10491 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10495 // Use dedicated unpack instructions for masks that match their pattern.
10496 if (isShuffleEquivalent(Mask,
10497 // First 128-bit lane:
10498 0, 16, 1, 17, 2, 18, 3, 19,
10499 // Second 128-bit lane:
10500 8, 24, 9, 25, 10, 26, 11, 27))
10501 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10502 if (isShuffleEquivalent(Mask,
10503 // First 128-bit lane:
10504 4, 20, 5, 21, 6, 22, 7, 23,
10505 // Second 128-bit lane:
10506 12, 28, 13, 29, 14, 30, 15, 31))
10507 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10509 if (isSingleInputShuffleMask(Mask)) {
10510 // There are no generalized cross-lane shuffle operations available on i16
10512 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10513 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10516 SDValue PSHUFBMask[32];
10517 for (int i = 0; i < 16; ++i) {
10518 if (Mask[i] == -1) {
10519 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10523 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10524 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10525 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10526 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10528 return DAG.getNode(
10529 ISD::BITCAST, DL, MVT::v16i16,
10531 X86ISD::PSHUFB, DL, MVT::v32i8,
10532 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10533 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10536 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10538 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10539 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10542 // Otherwise fall back on generic lowering.
10543 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10546 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10548 /// This routine is only called when we have AVX2 and thus a reasonable
10549 /// instruction set for v32i8 shuffling..
10550 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10551 const X86Subtarget *Subtarget,
10552 SelectionDAG &DAG) {
10554 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10555 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10556 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10557 ArrayRef<int> Mask = SVOp->getMask();
10558 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10559 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10561 // Check for being able to broadcast a single element.
10562 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10563 Mask, Subtarget, DAG))
10566 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10570 // Use dedicated unpack instructions for masks that match their pattern.
10571 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10573 if (isShuffleEquivalent(
10575 // First 128-bit lane:
10576 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10577 // Second 128-bit lane:
10578 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10579 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10580 if (isShuffleEquivalent(
10582 // First 128-bit lane:
10583 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10584 // Second 128-bit lane:
10585 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10586 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10588 if (isSingleInputShuffleMask(Mask)) {
10589 // There are no generalized cross-lane shuffle operations available on i8
10591 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10592 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10595 SDValue PSHUFBMask[32];
10596 for (int i = 0; i < 32; ++i)
10599 ? DAG.getUNDEF(MVT::i8)
10600 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10602 return DAG.getNode(
10603 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10604 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10607 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10609 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10610 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10613 // Otherwise fall back on generic lowering.
10614 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10617 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10619 /// This routine either breaks down the specific type of a 256-bit x86 vector
10620 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10621 /// together based on the available instructions.
10622 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10623 MVT VT, const X86Subtarget *Subtarget,
10624 SelectionDAG &DAG) {
10626 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10627 ArrayRef<int> Mask = SVOp->getMask();
10629 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10630 // check for those subtargets here and avoid much of the subtarget querying in
10631 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10632 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10633 // floating point types there eventually, just immediately cast everything to
10634 // a float and operate entirely in that domain.
10635 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10636 int ElementBits = VT.getScalarSizeInBits();
10637 if (ElementBits < 32)
10638 // No floating point type available, decompose into 128-bit vectors.
10639 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10641 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10642 VT.getVectorNumElements());
10643 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10644 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10645 return DAG.getNode(ISD::BITCAST, DL, VT,
10646 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10649 switch (VT.SimpleTy) {
10651 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10653 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10655 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10657 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10659 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10661 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10664 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10668 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10669 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10670 const X86Subtarget *Subtarget,
10671 SelectionDAG &DAG) {
10673 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10674 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10675 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10676 ArrayRef<int> Mask = SVOp->getMask();
10677 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10679 // FIXME: Implement direct support for this type!
10680 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10683 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10684 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10685 const X86Subtarget *Subtarget,
10686 SelectionDAG &DAG) {
10688 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10689 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10690 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10691 ArrayRef<int> Mask = SVOp->getMask();
10692 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10694 // FIXME: Implement direct support for this type!
10695 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10698 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10699 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10700 const X86Subtarget *Subtarget,
10701 SelectionDAG &DAG) {
10703 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10704 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10705 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10706 ArrayRef<int> Mask = SVOp->getMask();
10707 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10709 // FIXME: Implement direct support for this type!
10710 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10713 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10714 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10715 const X86Subtarget *Subtarget,
10716 SelectionDAG &DAG) {
10718 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10719 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10720 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10721 ArrayRef<int> Mask = SVOp->getMask();
10722 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10724 // FIXME: Implement direct support for this type!
10725 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10728 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10729 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10730 const X86Subtarget *Subtarget,
10731 SelectionDAG &DAG) {
10733 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10734 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10735 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10736 ArrayRef<int> Mask = SVOp->getMask();
10737 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10738 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10740 // FIXME: Implement direct support for this type!
10741 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10744 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10745 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10746 const X86Subtarget *Subtarget,
10747 SelectionDAG &DAG) {
10749 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10750 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10751 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10752 ArrayRef<int> Mask = SVOp->getMask();
10753 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10754 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10756 // FIXME: Implement direct support for this type!
10757 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10760 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10762 /// This routine either breaks down the specific type of a 512-bit x86 vector
10763 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10764 /// together based on the available instructions.
10765 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10766 MVT VT, const X86Subtarget *Subtarget,
10767 SelectionDAG &DAG) {
10769 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10770 ArrayRef<int> Mask = SVOp->getMask();
10771 assert(Subtarget->hasAVX512() &&
10772 "Cannot lower 512-bit vectors w/ basic ISA!");
10774 // Check for being able to broadcast a single element.
10775 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10776 Mask, Subtarget, DAG))
10779 // Dispatch to each element type for lowering. If we don't have supprot for
10780 // specific element type shuffles at 512 bits, immediately split them and
10781 // lower them. Each lowering routine of a given type is allowed to assume that
10782 // the requisite ISA extensions for that element type are available.
10783 switch (VT.SimpleTy) {
10785 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10787 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10789 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10791 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10793 if (Subtarget->hasBWI())
10794 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10797 if (Subtarget->hasBWI())
10798 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10802 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10805 // Otherwise fall back on splitting.
10806 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10809 /// \brief Top-level lowering for x86 vector shuffles.
10811 /// This handles decomposition, canonicalization, and lowering of all x86
10812 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10813 /// above in helper routines. The canonicalization attempts to widen shuffles
10814 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10815 /// s.t. only one of the two inputs needs to be tested, etc.
10816 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10817 SelectionDAG &DAG) {
10818 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10819 ArrayRef<int> Mask = SVOp->getMask();
10820 SDValue V1 = Op.getOperand(0);
10821 SDValue V2 = Op.getOperand(1);
10822 MVT VT = Op.getSimpleValueType();
10823 int NumElements = VT.getVectorNumElements();
10826 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10828 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10829 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10830 if (V1IsUndef && V2IsUndef)
10831 return DAG.getUNDEF(VT);
10833 // When we create a shuffle node we put the UNDEF node to second operand,
10834 // but in some cases the first operand may be transformed to UNDEF.
10835 // In this case we should just commute the node.
10837 return DAG.getCommutedVectorShuffle(*SVOp);
10839 // Check for non-undef masks pointing at an undef vector and make the masks
10840 // undef as well. This makes it easier to match the shuffle based solely on
10844 if (M >= NumElements) {
10845 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10846 for (int &M : NewMask)
10847 if (M >= NumElements)
10849 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10852 // Try to collapse shuffles into using a vector type with fewer elements but
10853 // wider element types. We cap this to not form integers or floating point
10854 // elements wider than 64 bits, but it might be interesting to form i128
10855 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10856 SmallVector<int, 16> WidenedMask;
10857 if (VT.getScalarSizeInBits() < 64 &&
10858 canWidenShuffleElements(Mask, WidenedMask)) {
10859 MVT NewEltVT = VT.isFloatingPoint()
10860 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10861 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10862 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10863 // Make sure that the new vector type is legal. For example, v2f64 isn't
10865 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10866 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10867 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10868 return DAG.getNode(ISD::BITCAST, dl, VT,
10869 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10873 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10874 for (int M : SVOp->getMask())
10876 ++NumUndefElements;
10877 else if (M < NumElements)
10882 // Commute the shuffle as needed such that more elements come from V1 than
10883 // V2. This allows us to match the shuffle pattern strictly on how many
10884 // elements come from V1 without handling the symmetric cases.
10885 if (NumV2Elements > NumV1Elements)
10886 return DAG.getCommutedVectorShuffle(*SVOp);
10888 // When the number of V1 and V2 elements are the same, try to minimize the
10889 // number of uses of V2 in the low half of the vector. When that is tied,
10890 // ensure that the sum of indices for V1 is equal to or lower than the sum
10891 // indices for V2. When those are equal, try to ensure that the number of odd
10892 // indices for V1 is lower than the number of odd indices for V2.
10893 if (NumV1Elements == NumV2Elements) {
10894 int LowV1Elements = 0, LowV2Elements = 0;
10895 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10896 if (M >= NumElements)
10900 if (LowV2Elements > LowV1Elements) {
10901 return DAG.getCommutedVectorShuffle(*SVOp);
10902 } else if (LowV2Elements == LowV1Elements) {
10903 int SumV1Indices = 0, SumV2Indices = 0;
10904 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10905 if (SVOp->getMask()[i] >= NumElements)
10907 else if (SVOp->getMask()[i] >= 0)
10909 if (SumV2Indices < SumV1Indices) {
10910 return DAG.getCommutedVectorShuffle(*SVOp);
10911 } else if (SumV2Indices == SumV1Indices) {
10912 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10913 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10914 if (SVOp->getMask()[i] >= NumElements)
10915 NumV2OddIndices += i % 2;
10916 else if (SVOp->getMask()[i] >= 0)
10917 NumV1OddIndices += i % 2;
10918 if (NumV2OddIndices < NumV1OddIndices)
10919 return DAG.getCommutedVectorShuffle(*SVOp);
10924 // For each vector width, delegate to a specialized lowering routine.
10925 if (VT.getSizeInBits() == 128)
10926 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10928 if (VT.getSizeInBits() == 256)
10929 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10931 // Force AVX-512 vectors to be scalarized for now.
10932 // FIXME: Implement AVX-512 support!
10933 if (VT.getSizeInBits() == 512)
10934 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10936 llvm_unreachable("Unimplemented!");
10940 //===----------------------------------------------------------------------===//
10941 // Legacy vector shuffle lowering
10943 // This code is the legacy code handling vector shuffles until the above
10944 // replaces its functionality and performance.
10945 //===----------------------------------------------------------------------===//
10947 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10948 bool hasInt256, unsigned *MaskOut = nullptr) {
10949 MVT EltVT = VT.getVectorElementType();
10951 // There is no blend with immediate in AVX-512.
10952 if (VT.is512BitVector())
10955 if (!hasSSE41 || EltVT == MVT::i8)
10957 if (!hasInt256 && VT == MVT::v16i16)
10960 unsigned MaskValue = 0;
10961 unsigned NumElems = VT.getVectorNumElements();
10962 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10963 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10964 unsigned NumElemsInLane = NumElems / NumLanes;
10966 // Blend for v16i16 should be symetric for the both lanes.
10967 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10969 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10970 int EltIdx = MaskVals[i];
10972 if ((EltIdx < 0 || EltIdx == (int)i) &&
10973 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10976 if (((unsigned)EltIdx == (i + NumElems)) &&
10977 (SndLaneEltIdx < 0 ||
10978 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10979 MaskValue |= (1 << i);
10985 *MaskOut = MaskValue;
10989 // Try to lower a shuffle node into a simple blend instruction.
10990 // This function assumes isBlendMask returns true for this
10991 // SuffleVectorSDNode
10992 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10993 unsigned MaskValue,
10994 const X86Subtarget *Subtarget,
10995 SelectionDAG &DAG) {
10996 MVT VT = SVOp->getSimpleValueType(0);
10997 MVT EltVT = VT.getVectorElementType();
10998 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10999 Subtarget->hasInt256() && "Trying to lower a "
11000 "VECTOR_SHUFFLE to a Blend but "
11001 "with the wrong mask"));
11002 SDValue V1 = SVOp->getOperand(0);
11003 SDValue V2 = SVOp->getOperand(1);
11005 unsigned NumElems = VT.getVectorNumElements();
11007 // Convert i32 vectors to floating point if it is not AVX2.
11008 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
11010 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
11011 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
11013 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
11014 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
11017 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
11018 DAG.getConstant(MaskValue, MVT::i32));
11019 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
11022 /// In vector type \p VT, return true if the element at index \p InputIdx
11023 /// falls on a different 128-bit lane than \p OutputIdx.
11024 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
11025 unsigned OutputIdx) {
11026 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
11027 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
11030 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
11031 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
11032 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
11033 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
11035 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
11036 SelectionDAG &DAG) {
11037 MVT VT = V1.getSimpleValueType();
11038 assert(VT.is128BitVector() || VT.is256BitVector());
11040 MVT EltVT = VT.getVectorElementType();
11041 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11042 unsigned NumElts = VT.getVectorNumElements();
11044 SmallVector<SDValue, 32> PshufbMask;
11045 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11046 int InputIdx = MaskVals[OutputIdx];
11047 unsigned InputByteIdx;
11049 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11050 InputByteIdx = 0x80;
11052 // Cross lane is not allowed.
11053 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11055 InputByteIdx = InputIdx * EltSizeInBytes;
11056 // Index is an byte offset within the 128-bit lane.
11057 InputByteIdx &= 0xf;
11060 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11061 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11062 if (InputByteIdx != 0x80)
11067 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11069 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11070 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11071 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11074 // v8i16 shuffles - Prefer shuffles in the following order:
11075 // 1. [all] pshuflw, pshufhw, optional move
11076 // 2. [ssse3] 1 x pshufb
11077 // 3. [ssse3] 2 x pshufb + 1 x por
11078 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11080 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11081 SelectionDAG &DAG) {
11082 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11083 SDValue V1 = SVOp->getOperand(0);
11084 SDValue V2 = SVOp->getOperand(1);
11086 SmallVector<int, 8> MaskVals;
11088 // Determine if more than 1 of the words in each of the low and high quadwords
11089 // of the result come from the same quadword of one of the two inputs. Undef
11090 // mask values count as coming from any quadword, for better codegen.
11092 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11093 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11094 unsigned LoQuad[] = { 0, 0, 0, 0 };
11095 unsigned HiQuad[] = { 0, 0, 0, 0 };
11096 // Indices of quads used.
11097 std::bitset<4> InputQuads;
11098 for (unsigned i = 0; i < 8; ++i) {
11099 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11100 int EltIdx = SVOp->getMaskElt(i);
11101 MaskVals.push_back(EltIdx);
11109 ++Quad[EltIdx / 4];
11110 InputQuads.set(EltIdx / 4);
11113 int BestLoQuad = -1;
11114 unsigned MaxQuad = 1;
11115 for (unsigned i = 0; i < 4; ++i) {
11116 if (LoQuad[i] > MaxQuad) {
11118 MaxQuad = LoQuad[i];
11122 int BestHiQuad = -1;
11124 for (unsigned i = 0; i < 4; ++i) {
11125 if (HiQuad[i] > MaxQuad) {
11127 MaxQuad = HiQuad[i];
11131 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11132 // of the two input vectors, shuffle them into one input vector so only a
11133 // single pshufb instruction is necessary. If there are more than 2 input
11134 // quads, disable the next transformation since it does not help SSSE3.
11135 bool V1Used = InputQuads[0] || InputQuads[1];
11136 bool V2Used = InputQuads[2] || InputQuads[3];
11137 if (Subtarget->hasSSSE3()) {
11138 if (InputQuads.count() == 2 && V1Used && V2Used) {
11139 BestLoQuad = InputQuads[0] ? 0 : 1;
11140 BestHiQuad = InputQuads[2] ? 2 : 3;
11142 if (InputQuads.count() > 2) {
11148 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11149 // the shuffle mask. If a quad is scored as -1, that means that it contains
11150 // words from all 4 input quadwords.
11152 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11154 BestLoQuad < 0 ? 0 : BestLoQuad,
11155 BestHiQuad < 0 ? 1 : BestHiQuad
11157 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11158 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11159 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11160 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11162 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11163 // source words for the shuffle, to aid later transformations.
11164 bool AllWordsInNewV = true;
11165 bool InOrder[2] = { true, true };
11166 for (unsigned i = 0; i != 8; ++i) {
11167 int idx = MaskVals[i];
11169 InOrder[i/4] = false;
11170 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11172 AllWordsInNewV = false;
11176 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11177 if (AllWordsInNewV) {
11178 for (int i = 0; i != 8; ++i) {
11179 int idx = MaskVals[i];
11182 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11183 if ((idx != i) && idx < 4)
11185 if ((idx != i) && idx > 3)
11194 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11195 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11196 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11197 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11198 unsigned TargetMask = 0;
11199 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11200 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11201 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11202 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11203 getShufflePSHUFLWImmediate(SVOp);
11204 V1 = NewV.getOperand(0);
11205 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11209 // Promote splats to a larger type which usually leads to more efficient code.
11210 // FIXME: Is this true if pshufb is available?
11211 if (SVOp->isSplat())
11212 return PromoteSplat(SVOp, DAG);
11214 // If we have SSSE3, and all words of the result are from 1 input vector,
11215 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11216 // is present, fall back to case 4.
11217 if (Subtarget->hasSSSE3()) {
11218 SmallVector<SDValue,16> pshufbMask;
11220 // If we have elements from both input vectors, set the high bit of the
11221 // shuffle mask element to zero out elements that come from V2 in the V1
11222 // mask, and elements that come from V1 in the V2 mask, so that the two
11223 // results can be OR'd together.
11224 bool TwoInputs = V1Used && V2Used;
11225 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11227 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11229 // Calculate the shuffle mask for the second input, shuffle it, and
11230 // OR it with the first shuffled input.
11231 CommuteVectorShuffleMask(MaskVals, 8);
11232 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11233 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11234 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11237 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11238 // and update MaskVals with new element order.
11239 std::bitset<8> InOrder;
11240 if (BestLoQuad >= 0) {
11241 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11242 for (int i = 0; i != 4; ++i) {
11243 int idx = MaskVals[i];
11246 } else if ((idx / 4) == BestLoQuad) {
11247 MaskV[i] = idx & 3;
11251 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11254 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11255 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11256 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11257 NewV.getOperand(0),
11258 getShufflePSHUFLWImmediate(SVOp), DAG);
11262 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11263 // and update MaskVals with the new element order.
11264 if (BestHiQuad >= 0) {
11265 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11266 for (unsigned i = 4; i != 8; ++i) {
11267 int idx = MaskVals[i];
11270 } else if ((idx / 4) == BestHiQuad) {
11271 MaskV[i] = (idx & 3) + 4;
11275 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11278 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11279 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11280 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11281 NewV.getOperand(0),
11282 getShufflePSHUFHWImmediate(SVOp), DAG);
11286 // In case BestHi & BestLo were both -1, which means each quadword has a word
11287 // from each of the four input quadwords, calculate the InOrder bitvector now
11288 // before falling through to the insert/extract cleanup.
11289 if (BestLoQuad == -1 && BestHiQuad == -1) {
11291 for (int i = 0; i != 8; ++i)
11292 if (MaskVals[i] < 0 || MaskVals[i] == i)
11296 // The other elements are put in the right place using pextrw and pinsrw.
11297 for (unsigned i = 0; i != 8; ++i) {
11300 int EltIdx = MaskVals[i];
11303 SDValue ExtOp = (EltIdx < 8) ?
11304 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11305 DAG.getIntPtrConstant(EltIdx)) :
11306 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11307 DAG.getIntPtrConstant(EltIdx - 8));
11308 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11309 DAG.getIntPtrConstant(i));
11314 /// \brief v16i16 shuffles
11316 /// FIXME: We only support generation of a single pshufb currently. We can
11317 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11318 /// well (e.g 2 x pshufb + 1 x por).
11320 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11321 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11322 SDValue V1 = SVOp->getOperand(0);
11323 SDValue V2 = SVOp->getOperand(1);
11326 if (V2.getOpcode() != ISD::UNDEF)
11329 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11330 return getPSHUFB(MaskVals, V1, dl, DAG);
11333 // v16i8 shuffles - Prefer shuffles in the following order:
11334 // 1. [ssse3] 1 x pshufb
11335 // 2. [ssse3] 2 x pshufb + 1 x por
11336 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11337 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11338 const X86Subtarget* Subtarget,
11339 SelectionDAG &DAG) {
11340 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11341 SDValue V1 = SVOp->getOperand(0);
11342 SDValue V2 = SVOp->getOperand(1);
11344 ArrayRef<int> MaskVals = SVOp->getMask();
11346 // Promote splats to a larger type which usually leads to more efficient code.
11347 // FIXME: Is this true if pshufb is available?
11348 if (SVOp->isSplat())
11349 return PromoteSplat(SVOp, DAG);
11351 // If we have SSSE3, case 1 is generated when all result bytes come from
11352 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11353 // present, fall back to case 3.
11355 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11356 if (Subtarget->hasSSSE3()) {
11357 SmallVector<SDValue,16> pshufbMask;
11359 // If all result elements are from one input vector, then only translate
11360 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11362 // Otherwise, we have elements from both input vectors, and must zero out
11363 // elements that come from V2 in the first mask, and V1 in the second mask
11364 // so that we can OR them together.
11365 for (unsigned i = 0; i != 16; ++i) {
11366 int EltIdx = MaskVals[i];
11367 if (EltIdx < 0 || EltIdx >= 16)
11369 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11371 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11372 DAG.getNode(ISD::BUILD_VECTOR, dl,
11373 MVT::v16i8, pshufbMask));
11375 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11376 // the 2nd operand if it's undefined or zero.
11377 if (V2.getOpcode() == ISD::UNDEF ||
11378 ISD::isBuildVectorAllZeros(V2.getNode()))
11381 // Calculate the shuffle mask for the second input, shuffle it, and
11382 // OR it with the first shuffled input.
11383 pshufbMask.clear();
11384 for (unsigned i = 0; i != 16; ++i) {
11385 int EltIdx = MaskVals[i];
11386 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11387 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11389 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11390 DAG.getNode(ISD::BUILD_VECTOR, dl,
11391 MVT::v16i8, pshufbMask));
11392 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11395 // No SSSE3 - Calculate in place words and then fix all out of place words
11396 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11397 // the 16 different words that comprise the two doublequadword input vectors.
11398 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11399 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11401 for (int i = 0; i != 8; ++i) {
11402 int Elt0 = MaskVals[i*2];
11403 int Elt1 = MaskVals[i*2+1];
11405 // This word of the result is all undef, skip it.
11406 if (Elt0 < 0 && Elt1 < 0)
11409 // This word of the result is already in the correct place, skip it.
11410 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11413 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11414 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11417 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11418 // using a single extract together, load it and store it.
11419 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11420 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11421 DAG.getIntPtrConstant(Elt1 / 2));
11422 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11423 DAG.getIntPtrConstant(i));
11427 // If Elt1 is defined, extract it from the appropriate source. If the
11428 // source byte is not also odd, shift the extracted word left 8 bits
11429 // otherwise clear the bottom 8 bits if we need to do an or.
11431 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11432 DAG.getIntPtrConstant(Elt1 / 2));
11433 if ((Elt1 & 1) == 0)
11434 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11436 TLI.getShiftAmountTy(InsElt.getValueType())));
11437 else if (Elt0 >= 0)
11438 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11439 DAG.getConstant(0xFF00, MVT::i16));
11441 // If Elt0 is defined, extract it from the appropriate source. If the
11442 // source byte is not also even, shift the extracted word right 8 bits. If
11443 // Elt1 was also defined, OR the extracted values together before
11444 // inserting them in the result.
11446 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11447 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11448 if ((Elt0 & 1) != 0)
11449 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11451 TLI.getShiftAmountTy(InsElt0.getValueType())));
11452 else if (Elt1 >= 0)
11453 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11454 DAG.getConstant(0x00FF, MVT::i16));
11455 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11458 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11459 DAG.getIntPtrConstant(i));
11461 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11464 // v32i8 shuffles - Translate to VPSHUFB if possible.
11466 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11467 const X86Subtarget *Subtarget,
11468 SelectionDAG &DAG) {
11469 MVT VT = SVOp->getSimpleValueType(0);
11470 SDValue V1 = SVOp->getOperand(0);
11471 SDValue V2 = SVOp->getOperand(1);
11473 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11475 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11476 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11477 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11479 // VPSHUFB may be generated if
11480 // (1) one of input vector is undefined or zeroinitializer.
11481 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11482 // And (2) the mask indexes don't cross the 128-bit lane.
11483 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11484 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11487 if (V1IsAllZero && !V2IsAllZero) {
11488 CommuteVectorShuffleMask(MaskVals, 32);
11491 return getPSHUFB(MaskVals, V1, dl, DAG);
11494 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11495 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11496 /// done when every pair / quad of shuffle mask elements point to elements in
11497 /// the right sequence. e.g.
11498 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11500 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11501 SelectionDAG &DAG) {
11502 MVT VT = SVOp->getSimpleValueType(0);
11504 unsigned NumElems = VT.getVectorNumElements();
11507 switch (VT.SimpleTy) {
11508 default: llvm_unreachable("Unexpected!");
11511 return SDValue(SVOp, 0);
11512 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11513 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11514 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11515 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11516 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11517 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11520 SmallVector<int, 8> MaskVec;
11521 for (unsigned i = 0; i != NumElems; i += Scale) {
11523 for (unsigned j = 0; j != Scale; ++j) {
11524 int EltIdx = SVOp->getMaskElt(i+j);
11528 StartIdx = (EltIdx / Scale);
11529 if (EltIdx != (int)(StartIdx*Scale + j))
11532 MaskVec.push_back(StartIdx);
11535 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11536 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11537 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11540 /// getVZextMovL - Return a zero-extending vector move low node.
11542 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11543 SDValue SrcOp, SelectionDAG &DAG,
11544 const X86Subtarget *Subtarget, SDLoc dl) {
11545 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11546 LoadSDNode *LD = nullptr;
11547 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11548 LD = dyn_cast<LoadSDNode>(SrcOp);
11550 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11552 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11553 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11554 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11555 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11556 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11558 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11559 return DAG.getNode(ISD::BITCAST, dl, VT,
11560 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11561 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11563 SrcOp.getOperand(0)
11569 return DAG.getNode(ISD::BITCAST, dl, VT,
11570 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11571 DAG.getNode(ISD::BITCAST, dl,
11575 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11576 /// which could not be matched by any known target speficic shuffle
11578 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11580 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11581 if (NewOp.getNode())
11584 MVT VT = SVOp->getSimpleValueType(0);
11586 unsigned NumElems = VT.getVectorNumElements();
11587 unsigned NumLaneElems = NumElems / 2;
11590 MVT EltVT = VT.getVectorElementType();
11591 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11594 SmallVector<int, 16> Mask;
11595 for (unsigned l = 0; l < 2; ++l) {
11596 // Build a shuffle mask for the output, discovering on the fly which
11597 // input vectors to use as shuffle operands (recorded in InputUsed).
11598 // If building a suitable shuffle vector proves too hard, then bail
11599 // out with UseBuildVector set.
11600 bool UseBuildVector = false;
11601 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11602 unsigned LaneStart = l * NumLaneElems;
11603 for (unsigned i = 0; i != NumLaneElems; ++i) {
11604 // The mask element. This indexes into the input.
11605 int Idx = SVOp->getMaskElt(i+LaneStart);
11607 // the mask element does not index into any input vector.
11608 Mask.push_back(-1);
11612 // The input vector this mask element indexes into.
11613 int Input = Idx / NumLaneElems;
11615 // Turn the index into an offset from the start of the input vector.
11616 Idx -= Input * NumLaneElems;
11618 // Find or create a shuffle vector operand to hold this input.
11620 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11621 if (InputUsed[OpNo] == Input)
11622 // This input vector is already an operand.
11624 if (InputUsed[OpNo] < 0) {
11625 // Create a new operand for this input vector.
11626 InputUsed[OpNo] = Input;
11631 if (OpNo >= array_lengthof(InputUsed)) {
11632 // More than two input vectors used! Give up on trying to create a
11633 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11634 UseBuildVector = true;
11638 // Add the mask index for the new shuffle vector.
11639 Mask.push_back(Idx + OpNo * NumLaneElems);
11642 if (UseBuildVector) {
11643 SmallVector<SDValue, 16> SVOps;
11644 for (unsigned i = 0; i != NumLaneElems; ++i) {
11645 // The mask element. This indexes into the input.
11646 int Idx = SVOp->getMaskElt(i+LaneStart);
11648 SVOps.push_back(DAG.getUNDEF(EltVT));
11652 // The input vector this mask element indexes into.
11653 int Input = Idx / NumElems;
11655 // Turn the index into an offset from the start of the input vector.
11656 Idx -= Input * NumElems;
11658 // Extract the vector element by hand.
11659 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11660 SVOp->getOperand(Input),
11661 DAG.getIntPtrConstant(Idx)));
11664 // Construct the output using a BUILD_VECTOR.
11665 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11666 } else if (InputUsed[0] < 0) {
11667 // No input vectors were used! The result is undefined.
11668 Output[l] = DAG.getUNDEF(NVT);
11670 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11671 (InputUsed[0] % 2) * NumLaneElems,
11673 // If only one input was used, use an undefined vector for the other.
11674 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11675 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11676 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11677 // At least one input vector was used. Create a new shuffle vector.
11678 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11684 // Concatenate the result back
11685 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11688 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11689 /// 4 elements, and match them with several different shuffle types.
11691 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11692 SDValue V1 = SVOp->getOperand(0);
11693 SDValue V2 = SVOp->getOperand(1);
11695 MVT VT = SVOp->getSimpleValueType(0);
11697 assert(VT.is128BitVector() && "Unsupported vector size");
11699 std::pair<int, int> Locs[4];
11700 int Mask1[] = { -1, -1, -1, -1 };
11701 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11703 unsigned NumHi = 0;
11704 unsigned NumLo = 0;
11705 for (unsigned i = 0; i != 4; ++i) {
11706 int Idx = PermMask[i];
11708 Locs[i] = std::make_pair(-1, -1);
11710 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11712 Locs[i] = std::make_pair(0, NumLo);
11713 Mask1[NumLo] = Idx;
11716 Locs[i] = std::make_pair(1, NumHi);
11718 Mask1[2+NumHi] = Idx;
11724 if (NumLo <= 2 && NumHi <= 2) {
11725 // If no more than two elements come from either vector. This can be
11726 // implemented with two shuffles. First shuffle gather the elements.
11727 // The second shuffle, which takes the first shuffle as both of its
11728 // vector operands, put the elements into the right order.
11729 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11731 int Mask2[] = { -1, -1, -1, -1 };
11733 for (unsigned i = 0; i != 4; ++i)
11734 if (Locs[i].first != -1) {
11735 unsigned Idx = (i < 2) ? 0 : 4;
11736 Idx += Locs[i].first * 2 + Locs[i].second;
11740 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11743 if (NumLo == 3 || NumHi == 3) {
11744 // Otherwise, we must have three elements from one vector, call it X, and
11745 // one element from the other, call it Y. First, use a shufps to build an
11746 // intermediate vector with the one element from Y and the element from X
11747 // that will be in the same half in the final destination (the indexes don't
11748 // matter). Then, use a shufps to build the final vector, taking the half
11749 // containing the element from Y from the intermediate, and the other half
11752 // Normalize it so the 3 elements come from V1.
11753 CommuteVectorShuffleMask(PermMask, 4);
11757 // Find the element from V2.
11759 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11760 int Val = PermMask[HiIndex];
11767 Mask1[0] = PermMask[HiIndex];
11769 Mask1[2] = PermMask[HiIndex^1];
11771 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11773 if (HiIndex >= 2) {
11774 Mask1[0] = PermMask[0];
11775 Mask1[1] = PermMask[1];
11776 Mask1[2] = HiIndex & 1 ? 6 : 4;
11777 Mask1[3] = HiIndex & 1 ? 4 : 6;
11778 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11781 Mask1[0] = HiIndex & 1 ? 2 : 0;
11782 Mask1[1] = HiIndex & 1 ? 0 : 2;
11783 Mask1[2] = PermMask[2];
11784 Mask1[3] = PermMask[3];
11789 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11792 // Break it into (shuffle shuffle_hi, shuffle_lo).
11793 int LoMask[] = { -1, -1, -1, -1 };
11794 int HiMask[] = { -1, -1, -1, -1 };
11796 int *MaskPtr = LoMask;
11797 unsigned MaskIdx = 0;
11798 unsigned LoIdx = 0;
11799 unsigned HiIdx = 2;
11800 for (unsigned i = 0; i != 4; ++i) {
11807 int Idx = PermMask[i];
11809 Locs[i] = std::make_pair(-1, -1);
11810 } else if (Idx < 4) {
11811 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11812 MaskPtr[LoIdx] = Idx;
11815 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11816 MaskPtr[HiIdx] = Idx;
11821 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11822 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11823 int MaskOps[] = { -1, -1, -1, -1 };
11824 for (unsigned i = 0; i != 4; ++i)
11825 if (Locs[i].first != -1)
11826 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11827 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11830 static bool MayFoldVectorLoad(SDValue V) {
11831 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11832 V = V.getOperand(0);
11834 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11835 V = V.getOperand(0);
11836 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11837 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11838 // BUILD_VECTOR (load), undef
11839 V = V.getOperand(0);
11841 return MayFoldLoad(V);
11845 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11846 MVT VT = Op.getSimpleValueType();
11848 // Canonizalize to v2f64.
11849 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11850 return DAG.getNode(ISD::BITCAST, dl, VT,
11851 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11856 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11858 SDValue V1 = Op.getOperand(0);
11859 SDValue V2 = Op.getOperand(1);
11860 MVT VT = Op.getSimpleValueType();
11862 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11864 if (HasSSE2 && VT == MVT::v2f64)
11865 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11867 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11868 return DAG.getNode(ISD::BITCAST, dl, VT,
11869 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11870 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11871 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11875 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11876 SDValue V1 = Op.getOperand(0);
11877 SDValue V2 = Op.getOperand(1);
11878 MVT VT = Op.getSimpleValueType();
11880 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11881 "unsupported shuffle type");
11883 if (V2.getOpcode() == ISD::UNDEF)
11887 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11891 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11892 SDValue V1 = Op.getOperand(0);
11893 SDValue V2 = Op.getOperand(1);
11894 MVT VT = Op.getSimpleValueType();
11895 unsigned NumElems = VT.getVectorNumElements();
11897 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11898 // operand of these instructions is only memory, so check if there's a
11899 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11901 bool CanFoldLoad = false;
11903 // Trivial case, when V2 comes from a load.
11904 if (MayFoldVectorLoad(V2))
11905 CanFoldLoad = true;
11907 // When V1 is a load, it can be folded later into a store in isel, example:
11908 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11910 // (MOVLPSmr addr:$src1, VR128:$src2)
11911 // So, recognize this potential and also use MOVLPS or MOVLPD
11912 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11913 CanFoldLoad = true;
11915 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11917 if (HasSSE2 && NumElems == 2)
11918 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11921 // If we don't care about the second element, proceed to use movss.
11922 if (SVOp->getMaskElt(1) != -1)
11923 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11926 // movl and movlp will both match v2i64, but v2i64 is never matched by
11927 // movl earlier because we make it strict to avoid messing with the movlp load
11928 // folding logic (see the code above getMOVLP call). Match it here then,
11929 // this is horrible, but will stay like this until we move all shuffle
11930 // matching to x86 specific nodes. Note that for the 1st condition all
11931 // types are matched with movsd.
11933 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11934 // as to remove this logic from here, as much as possible
11935 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11936 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11937 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11940 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11942 // Invert the operand order and use SHUFPS to match it.
11943 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11944 getShuffleSHUFImmediate(SVOp), DAG);
11947 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11948 SelectionDAG &DAG) {
11950 MVT VT = Load->getSimpleValueType(0);
11951 MVT EVT = VT.getVectorElementType();
11952 SDValue Addr = Load->getOperand(1);
11953 SDValue NewAddr = DAG.getNode(
11954 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11955 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11958 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11959 DAG.getMachineFunction().getMachineMemOperand(
11960 Load->getMemOperand(), 0, EVT.getStoreSize()));
11964 // It is only safe to call this function if isINSERTPSMask is true for
11965 // this shufflevector mask.
11966 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11967 SelectionDAG &DAG) {
11968 // Generate an insertps instruction when inserting an f32 from memory onto a
11969 // v4f32 or when copying a member from one v4f32 to another.
11970 // We also use it for transferring i32 from one register to another,
11971 // since it simply copies the same bits.
11972 // If we're transferring an i32 from memory to a specific element in a
11973 // register, we output a generic DAG that will match the PINSRD
11975 MVT VT = SVOp->getSimpleValueType(0);
11976 MVT EVT = VT.getVectorElementType();
11977 SDValue V1 = SVOp->getOperand(0);
11978 SDValue V2 = SVOp->getOperand(1);
11979 auto Mask = SVOp->getMask();
11980 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11981 "unsupported vector type for insertps/pinsrd");
11983 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11984 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11985 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11989 unsigned DestIndex;
11993 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11996 // If we have 1 element from each vector, we have to check if we're
11997 // changing V1's element's place. If so, we're done. Otherwise, we
11998 // should assume we're changing V2's element's place and behave
12000 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
12001 assert(DestIndex <= INT32_MAX && "truncated destination index");
12002 if (FromV1 == FromV2 &&
12003 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
12007 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12010 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
12011 "More than one element from V1 and from V2, or no elements from one "
12012 "of the vectors. This case should not have returned true from "
12017 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
12020 // Get an index into the source vector in the range [0,4) (the mask is
12021 // in the range [0,8) because it can address V1 and V2)
12022 unsigned SrcIndex = Mask[DestIndex] % 4;
12023 if (MayFoldLoad(From)) {
12024 // Trivial case, when From comes from a load and is only used by the
12025 // shuffle. Make it use insertps from the vector that we need from that
12028 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
12029 if (!NewLoad.getNode())
12032 if (EVT == MVT::f32) {
12033 // Create this as a scalar to vector to match the instruction pattern.
12034 SDValue LoadScalarToVector =
12035 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
12036 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
12037 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12039 } else { // EVT == MVT::i32
12040 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12041 // instruction, to match the PINSRD instruction, which loads an i32 to a
12042 // certain vector element.
12043 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12044 DAG.getConstant(DestIndex, MVT::i32));
12048 // Vector-element-to-vector
12049 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12050 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12053 // Reduce a vector shuffle to zext.
12054 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12055 SelectionDAG &DAG) {
12056 // PMOVZX is only available from SSE41.
12057 if (!Subtarget->hasSSE41())
12060 MVT VT = Op.getSimpleValueType();
12062 // Only AVX2 support 256-bit vector integer extending.
12063 if (!Subtarget->hasInt256() && VT.is256BitVector())
12066 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12068 SDValue V1 = Op.getOperand(0);
12069 SDValue V2 = Op.getOperand(1);
12070 unsigned NumElems = VT.getVectorNumElements();
12072 // Extending is an unary operation and the element type of the source vector
12073 // won't be equal to or larger than i64.
12074 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12075 VT.getVectorElementType() == MVT::i64)
12078 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12079 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12080 while ((1U << Shift) < NumElems) {
12081 if (SVOp->getMaskElt(1U << Shift) == 1)
12084 // The maximal ratio is 8, i.e. from i8 to i64.
12089 // Check the shuffle mask.
12090 unsigned Mask = (1U << Shift) - 1;
12091 for (unsigned i = 0; i != NumElems; ++i) {
12092 int EltIdx = SVOp->getMaskElt(i);
12093 if ((i & Mask) != 0 && EltIdx != -1)
12095 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12099 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12100 MVT NeVT = MVT::getIntegerVT(NBits);
12101 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12103 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12106 return DAG.getNode(ISD::BITCAST, DL, VT,
12107 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12110 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12111 SelectionDAG &DAG) {
12112 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12113 MVT VT = Op.getSimpleValueType();
12115 SDValue V1 = Op.getOperand(0);
12116 SDValue V2 = Op.getOperand(1);
12118 if (isZeroShuffle(SVOp))
12119 return getZeroVector(VT, Subtarget, DAG, dl);
12121 // Handle splat operations
12122 if (SVOp->isSplat()) {
12123 // Use vbroadcast whenever the splat comes from a foldable load
12124 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12125 if (Broadcast.getNode())
12129 // Check integer expanding shuffles.
12130 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12131 if (NewOp.getNode())
12134 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12136 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12137 VT == MVT::v32i8) {
12138 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12139 if (NewOp.getNode())
12140 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12141 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12142 // FIXME: Figure out a cleaner way to do this.
12143 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12144 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12145 if (NewOp.getNode()) {
12146 MVT NewVT = NewOp.getSimpleValueType();
12147 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12148 NewVT, true, false))
12149 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12152 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12153 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12154 if (NewOp.getNode()) {
12155 MVT NewVT = NewOp.getSimpleValueType();
12156 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12157 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12166 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12167 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12168 SDValue V1 = Op.getOperand(0);
12169 SDValue V2 = Op.getOperand(1);
12170 MVT VT = Op.getSimpleValueType();
12172 unsigned NumElems = VT.getVectorNumElements();
12173 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12174 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12175 bool V1IsSplat = false;
12176 bool V2IsSplat = false;
12177 bool HasSSE2 = Subtarget->hasSSE2();
12178 bool HasFp256 = Subtarget->hasFp256();
12179 bool HasInt256 = Subtarget->hasInt256();
12180 MachineFunction &MF = DAG.getMachineFunction();
12181 bool OptForSize = MF.getFunction()->getAttributes().
12182 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12184 // Check if we should use the experimental vector shuffle lowering. If so,
12185 // delegate completely to that code path.
12186 if (ExperimentalVectorShuffleLowering)
12187 return lowerVectorShuffle(Op, Subtarget, DAG);
12189 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12191 if (V1IsUndef && V2IsUndef)
12192 return DAG.getUNDEF(VT);
12194 // When we create a shuffle node we put the UNDEF node to second operand,
12195 // but in some cases the first operand may be transformed to UNDEF.
12196 // In this case we should just commute the node.
12198 return DAG.getCommutedVectorShuffle(*SVOp);
12200 // Vector shuffle lowering takes 3 steps:
12202 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12203 // narrowing and commutation of operands should be handled.
12204 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12206 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12207 // so the shuffle can be broken into other shuffles and the legalizer can
12208 // try the lowering again.
12210 // The general idea is that no vector_shuffle operation should be left to
12211 // be matched during isel, all of them must be converted to a target specific
12214 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12215 // narrowing and commutation of operands should be handled. The actual code
12216 // doesn't include all of those, work in progress...
12217 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12218 if (NewOp.getNode())
12221 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12223 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12224 // unpckh_undef). Only use pshufd if speed is more important than size.
12225 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12226 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12227 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12228 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12230 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12231 V2IsUndef && MayFoldVectorLoad(V1))
12232 return getMOVDDup(Op, dl, V1, DAG);
12234 if (isMOVHLPS_v_undef_Mask(M, VT))
12235 return getMOVHighToLow(Op, dl, DAG);
12237 // Use to match splats
12238 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12239 (VT == MVT::v2f64 || VT == MVT::v2i64))
12240 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12242 if (isPSHUFDMask(M, VT)) {
12243 // The actual implementation will match the mask in the if above and then
12244 // during isel it can match several different instructions, not only pshufd
12245 // as its name says, sad but true, emulate the behavior for now...
12246 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12247 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12249 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12251 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12252 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12254 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12255 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12258 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12262 if (isPALIGNRMask(M, VT, Subtarget))
12263 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12264 getShufflePALIGNRImmediate(SVOp),
12267 if (isVALIGNMask(M, VT, Subtarget))
12268 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12269 getShuffleVALIGNImmediate(SVOp),
12272 // Check if this can be converted into a logical shift.
12273 bool isLeft = false;
12274 unsigned ShAmt = 0;
12276 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12277 if (isShift && ShVal.hasOneUse()) {
12278 // If the shifted value has multiple uses, it may be cheaper to use
12279 // v_set0 + movlhps or movhlps, etc.
12280 MVT EltVT = VT.getVectorElementType();
12281 ShAmt *= EltVT.getSizeInBits();
12282 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12285 if (isMOVLMask(M, VT)) {
12286 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12287 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12288 if (!isMOVLPMask(M, VT)) {
12289 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12290 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12292 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12293 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12297 // FIXME: fold these into legal mask.
12298 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12299 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12301 if (isMOVHLPSMask(M, VT))
12302 return getMOVHighToLow(Op, dl, DAG);
12304 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12305 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12307 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12308 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12310 if (isMOVLPMask(M, VT))
12311 return getMOVLP(Op, dl, DAG, HasSSE2);
12313 if (ShouldXformToMOVHLPS(M, VT) ||
12314 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12315 return DAG.getCommutedVectorShuffle(*SVOp);
12318 // No better options. Use a vshldq / vsrldq.
12319 MVT EltVT = VT.getVectorElementType();
12320 ShAmt *= EltVT.getSizeInBits();
12321 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12324 bool Commuted = false;
12325 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12326 // 1,1,1,1 -> v8i16 though.
12327 BitVector UndefElements;
12328 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12329 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12331 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12332 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12335 // Canonicalize the splat or undef, if present, to be on the RHS.
12336 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12337 CommuteVectorShuffleMask(M, NumElems);
12339 std::swap(V1IsSplat, V2IsSplat);
12343 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12344 // Shuffling low element of v1 into undef, just return v1.
12347 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12348 // the instruction selector will not match, so get a canonical MOVL with
12349 // swapped operands to undo the commute.
12350 return getMOVL(DAG, dl, VT, V2, V1);
12353 if (isUNPCKLMask(M, VT, HasInt256))
12354 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12356 if (isUNPCKHMask(M, VT, HasInt256))
12357 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12360 // Normalize mask so all entries that point to V2 points to its first
12361 // element then try to match unpck{h|l} again. If match, return a
12362 // new vector_shuffle with the corrected mask.p
12363 SmallVector<int, 8> NewMask(M.begin(), M.end());
12364 NormalizeMask(NewMask, NumElems);
12365 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12366 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12367 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12368 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12372 // Commute is back and try unpck* again.
12373 // FIXME: this seems wrong.
12374 CommuteVectorShuffleMask(M, NumElems);
12376 std::swap(V1IsSplat, V2IsSplat);
12378 if (isUNPCKLMask(M, VT, HasInt256))
12379 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12381 if (isUNPCKHMask(M, VT, HasInt256))
12382 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12385 // Normalize the node to match x86 shuffle ops if needed
12386 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12387 return DAG.getCommutedVectorShuffle(*SVOp);
12389 // The checks below are all present in isShuffleMaskLegal, but they are
12390 // inlined here right now to enable us to directly emit target specific
12391 // nodes, and remove one by one until they don't return Op anymore.
12393 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12394 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12395 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12396 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12399 if (isPSHUFHWMask(M, VT, HasInt256))
12400 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12401 getShufflePSHUFHWImmediate(SVOp),
12404 if (isPSHUFLWMask(M, VT, HasInt256))
12405 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12406 getShufflePSHUFLWImmediate(SVOp),
12409 unsigned MaskValue;
12410 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12412 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12414 if (isSHUFPMask(M, VT))
12415 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12416 getShuffleSHUFImmediate(SVOp), DAG);
12418 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12419 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12420 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12421 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12423 //===--------------------------------------------------------------------===//
12424 // Generate target specific nodes for 128 or 256-bit shuffles only
12425 // supported in the AVX instruction set.
12428 // Handle VMOVDDUPY permutations
12429 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12430 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12432 // Handle VPERMILPS/D* permutations
12433 if (isVPERMILPMask(M, VT)) {
12434 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12435 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12436 getShuffleSHUFImmediate(SVOp), DAG);
12437 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12438 getShuffleSHUFImmediate(SVOp), DAG);
12442 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12443 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12444 Idx*(NumElems/2), DAG, dl);
12446 // Handle VPERM2F128/VPERM2I128 permutations
12447 if (isVPERM2X128Mask(M, VT, HasFp256))
12448 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12449 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12451 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12452 return getINSERTPS(SVOp, dl, DAG);
12455 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12456 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12458 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12459 VT.is512BitVector()) {
12460 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12461 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12462 SmallVector<SDValue, 16> permclMask;
12463 for (unsigned i = 0; i != NumElems; ++i) {
12464 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12467 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12469 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12470 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12471 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12472 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12473 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12476 //===--------------------------------------------------------------------===//
12477 // Since no target specific shuffle was selected for this generic one,
12478 // lower it into other known shuffles. FIXME: this isn't true yet, but
12479 // this is the plan.
12482 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12483 if (VT == MVT::v8i16) {
12484 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12485 if (NewOp.getNode())
12489 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12490 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12491 if (NewOp.getNode())
12495 if (VT == MVT::v16i8) {
12496 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12497 if (NewOp.getNode())
12501 if (VT == MVT::v32i8) {
12502 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12503 if (NewOp.getNode())
12507 // Handle all 128-bit wide vectors with 4 elements, and match them with
12508 // several different shuffle types.
12509 if (NumElems == 4 && VT.is128BitVector())
12510 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12512 // Handle general 256-bit shuffles
12513 if (VT.is256BitVector())
12514 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12519 // This function assumes its argument is a BUILD_VECTOR of constants or
12520 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12522 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12523 unsigned &MaskValue) {
12525 unsigned NumElems = BuildVector->getNumOperands();
12526 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12527 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12528 unsigned NumElemsInLane = NumElems / NumLanes;
12530 // Blend for v16i16 should be symetric for the both lanes.
12531 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12532 SDValue EltCond = BuildVector->getOperand(i);
12533 SDValue SndLaneEltCond =
12534 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12536 int Lane1Cond = -1, Lane2Cond = -1;
12537 if (isa<ConstantSDNode>(EltCond))
12538 Lane1Cond = !isZero(EltCond);
12539 if (isa<ConstantSDNode>(SndLaneEltCond))
12540 Lane2Cond = !isZero(SndLaneEltCond);
12542 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12543 // Lane1Cond != 0, means we want the first argument.
12544 // Lane1Cond == 0, means we want the second argument.
12545 // The encoding of this argument is 0 for the first argument, 1
12546 // for the second. Therefore, invert the condition.
12547 MaskValue |= !Lane1Cond << i;
12548 else if (Lane1Cond < 0)
12549 MaskValue |= !Lane2Cond << i;
12556 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12558 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12559 SelectionDAG &DAG) {
12560 SDValue Cond = Op.getOperand(0);
12561 SDValue LHS = Op.getOperand(1);
12562 SDValue RHS = Op.getOperand(2);
12564 MVT VT = Op.getSimpleValueType();
12565 MVT EltVT = VT.getVectorElementType();
12566 unsigned NumElems = VT.getVectorNumElements();
12568 // There is no blend with immediate in AVX-512.
12569 if (VT.is512BitVector())
12572 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12574 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12577 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12580 // Check the mask for BLEND and build the value.
12581 unsigned MaskValue = 0;
12582 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12585 // Convert i32 vectors to floating point if it is not AVX2.
12586 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12588 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12589 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12591 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12592 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12595 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12596 DAG.getConstant(MaskValue, MVT::i32));
12597 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12600 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12601 // A vselect where all conditions and data are constants can be optimized into
12602 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12603 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12604 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12605 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12608 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12609 if (BlendOp.getNode())
12612 // Some types for vselect were previously set to Expand, not Legal or
12613 // Custom. Return an empty SDValue so we fall-through to Expand, after
12614 // the Custom lowering phase.
12615 MVT VT = Op.getSimpleValueType();
12616 switch (VT.SimpleTy) {
12621 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12626 // We couldn't create a "Blend with immediate" node.
12627 // This node should still be legal, but we'll have to emit a blendv*
12632 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12633 MVT VT = Op.getSimpleValueType();
12636 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12639 if (VT.getSizeInBits() == 8) {
12640 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12641 Op.getOperand(0), Op.getOperand(1));
12642 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12643 DAG.getValueType(VT));
12644 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12647 if (VT.getSizeInBits() == 16) {
12648 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12649 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12651 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12652 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12653 DAG.getNode(ISD::BITCAST, dl,
12656 Op.getOperand(1)));
12657 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12658 Op.getOperand(0), Op.getOperand(1));
12659 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12660 DAG.getValueType(VT));
12661 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12664 if (VT == MVT::f32) {
12665 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12666 // the result back to FR32 register. It's only worth matching if the
12667 // result has a single use which is a store or a bitcast to i32. And in
12668 // the case of a store, it's not worth it if the index is a constant 0,
12669 // because a MOVSSmr can be used instead, which is smaller and faster.
12670 if (!Op.hasOneUse())
12672 SDNode *User = *Op.getNode()->use_begin();
12673 if ((User->getOpcode() != ISD::STORE ||
12674 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12675 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12676 (User->getOpcode() != ISD::BITCAST ||
12677 User->getValueType(0) != MVT::i32))
12679 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12680 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12683 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12686 if (VT == MVT::i32 || VT == MVT::i64) {
12687 // ExtractPS/pextrq works with constant index.
12688 if (isa<ConstantSDNode>(Op.getOperand(1)))
12694 /// Extract one bit from mask vector, like v16i1 or v8i1.
12695 /// AVX-512 feature.
12697 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12698 SDValue Vec = Op.getOperand(0);
12700 MVT VecVT = Vec.getSimpleValueType();
12701 SDValue Idx = Op.getOperand(1);
12702 MVT EltVT = Op.getSimpleValueType();
12704 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12706 // variable index can't be handled in mask registers,
12707 // extend vector to VR512
12708 if (!isa<ConstantSDNode>(Idx)) {
12709 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12710 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12711 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12712 ExtVT.getVectorElementType(), Ext, Idx);
12713 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12716 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12717 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12718 unsigned MaxSift = rc->getSize()*8 - 1;
12719 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12720 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12721 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12722 DAG.getConstant(MaxSift, MVT::i8));
12723 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12724 DAG.getIntPtrConstant(0));
12728 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12729 SelectionDAG &DAG) const {
12731 SDValue Vec = Op.getOperand(0);
12732 MVT VecVT = Vec.getSimpleValueType();
12733 SDValue Idx = Op.getOperand(1);
12735 if (Op.getSimpleValueType() == MVT::i1)
12736 return ExtractBitFromMaskVector(Op, DAG);
12738 if (!isa<ConstantSDNode>(Idx)) {
12739 if (VecVT.is512BitVector() ||
12740 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12741 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12744 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12745 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12746 MaskEltVT.getSizeInBits());
12748 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12749 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12750 getZeroVector(MaskVT, Subtarget, DAG, dl),
12751 Idx, DAG.getConstant(0, getPointerTy()));
12752 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12753 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12754 Perm, DAG.getConstant(0, getPointerTy()));
12759 // If this is a 256-bit vector result, first extract the 128-bit vector and
12760 // then extract the element from the 128-bit vector.
12761 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12763 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12764 // Get the 128-bit vector.
12765 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12766 MVT EltVT = VecVT.getVectorElementType();
12768 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12770 //if (IdxVal >= NumElems/2)
12771 // IdxVal -= NumElems/2;
12772 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12773 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12774 DAG.getConstant(IdxVal, MVT::i32));
12777 assert(VecVT.is128BitVector() && "Unexpected vector length");
12779 if (Subtarget->hasSSE41()) {
12780 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12785 MVT VT = Op.getSimpleValueType();
12786 // TODO: handle v16i8.
12787 if (VT.getSizeInBits() == 16) {
12788 SDValue Vec = Op.getOperand(0);
12789 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12791 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12792 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12793 DAG.getNode(ISD::BITCAST, dl,
12795 Op.getOperand(1)));
12796 // Transform it so it match pextrw which produces a 32-bit result.
12797 MVT EltVT = MVT::i32;
12798 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12799 Op.getOperand(0), Op.getOperand(1));
12800 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12801 DAG.getValueType(VT));
12802 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12805 if (VT.getSizeInBits() == 32) {
12806 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12810 // SHUFPS the element to the lowest double word, then movss.
12811 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12812 MVT VVT = Op.getOperand(0).getSimpleValueType();
12813 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12814 DAG.getUNDEF(VVT), Mask);
12815 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12816 DAG.getIntPtrConstant(0));
12819 if (VT.getSizeInBits() == 64) {
12820 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12821 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12822 // to match extract_elt for f64.
12823 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12827 // UNPCKHPD the element to the lowest double word, then movsd.
12828 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12829 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12830 int Mask[2] = { 1, -1 };
12831 MVT VVT = Op.getOperand(0).getSimpleValueType();
12832 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12833 DAG.getUNDEF(VVT), Mask);
12834 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12835 DAG.getIntPtrConstant(0));
12841 /// Insert one bit to mask vector, like v16i1 or v8i1.
12842 /// AVX-512 feature.
12844 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12846 SDValue Vec = Op.getOperand(0);
12847 SDValue Elt = Op.getOperand(1);
12848 SDValue Idx = Op.getOperand(2);
12849 MVT VecVT = Vec.getSimpleValueType();
12851 if (!isa<ConstantSDNode>(Idx)) {
12852 // Non constant index. Extend source and destination,
12853 // insert element and then truncate the result.
12854 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12855 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12856 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12857 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12858 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12859 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12862 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12863 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12864 if (Vec.getOpcode() == ISD::UNDEF)
12865 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12866 DAG.getConstant(IdxVal, MVT::i8));
12867 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12868 unsigned MaxSift = rc->getSize()*8 - 1;
12869 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12870 DAG.getConstant(MaxSift, MVT::i8));
12871 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12872 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12873 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12876 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12877 SelectionDAG &DAG) const {
12878 MVT VT = Op.getSimpleValueType();
12879 MVT EltVT = VT.getVectorElementType();
12881 if (EltVT == MVT::i1)
12882 return InsertBitToMaskVector(Op, DAG);
12885 SDValue N0 = Op.getOperand(0);
12886 SDValue N1 = Op.getOperand(1);
12887 SDValue N2 = Op.getOperand(2);
12888 if (!isa<ConstantSDNode>(N2))
12890 auto *N2C = cast<ConstantSDNode>(N2);
12891 unsigned IdxVal = N2C->getZExtValue();
12893 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12894 // into that, and then insert the subvector back into the result.
12895 if (VT.is256BitVector() || VT.is512BitVector()) {
12896 // Get the desired 128-bit vector half.
12897 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12899 // Insert the element into the desired half.
12900 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12901 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12903 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12904 DAG.getConstant(IdxIn128, MVT::i32));
12906 // Insert the changed part back to the 256-bit vector
12907 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12909 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12911 if (Subtarget->hasSSE41()) {
12912 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12914 if (VT == MVT::v8i16) {
12915 Opc = X86ISD::PINSRW;
12917 assert(VT == MVT::v16i8);
12918 Opc = X86ISD::PINSRB;
12921 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12923 if (N1.getValueType() != MVT::i32)
12924 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12925 if (N2.getValueType() != MVT::i32)
12926 N2 = DAG.getIntPtrConstant(IdxVal);
12927 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12930 if (EltVT == MVT::f32) {
12931 // Bits [7:6] of the constant are the source select. This will always be
12932 // zero here. The DAG Combiner may combine an extract_elt index into
12934 // bits. For example (insert (extract, 3), 2) could be matched by
12936 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12937 // Bits [5:4] of the constant are the destination select. This is the
12938 // value of the incoming immediate.
12939 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12940 // combine either bitwise AND or insert of float 0.0 to set these bits.
12941 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12942 // Create this as a scalar to vector..
12943 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12944 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12947 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12948 // PINSR* works with constant index.
12953 if (EltVT == MVT::i8)
12956 if (EltVT.getSizeInBits() == 16) {
12957 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12958 // as its second argument.
12959 if (N1.getValueType() != MVT::i32)
12960 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12961 if (N2.getValueType() != MVT::i32)
12962 N2 = DAG.getIntPtrConstant(IdxVal);
12963 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12968 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12970 MVT OpVT = Op.getSimpleValueType();
12972 // If this is a 256-bit vector result, first insert into a 128-bit
12973 // vector and then insert into the 256-bit vector.
12974 if (!OpVT.is128BitVector()) {
12975 // Insert into a 128-bit vector.
12976 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12977 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12978 OpVT.getVectorNumElements() / SizeFactor);
12980 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12982 // Insert the 128-bit vector.
12983 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12986 if (OpVT == MVT::v1i64 &&
12987 Op.getOperand(0).getValueType() == MVT::i64)
12988 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12990 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12991 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12992 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12993 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12996 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12997 // a simple subregister reference or explicit instructions to grab
12998 // upper bits of a vector.
12999 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13000 SelectionDAG &DAG) {
13002 SDValue In = Op.getOperand(0);
13003 SDValue Idx = Op.getOperand(1);
13004 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13005 MVT ResVT = Op.getSimpleValueType();
13006 MVT InVT = In.getSimpleValueType();
13008 if (Subtarget->hasFp256()) {
13009 if (ResVT.is128BitVector() &&
13010 (InVT.is256BitVector() || InVT.is512BitVector()) &&
13011 isa<ConstantSDNode>(Idx)) {
13012 return Extract128BitVector(In, IdxVal, DAG, dl);
13014 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
13015 isa<ConstantSDNode>(Idx)) {
13016 return Extract256BitVector(In, IdxVal, DAG, dl);
13022 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
13023 // simple superregister reference or explicit instructions to insert
13024 // the upper bits of a vector.
13025 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
13026 SelectionDAG &DAG) {
13027 if (Subtarget->hasFp256()) {
13028 SDLoc dl(Op.getNode());
13029 SDValue Vec = Op.getNode()->getOperand(0);
13030 SDValue SubVec = Op.getNode()->getOperand(1);
13031 SDValue Idx = Op.getNode()->getOperand(2);
13033 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
13034 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
13035 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
13036 isa<ConstantSDNode>(Idx)) {
13037 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13038 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13041 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13042 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13043 isa<ConstantSDNode>(Idx)) {
13044 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13045 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13051 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13052 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13053 // one of the above mentioned nodes. It has to be wrapped because otherwise
13054 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13055 // be used to form addressing mode. These wrapped nodes will be selected
13058 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13059 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13061 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13062 // global base reg.
13063 unsigned char OpFlag = 0;
13064 unsigned WrapperKind = X86ISD::Wrapper;
13065 CodeModel::Model M = DAG.getTarget().getCodeModel();
13067 if (Subtarget->isPICStyleRIPRel() &&
13068 (M == CodeModel::Small || M == CodeModel::Kernel))
13069 WrapperKind = X86ISD::WrapperRIP;
13070 else if (Subtarget->isPICStyleGOT())
13071 OpFlag = X86II::MO_GOTOFF;
13072 else if (Subtarget->isPICStyleStubPIC())
13073 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13075 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13076 CP->getAlignment(),
13077 CP->getOffset(), OpFlag);
13079 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13080 // With PIC, the address is actually $g + Offset.
13082 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13083 DAG.getNode(X86ISD::GlobalBaseReg,
13084 SDLoc(), getPointerTy()),
13091 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13092 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13094 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13095 // global base reg.
13096 unsigned char OpFlag = 0;
13097 unsigned WrapperKind = X86ISD::Wrapper;
13098 CodeModel::Model M = DAG.getTarget().getCodeModel();
13100 if (Subtarget->isPICStyleRIPRel() &&
13101 (M == CodeModel::Small || M == CodeModel::Kernel))
13102 WrapperKind = X86ISD::WrapperRIP;
13103 else if (Subtarget->isPICStyleGOT())
13104 OpFlag = X86II::MO_GOTOFF;
13105 else if (Subtarget->isPICStyleStubPIC())
13106 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13108 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13111 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13113 // With PIC, the address is actually $g + Offset.
13115 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13116 DAG.getNode(X86ISD::GlobalBaseReg,
13117 SDLoc(), getPointerTy()),
13124 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13125 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13127 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13128 // global base reg.
13129 unsigned char OpFlag = 0;
13130 unsigned WrapperKind = X86ISD::Wrapper;
13131 CodeModel::Model M = DAG.getTarget().getCodeModel();
13133 if (Subtarget->isPICStyleRIPRel() &&
13134 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13135 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13136 OpFlag = X86II::MO_GOTPCREL;
13137 WrapperKind = X86ISD::WrapperRIP;
13138 } else if (Subtarget->isPICStyleGOT()) {
13139 OpFlag = X86II::MO_GOT;
13140 } else if (Subtarget->isPICStyleStubPIC()) {
13141 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13142 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13143 OpFlag = X86II::MO_DARWIN_NONLAZY;
13146 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13149 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13151 // With PIC, the address is actually $g + Offset.
13152 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13153 !Subtarget->is64Bit()) {
13154 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13155 DAG.getNode(X86ISD::GlobalBaseReg,
13156 SDLoc(), getPointerTy()),
13160 // For symbols that require a load from a stub to get the address, emit the
13162 if (isGlobalStubReference(OpFlag))
13163 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13164 MachinePointerInfo::getGOT(), false, false, false, 0);
13170 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13171 // Create the TargetBlockAddressAddress node.
13172 unsigned char OpFlags =
13173 Subtarget->ClassifyBlockAddressReference();
13174 CodeModel::Model M = DAG.getTarget().getCodeModel();
13175 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13176 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13178 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13181 if (Subtarget->isPICStyleRIPRel() &&
13182 (M == CodeModel::Small || M == CodeModel::Kernel))
13183 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13185 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13187 // With PIC, the address is actually $g + Offset.
13188 if (isGlobalRelativeToPICBase(OpFlags)) {
13189 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13190 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13198 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13199 int64_t Offset, SelectionDAG &DAG) const {
13200 // Create the TargetGlobalAddress node, folding in the constant
13201 // offset if it is legal.
13202 unsigned char OpFlags =
13203 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13204 CodeModel::Model M = DAG.getTarget().getCodeModel();
13206 if (OpFlags == X86II::MO_NO_FLAG &&
13207 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13208 // A direct static reference to a global.
13209 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13212 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13215 if (Subtarget->isPICStyleRIPRel() &&
13216 (M == CodeModel::Small || M == CodeModel::Kernel))
13217 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13219 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13221 // With PIC, the address is actually $g + Offset.
13222 if (isGlobalRelativeToPICBase(OpFlags)) {
13223 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13224 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13228 // For globals that require a load from a stub to get the address, emit the
13230 if (isGlobalStubReference(OpFlags))
13231 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13232 MachinePointerInfo::getGOT(), false, false, false, 0);
13234 // If there was a non-zero offset that we didn't fold, create an explicit
13235 // addition for it.
13237 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13238 DAG.getConstant(Offset, getPointerTy()));
13244 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13245 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13246 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13247 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13251 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13252 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13253 unsigned char OperandFlags, bool LocalDynamic = false) {
13254 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13255 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13257 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13258 GA->getValueType(0),
13262 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13266 SDValue Ops[] = { Chain, TGA, *InFlag };
13267 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13269 SDValue Ops[] = { Chain, TGA };
13270 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13273 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13274 MFI->setAdjustsStack(true);
13275 MFI->setHasCalls(true);
13277 SDValue Flag = Chain.getValue(1);
13278 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13281 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13283 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13286 SDLoc dl(GA); // ? function entry point might be better
13287 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13288 DAG.getNode(X86ISD::GlobalBaseReg,
13289 SDLoc(), PtrVT), InFlag);
13290 InFlag = Chain.getValue(1);
13292 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13295 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13297 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13299 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13300 X86::RAX, X86II::MO_TLSGD);
13303 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13309 // Get the start address of the TLS block for this module.
13310 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13311 .getInfo<X86MachineFunctionInfo>();
13312 MFI->incNumLocalDynamicTLSAccesses();
13316 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13317 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13320 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13321 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13322 InFlag = Chain.getValue(1);
13323 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13324 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13327 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13331 unsigned char OperandFlags = X86II::MO_DTPOFF;
13332 unsigned WrapperKind = X86ISD::Wrapper;
13333 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13334 GA->getValueType(0),
13335 GA->getOffset(), OperandFlags);
13336 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13338 // Add x@dtpoff with the base.
13339 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13342 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13343 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13344 const EVT PtrVT, TLSModel::Model model,
13345 bool is64Bit, bool isPIC) {
13348 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13349 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13350 is64Bit ? 257 : 256));
13352 SDValue ThreadPointer =
13353 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13354 MachinePointerInfo(Ptr), false, false, false, 0);
13356 unsigned char OperandFlags = 0;
13357 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13359 unsigned WrapperKind = X86ISD::Wrapper;
13360 if (model == TLSModel::LocalExec) {
13361 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13362 } else if (model == TLSModel::InitialExec) {
13364 OperandFlags = X86II::MO_GOTTPOFF;
13365 WrapperKind = X86ISD::WrapperRIP;
13367 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13370 llvm_unreachable("Unexpected model");
13373 // emit "addl x@ntpoff,%eax" (local exec)
13374 // or "addl x@indntpoff,%eax" (initial exec)
13375 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13377 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13378 GA->getOffset(), OperandFlags);
13379 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13381 if (model == TLSModel::InitialExec) {
13382 if (isPIC && !is64Bit) {
13383 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13384 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13388 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13389 MachinePointerInfo::getGOT(), false, false, false, 0);
13392 // The address of the thread local variable is the add of the thread
13393 // pointer with the offset of the variable.
13394 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13398 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13400 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13401 const GlobalValue *GV = GA->getGlobal();
13403 if (Subtarget->isTargetELF()) {
13404 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13407 case TLSModel::GeneralDynamic:
13408 if (Subtarget->is64Bit())
13409 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13410 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13411 case TLSModel::LocalDynamic:
13412 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13413 Subtarget->is64Bit());
13414 case TLSModel::InitialExec:
13415 case TLSModel::LocalExec:
13416 return LowerToTLSExecModel(
13417 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13418 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13420 llvm_unreachable("Unknown TLS model.");
13423 if (Subtarget->isTargetDarwin()) {
13424 // Darwin only has one model of TLS. Lower to that.
13425 unsigned char OpFlag = 0;
13426 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13427 X86ISD::WrapperRIP : X86ISD::Wrapper;
13429 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13430 // global base reg.
13431 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13432 !Subtarget->is64Bit();
13434 OpFlag = X86II::MO_TLVP_PIC_BASE;
13436 OpFlag = X86II::MO_TLVP;
13438 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13439 GA->getValueType(0),
13440 GA->getOffset(), OpFlag);
13441 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13443 // With PIC32, the address is actually $g + Offset.
13445 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13446 DAG.getNode(X86ISD::GlobalBaseReg,
13447 SDLoc(), getPointerTy()),
13450 // Lowering the machine isd will make sure everything is in the right
13452 SDValue Chain = DAG.getEntryNode();
13453 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13454 SDValue Args[] = { Chain, Offset };
13455 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13457 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13458 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13459 MFI->setAdjustsStack(true);
13461 // And our return value (tls address) is in the standard call return value
13463 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13464 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13465 Chain.getValue(1));
13468 if (Subtarget->isTargetKnownWindowsMSVC() ||
13469 Subtarget->isTargetWindowsGNU()) {
13470 // Just use the implicit TLS architecture
13471 // Need to generate someting similar to:
13472 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13474 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13475 // mov rcx, qword [rdx+rcx*8]
13476 // mov eax, .tls$:tlsvar
13477 // [rax+rcx] contains the address
13478 // Windows 64bit: gs:0x58
13479 // Windows 32bit: fs:__tls_array
13482 SDValue Chain = DAG.getEntryNode();
13484 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13485 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13486 // use its literal value of 0x2C.
13487 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13488 ? Type::getInt8PtrTy(*DAG.getContext(),
13490 : Type::getInt32PtrTy(*DAG.getContext(),
13494 Subtarget->is64Bit()
13495 ? DAG.getIntPtrConstant(0x58)
13496 : (Subtarget->isTargetWindowsGNU()
13497 ? DAG.getIntPtrConstant(0x2C)
13498 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13500 SDValue ThreadPointer =
13501 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13502 MachinePointerInfo(Ptr), false, false, false, 0);
13504 // Load the _tls_index variable
13505 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13506 if (Subtarget->is64Bit())
13507 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13508 IDX, MachinePointerInfo(), MVT::i32,
13509 false, false, false, 0);
13511 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13512 false, false, false, 0);
13514 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13516 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13518 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13519 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13520 false, false, false, 0);
13522 // Get the offset of start of .tls section
13523 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13524 GA->getValueType(0),
13525 GA->getOffset(), X86II::MO_SECREL);
13526 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13528 // The address of the thread local variable is the add of the thread
13529 // pointer with the offset of the variable.
13530 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13533 llvm_unreachable("TLS not implemented for this target.");
13536 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13537 /// and take a 2 x i32 value to shift plus a shift amount.
13538 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13539 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13540 MVT VT = Op.getSimpleValueType();
13541 unsigned VTBits = VT.getSizeInBits();
13543 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13544 SDValue ShOpLo = Op.getOperand(0);
13545 SDValue ShOpHi = Op.getOperand(1);
13546 SDValue ShAmt = Op.getOperand(2);
13547 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13548 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13550 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13551 DAG.getConstant(VTBits - 1, MVT::i8));
13552 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13553 DAG.getConstant(VTBits - 1, MVT::i8))
13554 : DAG.getConstant(0, VT);
13556 SDValue Tmp2, Tmp3;
13557 if (Op.getOpcode() == ISD::SHL_PARTS) {
13558 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13559 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13561 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13562 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13565 // If the shift amount is larger or equal than the width of a part we can't
13566 // rely on the results of shld/shrd. Insert a test and select the appropriate
13567 // values for large shift amounts.
13568 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13569 DAG.getConstant(VTBits, MVT::i8));
13570 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13571 AndNode, DAG.getConstant(0, MVT::i8));
13574 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13575 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13576 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13578 if (Op.getOpcode() == ISD::SHL_PARTS) {
13579 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13580 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13582 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13583 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13586 SDValue Ops[2] = { Lo, Hi };
13587 return DAG.getMergeValues(Ops, dl);
13590 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13591 SelectionDAG &DAG) const {
13592 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13595 if (SrcVT.isVector()) {
13596 if (SrcVT.getVectorElementType() == MVT::i1) {
13597 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13598 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13599 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13600 Op.getOperand(0)));
13605 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13606 "Unknown SINT_TO_FP to lower!");
13608 // These are really Legal; return the operand so the caller accepts it as
13610 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13612 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13613 Subtarget->is64Bit()) {
13617 unsigned Size = SrcVT.getSizeInBits()/8;
13618 MachineFunction &MF = DAG.getMachineFunction();
13619 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13620 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13621 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13623 MachinePointerInfo::getFixedStack(SSFI),
13625 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13628 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13630 SelectionDAG &DAG) const {
13634 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13636 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13638 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13640 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13642 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13643 MachineMemOperand *MMO;
13645 int SSFI = FI->getIndex();
13647 DAG.getMachineFunction()
13648 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13649 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13651 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13652 StackSlot = StackSlot.getOperand(1);
13654 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13655 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13657 Tys, Ops, SrcVT, MMO);
13660 Chain = Result.getValue(1);
13661 SDValue InFlag = Result.getValue(2);
13663 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13664 // shouldn't be necessary except that RFP cannot be live across
13665 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13666 MachineFunction &MF = DAG.getMachineFunction();
13667 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13668 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13669 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13670 Tys = DAG.getVTList(MVT::Other);
13672 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13674 MachineMemOperand *MMO =
13675 DAG.getMachineFunction()
13676 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13677 MachineMemOperand::MOStore, SSFISize, SSFISize);
13679 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13680 Ops, Op.getValueType(), MMO);
13681 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13682 MachinePointerInfo::getFixedStack(SSFI),
13683 false, false, false, 0);
13689 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13690 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13691 SelectionDAG &DAG) const {
13692 // This algorithm is not obvious. Here it is what we're trying to output:
13695 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13696 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13698 haddpd %xmm0, %xmm0
13700 pshufd $0x4e, %xmm0, %xmm1
13706 LLVMContext *Context = DAG.getContext();
13708 // Build some magic constants.
13709 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13710 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13711 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13713 SmallVector<Constant*,2> CV1;
13715 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13716 APInt(64, 0x4330000000000000ULL))));
13718 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13719 APInt(64, 0x4530000000000000ULL))));
13720 Constant *C1 = ConstantVector::get(CV1);
13721 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13723 // Load the 64-bit value into an XMM register.
13724 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13726 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13727 MachinePointerInfo::getConstantPool(),
13728 false, false, false, 16);
13729 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13730 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13733 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13734 MachinePointerInfo::getConstantPool(),
13735 false, false, false, 16);
13736 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13737 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13740 if (Subtarget->hasSSE3()) {
13741 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13742 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13744 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13745 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13747 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13748 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13752 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13753 DAG.getIntPtrConstant(0));
13756 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13757 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13758 SelectionDAG &DAG) const {
13760 // FP constant to bias correct the final result.
13761 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13764 // Load the 32-bit value into an XMM register.
13765 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13768 // Zero out the upper parts of the register.
13769 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13771 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13772 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13773 DAG.getIntPtrConstant(0));
13775 // Or the load with the bias.
13776 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13777 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13778 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13779 MVT::v2f64, Load)),
13780 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13781 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13782 MVT::v2f64, Bias)));
13783 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13784 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13785 DAG.getIntPtrConstant(0));
13787 // Subtract the bias.
13788 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13790 // Handle final rounding.
13791 EVT DestVT = Op.getValueType();
13793 if (DestVT.bitsLT(MVT::f64))
13794 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13795 DAG.getIntPtrConstant(0));
13796 if (DestVT.bitsGT(MVT::f64))
13797 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13799 // Handle final rounding.
13803 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13804 const X86Subtarget &Subtarget) {
13805 // The algorithm is the following:
13806 // #ifdef __SSE4_1__
13807 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13808 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13809 // (uint4) 0x53000000, 0xaa);
13811 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13812 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13814 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13815 // return (float4) lo + fhi;
13818 SDValue V = Op->getOperand(0);
13819 EVT VecIntVT = V.getValueType();
13820 bool Is128 = VecIntVT == MVT::v4i32;
13821 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13822 // If we convert to something else than the supported type, e.g., to v4f64,
13824 if (VecFloatVT != Op->getValueType(0))
13827 unsigned NumElts = VecIntVT.getVectorNumElements();
13828 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13829 "Unsupported custom type");
13830 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13832 // In the #idef/#else code, we have in common:
13833 // - The vector of constants:
13839 // Create the splat vector for 0x4b000000.
13840 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13841 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13842 CstLow, CstLow, CstLow, CstLow};
13843 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13844 makeArrayRef(&CstLowArray[0], NumElts));
13845 // Create the splat vector for 0x53000000.
13846 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13847 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13848 CstHigh, CstHigh, CstHigh, CstHigh};
13849 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13850 makeArrayRef(&CstHighArray[0], NumElts));
13852 // Create the right shift.
13853 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13854 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13855 CstShift, CstShift, CstShift, CstShift};
13856 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13857 makeArrayRef(&CstShiftArray[0], NumElts));
13858 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13861 if (Subtarget.hasSSE41()) {
13862 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13863 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13864 SDValue VecCstLowBitcast =
13865 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13866 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13867 // Low will be bitcasted right away, so do not bother bitcasting back to its
13869 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13870 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13871 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13872 // (uint4) 0x53000000, 0xaa);
13873 SDValue VecCstHighBitcast =
13874 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13875 SDValue VecShiftBitcast =
13876 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13877 // High will be bitcasted right away, so do not bother bitcasting back to
13878 // its original type.
13879 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13880 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13882 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13883 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13884 CstMask, CstMask, CstMask);
13885 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13886 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13887 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13889 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13890 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13893 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13894 SDValue CstFAdd = DAG.getConstantFP(
13895 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13896 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13897 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13898 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13899 makeArrayRef(&CstFAddArray[0], NumElts));
13901 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13902 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13904 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13905 // return (float4) lo + fhi;
13906 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13907 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13910 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13911 SelectionDAG &DAG) const {
13912 SDValue N0 = Op.getOperand(0);
13913 MVT SVT = N0.getSimpleValueType();
13916 switch (SVT.SimpleTy) {
13918 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13923 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13924 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13925 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13929 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13931 llvm_unreachable(nullptr);
13934 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13935 SelectionDAG &DAG) const {
13936 SDValue N0 = Op.getOperand(0);
13939 if (Op.getValueType().isVector())
13940 return lowerUINT_TO_FP_vec(Op, DAG);
13942 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13943 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13944 // the optimization here.
13945 if (DAG.SignBitIsZero(N0))
13946 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13948 MVT SrcVT = N0.getSimpleValueType();
13949 MVT DstVT = Op.getSimpleValueType();
13950 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13951 return LowerUINT_TO_FP_i64(Op, DAG);
13952 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13953 return LowerUINT_TO_FP_i32(Op, DAG);
13954 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13957 // Make a 64-bit buffer, and use it to build an FILD.
13958 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13959 if (SrcVT == MVT::i32) {
13960 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13961 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13962 getPointerTy(), StackSlot, WordOff);
13963 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13964 StackSlot, MachinePointerInfo(),
13966 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13967 OffsetSlot, MachinePointerInfo(),
13969 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13973 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13974 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13975 StackSlot, MachinePointerInfo(),
13977 // For i64 source, we need to add the appropriate power of 2 if the input
13978 // was negative. This is the same as the optimization in
13979 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13980 // we must be careful to do the computation in x87 extended precision, not
13981 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13982 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13983 MachineMemOperand *MMO =
13984 DAG.getMachineFunction()
13985 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13986 MachineMemOperand::MOLoad, 8, 8);
13988 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13989 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13990 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13993 APInt FF(32, 0x5F800000ULL);
13995 // Check whether the sign bit is set.
13996 SDValue SignSet = DAG.getSetCC(dl,
13997 getSetCCResultType(*DAG.getContext(), MVT::i64),
13998 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
14001 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
14002 SDValue FudgePtr = DAG.getConstantPool(
14003 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
14006 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
14007 SDValue Zero = DAG.getIntPtrConstant(0);
14008 SDValue Four = DAG.getIntPtrConstant(4);
14009 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
14011 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
14013 // Load the value out, extending it from f32 to f80.
14014 // FIXME: Avoid the extend by constructing the right constant pool?
14015 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
14016 FudgePtr, MachinePointerInfo::getConstantPool(),
14017 MVT::f32, false, false, false, 4);
14018 // Extend everything to 80 bits to force it to be done on x87.
14019 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
14020 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
14023 std::pair<SDValue,SDValue>
14024 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
14025 bool IsSigned, bool IsReplace) const {
14028 EVT DstTy = Op.getValueType();
14030 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
14031 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
14035 assert(DstTy.getSimpleVT() <= MVT::i64 &&
14036 DstTy.getSimpleVT() >= MVT::i16 &&
14037 "Unknown FP_TO_INT to lower!");
14039 // These are really Legal.
14040 if (DstTy == MVT::i32 &&
14041 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14042 return std::make_pair(SDValue(), SDValue());
14043 if (Subtarget->is64Bit() &&
14044 DstTy == MVT::i64 &&
14045 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14046 return std::make_pair(SDValue(), SDValue());
14048 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14049 // stack slot, or into the FTOL runtime function.
14050 MachineFunction &MF = DAG.getMachineFunction();
14051 unsigned MemSize = DstTy.getSizeInBits()/8;
14052 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14053 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14056 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14057 Opc = X86ISD::WIN_FTOL;
14059 switch (DstTy.getSimpleVT().SimpleTy) {
14060 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14061 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14062 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14063 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14066 SDValue Chain = DAG.getEntryNode();
14067 SDValue Value = Op.getOperand(0);
14068 EVT TheVT = Op.getOperand(0).getValueType();
14069 // FIXME This causes a redundant load/store if the SSE-class value is already
14070 // in memory, such as if it is on the callstack.
14071 if (isScalarFPTypeInSSEReg(TheVT)) {
14072 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14073 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14074 MachinePointerInfo::getFixedStack(SSFI),
14076 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14078 Chain, StackSlot, DAG.getValueType(TheVT)
14081 MachineMemOperand *MMO =
14082 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14083 MachineMemOperand::MOLoad, MemSize, MemSize);
14084 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14085 Chain = Value.getValue(1);
14086 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14087 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14090 MachineMemOperand *MMO =
14091 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14092 MachineMemOperand::MOStore, MemSize, MemSize);
14094 if (Opc != X86ISD::WIN_FTOL) {
14095 // Build the FP_TO_INT*_IN_MEM
14096 SDValue Ops[] = { Chain, Value, StackSlot };
14097 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14099 return std::make_pair(FIST, StackSlot);
14101 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14102 DAG.getVTList(MVT::Other, MVT::Glue),
14104 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14105 MVT::i32, ftol.getValue(1));
14106 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14107 MVT::i32, eax.getValue(2));
14108 SDValue Ops[] = { eax, edx };
14109 SDValue pair = IsReplace
14110 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14111 : DAG.getMergeValues(Ops, DL);
14112 return std::make_pair(pair, SDValue());
14116 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14117 const X86Subtarget *Subtarget) {
14118 MVT VT = Op->getSimpleValueType(0);
14119 SDValue In = Op->getOperand(0);
14120 MVT InVT = In.getSimpleValueType();
14123 // Optimize vectors in AVX mode:
14126 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14127 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14128 // Concat upper and lower parts.
14131 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14132 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14133 // Concat upper and lower parts.
14136 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14137 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14138 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14141 if (Subtarget->hasInt256())
14142 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14144 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14145 SDValue Undef = DAG.getUNDEF(InVT);
14146 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14147 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14148 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14150 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14151 VT.getVectorNumElements()/2);
14153 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14154 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14156 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14159 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14160 SelectionDAG &DAG) {
14161 MVT VT = Op->getSimpleValueType(0);
14162 SDValue In = Op->getOperand(0);
14163 MVT InVT = In.getSimpleValueType();
14165 unsigned int NumElts = VT.getVectorNumElements();
14166 if (NumElts != 8 && NumElts != 16)
14169 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14170 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14172 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14173 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14174 // Now we have only mask extension
14175 assert(InVT.getVectorElementType() == MVT::i1);
14176 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14177 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14178 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14179 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14180 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14181 MachinePointerInfo::getConstantPool(),
14182 false, false, false, Alignment);
14184 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14185 if (VT.is512BitVector())
14187 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14190 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14191 SelectionDAG &DAG) {
14192 if (Subtarget->hasFp256()) {
14193 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14201 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14202 SelectionDAG &DAG) {
14204 MVT VT = Op.getSimpleValueType();
14205 SDValue In = Op.getOperand(0);
14206 MVT SVT = In.getSimpleValueType();
14208 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14209 return LowerZERO_EXTEND_AVX512(Op, DAG);
14211 if (Subtarget->hasFp256()) {
14212 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14217 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14218 VT.getVectorNumElements() != SVT.getVectorNumElements());
14222 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14224 MVT VT = Op.getSimpleValueType();
14225 SDValue In = Op.getOperand(0);
14226 MVT InVT = In.getSimpleValueType();
14228 if (VT == MVT::i1) {
14229 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14230 "Invalid scalar TRUNCATE operation");
14231 if (InVT.getSizeInBits() >= 32)
14233 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14234 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14236 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14237 "Invalid TRUNCATE operation");
14239 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14240 if (VT.getVectorElementType().getSizeInBits() >=8)
14241 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14243 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14244 unsigned NumElts = InVT.getVectorNumElements();
14245 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14246 if (InVT.getSizeInBits() < 512) {
14247 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14248 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14252 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14253 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14254 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14255 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14256 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14257 MachinePointerInfo::getConstantPool(),
14258 false, false, false, Alignment);
14259 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14260 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14261 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14264 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14265 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14266 if (Subtarget->hasInt256()) {
14267 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14268 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14269 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14271 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14272 DAG.getIntPtrConstant(0));
14275 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14276 DAG.getIntPtrConstant(0));
14277 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14278 DAG.getIntPtrConstant(2));
14279 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14280 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14281 static const int ShufMask[] = {0, 2, 4, 6};
14282 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14285 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14286 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14287 if (Subtarget->hasInt256()) {
14288 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14290 SmallVector<SDValue,32> pshufbMask;
14291 for (unsigned i = 0; i < 2; ++i) {
14292 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14293 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14294 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14295 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14296 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14297 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14298 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14299 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14300 for (unsigned j = 0; j < 8; ++j)
14301 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14303 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14304 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14305 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14307 static const int ShufMask[] = {0, 2, -1, -1};
14308 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14310 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14311 DAG.getIntPtrConstant(0));
14312 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14315 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14316 DAG.getIntPtrConstant(0));
14318 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14319 DAG.getIntPtrConstant(4));
14321 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14322 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14324 // The PSHUFB mask:
14325 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14326 -1, -1, -1, -1, -1, -1, -1, -1};
14328 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14329 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14330 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14332 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14333 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14335 // The MOVLHPS Mask:
14336 static const int ShufMask2[] = {0, 1, 4, 5};
14337 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14338 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14341 // Handle truncation of V256 to V128 using shuffles.
14342 if (!VT.is128BitVector() || !InVT.is256BitVector())
14345 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14347 unsigned NumElems = VT.getVectorNumElements();
14348 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14350 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14351 // Prepare truncation shuffle mask
14352 for (unsigned i = 0; i != NumElems; ++i)
14353 MaskVec[i] = i * 2;
14354 SDValue V = DAG.getVectorShuffle(NVT, DL,
14355 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14356 DAG.getUNDEF(NVT), &MaskVec[0]);
14357 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14358 DAG.getIntPtrConstant(0));
14361 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14362 SelectionDAG &DAG) const {
14363 assert(!Op.getSimpleValueType().isVector());
14365 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14366 /*IsSigned=*/ true, /*IsReplace=*/ false);
14367 SDValue FIST = Vals.first, StackSlot = Vals.second;
14368 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14369 if (!FIST.getNode()) return Op;
14371 if (StackSlot.getNode())
14372 // Load the result.
14373 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14374 FIST, StackSlot, MachinePointerInfo(),
14375 false, false, false, 0);
14377 // The node is the result.
14381 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14382 SelectionDAG &DAG) const {
14383 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14384 /*IsSigned=*/ false, /*IsReplace=*/ false);
14385 SDValue FIST = Vals.first, StackSlot = Vals.second;
14386 assert(FIST.getNode() && "Unexpected failure");
14388 if (StackSlot.getNode())
14389 // Load the result.
14390 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14391 FIST, StackSlot, MachinePointerInfo(),
14392 false, false, false, 0);
14394 // The node is the result.
14398 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14400 MVT VT = Op.getSimpleValueType();
14401 SDValue In = Op.getOperand(0);
14402 MVT SVT = In.getSimpleValueType();
14404 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14406 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14407 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14408 In, DAG.getUNDEF(SVT)));
14411 /// The only differences between FABS and FNEG are the mask and the logic op.
14412 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14413 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14414 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14415 "Wrong opcode for lowering FABS or FNEG.");
14417 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14419 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14420 // into an FNABS. We'll lower the FABS after that if it is still in use.
14422 for (SDNode *User : Op->uses())
14423 if (User->getOpcode() == ISD::FNEG)
14426 SDValue Op0 = Op.getOperand(0);
14427 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14430 MVT VT = Op.getSimpleValueType();
14431 // Assume scalar op for initialization; update for vector if needed.
14432 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14433 // generate a 16-byte vector constant and logic op even for the scalar case.
14434 // Using a 16-byte mask allows folding the load of the mask with
14435 // the logic op, so it can save (~4 bytes) on code size.
14437 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14438 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14439 // decide if we should generate a 16-byte constant mask when we only need 4 or
14440 // 8 bytes for the scalar case.
14441 if (VT.isVector()) {
14442 EltVT = VT.getVectorElementType();
14443 NumElts = VT.getVectorNumElements();
14446 unsigned EltBits = EltVT.getSizeInBits();
14447 LLVMContext *Context = DAG.getContext();
14448 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14450 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14451 Constant *C = ConstantInt::get(*Context, MaskElt);
14452 C = ConstantVector::getSplat(NumElts, C);
14453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14454 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14455 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14456 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14457 MachinePointerInfo::getConstantPool(),
14458 false, false, false, Alignment);
14460 if (VT.isVector()) {
14461 // For a vector, cast operands to a vector type, perform the logic op,
14462 // and cast the result back to the original value type.
14463 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14464 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14465 SDValue Operand = IsFNABS ?
14466 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14467 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14468 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14469 return DAG.getNode(ISD::BITCAST, dl, VT,
14470 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14473 // If not vector, then scalar.
14474 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14475 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14476 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14479 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14480 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14481 LLVMContext *Context = DAG.getContext();
14482 SDValue Op0 = Op.getOperand(0);
14483 SDValue Op1 = Op.getOperand(1);
14485 MVT VT = Op.getSimpleValueType();
14486 MVT SrcVT = Op1.getSimpleValueType();
14488 // If second operand is smaller, extend it first.
14489 if (SrcVT.bitsLT(VT)) {
14490 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14493 // And if it is bigger, shrink it first.
14494 if (SrcVT.bitsGT(VT)) {
14495 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14499 // At this point the operands and the result should have the same
14500 // type, and that won't be f80 since that is not custom lowered.
14502 const fltSemantics &Sem =
14503 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14504 const unsigned SizeInBits = VT.getSizeInBits();
14506 SmallVector<Constant *, 4> CV(
14507 VT == MVT::f64 ? 2 : 4,
14508 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14510 // First, clear all bits but the sign bit from the second operand (sign).
14511 CV[0] = ConstantFP::get(*Context,
14512 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14513 Constant *C = ConstantVector::get(CV);
14514 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14515 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14516 MachinePointerInfo::getConstantPool(),
14517 false, false, false, 16);
14518 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14520 // Next, clear the sign bit from the first operand (magnitude).
14521 CV[0] = ConstantFP::get(
14522 *Context, APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14523 C = ConstantVector::get(CV);
14524 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14525 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14526 MachinePointerInfo::getConstantPool(),
14527 false, false, false, 16);
14528 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14530 // OR the magnitude value with the sign bit.
14531 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14534 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14535 SDValue N0 = Op.getOperand(0);
14537 MVT VT = Op.getSimpleValueType();
14539 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14540 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14541 DAG.getConstant(1, VT));
14542 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14545 // Check whether an OR'd tree is PTEST-able.
14546 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14547 SelectionDAG &DAG) {
14548 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14550 if (!Subtarget->hasSSE41())
14553 if (!Op->hasOneUse())
14556 SDNode *N = Op.getNode();
14559 SmallVector<SDValue, 8> Opnds;
14560 DenseMap<SDValue, unsigned> VecInMap;
14561 SmallVector<SDValue, 8> VecIns;
14562 EVT VT = MVT::Other;
14564 // Recognize a special case where a vector is casted into wide integer to
14566 Opnds.push_back(N->getOperand(0));
14567 Opnds.push_back(N->getOperand(1));
14569 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14570 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14571 // BFS traverse all OR'd operands.
14572 if (I->getOpcode() == ISD::OR) {
14573 Opnds.push_back(I->getOperand(0));
14574 Opnds.push_back(I->getOperand(1));
14575 // Re-evaluate the number of nodes to be traversed.
14576 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14580 // Quit if a non-EXTRACT_VECTOR_ELT
14581 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14584 // Quit if without a constant index.
14585 SDValue Idx = I->getOperand(1);
14586 if (!isa<ConstantSDNode>(Idx))
14589 SDValue ExtractedFromVec = I->getOperand(0);
14590 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14591 if (M == VecInMap.end()) {
14592 VT = ExtractedFromVec.getValueType();
14593 // Quit if not 128/256-bit vector.
14594 if (!VT.is128BitVector() && !VT.is256BitVector())
14596 // Quit if not the same type.
14597 if (VecInMap.begin() != VecInMap.end() &&
14598 VT != VecInMap.begin()->first.getValueType())
14600 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14601 VecIns.push_back(ExtractedFromVec);
14603 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14606 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14607 "Not extracted from 128-/256-bit vector.");
14609 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14611 for (DenseMap<SDValue, unsigned>::const_iterator
14612 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14613 // Quit if not all elements are used.
14614 if (I->second != FullMask)
14618 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14620 // Cast all vectors into TestVT for PTEST.
14621 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14622 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14624 // If more than one full vectors are evaluated, OR them first before PTEST.
14625 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14626 // Each iteration will OR 2 nodes and append the result until there is only
14627 // 1 node left, i.e. the final OR'd value of all vectors.
14628 SDValue LHS = VecIns[Slot];
14629 SDValue RHS = VecIns[Slot + 1];
14630 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14633 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14634 VecIns.back(), VecIns.back());
14637 /// \brief return true if \c Op has a use that doesn't just read flags.
14638 static bool hasNonFlagsUse(SDValue Op) {
14639 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14641 SDNode *User = *UI;
14642 unsigned UOpNo = UI.getOperandNo();
14643 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14644 // Look pass truncate.
14645 UOpNo = User->use_begin().getOperandNo();
14646 User = *User->use_begin();
14649 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14650 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14656 /// Emit nodes that will be selected as "test Op0,Op0", or something
14658 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14659 SelectionDAG &DAG) const {
14660 if (Op.getValueType() == MVT::i1)
14661 // KORTEST instruction should be selected
14662 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14663 DAG.getConstant(0, Op.getValueType()));
14665 // CF and OF aren't always set the way we want. Determine which
14666 // of these we need.
14667 bool NeedCF = false;
14668 bool NeedOF = false;
14671 case X86::COND_A: case X86::COND_AE:
14672 case X86::COND_B: case X86::COND_BE:
14675 case X86::COND_G: case X86::COND_GE:
14676 case X86::COND_L: case X86::COND_LE:
14677 case X86::COND_O: case X86::COND_NO: {
14678 // Check if we really need to set the
14679 // Overflow flag. If NoSignedWrap is present
14680 // that is not actually needed.
14681 switch (Op->getOpcode()) {
14686 const BinaryWithFlagsSDNode *BinNode =
14687 cast<BinaryWithFlagsSDNode>(Op.getNode());
14688 if (BinNode->hasNoSignedWrap())
14698 // See if we can use the EFLAGS value from the operand instead of
14699 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14700 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14701 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14702 // Emit a CMP with 0, which is the TEST pattern.
14703 //if (Op.getValueType() == MVT::i1)
14704 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14705 // DAG.getConstant(0, MVT::i1));
14706 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14707 DAG.getConstant(0, Op.getValueType()));
14709 unsigned Opcode = 0;
14710 unsigned NumOperands = 0;
14712 // Truncate operations may prevent the merge of the SETCC instruction
14713 // and the arithmetic instruction before it. Attempt to truncate the operands
14714 // of the arithmetic instruction and use a reduced bit-width instruction.
14715 bool NeedTruncation = false;
14716 SDValue ArithOp = Op;
14717 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14718 SDValue Arith = Op->getOperand(0);
14719 // Both the trunc and the arithmetic op need to have one user each.
14720 if (Arith->hasOneUse())
14721 switch (Arith.getOpcode()) {
14728 NeedTruncation = true;
14734 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14735 // which may be the result of a CAST. We use the variable 'Op', which is the
14736 // non-casted variable when we check for possible users.
14737 switch (ArithOp.getOpcode()) {
14739 // Due to an isel shortcoming, be conservative if this add is likely to be
14740 // selected as part of a load-modify-store instruction. When the root node
14741 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14742 // uses of other nodes in the match, such as the ADD in this case. This
14743 // leads to the ADD being left around and reselected, with the result being
14744 // two adds in the output. Alas, even if none our users are stores, that
14745 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14746 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14747 // climbing the DAG back to the root, and it doesn't seem to be worth the
14749 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14750 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14751 if (UI->getOpcode() != ISD::CopyToReg &&
14752 UI->getOpcode() != ISD::SETCC &&
14753 UI->getOpcode() != ISD::STORE)
14756 if (ConstantSDNode *C =
14757 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14758 // An add of one will be selected as an INC.
14759 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14760 Opcode = X86ISD::INC;
14765 // An add of negative one (subtract of one) will be selected as a DEC.
14766 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14767 Opcode = X86ISD::DEC;
14773 // Otherwise use a regular EFLAGS-setting add.
14774 Opcode = X86ISD::ADD;
14779 // If we have a constant logical shift that's only used in a comparison
14780 // against zero turn it into an equivalent AND. This allows turning it into
14781 // a TEST instruction later.
14782 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14783 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14784 EVT VT = Op.getValueType();
14785 unsigned BitWidth = VT.getSizeInBits();
14786 unsigned ShAmt = Op->getConstantOperandVal(1);
14787 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14789 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14790 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14791 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14792 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14794 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14795 DAG.getConstant(Mask, VT));
14796 DAG.ReplaceAllUsesWith(Op, New);
14802 // If the primary and result isn't used, don't bother using X86ISD::AND,
14803 // because a TEST instruction will be better.
14804 if (!hasNonFlagsUse(Op))
14810 // Due to the ISEL shortcoming noted above, be conservative if this op is
14811 // likely to be selected as part of a load-modify-store instruction.
14812 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14813 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14814 if (UI->getOpcode() == ISD::STORE)
14817 // Otherwise use a regular EFLAGS-setting instruction.
14818 switch (ArithOp.getOpcode()) {
14819 default: llvm_unreachable("unexpected operator!");
14820 case ISD::SUB: Opcode = X86ISD::SUB; break;
14821 case ISD::XOR: Opcode = X86ISD::XOR; break;
14822 case ISD::AND: Opcode = X86ISD::AND; break;
14824 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14825 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14826 if (EFLAGS.getNode())
14829 Opcode = X86ISD::OR;
14843 return SDValue(Op.getNode(), 1);
14849 // If we found that truncation is beneficial, perform the truncation and
14851 if (NeedTruncation) {
14852 EVT VT = Op.getValueType();
14853 SDValue WideVal = Op->getOperand(0);
14854 EVT WideVT = WideVal.getValueType();
14855 unsigned ConvertedOp = 0;
14856 // Use a target machine opcode to prevent further DAGCombine
14857 // optimizations that may separate the arithmetic operations
14858 // from the setcc node.
14859 switch (WideVal.getOpcode()) {
14861 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14862 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14863 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14864 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14865 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14869 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14870 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14871 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14872 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14873 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14879 // Emit a CMP with 0, which is the TEST pattern.
14880 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14881 DAG.getConstant(0, Op.getValueType()));
14883 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14884 SmallVector<SDValue, 4> Ops;
14885 for (unsigned i = 0; i != NumOperands; ++i)
14886 Ops.push_back(Op.getOperand(i));
14888 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14889 DAG.ReplaceAllUsesWith(Op, New);
14890 return SDValue(New.getNode(), 1);
14893 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14895 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14896 SDLoc dl, SelectionDAG &DAG) const {
14897 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14898 if (C->getAPIntValue() == 0)
14899 return EmitTest(Op0, X86CC, dl, DAG);
14901 if (Op0.getValueType() == MVT::i1)
14902 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14905 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14906 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14907 // Do the comparison at i32 if it's smaller, besides the Atom case.
14908 // This avoids subregister aliasing issues. Keep the smaller reference
14909 // if we're optimizing for size, however, as that'll allow better folding
14910 // of memory operations.
14911 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14912 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14913 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14914 !Subtarget->isAtom()) {
14915 unsigned ExtendOp =
14916 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14917 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14918 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14920 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14921 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14922 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14924 return SDValue(Sub.getNode(), 1);
14926 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14929 /// Convert a comparison if required by the subtarget.
14930 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14931 SelectionDAG &DAG) const {
14932 // If the subtarget does not support the FUCOMI instruction, floating-point
14933 // comparisons have to be converted.
14934 if (Subtarget->hasCMov() ||
14935 Cmp.getOpcode() != X86ISD::CMP ||
14936 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14937 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14940 // The instruction selector will select an FUCOM instruction instead of
14941 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14942 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14943 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14945 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14946 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14947 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14948 DAG.getConstant(8, MVT::i8));
14949 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14950 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14953 /// The minimum architected relative accuracy is 2^-12. We need one
14954 /// Newton-Raphson step to have a good float result (24 bits of precision).
14955 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14956 DAGCombinerInfo &DCI,
14957 unsigned &RefinementSteps,
14958 bool &UseOneConstNR) const {
14959 // FIXME: We should use instruction latency models to calculate the cost of
14960 // each potential sequence, but this is very hard to do reliably because
14961 // at least Intel's Core* chips have variable timing based on the number of
14962 // significant digits in the divisor and/or sqrt operand.
14963 if (!Subtarget->useSqrtEst())
14966 EVT VT = Op.getValueType();
14968 // SSE1 has rsqrtss and rsqrtps.
14969 // TODO: Add support for AVX512 (v16f32).
14970 // It is likely not profitable to do this for f64 because a double-precision
14971 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14972 // instructions: convert to single, rsqrtss, convert back to double, refine
14973 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14974 // along with FMA, this could be a throughput win.
14975 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14976 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14977 RefinementSteps = 1;
14978 UseOneConstNR = false;
14979 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14984 /// The minimum architected relative accuracy is 2^-12. We need one
14985 /// Newton-Raphson step to have a good float result (24 bits of precision).
14986 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14987 DAGCombinerInfo &DCI,
14988 unsigned &RefinementSteps) const {
14989 // FIXME: We should use instruction latency models to calculate the cost of
14990 // each potential sequence, but this is very hard to do reliably because
14991 // at least Intel's Core* chips have variable timing based on the number of
14992 // significant digits in the divisor.
14993 if (!Subtarget->useReciprocalEst())
14996 EVT VT = Op.getValueType();
14998 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14999 // TODO: Add support for AVX512 (v16f32).
15000 // It is likely not profitable to do this for f64 because a double-precision
15001 // reciprocal estimate with refinement on x86 prior to FMA requires
15002 // 15 instructions: convert to single, rcpss, convert back to double, refine
15003 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
15004 // along with FMA, this could be a throughput win.
15005 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
15006 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
15007 RefinementSteps = ReciprocalEstimateRefinementSteps;
15008 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
15013 static bool isAllOnes(SDValue V) {
15014 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
15015 return C && C->isAllOnesValue();
15018 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
15019 /// if it's possible.
15020 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15021 SDLoc dl, SelectionDAG &DAG) const {
15022 SDValue Op0 = And.getOperand(0);
15023 SDValue Op1 = And.getOperand(1);
15024 if (Op0.getOpcode() == ISD::TRUNCATE)
15025 Op0 = Op0.getOperand(0);
15026 if (Op1.getOpcode() == ISD::TRUNCATE)
15027 Op1 = Op1.getOperand(0);
15030 if (Op1.getOpcode() == ISD::SHL)
15031 std::swap(Op0, Op1);
15032 if (Op0.getOpcode() == ISD::SHL) {
15033 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15034 if (And00C->getZExtValue() == 1) {
15035 // If we looked past a truncate, check that it's only truncating away
15037 unsigned BitWidth = Op0.getValueSizeInBits();
15038 unsigned AndBitWidth = And.getValueSizeInBits();
15039 if (BitWidth > AndBitWidth) {
15041 DAG.computeKnownBits(Op0, Zeros, Ones);
15042 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15046 RHS = Op0.getOperand(1);
15048 } else if (Op1.getOpcode() == ISD::Constant) {
15049 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15050 uint64_t AndRHSVal = AndRHS->getZExtValue();
15051 SDValue AndLHS = Op0;
15053 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15054 LHS = AndLHS.getOperand(0);
15055 RHS = AndLHS.getOperand(1);
15058 // Use BT if the immediate can't be encoded in a TEST instruction.
15059 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15061 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15065 if (LHS.getNode()) {
15066 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15067 // instruction. Since the shift amount is in-range-or-undefined, we know
15068 // that doing a bittest on the i32 value is ok. We extend to i32 because
15069 // the encoding for the i16 version is larger than the i32 version.
15070 // Also promote i16 to i32 for performance / code size reason.
15071 if (LHS.getValueType() == MVT::i8 ||
15072 LHS.getValueType() == MVT::i16)
15073 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15075 // If the operand types disagree, extend the shift amount to match. Since
15076 // BT ignores high bits (like shifts) we can use anyextend.
15077 if (LHS.getValueType() != RHS.getValueType())
15078 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15080 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15081 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15082 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15083 DAG.getConstant(Cond, MVT::i8), BT);
15089 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15091 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15096 // SSE Condition code mapping:
15105 switch (SetCCOpcode) {
15106 default: llvm_unreachable("Unexpected SETCC condition");
15108 case ISD::SETEQ: SSECC = 0; break;
15110 case ISD::SETGT: Swap = true; // Fallthrough
15112 case ISD::SETOLT: SSECC = 1; break;
15114 case ISD::SETGE: Swap = true; // Fallthrough
15116 case ISD::SETOLE: SSECC = 2; break;
15117 case ISD::SETUO: SSECC = 3; break;
15119 case ISD::SETNE: SSECC = 4; break;
15120 case ISD::SETULE: Swap = true; // Fallthrough
15121 case ISD::SETUGE: SSECC = 5; break;
15122 case ISD::SETULT: Swap = true; // Fallthrough
15123 case ISD::SETUGT: SSECC = 6; break;
15124 case ISD::SETO: SSECC = 7; break;
15126 case ISD::SETONE: SSECC = 8; break;
15129 std::swap(Op0, Op1);
15134 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15135 // ones, and then concatenate the result back.
15136 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15137 MVT VT = Op.getSimpleValueType();
15139 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15140 "Unsupported value type for operation");
15142 unsigned NumElems = VT.getVectorNumElements();
15144 SDValue CC = Op.getOperand(2);
15146 // Extract the LHS vectors
15147 SDValue LHS = Op.getOperand(0);
15148 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15149 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15151 // Extract the RHS vectors
15152 SDValue RHS = Op.getOperand(1);
15153 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15154 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15156 // Issue the operation on the smaller types and concatenate the result back
15157 MVT EltVT = VT.getVectorElementType();
15158 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15159 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15160 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15161 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15164 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15165 const X86Subtarget *Subtarget) {
15166 SDValue Op0 = Op.getOperand(0);
15167 SDValue Op1 = Op.getOperand(1);
15168 SDValue CC = Op.getOperand(2);
15169 MVT VT = Op.getSimpleValueType();
15172 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15173 Op.getValueType().getScalarType() == MVT::i1 &&
15174 "Cannot set masked compare for this operation");
15176 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15178 bool Unsigned = false;
15181 switch (SetCCOpcode) {
15182 default: llvm_unreachable("Unexpected SETCC condition");
15183 case ISD::SETNE: SSECC = 4; break;
15184 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15185 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15186 case ISD::SETLT: Swap = true; //fall-through
15187 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15188 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15189 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15190 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15191 case ISD::SETULE: Unsigned = true; //fall-through
15192 case ISD::SETLE: SSECC = 2; break;
15196 std::swap(Op0, Op1);
15198 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15199 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15200 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15201 DAG.getConstant(SSECC, MVT::i8));
15204 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15205 /// operand \p Op1. If non-trivial (for example because it's not constant)
15206 /// return an empty value.
15207 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15209 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15213 MVT VT = Op1.getSimpleValueType();
15214 MVT EVT = VT.getVectorElementType();
15215 unsigned n = VT.getVectorNumElements();
15216 SmallVector<SDValue, 8> ULTOp1;
15218 for (unsigned i = 0; i < n; ++i) {
15219 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15220 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15223 // Avoid underflow.
15224 APInt Val = Elt->getAPIntValue();
15228 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15231 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15234 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15235 SelectionDAG &DAG) {
15236 SDValue Op0 = Op.getOperand(0);
15237 SDValue Op1 = Op.getOperand(1);
15238 SDValue CC = Op.getOperand(2);
15239 MVT VT = Op.getSimpleValueType();
15240 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15241 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15246 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15247 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15250 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15251 unsigned Opc = X86ISD::CMPP;
15252 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15253 assert(VT.getVectorNumElements() <= 16);
15254 Opc = X86ISD::CMPM;
15256 // In the two special cases we can't handle, emit two comparisons.
15259 unsigned CombineOpc;
15260 if (SetCCOpcode == ISD::SETUEQ) {
15261 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15263 assert(SetCCOpcode == ISD::SETONE);
15264 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15267 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15268 DAG.getConstant(CC0, MVT::i8));
15269 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15270 DAG.getConstant(CC1, MVT::i8));
15271 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15273 // Handle all other FP comparisons here.
15274 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15275 DAG.getConstant(SSECC, MVT::i8));
15278 // Break 256-bit integer vector compare into smaller ones.
15279 if (VT.is256BitVector() && !Subtarget->hasInt256())
15280 return Lower256IntVSETCC(Op, DAG);
15282 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15283 EVT OpVT = Op1.getValueType();
15284 if (Subtarget->hasAVX512()) {
15285 if (Op1.getValueType().is512BitVector() ||
15286 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15287 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15288 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15290 // In AVX-512 architecture setcc returns mask with i1 elements,
15291 // But there is no compare instruction for i8 and i16 elements in KNL.
15292 // We are not talking about 512-bit operands in this case, these
15293 // types are illegal.
15295 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15296 OpVT.getVectorElementType().getSizeInBits() >= 8))
15297 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15298 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15301 // We are handling one of the integer comparisons here. Since SSE only has
15302 // GT and EQ comparisons for integer, swapping operands and multiple
15303 // operations may be required for some comparisons.
15305 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15306 bool Subus = false;
15308 switch (SetCCOpcode) {
15309 default: llvm_unreachable("Unexpected SETCC condition");
15310 case ISD::SETNE: Invert = true;
15311 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15312 case ISD::SETLT: Swap = true;
15313 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15314 case ISD::SETGE: Swap = true;
15315 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15316 Invert = true; break;
15317 case ISD::SETULT: Swap = true;
15318 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15319 FlipSigns = true; break;
15320 case ISD::SETUGE: Swap = true;
15321 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15322 FlipSigns = true; Invert = true; break;
15325 // Special case: Use min/max operations for SETULE/SETUGE
15326 MVT VET = VT.getVectorElementType();
15328 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15329 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15332 switch (SetCCOpcode) {
15334 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15335 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15338 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15341 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15342 if (!MinMax && hasSubus) {
15343 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15345 // t = psubus Op0, Op1
15346 // pcmpeq t, <0..0>
15347 switch (SetCCOpcode) {
15349 case ISD::SETULT: {
15350 // If the comparison is against a constant we can turn this into a
15351 // setule. With psubus, setule does not require a swap. This is
15352 // beneficial because the constant in the register is no longer
15353 // destructed as the destination so it can be hoisted out of a loop.
15354 // Only do this pre-AVX since vpcmp* is no longer destructive.
15355 if (Subtarget->hasAVX())
15357 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15358 if (ULEOp1.getNode()) {
15360 Subus = true; Invert = false; Swap = false;
15364 // Psubus is better than flip-sign because it requires no inversion.
15365 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15366 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15370 Opc = X86ISD::SUBUS;
15376 std::swap(Op0, Op1);
15378 // Check that the operation in question is available (most are plain SSE2,
15379 // but PCMPGTQ and PCMPEQQ have different requirements).
15380 if (VT == MVT::v2i64) {
15381 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15382 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15384 // First cast everything to the right type.
15385 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15386 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15388 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15389 // bits of the inputs before performing those operations. The lower
15390 // compare is always unsigned.
15393 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15395 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15396 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15397 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15398 Sign, Zero, Sign, Zero);
15400 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15401 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15403 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15404 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15405 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15407 // Create masks for only the low parts/high parts of the 64 bit integers.
15408 static const int MaskHi[] = { 1, 1, 3, 3 };
15409 static const int MaskLo[] = { 0, 0, 2, 2 };
15410 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15411 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15412 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15414 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15415 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15418 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15420 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15423 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15424 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15425 // pcmpeqd + pshufd + pand.
15426 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15428 // First cast everything to the right type.
15429 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15430 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15433 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15435 // Make sure the lower and upper halves are both all-ones.
15436 static const int Mask[] = { 1, 0, 3, 2 };
15437 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15438 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15441 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15443 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15447 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15448 // bits of the inputs before performing those operations.
15450 EVT EltVT = VT.getVectorElementType();
15451 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15452 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15453 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15456 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15458 // If the logical-not of the result is required, perform that now.
15460 Result = DAG.getNOT(dl, Result, VT);
15463 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15466 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15467 getZeroVector(VT, Subtarget, DAG, dl));
15472 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15474 MVT VT = Op.getSimpleValueType();
15476 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15478 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15479 && "SetCC type must be 8-bit or 1-bit integer");
15480 SDValue Op0 = Op.getOperand(0);
15481 SDValue Op1 = Op.getOperand(1);
15483 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15485 // Optimize to BT if possible.
15486 // Lower (X & (1 << N)) == 0 to BT(X, N).
15487 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15488 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15489 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15490 Op1.getOpcode() == ISD::Constant &&
15491 cast<ConstantSDNode>(Op1)->isNullValue() &&
15492 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15493 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15494 if (NewSetCC.getNode()) {
15496 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15501 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15503 if (Op1.getOpcode() == ISD::Constant &&
15504 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15505 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15506 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15508 // If the input is a setcc, then reuse the input setcc or use a new one with
15509 // the inverted condition.
15510 if (Op0.getOpcode() == X86ISD::SETCC) {
15511 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15512 bool Invert = (CC == ISD::SETNE) ^
15513 cast<ConstantSDNode>(Op1)->isNullValue();
15517 CCode = X86::GetOppositeBranchCondition(CCode);
15518 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15519 DAG.getConstant(CCode, MVT::i8),
15520 Op0.getOperand(1));
15522 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15526 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15527 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15528 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15530 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15531 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15534 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15535 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15536 if (X86CC == X86::COND_INVALID)
15539 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15540 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15541 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15542 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15544 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15548 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15549 static bool isX86LogicalCmp(SDValue Op) {
15550 unsigned Opc = Op.getNode()->getOpcode();
15551 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15552 Opc == X86ISD::SAHF)
15554 if (Op.getResNo() == 1 &&
15555 (Opc == X86ISD::ADD ||
15556 Opc == X86ISD::SUB ||
15557 Opc == X86ISD::ADC ||
15558 Opc == X86ISD::SBB ||
15559 Opc == X86ISD::SMUL ||
15560 Opc == X86ISD::UMUL ||
15561 Opc == X86ISD::INC ||
15562 Opc == X86ISD::DEC ||
15563 Opc == X86ISD::OR ||
15564 Opc == X86ISD::XOR ||
15565 Opc == X86ISD::AND))
15568 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15574 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15575 if (V.getOpcode() != ISD::TRUNCATE)
15578 SDValue VOp0 = V.getOperand(0);
15579 unsigned InBits = VOp0.getValueSizeInBits();
15580 unsigned Bits = V.getValueSizeInBits();
15581 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15584 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15585 bool addTest = true;
15586 SDValue Cond = Op.getOperand(0);
15587 SDValue Op1 = Op.getOperand(1);
15588 SDValue Op2 = Op.getOperand(2);
15590 EVT VT = Op1.getValueType();
15593 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15594 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15595 // sequence later on.
15596 if (Cond.getOpcode() == ISD::SETCC &&
15597 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15598 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15599 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15600 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15601 int SSECC = translateX86FSETCC(
15602 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15605 if (Subtarget->hasAVX512()) {
15606 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15607 DAG.getConstant(SSECC, MVT::i8));
15608 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15610 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15611 DAG.getConstant(SSECC, MVT::i8));
15612 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15613 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15614 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15618 if (Cond.getOpcode() == ISD::SETCC) {
15619 SDValue NewCond = LowerSETCC(Cond, DAG);
15620 if (NewCond.getNode())
15624 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15625 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15626 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15627 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15628 if (Cond.getOpcode() == X86ISD::SETCC &&
15629 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15630 isZero(Cond.getOperand(1).getOperand(1))) {
15631 SDValue Cmp = Cond.getOperand(1);
15633 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15635 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15636 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15637 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15639 SDValue CmpOp0 = Cmp.getOperand(0);
15640 // Apply further optimizations for special cases
15641 // (select (x != 0), -1, 0) -> neg & sbb
15642 // (select (x == 0), 0, -1) -> neg & sbb
15643 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15644 if (YC->isNullValue() &&
15645 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15646 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15647 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15648 DAG.getConstant(0, CmpOp0.getValueType()),
15650 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15651 DAG.getConstant(X86::COND_B, MVT::i8),
15652 SDValue(Neg.getNode(), 1));
15656 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15657 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15658 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15660 SDValue Res = // Res = 0 or -1.
15661 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15662 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15664 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15665 Res = DAG.getNOT(DL, Res, Res.getValueType());
15667 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15668 if (!N2C || !N2C->isNullValue())
15669 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15674 // Look past (and (setcc_carry (cmp ...)), 1).
15675 if (Cond.getOpcode() == ISD::AND &&
15676 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15677 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15678 if (C && C->getAPIntValue() == 1)
15679 Cond = Cond.getOperand(0);
15682 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15683 // setting operand in place of the X86ISD::SETCC.
15684 unsigned CondOpcode = Cond.getOpcode();
15685 if (CondOpcode == X86ISD::SETCC ||
15686 CondOpcode == X86ISD::SETCC_CARRY) {
15687 CC = Cond.getOperand(0);
15689 SDValue Cmp = Cond.getOperand(1);
15690 unsigned Opc = Cmp.getOpcode();
15691 MVT VT = Op.getSimpleValueType();
15693 bool IllegalFPCMov = false;
15694 if (VT.isFloatingPoint() && !VT.isVector() &&
15695 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15696 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15698 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15699 Opc == X86ISD::BT) { // FIXME
15703 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15704 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15705 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15706 Cond.getOperand(0).getValueType() != MVT::i8)) {
15707 SDValue LHS = Cond.getOperand(0);
15708 SDValue RHS = Cond.getOperand(1);
15709 unsigned X86Opcode;
15712 switch (CondOpcode) {
15713 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15714 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15715 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15716 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15717 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15718 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15719 default: llvm_unreachable("unexpected overflowing operator");
15721 if (CondOpcode == ISD::UMULO)
15722 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15725 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15727 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15729 if (CondOpcode == ISD::UMULO)
15730 Cond = X86Op.getValue(2);
15732 Cond = X86Op.getValue(1);
15734 CC = DAG.getConstant(X86Cond, MVT::i8);
15739 // Look pass the truncate if the high bits are known zero.
15740 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15741 Cond = Cond.getOperand(0);
15743 // We know the result of AND is compared against zero. Try to match
15745 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15746 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15747 if (NewSetCC.getNode()) {
15748 CC = NewSetCC.getOperand(0);
15749 Cond = NewSetCC.getOperand(1);
15756 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15757 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15760 // a < b ? -1 : 0 -> RES = ~setcc_carry
15761 // a < b ? 0 : -1 -> RES = setcc_carry
15762 // a >= b ? -1 : 0 -> RES = setcc_carry
15763 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15764 if (Cond.getOpcode() == X86ISD::SUB) {
15765 Cond = ConvertCmpIfNecessary(Cond, DAG);
15766 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15768 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15769 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15770 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15771 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15772 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15773 return DAG.getNOT(DL, Res, Res.getValueType());
15778 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15779 // widen the cmov and push the truncate through. This avoids introducing a new
15780 // branch during isel and doesn't add any extensions.
15781 if (Op.getValueType() == MVT::i8 &&
15782 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15783 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15784 if (T1.getValueType() == T2.getValueType() &&
15785 // Blacklist CopyFromReg to avoid partial register stalls.
15786 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15787 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15788 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15789 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15793 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15794 // condition is true.
15795 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15796 SDValue Ops[] = { Op2, Op1, CC, Cond };
15797 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15800 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15801 SelectionDAG &DAG) {
15802 MVT VT = Op->getSimpleValueType(0);
15803 SDValue In = Op->getOperand(0);
15804 MVT InVT = In.getSimpleValueType();
15805 MVT VTElt = VT.getVectorElementType();
15806 MVT InVTElt = InVT.getVectorElementType();
15810 if ((InVTElt == MVT::i1) &&
15811 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15812 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15814 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15815 VTElt.getSizeInBits() <= 16)) ||
15817 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15818 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15820 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15821 VTElt.getSizeInBits() >= 32))))
15822 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15824 unsigned int NumElts = VT.getVectorNumElements();
15826 if (NumElts != 8 && NumElts != 16)
15829 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15830 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15831 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15832 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15835 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15836 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15838 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15839 Constant *C = ConstantInt::get(*DAG.getContext(),
15840 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15842 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15843 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15844 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15845 MachinePointerInfo::getConstantPool(),
15846 false, false, false, Alignment);
15847 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15848 if (VT.is512BitVector())
15850 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15853 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15854 SelectionDAG &DAG) {
15855 MVT VT = Op->getSimpleValueType(0);
15856 SDValue In = Op->getOperand(0);
15857 MVT InVT = In.getSimpleValueType();
15860 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15861 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15863 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15864 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15865 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15868 if (Subtarget->hasInt256())
15869 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15871 // Optimize vectors in AVX mode
15872 // Sign extend v8i16 to v8i32 and
15875 // Divide input vector into two parts
15876 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15877 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15878 // concat the vectors to original VT
15880 unsigned NumElems = InVT.getVectorNumElements();
15881 SDValue Undef = DAG.getUNDEF(InVT);
15883 SmallVector<int,8> ShufMask1(NumElems, -1);
15884 for (unsigned i = 0; i != NumElems/2; ++i)
15887 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15889 SmallVector<int,8> ShufMask2(NumElems, -1);
15890 for (unsigned i = 0; i != NumElems/2; ++i)
15891 ShufMask2[i] = i + NumElems/2;
15893 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15895 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15896 VT.getVectorNumElements()/2);
15898 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15899 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15901 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15904 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15905 // may emit an illegal shuffle but the expansion is still better than scalar
15906 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15907 // we'll emit a shuffle and a arithmetic shift.
15908 // TODO: It is possible to support ZExt by zeroing the undef values during
15909 // the shuffle phase or after the shuffle.
15910 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15911 SelectionDAG &DAG) {
15912 MVT RegVT = Op.getSimpleValueType();
15913 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15914 assert(RegVT.isInteger() &&
15915 "We only custom lower integer vector sext loads.");
15917 // Nothing useful we can do without SSE2 shuffles.
15918 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15920 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15922 EVT MemVT = Ld->getMemoryVT();
15923 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15924 unsigned RegSz = RegVT.getSizeInBits();
15926 ISD::LoadExtType Ext = Ld->getExtensionType();
15928 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15929 && "Only anyext and sext are currently implemented.");
15930 assert(MemVT != RegVT && "Cannot extend to the same type");
15931 assert(MemVT.isVector() && "Must load a vector from memory");
15933 unsigned NumElems = RegVT.getVectorNumElements();
15934 unsigned MemSz = MemVT.getSizeInBits();
15935 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15937 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15938 // The only way in which we have a legal 256-bit vector result but not the
15939 // integer 256-bit operations needed to directly lower a sextload is if we
15940 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15941 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15942 // correctly legalized. We do this late to allow the canonical form of
15943 // sextload to persist throughout the rest of the DAG combiner -- it wants
15944 // to fold together any extensions it can, and so will fuse a sign_extend
15945 // of an sextload into a sextload targeting a wider value.
15947 if (MemSz == 128) {
15948 // Just switch this to a normal load.
15949 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15950 "it must be a legal 128-bit vector "
15952 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15953 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15954 Ld->isInvariant(), Ld->getAlignment());
15956 assert(MemSz < 128 &&
15957 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15958 // Do an sext load to a 128-bit vector type. We want to use the same
15959 // number of elements, but elements half as wide. This will end up being
15960 // recursively lowered by this routine, but will succeed as we definitely
15961 // have all the necessary features if we're using AVX1.
15963 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15964 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15966 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15967 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15968 Ld->isNonTemporal(), Ld->isInvariant(),
15969 Ld->getAlignment());
15972 // Replace chain users with the new chain.
15973 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15974 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15976 // Finally, do a normal sign-extend to the desired register.
15977 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15980 // All sizes must be a power of two.
15981 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15982 "Non-power-of-two elements are not custom lowered!");
15984 // Attempt to load the original value using scalar loads.
15985 // Find the largest scalar type that divides the total loaded size.
15986 MVT SclrLoadTy = MVT::i8;
15987 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15988 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15989 MVT Tp = (MVT::SimpleValueType)tp;
15990 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15995 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15996 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15998 SclrLoadTy = MVT::f64;
16000 // Calculate the number of scalar loads that we need to perform
16001 // in order to load our vector from memory.
16002 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16004 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
16005 "Can only lower sext loads with a single scalar load!");
16007 unsigned loadRegZize = RegSz;
16008 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16011 // Represent our vector as a sequence of elements which are the
16012 // largest scalar that we can load.
16013 EVT LoadUnitVecVT = EVT::getVectorVT(
16014 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
16016 // Represent the data using the same element type that is stored in
16017 // memory. In practice, we ''widen'' MemVT.
16019 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16020 loadRegZize / MemVT.getScalarType().getSizeInBits());
16022 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16023 "Invalid vector type");
16025 // We can't shuffle using an illegal type.
16026 assert(TLI.isTypeLegal(WideVecVT) &&
16027 "We only lower types that form legal widened vector types");
16029 SmallVector<SDValue, 8> Chains;
16030 SDValue Ptr = Ld->getBasePtr();
16031 SDValue Increment =
16032 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16033 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16035 for (unsigned i = 0; i < NumLoads; ++i) {
16036 // Perform a single load.
16037 SDValue ScalarLoad =
16038 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16039 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16040 Ld->getAlignment());
16041 Chains.push_back(ScalarLoad.getValue(1));
16042 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16043 // another round of DAGCombining.
16045 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16047 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16048 ScalarLoad, DAG.getIntPtrConstant(i));
16050 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16053 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16055 // Bitcast the loaded value to a vector of the original element type, in
16056 // the size of the target vector type.
16057 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16058 unsigned SizeRatio = RegSz / MemSz;
16060 if (Ext == ISD::SEXTLOAD) {
16061 // If we have SSE4.1, we can directly emit a VSEXT node.
16062 if (Subtarget->hasSSE41()) {
16063 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16064 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16068 // Otherwise we'll shuffle the small elements in the high bits of the
16069 // larger type and perform an arithmetic shift. If the shift is not legal
16070 // it's better to scalarize.
16071 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16072 "We can't implement a sext load without an arithmetic right shift!");
16074 // Redistribute the loaded elements into the different locations.
16075 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16076 for (unsigned i = 0; i != NumElems; ++i)
16077 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16079 SDValue Shuff = DAG.getVectorShuffle(
16080 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16082 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16084 // Build the arithmetic shift.
16085 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16086 MemVT.getVectorElementType().getSizeInBits();
16088 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16090 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16094 // Redistribute the loaded elements into the different locations.
16095 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16096 for (unsigned i = 0; i != NumElems; ++i)
16097 ShuffleVec[i * SizeRatio] = i;
16099 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16100 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16102 // Bitcast to the requested type.
16103 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16104 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16108 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16109 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16110 // from the AND / OR.
16111 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16112 Opc = Op.getOpcode();
16113 if (Opc != ISD::OR && Opc != ISD::AND)
16115 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16116 Op.getOperand(0).hasOneUse() &&
16117 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16118 Op.getOperand(1).hasOneUse());
16121 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16122 // 1 and that the SETCC node has a single use.
16123 static bool isXor1OfSetCC(SDValue Op) {
16124 if (Op.getOpcode() != ISD::XOR)
16126 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16127 if (N1C && N1C->getAPIntValue() == 1) {
16128 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16129 Op.getOperand(0).hasOneUse();
16134 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16135 bool addTest = true;
16136 SDValue Chain = Op.getOperand(0);
16137 SDValue Cond = Op.getOperand(1);
16138 SDValue Dest = Op.getOperand(2);
16141 bool Inverted = false;
16143 if (Cond.getOpcode() == ISD::SETCC) {
16144 // Check for setcc([su]{add,sub,mul}o == 0).
16145 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16146 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16147 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16148 Cond.getOperand(0).getResNo() == 1 &&
16149 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16150 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16151 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16152 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16153 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16154 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16156 Cond = Cond.getOperand(0);
16158 SDValue NewCond = LowerSETCC(Cond, DAG);
16159 if (NewCond.getNode())
16164 // FIXME: LowerXALUO doesn't handle these!!
16165 else if (Cond.getOpcode() == X86ISD::ADD ||
16166 Cond.getOpcode() == X86ISD::SUB ||
16167 Cond.getOpcode() == X86ISD::SMUL ||
16168 Cond.getOpcode() == X86ISD::UMUL)
16169 Cond = LowerXALUO(Cond, DAG);
16172 // Look pass (and (setcc_carry (cmp ...)), 1).
16173 if (Cond.getOpcode() == ISD::AND &&
16174 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16175 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16176 if (C && C->getAPIntValue() == 1)
16177 Cond = Cond.getOperand(0);
16180 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16181 // setting operand in place of the X86ISD::SETCC.
16182 unsigned CondOpcode = Cond.getOpcode();
16183 if (CondOpcode == X86ISD::SETCC ||
16184 CondOpcode == X86ISD::SETCC_CARRY) {
16185 CC = Cond.getOperand(0);
16187 SDValue Cmp = Cond.getOperand(1);
16188 unsigned Opc = Cmp.getOpcode();
16189 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16190 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16194 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16198 // These can only come from an arithmetic instruction with overflow,
16199 // e.g. SADDO, UADDO.
16200 Cond = Cond.getNode()->getOperand(1);
16206 CondOpcode = Cond.getOpcode();
16207 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16208 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16209 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16210 Cond.getOperand(0).getValueType() != MVT::i8)) {
16211 SDValue LHS = Cond.getOperand(0);
16212 SDValue RHS = Cond.getOperand(1);
16213 unsigned X86Opcode;
16216 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16217 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16219 switch (CondOpcode) {
16220 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16222 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16224 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16227 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16228 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16230 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16232 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16235 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16236 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16237 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16238 default: llvm_unreachable("unexpected overflowing operator");
16241 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16242 if (CondOpcode == ISD::UMULO)
16243 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16246 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16248 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16250 if (CondOpcode == ISD::UMULO)
16251 Cond = X86Op.getValue(2);
16253 Cond = X86Op.getValue(1);
16255 CC = DAG.getConstant(X86Cond, MVT::i8);
16259 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16260 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16261 if (CondOpc == ISD::OR) {
16262 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16263 // two branches instead of an explicit OR instruction with a
16265 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16266 isX86LogicalCmp(Cmp)) {
16267 CC = Cond.getOperand(0).getOperand(0);
16268 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16269 Chain, Dest, CC, Cmp);
16270 CC = Cond.getOperand(1).getOperand(0);
16274 } else { // ISD::AND
16275 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16276 // two branches instead of an explicit AND instruction with a
16277 // separate test. However, we only do this if this block doesn't
16278 // have a fall-through edge, because this requires an explicit
16279 // jmp when the condition is false.
16280 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16281 isX86LogicalCmp(Cmp) &&
16282 Op.getNode()->hasOneUse()) {
16283 X86::CondCode CCode =
16284 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16285 CCode = X86::GetOppositeBranchCondition(CCode);
16286 CC = DAG.getConstant(CCode, MVT::i8);
16287 SDNode *User = *Op.getNode()->use_begin();
16288 // Look for an unconditional branch following this conditional branch.
16289 // We need this because we need to reverse the successors in order
16290 // to implement FCMP_OEQ.
16291 if (User->getOpcode() == ISD::BR) {
16292 SDValue FalseBB = User->getOperand(1);
16294 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16295 assert(NewBR == User);
16299 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16300 Chain, Dest, CC, Cmp);
16301 X86::CondCode CCode =
16302 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16303 CCode = X86::GetOppositeBranchCondition(CCode);
16304 CC = DAG.getConstant(CCode, MVT::i8);
16310 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16311 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16312 // It should be transformed during dag combiner except when the condition
16313 // is set by a arithmetics with overflow node.
16314 X86::CondCode CCode =
16315 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16316 CCode = X86::GetOppositeBranchCondition(CCode);
16317 CC = DAG.getConstant(CCode, MVT::i8);
16318 Cond = Cond.getOperand(0).getOperand(1);
16320 } else if (Cond.getOpcode() == ISD::SETCC &&
16321 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16322 // For FCMP_OEQ, we can emit
16323 // two branches instead of an explicit AND instruction with a
16324 // separate test. However, we only do this if this block doesn't
16325 // have a fall-through edge, because this requires an explicit
16326 // jmp when the condition is false.
16327 if (Op.getNode()->hasOneUse()) {
16328 SDNode *User = *Op.getNode()->use_begin();
16329 // Look for an unconditional branch following this conditional branch.
16330 // We need this because we need to reverse the successors in order
16331 // to implement FCMP_OEQ.
16332 if (User->getOpcode() == ISD::BR) {
16333 SDValue FalseBB = User->getOperand(1);
16335 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16336 assert(NewBR == User);
16340 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16341 Cond.getOperand(0), Cond.getOperand(1));
16342 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16343 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16344 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16345 Chain, Dest, CC, Cmp);
16346 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16351 } else if (Cond.getOpcode() == ISD::SETCC &&
16352 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16353 // For FCMP_UNE, we can emit
16354 // two branches instead of an explicit AND instruction with a
16355 // separate test. However, we only do this if this block doesn't
16356 // have a fall-through edge, because this requires an explicit
16357 // jmp when the condition is false.
16358 if (Op.getNode()->hasOneUse()) {
16359 SDNode *User = *Op.getNode()->use_begin();
16360 // Look for an unconditional branch following this conditional branch.
16361 // We need this because we need to reverse the successors in order
16362 // to implement FCMP_UNE.
16363 if (User->getOpcode() == ISD::BR) {
16364 SDValue FalseBB = User->getOperand(1);
16366 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16367 assert(NewBR == User);
16370 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16371 Cond.getOperand(0), Cond.getOperand(1));
16372 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16373 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16374 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16375 Chain, Dest, CC, Cmp);
16376 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16386 // Look pass the truncate if the high bits are known zero.
16387 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16388 Cond = Cond.getOperand(0);
16390 // We know the result of AND is compared against zero. Try to match
16392 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16393 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16394 if (NewSetCC.getNode()) {
16395 CC = NewSetCC.getOperand(0);
16396 Cond = NewSetCC.getOperand(1);
16403 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16404 CC = DAG.getConstant(X86Cond, MVT::i8);
16405 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16407 Cond = ConvertCmpIfNecessary(Cond, DAG);
16408 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16409 Chain, Dest, CC, Cond);
16412 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16413 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16414 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16415 // that the guard pages used by the OS virtual memory manager are allocated in
16416 // correct sequence.
16418 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16419 SelectionDAG &DAG) const {
16420 MachineFunction &MF = DAG.getMachineFunction();
16421 bool SplitStack = MF.shouldSplitStack();
16422 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16427 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16428 SDNode* Node = Op.getNode();
16430 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16431 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16432 " not tell us which reg is the stack pointer!");
16433 EVT VT = Node->getValueType(0);
16434 SDValue Tmp1 = SDValue(Node, 0);
16435 SDValue Tmp2 = SDValue(Node, 1);
16436 SDValue Tmp3 = Node->getOperand(2);
16437 SDValue Chain = Tmp1.getOperand(0);
16439 // Chain the dynamic stack allocation so that it doesn't modify the stack
16440 // pointer when other instructions are using the stack.
16441 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16444 SDValue Size = Tmp2.getOperand(1);
16445 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16446 Chain = SP.getValue(1);
16447 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16448 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16449 unsigned StackAlign = TFI.getStackAlignment();
16450 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16451 if (Align > StackAlign)
16452 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16453 DAG.getConstant(-(uint64_t)Align, VT));
16454 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16456 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16457 DAG.getIntPtrConstant(0, true), SDValue(),
16460 SDValue Ops[2] = { Tmp1, Tmp2 };
16461 return DAG.getMergeValues(Ops, dl);
16465 SDValue Chain = Op.getOperand(0);
16466 SDValue Size = Op.getOperand(1);
16467 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16468 EVT VT = Op.getNode()->getValueType(0);
16470 bool Is64Bit = Subtarget->is64Bit();
16471 EVT SPTy = getPointerTy();
16474 MachineRegisterInfo &MRI = MF.getRegInfo();
16477 // The 64 bit implementation of segmented stacks needs to clobber both r10
16478 // r11. This makes it impossible to use it along with nested parameters.
16479 const Function *F = MF.getFunction();
16481 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16483 if (I->hasNestAttr())
16484 report_fatal_error("Cannot use segmented stacks with functions that "
16485 "have nested arguments.");
16488 const TargetRegisterClass *AddrRegClass =
16489 getRegClassFor(getPointerTy());
16490 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16491 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16492 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16493 DAG.getRegister(Vreg, SPTy));
16494 SDValue Ops1[2] = { Value, Chain };
16495 return DAG.getMergeValues(Ops1, dl);
16498 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16500 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16501 Flag = Chain.getValue(1);
16502 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16504 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16506 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16507 DAG.getSubtarget().getRegisterInfo());
16508 unsigned SPReg = RegInfo->getStackRegister();
16509 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16510 Chain = SP.getValue(1);
16513 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16514 DAG.getConstant(-(uint64_t)Align, VT));
16515 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16518 SDValue Ops1[2] = { SP, Chain };
16519 return DAG.getMergeValues(Ops1, dl);
16523 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16524 MachineFunction &MF = DAG.getMachineFunction();
16525 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16527 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16530 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16531 // vastart just stores the address of the VarArgsFrameIndex slot into the
16532 // memory location argument.
16533 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16535 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16536 MachinePointerInfo(SV), false, false, 0);
16540 // gp_offset (0 - 6 * 8)
16541 // fp_offset (48 - 48 + 8 * 16)
16542 // overflow_arg_area (point to parameters coming in memory).
16544 SmallVector<SDValue, 8> MemOps;
16545 SDValue FIN = Op.getOperand(1);
16547 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16548 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16550 FIN, MachinePointerInfo(SV), false, false, 0);
16551 MemOps.push_back(Store);
16554 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16555 FIN, DAG.getIntPtrConstant(4));
16556 Store = DAG.getStore(Op.getOperand(0), DL,
16557 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16559 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16560 MemOps.push_back(Store);
16562 // Store ptr to overflow_arg_area
16563 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16564 FIN, DAG.getIntPtrConstant(4));
16565 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16567 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16568 MachinePointerInfo(SV, 8),
16570 MemOps.push_back(Store);
16572 // Store ptr to reg_save_area.
16573 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16574 FIN, DAG.getIntPtrConstant(8));
16575 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16577 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16578 MachinePointerInfo(SV, 16), false, false, 0);
16579 MemOps.push_back(Store);
16580 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16583 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16584 assert(Subtarget->is64Bit() &&
16585 "LowerVAARG only handles 64-bit va_arg!");
16586 assert((Subtarget->isTargetLinux() ||
16587 Subtarget->isTargetDarwin()) &&
16588 "Unhandled target in LowerVAARG");
16589 assert(Op.getNode()->getNumOperands() == 4);
16590 SDValue Chain = Op.getOperand(0);
16591 SDValue SrcPtr = Op.getOperand(1);
16592 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16593 unsigned Align = Op.getConstantOperandVal(3);
16596 EVT ArgVT = Op.getNode()->getValueType(0);
16597 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16598 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16601 // Decide which area this value should be read from.
16602 // TODO: Implement the AMD64 ABI in its entirety. This simple
16603 // selection mechanism works only for the basic types.
16604 if (ArgVT == MVT::f80) {
16605 llvm_unreachable("va_arg for f80 not yet implemented");
16606 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16607 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16608 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16609 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16611 llvm_unreachable("Unhandled argument type in LowerVAARG");
16614 if (ArgMode == 2) {
16615 // Sanity Check: Make sure using fp_offset makes sense.
16616 assert(!DAG.getTarget().Options.UseSoftFloat &&
16617 !(DAG.getMachineFunction()
16618 .getFunction()->getAttributes()
16619 .hasAttribute(AttributeSet::FunctionIndex,
16620 Attribute::NoImplicitFloat)) &&
16621 Subtarget->hasSSE1());
16624 // Insert VAARG_64 node into the DAG
16625 // VAARG_64 returns two values: Variable Argument Address, Chain
16626 SmallVector<SDValue, 11> InstOps;
16627 InstOps.push_back(Chain);
16628 InstOps.push_back(SrcPtr);
16629 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16630 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16631 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16632 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16633 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16634 VTs, InstOps, MVT::i64,
16635 MachinePointerInfo(SV),
16637 /*Volatile=*/false,
16639 /*WriteMem=*/true);
16640 Chain = VAARG.getValue(1);
16642 // Load the next argument and return it
16643 return DAG.getLoad(ArgVT, dl,
16646 MachinePointerInfo(),
16647 false, false, false, 0);
16650 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16651 SelectionDAG &DAG) {
16652 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16653 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16654 SDValue Chain = Op.getOperand(0);
16655 SDValue DstPtr = Op.getOperand(1);
16656 SDValue SrcPtr = Op.getOperand(2);
16657 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16658 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16661 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16662 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16664 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16667 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16668 // amount is a constant. Takes immediate version of shift as input.
16669 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16670 SDValue SrcOp, uint64_t ShiftAmt,
16671 SelectionDAG &DAG) {
16672 MVT ElementType = VT.getVectorElementType();
16674 // Fold this packed shift into its first operand if ShiftAmt is 0.
16678 // Check for ShiftAmt >= element width
16679 if (ShiftAmt >= ElementType.getSizeInBits()) {
16680 if (Opc == X86ISD::VSRAI)
16681 ShiftAmt = ElementType.getSizeInBits() - 1;
16683 return DAG.getConstant(0, VT);
16686 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16687 && "Unknown target vector shift-by-constant node");
16689 // Fold this packed vector shift into a build vector if SrcOp is a
16690 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16691 if (VT == SrcOp.getSimpleValueType() &&
16692 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16693 SmallVector<SDValue, 8> Elts;
16694 unsigned NumElts = SrcOp->getNumOperands();
16695 ConstantSDNode *ND;
16698 default: llvm_unreachable(nullptr);
16699 case X86ISD::VSHLI:
16700 for (unsigned i=0; i!=NumElts; ++i) {
16701 SDValue CurrentOp = SrcOp->getOperand(i);
16702 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16703 Elts.push_back(CurrentOp);
16706 ND = cast<ConstantSDNode>(CurrentOp);
16707 const APInt &C = ND->getAPIntValue();
16708 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16711 case X86ISD::VSRLI:
16712 for (unsigned i=0; i!=NumElts; ++i) {
16713 SDValue CurrentOp = SrcOp->getOperand(i);
16714 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16715 Elts.push_back(CurrentOp);
16718 ND = cast<ConstantSDNode>(CurrentOp);
16719 const APInt &C = ND->getAPIntValue();
16720 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16723 case X86ISD::VSRAI:
16724 for (unsigned i=0; i!=NumElts; ++i) {
16725 SDValue CurrentOp = SrcOp->getOperand(i);
16726 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16727 Elts.push_back(CurrentOp);
16730 ND = cast<ConstantSDNode>(CurrentOp);
16731 const APInt &C = ND->getAPIntValue();
16732 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16737 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16740 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16743 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16744 // may or may not be a constant. Takes immediate version of shift as input.
16745 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16746 SDValue SrcOp, SDValue ShAmt,
16747 SelectionDAG &DAG) {
16748 MVT SVT = ShAmt.getSimpleValueType();
16749 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16751 // Catch shift-by-constant.
16752 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16753 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16754 CShAmt->getZExtValue(), DAG);
16756 // Change opcode to non-immediate version
16758 default: llvm_unreachable("Unknown target vector shift node");
16759 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16760 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16761 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16764 const X86Subtarget &Subtarget =
16765 DAG.getTarget().getSubtarget<X86Subtarget>();
16766 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16767 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16768 // Let the shuffle legalizer expand this shift amount node.
16769 SDValue Op0 = ShAmt.getOperand(0);
16770 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16771 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16773 // Need to build a vector containing shift amount.
16774 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16775 SmallVector<SDValue, 4> ShOps;
16776 ShOps.push_back(ShAmt);
16777 if (SVT == MVT::i32) {
16778 ShOps.push_back(DAG.getConstant(0, SVT));
16779 ShOps.push_back(DAG.getUNDEF(SVT));
16781 ShOps.push_back(DAG.getUNDEF(SVT));
16783 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16784 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16787 // The return type has to be a 128-bit type with the same element
16788 // type as the input type.
16789 MVT EltVT = VT.getVectorElementType();
16790 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16792 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16793 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16796 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16797 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16798 /// necessary casting for \p Mask when lowering masking intrinsics.
16799 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16800 SDValue PreservedSrc,
16801 const X86Subtarget *Subtarget,
16802 SelectionDAG &DAG) {
16803 EVT VT = Op.getValueType();
16804 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16805 MVT::i1, VT.getVectorNumElements());
16806 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16807 Mask.getValueType().getSizeInBits());
16810 assert(MaskVT.isSimple() && "invalid mask type");
16812 if (isAllOnes(Mask))
16815 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16816 // are extracted by EXTRACT_SUBVECTOR.
16817 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16818 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16819 DAG.getIntPtrConstant(0));
16821 switch (Op.getOpcode()) {
16823 case X86ISD::PCMPEQM:
16824 case X86ISD::PCMPGTM:
16826 case X86ISD::CMPMU:
16827 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16829 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16830 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16831 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16834 /// \brief Creates an SDNode for a predicated scalar operation.
16835 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16836 /// The mask is comming as MVT::i8 and it should be truncated
16837 /// to MVT::i1 while lowering masking intrinsics.
16838 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16839 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16840 /// a scalar instruction.
16841 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16842 SDValue PreservedSrc,
16843 const X86Subtarget *Subtarget,
16844 SelectionDAG &DAG) {
16845 if (isAllOnes(Mask))
16848 EVT VT = Op.getValueType();
16850 // The mask should be of type MVT::i1
16851 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16853 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16854 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16855 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16858 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16860 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16861 case Intrinsic::x86_fma_vfmadd_ps:
16862 case Intrinsic::x86_fma_vfmadd_pd:
16863 case Intrinsic::x86_fma_vfmadd_ps_256:
16864 case Intrinsic::x86_fma_vfmadd_pd_256:
16865 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16866 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16867 return X86ISD::FMADD;
16868 case Intrinsic::x86_fma_vfmsub_ps:
16869 case Intrinsic::x86_fma_vfmsub_pd:
16870 case Intrinsic::x86_fma_vfmsub_ps_256:
16871 case Intrinsic::x86_fma_vfmsub_pd_256:
16872 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16873 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16874 return X86ISD::FMSUB;
16875 case Intrinsic::x86_fma_vfnmadd_ps:
16876 case Intrinsic::x86_fma_vfnmadd_pd:
16877 case Intrinsic::x86_fma_vfnmadd_ps_256:
16878 case Intrinsic::x86_fma_vfnmadd_pd_256:
16879 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16880 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16881 return X86ISD::FNMADD;
16882 case Intrinsic::x86_fma_vfnmsub_ps:
16883 case Intrinsic::x86_fma_vfnmsub_pd:
16884 case Intrinsic::x86_fma_vfnmsub_ps_256:
16885 case Intrinsic::x86_fma_vfnmsub_pd_256:
16886 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16887 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16888 return X86ISD::FNMSUB;
16889 case Intrinsic::x86_fma_vfmaddsub_ps:
16890 case Intrinsic::x86_fma_vfmaddsub_pd:
16891 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16892 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16893 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16894 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16895 return X86ISD::FMADDSUB;
16896 case Intrinsic::x86_fma_vfmsubadd_ps:
16897 case Intrinsic::x86_fma_vfmsubadd_pd:
16898 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16899 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16900 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16901 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16902 return X86ISD::FMSUBADD;
16906 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16907 SelectionDAG &DAG) {
16909 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16910 EVT VT = Op.getValueType();
16911 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16913 switch(IntrData->Type) {
16914 case INTR_TYPE_1OP:
16915 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16916 case INTR_TYPE_2OP:
16917 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16919 case INTR_TYPE_3OP:
16920 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16921 Op.getOperand(2), Op.getOperand(3));
16922 case INTR_TYPE_1OP_MASK_RM: {
16923 SDValue Src = Op.getOperand(1);
16924 SDValue Src0 = Op.getOperand(2);
16925 SDValue Mask = Op.getOperand(3);
16926 SDValue RoundingMode = Op.getOperand(4);
16927 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16929 Mask, Src0, Subtarget, DAG);
16931 case INTR_TYPE_SCALAR_MASK_RM: {
16932 SDValue Src1 = Op.getOperand(1);
16933 SDValue Src2 = Op.getOperand(2);
16934 SDValue Src0 = Op.getOperand(3);
16935 SDValue Mask = Op.getOperand(4);
16936 SDValue RoundingMode = Op.getOperand(5);
16937 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16939 Mask, Src0, Subtarget, DAG);
16941 case INTR_TYPE_2OP_MASK: {
16942 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16944 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16947 case CMP_MASK_CC: {
16948 // Comparison intrinsics with masks.
16949 // Example of transformation:
16950 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16951 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16953 // (v8i1 (insert_subvector undef,
16954 // (v2i1 (and (PCMPEQM %a, %b),
16955 // (extract_subvector
16956 // (v8i1 (bitcast %mask)), 0))), 0))))
16957 EVT VT = Op.getOperand(1).getValueType();
16958 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16959 VT.getVectorNumElements());
16960 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16961 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16962 Mask.getValueType().getSizeInBits());
16964 if (IntrData->Type == CMP_MASK_CC) {
16965 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16966 Op.getOperand(2), Op.getOperand(3));
16968 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16969 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16972 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16973 DAG.getTargetConstant(0, MaskVT),
16975 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16976 DAG.getUNDEF(BitcastVT), CmpMask,
16977 DAG.getIntPtrConstant(0));
16978 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16980 case COMI: { // Comparison intrinsics
16981 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16982 SDValue LHS = Op.getOperand(1);
16983 SDValue RHS = Op.getOperand(2);
16984 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16985 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16986 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16987 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16988 DAG.getConstant(X86CC, MVT::i8), Cond);
16989 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16992 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16993 Op.getOperand(1), Op.getOperand(2), DAG);
16995 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16996 Op.getSimpleValueType(),
16998 Op.getOperand(2), DAG),
16999 Op.getOperand(4), Op.getOperand(3), Subtarget,
17001 case COMPRESS_EXPAND_IN_REG: {
17002 SDValue Mask = Op.getOperand(3);
17003 SDValue DataToCompress = Op.getOperand(1);
17004 SDValue PassThru = Op.getOperand(2);
17005 if (isAllOnes(Mask)) // return data as is
17006 return Op.getOperand(1);
17007 EVT VT = Op.getValueType();
17008 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17009 VT.getVectorNumElements());
17010 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17011 Mask.getValueType().getSizeInBits());
17013 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17014 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17015 DAG.getIntPtrConstant(0));
17017 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
17021 SDValue Mask = Op.getOperand(3);
17022 EVT VT = Op.getValueType();
17023 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17024 VT.getVectorNumElements());
17025 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17026 Mask.getValueType().getSizeInBits());
17028 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17029 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17030 DAG.getIntPtrConstant(0));
17031 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
17036 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
17037 dl, Op.getValueType(),
17041 Op.getOperand(4), Op.getOperand(1),
17050 default: return SDValue(); // Don't custom lower most intrinsics.
17052 case Intrinsic::x86_avx512_mask_valign_q_512:
17053 case Intrinsic::x86_avx512_mask_valign_d_512:
17054 // Vector source operands are swapped.
17055 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17056 Op.getValueType(), Op.getOperand(2),
17059 Op.getOperand(5), Op.getOperand(4),
17062 // ptest and testp intrinsics. The intrinsic these come from are designed to
17063 // return an integer value, not just an instruction so lower it to the ptest
17064 // or testp pattern and a setcc for the result.
17065 case Intrinsic::x86_sse41_ptestz:
17066 case Intrinsic::x86_sse41_ptestc:
17067 case Intrinsic::x86_sse41_ptestnzc:
17068 case Intrinsic::x86_avx_ptestz_256:
17069 case Intrinsic::x86_avx_ptestc_256:
17070 case Intrinsic::x86_avx_ptestnzc_256:
17071 case Intrinsic::x86_avx_vtestz_ps:
17072 case Intrinsic::x86_avx_vtestc_ps:
17073 case Intrinsic::x86_avx_vtestnzc_ps:
17074 case Intrinsic::x86_avx_vtestz_pd:
17075 case Intrinsic::x86_avx_vtestc_pd:
17076 case Intrinsic::x86_avx_vtestnzc_pd:
17077 case Intrinsic::x86_avx_vtestz_ps_256:
17078 case Intrinsic::x86_avx_vtestc_ps_256:
17079 case Intrinsic::x86_avx_vtestnzc_ps_256:
17080 case Intrinsic::x86_avx_vtestz_pd_256:
17081 case Intrinsic::x86_avx_vtestc_pd_256:
17082 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17083 bool IsTestPacked = false;
17086 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17087 case Intrinsic::x86_avx_vtestz_ps:
17088 case Intrinsic::x86_avx_vtestz_pd:
17089 case Intrinsic::x86_avx_vtestz_ps_256:
17090 case Intrinsic::x86_avx_vtestz_pd_256:
17091 IsTestPacked = true; // Fallthrough
17092 case Intrinsic::x86_sse41_ptestz:
17093 case Intrinsic::x86_avx_ptestz_256:
17095 X86CC = X86::COND_E;
17097 case Intrinsic::x86_avx_vtestc_ps:
17098 case Intrinsic::x86_avx_vtestc_pd:
17099 case Intrinsic::x86_avx_vtestc_ps_256:
17100 case Intrinsic::x86_avx_vtestc_pd_256:
17101 IsTestPacked = true; // Fallthrough
17102 case Intrinsic::x86_sse41_ptestc:
17103 case Intrinsic::x86_avx_ptestc_256:
17105 X86CC = X86::COND_B;
17107 case Intrinsic::x86_avx_vtestnzc_ps:
17108 case Intrinsic::x86_avx_vtestnzc_pd:
17109 case Intrinsic::x86_avx_vtestnzc_ps_256:
17110 case Intrinsic::x86_avx_vtestnzc_pd_256:
17111 IsTestPacked = true; // Fallthrough
17112 case Intrinsic::x86_sse41_ptestnzc:
17113 case Intrinsic::x86_avx_ptestnzc_256:
17115 X86CC = X86::COND_A;
17119 SDValue LHS = Op.getOperand(1);
17120 SDValue RHS = Op.getOperand(2);
17121 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17122 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17123 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17124 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17125 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17127 case Intrinsic::x86_avx512_kortestz_w:
17128 case Intrinsic::x86_avx512_kortestc_w: {
17129 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17130 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17131 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17132 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17133 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17134 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17135 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17138 case Intrinsic::x86_sse42_pcmpistria128:
17139 case Intrinsic::x86_sse42_pcmpestria128:
17140 case Intrinsic::x86_sse42_pcmpistric128:
17141 case Intrinsic::x86_sse42_pcmpestric128:
17142 case Intrinsic::x86_sse42_pcmpistrio128:
17143 case Intrinsic::x86_sse42_pcmpestrio128:
17144 case Intrinsic::x86_sse42_pcmpistris128:
17145 case Intrinsic::x86_sse42_pcmpestris128:
17146 case Intrinsic::x86_sse42_pcmpistriz128:
17147 case Intrinsic::x86_sse42_pcmpestriz128: {
17151 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17152 case Intrinsic::x86_sse42_pcmpistria128:
17153 Opcode = X86ISD::PCMPISTRI;
17154 X86CC = X86::COND_A;
17156 case Intrinsic::x86_sse42_pcmpestria128:
17157 Opcode = X86ISD::PCMPESTRI;
17158 X86CC = X86::COND_A;
17160 case Intrinsic::x86_sse42_pcmpistric128:
17161 Opcode = X86ISD::PCMPISTRI;
17162 X86CC = X86::COND_B;
17164 case Intrinsic::x86_sse42_pcmpestric128:
17165 Opcode = X86ISD::PCMPESTRI;
17166 X86CC = X86::COND_B;
17168 case Intrinsic::x86_sse42_pcmpistrio128:
17169 Opcode = X86ISD::PCMPISTRI;
17170 X86CC = X86::COND_O;
17172 case Intrinsic::x86_sse42_pcmpestrio128:
17173 Opcode = X86ISD::PCMPESTRI;
17174 X86CC = X86::COND_O;
17176 case Intrinsic::x86_sse42_pcmpistris128:
17177 Opcode = X86ISD::PCMPISTRI;
17178 X86CC = X86::COND_S;
17180 case Intrinsic::x86_sse42_pcmpestris128:
17181 Opcode = X86ISD::PCMPESTRI;
17182 X86CC = X86::COND_S;
17184 case Intrinsic::x86_sse42_pcmpistriz128:
17185 Opcode = X86ISD::PCMPISTRI;
17186 X86CC = X86::COND_E;
17188 case Intrinsic::x86_sse42_pcmpestriz128:
17189 Opcode = X86ISD::PCMPESTRI;
17190 X86CC = X86::COND_E;
17193 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17194 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17195 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17196 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17197 DAG.getConstant(X86CC, MVT::i8),
17198 SDValue(PCMP.getNode(), 1));
17199 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17202 case Intrinsic::x86_sse42_pcmpistri128:
17203 case Intrinsic::x86_sse42_pcmpestri128: {
17205 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17206 Opcode = X86ISD::PCMPISTRI;
17208 Opcode = X86ISD::PCMPESTRI;
17210 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17211 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17212 return DAG.getNode(Opcode, dl, VTs, NewOps);
17215 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17216 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17217 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17218 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17219 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17220 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17221 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17222 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17223 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17224 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17225 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17226 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17227 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17228 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17229 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17230 dl, Op.getValueType(),
17234 Op.getOperand(4), Op.getOperand(1),
17240 case Intrinsic::x86_fma_vfmadd_ps:
17241 case Intrinsic::x86_fma_vfmadd_pd:
17242 case Intrinsic::x86_fma_vfmsub_ps:
17243 case Intrinsic::x86_fma_vfmsub_pd:
17244 case Intrinsic::x86_fma_vfnmadd_ps:
17245 case Intrinsic::x86_fma_vfnmadd_pd:
17246 case Intrinsic::x86_fma_vfnmsub_ps:
17247 case Intrinsic::x86_fma_vfnmsub_pd:
17248 case Intrinsic::x86_fma_vfmaddsub_ps:
17249 case Intrinsic::x86_fma_vfmaddsub_pd:
17250 case Intrinsic::x86_fma_vfmsubadd_ps:
17251 case Intrinsic::x86_fma_vfmsubadd_pd:
17252 case Intrinsic::x86_fma_vfmadd_ps_256:
17253 case Intrinsic::x86_fma_vfmadd_pd_256:
17254 case Intrinsic::x86_fma_vfmsub_ps_256:
17255 case Intrinsic::x86_fma_vfmsub_pd_256:
17256 case Intrinsic::x86_fma_vfnmadd_ps_256:
17257 case Intrinsic::x86_fma_vfnmadd_pd_256:
17258 case Intrinsic::x86_fma_vfnmsub_ps_256:
17259 case Intrinsic::x86_fma_vfnmsub_pd_256:
17260 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17261 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17262 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17263 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17264 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17265 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17269 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17270 SDValue Src, SDValue Mask, SDValue Base,
17271 SDValue Index, SDValue ScaleOp, SDValue Chain,
17272 const X86Subtarget * Subtarget) {
17274 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17275 assert(C && "Invalid scale type");
17276 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17277 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17278 Index.getSimpleValueType().getVectorNumElements());
17280 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17282 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17284 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17285 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17286 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17287 SDValue Segment = DAG.getRegister(0, MVT::i32);
17288 if (Src.getOpcode() == ISD::UNDEF)
17289 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17290 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17291 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17292 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17293 return DAG.getMergeValues(RetOps, dl);
17296 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17297 SDValue Src, SDValue Mask, SDValue Base,
17298 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17300 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17301 assert(C && "Invalid scale type");
17302 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17303 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17304 SDValue Segment = DAG.getRegister(0, MVT::i32);
17305 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17306 Index.getSimpleValueType().getVectorNumElements());
17308 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17310 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17312 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17313 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17314 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17315 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17316 return SDValue(Res, 1);
17319 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17320 SDValue Mask, SDValue Base, SDValue Index,
17321 SDValue ScaleOp, SDValue Chain) {
17323 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17324 assert(C && "Invalid scale type");
17325 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17326 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17327 SDValue Segment = DAG.getRegister(0, MVT::i32);
17329 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17331 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17333 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17335 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17336 //SDVTList VTs = DAG.getVTList(MVT::Other);
17337 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17338 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17339 return SDValue(Res, 0);
17342 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17343 // read performance monitor counters (x86_rdpmc).
17344 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17345 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17346 SmallVectorImpl<SDValue> &Results) {
17347 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17348 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17351 // The ECX register is used to select the index of the performance counter
17353 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17355 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17357 // Reads the content of a 64-bit performance counter and returns it in the
17358 // registers EDX:EAX.
17359 if (Subtarget->is64Bit()) {
17360 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17361 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17364 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17365 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17368 Chain = HI.getValue(1);
17370 if (Subtarget->is64Bit()) {
17371 // The EAX register is loaded with the low-order 32 bits. The EDX register
17372 // is loaded with the supported high-order bits of the counter.
17373 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17374 DAG.getConstant(32, MVT::i8));
17375 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17376 Results.push_back(Chain);
17380 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17381 SDValue Ops[] = { LO, HI };
17382 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17383 Results.push_back(Pair);
17384 Results.push_back(Chain);
17387 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17388 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17389 // also used to custom lower READCYCLECOUNTER nodes.
17390 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17391 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17392 SmallVectorImpl<SDValue> &Results) {
17393 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17394 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17397 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17398 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17399 // and the EAX register is loaded with the low-order 32 bits.
17400 if (Subtarget->is64Bit()) {
17401 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17402 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17405 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17406 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17409 SDValue Chain = HI.getValue(1);
17411 if (Opcode == X86ISD::RDTSCP_DAG) {
17412 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17414 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17415 // the ECX register. Add 'ecx' explicitly to the chain.
17416 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17418 // Explicitly store the content of ECX at the location passed in input
17419 // to the 'rdtscp' intrinsic.
17420 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17421 MachinePointerInfo(), false, false, 0);
17424 if (Subtarget->is64Bit()) {
17425 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17426 // the EAX register is loaded with the low-order 32 bits.
17427 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17428 DAG.getConstant(32, MVT::i8));
17429 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17430 Results.push_back(Chain);
17434 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17435 SDValue Ops[] = { LO, HI };
17436 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17437 Results.push_back(Pair);
17438 Results.push_back(Chain);
17441 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17442 SelectionDAG &DAG) {
17443 SmallVector<SDValue, 2> Results;
17445 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17447 return DAG.getMergeValues(Results, DL);
17451 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17452 SelectionDAG &DAG) {
17453 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17455 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17460 switch(IntrData->Type) {
17462 llvm_unreachable("Unknown Intrinsic Type");
17466 // Emit the node with the right value type.
17467 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17468 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17470 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17471 // Otherwise return the value from Rand, which is always 0, casted to i32.
17472 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17473 DAG.getConstant(1, Op->getValueType(1)),
17474 DAG.getConstant(X86::COND_B, MVT::i32),
17475 SDValue(Result.getNode(), 1) };
17476 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17477 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17480 // Return { result, isValid, chain }.
17481 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17482 SDValue(Result.getNode(), 2));
17485 //gather(v1, mask, index, base, scale);
17486 SDValue Chain = Op.getOperand(0);
17487 SDValue Src = Op.getOperand(2);
17488 SDValue Base = Op.getOperand(3);
17489 SDValue Index = Op.getOperand(4);
17490 SDValue Mask = Op.getOperand(5);
17491 SDValue Scale = Op.getOperand(6);
17492 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17496 //scatter(base, mask, index, v1, scale);
17497 SDValue Chain = Op.getOperand(0);
17498 SDValue Base = Op.getOperand(2);
17499 SDValue Mask = Op.getOperand(3);
17500 SDValue Index = Op.getOperand(4);
17501 SDValue Src = Op.getOperand(5);
17502 SDValue Scale = Op.getOperand(6);
17503 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17506 SDValue Hint = Op.getOperand(6);
17508 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17509 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17510 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17511 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17512 SDValue Chain = Op.getOperand(0);
17513 SDValue Mask = Op.getOperand(2);
17514 SDValue Index = Op.getOperand(3);
17515 SDValue Base = Op.getOperand(4);
17516 SDValue Scale = Op.getOperand(5);
17517 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17519 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17521 SmallVector<SDValue, 2> Results;
17522 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17523 return DAG.getMergeValues(Results, dl);
17525 // Read Performance Monitoring Counters.
17527 SmallVector<SDValue, 2> Results;
17528 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17529 return DAG.getMergeValues(Results, dl);
17531 // XTEST intrinsics.
17533 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17534 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17535 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17536 DAG.getConstant(X86::COND_NE, MVT::i8),
17538 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17539 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17540 Ret, SDValue(InTrans.getNode(), 1));
17544 SmallVector<SDValue, 2> Results;
17545 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17546 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17547 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17548 DAG.getConstant(-1, MVT::i8));
17549 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17550 Op.getOperand(4), GenCF.getValue(1));
17551 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17552 Op.getOperand(5), MachinePointerInfo(),
17554 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17555 DAG.getConstant(X86::COND_B, MVT::i8),
17557 Results.push_back(SetCC);
17558 Results.push_back(Store);
17559 return DAG.getMergeValues(Results, dl);
17561 case COMPRESS_TO_MEM: {
17563 SDValue Mask = Op.getOperand(4);
17564 SDValue DataToCompress = Op.getOperand(3);
17565 SDValue Addr = Op.getOperand(2);
17566 SDValue Chain = Op.getOperand(0);
17568 if (isAllOnes(Mask)) // return just a store
17569 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17570 MachinePointerInfo(), false, false, 0);
17572 EVT VT = DataToCompress.getValueType();
17573 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17574 VT.getVectorNumElements());
17575 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17576 Mask.getValueType().getSizeInBits());
17577 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17578 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17579 DAG.getIntPtrConstant(0));
17581 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17582 DataToCompress, DAG.getUNDEF(VT));
17583 return DAG.getStore(Chain, dl, Compressed, Addr,
17584 MachinePointerInfo(), false, false, 0);
17586 case EXPAND_FROM_MEM: {
17588 SDValue Mask = Op.getOperand(4);
17589 SDValue PathThru = Op.getOperand(3);
17590 SDValue Addr = Op.getOperand(2);
17591 SDValue Chain = Op.getOperand(0);
17592 EVT VT = Op.getValueType();
17594 if (isAllOnes(Mask)) // return just a load
17595 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17597 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17598 VT.getVectorNumElements());
17599 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17600 Mask.getValueType().getSizeInBits());
17601 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17602 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17603 DAG.getIntPtrConstant(0));
17605 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17606 false, false, false, 0);
17608 SmallVector<SDValue, 2> Results;
17609 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
17611 Results.push_back(Chain);
17612 return DAG.getMergeValues(Results, dl);
17617 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17618 SelectionDAG &DAG) const {
17619 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17620 MFI->setReturnAddressIsTaken(true);
17622 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17625 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17627 EVT PtrVT = getPointerTy();
17630 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17631 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17632 DAG.getSubtarget().getRegisterInfo());
17633 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17634 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17635 DAG.getNode(ISD::ADD, dl, PtrVT,
17636 FrameAddr, Offset),
17637 MachinePointerInfo(), false, false, false, 0);
17640 // Just load the return address.
17641 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17642 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17643 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17646 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17647 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17648 MFI->setFrameAddressIsTaken(true);
17650 EVT VT = Op.getValueType();
17651 SDLoc dl(Op); // FIXME probably not meaningful
17652 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17653 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17654 DAG.getSubtarget().getRegisterInfo());
17655 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17656 DAG.getMachineFunction());
17657 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17658 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17659 "Invalid Frame Register!");
17660 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17662 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17663 MachinePointerInfo(),
17664 false, false, false, 0);
17668 // FIXME? Maybe this could be a TableGen attribute on some registers and
17669 // this table could be generated automatically from RegInfo.
17670 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17672 unsigned Reg = StringSwitch<unsigned>(RegName)
17673 .Case("esp", X86::ESP)
17674 .Case("rsp", X86::RSP)
17678 report_fatal_error("Invalid register name global variable");
17681 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17682 SelectionDAG &DAG) const {
17683 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17684 DAG.getSubtarget().getRegisterInfo());
17685 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17688 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17689 SDValue Chain = Op.getOperand(0);
17690 SDValue Offset = Op.getOperand(1);
17691 SDValue Handler = Op.getOperand(2);
17694 EVT PtrVT = getPointerTy();
17695 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17696 DAG.getSubtarget().getRegisterInfo());
17697 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17698 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17699 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17700 "Invalid Frame Register!");
17701 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17702 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17704 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17705 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17706 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17707 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17709 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17711 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17712 DAG.getRegister(StoreAddrReg, PtrVT));
17715 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17716 SelectionDAG &DAG) const {
17718 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17719 DAG.getVTList(MVT::i32, MVT::Other),
17720 Op.getOperand(0), Op.getOperand(1));
17723 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17724 SelectionDAG &DAG) const {
17726 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17727 Op.getOperand(0), Op.getOperand(1));
17730 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17731 return Op.getOperand(0);
17734 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17735 SelectionDAG &DAG) const {
17736 SDValue Root = Op.getOperand(0);
17737 SDValue Trmp = Op.getOperand(1); // trampoline
17738 SDValue FPtr = Op.getOperand(2); // nested function
17739 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17742 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17743 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17745 if (Subtarget->is64Bit()) {
17746 SDValue OutChains[6];
17748 // Large code-model.
17749 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17750 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17752 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17753 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17755 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17757 // Load the pointer to the nested function into R11.
17758 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17759 SDValue Addr = Trmp;
17760 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17761 Addr, MachinePointerInfo(TrmpAddr),
17764 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17765 DAG.getConstant(2, MVT::i64));
17766 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17767 MachinePointerInfo(TrmpAddr, 2),
17770 // Load the 'nest' parameter value into R10.
17771 // R10 is specified in X86CallingConv.td
17772 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17773 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17774 DAG.getConstant(10, MVT::i64));
17775 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17776 Addr, MachinePointerInfo(TrmpAddr, 10),
17779 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17780 DAG.getConstant(12, MVT::i64));
17781 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17782 MachinePointerInfo(TrmpAddr, 12),
17785 // Jump to the nested function.
17786 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17787 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17788 DAG.getConstant(20, MVT::i64));
17789 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17790 Addr, MachinePointerInfo(TrmpAddr, 20),
17793 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17794 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17795 DAG.getConstant(22, MVT::i64));
17796 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17797 MachinePointerInfo(TrmpAddr, 22),
17800 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17802 const Function *Func =
17803 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17804 CallingConv::ID CC = Func->getCallingConv();
17809 llvm_unreachable("Unsupported calling convention");
17810 case CallingConv::C:
17811 case CallingConv::X86_StdCall: {
17812 // Pass 'nest' parameter in ECX.
17813 // Must be kept in sync with X86CallingConv.td
17814 NestReg = X86::ECX;
17816 // Check that ECX wasn't needed by an 'inreg' parameter.
17817 FunctionType *FTy = Func->getFunctionType();
17818 const AttributeSet &Attrs = Func->getAttributes();
17820 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17821 unsigned InRegCount = 0;
17824 for (FunctionType::param_iterator I = FTy->param_begin(),
17825 E = FTy->param_end(); I != E; ++I, ++Idx)
17826 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17827 // FIXME: should only count parameters that are lowered to integers.
17828 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17830 if (InRegCount > 2) {
17831 report_fatal_error("Nest register in use - reduce number of inreg"
17837 case CallingConv::X86_FastCall:
17838 case CallingConv::X86_ThisCall:
17839 case CallingConv::Fast:
17840 // Pass 'nest' parameter in EAX.
17841 // Must be kept in sync with X86CallingConv.td
17842 NestReg = X86::EAX;
17846 SDValue OutChains[4];
17847 SDValue Addr, Disp;
17849 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17850 DAG.getConstant(10, MVT::i32));
17851 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17853 // This is storing the opcode for MOV32ri.
17854 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17855 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17856 OutChains[0] = DAG.getStore(Root, dl,
17857 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17858 Trmp, MachinePointerInfo(TrmpAddr),
17861 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17862 DAG.getConstant(1, MVT::i32));
17863 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17864 MachinePointerInfo(TrmpAddr, 1),
17867 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17868 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17869 DAG.getConstant(5, MVT::i32));
17870 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17871 MachinePointerInfo(TrmpAddr, 5),
17874 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17875 DAG.getConstant(6, MVT::i32));
17876 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17877 MachinePointerInfo(TrmpAddr, 6),
17880 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17884 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17885 SelectionDAG &DAG) const {
17887 The rounding mode is in bits 11:10 of FPSR, and has the following
17889 00 Round to nearest
17894 FLT_ROUNDS, on the other hand, expects the following:
17901 To perform the conversion, we do:
17902 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17905 MachineFunction &MF = DAG.getMachineFunction();
17906 const TargetMachine &TM = MF.getTarget();
17907 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17908 unsigned StackAlignment = TFI.getStackAlignment();
17909 MVT VT = Op.getSimpleValueType();
17912 // Save FP Control Word to stack slot
17913 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17914 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17916 MachineMemOperand *MMO =
17917 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17918 MachineMemOperand::MOStore, 2, 2);
17920 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17921 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17922 DAG.getVTList(MVT::Other),
17923 Ops, MVT::i16, MMO);
17925 // Load FP Control Word from stack slot
17926 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17927 MachinePointerInfo(), false, false, false, 0);
17929 // Transform as necessary
17931 DAG.getNode(ISD::SRL, DL, MVT::i16,
17932 DAG.getNode(ISD::AND, DL, MVT::i16,
17933 CWD, DAG.getConstant(0x800, MVT::i16)),
17934 DAG.getConstant(11, MVT::i8));
17936 DAG.getNode(ISD::SRL, DL, MVT::i16,
17937 DAG.getNode(ISD::AND, DL, MVT::i16,
17938 CWD, DAG.getConstant(0x400, MVT::i16)),
17939 DAG.getConstant(9, MVT::i8));
17942 DAG.getNode(ISD::AND, DL, MVT::i16,
17943 DAG.getNode(ISD::ADD, DL, MVT::i16,
17944 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17945 DAG.getConstant(1, MVT::i16)),
17946 DAG.getConstant(3, MVT::i16));
17948 return DAG.getNode((VT.getSizeInBits() < 16 ?
17949 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17952 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17953 MVT VT = Op.getSimpleValueType();
17955 unsigned NumBits = VT.getSizeInBits();
17958 Op = Op.getOperand(0);
17959 if (VT == MVT::i8) {
17960 // Zero extend to i32 since there is not an i8 bsr.
17962 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17965 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17966 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17967 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17969 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17972 DAG.getConstant(NumBits+NumBits-1, OpVT),
17973 DAG.getConstant(X86::COND_E, MVT::i8),
17976 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17978 // Finally xor with NumBits-1.
17979 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17982 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17986 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17987 MVT VT = Op.getSimpleValueType();
17989 unsigned NumBits = VT.getSizeInBits();
17992 Op = Op.getOperand(0);
17993 if (VT == MVT::i8) {
17994 // Zero extend to i32 since there is not an i8 bsr.
17996 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17999 // Issue a bsr (scan bits in reverse).
18000 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18001 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18003 // And xor with NumBits-1.
18004 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
18007 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18011 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18012 MVT VT = Op.getSimpleValueType();
18013 unsigned NumBits = VT.getSizeInBits();
18015 Op = Op.getOperand(0);
18017 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18018 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18019 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
18021 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18024 DAG.getConstant(NumBits, VT),
18025 DAG.getConstant(X86::COND_E, MVT::i8),
18028 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18031 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18032 // ones, and then concatenate the result back.
18033 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18034 MVT VT = Op.getSimpleValueType();
18036 assert(VT.is256BitVector() && VT.isInteger() &&
18037 "Unsupported value type for operation");
18039 unsigned NumElems = VT.getVectorNumElements();
18042 // Extract the LHS vectors
18043 SDValue LHS = Op.getOperand(0);
18044 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18045 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18047 // Extract the RHS vectors
18048 SDValue RHS = Op.getOperand(1);
18049 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18050 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18052 MVT EltVT = VT.getVectorElementType();
18053 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18055 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18056 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18057 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18060 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18061 assert(Op.getSimpleValueType().is256BitVector() &&
18062 Op.getSimpleValueType().isInteger() &&
18063 "Only handle AVX 256-bit vector integer operation");
18064 return Lower256IntArith(Op, DAG);
18067 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18068 assert(Op.getSimpleValueType().is256BitVector() &&
18069 Op.getSimpleValueType().isInteger() &&
18070 "Only handle AVX 256-bit vector integer operation");
18071 return Lower256IntArith(Op, DAG);
18074 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18075 SelectionDAG &DAG) {
18077 MVT VT = Op.getSimpleValueType();
18079 // Decompose 256-bit ops into smaller 128-bit ops.
18080 if (VT.is256BitVector() && !Subtarget->hasInt256())
18081 return Lower256IntArith(Op, DAG);
18083 SDValue A = Op.getOperand(0);
18084 SDValue B = Op.getOperand(1);
18086 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18087 if (VT == MVT::v4i32) {
18088 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18089 "Should not custom lower when pmuldq is available!");
18091 // Extract the odd parts.
18092 static const int UnpackMask[] = { 1, -1, 3, -1 };
18093 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18094 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18096 // Multiply the even parts.
18097 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18098 // Now multiply odd parts.
18099 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18101 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18102 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18104 // Merge the two vectors back together with a shuffle. This expands into 2
18106 static const int ShufMask[] = { 0, 4, 2, 6 };
18107 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18110 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18111 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18113 // Ahi = psrlqi(a, 32);
18114 // Bhi = psrlqi(b, 32);
18116 // AloBlo = pmuludq(a, b);
18117 // AloBhi = pmuludq(a, Bhi);
18118 // AhiBlo = pmuludq(Ahi, b);
18120 // AloBhi = psllqi(AloBhi, 32);
18121 // AhiBlo = psllqi(AhiBlo, 32);
18122 // return AloBlo + AloBhi + AhiBlo;
18124 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18125 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18127 // Bit cast to 32-bit vectors for MULUDQ
18128 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18129 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18130 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18131 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18132 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18133 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18135 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18136 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18137 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18139 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18140 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18142 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18143 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18146 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18147 assert(Subtarget->isTargetWin64() && "Unexpected target");
18148 EVT VT = Op.getValueType();
18149 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18150 "Unexpected return type for lowering");
18154 switch (Op->getOpcode()) {
18155 default: llvm_unreachable("Unexpected request for libcall!");
18156 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18157 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18158 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18159 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18160 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18161 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18165 SDValue InChain = DAG.getEntryNode();
18167 TargetLowering::ArgListTy Args;
18168 TargetLowering::ArgListEntry Entry;
18169 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18170 EVT ArgVT = Op->getOperand(i).getValueType();
18171 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18172 "Unexpected argument type for lowering");
18173 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18174 Entry.Node = StackPtr;
18175 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18177 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18178 Entry.Ty = PointerType::get(ArgTy,0);
18179 Entry.isSExt = false;
18180 Entry.isZExt = false;
18181 Args.push_back(Entry);
18184 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18187 TargetLowering::CallLoweringInfo CLI(DAG);
18188 CLI.setDebugLoc(dl).setChain(InChain)
18189 .setCallee(getLibcallCallingConv(LC),
18190 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18191 Callee, std::move(Args), 0)
18192 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18194 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18195 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18198 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18199 SelectionDAG &DAG) {
18200 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18201 EVT VT = Op0.getValueType();
18204 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18205 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18207 // PMULxD operations multiply each even value (starting at 0) of LHS with
18208 // the related value of RHS and produce a widen result.
18209 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18210 // => <2 x i64> <ae|cg>
18212 // In other word, to have all the results, we need to perform two PMULxD:
18213 // 1. one with the even values.
18214 // 2. one with the odd values.
18215 // To achieve #2, with need to place the odd values at an even position.
18217 // Place the odd value at an even position (basically, shift all values 1
18218 // step to the left):
18219 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18220 // <a|b|c|d> => <b|undef|d|undef>
18221 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18222 // <e|f|g|h> => <f|undef|h|undef>
18223 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18225 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18227 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18228 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18230 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18231 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18232 // => <2 x i64> <ae|cg>
18233 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18234 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18235 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18236 // => <2 x i64> <bf|dh>
18237 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18238 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18240 // Shuffle it back into the right order.
18241 SDValue Highs, Lows;
18242 if (VT == MVT::v8i32) {
18243 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18244 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18245 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18246 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18248 const int HighMask[] = {1, 5, 3, 7};
18249 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18250 const int LowMask[] = {0, 4, 2, 6};
18251 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18254 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18255 // unsigned multiply.
18256 if (IsSigned && !Subtarget->hasSSE41()) {
18258 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18259 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18260 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18261 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18262 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18264 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18265 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18268 // The first result of MUL_LOHI is actually the low value, followed by the
18270 SDValue Ops[] = {Lows, Highs};
18271 return DAG.getMergeValues(Ops, dl);
18274 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18275 const X86Subtarget *Subtarget) {
18276 MVT VT = Op.getSimpleValueType();
18278 SDValue R = Op.getOperand(0);
18279 SDValue Amt = Op.getOperand(1);
18281 // Optimize shl/srl/sra with constant shift amount.
18282 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18283 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18284 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18286 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18287 (Subtarget->hasInt256() &&
18288 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18289 (Subtarget->hasAVX512() &&
18290 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18291 if (Op.getOpcode() == ISD::SHL)
18292 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18294 if (Op.getOpcode() == ISD::SRL)
18295 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18297 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18298 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18302 if (VT == MVT::v16i8) {
18303 if (Op.getOpcode() == ISD::SHL) {
18304 // Make a large shift.
18305 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18306 MVT::v8i16, R, ShiftAmt,
18308 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18309 // Zero out the rightmost bits.
18310 SmallVector<SDValue, 16> V(16,
18311 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18313 return DAG.getNode(ISD::AND, dl, VT, SHL,
18314 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18316 if (Op.getOpcode() == ISD::SRL) {
18317 // Make a large shift.
18318 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18319 MVT::v8i16, R, ShiftAmt,
18321 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18322 // Zero out the leftmost bits.
18323 SmallVector<SDValue, 16> V(16,
18324 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18326 return DAG.getNode(ISD::AND, dl, VT, SRL,
18327 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18329 if (Op.getOpcode() == ISD::SRA) {
18330 if (ShiftAmt == 7) {
18331 // R s>> 7 === R s< 0
18332 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18333 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18336 // R s>> a === ((R u>> a) ^ m) - m
18337 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18338 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18340 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18341 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18342 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18345 llvm_unreachable("Unknown shift opcode.");
18348 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18349 if (Op.getOpcode() == ISD::SHL) {
18350 // Make a large shift.
18351 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18352 MVT::v16i16, R, ShiftAmt,
18354 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18355 // Zero out the rightmost bits.
18356 SmallVector<SDValue, 32> V(32,
18357 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18359 return DAG.getNode(ISD::AND, dl, VT, SHL,
18360 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18362 if (Op.getOpcode() == ISD::SRL) {
18363 // Make a large shift.
18364 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18365 MVT::v16i16, R, ShiftAmt,
18367 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18368 // Zero out the leftmost bits.
18369 SmallVector<SDValue, 32> V(32,
18370 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18372 return DAG.getNode(ISD::AND, dl, VT, SRL,
18373 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18375 if (Op.getOpcode() == ISD::SRA) {
18376 if (ShiftAmt == 7) {
18377 // R s>> 7 === R s< 0
18378 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18379 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18382 // R s>> a === ((R u>> a) ^ m) - m
18383 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18384 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18386 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18387 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18388 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18391 llvm_unreachable("Unknown shift opcode.");
18396 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18397 if (!Subtarget->is64Bit() &&
18398 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18399 Amt.getOpcode() == ISD::BITCAST &&
18400 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18401 Amt = Amt.getOperand(0);
18402 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18403 VT.getVectorNumElements();
18404 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18405 uint64_t ShiftAmt = 0;
18406 for (unsigned i = 0; i != Ratio; ++i) {
18407 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18411 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18413 // Check remaining shift amounts.
18414 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18415 uint64_t ShAmt = 0;
18416 for (unsigned j = 0; j != Ratio; ++j) {
18417 ConstantSDNode *C =
18418 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18422 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18424 if (ShAmt != ShiftAmt)
18427 switch (Op.getOpcode()) {
18429 llvm_unreachable("Unknown shift opcode!");
18431 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18434 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18437 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18445 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18446 const X86Subtarget* Subtarget) {
18447 MVT VT = Op.getSimpleValueType();
18449 SDValue R = Op.getOperand(0);
18450 SDValue Amt = Op.getOperand(1);
18452 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18453 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18454 (Subtarget->hasInt256() &&
18455 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18456 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18457 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18459 EVT EltVT = VT.getVectorElementType();
18461 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18462 // Check if this build_vector node is doing a splat.
18463 // If so, then set BaseShAmt equal to the splat value.
18464 BaseShAmt = BV->getSplatValue();
18465 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18466 BaseShAmt = SDValue();
18468 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18469 Amt = Amt.getOperand(0);
18471 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18472 if (SVN && SVN->isSplat()) {
18473 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18474 SDValue InVec = Amt.getOperand(0);
18475 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18476 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18477 "Unexpected shuffle index found!");
18478 BaseShAmt = InVec.getOperand(SplatIdx);
18479 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18480 if (ConstantSDNode *C =
18481 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18482 if (C->getZExtValue() == SplatIdx)
18483 BaseShAmt = InVec.getOperand(1);
18488 // Avoid introducing an extract element from a shuffle.
18489 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18490 DAG.getIntPtrConstant(SplatIdx));
18494 if (BaseShAmt.getNode()) {
18495 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18496 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18497 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18498 else if (EltVT.bitsLT(MVT::i32))
18499 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18501 switch (Op.getOpcode()) {
18503 llvm_unreachable("Unknown shift opcode!");
18505 switch (VT.SimpleTy) {
18506 default: return SDValue();
18515 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18518 switch (VT.SimpleTy) {
18519 default: return SDValue();
18526 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18529 switch (VT.SimpleTy) {
18530 default: return SDValue();
18539 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18545 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18546 if (!Subtarget->is64Bit() &&
18547 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18548 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18549 Amt.getOpcode() == ISD::BITCAST &&
18550 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18551 Amt = Amt.getOperand(0);
18552 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18553 VT.getVectorNumElements();
18554 std::vector<SDValue> Vals(Ratio);
18555 for (unsigned i = 0; i != Ratio; ++i)
18556 Vals[i] = Amt.getOperand(i);
18557 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18558 for (unsigned j = 0; j != Ratio; ++j)
18559 if (Vals[j] != Amt.getOperand(i + j))
18562 switch (Op.getOpcode()) {
18564 llvm_unreachable("Unknown shift opcode!");
18566 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18568 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18570 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18577 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18578 SelectionDAG &DAG) {
18579 MVT VT = Op.getSimpleValueType();
18581 SDValue R = Op.getOperand(0);
18582 SDValue Amt = Op.getOperand(1);
18585 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18586 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18588 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18592 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18596 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18598 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18599 if (Subtarget->hasInt256()) {
18600 if (Op.getOpcode() == ISD::SRL &&
18601 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18602 VT == MVT::v4i64 || VT == MVT::v8i32))
18604 if (Op.getOpcode() == ISD::SHL &&
18605 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18606 VT == MVT::v4i64 || VT == MVT::v8i32))
18608 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18612 // If possible, lower this packed shift into a vector multiply instead of
18613 // expanding it into a sequence of scalar shifts.
18614 // Do this only if the vector shift count is a constant build_vector.
18615 if (Op.getOpcode() == ISD::SHL &&
18616 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18617 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18618 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18619 SmallVector<SDValue, 8> Elts;
18620 EVT SVT = VT.getScalarType();
18621 unsigned SVTBits = SVT.getSizeInBits();
18622 const APInt &One = APInt(SVTBits, 1);
18623 unsigned NumElems = VT.getVectorNumElements();
18625 for (unsigned i=0; i !=NumElems; ++i) {
18626 SDValue Op = Amt->getOperand(i);
18627 if (Op->getOpcode() == ISD::UNDEF) {
18628 Elts.push_back(Op);
18632 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18633 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18634 uint64_t ShAmt = C.getZExtValue();
18635 if (ShAmt >= SVTBits) {
18636 Elts.push_back(DAG.getUNDEF(SVT));
18639 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18641 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18642 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18645 // Lower SHL with variable shift amount.
18646 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18647 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18649 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18650 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18651 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18652 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18655 // If possible, lower this shift as a sequence of two shifts by
18656 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18658 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18660 // Could be rewritten as:
18661 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18663 // The advantage is that the two shifts from the example would be
18664 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18665 // the vector shift into four scalar shifts plus four pairs of vector
18667 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18668 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18669 unsigned TargetOpcode = X86ISD::MOVSS;
18670 bool CanBeSimplified;
18671 // The splat value for the first packed shift (the 'X' from the example).
18672 SDValue Amt1 = Amt->getOperand(0);
18673 // The splat value for the second packed shift (the 'Y' from the example).
18674 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18675 Amt->getOperand(2);
18677 // See if it is possible to replace this node with a sequence of
18678 // two shifts followed by a MOVSS/MOVSD
18679 if (VT == MVT::v4i32) {
18680 // Check if it is legal to use a MOVSS.
18681 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18682 Amt2 == Amt->getOperand(3);
18683 if (!CanBeSimplified) {
18684 // Otherwise, check if we can still simplify this node using a MOVSD.
18685 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18686 Amt->getOperand(2) == Amt->getOperand(3);
18687 TargetOpcode = X86ISD::MOVSD;
18688 Amt2 = Amt->getOperand(2);
18691 // Do similar checks for the case where the machine value type
18693 CanBeSimplified = Amt1 == Amt->getOperand(1);
18694 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18695 CanBeSimplified = Amt2 == Amt->getOperand(i);
18697 if (!CanBeSimplified) {
18698 TargetOpcode = X86ISD::MOVSD;
18699 CanBeSimplified = true;
18700 Amt2 = Amt->getOperand(4);
18701 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18702 CanBeSimplified = Amt1 == Amt->getOperand(i);
18703 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18704 CanBeSimplified = Amt2 == Amt->getOperand(j);
18708 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18709 isa<ConstantSDNode>(Amt2)) {
18710 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18711 EVT CastVT = MVT::v4i32;
18713 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18714 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18716 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18717 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18718 if (TargetOpcode == X86ISD::MOVSD)
18719 CastVT = MVT::v2i64;
18720 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18721 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18722 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18724 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18728 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18729 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18732 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18733 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18735 // Turn 'a' into a mask suitable for VSELECT
18736 SDValue VSelM = DAG.getConstant(0x80, VT);
18737 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18738 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18740 SDValue CM1 = DAG.getConstant(0x0f, VT);
18741 SDValue CM2 = DAG.getConstant(0x3f, VT);
18743 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18744 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18745 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18746 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18747 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18750 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18751 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18752 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18754 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18755 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18756 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18757 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18758 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18761 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18762 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18763 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18765 // return VSELECT(r, r+r, a);
18766 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18767 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18771 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18772 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18773 // solution better.
18774 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18775 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18777 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18778 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18779 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18780 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18781 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18784 // Decompose 256-bit shifts into smaller 128-bit shifts.
18785 if (VT.is256BitVector()) {
18786 unsigned NumElems = VT.getVectorNumElements();
18787 MVT EltVT = VT.getVectorElementType();
18788 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18790 // Extract the two vectors
18791 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18792 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18794 // Recreate the shift amount vectors
18795 SDValue Amt1, Amt2;
18796 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18797 // Constant shift amount
18798 SmallVector<SDValue, 4> Amt1Csts;
18799 SmallVector<SDValue, 4> Amt2Csts;
18800 for (unsigned i = 0; i != NumElems/2; ++i)
18801 Amt1Csts.push_back(Amt->getOperand(i));
18802 for (unsigned i = NumElems/2; i != NumElems; ++i)
18803 Amt2Csts.push_back(Amt->getOperand(i));
18805 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18806 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18808 // Variable shift amount
18809 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18810 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18813 // Issue new vector shifts for the smaller types
18814 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18815 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18817 // Concatenate the result back
18818 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18824 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18825 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18826 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18827 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18828 // has only one use.
18829 SDNode *N = Op.getNode();
18830 SDValue LHS = N->getOperand(0);
18831 SDValue RHS = N->getOperand(1);
18832 unsigned BaseOp = 0;
18835 switch (Op.getOpcode()) {
18836 default: llvm_unreachable("Unknown ovf instruction!");
18838 // A subtract of one will be selected as a INC. Note that INC doesn't
18839 // set CF, so we can't do this for UADDO.
18840 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18842 BaseOp = X86ISD::INC;
18843 Cond = X86::COND_O;
18846 BaseOp = X86ISD::ADD;
18847 Cond = X86::COND_O;
18850 BaseOp = X86ISD::ADD;
18851 Cond = X86::COND_B;
18854 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18855 // set CF, so we can't do this for USUBO.
18856 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18858 BaseOp = X86ISD::DEC;
18859 Cond = X86::COND_O;
18862 BaseOp = X86ISD::SUB;
18863 Cond = X86::COND_O;
18866 BaseOp = X86ISD::SUB;
18867 Cond = X86::COND_B;
18870 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18871 Cond = X86::COND_O;
18873 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18874 if (N->getValueType(0) == MVT::i8) {
18875 BaseOp = X86ISD::UMUL8;
18876 Cond = X86::COND_O;
18879 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18881 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18884 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18885 DAG.getConstant(X86::COND_O, MVT::i32),
18886 SDValue(Sum.getNode(), 2));
18888 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18892 // Also sets EFLAGS.
18893 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18894 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18897 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18898 DAG.getConstant(Cond, MVT::i32),
18899 SDValue(Sum.getNode(), 1));
18901 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18904 // Sign extension of the low part of vector elements. This may be used either
18905 // when sign extend instructions are not available or if the vector element
18906 // sizes already match the sign-extended size. If the vector elements are in
18907 // their pre-extended size and sign extend instructions are available, that will
18908 // be handled by LowerSIGN_EXTEND.
18909 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18910 SelectionDAG &DAG) const {
18912 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18913 MVT VT = Op.getSimpleValueType();
18915 if (!Subtarget->hasSSE2() || !VT.isVector())
18918 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18919 ExtraVT.getScalarType().getSizeInBits();
18921 switch (VT.SimpleTy) {
18922 default: return SDValue();
18925 if (!Subtarget->hasFp256())
18927 if (!Subtarget->hasInt256()) {
18928 // needs to be split
18929 unsigned NumElems = VT.getVectorNumElements();
18931 // Extract the LHS vectors
18932 SDValue LHS = Op.getOperand(0);
18933 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18934 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18936 MVT EltVT = VT.getVectorElementType();
18937 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18939 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18940 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18941 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18943 SDValue Extra = DAG.getValueType(ExtraVT);
18945 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18946 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18948 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18953 SDValue Op0 = Op.getOperand(0);
18955 // This is a sign extension of some low part of vector elements without
18956 // changing the size of the vector elements themselves:
18957 // Shift-Left + Shift-Right-Algebraic.
18958 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18960 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18966 /// Returns true if the operand type is exactly twice the native width, and
18967 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18968 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18969 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18970 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18971 const X86Subtarget &Subtarget =
18972 getTargetMachine().getSubtarget<X86Subtarget>();
18973 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18976 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18977 else if (OpWidth == 128)
18978 return Subtarget.hasCmpxchg16b();
18983 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18984 return needsCmpXchgNb(SI->getValueOperand()->getType());
18987 // Note: this turns large loads into lock cmpxchg8b/16b.
18988 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18989 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18990 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18991 return needsCmpXchgNb(PTy->getElementType());
18994 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18995 const X86Subtarget &Subtarget =
18996 getTargetMachine().getSubtarget<X86Subtarget>();
18997 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18998 const Type *MemType = AI->getType();
19000 // If the operand is too big, we must see if cmpxchg8/16b is available
19001 // and default to library calls otherwise.
19002 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19003 return needsCmpXchgNb(MemType);
19005 AtomicRMWInst::BinOp Op = AI->getOperation();
19008 llvm_unreachable("Unknown atomic operation");
19009 case AtomicRMWInst::Xchg:
19010 case AtomicRMWInst::Add:
19011 case AtomicRMWInst::Sub:
19012 // It's better to use xadd, xsub or xchg for these in all cases.
19014 case AtomicRMWInst::Or:
19015 case AtomicRMWInst::And:
19016 case AtomicRMWInst::Xor:
19017 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19018 // prefix to a normal instruction for these operations.
19019 return !AI->use_empty();
19020 case AtomicRMWInst::Nand:
19021 case AtomicRMWInst::Max:
19022 case AtomicRMWInst::Min:
19023 case AtomicRMWInst::UMax:
19024 case AtomicRMWInst::UMin:
19025 // These always require a non-trivial set of data operations on x86. We must
19026 // use a cmpxchg loop.
19031 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19032 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19033 // no-sse2). There isn't any reason to disable it if the target processor
19035 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19039 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19040 const X86Subtarget &Subtarget =
19041 getTargetMachine().getSubtarget<X86Subtarget>();
19042 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19043 const Type *MemType = AI->getType();
19044 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19045 // there is no benefit in turning such RMWs into loads, and it is actually
19046 // harmful as it introduces a mfence.
19047 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19050 auto Builder = IRBuilder<>(AI);
19051 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19052 auto SynchScope = AI->getSynchScope();
19053 // We must restrict the ordering to avoid generating loads with Release or
19054 // ReleaseAcquire orderings.
19055 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19056 auto Ptr = AI->getPointerOperand();
19058 // Before the load we need a fence. Here is an example lifted from
19059 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19062 // x.store(1, relaxed);
19063 // r1 = y.fetch_add(0, release);
19065 // y.fetch_add(42, acquire);
19066 // r2 = x.load(relaxed);
19067 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19068 // lowered to just a load without a fence. A mfence flushes the store buffer,
19069 // making the optimization clearly correct.
19070 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19071 // otherwise, we might be able to be more agressive on relaxed idempotent
19072 // rmw. In practice, they do not look useful, so we don't try to be
19073 // especially clever.
19074 if (SynchScope == SingleThread) {
19075 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19076 // the IR level, so we must wrap it in an intrinsic.
19078 } else if (hasMFENCE(Subtarget)) {
19079 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19080 Intrinsic::x86_sse2_mfence);
19081 Builder.CreateCall(MFence);
19083 // FIXME: it might make sense to use a locked operation here but on a
19084 // different cache-line to prevent cache-line bouncing. In practice it
19085 // is probably a small win, and x86 processors without mfence are rare
19086 // enough that we do not bother.
19090 // Finally we can emit the atomic load.
19091 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19092 AI->getType()->getPrimitiveSizeInBits());
19093 Loaded->setAtomic(Order, SynchScope);
19094 AI->replaceAllUsesWith(Loaded);
19095 AI->eraseFromParent();
19099 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19100 SelectionDAG &DAG) {
19102 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19103 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19104 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19105 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19107 // The only fence that needs an instruction is a sequentially-consistent
19108 // cross-thread fence.
19109 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19110 if (hasMFENCE(*Subtarget))
19111 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19113 SDValue Chain = Op.getOperand(0);
19114 SDValue Zero = DAG.getConstant(0, MVT::i32);
19116 DAG.getRegister(X86::ESP, MVT::i32), // Base
19117 DAG.getTargetConstant(1, MVT::i8), // Scale
19118 DAG.getRegister(0, MVT::i32), // Index
19119 DAG.getTargetConstant(0, MVT::i32), // Disp
19120 DAG.getRegister(0, MVT::i32), // Segment.
19124 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19125 return SDValue(Res, 0);
19128 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19129 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19132 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19133 SelectionDAG &DAG) {
19134 MVT T = Op.getSimpleValueType();
19138 switch(T.SimpleTy) {
19139 default: llvm_unreachable("Invalid value type!");
19140 case MVT::i8: Reg = X86::AL; size = 1; break;
19141 case MVT::i16: Reg = X86::AX; size = 2; break;
19142 case MVT::i32: Reg = X86::EAX; size = 4; break;
19144 assert(Subtarget->is64Bit() && "Node not type legal!");
19145 Reg = X86::RAX; size = 8;
19148 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19149 Op.getOperand(2), SDValue());
19150 SDValue Ops[] = { cpIn.getValue(0),
19153 DAG.getTargetConstant(size, MVT::i8),
19154 cpIn.getValue(1) };
19155 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19156 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19157 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19161 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19162 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19163 MVT::i32, cpOut.getValue(2));
19164 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19165 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19167 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19168 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19169 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19173 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19174 SelectionDAG &DAG) {
19175 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19176 MVT DstVT = Op.getSimpleValueType();
19178 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19179 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19180 if (DstVT != MVT::f64)
19181 // This conversion needs to be expanded.
19184 SDValue InVec = Op->getOperand(0);
19186 unsigned NumElts = SrcVT.getVectorNumElements();
19187 EVT SVT = SrcVT.getVectorElementType();
19189 // Widen the vector in input in the case of MVT::v2i32.
19190 // Example: from MVT::v2i32 to MVT::v4i32.
19191 SmallVector<SDValue, 16> Elts;
19192 for (unsigned i = 0, e = NumElts; i != e; ++i)
19193 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19194 DAG.getIntPtrConstant(i)));
19196 // Explicitly mark the extra elements as Undef.
19197 SDValue Undef = DAG.getUNDEF(SVT);
19198 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19199 Elts.push_back(Undef);
19201 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19202 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19203 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19204 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19205 DAG.getIntPtrConstant(0));
19208 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19209 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19210 assert((DstVT == MVT::i64 ||
19211 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19212 "Unexpected custom BITCAST");
19213 // i64 <=> MMX conversions are Legal.
19214 if (SrcVT==MVT::i64 && DstVT.isVector())
19216 if (DstVT==MVT::i64 && SrcVT.isVector())
19218 // MMX <=> MMX conversions are Legal.
19219 if (SrcVT.isVector() && DstVT.isVector())
19221 // All other conversions need to be expanded.
19225 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19226 SelectionDAG &DAG) {
19227 SDNode *Node = Op.getNode();
19230 Op = Op.getOperand(0);
19231 EVT VT = Op.getValueType();
19232 assert((VT.is128BitVector() || VT.is256BitVector()) &&
19233 "CTPOP lowering only implemented for 128/256-bit wide vector types");
19235 unsigned NumElts = VT.getVectorNumElements();
19236 EVT EltVT = VT.getVectorElementType();
19237 unsigned Len = EltVT.getSizeInBits();
19239 // This is the vectorized version of the "best" algorithm from
19240 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19241 // with a minor tweak to use a series of adds + shifts instead of vector
19242 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
19244 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
19245 // v8i32 => Always profitable
19247 // FIXME: There a couple of possible improvements:
19249 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
19250 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
19252 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
19253 "CTPOP not implemented for this vector element type.");
19255 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
19256 // extra legalization.
19257 bool NeedsBitcast = EltVT == MVT::i32;
19258 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
19260 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
19261 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
19262 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
19264 // v = v - ((v >> 1) & 0x55555555...)
19265 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
19266 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
19267 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
19269 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19271 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
19272 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
19274 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
19276 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
19277 if (VT != And.getValueType())
19278 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19279 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
19281 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19282 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
19283 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
19284 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
19285 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
19287 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
19288 if (NeedsBitcast) {
19289 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
19290 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
19291 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
19294 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
19295 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
19296 if (VT != AndRHS.getValueType()) {
19297 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
19298 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
19300 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
19302 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19303 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
19304 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
19305 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
19306 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19308 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
19309 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
19310 if (NeedsBitcast) {
19311 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19312 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
19314 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
19315 if (VT != And.getValueType())
19316 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19318 // The algorithm mentioned above uses:
19319 // v = (v * 0x01010101...) >> (Len - 8)
19321 // Change it to use vector adds + vector shifts which yield faster results on
19322 // Haswell than using vector integer multiplication.
19324 // For i32 elements:
19325 // v = v + (v >> 8)
19326 // v = v + (v >> 16)
19328 // For i64 elements:
19329 // v = v + (v >> 8)
19330 // v = v + (v >> 16)
19331 // v = v + (v >> 32)
19334 SmallVector<SDValue, 8> Csts;
19335 for (unsigned i = 8; i <= Len/2; i *= 2) {
19336 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
19337 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
19338 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
19339 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
19343 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
19344 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
19345 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
19346 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
19347 if (NeedsBitcast) {
19348 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
19349 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
19351 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
19352 if (VT != And.getValueType())
19353 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
19358 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19359 SDNode *Node = Op.getNode();
19361 EVT T = Node->getValueType(0);
19362 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19363 DAG.getConstant(0, T), Node->getOperand(2));
19364 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19365 cast<AtomicSDNode>(Node)->getMemoryVT(),
19366 Node->getOperand(0),
19367 Node->getOperand(1), negOp,
19368 cast<AtomicSDNode>(Node)->getMemOperand(),
19369 cast<AtomicSDNode>(Node)->getOrdering(),
19370 cast<AtomicSDNode>(Node)->getSynchScope());
19373 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19374 SDNode *Node = Op.getNode();
19376 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19378 // Convert seq_cst store -> xchg
19379 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19380 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19381 // (The only way to get a 16-byte store is cmpxchg16b)
19382 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19383 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19384 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19385 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19386 cast<AtomicSDNode>(Node)->getMemoryVT(),
19387 Node->getOperand(0),
19388 Node->getOperand(1), Node->getOperand(2),
19389 cast<AtomicSDNode>(Node)->getMemOperand(),
19390 cast<AtomicSDNode>(Node)->getOrdering(),
19391 cast<AtomicSDNode>(Node)->getSynchScope());
19392 return Swap.getValue(1);
19394 // Other atomic stores have a simple pattern.
19398 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19399 EVT VT = Op.getNode()->getSimpleValueType(0);
19401 // Let legalize expand this if it isn't a legal type yet.
19402 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19405 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19408 bool ExtraOp = false;
19409 switch (Op.getOpcode()) {
19410 default: llvm_unreachable("Invalid code");
19411 case ISD::ADDC: Opc = X86ISD::ADD; break;
19412 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19413 case ISD::SUBC: Opc = X86ISD::SUB; break;
19414 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19418 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19420 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19421 Op.getOperand(1), Op.getOperand(2));
19424 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19425 SelectionDAG &DAG) {
19426 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19428 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19429 // which returns the values as { float, float } (in XMM0) or
19430 // { double, double } (which is returned in XMM0, XMM1).
19432 SDValue Arg = Op.getOperand(0);
19433 EVT ArgVT = Arg.getValueType();
19434 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19436 TargetLowering::ArgListTy Args;
19437 TargetLowering::ArgListEntry Entry;
19441 Entry.isSExt = false;
19442 Entry.isZExt = false;
19443 Args.push_back(Entry);
19445 bool isF64 = ArgVT == MVT::f64;
19446 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19447 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19448 // the results are returned via SRet in memory.
19449 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19451 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19453 Type *RetTy = isF64
19454 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19455 : (Type*)VectorType::get(ArgTy, 4);
19457 TargetLowering::CallLoweringInfo CLI(DAG);
19458 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19459 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19461 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19464 // Returned in xmm0 and xmm1.
19465 return CallResult.first;
19467 // Returned in bits 0:31 and 32:64 xmm0.
19468 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19469 CallResult.first, DAG.getIntPtrConstant(0));
19470 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19471 CallResult.first, DAG.getIntPtrConstant(1));
19472 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19473 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19476 /// LowerOperation - Provide custom lowering hooks for some operations.
19478 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19479 switch (Op.getOpcode()) {
19480 default: llvm_unreachable("Should not custom lower this!");
19481 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19482 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19483 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19484 return LowerCMP_SWAP(Op, Subtarget, DAG);
19485 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19486 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19487 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19488 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19489 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19490 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19491 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19492 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19493 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19494 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19495 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19496 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19497 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19498 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19499 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19500 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19501 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19502 case ISD::SHL_PARTS:
19503 case ISD::SRA_PARTS:
19504 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19505 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19506 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19507 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19508 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19509 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19510 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19511 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19512 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19513 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19514 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19516 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19517 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19518 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19519 case ISD::SETCC: return LowerSETCC(Op, DAG);
19520 case ISD::SELECT: return LowerSELECT(Op, DAG);
19521 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19522 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19523 case ISD::VASTART: return LowerVASTART(Op, DAG);
19524 case ISD::VAARG: return LowerVAARG(Op, DAG);
19525 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19526 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19527 case ISD::INTRINSIC_VOID:
19528 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19529 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19530 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19531 case ISD::FRAME_TO_ARGS_OFFSET:
19532 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19533 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19534 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19535 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19536 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19537 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19538 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19539 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19540 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19541 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19542 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19543 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19544 case ISD::UMUL_LOHI:
19545 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19548 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19554 case ISD::UMULO: return LowerXALUO(Op, DAG);
19555 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19556 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19560 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19561 case ISD::ADD: return LowerADD(Op, DAG);
19562 case ISD::SUB: return LowerSUB(Op, DAG);
19563 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19567 /// ReplaceNodeResults - Replace a node with an illegal result type
19568 /// with a new node built out of custom code.
19569 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19570 SmallVectorImpl<SDValue>&Results,
19571 SelectionDAG &DAG) const {
19573 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19574 switch (N->getOpcode()) {
19576 llvm_unreachable("Do not know how to custom type legalize this operation!");
19577 case ISD::SIGN_EXTEND_INREG:
19582 // We don't want to expand or promote these.
19589 case ISD::UDIVREM: {
19590 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19591 Results.push_back(V);
19594 case ISD::FP_TO_SINT:
19595 case ISD::FP_TO_UINT: {
19596 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19598 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19601 std::pair<SDValue,SDValue> Vals =
19602 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19603 SDValue FIST = Vals.first, StackSlot = Vals.second;
19604 if (FIST.getNode()) {
19605 EVT VT = N->getValueType(0);
19606 // Return a load from the stack slot.
19607 if (StackSlot.getNode())
19608 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19609 MachinePointerInfo(),
19610 false, false, false, 0));
19612 Results.push_back(FIST);
19616 case ISD::UINT_TO_FP: {
19617 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19618 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19619 N->getValueType(0) != MVT::v2f32)
19621 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19623 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19625 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19626 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19627 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19628 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19629 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19630 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19633 case ISD::FP_ROUND: {
19634 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19636 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19637 Results.push_back(V);
19640 case ISD::INTRINSIC_W_CHAIN: {
19641 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19643 default : llvm_unreachable("Do not know how to custom type "
19644 "legalize this intrinsic operation!");
19645 case Intrinsic::x86_rdtsc:
19646 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19648 case Intrinsic::x86_rdtscp:
19649 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19651 case Intrinsic::x86_rdpmc:
19652 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19655 case ISD::READCYCLECOUNTER: {
19656 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19659 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19660 EVT T = N->getValueType(0);
19661 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19662 bool Regs64bit = T == MVT::i128;
19663 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19664 SDValue cpInL, cpInH;
19665 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19666 DAG.getConstant(0, HalfT));
19667 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19668 DAG.getConstant(1, HalfT));
19669 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19670 Regs64bit ? X86::RAX : X86::EAX,
19672 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19673 Regs64bit ? X86::RDX : X86::EDX,
19674 cpInH, cpInL.getValue(1));
19675 SDValue swapInL, swapInH;
19676 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19677 DAG.getConstant(0, HalfT));
19678 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19679 DAG.getConstant(1, HalfT));
19680 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19681 Regs64bit ? X86::RBX : X86::EBX,
19682 swapInL, cpInH.getValue(1));
19683 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19684 Regs64bit ? X86::RCX : X86::ECX,
19685 swapInH, swapInL.getValue(1));
19686 SDValue Ops[] = { swapInH.getValue(0),
19688 swapInH.getValue(1) };
19689 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19690 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19691 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19692 X86ISD::LCMPXCHG8_DAG;
19693 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19694 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19695 Regs64bit ? X86::RAX : X86::EAX,
19696 HalfT, Result.getValue(1));
19697 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19698 Regs64bit ? X86::RDX : X86::EDX,
19699 HalfT, cpOutL.getValue(2));
19700 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19702 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19703 MVT::i32, cpOutH.getValue(2));
19705 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19706 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19707 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19709 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19710 Results.push_back(Success);
19711 Results.push_back(EFLAGS.getValue(1));
19714 case ISD::ATOMIC_SWAP:
19715 case ISD::ATOMIC_LOAD_ADD:
19716 case ISD::ATOMIC_LOAD_SUB:
19717 case ISD::ATOMIC_LOAD_AND:
19718 case ISD::ATOMIC_LOAD_OR:
19719 case ISD::ATOMIC_LOAD_XOR:
19720 case ISD::ATOMIC_LOAD_NAND:
19721 case ISD::ATOMIC_LOAD_MIN:
19722 case ISD::ATOMIC_LOAD_MAX:
19723 case ISD::ATOMIC_LOAD_UMIN:
19724 case ISD::ATOMIC_LOAD_UMAX:
19725 case ISD::ATOMIC_LOAD: {
19726 // Delegate to generic TypeLegalization. Situations we can really handle
19727 // should have already been dealt with by AtomicExpandPass.cpp.
19730 case ISD::BITCAST: {
19731 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19732 EVT DstVT = N->getValueType(0);
19733 EVT SrcVT = N->getOperand(0)->getValueType(0);
19735 if (SrcVT != MVT::f64 ||
19736 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19739 unsigned NumElts = DstVT.getVectorNumElements();
19740 EVT SVT = DstVT.getVectorElementType();
19741 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19742 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19743 MVT::v2f64, N->getOperand(0));
19744 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19746 if (ExperimentalVectorWideningLegalization) {
19747 // If we are legalizing vectors by widening, we already have the desired
19748 // legal vector type, just return it.
19749 Results.push_back(ToVecInt);
19753 SmallVector<SDValue, 8> Elts;
19754 for (unsigned i = 0, e = NumElts; i != e; ++i)
19755 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19756 ToVecInt, DAG.getIntPtrConstant(i)));
19758 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19763 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19765 default: return nullptr;
19766 case X86ISD::BSF: return "X86ISD::BSF";
19767 case X86ISD::BSR: return "X86ISD::BSR";
19768 case X86ISD::SHLD: return "X86ISD::SHLD";
19769 case X86ISD::SHRD: return "X86ISD::SHRD";
19770 case X86ISD::FAND: return "X86ISD::FAND";
19771 case X86ISD::FANDN: return "X86ISD::FANDN";
19772 case X86ISD::FOR: return "X86ISD::FOR";
19773 case X86ISD::FXOR: return "X86ISD::FXOR";
19774 case X86ISD::FSRL: return "X86ISD::FSRL";
19775 case X86ISD::FILD: return "X86ISD::FILD";
19776 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19777 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19778 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19779 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19780 case X86ISD::FLD: return "X86ISD::FLD";
19781 case X86ISD::FST: return "X86ISD::FST";
19782 case X86ISD::CALL: return "X86ISD::CALL";
19783 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19784 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19785 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19786 case X86ISD::BT: return "X86ISD::BT";
19787 case X86ISD::CMP: return "X86ISD::CMP";
19788 case X86ISD::COMI: return "X86ISD::COMI";
19789 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19790 case X86ISD::CMPM: return "X86ISD::CMPM";
19791 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19792 case X86ISD::SETCC: return "X86ISD::SETCC";
19793 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19794 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19795 case X86ISD::CMOV: return "X86ISD::CMOV";
19796 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19797 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19798 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19799 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19800 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19801 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19802 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19803 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19804 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19805 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19806 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19807 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19808 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19809 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19810 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19811 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19812 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19813 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19814 case X86ISD::HADD: return "X86ISD::HADD";
19815 case X86ISD::HSUB: return "X86ISD::HSUB";
19816 case X86ISD::FHADD: return "X86ISD::FHADD";
19817 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19818 case X86ISD::UMAX: return "X86ISD::UMAX";
19819 case X86ISD::UMIN: return "X86ISD::UMIN";
19820 case X86ISD::SMAX: return "X86ISD::SMAX";
19821 case X86ISD::SMIN: return "X86ISD::SMIN";
19822 case X86ISD::FMAX: return "X86ISD::FMAX";
19823 case X86ISD::FMIN: return "X86ISD::FMIN";
19824 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19825 case X86ISD::FMINC: return "X86ISD::FMINC";
19826 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19827 case X86ISD::FRCP: return "X86ISD::FRCP";
19828 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19829 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19830 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19831 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19832 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19833 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19834 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19835 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19836 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19837 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19838 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19839 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19840 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19841 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19842 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19843 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19844 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19845 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19846 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19847 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19848 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19849 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19850 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19851 case X86ISD::VSHL: return "X86ISD::VSHL";
19852 case X86ISD::VSRL: return "X86ISD::VSRL";
19853 case X86ISD::VSRA: return "X86ISD::VSRA";
19854 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19855 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19856 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19857 case X86ISD::CMPP: return "X86ISD::CMPP";
19858 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19859 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19860 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19861 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19862 case X86ISD::ADD: return "X86ISD::ADD";
19863 case X86ISD::SUB: return "X86ISD::SUB";
19864 case X86ISD::ADC: return "X86ISD::ADC";
19865 case X86ISD::SBB: return "X86ISD::SBB";
19866 case X86ISD::SMUL: return "X86ISD::SMUL";
19867 case X86ISD::UMUL: return "X86ISD::UMUL";
19868 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19869 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19870 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19871 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19872 case X86ISD::INC: return "X86ISD::INC";
19873 case X86ISD::DEC: return "X86ISD::DEC";
19874 case X86ISD::OR: return "X86ISD::OR";
19875 case X86ISD::XOR: return "X86ISD::XOR";
19876 case X86ISD::AND: return "X86ISD::AND";
19877 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19878 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19879 case X86ISD::PTEST: return "X86ISD::PTEST";
19880 case X86ISD::TESTP: return "X86ISD::TESTP";
19881 case X86ISD::TESTM: return "X86ISD::TESTM";
19882 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19883 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19884 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19885 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19886 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19887 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19888 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19889 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19890 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19891 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19892 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19893 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19894 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19895 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19896 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19897 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19898 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19899 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19900 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19901 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19902 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19903 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19904 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19905 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19906 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19907 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19908 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19909 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19910 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19911 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19912 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19913 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19914 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19915 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19916 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19917 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19918 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19919 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19920 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19921 case X86ISD::SAHF: return "X86ISD::SAHF";
19922 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19923 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19924 case X86ISD::FMADD: return "X86ISD::FMADD";
19925 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19926 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19927 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19928 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19929 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19930 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19931 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19932 case X86ISD::XTEST: return "X86ISD::XTEST";
19933 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19934 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19935 case X86ISD::SELECT: return "X86ISD::SELECT";
19939 // isLegalAddressingMode - Return true if the addressing mode represented
19940 // by AM is legal for this target, for a load/store of the specified type.
19941 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19943 // X86 supports extremely general addressing modes.
19944 CodeModel::Model M = getTargetMachine().getCodeModel();
19945 Reloc::Model R = getTargetMachine().getRelocationModel();
19947 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19948 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19953 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19955 // If a reference to this global requires an extra load, we can't fold it.
19956 if (isGlobalStubReference(GVFlags))
19959 // If BaseGV requires a register for the PIC base, we cannot also have a
19960 // BaseReg specified.
19961 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19964 // If lower 4G is not available, then we must use rip-relative addressing.
19965 if ((M != CodeModel::Small || R != Reloc::Static) &&
19966 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19970 switch (AM.Scale) {
19976 // These scales always work.
19981 // These scales are formed with basereg+scalereg. Only accept if there is
19986 default: // Other stuff never works.
19993 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19994 unsigned Bits = Ty->getScalarSizeInBits();
19996 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19997 // particularly cheaper than those without.
20001 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20002 // variable shifts just as cheap as scalar ones.
20003 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20006 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20007 // fully general vector.
20011 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20012 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20014 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20015 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20016 return NumBits1 > NumBits2;
20019 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20020 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20023 if (!isTypeLegal(EVT::getEVT(Ty1)))
20026 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20028 // Assuming the caller doesn't have a zeroext or signext return parameter,
20029 // truncation all the way down to i1 is valid.
20033 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20034 return isInt<32>(Imm);
20037 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20038 // Can also use sub to handle negated immediates.
20039 return isInt<32>(Imm);
20042 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20043 if (!VT1.isInteger() || !VT2.isInteger())
20045 unsigned NumBits1 = VT1.getSizeInBits();
20046 unsigned NumBits2 = VT2.getSizeInBits();
20047 return NumBits1 > NumBits2;
20050 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20051 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20052 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20055 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20056 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20057 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20060 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20061 EVT VT1 = Val.getValueType();
20062 if (isZExtFree(VT1, VT2))
20065 if (Val.getOpcode() != ISD::LOAD)
20068 if (!VT1.isSimple() || !VT1.isInteger() ||
20069 !VT2.isSimple() || !VT2.isInteger())
20072 switch (VT1.getSimpleVT().SimpleTy) {
20077 // X86 has 8, 16, and 32-bit zero-extending loads.
20085 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20086 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
20089 VT = VT.getScalarType();
20091 if (!VT.isSimple())
20094 switch (VT.getSimpleVT().SimpleTy) {
20105 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20106 // i16 instructions are longer (0x66 prefix) and potentially slower.
20107 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20110 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20111 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20112 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20113 /// are assumed to be legal.
20115 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20117 if (!VT.isSimple())
20120 MVT SVT = VT.getSimpleVT();
20122 // Very little shuffling can be done for 64-bit vectors right now.
20123 if (VT.getSizeInBits() == 64)
20126 // If this is a single-input shuffle with no 128 bit lane crossings we can
20127 // lower it into pshufb.
20128 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
20129 (SVT.is256BitVector() && Subtarget->hasInt256())) {
20130 bool isLegal = true;
20131 for (unsigned I = 0, E = M.size(); I != E; ++I) {
20132 if (M[I] >= (int)SVT.getVectorNumElements() ||
20133 ShuffleCrosses128bitLane(SVT, I, M[I])) {
20142 // FIXME: blends, shifts.
20143 return (SVT.getVectorNumElements() == 2 ||
20144 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
20145 isMOVLMask(M, SVT) ||
20146 isCommutedMOVLMask(M, SVT) ||
20147 isMOVHLPSMask(M, SVT) ||
20148 isSHUFPMask(M, SVT) ||
20149 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20150 isPSHUFDMask(M, SVT) ||
20151 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20152 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20153 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20154 isPALIGNRMask(M, SVT, Subtarget) ||
20155 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20156 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20157 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20158 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20159 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20160 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20164 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20166 if (!VT.isSimple())
20169 MVT SVT = VT.getSimpleVT();
20170 unsigned NumElts = SVT.getVectorNumElements();
20171 // FIXME: This collection of masks seems suspect.
20174 if (NumElts == 4 && SVT.is128BitVector()) {
20175 return (isMOVLMask(Mask, SVT) ||
20176 isCommutedMOVLMask(Mask, SVT, true) ||
20177 isSHUFPMask(Mask, SVT) ||
20178 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20179 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20180 Subtarget->hasInt256()));
20185 //===----------------------------------------------------------------------===//
20186 // X86 Scheduler Hooks
20187 //===----------------------------------------------------------------------===//
20189 /// Utility function to emit xbegin specifying the start of an RTM region.
20190 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20191 const TargetInstrInfo *TII) {
20192 DebugLoc DL = MI->getDebugLoc();
20194 const BasicBlock *BB = MBB->getBasicBlock();
20195 MachineFunction::iterator I = MBB;
20198 // For the v = xbegin(), we generate
20209 MachineBasicBlock *thisMBB = MBB;
20210 MachineFunction *MF = MBB->getParent();
20211 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20212 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20213 MF->insert(I, mainMBB);
20214 MF->insert(I, sinkMBB);
20216 // Transfer the remainder of BB and its successor edges to sinkMBB.
20217 sinkMBB->splice(sinkMBB->begin(), MBB,
20218 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20219 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20223 // # fallthrough to mainMBB
20224 // # abortion to sinkMBB
20225 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20226 thisMBB->addSuccessor(mainMBB);
20227 thisMBB->addSuccessor(sinkMBB);
20231 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20232 mainMBB->addSuccessor(sinkMBB);
20235 // EAX is live into the sinkMBB
20236 sinkMBB->addLiveIn(X86::EAX);
20237 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20238 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20241 MI->eraseFromParent();
20245 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20246 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20247 // in the .td file.
20248 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20249 const TargetInstrInfo *TII) {
20251 switch (MI->getOpcode()) {
20252 default: llvm_unreachable("illegal opcode!");
20253 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20254 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20255 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20256 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20257 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20258 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20259 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20260 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20263 DebugLoc dl = MI->getDebugLoc();
20264 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20266 unsigned NumArgs = MI->getNumOperands();
20267 for (unsigned i = 1; i < NumArgs; ++i) {
20268 MachineOperand &Op = MI->getOperand(i);
20269 if (!(Op.isReg() && Op.isImplicit()))
20270 MIB.addOperand(Op);
20272 if (MI->hasOneMemOperand())
20273 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20275 BuildMI(*BB, MI, dl,
20276 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20277 .addReg(X86::XMM0);
20279 MI->eraseFromParent();
20283 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20284 // defs in an instruction pattern
20285 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20286 const TargetInstrInfo *TII) {
20288 switch (MI->getOpcode()) {
20289 default: llvm_unreachable("illegal opcode!");
20290 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20291 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20292 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20293 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20294 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20295 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20296 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20297 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20300 DebugLoc dl = MI->getDebugLoc();
20301 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20303 unsigned NumArgs = MI->getNumOperands(); // remove the results
20304 for (unsigned i = 1; i < NumArgs; ++i) {
20305 MachineOperand &Op = MI->getOperand(i);
20306 if (!(Op.isReg() && Op.isImplicit()))
20307 MIB.addOperand(Op);
20309 if (MI->hasOneMemOperand())
20310 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20312 BuildMI(*BB, MI, dl,
20313 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20316 MI->eraseFromParent();
20320 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20321 const TargetInstrInfo *TII,
20322 const X86Subtarget* Subtarget) {
20323 DebugLoc dl = MI->getDebugLoc();
20325 // Address into RAX/EAX, other two args into ECX, EDX.
20326 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20327 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20328 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20329 for (int i = 0; i < X86::AddrNumOperands; ++i)
20330 MIB.addOperand(MI->getOperand(i));
20332 unsigned ValOps = X86::AddrNumOperands;
20333 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20334 .addReg(MI->getOperand(ValOps).getReg());
20335 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20336 .addReg(MI->getOperand(ValOps+1).getReg());
20338 // The instruction doesn't actually take any operands though.
20339 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20341 MI->eraseFromParent(); // The pseudo is gone now.
20345 MachineBasicBlock *
20346 X86TargetLowering::EmitVAARG64WithCustomInserter(
20348 MachineBasicBlock *MBB) const {
20349 // Emit va_arg instruction on X86-64.
20351 // Operands to this pseudo-instruction:
20352 // 0 ) Output : destination address (reg)
20353 // 1-5) Input : va_list address (addr, i64mem)
20354 // 6 ) ArgSize : Size (in bytes) of vararg type
20355 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20356 // 8 ) Align : Alignment of type
20357 // 9 ) EFLAGS (implicit-def)
20359 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20360 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20362 unsigned DestReg = MI->getOperand(0).getReg();
20363 MachineOperand &Base = MI->getOperand(1);
20364 MachineOperand &Scale = MI->getOperand(2);
20365 MachineOperand &Index = MI->getOperand(3);
20366 MachineOperand &Disp = MI->getOperand(4);
20367 MachineOperand &Segment = MI->getOperand(5);
20368 unsigned ArgSize = MI->getOperand(6).getImm();
20369 unsigned ArgMode = MI->getOperand(7).getImm();
20370 unsigned Align = MI->getOperand(8).getImm();
20372 // Memory Reference
20373 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20374 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20375 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20377 // Machine Information
20378 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20379 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20380 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20381 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20382 DebugLoc DL = MI->getDebugLoc();
20384 // struct va_list {
20387 // i64 overflow_area (address)
20388 // i64 reg_save_area (address)
20390 // sizeof(va_list) = 24
20391 // alignment(va_list) = 8
20393 unsigned TotalNumIntRegs = 6;
20394 unsigned TotalNumXMMRegs = 8;
20395 bool UseGPOffset = (ArgMode == 1);
20396 bool UseFPOffset = (ArgMode == 2);
20397 unsigned MaxOffset = TotalNumIntRegs * 8 +
20398 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20400 /* Align ArgSize to a multiple of 8 */
20401 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20402 bool NeedsAlign = (Align > 8);
20404 MachineBasicBlock *thisMBB = MBB;
20405 MachineBasicBlock *overflowMBB;
20406 MachineBasicBlock *offsetMBB;
20407 MachineBasicBlock *endMBB;
20409 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20410 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20411 unsigned OffsetReg = 0;
20413 if (!UseGPOffset && !UseFPOffset) {
20414 // If we only pull from the overflow region, we don't create a branch.
20415 // We don't need to alter control flow.
20416 OffsetDestReg = 0; // unused
20417 OverflowDestReg = DestReg;
20419 offsetMBB = nullptr;
20420 overflowMBB = thisMBB;
20423 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20424 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20425 // If not, pull from overflow_area. (branch to overflowMBB)
20430 // offsetMBB overflowMBB
20435 // Registers for the PHI in endMBB
20436 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20437 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20439 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20440 MachineFunction *MF = MBB->getParent();
20441 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20442 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20443 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20445 MachineFunction::iterator MBBIter = MBB;
20448 // Insert the new basic blocks
20449 MF->insert(MBBIter, offsetMBB);
20450 MF->insert(MBBIter, overflowMBB);
20451 MF->insert(MBBIter, endMBB);
20453 // Transfer the remainder of MBB and its successor edges to endMBB.
20454 endMBB->splice(endMBB->begin(), thisMBB,
20455 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20456 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20458 // Make offsetMBB and overflowMBB successors of thisMBB
20459 thisMBB->addSuccessor(offsetMBB);
20460 thisMBB->addSuccessor(overflowMBB);
20462 // endMBB is a successor of both offsetMBB and overflowMBB
20463 offsetMBB->addSuccessor(endMBB);
20464 overflowMBB->addSuccessor(endMBB);
20466 // Load the offset value into a register
20467 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20468 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20472 .addDisp(Disp, UseFPOffset ? 4 : 0)
20473 .addOperand(Segment)
20474 .setMemRefs(MMOBegin, MMOEnd);
20476 // Check if there is enough room left to pull this argument.
20477 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20479 .addImm(MaxOffset + 8 - ArgSizeA8);
20481 // Branch to "overflowMBB" if offset >= max
20482 // Fall through to "offsetMBB" otherwise
20483 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20484 .addMBB(overflowMBB);
20487 // In offsetMBB, emit code to use the reg_save_area.
20489 assert(OffsetReg != 0);
20491 // Read the reg_save_area address.
20492 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20493 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20498 .addOperand(Segment)
20499 .setMemRefs(MMOBegin, MMOEnd);
20501 // Zero-extend the offset
20502 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20503 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20506 .addImm(X86::sub_32bit);
20508 // Add the offset to the reg_save_area to get the final address.
20509 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20510 .addReg(OffsetReg64)
20511 .addReg(RegSaveReg);
20513 // Compute the offset for the next argument
20514 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20515 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20517 .addImm(UseFPOffset ? 16 : 8);
20519 // Store it back into the va_list.
20520 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20524 .addDisp(Disp, UseFPOffset ? 4 : 0)
20525 .addOperand(Segment)
20526 .addReg(NextOffsetReg)
20527 .setMemRefs(MMOBegin, MMOEnd);
20530 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20535 // Emit code to use overflow area
20538 // Load the overflow_area address into a register.
20539 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20540 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20545 .addOperand(Segment)
20546 .setMemRefs(MMOBegin, MMOEnd);
20548 // If we need to align it, do so. Otherwise, just copy the address
20549 // to OverflowDestReg.
20551 // Align the overflow address
20552 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20553 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20555 // aligned_addr = (addr + (align-1)) & ~(align-1)
20556 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20557 .addReg(OverflowAddrReg)
20560 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20562 .addImm(~(uint64_t)(Align-1));
20564 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20565 .addReg(OverflowAddrReg);
20568 // Compute the next overflow address after this argument.
20569 // (the overflow address should be kept 8-byte aligned)
20570 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20571 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20572 .addReg(OverflowDestReg)
20573 .addImm(ArgSizeA8);
20575 // Store the new overflow address.
20576 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20581 .addOperand(Segment)
20582 .addReg(NextAddrReg)
20583 .setMemRefs(MMOBegin, MMOEnd);
20585 // If we branched, emit the PHI to the front of endMBB.
20587 BuildMI(*endMBB, endMBB->begin(), DL,
20588 TII->get(X86::PHI), DestReg)
20589 .addReg(OffsetDestReg).addMBB(offsetMBB)
20590 .addReg(OverflowDestReg).addMBB(overflowMBB);
20593 // Erase the pseudo instruction
20594 MI->eraseFromParent();
20599 MachineBasicBlock *
20600 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20602 MachineBasicBlock *MBB) const {
20603 // Emit code to save XMM registers to the stack. The ABI says that the
20604 // number of registers to save is given in %al, so it's theoretically
20605 // possible to do an indirect jump trick to avoid saving all of them,
20606 // however this code takes a simpler approach and just executes all
20607 // of the stores if %al is non-zero. It's less code, and it's probably
20608 // easier on the hardware branch predictor, and stores aren't all that
20609 // expensive anyway.
20611 // Create the new basic blocks. One block contains all the XMM stores,
20612 // and one block is the final destination regardless of whether any
20613 // stores were performed.
20614 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20615 MachineFunction *F = MBB->getParent();
20616 MachineFunction::iterator MBBIter = MBB;
20618 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20619 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20620 F->insert(MBBIter, XMMSaveMBB);
20621 F->insert(MBBIter, EndMBB);
20623 // Transfer the remainder of MBB and its successor edges to EndMBB.
20624 EndMBB->splice(EndMBB->begin(), MBB,
20625 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20626 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20628 // The original block will now fall through to the XMM save block.
20629 MBB->addSuccessor(XMMSaveMBB);
20630 // The XMMSaveMBB will fall through to the end block.
20631 XMMSaveMBB->addSuccessor(EndMBB);
20633 // Now add the instructions.
20634 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20635 DebugLoc DL = MI->getDebugLoc();
20637 unsigned CountReg = MI->getOperand(0).getReg();
20638 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20639 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20641 if (!Subtarget->isTargetWin64()) {
20642 // If %al is 0, branch around the XMM save block.
20643 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20644 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20645 MBB->addSuccessor(EndMBB);
20648 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20649 // that was just emitted, but clearly shouldn't be "saved".
20650 assert((MI->getNumOperands() <= 3 ||
20651 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20652 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20653 && "Expected last argument to be EFLAGS");
20654 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20655 // In the XMM save block, save all the XMM argument registers.
20656 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20657 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20658 MachineMemOperand *MMO =
20659 F->getMachineMemOperand(
20660 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20661 MachineMemOperand::MOStore,
20662 /*Size=*/16, /*Align=*/16);
20663 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20664 .addFrameIndex(RegSaveFrameIndex)
20665 .addImm(/*Scale=*/1)
20666 .addReg(/*IndexReg=*/0)
20667 .addImm(/*Disp=*/Offset)
20668 .addReg(/*Segment=*/0)
20669 .addReg(MI->getOperand(i).getReg())
20670 .addMemOperand(MMO);
20673 MI->eraseFromParent(); // The pseudo instruction is gone now.
20678 // The EFLAGS operand of SelectItr might be missing a kill marker
20679 // because there were multiple uses of EFLAGS, and ISel didn't know
20680 // which to mark. Figure out whether SelectItr should have had a
20681 // kill marker, and set it if it should. Returns the correct kill
20683 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20684 MachineBasicBlock* BB,
20685 const TargetRegisterInfo* TRI) {
20686 // Scan forward through BB for a use/def of EFLAGS.
20687 MachineBasicBlock::iterator miI(std::next(SelectItr));
20688 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20689 const MachineInstr& mi = *miI;
20690 if (mi.readsRegister(X86::EFLAGS))
20692 if (mi.definesRegister(X86::EFLAGS))
20693 break; // Should have kill-flag - update below.
20696 // If we hit the end of the block, check whether EFLAGS is live into a
20698 if (miI == BB->end()) {
20699 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20700 sEnd = BB->succ_end();
20701 sItr != sEnd; ++sItr) {
20702 MachineBasicBlock* succ = *sItr;
20703 if (succ->isLiveIn(X86::EFLAGS))
20708 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20709 // out. SelectMI should have a kill flag on EFLAGS.
20710 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20714 MachineBasicBlock *
20715 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20716 MachineBasicBlock *BB) const {
20717 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20718 DebugLoc DL = MI->getDebugLoc();
20720 // To "insert" a SELECT_CC instruction, we actually have to insert the
20721 // diamond control-flow pattern. The incoming instruction knows the
20722 // destination vreg to set, the condition code register to branch on, the
20723 // true/false values to select between, and a branch opcode to use.
20724 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20725 MachineFunction::iterator It = BB;
20731 // cmpTY ccX, r1, r2
20733 // fallthrough --> copy0MBB
20734 MachineBasicBlock *thisMBB = BB;
20735 MachineFunction *F = BB->getParent();
20736 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20737 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20738 F->insert(It, copy0MBB);
20739 F->insert(It, sinkMBB);
20741 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20742 // live into the sink and copy blocks.
20743 const TargetRegisterInfo *TRI =
20744 BB->getParent()->getSubtarget().getRegisterInfo();
20745 if (!MI->killsRegister(X86::EFLAGS) &&
20746 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20747 copy0MBB->addLiveIn(X86::EFLAGS);
20748 sinkMBB->addLiveIn(X86::EFLAGS);
20751 // Transfer the remainder of BB and its successor edges to sinkMBB.
20752 sinkMBB->splice(sinkMBB->begin(), BB,
20753 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20754 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20756 // Add the true and fallthrough blocks as its successors.
20757 BB->addSuccessor(copy0MBB);
20758 BB->addSuccessor(sinkMBB);
20760 // Create the conditional branch instruction.
20762 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20763 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20766 // %FalseValue = ...
20767 // # fallthrough to sinkMBB
20768 copy0MBB->addSuccessor(sinkMBB);
20771 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20773 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20774 TII->get(X86::PHI), MI->getOperand(0).getReg())
20775 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20776 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20778 MI->eraseFromParent(); // The pseudo instruction is gone now.
20782 MachineBasicBlock *
20783 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20784 MachineBasicBlock *BB) const {
20785 MachineFunction *MF = BB->getParent();
20786 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20787 DebugLoc DL = MI->getDebugLoc();
20788 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20790 assert(MF->shouldSplitStack());
20792 const bool Is64Bit = Subtarget->is64Bit();
20793 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20795 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20796 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20799 // ... [Till the alloca]
20800 // If stacklet is not large enough, jump to mallocMBB
20803 // Allocate by subtracting from RSP
20804 // Jump to continueMBB
20807 // Allocate by call to runtime
20811 // [rest of original BB]
20814 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20815 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20816 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20818 MachineRegisterInfo &MRI = MF->getRegInfo();
20819 const TargetRegisterClass *AddrRegClass =
20820 getRegClassFor(getPointerTy());
20822 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20823 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20824 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20825 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20826 sizeVReg = MI->getOperand(1).getReg(),
20827 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20829 MachineFunction::iterator MBBIter = BB;
20832 MF->insert(MBBIter, bumpMBB);
20833 MF->insert(MBBIter, mallocMBB);
20834 MF->insert(MBBIter, continueMBB);
20836 continueMBB->splice(continueMBB->begin(), BB,
20837 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20838 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20840 // Add code to the main basic block to check if the stack limit has been hit,
20841 // and if so, jump to mallocMBB otherwise to bumpMBB.
20842 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20843 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20844 .addReg(tmpSPVReg).addReg(sizeVReg);
20845 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20846 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20847 .addReg(SPLimitVReg);
20848 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
20850 // bumpMBB simply decreases the stack pointer, since we know the current
20851 // stacklet has enough space.
20852 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20853 .addReg(SPLimitVReg);
20854 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20855 .addReg(SPLimitVReg);
20856 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20858 // Calls into a routine in libgcc to allocate more space from the heap.
20859 const uint32_t *RegMask = MF->getTarget()
20860 .getSubtargetImpl()
20861 ->getRegisterInfo()
20862 ->getCallPreservedMask(CallingConv::C);
20864 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20866 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20867 .addExternalSymbol("__morestack_allocate_stack_space")
20868 .addRegMask(RegMask)
20869 .addReg(X86::RDI, RegState::Implicit)
20870 .addReg(X86::RAX, RegState::ImplicitDefine);
20871 } else if (Is64Bit) {
20872 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20874 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20875 .addExternalSymbol("__morestack_allocate_stack_space")
20876 .addRegMask(RegMask)
20877 .addReg(X86::EDI, RegState::Implicit)
20878 .addReg(X86::EAX, RegState::ImplicitDefine);
20880 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20882 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20883 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20884 .addExternalSymbol("__morestack_allocate_stack_space")
20885 .addRegMask(RegMask)
20886 .addReg(X86::EAX, RegState::ImplicitDefine);
20890 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20893 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20894 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20895 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20897 // Set up the CFG correctly.
20898 BB->addSuccessor(bumpMBB);
20899 BB->addSuccessor(mallocMBB);
20900 mallocMBB->addSuccessor(continueMBB);
20901 bumpMBB->addSuccessor(continueMBB);
20903 // Take care of the PHI nodes.
20904 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20905 MI->getOperand(0).getReg())
20906 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20907 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20909 // Delete the original pseudo instruction.
20910 MI->eraseFromParent();
20913 return continueMBB;
20916 MachineBasicBlock *
20917 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20918 MachineBasicBlock *BB) const {
20919 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20920 DebugLoc DL = MI->getDebugLoc();
20922 assert(!Subtarget->isTargetMachO());
20924 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20925 // non-trivial part is impdef of ESP.
20927 if (Subtarget->isTargetWin64()) {
20928 if (Subtarget->isTargetCygMing()) {
20929 // ___chkstk(Mingw64):
20930 // Clobbers R10, R11, RAX and EFLAGS.
20932 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20933 .addExternalSymbol("___chkstk")
20934 .addReg(X86::RAX, RegState::Implicit)
20935 .addReg(X86::RSP, RegState::Implicit)
20936 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20937 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20938 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20940 // __chkstk(MSVCRT): does not update stack pointer.
20941 // Clobbers R10, R11 and EFLAGS.
20942 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20943 .addExternalSymbol("__chkstk")
20944 .addReg(X86::RAX, RegState::Implicit)
20945 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20946 // RAX has the offset to be subtracted from RSP.
20947 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20952 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20953 Subtarget->isTargetWindowsItanium())
20957 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20958 .addExternalSymbol(StackProbeSymbol)
20959 .addReg(X86::EAX, RegState::Implicit)
20960 .addReg(X86::ESP, RegState::Implicit)
20961 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20962 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20963 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20966 MI->eraseFromParent(); // The pseudo instruction is gone now.
20970 MachineBasicBlock *
20971 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20972 MachineBasicBlock *BB) const {
20973 // This is pretty easy. We're taking the value that we received from
20974 // our load from the relocation, sticking it in either RDI (x86-64)
20975 // or EAX and doing an indirect call. The return value will then
20976 // be in the normal return register.
20977 MachineFunction *F = BB->getParent();
20978 const X86InstrInfo *TII =
20979 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20980 DebugLoc DL = MI->getDebugLoc();
20982 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20983 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20985 // Get a register mask for the lowered call.
20986 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20987 // proper register mask.
20988 const uint32_t *RegMask = F->getTarget()
20989 .getSubtargetImpl()
20990 ->getRegisterInfo()
20991 ->getCallPreservedMask(CallingConv::C);
20992 if (Subtarget->is64Bit()) {
20993 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20994 TII->get(X86::MOV64rm), X86::RDI)
20996 .addImm(0).addReg(0)
20997 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20998 MI->getOperand(3).getTargetFlags())
21000 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21001 addDirectMem(MIB, X86::RDI);
21002 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21003 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21004 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21005 TII->get(X86::MOV32rm), X86::EAX)
21007 .addImm(0).addReg(0)
21008 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21009 MI->getOperand(3).getTargetFlags())
21011 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21012 addDirectMem(MIB, X86::EAX);
21013 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21015 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21016 TII->get(X86::MOV32rm), X86::EAX)
21017 .addReg(TII->getGlobalBaseReg(F))
21018 .addImm(0).addReg(0)
21019 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21020 MI->getOperand(3).getTargetFlags())
21022 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21023 addDirectMem(MIB, X86::EAX);
21024 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21027 MI->eraseFromParent(); // The pseudo instruction is gone now.
21031 MachineBasicBlock *
21032 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21033 MachineBasicBlock *MBB) const {
21034 DebugLoc DL = MI->getDebugLoc();
21035 MachineFunction *MF = MBB->getParent();
21036 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21037 MachineRegisterInfo &MRI = MF->getRegInfo();
21039 const BasicBlock *BB = MBB->getBasicBlock();
21040 MachineFunction::iterator I = MBB;
21043 // Memory Reference
21044 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21045 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21048 unsigned MemOpndSlot = 0;
21050 unsigned CurOp = 0;
21052 DstReg = MI->getOperand(CurOp++).getReg();
21053 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21054 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21055 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21056 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21058 MemOpndSlot = CurOp;
21060 MVT PVT = getPointerTy();
21061 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21062 "Invalid Pointer Size!");
21064 // For v = setjmp(buf), we generate
21067 // buf[LabelOffset] = restoreMBB
21068 // SjLjSetup restoreMBB
21074 // v = phi(main, restore)
21077 // if base pointer being used, load it from frame
21080 MachineBasicBlock *thisMBB = MBB;
21081 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21082 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21083 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21084 MF->insert(I, mainMBB);
21085 MF->insert(I, sinkMBB);
21086 MF->push_back(restoreMBB);
21088 MachineInstrBuilder MIB;
21090 // Transfer the remainder of BB and its successor edges to sinkMBB.
21091 sinkMBB->splice(sinkMBB->begin(), MBB,
21092 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21093 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21096 unsigned PtrStoreOpc = 0;
21097 unsigned LabelReg = 0;
21098 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21099 Reloc::Model RM = MF->getTarget().getRelocationModel();
21100 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21101 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21103 // Prepare IP either in reg or imm.
21104 if (!UseImmLabel) {
21105 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21106 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21107 LabelReg = MRI.createVirtualRegister(PtrRC);
21108 if (Subtarget->is64Bit()) {
21109 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21113 .addMBB(restoreMBB)
21116 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21117 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21118 .addReg(XII->getGlobalBaseReg(MF))
21121 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21125 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21127 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21128 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21129 if (i == X86::AddrDisp)
21130 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21132 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21135 MIB.addReg(LabelReg);
21137 MIB.addMBB(restoreMBB);
21138 MIB.setMemRefs(MMOBegin, MMOEnd);
21140 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21141 .addMBB(restoreMBB);
21143 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21144 MF->getSubtarget().getRegisterInfo());
21145 MIB.addRegMask(RegInfo->getNoPreservedMask());
21146 thisMBB->addSuccessor(mainMBB);
21147 thisMBB->addSuccessor(restoreMBB);
21151 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21152 mainMBB->addSuccessor(sinkMBB);
21155 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21156 TII->get(X86::PHI), DstReg)
21157 .addReg(mainDstReg).addMBB(mainMBB)
21158 .addReg(restoreDstReg).addMBB(restoreMBB);
21161 if (RegInfo->hasBasePointer(*MF)) {
21162 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21163 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21164 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21165 X86FI->setRestoreBasePointer(MF);
21166 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21167 unsigned BasePtr = RegInfo->getBaseRegister();
21168 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21169 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21170 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21171 .setMIFlag(MachineInstr::FrameSetup);
21173 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21174 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21175 restoreMBB->addSuccessor(sinkMBB);
21177 MI->eraseFromParent();
21181 MachineBasicBlock *
21182 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21183 MachineBasicBlock *MBB) const {
21184 DebugLoc DL = MI->getDebugLoc();
21185 MachineFunction *MF = MBB->getParent();
21186 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21187 MachineRegisterInfo &MRI = MF->getRegInfo();
21189 // Memory Reference
21190 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21191 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21193 MVT PVT = getPointerTy();
21194 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21195 "Invalid Pointer Size!");
21197 const TargetRegisterClass *RC =
21198 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21199 unsigned Tmp = MRI.createVirtualRegister(RC);
21200 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21201 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21202 MF->getSubtarget().getRegisterInfo());
21203 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21204 unsigned SP = RegInfo->getStackRegister();
21206 MachineInstrBuilder MIB;
21208 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21209 const int64_t SPOffset = 2 * PVT.getStoreSize();
21211 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21212 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21215 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21216 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21217 MIB.addOperand(MI->getOperand(i));
21218 MIB.setMemRefs(MMOBegin, MMOEnd);
21220 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21221 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21222 if (i == X86::AddrDisp)
21223 MIB.addDisp(MI->getOperand(i), LabelOffset);
21225 MIB.addOperand(MI->getOperand(i));
21227 MIB.setMemRefs(MMOBegin, MMOEnd);
21229 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21230 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21231 if (i == X86::AddrDisp)
21232 MIB.addDisp(MI->getOperand(i), SPOffset);
21234 MIB.addOperand(MI->getOperand(i));
21236 MIB.setMemRefs(MMOBegin, MMOEnd);
21238 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21240 MI->eraseFromParent();
21244 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21245 // accumulator loops. Writing back to the accumulator allows the coalescer
21246 // to remove extra copies in the loop.
21247 MachineBasicBlock *
21248 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21249 MachineBasicBlock *MBB) const {
21250 MachineOperand &AddendOp = MI->getOperand(3);
21252 // Bail out early if the addend isn't a register - we can't switch these.
21253 if (!AddendOp.isReg())
21256 MachineFunction &MF = *MBB->getParent();
21257 MachineRegisterInfo &MRI = MF.getRegInfo();
21259 // Check whether the addend is defined by a PHI:
21260 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21261 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21262 if (!AddendDef.isPHI())
21265 // Look for the following pattern:
21267 // %addend = phi [%entry, 0], [%loop, %result]
21269 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21273 // %addend = phi [%entry, 0], [%loop, %result]
21275 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21277 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21278 assert(AddendDef.getOperand(i).isReg());
21279 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21280 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21281 if (&PHISrcInst == MI) {
21282 // Found a matching instruction.
21283 unsigned NewFMAOpc = 0;
21284 switch (MI->getOpcode()) {
21285 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21286 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21287 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21288 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21289 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21290 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21291 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21292 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21293 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21294 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21295 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21296 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21297 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21298 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21299 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21300 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21301 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21302 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21303 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21304 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21306 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21307 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21308 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21309 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21310 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21311 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21312 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21313 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21314 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21315 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21316 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21317 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21318 default: llvm_unreachable("Unrecognized FMA variant.");
21321 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21322 MachineInstrBuilder MIB =
21323 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21324 .addOperand(MI->getOperand(0))
21325 .addOperand(MI->getOperand(3))
21326 .addOperand(MI->getOperand(2))
21327 .addOperand(MI->getOperand(1));
21328 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21329 MI->eraseFromParent();
21336 MachineBasicBlock *
21337 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21338 MachineBasicBlock *BB) const {
21339 switch (MI->getOpcode()) {
21340 default: llvm_unreachable("Unexpected instr type to insert");
21341 case X86::TAILJMPd64:
21342 case X86::TAILJMPr64:
21343 case X86::TAILJMPm64:
21344 llvm_unreachable("TAILJMP64 would not be touched here.");
21345 case X86::TCRETURNdi64:
21346 case X86::TCRETURNri64:
21347 case X86::TCRETURNmi64:
21349 case X86::WIN_ALLOCA:
21350 return EmitLoweredWinAlloca(MI, BB);
21351 case X86::SEG_ALLOCA_32:
21352 case X86::SEG_ALLOCA_64:
21353 return EmitLoweredSegAlloca(MI, BB);
21354 case X86::TLSCall_32:
21355 case X86::TLSCall_64:
21356 return EmitLoweredTLSCall(MI, BB);
21357 case X86::CMOV_GR8:
21358 case X86::CMOV_FR32:
21359 case X86::CMOV_FR64:
21360 case X86::CMOV_V4F32:
21361 case X86::CMOV_V2F64:
21362 case X86::CMOV_V2I64:
21363 case X86::CMOV_V8F32:
21364 case X86::CMOV_V4F64:
21365 case X86::CMOV_V4I64:
21366 case X86::CMOV_V16F32:
21367 case X86::CMOV_V8F64:
21368 case X86::CMOV_V8I64:
21369 case X86::CMOV_GR16:
21370 case X86::CMOV_GR32:
21371 case X86::CMOV_RFP32:
21372 case X86::CMOV_RFP64:
21373 case X86::CMOV_RFP80:
21374 return EmitLoweredSelect(MI, BB);
21376 case X86::FP32_TO_INT16_IN_MEM:
21377 case X86::FP32_TO_INT32_IN_MEM:
21378 case X86::FP32_TO_INT64_IN_MEM:
21379 case X86::FP64_TO_INT16_IN_MEM:
21380 case X86::FP64_TO_INT32_IN_MEM:
21381 case X86::FP64_TO_INT64_IN_MEM:
21382 case X86::FP80_TO_INT16_IN_MEM:
21383 case X86::FP80_TO_INT32_IN_MEM:
21384 case X86::FP80_TO_INT64_IN_MEM: {
21385 MachineFunction *F = BB->getParent();
21386 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21387 DebugLoc DL = MI->getDebugLoc();
21389 // Change the floating point control register to use "round towards zero"
21390 // mode when truncating to an integer value.
21391 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21392 addFrameReference(BuildMI(*BB, MI, DL,
21393 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21395 // Load the old value of the high byte of the control word...
21397 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21398 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21401 // Set the high part to be round to zero...
21402 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21405 // Reload the modified control word now...
21406 addFrameReference(BuildMI(*BB, MI, DL,
21407 TII->get(X86::FLDCW16m)), CWFrameIdx);
21409 // Restore the memory image of control word to original value
21410 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21413 // Get the X86 opcode to use.
21415 switch (MI->getOpcode()) {
21416 default: llvm_unreachable("illegal opcode!");
21417 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21418 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21419 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21420 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21421 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21422 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21423 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21424 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21425 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21429 MachineOperand &Op = MI->getOperand(0);
21431 AM.BaseType = X86AddressMode::RegBase;
21432 AM.Base.Reg = Op.getReg();
21434 AM.BaseType = X86AddressMode::FrameIndexBase;
21435 AM.Base.FrameIndex = Op.getIndex();
21437 Op = MI->getOperand(1);
21439 AM.Scale = Op.getImm();
21440 Op = MI->getOperand(2);
21442 AM.IndexReg = Op.getImm();
21443 Op = MI->getOperand(3);
21444 if (Op.isGlobal()) {
21445 AM.GV = Op.getGlobal();
21447 AM.Disp = Op.getImm();
21449 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21450 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21452 // Reload the original control word now.
21453 addFrameReference(BuildMI(*BB, MI, DL,
21454 TII->get(X86::FLDCW16m)), CWFrameIdx);
21456 MI->eraseFromParent(); // The pseudo instruction is gone now.
21459 // String/text processing lowering.
21460 case X86::PCMPISTRM128REG:
21461 case X86::VPCMPISTRM128REG:
21462 case X86::PCMPISTRM128MEM:
21463 case X86::VPCMPISTRM128MEM:
21464 case X86::PCMPESTRM128REG:
21465 case X86::VPCMPESTRM128REG:
21466 case X86::PCMPESTRM128MEM:
21467 case X86::VPCMPESTRM128MEM:
21468 assert(Subtarget->hasSSE42() &&
21469 "Target must have SSE4.2 or AVX features enabled");
21470 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21472 // String/text processing lowering.
21473 case X86::PCMPISTRIREG:
21474 case X86::VPCMPISTRIREG:
21475 case X86::PCMPISTRIMEM:
21476 case X86::VPCMPISTRIMEM:
21477 case X86::PCMPESTRIREG:
21478 case X86::VPCMPESTRIREG:
21479 case X86::PCMPESTRIMEM:
21480 case X86::VPCMPESTRIMEM:
21481 assert(Subtarget->hasSSE42() &&
21482 "Target must have SSE4.2 or AVX features enabled");
21483 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21485 // Thread synchronization.
21487 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21492 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21494 case X86::VASTART_SAVE_XMM_REGS:
21495 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21497 case X86::VAARG_64:
21498 return EmitVAARG64WithCustomInserter(MI, BB);
21500 case X86::EH_SjLj_SetJmp32:
21501 case X86::EH_SjLj_SetJmp64:
21502 return emitEHSjLjSetJmp(MI, BB);
21504 case X86::EH_SjLj_LongJmp32:
21505 case X86::EH_SjLj_LongJmp64:
21506 return emitEHSjLjLongJmp(MI, BB);
21508 case TargetOpcode::STATEPOINT:
21509 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21510 // this point in the process. We diverge later.
21511 return emitPatchPoint(MI, BB);
21513 case TargetOpcode::STACKMAP:
21514 case TargetOpcode::PATCHPOINT:
21515 return emitPatchPoint(MI, BB);
21517 case X86::VFMADDPDr213r:
21518 case X86::VFMADDPSr213r:
21519 case X86::VFMADDSDr213r:
21520 case X86::VFMADDSSr213r:
21521 case X86::VFMSUBPDr213r:
21522 case X86::VFMSUBPSr213r:
21523 case X86::VFMSUBSDr213r:
21524 case X86::VFMSUBSSr213r:
21525 case X86::VFNMADDPDr213r:
21526 case X86::VFNMADDPSr213r:
21527 case X86::VFNMADDSDr213r:
21528 case X86::VFNMADDSSr213r:
21529 case X86::VFNMSUBPDr213r:
21530 case X86::VFNMSUBPSr213r:
21531 case X86::VFNMSUBSDr213r:
21532 case X86::VFNMSUBSSr213r:
21533 case X86::VFMADDSUBPDr213r:
21534 case X86::VFMADDSUBPSr213r:
21535 case X86::VFMSUBADDPDr213r:
21536 case X86::VFMSUBADDPSr213r:
21537 case X86::VFMADDPDr213rY:
21538 case X86::VFMADDPSr213rY:
21539 case X86::VFMSUBPDr213rY:
21540 case X86::VFMSUBPSr213rY:
21541 case X86::VFNMADDPDr213rY:
21542 case X86::VFNMADDPSr213rY:
21543 case X86::VFNMSUBPDr213rY:
21544 case X86::VFNMSUBPSr213rY:
21545 case X86::VFMADDSUBPDr213rY:
21546 case X86::VFMADDSUBPSr213rY:
21547 case X86::VFMSUBADDPDr213rY:
21548 case X86::VFMSUBADDPSr213rY:
21549 return emitFMA3Instr(MI, BB);
21553 //===----------------------------------------------------------------------===//
21554 // X86 Optimization Hooks
21555 //===----------------------------------------------------------------------===//
21557 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21560 const SelectionDAG &DAG,
21561 unsigned Depth) const {
21562 unsigned BitWidth = KnownZero.getBitWidth();
21563 unsigned Opc = Op.getOpcode();
21564 assert((Opc >= ISD::BUILTIN_OP_END ||
21565 Opc == ISD::INTRINSIC_WO_CHAIN ||
21566 Opc == ISD::INTRINSIC_W_CHAIN ||
21567 Opc == ISD::INTRINSIC_VOID) &&
21568 "Should use MaskedValueIsZero if you don't know whether Op"
21569 " is a target node!");
21571 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21585 // These nodes' second result is a boolean.
21586 if (Op.getResNo() == 0)
21589 case X86ISD::SETCC:
21590 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21592 case ISD::INTRINSIC_WO_CHAIN: {
21593 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21594 unsigned NumLoBits = 0;
21597 case Intrinsic::x86_sse_movmsk_ps:
21598 case Intrinsic::x86_avx_movmsk_ps_256:
21599 case Intrinsic::x86_sse2_movmsk_pd:
21600 case Intrinsic::x86_avx_movmsk_pd_256:
21601 case Intrinsic::x86_mmx_pmovmskb:
21602 case Intrinsic::x86_sse2_pmovmskb_128:
21603 case Intrinsic::x86_avx2_pmovmskb: {
21604 // High bits of movmskp{s|d}, pmovmskb are known zero.
21606 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21607 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21608 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21609 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21610 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21611 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21612 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21613 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21615 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21624 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21626 const SelectionDAG &,
21627 unsigned Depth) const {
21628 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21629 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21630 return Op.getValueType().getScalarType().getSizeInBits();
21636 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21637 /// node is a GlobalAddress + offset.
21638 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21639 const GlobalValue* &GA,
21640 int64_t &Offset) const {
21641 if (N->getOpcode() == X86ISD::Wrapper) {
21642 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21643 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21644 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21648 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21651 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21652 /// same as extracting the high 128-bit part of 256-bit vector and then
21653 /// inserting the result into the low part of a new 256-bit vector
21654 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21655 EVT VT = SVOp->getValueType(0);
21656 unsigned NumElems = VT.getVectorNumElements();
21658 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21659 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21660 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21661 SVOp->getMaskElt(j) >= 0)
21667 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21668 /// same as extracting the low 128-bit part of 256-bit vector and then
21669 /// inserting the result into the high part of a new 256-bit vector
21670 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21671 EVT VT = SVOp->getValueType(0);
21672 unsigned NumElems = VT.getVectorNumElements();
21674 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21675 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21676 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21677 SVOp->getMaskElt(j) >= 0)
21683 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21684 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21685 TargetLowering::DAGCombinerInfo &DCI,
21686 const X86Subtarget* Subtarget) {
21688 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21689 SDValue V1 = SVOp->getOperand(0);
21690 SDValue V2 = SVOp->getOperand(1);
21691 EVT VT = SVOp->getValueType(0);
21692 unsigned NumElems = VT.getVectorNumElements();
21694 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21695 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21699 // V UNDEF BUILD_VECTOR UNDEF
21701 // CONCAT_VECTOR CONCAT_VECTOR
21704 // RESULT: V + zero extended
21706 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21707 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21708 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21711 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21714 // To match the shuffle mask, the first half of the mask should
21715 // be exactly the first vector, and all the rest a splat with the
21716 // first element of the second one.
21717 for (unsigned i = 0; i != NumElems/2; ++i)
21718 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21719 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21722 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21723 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21724 if (Ld->hasNUsesOfValue(1, 0)) {
21725 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21726 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21728 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21730 Ld->getPointerInfo(),
21731 Ld->getAlignment(),
21732 false/*isVolatile*/, true/*ReadMem*/,
21733 false/*WriteMem*/);
21735 // Make sure the newly-created LOAD is in the same position as Ld in
21736 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21737 // and update uses of Ld's output chain to use the TokenFactor.
21738 if (Ld->hasAnyUseOfValue(1)) {
21739 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21740 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21741 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21742 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21743 SDValue(ResNode.getNode(), 1));
21746 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21750 // Emit a zeroed vector and insert the desired subvector on its
21752 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21753 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21754 return DCI.CombineTo(N, InsV);
21757 //===--------------------------------------------------------------------===//
21758 // Combine some shuffles into subvector extracts and inserts:
21761 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21762 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21763 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21764 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21765 return DCI.CombineTo(N, InsV);
21768 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21769 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21770 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21771 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21772 return DCI.CombineTo(N, InsV);
21778 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21781 /// This is the leaf of the recursive combinine below. When we have found some
21782 /// chain of single-use x86 shuffle instructions and accumulated the combined
21783 /// shuffle mask represented by them, this will try to pattern match that mask
21784 /// into either a single instruction if there is a special purpose instruction
21785 /// for this operation, or into a PSHUFB instruction which is a fully general
21786 /// instruction but should only be used to replace chains over a certain depth.
21787 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21788 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21789 TargetLowering::DAGCombinerInfo &DCI,
21790 const X86Subtarget *Subtarget) {
21791 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21793 // Find the operand that enters the chain. Note that multiple uses are OK
21794 // here, we're not going to remove the operand we find.
21795 SDValue Input = Op.getOperand(0);
21796 while (Input.getOpcode() == ISD::BITCAST)
21797 Input = Input.getOperand(0);
21799 MVT VT = Input.getSimpleValueType();
21800 MVT RootVT = Root.getSimpleValueType();
21803 // Just remove no-op shuffle masks.
21804 if (Mask.size() == 1) {
21805 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21810 // Use the float domain if the operand type is a floating point type.
21811 bool FloatDomain = VT.isFloatingPoint();
21813 // For floating point shuffles, we don't have free copies in the shuffle
21814 // instructions or the ability to load as part of the instruction, so
21815 // canonicalize their shuffles to UNPCK or MOV variants.
21817 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21818 // vectors because it can have a load folded into it that UNPCK cannot. This
21819 // doesn't preclude something switching to the shorter encoding post-RA.
21821 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21822 bool Lo = Mask.equals(0, 0);
21825 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21826 // is no slower than UNPCKLPD but has the option to fold the input operand
21827 // into even an unaligned memory load.
21828 if (Lo && Subtarget->hasSSE3()) {
21829 Shuffle = X86ISD::MOVDDUP;
21830 ShuffleVT = MVT::v2f64;
21832 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21833 // than the UNPCK variants.
21834 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21835 ShuffleVT = MVT::v4f32;
21837 if (Depth == 1 && Root->getOpcode() == Shuffle)
21838 return false; // Nothing to do!
21839 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21840 DCI.AddToWorklist(Op.getNode());
21841 if (Shuffle == X86ISD::MOVDDUP)
21842 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21844 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21845 DCI.AddToWorklist(Op.getNode());
21846 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21850 if (Subtarget->hasSSE3() &&
21851 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21852 bool Lo = Mask.equals(0, 0, 2, 2);
21853 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21854 MVT ShuffleVT = MVT::v4f32;
21855 if (Depth == 1 && Root->getOpcode() == Shuffle)
21856 return false; // Nothing to do!
21857 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21858 DCI.AddToWorklist(Op.getNode());
21859 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21860 DCI.AddToWorklist(Op.getNode());
21861 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21865 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21866 bool Lo = Mask.equals(0, 0, 1, 1);
21867 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21868 MVT ShuffleVT = MVT::v4f32;
21869 if (Depth == 1 && Root->getOpcode() == Shuffle)
21870 return false; // Nothing to do!
21871 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21872 DCI.AddToWorklist(Op.getNode());
21873 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21874 DCI.AddToWorklist(Op.getNode());
21875 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21881 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21882 // variants as none of these have single-instruction variants that are
21883 // superior to the UNPCK formulation.
21884 if (!FloatDomain &&
21885 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21886 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21887 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21888 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21890 bool Lo = Mask[0] == 0;
21891 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21892 if (Depth == 1 && Root->getOpcode() == Shuffle)
21893 return false; // Nothing to do!
21895 switch (Mask.size()) {
21897 ShuffleVT = MVT::v8i16;
21900 ShuffleVT = MVT::v16i8;
21903 llvm_unreachable("Impossible mask size!");
21905 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21906 DCI.AddToWorklist(Op.getNode());
21907 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21908 DCI.AddToWorklist(Op.getNode());
21909 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21914 // Don't try to re-form single instruction chains under any circumstances now
21915 // that we've done encoding canonicalization for them.
21919 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21920 // can replace them with a single PSHUFB instruction profitably. Intel's
21921 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21922 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21923 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21924 SmallVector<SDValue, 16> PSHUFBMask;
21925 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21926 int Ratio = 16 / Mask.size();
21927 for (unsigned i = 0; i < 16; ++i) {
21928 if (Mask[i / Ratio] == SM_SentinelUndef) {
21929 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21932 int M = Mask[i / Ratio] != SM_SentinelZero
21933 ? Ratio * Mask[i / Ratio] + i % Ratio
21935 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21937 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21938 DCI.AddToWorklist(Op.getNode());
21939 SDValue PSHUFBMaskOp =
21940 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21941 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21942 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21943 DCI.AddToWorklist(Op.getNode());
21944 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21949 // Failed to find any combines.
21953 /// \brief Fully generic combining of x86 shuffle instructions.
21955 /// This should be the last combine run over the x86 shuffle instructions. Once
21956 /// they have been fully optimized, this will recursively consider all chains
21957 /// of single-use shuffle instructions, build a generic model of the cumulative
21958 /// shuffle operation, and check for simpler instructions which implement this
21959 /// operation. We use this primarily for two purposes:
21961 /// 1) Collapse generic shuffles to specialized single instructions when
21962 /// equivalent. In most cases, this is just an encoding size win, but
21963 /// sometimes we will collapse multiple generic shuffles into a single
21964 /// special-purpose shuffle.
21965 /// 2) Look for sequences of shuffle instructions with 3 or more total
21966 /// instructions, and replace them with the slightly more expensive SSSE3
21967 /// PSHUFB instruction if available. We do this as the last combining step
21968 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21969 /// a suitable short sequence of other instructions. The PHUFB will either
21970 /// use a register or have to read from memory and so is slightly (but only
21971 /// slightly) more expensive than the other shuffle instructions.
21973 /// Because this is inherently a quadratic operation (for each shuffle in
21974 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21975 /// This should never be an issue in practice as the shuffle lowering doesn't
21976 /// produce sequences of more than 8 instructions.
21978 /// FIXME: We will currently miss some cases where the redundant shuffling
21979 /// would simplify under the threshold for PSHUFB formation because of
21980 /// combine-ordering. To fix this, we should do the redundant instruction
21981 /// combining in this recursive walk.
21982 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21983 ArrayRef<int> RootMask,
21984 int Depth, bool HasPSHUFB,
21986 TargetLowering::DAGCombinerInfo &DCI,
21987 const X86Subtarget *Subtarget) {
21988 // Bound the depth of our recursive combine because this is ultimately
21989 // quadratic in nature.
21993 // Directly rip through bitcasts to find the underlying operand.
21994 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21995 Op = Op.getOperand(0);
21997 MVT VT = Op.getSimpleValueType();
21998 if (!VT.isVector())
21999 return false; // Bail if we hit a non-vector.
22000 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
22001 // version should be added.
22002 if (VT.getSizeInBits() != 128)
22005 assert(Root.getSimpleValueType().isVector() &&
22006 "Shuffles operate on vector types!");
22007 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22008 "Can only combine shuffles of the same vector register size.");
22010 if (!isTargetShuffle(Op.getOpcode()))
22012 SmallVector<int, 16> OpMask;
22014 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22015 // We only can combine unary shuffles which we can decode the mask for.
22016 if (!HaveMask || !IsUnary)
22019 assert(VT.getVectorNumElements() == OpMask.size() &&
22020 "Different mask size from vector size!");
22021 assert(((RootMask.size() > OpMask.size() &&
22022 RootMask.size() % OpMask.size() == 0) ||
22023 (OpMask.size() > RootMask.size() &&
22024 OpMask.size() % RootMask.size() == 0) ||
22025 OpMask.size() == RootMask.size()) &&
22026 "The smaller number of elements must divide the larger.");
22027 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22028 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22029 assert(((RootRatio == 1 && OpRatio == 1) ||
22030 (RootRatio == 1) != (OpRatio == 1)) &&
22031 "Must not have a ratio for both incoming and op masks!");
22033 SmallVector<int, 16> Mask;
22034 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22036 // Merge this shuffle operation's mask into our accumulated mask. Note that
22037 // this shuffle's mask will be the first applied to the input, followed by the
22038 // root mask to get us all the way to the root value arrangement. The reason
22039 // for this order is that we are recursing up the operation chain.
22040 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22041 int RootIdx = i / RootRatio;
22042 if (RootMask[RootIdx] < 0) {
22043 // This is a zero or undef lane, we're done.
22044 Mask.push_back(RootMask[RootIdx]);
22048 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22049 int OpIdx = RootMaskedIdx / OpRatio;
22050 if (OpMask[OpIdx] < 0) {
22051 // The incoming lanes are zero or undef, it doesn't matter which ones we
22053 Mask.push_back(OpMask[OpIdx]);
22057 // Ok, we have non-zero lanes, map them through.
22058 Mask.push_back(OpMask[OpIdx] * OpRatio +
22059 RootMaskedIdx % OpRatio);
22062 // See if we can recurse into the operand to combine more things.
22063 switch (Op.getOpcode()) {
22064 case X86ISD::PSHUFB:
22066 case X86ISD::PSHUFD:
22067 case X86ISD::PSHUFHW:
22068 case X86ISD::PSHUFLW:
22069 if (Op.getOperand(0).hasOneUse() &&
22070 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22071 HasPSHUFB, DAG, DCI, Subtarget))
22075 case X86ISD::UNPCKL:
22076 case X86ISD::UNPCKH:
22077 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
22078 // We can't check for single use, we have to check that this shuffle is the only user.
22079 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22080 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22081 HasPSHUFB, DAG, DCI, Subtarget))
22086 // Minor canonicalization of the accumulated shuffle mask to make it easier
22087 // to match below. All this does is detect masks with squential pairs of
22088 // elements, and shrink them to the half-width mask. It does this in a loop
22089 // so it will reduce the size of the mask to the minimal width mask which
22090 // performs an equivalent shuffle.
22091 SmallVector<int, 16> WidenedMask;
22092 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22093 Mask = std::move(WidenedMask);
22094 WidenedMask.clear();
22097 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22101 /// \brief Get the PSHUF-style mask from PSHUF node.
22103 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22104 /// PSHUF-style masks that can be reused with such instructions.
22105 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22106 SmallVector<int, 4> Mask;
22108 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
22112 switch (N.getOpcode()) {
22113 case X86ISD::PSHUFD:
22115 case X86ISD::PSHUFLW:
22118 case X86ISD::PSHUFHW:
22119 Mask.erase(Mask.begin(), Mask.begin() + 4);
22120 for (int &M : Mask)
22124 llvm_unreachable("No valid shuffle instruction found!");
22128 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22130 /// We walk up the chain and look for a combinable shuffle, skipping over
22131 /// shuffles that we could hoist this shuffle's transformation past without
22132 /// altering anything.
22134 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22136 TargetLowering::DAGCombinerInfo &DCI) {
22137 assert(N.getOpcode() == X86ISD::PSHUFD &&
22138 "Called with something other than an x86 128-bit half shuffle!");
22141 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22142 // of the shuffles in the chain so that we can form a fresh chain to replace
22144 SmallVector<SDValue, 8> Chain;
22145 SDValue V = N.getOperand(0);
22146 for (; V.hasOneUse(); V = V.getOperand(0)) {
22147 switch (V.getOpcode()) {
22149 return SDValue(); // Nothing combined!
22152 // Skip bitcasts as we always know the type for the target specific
22156 case X86ISD::PSHUFD:
22157 // Found another dword shuffle.
22160 case X86ISD::PSHUFLW:
22161 // Check that the low words (being shuffled) are the identity in the
22162 // dword shuffle, and the high words are self-contained.
22163 if (Mask[0] != 0 || Mask[1] != 1 ||
22164 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22167 Chain.push_back(V);
22170 case X86ISD::PSHUFHW:
22171 // Check that the high words (being shuffled) are the identity in the
22172 // dword shuffle, and the low words are self-contained.
22173 if (Mask[2] != 2 || Mask[3] != 3 ||
22174 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22177 Chain.push_back(V);
22180 case X86ISD::UNPCKL:
22181 case X86ISD::UNPCKH:
22182 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22183 // shuffle into a preceding word shuffle.
22184 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22187 // Search for a half-shuffle which we can combine with.
22188 unsigned CombineOp =
22189 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22190 if (V.getOperand(0) != V.getOperand(1) ||
22191 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22193 Chain.push_back(V);
22194 V = V.getOperand(0);
22196 switch (V.getOpcode()) {
22198 return SDValue(); // Nothing to combine.
22200 case X86ISD::PSHUFLW:
22201 case X86ISD::PSHUFHW:
22202 if (V.getOpcode() == CombineOp)
22205 Chain.push_back(V);
22209 V = V.getOperand(0);
22213 } while (V.hasOneUse());
22216 // Break out of the loop if we break out of the switch.
22220 if (!V.hasOneUse())
22221 // We fell out of the loop without finding a viable combining instruction.
22224 // Merge this node's mask and our incoming mask.
22225 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22226 for (int &M : Mask)
22228 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22229 getV4X86ShuffleImm8ForMask(Mask, DAG));
22231 // Rebuild the chain around this new shuffle.
22232 while (!Chain.empty()) {
22233 SDValue W = Chain.pop_back_val();
22235 if (V.getValueType() != W.getOperand(0).getValueType())
22236 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22238 switch (W.getOpcode()) {
22240 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22242 case X86ISD::UNPCKL:
22243 case X86ISD::UNPCKH:
22244 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22247 case X86ISD::PSHUFD:
22248 case X86ISD::PSHUFLW:
22249 case X86ISD::PSHUFHW:
22250 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22254 if (V.getValueType() != N.getValueType())
22255 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22257 // Return the new chain to replace N.
22261 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22263 /// We walk up the chain, skipping shuffles of the other half and looking
22264 /// through shuffles which switch halves trying to find a shuffle of the same
22265 /// pair of dwords.
22266 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22268 TargetLowering::DAGCombinerInfo &DCI) {
22270 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22271 "Called with something other than an x86 128-bit half shuffle!");
22273 unsigned CombineOpcode = N.getOpcode();
22275 // Walk up a single-use chain looking for a combinable shuffle.
22276 SDValue V = N.getOperand(0);
22277 for (; V.hasOneUse(); V = V.getOperand(0)) {
22278 switch (V.getOpcode()) {
22280 return false; // Nothing combined!
22283 // Skip bitcasts as we always know the type for the target specific
22287 case X86ISD::PSHUFLW:
22288 case X86ISD::PSHUFHW:
22289 if (V.getOpcode() == CombineOpcode)
22292 // Other-half shuffles are no-ops.
22295 // Break out of the loop if we break out of the switch.
22299 if (!V.hasOneUse())
22300 // We fell out of the loop without finding a viable combining instruction.
22303 // Combine away the bottom node as its shuffle will be accumulated into
22304 // a preceding shuffle.
22305 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22307 // Record the old value.
22310 // Merge this node's mask and our incoming mask (adjusted to account for all
22311 // the pshufd instructions encountered).
22312 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22313 for (int &M : Mask)
22315 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22316 getV4X86ShuffleImm8ForMask(Mask, DAG));
22318 // Check that the shuffles didn't cancel each other out. If not, we need to
22319 // combine to the new one.
22321 // Replace the combinable shuffle with the combined one, updating all users
22322 // so that we re-evaluate the chain here.
22323 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22328 /// \brief Try to combine x86 target specific shuffles.
22329 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22330 TargetLowering::DAGCombinerInfo &DCI,
22331 const X86Subtarget *Subtarget) {
22333 MVT VT = N.getSimpleValueType();
22334 SmallVector<int, 4> Mask;
22336 switch (N.getOpcode()) {
22337 case X86ISD::PSHUFD:
22338 case X86ISD::PSHUFLW:
22339 case X86ISD::PSHUFHW:
22340 Mask = getPSHUFShuffleMask(N);
22341 assert(Mask.size() == 4);
22347 // Nuke no-op shuffles that show up after combining.
22348 if (isNoopShuffleMask(Mask))
22349 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22351 // Look for simplifications involving one or two shuffle instructions.
22352 SDValue V = N.getOperand(0);
22353 switch (N.getOpcode()) {
22356 case X86ISD::PSHUFLW:
22357 case X86ISD::PSHUFHW:
22358 assert(VT == MVT::v8i16);
22361 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22362 return SDValue(); // We combined away this shuffle, so we're done.
22364 // See if this reduces to a PSHUFD which is no more expensive and can
22365 // combine with more operations. Note that it has to at least flip the
22366 // dwords as otherwise it would have been removed as a no-op.
22367 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22368 int DMask[] = {0, 1, 2, 3};
22369 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22370 DMask[DOffset + 0] = DOffset + 1;
22371 DMask[DOffset + 1] = DOffset + 0;
22372 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22373 DCI.AddToWorklist(V.getNode());
22374 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22375 getV4X86ShuffleImm8ForMask(DMask, DAG));
22376 DCI.AddToWorklist(V.getNode());
22377 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22380 // Look for shuffle patterns which can be implemented as a single unpack.
22381 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22382 // only works when we have a PSHUFD followed by two half-shuffles.
22383 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22384 (V.getOpcode() == X86ISD::PSHUFLW ||
22385 V.getOpcode() == X86ISD::PSHUFHW) &&
22386 V.getOpcode() != N.getOpcode() &&
22388 SDValue D = V.getOperand(0);
22389 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22390 D = D.getOperand(0);
22391 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22392 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22393 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22394 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22395 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22397 for (int i = 0; i < 4; ++i) {
22398 WordMask[i + NOffset] = Mask[i] + NOffset;
22399 WordMask[i + VOffset] = VMask[i] + VOffset;
22401 // Map the word mask through the DWord mask.
22403 for (int i = 0; i < 8; ++i)
22404 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22405 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22406 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22407 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22408 std::begin(UnpackLoMask)) ||
22409 std::equal(std::begin(MappedMask), std::end(MappedMask),
22410 std::begin(UnpackHiMask))) {
22411 // We can replace all three shuffles with an unpack.
22412 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22413 DCI.AddToWorklist(V.getNode());
22414 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22416 DL, MVT::v8i16, V, V);
22423 case X86ISD::PSHUFD:
22424 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22433 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22435 /// We combine this directly on the abstract vector shuffle nodes so it is
22436 /// easier to generically match. We also insert dummy vector shuffle nodes for
22437 /// the operands which explicitly discard the lanes which are unused by this
22438 /// operation to try to flow through the rest of the combiner the fact that
22439 /// they're unused.
22440 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22442 EVT VT = N->getValueType(0);
22444 // We only handle target-independent shuffles.
22445 // FIXME: It would be easy and harmless to use the target shuffle mask
22446 // extraction tool to support more.
22447 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22450 auto *SVN = cast<ShuffleVectorSDNode>(N);
22451 ArrayRef<int> Mask = SVN->getMask();
22452 SDValue V1 = N->getOperand(0);
22453 SDValue V2 = N->getOperand(1);
22455 // We require the first shuffle operand to be the SUB node, and the second to
22456 // be the ADD node.
22457 // FIXME: We should support the commuted patterns.
22458 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22461 // If there are other uses of these operations we can't fold them.
22462 if (!V1->hasOneUse() || !V2->hasOneUse())
22465 // Ensure that both operations have the same operands. Note that we can
22466 // commute the FADD operands.
22467 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22468 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22469 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22472 // We're looking for blends between FADD and FSUB nodes. We insist on these
22473 // nodes being lined up in a specific expected pattern.
22474 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22475 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22476 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22479 // Only specific types are legal at this point, assert so we notice if and
22480 // when these change.
22481 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22482 VT == MVT::v4f64) &&
22483 "Unknown vector type encountered!");
22485 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22488 /// PerformShuffleCombine - Performs several different shuffle combines.
22489 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22490 TargetLowering::DAGCombinerInfo &DCI,
22491 const X86Subtarget *Subtarget) {
22493 SDValue N0 = N->getOperand(0);
22494 SDValue N1 = N->getOperand(1);
22495 EVT VT = N->getValueType(0);
22497 // Don't create instructions with illegal types after legalize types has run.
22498 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22499 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22502 // If we have legalized the vector types, look for blends of FADD and FSUB
22503 // nodes that we can fuse into an ADDSUB node.
22504 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22505 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22508 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22509 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22510 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22511 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22513 // During Type Legalization, when promoting illegal vector types,
22514 // the backend might introduce new shuffle dag nodes and bitcasts.
22516 // This code performs the following transformation:
22517 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22518 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22520 // We do this only if both the bitcast and the BINOP dag nodes have
22521 // one use. Also, perform this transformation only if the new binary
22522 // operation is legal. This is to avoid introducing dag nodes that
22523 // potentially need to be further expanded (or custom lowered) into a
22524 // less optimal sequence of dag nodes.
22525 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22526 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22527 N0.getOpcode() == ISD::BITCAST) {
22528 SDValue BC0 = N0.getOperand(0);
22529 EVT SVT = BC0.getValueType();
22530 unsigned Opcode = BC0.getOpcode();
22531 unsigned NumElts = VT.getVectorNumElements();
22533 if (BC0.hasOneUse() && SVT.isVector() &&
22534 SVT.getVectorNumElements() * 2 == NumElts &&
22535 TLI.isOperationLegal(Opcode, VT)) {
22536 bool CanFold = false;
22548 unsigned SVTNumElts = SVT.getVectorNumElements();
22549 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22550 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22551 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22552 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22553 CanFold = SVOp->getMaskElt(i) < 0;
22556 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22557 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22558 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22559 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22564 // Only handle 128 wide vector from here on.
22565 if (!VT.is128BitVector())
22568 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22569 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22570 // consecutive, non-overlapping, and in the right order.
22571 SmallVector<SDValue, 16> Elts;
22572 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22573 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22575 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22579 if (isTargetShuffle(N->getOpcode())) {
22581 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22582 if (Shuffle.getNode())
22585 // Try recursively combining arbitrary sequences of x86 shuffle
22586 // instructions into higher-order shuffles. We do this after combining
22587 // specific PSHUF instruction sequences into their minimal form so that we
22588 // can evaluate how many specialized shuffle instructions are involved in
22589 // a particular chain.
22590 SmallVector<int, 1> NonceMask; // Just a placeholder.
22591 NonceMask.push_back(0);
22592 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22593 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22595 return SDValue(); // This routine will use CombineTo to replace N.
22601 /// PerformTruncateCombine - Converts truncate operation to
22602 /// a sequence of vector shuffle operations.
22603 /// It is possible when we truncate 256-bit vector to 128-bit vector
22604 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22605 TargetLowering::DAGCombinerInfo &DCI,
22606 const X86Subtarget *Subtarget) {
22610 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22611 /// specific shuffle of a load can be folded into a single element load.
22612 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22613 /// shuffles have been custom lowered so we need to handle those here.
22614 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22615 TargetLowering::DAGCombinerInfo &DCI) {
22616 if (DCI.isBeforeLegalizeOps())
22619 SDValue InVec = N->getOperand(0);
22620 SDValue EltNo = N->getOperand(1);
22622 if (!isa<ConstantSDNode>(EltNo))
22625 EVT OriginalVT = InVec.getValueType();
22627 if (InVec.getOpcode() == ISD::BITCAST) {
22628 // Don't duplicate a load with other uses.
22629 if (!InVec.hasOneUse())
22631 EVT BCVT = InVec.getOperand(0).getValueType();
22632 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22634 InVec = InVec.getOperand(0);
22637 EVT CurrentVT = InVec.getValueType();
22639 if (!isTargetShuffle(InVec.getOpcode()))
22642 // Don't duplicate a load with other uses.
22643 if (!InVec.hasOneUse())
22646 SmallVector<int, 16> ShuffleMask;
22648 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22649 ShuffleMask, UnaryShuffle))
22652 // Select the input vector, guarding against out of range extract vector.
22653 unsigned NumElems = CurrentVT.getVectorNumElements();
22654 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22655 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22656 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22657 : InVec.getOperand(1);
22659 // If inputs to shuffle are the same for both ops, then allow 2 uses
22660 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22662 if (LdNode.getOpcode() == ISD::BITCAST) {
22663 // Don't duplicate a load with other uses.
22664 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22667 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22668 LdNode = LdNode.getOperand(0);
22671 if (!ISD::isNormalLoad(LdNode.getNode()))
22674 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22676 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22679 EVT EltVT = N->getValueType(0);
22680 // If there's a bitcast before the shuffle, check if the load type and
22681 // alignment is valid.
22682 unsigned Align = LN0->getAlignment();
22683 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22684 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22685 EltVT.getTypeForEVT(*DAG.getContext()));
22687 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22690 // All checks match so transform back to vector_shuffle so that DAG combiner
22691 // can finish the job
22694 // Create shuffle node taking into account the case that its a unary shuffle
22695 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22696 : InVec.getOperand(1);
22697 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22698 InVec.getOperand(0), Shuffle,
22700 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22701 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22705 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22706 /// generation and convert it from being a bunch of shuffles and extracts
22707 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22708 /// storing the value and loading scalars back, while for x64 we should
22709 /// use 64-bit extracts and shifts.
22710 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22711 TargetLowering::DAGCombinerInfo &DCI) {
22712 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22713 if (NewOp.getNode())
22716 SDValue InputVector = N->getOperand(0);
22718 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22719 // from mmx to v2i32 has a single usage.
22720 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22721 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22722 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22723 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22724 N->getValueType(0),
22725 InputVector.getNode()->getOperand(0));
22727 // Only operate on vectors of 4 elements, where the alternative shuffling
22728 // gets to be more expensive.
22729 if (InputVector.getValueType() != MVT::v4i32)
22732 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22733 // single use which is a sign-extend or zero-extend, and all elements are
22735 SmallVector<SDNode *, 4> Uses;
22736 unsigned ExtractedElements = 0;
22737 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22738 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22739 if (UI.getUse().getResNo() != InputVector.getResNo())
22742 SDNode *Extract = *UI;
22743 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22746 if (Extract->getValueType(0) != MVT::i32)
22748 if (!Extract->hasOneUse())
22750 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22751 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22753 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22756 // Record which element was extracted.
22757 ExtractedElements |=
22758 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22760 Uses.push_back(Extract);
22763 // If not all the elements were used, this may not be worthwhile.
22764 if (ExtractedElements != 15)
22767 // Ok, we've now decided to do the transformation.
22768 // If 64-bit shifts are legal, use the extract-shift sequence,
22769 // otherwise bounce the vector off the cache.
22770 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22772 SDLoc dl(InputVector);
22774 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22775 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22776 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22777 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22778 DAG.getConstant(0, VecIdxTy));
22779 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22780 DAG.getConstant(1, VecIdxTy));
22782 SDValue ShAmt = DAG.getConstant(32,
22783 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22784 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22785 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22786 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22787 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22788 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22789 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22791 // Store the value to a temporary stack slot.
22792 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22793 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22794 MachinePointerInfo(), false, false, 0);
22796 EVT ElementType = InputVector.getValueType().getVectorElementType();
22797 unsigned EltSize = ElementType.getSizeInBits() / 8;
22799 // Replace each use (extract) with a load of the appropriate element.
22800 for (unsigned i = 0; i < 4; ++i) {
22801 uint64_t Offset = EltSize * i;
22802 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22804 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22805 StackPtr, OffsetVal);
22807 // Load the scalar.
22808 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22809 ScalarAddr, MachinePointerInfo(),
22810 false, false, false, 0);
22815 // Replace the extracts
22816 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22817 UE = Uses.end(); UI != UE; ++UI) {
22818 SDNode *Extract = *UI;
22820 SDValue Idx = Extract->getOperand(1);
22821 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22822 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22825 // The replacement was made in place; don't return anything.
22829 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22830 static std::pair<unsigned, bool>
22831 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22832 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22833 if (!VT.isVector())
22834 return std::make_pair(0, false);
22836 bool NeedSplit = false;
22837 switch (VT.getSimpleVT().SimpleTy) {
22838 default: return std::make_pair(0, false);
22841 if (!Subtarget->hasVLX())
22842 return std::make_pair(0, false);
22846 if (!Subtarget->hasBWI())
22847 return std::make_pair(0, false);
22851 if (!Subtarget->hasAVX512())
22852 return std::make_pair(0, false);
22857 if (!Subtarget->hasAVX2())
22859 if (!Subtarget->hasAVX())
22860 return std::make_pair(0, false);
22865 if (!Subtarget->hasSSE2())
22866 return std::make_pair(0, false);
22869 // SSE2 has only a small subset of the operations.
22870 bool hasUnsigned = Subtarget->hasSSE41() ||
22871 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22872 bool hasSigned = Subtarget->hasSSE41() ||
22873 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22875 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22878 // Check for x CC y ? x : y.
22879 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22880 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22885 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22888 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22891 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22894 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22896 // Check for x CC y ? y : x -- a min/max with reversed arms.
22897 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22898 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22903 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22906 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22909 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22912 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22916 return std::make_pair(Opc, NeedSplit);
22920 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22921 const X86Subtarget *Subtarget) {
22923 SDValue Cond = N->getOperand(0);
22924 SDValue LHS = N->getOperand(1);
22925 SDValue RHS = N->getOperand(2);
22927 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22928 SDValue CondSrc = Cond->getOperand(0);
22929 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22930 Cond = CondSrc->getOperand(0);
22933 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22936 // A vselect where all conditions and data are constants can be optimized into
22937 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22938 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22939 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22942 unsigned MaskValue = 0;
22943 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22946 MVT VT = N->getSimpleValueType(0);
22947 unsigned NumElems = VT.getVectorNumElements();
22948 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22949 for (unsigned i = 0; i < NumElems; ++i) {
22950 // Be sure we emit undef where we can.
22951 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22952 ShuffleMask[i] = -1;
22954 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22957 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22958 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22960 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22963 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22965 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22966 TargetLowering::DAGCombinerInfo &DCI,
22967 const X86Subtarget *Subtarget) {
22969 SDValue Cond = N->getOperand(0);
22970 // Get the LHS/RHS of the select.
22971 SDValue LHS = N->getOperand(1);
22972 SDValue RHS = N->getOperand(2);
22973 EVT VT = LHS.getValueType();
22974 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22976 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22977 // instructions match the semantics of the common C idiom x<y?x:y but not
22978 // x<=y?x:y, because of how they handle negative zero (which can be
22979 // ignored in unsafe-math mode).
22980 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22981 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22982 (Subtarget->hasSSE2() ||
22983 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22984 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22986 unsigned Opcode = 0;
22987 // Check for x CC y ? x : y.
22988 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22989 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22993 // Converting this to a min would handle NaNs incorrectly, and swapping
22994 // the operands would cause it to handle comparisons between positive
22995 // and negative zero incorrectly.
22996 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22997 if (!DAG.getTarget().Options.UnsafeFPMath &&
22998 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23000 std::swap(LHS, RHS);
23002 Opcode = X86ISD::FMIN;
23005 // Converting this to a min would handle comparisons between positive
23006 // and negative zero incorrectly.
23007 if (!DAG.getTarget().Options.UnsafeFPMath &&
23008 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23010 Opcode = X86ISD::FMIN;
23013 // Converting this to a min would handle both negative zeros and NaNs
23014 // incorrectly, but we can swap the operands to fix both.
23015 std::swap(LHS, RHS);
23019 Opcode = X86ISD::FMIN;
23023 // Converting this to a max would handle comparisons between positive
23024 // and negative zero incorrectly.
23025 if (!DAG.getTarget().Options.UnsafeFPMath &&
23026 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23028 Opcode = X86ISD::FMAX;
23031 // Converting this to a max would handle NaNs incorrectly, and swapping
23032 // the operands would cause it to handle comparisons between positive
23033 // and negative zero incorrectly.
23034 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23035 if (!DAG.getTarget().Options.UnsafeFPMath &&
23036 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23038 std::swap(LHS, RHS);
23040 Opcode = X86ISD::FMAX;
23043 // Converting this to a max would handle both negative zeros and NaNs
23044 // incorrectly, but we can swap the operands to fix both.
23045 std::swap(LHS, RHS);
23049 Opcode = X86ISD::FMAX;
23052 // Check for x CC y ? y : x -- a min/max with reversed arms.
23053 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23054 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23058 // Converting this to a min would handle comparisons between positive
23059 // and negative zero incorrectly, and swapping the operands would
23060 // cause it to handle NaNs incorrectly.
23061 if (!DAG.getTarget().Options.UnsafeFPMath &&
23062 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23063 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23065 std::swap(LHS, RHS);
23067 Opcode = X86ISD::FMIN;
23070 // Converting this to a min would handle NaNs incorrectly.
23071 if (!DAG.getTarget().Options.UnsafeFPMath &&
23072 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23074 Opcode = X86ISD::FMIN;
23077 // Converting this to a min would handle both negative zeros and NaNs
23078 // incorrectly, but we can swap the operands to fix both.
23079 std::swap(LHS, RHS);
23083 Opcode = X86ISD::FMIN;
23087 // Converting this to a max would handle NaNs incorrectly.
23088 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23090 Opcode = X86ISD::FMAX;
23093 // Converting this to a max would handle comparisons between positive
23094 // and negative zero incorrectly, and swapping the operands would
23095 // cause it to handle NaNs incorrectly.
23096 if (!DAG.getTarget().Options.UnsafeFPMath &&
23097 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23098 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23100 std::swap(LHS, RHS);
23102 Opcode = X86ISD::FMAX;
23105 // Converting this to a max would handle both negative zeros and NaNs
23106 // incorrectly, but we can swap the operands to fix both.
23107 std::swap(LHS, RHS);
23111 Opcode = X86ISD::FMAX;
23117 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23120 EVT CondVT = Cond.getValueType();
23121 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23122 CondVT.getVectorElementType() == MVT::i1) {
23123 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23124 // lowering on KNL. In this case we convert it to
23125 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23126 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23127 // Since SKX these selects have a proper lowering.
23128 EVT OpVT = LHS.getValueType();
23129 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23130 (OpVT.getVectorElementType() == MVT::i8 ||
23131 OpVT.getVectorElementType() == MVT::i16) &&
23132 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23133 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23134 DCI.AddToWorklist(Cond.getNode());
23135 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23138 // If this is a select between two integer constants, try to do some
23140 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23141 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23142 // Don't do this for crazy integer types.
23143 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23144 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23145 // so that TrueC (the true value) is larger than FalseC.
23146 bool NeedsCondInvert = false;
23148 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23149 // Efficiently invertible.
23150 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23151 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23152 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23153 NeedsCondInvert = true;
23154 std::swap(TrueC, FalseC);
23157 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23158 if (FalseC->getAPIntValue() == 0 &&
23159 TrueC->getAPIntValue().isPowerOf2()) {
23160 if (NeedsCondInvert) // Invert the condition if needed.
23161 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23162 DAG.getConstant(1, Cond.getValueType()));
23164 // Zero extend the condition if needed.
23165 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23167 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23168 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23169 DAG.getConstant(ShAmt, MVT::i8));
23172 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23173 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23174 if (NeedsCondInvert) // Invert the condition if needed.
23175 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23176 DAG.getConstant(1, Cond.getValueType()));
23178 // Zero extend the condition if needed.
23179 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23180 FalseC->getValueType(0), Cond);
23181 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23182 SDValue(FalseC, 0));
23185 // Optimize cases that will turn into an LEA instruction. This requires
23186 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23187 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23188 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23189 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23191 bool isFastMultiplier = false;
23193 switch ((unsigned char)Diff) {
23195 case 1: // result = add base, cond
23196 case 2: // result = lea base( , cond*2)
23197 case 3: // result = lea base(cond, cond*2)
23198 case 4: // result = lea base( , cond*4)
23199 case 5: // result = lea base(cond, cond*4)
23200 case 8: // result = lea base( , cond*8)
23201 case 9: // result = lea base(cond, cond*8)
23202 isFastMultiplier = true;
23207 if (isFastMultiplier) {
23208 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23209 if (NeedsCondInvert) // Invert the condition if needed.
23210 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23211 DAG.getConstant(1, Cond.getValueType()));
23213 // Zero extend the condition if needed.
23214 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23216 // Scale the condition by the difference.
23218 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23219 DAG.getConstant(Diff, Cond.getValueType()));
23221 // Add the base if non-zero.
23222 if (FalseC->getAPIntValue() != 0)
23223 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23224 SDValue(FalseC, 0));
23231 // Canonicalize max and min:
23232 // (x > y) ? x : y -> (x >= y) ? x : y
23233 // (x < y) ? x : y -> (x <= y) ? x : y
23234 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23235 // the need for an extra compare
23236 // against zero. e.g.
23237 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23239 // testl %edi, %edi
23241 // cmovgl %edi, %eax
23245 // cmovsl %eax, %edi
23246 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23247 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23248 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23249 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23254 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23255 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23256 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23257 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23262 // Early exit check
23263 if (!TLI.isTypeLegal(VT))
23266 // Match VSELECTs into subs with unsigned saturation.
23267 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23268 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23269 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23270 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23271 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23273 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23274 // left side invert the predicate to simplify logic below.
23276 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23278 CC = ISD::getSetCCInverse(CC, true);
23279 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23283 if (Other.getNode() && Other->getNumOperands() == 2 &&
23284 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23285 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23286 SDValue CondRHS = Cond->getOperand(1);
23288 // Look for a general sub with unsigned saturation first.
23289 // x >= y ? x-y : 0 --> subus x, y
23290 // x > y ? x-y : 0 --> subus x, y
23291 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23292 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23293 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23295 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23296 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23297 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23298 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23299 // If the RHS is a constant we have to reverse the const
23300 // canonicalization.
23301 // x > C-1 ? x+-C : 0 --> subus x, C
23302 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23303 CondRHSConst->getAPIntValue() ==
23304 (-OpRHSConst->getAPIntValue() - 1))
23305 return DAG.getNode(
23306 X86ISD::SUBUS, DL, VT, OpLHS,
23307 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23309 // Another special case: If C was a sign bit, the sub has been
23310 // canonicalized into a xor.
23311 // FIXME: Would it be better to use computeKnownBits to determine
23312 // whether it's safe to decanonicalize the xor?
23313 // x s< 0 ? x^C : 0 --> subus x, C
23314 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23315 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23316 OpRHSConst->getAPIntValue().isSignBit())
23317 // Note that we have to rebuild the RHS constant here to ensure we
23318 // don't rely on particular values of undef lanes.
23319 return DAG.getNode(
23320 X86ISD::SUBUS, DL, VT, OpLHS,
23321 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23326 // Try to match a min/max vector operation.
23327 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23328 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23329 unsigned Opc = ret.first;
23330 bool NeedSplit = ret.second;
23332 if (Opc && NeedSplit) {
23333 unsigned NumElems = VT.getVectorNumElements();
23334 // Extract the LHS vectors
23335 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23336 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23338 // Extract the RHS vectors
23339 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23340 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23342 // Create min/max for each subvector
23343 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23344 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23346 // Merge the result
23347 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23349 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23352 // Simplify vector selection if condition value type matches vselect
23354 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23355 assert(Cond.getValueType().isVector() &&
23356 "vector select expects a vector selector!");
23358 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23359 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23361 // Try invert the condition if true value is not all 1s and false value
23363 if (!TValIsAllOnes && !FValIsAllZeros &&
23364 // Check if the selector will be produced by CMPP*/PCMP*
23365 Cond.getOpcode() == ISD::SETCC &&
23366 // Check if SETCC has already been promoted
23367 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23368 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23369 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23371 if (TValIsAllZeros || FValIsAllOnes) {
23372 SDValue CC = Cond.getOperand(2);
23373 ISD::CondCode NewCC =
23374 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23375 Cond.getOperand(0).getValueType().isInteger());
23376 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23377 std::swap(LHS, RHS);
23378 TValIsAllOnes = FValIsAllOnes;
23379 FValIsAllZeros = TValIsAllZeros;
23383 if (TValIsAllOnes || FValIsAllZeros) {
23386 if (TValIsAllOnes && FValIsAllZeros)
23388 else if (TValIsAllOnes)
23389 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23390 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23391 else if (FValIsAllZeros)
23392 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23393 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23395 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23399 // If we know that this node is legal then we know that it is going to be
23400 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23401 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23402 // to simplify previous instructions.
23403 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23404 !DCI.isBeforeLegalize() &&
23405 // We explicitly check against v8i16 and v16i16 because, although
23406 // they're marked as Custom, they might only be legal when Cond is a
23407 // build_vector of constants. This will be taken care in a later
23409 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23410 VT != MVT::v8i16) &&
23411 // Don't optimize vector of constants. Those are handled by
23412 // the generic code and all the bits must be properly set for
23413 // the generic optimizer.
23414 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23415 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23417 // Don't optimize vector selects that map to mask-registers.
23421 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23422 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23424 APInt KnownZero, KnownOne;
23425 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23426 DCI.isBeforeLegalizeOps());
23427 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23428 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23430 // If we changed the computation somewhere in the DAG, this change
23431 // will affect all users of Cond.
23432 // Make sure it is fine and update all the nodes so that we do not
23433 // use the generic VSELECT anymore. Otherwise, we may perform
23434 // wrong optimizations as we messed up with the actual expectation
23435 // for the vector boolean values.
23436 if (Cond != TLO.Old) {
23437 // Check all uses of that condition operand to check whether it will be
23438 // consumed by non-BLEND instructions, which may depend on all bits are
23440 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23442 if (I->getOpcode() != ISD::VSELECT)
23443 // TODO: Add other opcodes eventually lowered into BLEND.
23446 // Update all the users of the condition, before committing the change,
23447 // so that the VSELECT optimizations that expect the correct vector
23448 // boolean value will not be triggered.
23449 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23451 DAG.ReplaceAllUsesOfValueWith(
23453 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23454 Cond, I->getOperand(1), I->getOperand(2)));
23455 DCI.CommitTargetLoweringOpt(TLO);
23458 // At this point, only Cond is changed. Change the condition
23459 // just for N to keep the opportunity to optimize all other
23460 // users their own way.
23461 DAG.ReplaceAllUsesOfValueWith(
23463 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23464 TLO.New, N->getOperand(1), N->getOperand(2)));
23469 // We should generate an X86ISD::BLENDI from a vselect if its argument
23470 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23471 // constants. This specific pattern gets generated when we split a
23472 // selector for a 512 bit vector in a machine without AVX512 (but with
23473 // 256-bit vectors), during legalization:
23475 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23477 // Iff we find this pattern and the build_vectors are built from
23478 // constants, we translate the vselect into a shuffle_vector that we
23479 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23480 if ((N->getOpcode() == ISD::VSELECT ||
23481 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23482 !DCI.isBeforeLegalize()) {
23483 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23484 if (Shuffle.getNode())
23491 // Check whether a boolean test is testing a boolean value generated by
23492 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23495 // Simplify the following patterns:
23496 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23497 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23498 // to (Op EFLAGS Cond)
23500 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23501 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23502 // to (Op EFLAGS !Cond)
23504 // where Op could be BRCOND or CMOV.
23506 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23507 // Quit if not CMP and SUB with its value result used.
23508 if (Cmp.getOpcode() != X86ISD::CMP &&
23509 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23512 // Quit if not used as a boolean value.
23513 if (CC != X86::COND_E && CC != X86::COND_NE)
23516 // Check CMP operands. One of them should be 0 or 1 and the other should be
23517 // an SetCC or extended from it.
23518 SDValue Op1 = Cmp.getOperand(0);
23519 SDValue Op2 = Cmp.getOperand(1);
23522 const ConstantSDNode* C = nullptr;
23523 bool needOppositeCond = (CC == X86::COND_E);
23524 bool checkAgainstTrue = false; // Is it a comparison against 1?
23526 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23528 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23530 else // Quit if all operands are not constants.
23533 if (C->getZExtValue() == 1) {
23534 needOppositeCond = !needOppositeCond;
23535 checkAgainstTrue = true;
23536 } else if (C->getZExtValue() != 0)
23537 // Quit if the constant is neither 0 or 1.
23540 bool truncatedToBoolWithAnd = false;
23541 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23542 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23543 SetCC.getOpcode() == ISD::TRUNCATE ||
23544 SetCC.getOpcode() == ISD::AND) {
23545 if (SetCC.getOpcode() == ISD::AND) {
23547 ConstantSDNode *CS;
23548 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23549 CS->getZExtValue() == 1)
23551 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23552 CS->getZExtValue() == 1)
23556 SetCC = SetCC.getOperand(OpIdx);
23557 truncatedToBoolWithAnd = true;
23559 SetCC = SetCC.getOperand(0);
23562 switch (SetCC.getOpcode()) {
23563 case X86ISD::SETCC_CARRY:
23564 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23565 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23566 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23567 // truncated to i1 using 'and'.
23568 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23570 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23571 "Invalid use of SETCC_CARRY!");
23573 case X86ISD::SETCC:
23574 // Set the condition code or opposite one if necessary.
23575 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23576 if (needOppositeCond)
23577 CC = X86::GetOppositeBranchCondition(CC);
23578 return SetCC.getOperand(1);
23579 case X86ISD::CMOV: {
23580 // Check whether false/true value has canonical one, i.e. 0 or 1.
23581 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23582 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23583 // Quit if true value is not a constant.
23586 // Quit if false value is not a constant.
23588 SDValue Op = SetCC.getOperand(0);
23589 // Skip 'zext' or 'trunc' node.
23590 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23591 Op.getOpcode() == ISD::TRUNCATE)
23592 Op = Op.getOperand(0);
23593 // A special case for rdrand/rdseed, where 0 is set if false cond is
23595 if ((Op.getOpcode() != X86ISD::RDRAND &&
23596 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23599 // Quit if false value is not the constant 0 or 1.
23600 bool FValIsFalse = true;
23601 if (FVal && FVal->getZExtValue() != 0) {
23602 if (FVal->getZExtValue() != 1)
23604 // If FVal is 1, opposite cond is needed.
23605 needOppositeCond = !needOppositeCond;
23606 FValIsFalse = false;
23608 // Quit if TVal is not the constant opposite of FVal.
23609 if (FValIsFalse && TVal->getZExtValue() != 1)
23611 if (!FValIsFalse && TVal->getZExtValue() != 0)
23613 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23614 if (needOppositeCond)
23615 CC = X86::GetOppositeBranchCondition(CC);
23616 return SetCC.getOperand(3);
23623 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23624 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23625 TargetLowering::DAGCombinerInfo &DCI,
23626 const X86Subtarget *Subtarget) {
23629 // If the flag operand isn't dead, don't touch this CMOV.
23630 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23633 SDValue FalseOp = N->getOperand(0);
23634 SDValue TrueOp = N->getOperand(1);
23635 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23636 SDValue Cond = N->getOperand(3);
23638 if (CC == X86::COND_E || CC == X86::COND_NE) {
23639 switch (Cond.getOpcode()) {
23643 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23644 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23645 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23651 Flags = checkBoolTestSetCCCombine(Cond, CC);
23652 if (Flags.getNode() &&
23653 // Extra check as FCMOV only supports a subset of X86 cond.
23654 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23655 SDValue Ops[] = { FalseOp, TrueOp,
23656 DAG.getConstant(CC, MVT::i8), Flags };
23657 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23660 // If this is a select between two integer constants, try to do some
23661 // optimizations. Note that the operands are ordered the opposite of SELECT
23663 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23664 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23665 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23666 // larger than FalseC (the false value).
23667 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23668 CC = X86::GetOppositeBranchCondition(CC);
23669 std::swap(TrueC, FalseC);
23670 std::swap(TrueOp, FalseOp);
23673 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23674 // This is efficient for any integer data type (including i8/i16) and
23676 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23677 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23678 DAG.getConstant(CC, MVT::i8), Cond);
23680 // Zero extend the condition if needed.
23681 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23683 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23684 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23685 DAG.getConstant(ShAmt, MVT::i8));
23686 if (N->getNumValues() == 2) // Dead flag value?
23687 return DCI.CombineTo(N, Cond, SDValue());
23691 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23692 // for any integer data type, including i8/i16.
23693 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23694 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23695 DAG.getConstant(CC, MVT::i8), Cond);
23697 // Zero extend the condition if needed.
23698 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23699 FalseC->getValueType(0), Cond);
23700 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23701 SDValue(FalseC, 0));
23703 if (N->getNumValues() == 2) // Dead flag value?
23704 return DCI.CombineTo(N, Cond, SDValue());
23708 // Optimize cases that will turn into an LEA instruction. This requires
23709 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23710 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23711 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23712 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23714 bool isFastMultiplier = false;
23716 switch ((unsigned char)Diff) {
23718 case 1: // result = add base, cond
23719 case 2: // result = lea base( , cond*2)
23720 case 3: // result = lea base(cond, cond*2)
23721 case 4: // result = lea base( , cond*4)
23722 case 5: // result = lea base(cond, cond*4)
23723 case 8: // result = lea base( , cond*8)
23724 case 9: // result = lea base(cond, cond*8)
23725 isFastMultiplier = true;
23730 if (isFastMultiplier) {
23731 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23732 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23733 DAG.getConstant(CC, MVT::i8), Cond);
23734 // Zero extend the condition if needed.
23735 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23737 // Scale the condition by the difference.
23739 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23740 DAG.getConstant(Diff, Cond.getValueType()));
23742 // Add the base if non-zero.
23743 if (FalseC->getAPIntValue() != 0)
23744 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23745 SDValue(FalseC, 0));
23746 if (N->getNumValues() == 2) // Dead flag value?
23747 return DCI.CombineTo(N, Cond, SDValue());
23754 // Handle these cases:
23755 // (select (x != c), e, c) -> select (x != c), e, x),
23756 // (select (x == c), c, e) -> select (x == c), x, e)
23757 // where the c is an integer constant, and the "select" is the combination
23758 // of CMOV and CMP.
23760 // The rationale for this change is that the conditional-move from a constant
23761 // needs two instructions, however, conditional-move from a register needs
23762 // only one instruction.
23764 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23765 // some instruction-combining opportunities. This opt needs to be
23766 // postponed as late as possible.
23768 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23769 // the DCI.xxxx conditions are provided to postpone the optimization as
23770 // late as possible.
23772 ConstantSDNode *CmpAgainst = nullptr;
23773 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23774 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23775 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23777 if (CC == X86::COND_NE &&
23778 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23779 CC = X86::GetOppositeBranchCondition(CC);
23780 std::swap(TrueOp, FalseOp);
23783 if (CC == X86::COND_E &&
23784 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23785 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23786 DAG.getConstant(CC, MVT::i8), Cond };
23787 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23795 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23796 const X86Subtarget *Subtarget) {
23797 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23799 default: return SDValue();
23800 // SSE/AVX/AVX2 blend intrinsics.
23801 case Intrinsic::x86_avx2_pblendvb:
23802 case Intrinsic::x86_avx2_pblendw:
23803 case Intrinsic::x86_avx2_pblendd_128:
23804 case Intrinsic::x86_avx2_pblendd_256:
23805 // Don't try to simplify this intrinsic if we don't have AVX2.
23806 if (!Subtarget->hasAVX2())
23809 case Intrinsic::x86_avx_blend_pd_256:
23810 case Intrinsic::x86_avx_blend_ps_256:
23811 case Intrinsic::x86_avx_blendv_pd_256:
23812 case Intrinsic::x86_avx_blendv_ps_256:
23813 // Don't try to simplify this intrinsic if we don't have AVX.
23814 if (!Subtarget->hasAVX())
23817 case Intrinsic::x86_sse41_pblendw:
23818 case Intrinsic::x86_sse41_blendpd:
23819 case Intrinsic::x86_sse41_blendps:
23820 case Intrinsic::x86_sse41_blendvps:
23821 case Intrinsic::x86_sse41_blendvpd:
23822 case Intrinsic::x86_sse41_pblendvb: {
23823 SDValue Op0 = N->getOperand(1);
23824 SDValue Op1 = N->getOperand(2);
23825 SDValue Mask = N->getOperand(3);
23827 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23828 if (!Subtarget->hasSSE41())
23831 // fold (blend A, A, Mask) -> A
23834 // fold (blend A, B, allZeros) -> A
23835 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23837 // fold (blend A, B, allOnes) -> B
23838 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23841 // Simplify the case where the mask is a constant i32 value.
23842 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23843 if (C->isNullValue())
23845 if (C->isAllOnesValue())
23852 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23853 case Intrinsic::x86_sse2_psrai_w:
23854 case Intrinsic::x86_sse2_psrai_d:
23855 case Intrinsic::x86_avx2_psrai_w:
23856 case Intrinsic::x86_avx2_psrai_d:
23857 case Intrinsic::x86_sse2_psra_w:
23858 case Intrinsic::x86_sse2_psra_d:
23859 case Intrinsic::x86_avx2_psra_w:
23860 case Intrinsic::x86_avx2_psra_d: {
23861 SDValue Op0 = N->getOperand(1);
23862 SDValue Op1 = N->getOperand(2);
23863 EVT VT = Op0.getValueType();
23864 assert(VT.isVector() && "Expected a vector type!");
23866 if (isa<BuildVectorSDNode>(Op1))
23867 Op1 = Op1.getOperand(0);
23869 if (!isa<ConstantSDNode>(Op1))
23872 EVT SVT = VT.getVectorElementType();
23873 unsigned SVTBits = SVT.getSizeInBits();
23875 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23876 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23877 uint64_t ShAmt = C.getZExtValue();
23879 // Don't try to convert this shift into a ISD::SRA if the shift
23880 // count is bigger than or equal to the element size.
23881 if (ShAmt >= SVTBits)
23884 // Trivial case: if the shift count is zero, then fold this
23885 // into the first operand.
23889 // Replace this packed shift intrinsic with a target independent
23891 SDValue Splat = DAG.getConstant(C, VT);
23892 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23897 /// PerformMulCombine - Optimize a single multiply with constant into two
23898 /// in order to implement it with two cheaper instructions, e.g.
23899 /// LEA + SHL, LEA + LEA.
23900 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23901 TargetLowering::DAGCombinerInfo &DCI) {
23902 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23905 EVT VT = N->getValueType(0);
23906 if (VT != MVT::i64)
23909 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23912 uint64_t MulAmt = C->getZExtValue();
23913 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23916 uint64_t MulAmt1 = 0;
23917 uint64_t MulAmt2 = 0;
23918 if ((MulAmt % 9) == 0) {
23920 MulAmt2 = MulAmt / 9;
23921 } else if ((MulAmt % 5) == 0) {
23923 MulAmt2 = MulAmt / 5;
23924 } else if ((MulAmt % 3) == 0) {
23926 MulAmt2 = MulAmt / 3;
23929 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23932 if (isPowerOf2_64(MulAmt2) &&
23933 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23934 // If second multiplifer is pow2, issue it first. We want the multiply by
23935 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23937 std::swap(MulAmt1, MulAmt2);
23940 if (isPowerOf2_64(MulAmt1))
23941 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23942 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23944 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23945 DAG.getConstant(MulAmt1, VT));
23947 if (isPowerOf2_64(MulAmt2))
23948 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23949 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23951 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23952 DAG.getConstant(MulAmt2, VT));
23954 // Do not add new nodes to DAG combiner worklist.
23955 DCI.CombineTo(N, NewMul, false);
23960 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23961 SDValue N0 = N->getOperand(0);
23962 SDValue N1 = N->getOperand(1);
23963 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23964 EVT VT = N0.getValueType();
23966 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23967 // since the result of setcc_c is all zero's or all ones.
23968 if (VT.isInteger() && !VT.isVector() &&
23969 N1C && N0.getOpcode() == ISD::AND &&
23970 N0.getOperand(1).getOpcode() == ISD::Constant) {
23971 SDValue N00 = N0.getOperand(0);
23972 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23973 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23974 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23975 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23976 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23977 APInt ShAmt = N1C->getAPIntValue();
23978 Mask = Mask.shl(ShAmt);
23980 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23981 N00, DAG.getConstant(Mask, VT));
23985 // Hardware support for vector shifts is sparse which makes us scalarize the
23986 // vector operations in many cases. Also, on sandybridge ADD is faster than
23988 // (shl V, 1) -> add V,V
23989 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23990 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23991 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23992 // We shift all of the values by one. In many cases we do not have
23993 // hardware support for this operation. This is better expressed as an ADD
23995 if (N1SplatC->getZExtValue() == 1)
23996 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24002 /// \brief Returns a vector of 0s if the node in input is a vector logical
24003 /// shift by a constant amount which is known to be bigger than or equal
24004 /// to the vector element size in bits.
24005 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24006 const X86Subtarget *Subtarget) {
24007 EVT VT = N->getValueType(0);
24009 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24010 (!Subtarget->hasInt256() ||
24011 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24014 SDValue Amt = N->getOperand(1);
24016 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24017 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24018 APInt ShiftAmt = AmtSplat->getAPIntValue();
24019 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24021 // SSE2/AVX2 logical shifts always return a vector of 0s
24022 // if the shift amount is bigger than or equal to
24023 // the element size. The constant shift amount will be
24024 // encoded as a 8-bit immediate.
24025 if (ShiftAmt.trunc(8).uge(MaxAmount))
24026 return getZeroVector(VT, Subtarget, DAG, DL);
24032 /// PerformShiftCombine - Combine shifts.
24033 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24034 TargetLowering::DAGCombinerInfo &DCI,
24035 const X86Subtarget *Subtarget) {
24036 if (N->getOpcode() == ISD::SHL) {
24037 SDValue V = PerformSHLCombine(N, DAG);
24038 if (V.getNode()) return V;
24041 if (N->getOpcode() != ISD::SRA) {
24042 // Try to fold this logical shift into a zero vector.
24043 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
24044 if (V.getNode()) return V;
24050 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24051 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24052 // and friends. Likewise for OR -> CMPNEQSS.
24053 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24054 TargetLowering::DAGCombinerInfo &DCI,
24055 const X86Subtarget *Subtarget) {
24058 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24059 // we're requiring SSE2 for both.
24060 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24061 SDValue N0 = N->getOperand(0);
24062 SDValue N1 = N->getOperand(1);
24063 SDValue CMP0 = N0->getOperand(1);
24064 SDValue CMP1 = N1->getOperand(1);
24067 // The SETCCs should both refer to the same CMP.
24068 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24071 SDValue CMP00 = CMP0->getOperand(0);
24072 SDValue CMP01 = CMP0->getOperand(1);
24073 EVT VT = CMP00.getValueType();
24075 if (VT == MVT::f32 || VT == MVT::f64) {
24076 bool ExpectingFlags = false;
24077 // Check for any users that want flags:
24078 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24079 !ExpectingFlags && UI != UE; ++UI)
24080 switch (UI->getOpcode()) {
24085 ExpectingFlags = true;
24087 case ISD::CopyToReg:
24088 case ISD::SIGN_EXTEND:
24089 case ISD::ZERO_EXTEND:
24090 case ISD::ANY_EXTEND:
24094 if (!ExpectingFlags) {
24095 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24096 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24098 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24099 X86::CondCode tmp = cc0;
24104 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24105 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24106 // FIXME: need symbolic constants for these magic numbers.
24107 // See X86ATTInstPrinter.cpp:printSSECC().
24108 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24109 if (Subtarget->hasAVX512()) {
24110 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24111 CMP01, DAG.getConstant(x86cc, MVT::i8));
24112 if (N->getValueType(0) != MVT::i1)
24113 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24117 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24118 CMP00.getValueType(), CMP00, CMP01,
24119 DAG.getConstant(x86cc, MVT::i8));
24121 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24122 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24124 if (is64BitFP && !Subtarget->is64Bit()) {
24125 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24126 // 64-bit integer, since that's not a legal type. Since
24127 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24128 // bits, but can do this little dance to extract the lowest 32 bits
24129 // and work with those going forward.
24130 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24132 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
24134 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24135 Vector32, DAG.getIntPtrConstant(0));
24139 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
24140 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24141 DAG.getConstant(1, IntVT));
24142 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
24143 return OneBitOfTruth;
24151 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24152 /// so it can be folded inside ANDNP.
24153 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24154 EVT VT = N->getValueType(0);
24156 // Match direct AllOnes for 128 and 256-bit vectors
24157 if (ISD::isBuildVectorAllOnes(N))
24160 // Look through a bit convert.
24161 if (N->getOpcode() == ISD::BITCAST)
24162 N = N->getOperand(0).getNode();
24164 // Sometimes the operand may come from a insert_subvector building a 256-bit
24166 if (VT.is256BitVector() &&
24167 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24168 SDValue V1 = N->getOperand(0);
24169 SDValue V2 = N->getOperand(1);
24171 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24172 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24173 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24174 ISD::isBuildVectorAllOnes(V2.getNode()))
24181 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24182 // register. In most cases we actually compare or select YMM-sized registers
24183 // and mixing the two types creates horrible code. This method optimizes
24184 // some of the transition sequences.
24185 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24186 TargetLowering::DAGCombinerInfo &DCI,
24187 const X86Subtarget *Subtarget) {
24188 EVT VT = N->getValueType(0);
24189 if (!VT.is256BitVector())
24192 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24193 N->getOpcode() == ISD::ZERO_EXTEND ||
24194 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24196 SDValue Narrow = N->getOperand(0);
24197 EVT NarrowVT = Narrow->getValueType(0);
24198 if (!NarrowVT.is128BitVector())
24201 if (Narrow->getOpcode() != ISD::XOR &&
24202 Narrow->getOpcode() != ISD::AND &&
24203 Narrow->getOpcode() != ISD::OR)
24206 SDValue N0 = Narrow->getOperand(0);
24207 SDValue N1 = Narrow->getOperand(1);
24210 // The Left side has to be a trunc.
24211 if (N0.getOpcode() != ISD::TRUNCATE)
24214 // The type of the truncated inputs.
24215 EVT WideVT = N0->getOperand(0)->getValueType(0);
24219 // The right side has to be a 'trunc' or a constant vector.
24220 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24221 ConstantSDNode *RHSConstSplat = nullptr;
24222 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24223 RHSConstSplat = RHSBV->getConstantSplatNode();
24224 if (!RHSTrunc && !RHSConstSplat)
24227 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24229 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24232 // Set N0 and N1 to hold the inputs to the new wide operation.
24233 N0 = N0->getOperand(0);
24234 if (RHSConstSplat) {
24235 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24236 SDValue(RHSConstSplat, 0));
24237 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24238 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24239 } else if (RHSTrunc) {
24240 N1 = N1->getOperand(0);
24243 // Generate the wide operation.
24244 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24245 unsigned Opcode = N->getOpcode();
24247 case ISD::ANY_EXTEND:
24249 case ISD::ZERO_EXTEND: {
24250 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24251 APInt Mask = APInt::getAllOnesValue(InBits);
24252 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24253 return DAG.getNode(ISD::AND, DL, VT,
24254 Op, DAG.getConstant(Mask, VT));
24256 case ISD::SIGN_EXTEND:
24257 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24258 Op, DAG.getValueType(NarrowVT));
24260 llvm_unreachable("Unexpected opcode");
24264 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24265 TargetLowering::DAGCombinerInfo &DCI,
24266 const X86Subtarget *Subtarget) {
24267 EVT VT = N->getValueType(0);
24268 if (DCI.isBeforeLegalizeOps())
24271 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24275 // Create BEXTR instructions
24276 // BEXTR is ((X >> imm) & (2**size-1))
24277 if (VT == MVT::i32 || VT == MVT::i64) {
24278 SDValue N0 = N->getOperand(0);
24279 SDValue N1 = N->getOperand(1);
24282 // Check for BEXTR.
24283 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24284 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24285 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24286 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24287 if (MaskNode && ShiftNode) {
24288 uint64_t Mask = MaskNode->getZExtValue();
24289 uint64_t Shift = ShiftNode->getZExtValue();
24290 if (isMask_64(Mask)) {
24291 uint64_t MaskSize = CountPopulation_64(Mask);
24292 if (Shift + MaskSize <= VT.getSizeInBits())
24293 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24294 DAG.getConstant(Shift | (MaskSize << 8), VT));
24302 // Want to form ANDNP nodes:
24303 // 1) In the hopes of then easily combining them with OR and AND nodes
24304 // to form PBLEND/PSIGN.
24305 // 2) To match ANDN packed intrinsics
24306 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24309 SDValue N0 = N->getOperand(0);
24310 SDValue N1 = N->getOperand(1);
24313 // Check LHS for vnot
24314 if (N0.getOpcode() == ISD::XOR &&
24315 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24316 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24317 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24319 // Check RHS for vnot
24320 if (N1.getOpcode() == ISD::XOR &&
24321 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24322 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24323 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24328 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24329 TargetLowering::DAGCombinerInfo &DCI,
24330 const X86Subtarget *Subtarget) {
24331 if (DCI.isBeforeLegalizeOps())
24334 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24338 SDValue N0 = N->getOperand(0);
24339 SDValue N1 = N->getOperand(1);
24340 EVT VT = N->getValueType(0);
24342 // look for psign/blend
24343 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24344 if (!Subtarget->hasSSSE3() ||
24345 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24348 // Canonicalize pandn to RHS
24349 if (N0.getOpcode() == X86ISD::ANDNP)
24351 // or (and (m, y), (pandn m, x))
24352 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24353 SDValue Mask = N1.getOperand(0);
24354 SDValue X = N1.getOperand(1);
24356 if (N0.getOperand(0) == Mask)
24357 Y = N0.getOperand(1);
24358 if (N0.getOperand(1) == Mask)
24359 Y = N0.getOperand(0);
24361 // Check to see if the mask appeared in both the AND and ANDNP and
24365 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24366 // Look through mask bitcast.
24367 if (Mask.getOpcode() == ISD::BITCAST)
24368 Mask = Mask.getOperand(0);
24369 if (X.getOpcode() == ISD::BITCAST)
24370 X = X.getOperand(0);
24371 if (Y.getOpcode() == ISD::BITCAST)
24372 Y = Y.getOperand(0);
24374 EVT MaskVT = Mask.getValueType();
24376 // Validate that the Mask operand is a vector sra node.
24377 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24378 // there is no psrai.b
24379 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24380 unsigned SraAmt = ~0;
24381 if (Mask.getOpcode() == ISD::SRA) {
24382 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24383 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24384 SraAmt = AmtConst->getZExtValue();
24385 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24386 SDValue SraC = Mask.getOperand(1);
24387 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24389 if ((SraAmt + 1) != EltBits)
24394 // Now we know we at least have a plendvb with the mask val. See if
24395 // we can form a psignb/w/d.
24396 // psign = x.type == y.type == mask.type && y = sub(0, x);
24397 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24398 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24399 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24400 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24401 "Unsupported VT for PSIGN");
24402 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24403 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24405 // PBLENDVB only available on SSE 4.1
24406 if (!Subtarget->hasSSE41())
24409 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24411 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24412 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24413 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24414 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24415 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24419 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24422 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24423 MachineFunction &MF = DAG.getMachineFunction();
24424 bool OptForSize = MF.getFunction()->getAttributes().
24425 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24427 // SHLD/SHRD instructions have lower register pressure, but on some
24428 // platforms they have higher latency than the equivalent
24429 // series of shifts/or that would otherwise be generated.
24430 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24431 // have higher latencies and we are not optimizing for size.
24432 if (!OptForSize && Subtarget->isSHLDSlow())
24435 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24437 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24439 if (!N0.hasOneUse() || !N1.hasOneUse())
24442 SDValue ShAmt0 = N0.getOperand(1);
24443 if (ShAmt0.getValueType() != MVT::i8)
24445 SDValue ShAmt1 = N1.getOperand(1);
24446 if (ShAmt1.getValueType() != MVT::i8)
24448 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24449 ShAmt0 = ShAmt0.getOperand(0);
24450 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24451 ShAmt1 = ShAmt1.getOperand(0);
24454 unsigned Opc = X86ISD::SHLD;
24455 SDValue Op0 = N0.getOperand(0);
24456 SDValue Op1 = N1.getOperand(0);
24457 if (ShAmt0.getOpcode() == ISD::SUB) {
24458 Opc = X86ISD::SHRD;
24459 std::swap(Op0, Op1);
24460 std::swap(ShAmt0, ShAmt1);
24463 unsigned Bits = VT.getSizeInBits();
24464 if (ShAmt1.getOpcode() == ISD::SUB) {
24465 SDValue Sum = ShAmt1.getOperand(0);
24466 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24467 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24468 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24469 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24470 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24471 return DAG.getNode(Opc, DL, VT,
24473 DAG.getNode(ISD::TRUNCATE, DL,
24476 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24477 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24479 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24480 return DAG.getNode(Opc, DL, VT,
24481 N0.getOperand(0), N1.getOperand(0),
24482 DAG.getNode(ISD::TRUNCATE, DL,
24489 // Generate NEG and CMOV for integer abs.
24490 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24491 EVT VT = N->getValueType(0);
24493 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24494 // 8-bit integer abs to NEG and CMOV.
24495 if (VT.isInteger() && VT.getSizeInBits() == 8)
24498 SDValue N0 = N->getOperand(0);
24499 SDValue N1 = N->getOperand(1);
24502 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24503 // and change it to SUB and CMOV.
24504 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24505 N0.getOpcode() == ISD::ADD &&
24506 N0.getOperand(1) == N1 &&
24507 N1.getOpcode() == ISD::SRA &&
24508 N1.getOperand(0) == N0.getOperand(0))
24509 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24510 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24511 // Generate SUB & CMOV.
24512 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24513 DAG.getConstant(0, VT), N0.getOperand(0));
24515 SDValue Ops[] = { N0.getOperand(0), Neg,
24516 DAG.getConstant(X86::COND_GE, MVT::i8),
24517 SDValue(Neg.getNode(), 1) };
24518 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24523 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24524 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24525 TargetLowering::DAGCombinerInfo &DCI,
24526 const X86Subtarget *Subtarget) {
24527 if (DCI.isBeforeLegalizeOps())
24530 if (Subtarget->hasCMov()) {
24531 SDValue RV = performIntegerAbsCombine(N, DAG);
24539 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24540 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24541 TargetLowering::DAGCombinerInfo &DCI,
24542 const X86Subtarget *Subtarget) {
24543 LoadSDNode *Ld = cast<LoadSDNode>(N);
24544 EVT RegVT = Ld->getValueType(0);
24545 EVT MemVT = Ld->getMemoryVT();
24547 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24549 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24550 // into two 16-byte operations.
24551 ISD::LoadExtType Ext = Ld->getExtensionType();
24552 unsigned Alignment = Ld->getAlignment();
24553 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24554 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24555 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24556 unsigned NumElems = RegVT.getVectorNumElements();
24560 SDValue Ptr = Ld->getBasePtr();
24561 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24563 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24565 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24566 Ld->getPointerInfo(), Ld->isVolatile(),
24567 Ld->isNonTemporal(), Ld->isInvariant(),
24569 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24570 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24571 Ld->getPointerInfo(), Ld->isVolatile(),
24572 Ld->isNonTemporal(), Ld->isInvariant(),
24573 std::min(16U, Alignment));
24574 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24576 Load2.getValue(1));
24578 SDValue NewVec = DAG.getUNDEF(RegVT);
24579 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24580 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24581 return DCI.CombineTo(N, NewVec, TF, true);
24587 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24588 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24589 const X86Subtarget *Subtarget) {
24590 StoreSDNode *St = cast<StoreSDNode>(N);
24591 EVT VT = St->getValue().getValueType();
24592 EVT StVT = St->getMemoryVT();
24594 SDValue StoredVal = St->getOperand(1);
24595 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24597 // If we are saving a concatenation of two XMM registers and 32-byte stores
24598 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24599 unsigned Alignment = St->getAlignment();
24600 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24601 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24602 StVT == VT && !IsAligned) {
24603 unsigned NumElems = VT.getVectorNumElements();
24607 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24608 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24610 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24611 SDValue Ptr0 = St->getBasePtr();
24612 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24614 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24615 St->getPointerInfo(), St->isVolatile(),
24616 St->isNonTemporal(), Alignment);
24617 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24618 St->getPointerInfo(), St->isVolatile(),
24619 St->isNonTemporal(),
24620 std::min(16U, Alignment));
24621 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24624 // Optimize trunc store (of multiple scalars) to shuffle and store.
24625 // First, pack all of the elements in one place. Next, store to memory
24626 // in fewer chunks.
24627 if (St->isTruncatingStore() && VT.isVector()) {
24628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24629 unsigned NumElems = VT.getVectorNumElements();
24630 assert(StVT != VT && "Cannot truncate to the same type");
24631 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24632 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24634 // From, To sizes and ElemCount must be pow of two
24635 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24636 // We are going to use the original vector elt for storing.
24637 // Accumulated smaller vector elements must be a multiple of the store size.
24638 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24640 unsigned SizeRatio = FromSz / ToSz;
24642 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24644 // Create a type on which we perform the shuffle
24645 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24646 StVT.getScalarType(), NumElems*SizeRatio);
24648 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24650 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24651 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24652 for (unsigned i = 0; i != NumElems; ++i)
24653 ShuffleVec[i] = i * SizeRatio;
24655 // Can't shuffle using an illegal type.
24656 if (!TLI.isTypeLegal(WideVecVT))
24659 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24660 DAG.getUNDEF(WideVecVT),
24662 // At this point all of the data is stored at the bottom of the
24663 // register. We now need to save it to mem.
24665 // Find the largest store unit
24666 MVT StoreType = MVT::i8;
24667 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24668 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24669 MVT Tp = (MVT::SimpleValueType)tp;
24670 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24674 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24675 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24676 (64 <= NumElems * ToSz))
24677 StoreType = MVT::f64;
24679 // Bitcast the original vector into a vector of store-size units
24680 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24681 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24682 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24683 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24684 SmallVector<SDValue, 8> Chains;
24685 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24686 TLI.getPointerTy());
24687 SDValue Ptr = St->getBasePtr();
24689 // Perform one or more big stores into memory.
24690 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24691 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24692 StoreType, ShuffWide,
24693 DAG.getIntPtrConstant(i));
24694 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24695 St->getPointerInfo(), St->isVolatile(),
24696 St->isNonTemporal(), St->getAlignment());
24697 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24698 Chains.push_back(Ch);
24701 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24704 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24705 // the FP state in cases where an emms may be missing.
24706 // A preferable solution to the general problem is to figure out the right
24707 // places to insert EMMS. This qualifies as a quick hack.
24709 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24710 if (VT.getSizeInBits() != 64)
24713 const Function *F = DAG.getMachineFunction().getFunction();
24714 bool NoImplicitFloatOps = F->getAttributes().
24715 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24716 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24717 && Subtarget->hasSSE2();
24718 if ((VT.isVector() ||
24719 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24720 isa<LoadSDNode>(St->getValue()) &&
24721 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24722 St->getChain().hasOneUse() && !St->isVolatile()) {
24723 SDNode* LdVal = St->getValue().getNode();
24724 LoadSDNode *Ld = nullptr;
24725 int TokenFactorIndex = -1;
24726 SmallVector<SDValue, 8> Ops;
24727 SDNode* ChainVal = St->getChain().getNode();
24728 // Must be a store of a load. We currently handle two cases: the load
24729 // is a direct child, and it's under an intervening TokenFactor. It is
24730 // possible to dig deeper under nested TokenFactors.
24731 if (ChainVal == LdVal)
24732 Ld = cast<LoadSDNode>(St->getChain());
24733 else if (St->getValue().hasOneUse() &&
24734 ChainVal->getOpcode() == ISD::TokenFactor) {
24735 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24736 if (ChainVal->getOperand(i).getNode() == LdVal) {
24737 TokenFactorIndex = i;
24738 Ld = cast<LoadSDNode>(St->getValue());
24740 Ops.push_back(ChainVal->getOperand(i));
24744 if (!Ld || !ISD::isNormalLoad(Ld))
24747 // If this is not the MMX case, i.e. we are just turning i64 load/store
24748 // into f64 load/store, avoid the transformation if there are multiple
24749 // uses of the loaded value.
24750 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24755 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24756 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24758 if (Subtarget->is64Bit() || F64IsLegal) {
24759 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24760 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24761 Ld->getPointerInfo(), Ld->isVolatile(),
24762 Ld->isNonTemporal(), Ld->isInvariant(),
24763 Ld->getAlignment());
24764 SDValue NewChain = NewLd.getValue(1);
24765 if (TokenFactorIndex != -1) {
24766 Ops.push_back(NewChain);
24767 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24769 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24770 St->getPointerInfo(),
24771 St->isVolatile(), St->isNonTemporal(),
24772 St->getAlignment());
24775 // Otherwise, lower to two pairs of 32-bit loads / stores.
24776 SDValue LoAddr = Ld->getBasePtr();
24777 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24778 DAG.getConstant(4, MVT::i32));
24780 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24781 Ld->getPointerInfo(),
24782 Ld->isVolatile(), Ld->isNonTemporal(),
24783 Ld->isInvariant(), Ld->getAlignment());
24784 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24785 Ld->getPointerInfo().getWithOffset(4),
24786 Ld->isVolatile(), Ld->isNonTemporal(),
24788 MinAlign(Ld->getAlignment(), 4));
24790 SDValue NewChain = LoLd.getValue(1);
24791 if (TokenFactorIndex != -1) {
24792 Ops.push_back(LoLd);
24793 Ops.push_back(HiLd);
24794 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24797 LoAddr = St->getBasePtr();
24798 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24799 DAG.getConstant(4, MVT::i32));
24801 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24802 St->getPointerInfo(),
24803 St->isVolatile(), St->isNonTemporal(),
24804 St->getAlignment());
24805 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24806 St->getPointerInfo().getWithOffset(4),
24808 St->isNonTemporal(),
24809 MinAlign(St->getAlignment(), 4));
24810 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24815 /// Return 'true' if this vector operation is "horizontal"
24816 /// and return the operands for the horizontal operation in LHS and RHS. A
24817 /// horizontal operation performs the binary operation on successive elements
24818 /// of its first operand, then on successive elements of its second operand,
24819 /// returning the resulting values in a vector. For example, if
24820 /// A = < float a0, float a1, float a2, float a3 >
24822 /// B = < float b0, float b1, float b2, float b3 >
24823 /// then the result of doing a horizontal operation on A and B is
24824 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24825 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24826 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24827 /// set to A, RHS to B, and the routine returns 'true'.
24828 /// Note that the binary operation should have the property that if one of the
24829 /// operands is UNDEF then the result is UNDEF.
24830 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24831 // Look for the following pattern: if
24832 // A = < float a0, float a1, float a2, float a3 >
24833 // B = < float b0, float b1, float b2, float b3 >
24835 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24836 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24837 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24838 // which is A horizontal-op B.
24840 // At least one of the operands should be a vector shuffle.
24841 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24842 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24845 MVT VT = LHS.getSimpleValueType();
24847 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24848 "Unsupported vector type for horizontal add/sub");
24850 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24851 // operate independently on 128-bit lanes.
24852 unsigned NumElts = VT.getVectorNumElements();
24853 unsigned NumLanes = VT.getSizeInBits()/128;
24854 unsigned NumLaneElts = NumElts / NumLanes;
24855 assert((NumLaneElts % 2 == 0) &&
24856 "Vector type should have an even number of elements in each lane");
24857 unsigned HalfLaneElts = NumLaneElts/2;
24859 // View LHS in the form
24860 // LHS = VECTOR_SHUFFLE A, B, LMask
24861 // If LHS is not a shuffle then pretend it is the shuffle
24862 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24863 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24866 SmallVector<int, 16> LMask(NumElts);
24867 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24868 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24869 A = LHS.getOperand(0);
24870 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24871 B = LHS.getOperand(1);
24872 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24873 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24875 if (LHS.getOpcode() != ISD::UNDEF)
24877 for (unsigned i = 0; i != NumElts; ++i)
24881 // Likewise, view RHS in the form
24882 // RHS = VECTOR_SHUFFLE C, D, RMask
24884 SmallVector<int, 16> RMask(NumElts);
24885 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24886 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24887 C = RHS.getOperand(0);
24888 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24889 D = RHS.getOperand(1);
24890 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24891 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24893 if (RHS.getOpcode() != ISD::UNDEF)
24895 for (unsigned i = 0; i != NumElts; ++i)
24899 // Check that the shuffles are both shuffling the same vectors.
24900 if (!(A == C && B == D) && !(A == D && B == C))
24903 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24904 if (!A.getNode() && !B.getNode())
24907 // If A and B occur in reverse order in RHS, then "swap" them (which means
24908 // rewriting the mask).
24910 CommuteVectorShuffleMask(RMask, NumElts);
24912 // At this point LHS and RHS are equivalent to
24913 // LHS = VECTOR_SHUFFLE A, B, LMask
24914 // RHS = VECTOR_SHUFFLE A, B, RMask
24915 // Check that the masks correspond to performing a horizontal operation.
24916 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24917 for (unsigned i = 0; i != NumLaneElts; ++i) {
24918 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24920 // Ignore any UNDEF components.
24921 if (LIdx < 0 || RIdx < 0 ||
24922 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24923 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24926 // Check that successive elements are being operated on. If not, this is
24927 // not a horizontal operation.
24928 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24929 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24930 if (!(LIdx == Index && RIdx == Index + 1) &&
24931 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24936 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24937 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24941 /// Do target-specific dag combines on floating point adds.
24942 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24943 const X86Subtarget *Subtarget) {
24944 EVT VT = N->getValueType(0);
24945 SDValue LHS = N->getOperand(0);
24946 SDValue RHS = N->getOperand(1);
24948 // Try to synthesize horizontal adds from adds of shuffles.
24949 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24950 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24951 isHorizontalBinOp(LHS, RHS, true))
24952 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24956 /// Do target-specific dag combines on floating point subs.
24957 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24958 const X86Subtarget *Subtarget) {
24959 EVT VT = N->getValueType(0);
24960 SDValue LHS = N->getOperand(0);
24961 SDValue RHS = N->getOperand(1);
24963 // Try to synthesize horizontal subs from subs of shuffles.
24964 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24965 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24966 isHorizontalBinOp(LHS, RHS, false))
24967 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24971 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24972 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24973 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24974 // F[X]OR(0.0, x) -> x
24975 // F[X]OR(x, 0.0) -> x
24976 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24977 if (C->getValueAPF().isPosZero())
24978 return N->getOperand(1);
24979 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24980 if (C->getValueAPF().isPosZero())
24981 return N->getOperand(0);
24985 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24986 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24987 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24989 // Only perform optimizations if UnsafeMath is used.
24990 if (!DAG.getTarget().Options.UnsafeFPMath)
24993 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24994 // into FMINC and FMAXC, which are Commutative operations.
24995 unsigned NewOp = 0;
24996 switch (N->getOpcode()) {
24997 default: llvm_unreachable("unknown opcode");
24998 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24999 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25002 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25003 N->getOperand(0), N->getOperand(1));
25006 /// Do target-specific dag combines on X86ISD::FAND nodes.
25007 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25008 // FAND(0.0, x) -> 0.0
25009 // FAND(x, 0.0) -> 0.0
25010 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25011 if (C->getValueAPF().isPosZero())
25012 return N->getOperand(0);
25013 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25014 if (C->getValueAPF().isPosZero())
25015 return N->getOperand(1);
25019 /// Do target-specific dag combines on X86ISD::FANDN nodes
25020 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25021 // FANDN(x, 0.0) -> 0.0
25022 // FANDN(0.0, x) -> x
25023 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25024 if (C->getValueAPF().isPosZero())
25025 return N->getOperand(1);
25026 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25027 if (C->getValueAPF().isPosZero())
25028 return N->getOperand(1);
25032 static SDValue PerformBTCombine(SDNode *N,
25034 TargetLowering::DAGCombinerInfo &DCI) {
25035 // BT ignores high bits in the bit index operand.
25036 SDValue Op1 = N->getOperand(1);
25037 if (Op1.hasOneUse()) {
25038 unsigned BitWidth = Op1.getValueSizeInBits();
25039 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25040 APInt KnownZero, KnownOne;
25041 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25042 !DCI.isBeforeLegalizeOps());
25043 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25044 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25045 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25046 DCI.CommitTargetLoweringOpt(TLO);
25051 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25052 SDValue Op = N->getOperand(0);
25053 if (Op.getOpcode() == ISD::BITCAST)
25054 Op = Op.getOperand(0);
25055 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25056 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25057 VT.getVectorElementType().getSizeInBits() ==
25058 OpVT.getVectorElementType().getSizeInBits()) {
25059 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25064 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25065 const X86Subtarget *Subtarget) {
25066 EVT VT = N->getValueType(0);
25067 if (!VT.isVector())
25070 SDValue N0 = N->getOperand(0);
25071 SDValue N1 = N->getOperand(1);
25072 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25075 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25076 // both SSE and AVX2 since there is no sign-extended shift right
25077 // operation on a vector with 64-bit elements.
25078 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25079 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25080 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25081 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25082 SDValue N00 = N0.getOperand(0);
25084 // EXTLOAD has a better solution on AVX2,
25085 // it may be replaced with X86ISD::VSEXT node.
25086 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25087 if (!ISD::isNormalLoad(N00.getNode()))
25090 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25091 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25093 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25099 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25100 TargetLowering::DAGCombinerInfo &DCI,
25101 const X86Subtarget *Subtarget) {
25102 SDValue N0 = N->getOperand(0);
25103 EVT VT = N->getValueType(0);
25105 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25106 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25107 // This exposes the sext to the sdivrem lowering, so that it directly extends
25108 // from AH (which we otherwise need to do contortions to access).
25109 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25110 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
25112 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25113 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
25114 N0.getOperand(0), N0.getOperand(1));
25115 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25116 return R.getValue(1);
25119 if (!DCI.isBeforeLegalizeOps())
25122 if (!Subtarget->hasFp256())
25125 if (VT.isVector() && VT.getSizeInBits() == 256) {
25126 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25134 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25135 const X86Subtarget* Subtarget) {
25137 EVT VT = N->getValueType(0);
25139 // Let legalize expand this if it isn't a legal type yet.
25140 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25143 EVT ScalarVT = VT.getScalarType();
25144 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25145 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
25148 SDValue A = N->getOperand(0);
25149 SDValue B = N->getOperand(1);
25150 SDValue C = N->getOperand(2);
25152 bool NegA = (A.getOpcode() == ISD::FNEG);
25153 bool NegB = (B.getOpcode() == ISD::FNEG);
25154 bool NegC = (C.getOpcode() == ISD::FNEG);
25156 // Negative multiplication when NegA xor NegB
25157 bool NegMul = (NegA != NegB);
25159 A = A.getOperand(0);
25161 B = B.getOperand(0);
25163 C = C.getOperand(0);
25167 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25169 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25171 return DAG.getNode(Opcode, dl, VT, A, B, C);
25174 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25175 TargetLowering::DAGCombinerInfo &DCI,
25176 const X86Subtarget *Subtarget) {
25177 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25178 // (and (i32 x86isd::setcc_carry), 1)
25179 // This eliminates the zext. This transformation is necessary because
25180 // ISD::SETCC is always legalized to i8.
25182 SDValue N0 = N->getOperand(0);
25183 EVT VT = N->getValueType(0);
25185 if (N0.getOpcode() == ISD::AND &&
25187 N0.getOperand(0).hasOneUse()) {
25188 SDValue N00 = N0.getOperand(0);
25189 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25190 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25191 if (!C || C->getZExtValue() != 1)
25193 return DAG.getNode(ISD::AND, dl, VT,
25194 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25195 N00.getOperand(0), N00.getOperand(1)),
25196 DAG.getConstant(1, VT));
25200 if (N0.getOpcode() == ISD::TRUNCATE &&
25202 N0.getOperand(0).hasOneUse()) {
25203 SDValue N00 = N0.getOperand(0);
25204 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25205 return DAG.getNode(ISD::AND, dl, VT,
25206 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25207 N00.getOperand(0), N00.getOperand(1)),
25208 DAG.getConstant(1, VT));
25211 if (VT.is256BitVector()) {
25212 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25217 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25218 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25219 // This exposes the zext to the udivrem lowering, so that it directly extends
25220 // from AH (which we otherwise need to do contortions to access).
25221 if (N0.getOpcode() == ISD::UDIVREM &&
25222 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25223 (VT == MVT::i32 || VT == MVT::i64)) {
25224 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25225 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25226 N0.getOperand(0), N0.getOperand(1));
25227 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25228 return R.getValue(1);
25234 // Optimize x == -y --> x+y == 0
25235 // x != -y --> x+y != 0
25236 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25237 const X86Subtarget* Subtarget) {
25238 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25239 SDValue LHS = N->getOperand(0);
25240 SDValue RHS = N->getOperand(1);
25241 EVT VT = N->getValueType(0);
25244 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25245 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25246 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25247 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25248 LHS.getValueType(), RHS, LHS.getOperand(1));
25249 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25250 addV, DAG.getConstant(0, addV.getValueType()), CC);
25252 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25253 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25254 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25255 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25256 RHS.getValueType(), LHS, RHS.getOperand(1));
25257 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25258 addV, DAG.getConstant(0, addV.getValueType()), CC);
25261 if (VT.getScalarType() == MVT::i1) {
25262 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25263 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25264 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25265 if (!IsSEXT0 && !IsVZero0)
25267 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25268 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25269 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25271 if (!IsSEXT1 && !IsVZero1)
25274 if (IsSEXT0 && IsVZero1) {
25275 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25276 if (CC == ISD::SETEQ)
25277 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25278 return LHS.getOperand(0);
25280 if (IsSEXT1 && IsVZero0) {
25281 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25282 if (CC == ISD::SETEQ)
25283 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25284 return RHS.getOperand(0);
25291 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25292 const X86Subtarget *Subtarget) {
25294 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25295 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25296 "X86insertps is only defined for v4x32");
25298 SDValue Ld = N->getOperand(1);
25299 if (MayFoldLoad(Ld)) {
25300 // Extract the countS bits from the immediate so we can get the proper
25301 // address when narrowing the vector load to a specific element.
25302 // When the second source op is a memory address, interps doesn't use
25303 // countS and just gets an f32 from that address.
25304 unsigned DestIndex =
25305 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25306 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25310 // Create this as a scalar to vector to match the instruction pattern.
25311 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25312 // countS bits are ignored when loading from memory on insertps, which
25313 // means we don't need to explicitly set them to 0.
25314 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25315 LoadScalarToVector, N->getOperand(2));
25318 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25319 // as "sbb reg,reg", since it can be extended without zext and produces
25320 // an all-ones bit which is more useful than 0/1 in some cases.
25321 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25324 return DAG.getNode(ISD::AND, DL, VT,
25325 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25326 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25327 DAG.getConstant(1, VT));
25328 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25329 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25330 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25331 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25334 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25335 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25336 TargetLowering::DAGCombinerInfo &DCI,
25337 const X86Subtarget *Subtarget) {
25339 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25340 SDValue EFLAGS = N->getOperand(1);
25342 if (CC == X86::COND_A) {
25343 // Try to convert COND_A into COND_B in an attempt to facilitate
25344 // materializing "setb reg".
25346 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25347 // cannot take an immediate as its first operand.
25349 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25350 EFLAGS.getValueType().isInteger() &&
25351 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25352 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25353 EFLAGS.getNode()->getVTList(),
25354 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25355 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25356 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25360 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25361 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25363 if (CC == X86::COND_B)
25364 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25368 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25369 if (Flags.getNode()) {
25370 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25371 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25377 // Optimize branch condition evaluation.
25379 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25380 TargetLowering::DAGCombinerInfo &DCI,
25381 const X86Subtarget *Subtarget) {
25383 SDValue Chain = N->getOperand(0);
25384 SDValue Dest = N->getOperand(1);
25385 SDValue EFLAGS = N->getOperand(3);
25386 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25390 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25391 if (Flags.getNode()) {
25392 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25393 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25400 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25401 SelectionDAG &DAG) {
25402 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25403 // optimize away operation when it's from a constant.
25405 // The general transformation is:
25406 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25407 // AND(VECTOR_CMP(x,y), constant2)
25408 // constant2 = UNARYOP(constant)
25410 // Early exit if this isn't a vector operation, the operand of the
25411 // unary operation isn't a bitwise AND, or if the sizes of the operations
25412 // aren't the same.
25413 EVT VT = N->getValueType(0);
25414 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25415 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25416 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25419 // Now check that the other operand of the AND is a constant. We could
25420 // make the transformation for non-constant splats as well, but it's unclear
25421 // that would be a benefit as it would not eliminate any operations, just
25422 // perform one more step in scalar code before moving to the vector unit.
25423 if (BuildVectorSDNode *BV =
25424 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25425 // Bail out if the vector isn't a constant.
25426 if (!BV->isConstant())
25429 // Everything checks out. Build up the new and improved node.
25431 EVT IntVT = BV->getValueType(0);
25432 // Create a new constant of the appropriate type for the transformed
25434 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25435 // The AND node needs bitcasts to/from an integer vector type around it.
25436 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25437 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25438 N->getOperand(0)->getOperand(0), MaskConst);
25439 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25446 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25447 const X86TargetLowering *XTLI) {
25448 // First try to optimize away the conversion entirely when it's
25449 // conditionally from a constant. Vectors only.
25450 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25451 if (Res != SDValue())
25454 // Now move on to more general possibilities.
25455 SDValue Op0 = N->getOperand(0);
25456 EVT InVT = Op0->getValueType(0);
25458 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25459 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25461 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25462 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25463 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25466 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25467 // a 32-bit target where SSE doesn't support i64->FP operations.
25468 if (Op0.getOpcode() == ISD::LOAD) {
25469 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25470 EVT VT = Ld->getValueType(0);
25471 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25472 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25473 !XTLI->getSubtarget()->is64Bit() &&
25475 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25476 Ld->getChain(), Op0, DAG);
25477 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25484 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25485 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25486 X86TargetLowering::DAGCombinerInfo &DCI) {
25487 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25488 // the result is either zero or one (depending on the input carry bit).
25489 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25490 if (X86::isZeroNode(N->getOperand(0)) &&
25491 X86::isZeroNode(N->getOperand(1)) &&
25492 // We don't have a good way to replace an EFLAGS use, so only do this when
25494 SDValue(N, 1).use_empty()) {
25496 EVT VT = N->getValueType(0);
25497 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25498 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25499 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25500 DAG.getConstant(X86::COND_B,MVT::i8),
25502 DAG.getConstant(1, VT));
25503 return DCI.CombineTo(N, Res1, CarryOut);
25509 // fold (add Y, (sete X, 0)) -> adc 0, Y
25510 // (add Y, (setne X, 0)) -> sbb -1, Y
25511 // (sub (sete X, 0), Y) -> sbb 0, Y
25512 // (sub (setne X, 0), Y) -> adc -1, Y
25513 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25516 // Look through ZExts.
25517 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25518 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25521 SDValue SetCC = Ext.getOperand(0);
25522 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25525 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25526 if (CC != X86::COND_E && CC != X86::COND_NE)
25529 SDValue Cmp = SetCC.getOperand(1);
25530 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25531 !X86::isZeroNode(Cmp.getOperand(1)) ||
25532 !Cmp.getOperand(0).getValueType().isInteger())
25535 SDValue CmpOp0 = Cmp.getOperand(0);
25536 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25537 DAG.getConstant(1, CmpOp0.getValueType()));
25539 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25540 if (CC == X86::COND_NE)
25541 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25542 DL, OtherVal.getValueType(), OtherVal,
25543 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25544 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25545 DL, OtherVal.getValueType(), OtherVal,
25546 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25549 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25550 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25551 const X86Subtarget *Subtarget) {
25552 EVT VT = N->getValueType(0);
25553 SDValue Op0 = N->getOperand(0);
25554 SDValue Op1 = N->getOperand(1);
25556 // Try to synthesize horizontal adds from adds of shuffles.
25557 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25558 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25559 isHorizontalBinOp(Op0, Op1, true))
25560 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25562 return OptimizeConditionalInDecrement(N, DAG);
25565 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25566 const X86Subtarget *Subtarget) {
25567 SDValue Op0 = N->getOperand(0);
25568 SDValue Op1 = N->getOperand(1);
25570 // X86 can't encode an immediate LHS of a sub. See if we can push the
25571 // negation into a preceding instruction.
25572 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25573 // If the RHS of the sub is a XOR with one use and a constant, invert the
25574 // immediate. Then add one to the LHS of the sub so we can turn
25575 // X-Y -> X+~Y+1, saving one register.
25576 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25577 isa<ConstantSDNode>(Op1.getOperand(1))) {
25578 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25579 EVT VT = Op0.getValueType();
25580 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25582 DAG.getConstant(~XorC, VT));
25583 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25584 DAG.getConstant(C->getAPIntValue()+1, VT));
25588 // Try to synthesize horizontal adds from adds of shuffles.
25589 EVT VT = N->getValueType(0);
25590 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25591 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25592 isHorizontalBinOp(Op0, Op1, true))
25593 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25595 return OptimizeConditionalInDecrement(N, DAG);
25598 /// performVZEXTCombine - Performs build vector combines
25599 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25600 TargetLowering::DAGCombinerInfo &DCI,
25601 const X86Subtarget *Subtarget) {
25603 MVT VT = N->getSimpleValueType(0);
25604 SDValue Op = N->getOperand(0);
25605 MVT OpVT = Op.getSimpleValueType();
25606 MVT OpEltVT = OpVT.getVectorElementType();
25607 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25609 // (vzext (bitcast (vzext (x)) -> (vzext x)
25611 while (V.getOpcode() == ISD::BITCAST)
25612 V = V.getOperand(0);
25614 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25615 MVT InnerVT = V.getSimpleValueType();
25616 MVT InnerEltVT = InnerVT.getVectorElementType();
25618 // If the element sizes match exactly, we can just do one larger vzext. This
25619 // is always an exact type match as vzext operates on integer types.
25620 if (OpEltVT == InnerEltVT) {
25621 assert(OpVT == InnerVT && "Types must match for vzext!");
25622 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25625 // The only other way we can combine them is if only a single element of the
25626 // inner vzext is used in the input to the outer vzext.
25627 if (InnerEltVT.getSizeInBits() < InputBits)
25630 // In this case, the inner vzext is completely dead because we're going to
25631 // only look at bits inside of the low element. Just do the outer vzext on
25632 // a bitcast of the input to the inner.
25633 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25634 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25637 // Check if we can bypass extracting and re-inserting an element of an input
25638 // vector. Essentialy:
25639 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25640 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25641 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25642 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25643 SDValue ExtractedV = V.getOperand(0);
25644 SDValue OrigV = ExtractedV.getOperand(0);
25645 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25646 if (ExtractIdx->getZExtValue() == 0) {
25647 MVT OrigVT = OrigV.getSimpleValueType();
25648 // Extract a subvector if necessary...
25649 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25650 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25651 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25652 OrigVT.getVectorNumElements() / Ratio);
25653 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25654 DAG.getIntPtrConstant(0));
25656 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25657 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25664 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25665 DAGCombinerInfo &DCI) const {
25666 SelectionDAG &DAG = DCI.DAG;
25667 switch (N->getOpcode()) {
25669 case ISD::EXTRACT_VECTOR_ELT:
25670 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25673 case X86ISD::SHRUNKBLEND:
25674 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25675 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25676 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25677 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25678 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25679 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25682 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25683 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25684 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25685 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25686 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25687 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25688 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25689 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25690 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25692 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25694 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25695 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25696 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25697 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25698 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25699 case ISD::ANY_EXTEND:
25700 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25701 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25702 case ISD::SIGN_EXTEND_INREG:
25703 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25704 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25705 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25706 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25707 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25708 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25709 case X86ISD::SHUFP: // Handle all target specific shuffles
25710 case X86ISD::PALIGNR:
25711 case X86ISD::UNPCKH:
25712 case X86ISD::UNPCKL:
25713 case X86ISD::MOVHLPS:
25714 case X86ISD::MOVLHPS:
25715 case X86ISD::PSHUFB:
25716 case X86ISD::PSHUFD:
25717 case X86ISD::PSHUFHW:
25718 case X86ISD::PSHUFLW:
25719 case X86ISD::MOVSS:
25720 case X86ISD::MOVSD:
25721 case X86ISD::VPERMILPI:
25722 case X86ISD::VPERM2X128:
25723 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25724 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25725 case ISD::INTRINSIC_WO_CHAIN:
25726 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25727 case X86ISD::INSERTPS:
25728 return PerformINSERTPSCombine(N, DAG, Subtarget);
25729 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25735 /// isTypeDesirableForOp - Return true if the target has native support for
25736 /// the specified value type and it is 'desirable' to use the type for the
25737 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25738 /// instruction encodings are longer and some i16 instructions are slow.
25739 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25740 if (!isTypeLegal(VT))
25742 if (VT != MVT::i16)
25749 case ISD::SIGN_EXTEND:
25750 case ISD::ZERO_EXTEND:
25751 case ISD::ANY_EXTEND:
25764 /// IsDesirableToPromoteOp - This method query the target whether it is
25765 /// beneficial for dag combiner to promote the specified node. If true, it
25766 /// should return the desired promotion type by reference.
25767 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25768 EVT VT = Op.getValueType();
25769 if (VT != MVT::i16)
25772 bool Promote = false;
25773 bool Commute = false;
25774 switch (Op.getOpcode()) {
25777 LoadSDNode *LD = cast<LoadSDNode>(Op);
25778 // If the non-extending load has a single use and it's not live out, then it
25779 // might be folded.
25780 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25781 Op.hasOneUse()*/) {
25782 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25783 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25784 // The only case where we'd want to promote LOAD (rather then it being
25785 // promoted as an operand is when it's only use is liveout.
25786 if (UI->getOpcode() != ISD::CopyToReg)
25793 case ISD::SIGN_EXTEND:
25794 case ISD::ZERO_EXTEND:
25795 case ISD::ANY_EXTEND:
25800 SDValue N0 = Op.getOperand(0);
25801 // Look out for (store (shl (load), x)).
25802 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25815 SDValue N0 = Op.getOperand(0);
25816 SDValue N1 = Op.getOperand(1);
25817 if (!Commute && MayFoldLoad(N1))
25819 // Avoid disabling potential load folding opportunities.
25820 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25822 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25832 //===----------------------------------------------------------------------===//
25833 // X86 Inline Assembly Support
25834 //===----------------------------------------------------------------------===//
25837 // Helper to match a string separated by whitespace.
25838 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25839 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25841 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25842 StringRef piece(*args[i]);
25843 if (!s.startswith(piece)) // Check if the piece matches.
25846 s = s.substr(piece.size());
25847 StringRef::size_type pos = s.find_first_not_of(" \t");
25848 if (pos == 0) // We matched a prefix.
25856 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25859 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25861 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25862 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25863 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25864 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25866 if (AsmPieces.size() == 3)
25868 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25875 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25876 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25878 std::string AsmStr = IA->getAsmString();
25880 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25881 if (!Ty || Ty->getBitWidth() % 16 != 0)
25884 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25885 SmallVector<StringRef, 4> AsmPieces;
25886 SplitString(AsmStr, AsmPieces, ";\n");
25888 switch (AsmPieces.size()) {
25889 default: return false;
25891 // FIXME: this should verify that we are targeting a 486 or better. If not,
25892 // we will turn this bswap into something that will be lowered to logical
25893 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25894 // lower so don't worry about this.
25896 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25897 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25898 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25899 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25900 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25901 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25902 // No need to check constraints, nothing other than the equivalent of
25903 // "=r,0" would be valid here.
25904 return IntrinsicLowering::LowerToByteSwap(CI);
25907 // rorw $$8, ${0:w} --> llvm.bswap.i16
25908 if (CI->getType()->isIntegerTy(16) &&
25909 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25910 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25911 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25913 const std::string &ConstraintsStr = IA->getConstraintString();
25914 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25915 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25916 if (clobbersFlagRegisters(AsmPieces))
25917 return IntrinsicLowering::LowerToByteSwap(CI);
25921 if (CI->getType()->isIntegerTy(32) &&
25922 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25923 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25924 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25925 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25927 const std::string &ConstraintsStr = IA->getConstraintString();
25928 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25929 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25930 if (clobbersFlagRegisters(AsmPieces))
25931 return IntrinsicLowering::LowerToByteSwap(CI);
25934 if (CI->getType()->isIntegerTy(64)) {
25935 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25936 if (Constraints.size() >= 2 &&
25937 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25938 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25939 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25940 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25941 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25942 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25943 return IntrinsicLowering::LowerToByteSwap(CI);
25951 /// getConstraintType - Given a constraint letter, return the type of
25952 /// constraint it is for this target.
25953 X86TargetLowering::ConstraintType
25954 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25955 if (Constraint.size() == 1) {
25956 switch (Constraint[0]) {
25967 return C_RegisterClass;
25991 return TargetLowering::getConstraintType(Constraint);
25994 /// Examine constraint type and operand type and determine a weight value.
25995 /// This object must already have been set up with the operand type
25996 /// and the current alternative constraint selected.
25997 TargetLowering::ConstraintWeight
25998 X86TargetLowering::getSingleConstraintMatchWeight(
25999 AsmOperandInfo &info, const char *constraint) const {
26000 ConstraintWeight weight = CW_Invalid;
26001 Value *CallOperandVal = info.CallOperandVal;
26002 // If we don't have a value, we can't do a match,
26003 // but allow it at the lowest weight.
26004 if (!CallOperandVal)
26006 Type *type = CallOperandVal->getType();
26007 // Look at the constraint type.
26008 switch (*constraint) {
26010 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26021 if (CallOperandVal->getType()->isIntegerTy())
26022 weight = CW_SpecificReg;
26027 if (type->isFloatingPointTy())
26028 weight = CW_SpecificReg;
26031 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26032 weight = CW_SpecificReg;
26036 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26037 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26038 weight = CW_Register;
26041 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26042 if (C->getZExtValue() <= 31)
26043 weight = CW_Constant;
26047 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26048 if (C->getZExtValue() <= 63)
26049 weight = CW_Constant;
26053 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26054 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26055 weight = CW_Constant;
26059 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26060 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26061 weight = CW_Constant;
26065 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26066 if (C->getZExtValue() <= 3)
26067 weight = CW_Constant;
26071 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26072 if (C->getZExtValue() <= 0xff)
26073 weight = CW_Constant;
26078 if (dyn_cast<ConstantFP>(CallOperandVal)) {
26079 weight = CW_Constant;
26083 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26084 if ((C->getSExtValue() >= -0x80000000LL) &&
26085 (C->getSExtValue() <= 0x7fffffffLL))
26086 weight = CW_Constant;
26090 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26091 if (C->getZExtValue() <= 0xffffffff)
26092 weight = CW_Constant;
26099 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26100 /// with another that has more specific requirements based on the type of the
26101 /// corresponding operand.
26102 const char *X86TargetLowering::
26103 LowerXConstraint(EVT ConstraintVT) const {
26104 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26105 // 'f' like normal targets.
26106 if (ConstraintVT.isFloatingPoint()) {
26107 if (Subtarget->hasSSE2())
26109 if (Subtarget->hasSSE1())
26113 return TargetLowering::LowerXConstraint(ConstraintVT);
26116 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26117 /// vector. If it is invalid, don't add anything to Ops.
26118 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26119 std::string &Constraint,
26120 std::vector<SDValue>&Ops,
26121 SelectionDAG &DAG) const {
26124 // Only support length 1 constraints for now.
26125 if (Constraint.length() > 1) return;
26127 char ConstraintLetter = Constraint[0];
26128 switch (ConstraintLetter) {
26131 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26132 if (C->getZExtValue() <= 31) {
26133 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26139 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26140 if (C->getZExtValue() <= 63) {
26141 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26147 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26148 if (isInt<8>(C->getSExtValue())) {
26149 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26155 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26156 if (C->getZExtValue() <= 255) {
26157 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26163 // 32-bit signed value
26164 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26165 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26166 C->getSExtValue())) {
26167 // Widen to 64 bits here to get it sign extended.
26168 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26171 // FIXME gcc accepts some relocatable values here too, but only in certain
26172 // memory models; it's complicated.
26177 // 32-bit unsigned value
26178 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26179 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26180 C->getZExtValue())) {
26181 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26185 // FIXME gcc accepts some relocatable values here too, but only in certain
26186 // memory models; it's complicated.
26190 // Literal immediates are always ok.
26191 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26192 // Widen to 64 bits here to get it sign extended.
26193 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26197 // In any sort of PIC mode addresses need to be computed at runtime by
26198 // adding in a register or some sort of table lookup. These can't
26199 // be used as immediates.
26200 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26203 // If we are in non-pic codegen mode, we allow the address of a global (with
26204 // an optional displacement) to be used with 'i'.
26205 GlobalAddressSDNode *GA = nullptr;
26206 int64_t Offset = 0;
26208 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26210 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26211 Offset += GA->getOffset();
26213 } else if (Op.getOpcode() == ISD::ADD) {
26214 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26215 Offset += C->getZExtValue();
26216 Op = Op.getOperand(0);
26219 } else if (Op.getOpcode() == ISD::SUB) {
26220 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26221 Offset += -C->getZExtValue();
26222 Op = Op.getOperand(0);
26227 // Otherwise, this isn't something we can handle, reject it.
26231 const GlobalValue *GV = GA->getGlobal();
26232 // If we require an extra load to get this address, as in PIC mode, we
26233 // can't accept it.
26234 if (isGlobalStubReference(
26235 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26238 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26239 GA->getValueType(0), Offset);
26244 if (Result.getNode()) {
26245 Ops.push_back(Result);
26248 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26251 std::pair<unsigned, const TargetRegisterClass*>
26252 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26254 // First, see if this is a constraint that directly corresponds to an LLVM
26256 if (Constraint.size() == 1) {
26257 // GCC Constraint Letters
26258 switch (Constraint[0]) {
26260 // TODO: Slight differences here in allocation order and leaving
26261 // RIP in the class. Do they matter any more here than they do
26262 // in the normal allocation?
26263 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26264 if (Subtarget->is64Bit()) {
26265 if (VT == MVT::i32 || VT == MVT::f32)
26266 return std::make_pair(0U, &X86::GR32RegClass);
26267 if (VT == MVT::i16)
26268 return std::make_pair(0U, &X86::GR16RegClass);
26269 if (VT == MVT::i8 || VT == MVT::i1)
26270 return std::make_pair(0U, &X86::GR8RegClass);
26271 if (VT == MVT::i64 || VT == MVT::f64)
26272 return std::make_pair(0U, &X86::GR64RegClass);
26275 // 32-bit fallthrough
26276 case 'Q': // Q_REGS
26277 if (VT == MVT::i32 || VT == MVT::f32)
26278 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26279 if (VT == MVT::i16)
26280 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26281 if (VT == MVT::i8 || VT == MVT::i1)
26282 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26283 if (VT == MVT::i64)
26284 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26286 case 'r': // GENERAL_REGS
26287 case 'l': // INDEX_REGS
26288 if (VT == MVT::i8 || VT == MVT::i1)
26289 return std::make_pair(0U, &X86::GR8RegClass);
26290 if (VT == MVT::i16)
26291 return std::make_pair(0U, &X86::GR16RegClass);
26292 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26293 return std::make_pair(0U, &X86::GR32RegClass);
26294 return std::make_pair(0U, &X86::GR64RegClass);
26295 case 'R': // LEGACY_REGS
26296 if (VT == MVT::i8 || VT == MVT::i1)
26297 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26298 if (VT == MVT::i16)
26299 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26300 if (VT == MVT::i32 || !Subtarget->is64Bit())
26301 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26302 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26303 case 'f': // FP Stack registers.
26304 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26305 // value to the correct fpstack register class.
26306 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26307 return std::make_pair(0U, &X86::RFP32RegClass);
26308 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26309 return std::make_pair(0U, &X86::RFP64RegClass);
26310 return std::make_pair(0U, &X86::RFP80RegClass);
26311 case 'y': // MMX_REGS if MMX allowed.
26312 if (!Subtarget->hasMMX()) break;
26313 return std::make_pair(0U, &X86::VR64RegClass);
26314 case 'Y': // SSE_REGS if SSE2 allowed
26315 if (!Subtarget->hasSSE2()) break;
26317 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26318 if (!Subtarget->hasSSE1()) break;
26320 switch (VT.SimpleTy) {
26322 // Scalar SSE types.
26325 return std::make_pair(0U, &X86::FR32RegClass);
26328 return std::make_pair(0U, &X86::FR64RegClass);
26336 return std::make_pair(0U, &X86::VR128RegClass);
26344 return std::make_pair(0U, &X86::VR256RegClass);
26349 return std::make_pair(0U, &X86::VR512RegClass);
26355 // Use the default implementation in TargetLowering to convert the register
26356 // constraint into a member of a register class.
26357 std::pair<unsigned, const TargetRegisterClass*> Res;
26358 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26360 // Not found as a standard register?
26362 // Map st(0) -> st(7) -> ST0
26363 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26364 tolower(Constraint[1]) == 's' &&
26365 tolower(Constraint[2]) == 't' &&
26366 Constraint[3] == '(' &&
26367 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26368 Constraint[5] == ')' &&
26369 Constraint[6] == '}') {
26371 Res.first = X86::FP0+Constraint[4]-'0';
26372 Res.second = &X86::RFP80RegClass;
26376 // GCC allows "st(0)" to be called just plain "st".
26377 if (StringRef("{st}").equals_lower(Constraint)) {
26378 Res.first = X86::FP0;
26379 Res.second = &X86::RFP80RegClass;
26384 if (StringRef("{flags}").equals_lower(Constraint)) {
26385 Res.first = X86::EFLAGS;
26386 Res.second = &X86::CCRRegClass;
26390 // 'A' means EAX + EDX.
26391 if (Constraint == "A") {
26392 Res.first = X86::EAX;
26393 Res.second = &X86::GR32_ADRegClass;
26399 // Otherwise, check to see if this is a register class of the wrong value
26400 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26401 // turn into {ax},{dx}.
26402 if (Res.second->hasType(VT))
26403 return Res; // Correct type already, nothing to do.
26405 // All of the single-register GCC register classes map their values onto
26406 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26407 // really want an 8-bit or 32-bit register, map to the appropriate register
26408 // class and return the appropriate register.
26409 if (Res.second == &X86::GR16RegClass) {
26410 if (VT == MVT::i8 || VT == MVT::i1) {
26411 unsigned DestReg = 0;
26412 switch (Res.first) {
26414 case X86::AX: DestReg = X86::AL; break;
26415 case X86::DX: DestReg = X86::DL; break;
26416 case X86::CX: DestReg = X86::CL; break;
26417 case X86::BX: DestReg = X86::BL; break;
26420 Res.first = DestReg;
26421 Res.second = &X86::GR8RegClass;
26423 } else if (VT == MVT::i32 || VT == MVT::f32) {
26424 unsigned DestReg = 0;
26425 switch (Res.first) {
26427 case X86::AX: DestReg = X86::EAX; break;
26428 case X86::DX: DestReg = X86::EDX; break;
26429 case X86::CX: DestReg = X86::ECX; break;
26430 case X86::BX: DestReg = X86::EBX; break;
26431 case X86::SI: DestReg = X86::ESI; break;
26432 case X86::DI: DestReg = X86::EDI; break;
26433 case X86::BP: DestReg = X86::EBP; break;
26434 case X86::SP: DestReg = X86::ESP; break;
26437 Res.first = DestReg;
26438 Res.second = &X86::GR32RegClass;
26440 } else if (VT == MVT::i64 || VT == MVT::f64) {
26441 unsigned DestReg = 0;
26442 switch (Res.first) {
26444 case X86::AX: DestReg = X86::RAX; break;
26445 case X86::DX: DestReg = X86::RDX; break;
26446 case X86::CX: DestReg = X86::RCX; break;
26447 case X86::BX: DestReg = X86::RBX; break;
26448 case X86::SI: DestReg = X86::RSI; break;
26449 case X86::DI: DestReg = X86::RDI; break;
26450 case X86::BP: DestReg = X86::RBP; break;
26451 case X86::SP: DestReg = X86::RSP; break;
26454 Res.first = DestReg;
26455 Res.second = &X86::GR64RegClass;
26458 } else if (Res.second == &X86::FR32RegClass ||
26459 Res.second == &X86::FR64RegClass ||
26460 Res.second == &X86::VR128RegClass ||
26461 Res.second == &X86::VR256RegClass ||
26462 Res.second == &X86::FR32XRegClass ||
26463 Res.second == &X86::FR64XRegClass ||
26464 Res.second == &X86::VR128XRegClass ||
26465 Res.second == &X86::VR256XRegClass ||
26466 Res.second == &X86::VR512RegClass) {
26467 // Handle references to XMM physical registers that got mapped into the
26468 // wrong class. This can happen with constraints like {xmm0} where the
26469 // target independent register mapper will just pick the first match it can
26470 // find, ignoring the required type.
26472 if (VT == MVT::f32 || VT == MVT::i32)
26473 Res.second = &X86::FR32RegClass;
26474 else if (VT == MVT::f64 || VT == MVT::i64)
26475 Res.second = &X86::FR64RegClass;
26476 else if (X86::VR128RegClass.hasType(VT))
26477 Res.second = &X86::VR128RegClass;
26478 else if (X86::VR256RegClass.hasType(VT))
26479 Res.second = &X86::VR256RegClass;
26480 else if (X86::VR512RegClass.hasType(VT))
26481 Res.second = &X86::VR512RegClass;
26487 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26489 // Scaling factors are not free at all.
26490 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26491 // will take 2 allocations in the out of order engine instead of 1
26492 // for plain addressing mode, i.e. inst (reg1).
26494 // vaddps (%rsi,%drx), %ymm0, %ymm1
26495 // Requires two allocations (one for the load, one for the computation)
26497 // vaddps (%rsi), %ymm0, %ymm1
26498 // Requires just 1 allocation, i.e., freeing allocations for other operations
26499 // and having less micro operations to execute.
26501 // For some X86 architectures, this is even worse because for instance for
26502 // stores, the complex addressing mode forces the instruction to use the
26503 // "load" ports instead of the dedicated "store" port.
26504 // E.g., on Haswell:
26505 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26506 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26507 if (isLegalAddressingMode(AM, Ty))
26508 // Scale represents reg2 * scale, thus account for 1
26509 // as soon as we use a second register.
26510 return AM.Scale != 0;
26514 bool X86TargetLowering::isTargetFTOL() const {
26515 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();