1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86ShuffleDecode.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/Dwarf.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
54 using namespace dwarf;
56 STATISTIC(NumTailCalls, "Number of tail calls");
59 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
61 // Forward declarations.
62 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
65 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
67 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
69 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
70 if (is64Bit) return new X8664_MachoTargetObjectFile();
71 return new TargetLoweringObjectFileMachO();
72 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
73 if (is64Bit) return new X8664_ELFTargetObjectFile(TM);
74 return new X8632_ELFTargetObjectFile(TM);
75 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) {
76 return new TargetLoweringObjectFileCOFF();
78 llvm_unreachable("unknown subtarget type");
81 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
82 : TargetLowering(TM, createTLOF(TM)) {
83 Subtarget = &TM.getSubtarget<X86Subtarget>();
84 X86ScalarSSEf64 = Subtarget->hasSSE2();
85 X86ScalarSSEf32 = Subtarget->hasSSE1();
86 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
88 RegInfo = TM.getRegisterInfo();
91 // Set up the TargetLowering object.
93 // X86 is weird, it always uses i8 for shift amounts and setcc results.
94 setShiftAmountType(MVT::i8);
95 setBooleanContents(ZeroOrOneBooleanContent);
96 setSchedulingPreference(Sched::RegPressure);
97 setStackPointerRegisterToSaveRestore(X86StackPtr);
99 if (Subtarget->isTargetDarwin()) {
100 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
101 setUseUnderscoreSetJmp(false);
102 setUseUnderscoreLongJmp(false);
103 } else if (Subtarget->isTargetMingw()) {
104 // MS runtime is weird: it exports _setjmp, but longjmp!
105 setUseUnderscoreSetJmp(true);
106 setUseUnderscoreLongJmp(false);
108 setUseUnderscoreSetJmp(true);
109 setUseUnderscoreLongJmp(true);
112 // Set up the register classes.
113 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
114 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
115 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
116 if (Subtarget->is64Bit())
117 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
119 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
121 // We don't accept any truncstore of integer registers.
122 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
124 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
125 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
127 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
129 // SETOEQ and SETUNE require checking two conditions.
130 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
131 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
132 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
133 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
135 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
137 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
139 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
140 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
141 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
143 if (Subtarget->is64Bit()) {
144 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
145 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
146 } else if (!UseSoftFloat) {
147 // We have an algorithm for SSE2->double, and we turn this into a
148 // 64-bit FILD followed by conditional FADD for other targets.
149 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
150 // We have an algorithm for SSE2, and we turn this into a 64-bit
151 // FILD for other targets.
152 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
155 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
157 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
158 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
161 // SSE has no i16 to fp conversion, only i32
162 if (X86ScalarSSEf32) {
163 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
164 // f32 and f64 cases are Legal, f80 case is not
165 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
167 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
168 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
172 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
175 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
176 // are Legal, f80 is custom lowered.
177 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
178 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
180 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
182 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
183 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
185 if (X86ScalarSSEf32) {
186 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
187 // f32 and f64 cases are Legal, f80 case is not
188 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
190 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
191 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
194 // Handle FP_TO_UINT by promoting the destination to a larger signed
196 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
197 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
198 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
200 if (Subtarget->is64Bit()) {
201 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
202 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
203 } else if (!UseSoftFloat) {
204 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
205 // Expand FP_TO_UINT into a select.
206 // FIXME: We would like to use a Custom expander here eventually to do
207 // the optimal thing for SSE vs. the default expansion in the legalizer.
208 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
210 // With SSE3 we can use fisttpll to convert to a signed i64; without
211 // SSE, we're stuck with a fistpll.
212 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
215 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
216 if (!X86ScalarSSEf64) {
217 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
218 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
219 if (Subtarget->is64Bit()) {
220 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
221 // Without SSE, i64->f64 goes through memory; i64->MMX is Legal.
222 if (Subtarget->hasMMX() && !DisableMMX)
223 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom);
225 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
229 // Scalar integer divide and remainder are lowered to use operations that
230 // produce two results, to match the available instructions. This exposes
231 // the two-result form to trivial CSE, which is able to combine x/y and x%y
232 // into a single instruction.
234 // Scalar integer multiply-high is also lowered to use two-result
235 // operations, to match the available instructions. However, plain multiply
236 // (low) operations are left as Legal, as there are single-result
237 // instructions for this in x86. Using the two-result multiply instructions
238 // when both high and low results are needed must be arranged by dagcombine.
239 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
240 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
241 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
242 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
243 setOperationAction(ISD::SREM , MVT::i8 , Expand);
244 setOperationAction(ISD::UREM , MVT::i8 , Expand);
245 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
246 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
247 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
248 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
249 setOperationAction(ISD::SREM , MVT::i16 , Expand);
250 setOperationAction(ISD::UREM , MVT::i16 , Expand);
251 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
252 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
253 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
254 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
255 setOperationAction(ISD::SREM , MVT::i32 , Expand);
256 setOperationAction(ISD::UREM , MVT::i32 , Expand);
257 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
258 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
259 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
260 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
261 setOperationAction(ISD::SREM , MVT::i64 , Expand);
262 setOperationAction(ISD::UREM , MVT::i64 , Expand);
264 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
265 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
266 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
267 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
268 if (Subtarget->is64Bit())
269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
273 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
274 setOperationAction(ISD::FREM , MVT::f32 , Expand);
275 setOperationAction(ISD::FREM , MVT::f64 , Expand);
276 setOperationAction(ISD::FREM , MVT::f80 , Expand);
277 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
279 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
280 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
281 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
282 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
283 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
285 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
286 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
287 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
288 if (Subtarget->is64Bit()) {
289 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
290 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
291 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
294 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
295 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
297 // These should be promoted to a larger select which is supported.
298 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
299 // X86 wants to expand cmov itself.
300 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
302 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
303 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
304 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
305 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
306 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
307 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
308 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
309 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
310 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
311 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
312 if (Subtarget->is64Bit()) {
313 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
314 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
316 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
319 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
320 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
321 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
322 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
323 if (Subtarget->is64Bit())
324 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
325 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
326 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
327 if (Subtarget->is64Bit()) {
328 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
329 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
330 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
331 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
332 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
334 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
335 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
336 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
337 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
338 if (Subtarget->is64Bit()) {
339 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
340 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
341 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
344 if (Subtarget->hasSSE1())
345 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
347 // We may not have a libcall for MEMBARRIER so we should lower this.
348 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
350 // On X86 and X86-64, atomic operations are lowered to locked instructions.
351 // Locked instructions, in turn, have implicit fence semantics (all memory
352 // operations are flushed before issuing the locked instruction, and they
353 // are not buffered), so we can fold away the common pattern of
354 // fence-atomic-fence.
355 setShouldFoldAtomicFences(true);
357 // Expand certain atomics
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
360 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
361 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
365 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
366 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
368 if (!Subtarget->is64Bit()) {
369 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
374 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
375 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
378 // FIXME - use subtarget debug flags
379 if (!Subtarget->isTargetDarwin() &&
380 !Subtarget->isTargetELF() &&
381 !Subtarget->isTargetCygMing()) {
382 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
385 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
386 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
387 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
388 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
389 if (Subtarget->is64Bit()) {
390 setExceptionPointerRegister(X86::RAX);
391 setExceptionSelectorRegister(X86::RDX);
393 setExceptionPointerRegister(X86::EAX);
394 setExceptionSelectorRegister(X86::EDX);
396 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
397 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
399 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
401 setOperationAction(ISD::TRAP, MVT::Other, Legal);
403 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
404 setOperationAction(ISD::VASTART , MVT::Other, Custom);
405 setOperationAction(ISD::VAEND , MVT::Other, Expand);
406 if (Subtarget->is64Bit()) {
407 setOperationAction(ISD::VAARG , MVT::Other, Custom);
408 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
410 setOperationAction(ISD::VAARG , MVT::Other, Expand);
411 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
414 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
415 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
416 if (Subtarget->is64Bit())
417 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
418 if (Subtarget->isTargetCygMing())
419 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
421 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
423 if (!UseSoftFloat && X86ScalarSSEf64) {
424 // f32 and f64 use SSE.
425 // Set up the FP register classes.
426 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
427 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
429 // Use ANDPD to simulate FABS.
430 setOperationAction(ISD::FABS , MVT::f64, Custom);
431 setOperationAction(ISD::FABS , MVT::f32, Custom);
433 // Use XORP to simulate FNEG.
434 setOperationAction(ISD::FNEG , MVT::f64, Custom);
435 setOperationAction(ISD::FNEG , MVT::f32, Custom);
437 // Use ANDPD and ORPD to simulate FCOPYSIGN.
438 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
439 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
441 // We don't support sin/cos/fmod
442 setOperationAction(ISD::FSIN , MVT::f64, Expand);
443 setOperationAction(ISD::FCOS , MVT::f64, Expand);
444 setOperationAction(ISD::FSIN , MVT::f32, Expand);
445 setOperationAction(ISD::FCOS , MVT::f32, Expand);
447 // Expand FP immediates into loads from the stack, except for the special
449 addLegalFPImmediate(APFloat(+0.0)); // xorpd
450 addLegalFPImmediate(APFloat(+0.0f)); // xorps
451 } else if (!UseSoftFloat && X86ScalarSSEf32) {
452 // Use SSE for f32, x87 for f64.
453 // Set up the FP register classes.
454 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
455 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
457 // Use ANDPS to simulate FABS.
458 setOperationAction(ISD::FABS , MVT::f32, Custom);
460 // Use XORP to simulate FNEG.
461 setOperationAction(ISD::FNEG , MVT::f32, Custom);
463 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
465 // Use ANDPS and ORPS to simulate FCOPYSIGN.
466 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
467 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
469 // We don't support sin/cos/fmod
470 setOperationAction(ISD::FSIN , MVT::f32, Expand);
471 setOperationAction(ISD::FCOS , MVT::f32, Expand);
473 // Special cases we handle for FP constants.
474 addLegalFPImmediate(APFloat(+0.0f)); // xorps
475 addLegalFPImmediate(APFloat(+0.0)); // FLD0
476 addLegalFPImmediate(APFloat(+1.0)); // FLD1
477 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
478 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
481 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
482 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
484 } else if (!UseSoftFloat) {
485 // f32 and f64 in x87.
486 // Set up the FP register classes.
487 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
488 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
490 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
491 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
492 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
493 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
496 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
497 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
499 addLegalFPImmediate(APFloat(+0.0)); // FLD0
500 addLegalFPImmediate(APFloat(+1.0)); // FLD1
501 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
502 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
503 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
504 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
505 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
506 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
509 // Long double always uses X87.
511 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
512 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
513 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
516 APFloat TmpFlt(+0.0);
517 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
519 addLegalFPImmediate(TmpFlt); // FLD0
521 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
522 APFloat TmpFlt2(+1.0);
523 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
525 addLegalFPImmediate(TmpFlt2); // FLD1
526 TmpFlt2.changeSign();
527 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
531 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
532 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
536 // Always use a library call for pow.
537 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
538 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
539 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
541 setOperationAction(ISD::FLOG, MVT::f80, Expand);
542 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
543 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
544 setOperationAction(ISD::FEXP, MVT::f80, Expand);
545 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
547 // First set operation action for all vector types to either promote
548 // (for widening) or expand (for scalarization). Then we will selectively
549 // turn on ones that can be effectively codegen'd.
550 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
551 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
552 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
567 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
568 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
601 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
605 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
606 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
607 setTruncStoreAction((MVT::SimpleValueType)VT,
608 (MVT::SimpleValueType)InnerVT, Expand);
609 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
610 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
611 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
614 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
615 // with -msoft-float, disable use of MMX as well.
616 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
617 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false);
618 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
619 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
621 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
623 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
624 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
625 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
626 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
628 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
629 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
630 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
631 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
633 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
634 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
636 setOperationAction(ISD::AND, MVT::v8i8, Promote);
637 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
638 setOperationAction(ISD::AND, MVT::v4i16, Promote);
639 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
640 setOperationAction(ISD::AND, MVT::v2i32, Promote);
641 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
642 setOperationAction(ISD::AND, MVT::v1i64, Legal);
644 setOperationAction(ISD::OR, MVT::v8i8, Promote);
645 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
646 setOperationAction(ISD::OR, MVT::v4i16, Promote);
647 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
648 setOperationAction(ISD::OR, MVT::v2i32, Promote);
649 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
650 setOperationAction(ISD::OR, MVT::v1i64, Legal);
652 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
653 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
654 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
655 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
656 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
657 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
658 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
660 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
661 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
662 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
663 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
664 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
665 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
666 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
668 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
669 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
670 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
671 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
675 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
676 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
678 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
679 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
680 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
682 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
684 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
685 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
686 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
687 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
688 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
689 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
690 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
692 if (!X86ScalarSSEf64 && Subtarget->is64Bit()) {
693 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom);
694 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom);
695 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom);
696 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom);
700 if (!UseSoftFloat && Subtarget->hasSSE1()) {
701 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
703 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
704 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
705 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
706 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
707 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
708 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
709 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
710 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
711 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
712 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
713 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
714 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
717 if (!UseSoftFloat && Subtarget->hasSSE2()) {
718 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
720 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
721 // registers cannot be used even for integer operations.
722 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
723 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
724 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
725 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
727 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
728 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
729 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
730 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
731 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
732 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
733 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
734 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
735 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
736 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
737 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
738 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
739 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
740 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
741 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
742 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
744 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
745 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
746 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
747 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
750 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
751 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
752 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
753 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
755 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
756 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
757 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
758 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
759 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
761 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
762 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
763 EVT VT = (MVT::SimpleValueType)i;
764 // Do not attempt to custom lower non-power-of-2 vectors
765 if (!isPowerOf2_32(VT.getVectorNumElements()))
767 // Do not attempt to custom lower non-128-bit vectors
768 if (!VT.is128BitVector())
770 setOperationAction(ISD::BUILD_VECTOR,
771 VT.getSimpleVT().SimpleTy, Custom);
772 setOperationAction(ISD::VECTOR_SHUFFLE,
773 VT.getSimpleVT().SimpleTy, Custom);
774 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
775 VT.getSimpleVT().SimpleTy, Custom);
778 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
779 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
780 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
781 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
782 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
783 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
785 if (Subtarget->is64Bit()) {
786 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
787 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
790 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
791 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
792 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
795 // Do not attempt to promote non-128-bit vectors
796 if (!VT.is128BitVector())
799 setOperationAction(ISD::AND, SVT, Promote);
800 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
801 setOperationAction(ISD::OR, SVT, Promote);
802 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
803 setOperationAction(ISD::XOR, SVT, Promote);
804 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
805 setOperationAction(ISD::LOAD, SVT, Promote);
806 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
807 setOperationAction(ISD::SELECT, SVT, Promote);
808 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
811 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
813 // Custom lower v2i64 and v2f64 selects.
814 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
815 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
816 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
817 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
819 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
820 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
821 if (!DisableMMX && Subtarget->hasMMX()) {
822 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
823 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
827 if (Subtarget->hasSSE41()) {
828 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
829 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
830 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
831 setOperationAction(ISD::FRINT, MVT::f32, Legal);
832 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
833 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
834 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
835 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
836 setOperationAction(ISD::FRINT, MVT::f64, Legal);
837 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
839 // FIXME: Do we need to handle scalar-to-vector here?
840 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
842 // Can turn SHL into an integer multiply.
843 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
844 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
846 // i8 and i16 vectors are custom , because the source register and source
847 // source memory operand types are not the same width. f32 vectors are
848 // custom since the immediate controlling the insert encodes additional
850 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
851 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
852 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
853 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
855 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
856 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
857 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
858 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
860 if (Subtarget->is64Bit()) {
861 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
862 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
866 if (Subtarget->hasSSE42()) {
867 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
870 if (!UseSoftFloat && Subtarget->hasAVX()) {
871 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
872 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
873 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
874 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
875 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
877 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
878 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
879 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
880 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
881 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
882 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
883 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
884 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
885 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
886 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
887 setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
888 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
889 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
890 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
891 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
893 // Operations to consider commented out -v16i16 v32i8
894 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
895 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
896 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
897 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
898 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
899 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
900 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
901 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
902 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
903 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
904 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
905 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
906 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
907 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
909 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
910 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
911 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
912 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
914 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
915 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
916 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
917 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
920 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
923 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
924 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
925 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
928 // Not sure we want to do this since there are no 256-bit integer
931 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
932 // This includes 256-bit vectors
933 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
934 EVT VT = (MVT::SimpleValueType)i;
936 // Do not attempt to custom lower non-power-of-2 vectors
937 if (!isPowerOf2_32(VT.getVectorNumElements()))
940 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
941 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
942 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
945 if (Subtarget->is64Bit()) {
946 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
947 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
952 // Not sure we want to do this since there are no 256-bit integer
955 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
956 // Including 256-bit vectors
957 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
958 EVT VT = (MVT::SimpleValueType)i;
960 if (!VT.is256BitVector()) {
963 setOperationAction(ISD::AND, VT, Promote);
964 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
965 setOperationAction(ISD::OR, VT, Promote);
966 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
967 setOperationAction(ISD::XOR, VT, Promote);
968 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
969 setOperationAction(ISD::LOAD, VT, Promote);
970 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
971 setOperationAction(ISD::SELECT, VT, Promote);
972 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
975 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
979 // We want to custom lower some of our intrinsics.
980 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
982 // Add/Sub/Mul with overflow operations are custom lowered.
983 setOperationAction(ISD::SADDO, MVT::i32, Custom);
984 setOperationAction(ISD::UADDO, MVT::i32, Custom);
985 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
986 setOperationAction(ISD::USUBO, MVT::i32, Custom);
987 setOperationAction(ISD::SMULO, MVT::i32, Custom);
989 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
990 // handle type legalization for these operations here.
992 // FIXME: We really should do custom legalization for addition and
993 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
994 // than generic legalization for 64-bit multiplication-with-overflow, though.
995 if (Subtarget->is64Bit()) {
996 setOperationAction(ISD::SADDO, MVT::i64, Custom);
997 setOperationAction(ISD::UADDO, MVT::i64, Custom);
998 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
999 setOperationAction(ISD::USUBO, MVT::i64, Custom);
1000 setOperationAction(ISD::SMULO, MVT::i64, Custom);
1003 if (!Subtarget->is64Bit()) {
1004 // These libcalls are not available in 32-bit.
1005 setLibcallName(RTLIB::SHL_I128, 0);
1006 setLibcallName(RTLIB::SRL_I128, 0);
1007 setLibcallName(RTLIB::SRA_I128, 0);
1010 // We have target-specific dag combine patterns for the following nodes:
1011 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1012 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1013 setTargetDAGCombine(ISD::BUILD_VECTOR);
1014 setTargetDAGCombine(ISD::SELECT);
1015 setTargetDAGCombine(ISD::SHL);
1016 setTargetDAGCombine(ISD::SRA);
1017 setTargetDAGCombine(ISD::SRL);
1018 setTargetDAGCombine(ISD::OR);
1019 setTargetDAGCombine(ISD::STORE);
1020 setTargetDAGCombine(ISD::ZERO_EXTEND);
1021 if (Subtarget->is64Bit())
1022 setTargetDAGCombine(ISD::MUL);
1024 computeRegisterProperties();
1026 // FIXME: These should be based on subtarget info. Plus, the values should
1027 // be smaller when we are in optimizing for size mode.
1028 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1029 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1030 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1031 setPrefLoopAlignment(16);
1032 benefitFromCodePlacementOpt = true;
1036 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1041 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1042 /// the desired ByVal argument alignment.
1043 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1046 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1047 if (VTy->getBitWidth() == 128)
1049 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1050 unsigned EltAlign = 0;
1051 getMaxByValAlign(ATy->getElementType(), EltAlign);
1052 if (EltAlign > MaxAlign)
1053 MaxAlign = EltAlign;
1054 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1055 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1056 unsigned EltAlign = 0;
1057 getMaxByValAlign(STy->getElementType(i), EltAlign);
1058 if (EltAlign > MaxAlign)
1059 MaxAlign = EltAlign;
1067 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1068 /// function arguments in the caller parameter area. For X86, aggregates
1069 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1070 /// are at 4-byte boundaries.
1071 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1072 if (Subtarget->is64Bit()) {
1073 // Max of 8 and alignment of type.
1074 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1081 if (Subtarget->hasSSE1())
1082 getMaxByValAlign(Ty, Align);
1086 /// getOptimalMemOpType - Returns the target specific optimal type for load
1087 /// and store operations as a result of memset, memcpy, and memmove
1088 /// lowering. If DstAlign is zero that means it's safe to destination
1089 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1090 /// means there isn't a need to check it against alignment requirement,
1091 /// probably because the source does not need to be loaded. If
1092 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1093 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1094 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1095 /// constant so it does not need to be loaded.
1096 /// It returns EVT::Other if the type should be determined using generic
1097 /// target-independent logic.
1099 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1100 unsigned DstAlign, unsigned SrcAlign,
1101 bool NonScalarIntSafe,
1103 MachineFunction &MF) const {
1104 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1105 // linux. This is because the stack realignment code can't handle certain
1106 // cases like PR2962. This should be removed when PR2962 is fixed.
1107 const Function *F = MF.getFunction();
1108 if (NonScalarIntSafe &&
1109 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1111 (Subtarget->isUnalignedMemAccessFast() ||
1112 ((DstAlign == 0 || DstAlign >= 16) &&
1113 (SrcAlign == 0 || SrcAlign >= 16))) &&
1114 Subtarget->getStackAlignment() >= 16) {
1115 if (Subtarget->hasSSE2())
1117 if (Subtarget->hasSSE1())
1119 } else if (!MemcpyStrSrc && Size >= 8 &&
1120 !Subtarget->is64Bit() &&
1121 Subtarget->getStackAlignment() >= 8 &&
1122 Subtarget->hasSSE2()) {
1123 // Do not use f64 to lower memcpy if source is string constant. It's
1124 // better to use i32 to avoid the loads.
1128 if (Subtarget->is64Bit() && Size >= 8)
1133 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1134 /// current function. The returned value is a member of the
1135 /// MachineJumpTableInfo::JTEntryKind enum.
1136 unsigned X86TargetLowering::getJumpTableEncoding() const {
1137 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1139 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1140 Subtarget->isPICStyleGOT())
1141 return MachineJumpTableInfo::EK_Custom32;
1143 // Otherwise, use the normal jump table encoding heuristics.
1144 return TargetLowering::getJumpTableEncoding();
1147 /// getPICBaseSymbol - Return the X86-32 PIC base.
1149 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1150 MCContext &Ctx) const {
1151 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1152 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1153 Twine(MF->getFunctionNumber())+"$pb");
1158 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1159 const MachineBasicBlock *MBB,
1160 unsigned uid,MCContext &Ctx) const{
1161 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1162 Subtarget->isPICStyleGOT());
1163 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1165 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1166 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1169 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1171 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1172 SelectionDAG &DAG) const {
1173 if (!Subtarget->is64Bit())
1174 // This doesn't have DebugLoc associated with it, but is not really the
1175 // same as a Register.
1176 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1180 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1181 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1183 const MCExpr *X86TargetLowering::
1184 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1185 MCContext &Ctx) const {
1186 // X86-64 uses RIP relative addressing based on the jump table label.
1187 if (Subtarget->isPICStyleRIPRel())
1188 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1190 // Otherwise, the reference is relative to the PIC base.
1191 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1194 /// getFunctionAlignment - Return the Log2 alignment of this function.
1195 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1196 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1199 std::pair<const TargetRegisterClass*, uint8_t>
1200 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1201 const TargetRegisterClass *RRC = 0;
1203 switch (VT.getSimpleVT().SimpleTy) {
1205 return TargetLowering::findRepresentativeClass(VT);
1206 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1207 RRC = (Subtarget->is64Bit()
1208 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1210 case MVT::v8i8: case MVT::v4i16:
1211 case MVT::v2i32: case MVT::v1i64:
1212 RRC = X86::VR64RegisterClass;
1214 case MVT::f32: case MVT::f64:
1215 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1216 case MVT::v4f32: case MVT::v2f64:
1217 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1219 RRC = X86::VR128RegisterClass;
1222 return std::make_pair(RRC, Cost);
1226 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
1227 MachineFunction &MF) const {
1228 unsigned FPDiff = RegInfo->hasFP(MF) ? 1 : 0;
1229 switch (RC->getID()) {
1232 case X86::GR32RegClassID:
1234 case X86::GR64RegClassID:
1236 case X86::VR128RegClassID:
1237 return Subtarget->is64Bit() ? 10 : 4;
1238 case X86::VR64RegClassID:
1243 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1244 unsigned &Offset) const {
1245 if (!Subtarget->isTargetLinux())
1248 if (Subtarget->is64Bit()) {
1249 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1251 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1264 //===----------------------------------------------------------------------===//
1265 // Return Value Calling Convention Implementation
1266 //===----------------------------------------------------------------------===//
1268 #include "X86GenCallingConv.inc"
1271 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1272 const SmallVectorImpl<ISD::OutputArg> &Outs,
1273 LLVMContext &Context) const {
1274 SmallVector<CCValAssign, 16> RVLocs;
1275 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1277 return CCInfo.CheckReturn(Outs, RetCC_X86);
1281 X86TargetLowering::LowerReturn(SDValue Chain,
1282 CallingConv::ID CallConv, bool isVarArg,
1283 const SmallVectorImpl<ISD::OutputArg> &Outs,
1284 const SmallVectorImpl<SDValue> &OutVals,
1285 DebugLoc dl, SelectionDAG &DAG) const {
1286 MachineFunction &MF = DAG.getMachineFunction();
1287 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1289 SmallVector<CCValAssign, 16> RVLocs;
1290 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1291 RVLocs, *DAG.getContext());
1292 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1294 // Add the regs to the liveout set for the function.
1295 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1296 for (unsigned i = 0; i != RVLocs.size(); ++i)
1297 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1298 MRI.addLiveOut(RVLocs[i].getLocReg());
1302 SmallVector<SDValue, 6> RetOps;
1303 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1304 // Operand #1 = Bytes To Pop
1305 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1308 // Copy the result values into the output registers.
1309 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1310 CCValAssign &VA = RVLocs[i];
1311 assert(VA.isRegLoc() && "Can only return in registers!");
1312 SDValue ValToCopy = OutVals[i];
1313 EVT ValVT = ValToCopy.getValueType();
1315 // If this is x86-64, and we disabled SSE, we can't return FP values
1316 if ((ValVT == MVT::f32 || ValVT == MVT::f64) &&
1317 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1318 report_fatal_error("SSE register return with SSE disabled");
1320 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1321 // llvm-gcc has never done it right and no one has noticed, so this
1322 // should be OK for now.
1323 if (ValVT == MVT::f64 &&
1324 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1325 report_fatal_error("SSE2 register return with SSE2 disabled");
1327 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1328 // the RET instruction and handled by the FP Stackifier.
1329 if (VA.getLocReg() == X86::ST0 ||
1330 VA.getLocReg() == X86::ST1) {
1331 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1332 // change the value to the FP stack register class.
1333 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1334 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1335 RetOps.push_back(ValToCopy);
1336 // Don't emit a copytoreg.
1340 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1341 // which is returned in RAX / RDX.
1342 if (Subtarget->is64Bit()) {
1343 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1344 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1345 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1346 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1349 // If we don't have SSE2 available, convert to v4f32 so the generated
1350 // register is legal.
1351 if (!Subtarget->hasSSE2())
1352 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,ValToCopy);
1357 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1358 Flag = Chain.getValue(1);
1361 // The x86-64 ABI for returning structs by value requires that we copy
1362 // the sret argument into %rax for the return. We saved the argument into
1363 // a virtual register in the entry block, so now we copy the value out
1365 if (Subtarget->is64Bit() &&
1366 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1367 MachineFunction &MF = DAG.getMachineFunction();
1368 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1369 unsigned Reg = FuncInfo->getSRetReturnReg();
1371 "SRetReturnReg should have been set in LowerFormalArguments().");
1372 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1374 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1375 Flag = Chain.getValue(1);
1377 // RAX now acts like a return value.
1378 MRI.addLiveOut(X86::RAX);
1381 RetOps[0] = Chain; // Update chain.
1383 // Add the flag if we have it.
1385 RetOps.push_back(Flag);
1387 return DAG.getNode(X86ISD::RET_FLAG, dl,
1388 MVT::Other, &RetOps[0], RetOps.size());
1391 /// LowerCallResult - Lower the result values of a call into the
1392 /// appropriate copies out of appropriate physical registers.
1395 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1396 CallingConv::ID CallConv, bool isVarArg,
1397 const SmallVectorImpl<ISD::InputArg> &Ins,
1398 DebugLoc dl, SelectionDAG &DAG,
1399 SmallVectorImpl<SDValue> &InVals) const {
1401 // Assign locations to each value returned by this call.
1402 SmallVector<CCValAssign, 16> RVLocs;
1403 bool Is64Bit = Subtarget->is64Bit();
1404 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1405 RVLocs, *DAG.getContext());
1406 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1408 // Copy all of the result registers out of their specified physreg.
1409 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1410 CCValAssign &VA = RVLocs[i];
1411 EVT CopyVT = VA.getValVT();
1413 // If this is x86-64, and we disabled SSE, we can't return FP values
1414 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1415 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1416 report_fatal_error("SSE register return with SSE disabled");
1421 // If this is a call to a function that returns an fp value on the floating
1422 // point stack, we must guarantee the the value is popped from the stack, so
1423 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1424 // if the return value is not used. We use the FpGET_ST0 instructions
1426 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1427 // If we prefer to use the value in xmm registers, copy it out as f80 and
1428 // use a truncate to move it from fp stack reg to xmm reg.
1429 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1430 bool isST0 = VA.getLocReg() == X86::ST0;
1432 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1433 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1434 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1435 SDValue Ops[] = { Chain, InFlag };
1436 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag,
1438 Val = Chain.getValue(0);
1440 // Round the f80 to the right size, which also moves it to the appropriate
1442 if (CopyVT != VA.getValVT())
1443 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1444 // This truncation won't change the value.
1445 DAG.getIntPtrConstant(1));
1446 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1447 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1448 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1449 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1450 MVT::v2i64, InFlag).getValue(1);
1451 Val = Chain.getValue(0);
1452 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1453 Val, DAG.getConstant(0, MVT::i64));
1455 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1456 MVT::i64, InFlag).getValue(1);
1457 Val = Chain.getValue(0);
1459 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1461 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1462 CopyVT, InFlag).getValue(1);
1463 Val = Chain.getValue(0);
1465 InFlag = Chain.getValue(2);
1466 InVals.push_back(Val);
1473 //===----------------------------------------------------------------------===//
1474 // C & StdCall & Fast Calling Convention implementation
1475 //===----------------------------------------------------------------------===//
1476 // StdCall calling convention seems to be standard for many Windows' API
1477 // routines and around. It differs from C calling convention just a little:
1478 // callee should clean up the stack, not caller. Symbols should be also
1479 // decorated in some fancy way :) It doesn't support any vector arguments.
1480 // For info on fast calling convention see Fast Calling Convention (tail call)
1481 // implementation LowerX86_32FastCCCallTo.
1483 /// CallIsStructReturn - Determines whether a call uses struct return
1485 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1489 return Outs[0].Flags.isSRet();
1492 /// ArgsAreStructReturn - Determines whether a function uses struct
1493 /// return semantics.
1495 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1499 return Ins[0].Flags.isSRet();
1502 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1503 /// given CallingConvention value.
1504 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1505 if (Subtarget->is64Bit()) {
1506 if (CC == CallingConv::GHC)
1507 return CC_X86_64_GHC;
1508 else if (Subtarget->isTargetWin64())
1509 return CC_X86_Win64_C;
1514 if (CC == CallingConv::X86_FastCall)
1515 return CC_X86_32_FastCall;
1516 else if (CC == CallingConv::X86_ThisCall)
1517 return CC_X86_32_ThisCall;
1518 else if (CC == CallingConv::Fast)
1519 return CC_X86_32_FastCC;
1520 else if (CC == CallingConv::GHC)
1521 return CC_X86_32_GHC;
1526 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1527 /// by "Src" to address "Dst" with size and alignment information specified by
1528 /// the specific parameter attribute. The copy will be passed as a byval
1529 /// function parameter.
1531 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1532 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1534 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1535 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1536 /*isVolatile*/false, /*AlwaysInline=*/true,
1540 /// IsTailCallConvention - Return true if the calling convention is one that
1541 /// supports tail call optimization.
1542 static bool IsTailCallConvention(CallingConv::ID CC) {
1543 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1546 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1547 /// a tailcall target by changing its ABI.
1548 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1549 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1553 X86TargetLowering::LowerMemArgument(SDValue Chain,
1554 CallingConv::ID CallConv,
1555 const SmallVectorImpl<ISD::InputArg> &Ins,
1556 DebugLoc dl, SelectionDAG &DAG,
1557 const CCValAssign &VA,
1558 MachineFrameInfo *MFI,
1560 // Create the nodes corresponding to a load from this parameter slot.
1561 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1562 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1563 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1566 // If value is passed by pointer we have address passed instead of the value
1568 if (VA.getLocInfo() == CCValAssign::Indirect)
1569 ValVT = VA.getLocVT();
1571 ValVT = VA.getValVT();
1573 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1574 // changed with more analysis.
1575 // In case of tail call optimization mark all arguments mutable. Since they
1576 // could be overwritten by lowering of arguments in case of a tail call.
1577 if (Flags.isByVal()) {
1578 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1579 VA.getLocMemOffset(), isImmutable);
1580 return DAG.getFrameIndex(FI, getPointerTy());
1582 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1583 VA.getLocMemOffset(), isImmutable);
1584 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1585 return DAG.getLoad(ValVT, dl, Chain, FIN,
1586 PseudoSourceValue::getFixedStack(FI), 0,
1592 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1593 CallingConv::ID CallConv,
1595 const SmallVectorImpl<ISD::InputArg> &Ins,
1598 SmallVectorImpl<SDValue> &InVals)
1600 MachineFunction &MF = DAG.getMachineFunction();
1601 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1603 const Function* Fn = MF.getFunction();
1604 if (Fn->hasExternalLinkage() &&
1605 Subtarget->isTargetCygMing() &&
1606 Fn->getName() == "main")
1607 FuncInfo->setForceFramePointer(true);
1609 MachineFrameInfo *MFI = MF.getFrameInfo();
1610 bool Is64Bit = Subtarget->is64Bit();
1611 bool IsWin64 = Subtarget->isTargetWin64();
1613 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1614 "Var args not supported with calling convention fastcc or ghc");
1616 // Assign locations to all of the incoming arguments.
1617 SmallVector<CCValAssign, 16> ArgLocs;
1618 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1619 ArgLocs, *DAG.getContext());
1620 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1622 unsigned LastVal = ~0U;
1624 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1625 CCValAssign &VA = ArgLocs[i];
1626 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1628 assert(VA.getValNo() != LastVal &&
1629 "Don't support value assigned to multiple locs yet");
1630 LastVal = VA.getValNo();
1632 if (VA.isRegLoc()) {
1633 EVT RegVT = VA.getLocVT();
1634 TargetRegisterClass *RC = NULL;
1635 if (RegVT == MVT::i32)
1636 RC = X86::GR32RegisterClass;
1637 else if (Is64Bit && RegVT == MVT::i64)
1638 RC = X86::GR64RegisterClass;
1639 else if (RegVT == MVT::f32)
1640 RC = X86::FR32RegisterClass;
1641 else if (RegVT == MVT::f64)
1642 RC = X86::FR64RegisterClass;
1643 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1644 RC = X86::VR256RegisterClass;
1645 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1646 RC = X86::VR128RegisterClass;
1647 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1648 RC = X86::VR64RegisterClass;
1650 llvm_unreachable("Unknown argument type!");
1652 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1653 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1655 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1656 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1658 if (VA.getLocInfo() == CCValAssign::SExt)
1659 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1660 DAG.getValueType(VA.getValVT()));
1661 else if (VA.getLocInfo() == CCValAssign::ZExt)
1662 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1663 DAG.getValueType(VA.getValVT()));
1664 else if (VA.getLocInfo() == CCValAssign::BCvt)
1665 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1667 if (VA.isExtInLoc()) {
1668 // Handle MMX values passed in XMM regs.
1669 if (RegVT.isVector()) {
1670 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1671 ArgValue, DAG.getConstant(0, MVT::i64));
1672 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1674 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1677 assert(VA.isMemLoc());
1678 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1681 // If value is passed via pointer - do a load.
1682 if (VA.getLocInfo() == CCValAssign::Indirect)
1683 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
1686 InVals.push_back(ArgValue);
1689 // The x86-64 ABI for returning structs by value requires that we copy
1690 // the sret argument into %rax for the return. Save the argument into
1691 // a virtual register so that we can access it from the return points.
1692 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1693 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1694 unsigned Reg = FuncInfo->getSRetReturnReg();
1696 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1697 FuncInfo->setSRetReturnReg(Reg);
1699 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1700 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1703 unsigned StackSize = CCInfo.getNextStackOffset();
1704 // Align stack specially for tail calls.
1705 if (FuncIsMadeTailCallSafe(CallConv))
1706 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1708 // If the function takes variable number of arguments, make a frame index for
1709 // the start of the first vararg value... for expansion of llvm.va_start.
1711 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1712 CallConv != CallingConv::X86_ThisCall)) {
1713 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1716 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1718 // FIXME: We should really autogenerate these arrays
1719 static const unsigned GPR64ArgRegsWin64[] = {
1720 X86::RCX, X86::RDX, X86::R8, X86::R9
1722 static const unsigned XMMArgRegsWin64[] = {
1723 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1725 static const unsigned GPR64ArgRegs64Bit[] = {
1726 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1728 static const unsigned XMMArgRegs64Bit[] = {
1729 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1730 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1732 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1735 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1736 GPR64ArgRegs = GPR64ArgRegsWin64;
1737 XMMArgRegs = XMMArgRegsWin64;
1739 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1740 GPR64ArgRegs = GPR64ArgRegs64Bit;
1741 XMMArgRegs = XMMArgRegs64Bit;
1743 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1745 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1748 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1749 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1750 "SSE register cannot be used when SSE is disabled!");
1751 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1752 "SSE register cannot be used when SSE is disabled!");
1753 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1754 // Kernel mode asks for SSE to be disabled, so don't push them
1756 TotalNumXMMRegs = 0;
1758 // For X86-64, if there are vararg parameters that are passed via
1759 // registers, then we must store them to their spots on the stack so they
1760 // may be loaded by deferencing the result of va_next.
1761 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1762 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1763 FuncInfo->setRegSaveFrameIndex(
1764 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1767 // Store the integer parameter registers.
1768 SmallVector<SDValue, 8> MemOps;
1769 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1771 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1772 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1773 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1774 DAG.getIntPtrConstant(Offset));
1775 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1776 X86::GR64RegisterClass);
1777 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1779 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1780 PseudoSourceValue::getFixedStack(
1781 FuncInfo->getRegSaveFrameIndex()),
1782 Offset, false, false, 0);
1783 MemOps.push_back(Store);
1787 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1788 // Now store the XMM (fp + vector) parameter registers.
1789 SmallVector<SDValue, 11> SaveXMMOps;
1790 SaveXMMOps.push_back(Chain);
1792 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1793 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1794 SaveXMMOps.push_back(ALVal);
1796 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1797 FuncInfo->getRegSaveFrameIndex()));
1798 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1799 FuncInfo->getVarArgsFPOffset()));
1801 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1802 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1803 X86::VR128RegisterClass);
1804 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1805 SaveXMMOps.push_back(Val);
1807 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1809 &SaveXMMOps[0], SaveXMMOps.size()));
1812 if (!MemOps.empty())
1813 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1814 &MemOps[0], MemOps.size());
1818 // Some CCs need callee pop.
1819 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1820 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1822 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1823 // If this is an sret function, the return should pop the hidden pointer.
1824 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1825 FuncInfo->setBytesToPopOnReturn(4);
1829 // RegSaveFrameIndex is X86-64 only.
1830 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1831 if (CallConv == CallingConv::X86_FastCall ||
1832 CallConv == CallingConv::X86_ThisCall)
1833 // fastcc functions can't have varargs.
1834 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1841 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1842 SDValue StackPtr, SDValue Arg,
1843 DebugLoc dl, SelectionDAG &DAG,
1844 const CCValAssign &VA,
1845 ISD::ArgFlagsTy Flags) const {
1846 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1847 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1848 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1849 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1850 if (Flags.isByVal()) {
1851 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1853 return DAG.getStore(Chain, dl, Arg, PtrOff,
1854 PseudoSourceValue::getStack(), LocMemOffset,
1858 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1859 /// optimization is performed and it is required.
1861 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1862 SDValue &OutRetAddr, SDValue Chain,
1863 bool IsTailCall, bool Is64Bit,
1864 int FPDiff, DebugLoc dl) const {
1865 // Adjust the Return address stack slot.
1866 EVT VT = getPointerTy();
1867 OutRetAddr = getReturnAddressFrameIndex(DAG);
1869 // Load the "old" Return address.
1870 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
1871 return SDValue(OutRetAddr.getNode(), 1);
1874 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1875 /// optimization is performed and it is required (FPDiff!=0).
1877 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1878 SDValue Chain, SDValue RetAddrFrIdx,
1879 bool Is64Bit, int FPDiff, DebugLoc dl) {
1880 // Store the return address to the appropriate stack slot.
1881 if (!FPDiff) return Chain;
1882 // Calculate the new stack slot for the return address.
1883 int SlotSize = Is64Bit ? 8 : 4;
1884 int NewReturnAddrFI =
1885 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1886 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1887 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1888 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1889 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
1895 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1896 CallingConv::ID CallConv, bool isVarArg,
1898 const SmallVectorImpl<ISD::OutputArg> &Outs,
1899 const SmallVectorImpl<SDValue> &OutVals,
1900 const SmallVectorImpl<ISD::InputArg> &Ins,
1901 DebugLoc dl, SelectionDAG &DAG,
1902 SmallVectorImpl<SDValue> &InVals) const {
1903 MachineFunction &MF = DAG.getMachineFunction();
1904 bool Is64Bit = Subtarget->is64Bit();
1905 bool IsStructRet = CallIsStructReturn(Outs);
1906 bool IsSibcall = false;
1909 // Check if it's really possible to do a tail call.
1910 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1911 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1912 Outs, OutVals, Ins, DAG);
1914 // Sibcalls are automatically detected tailcalls which do not require
1916 if (!GuaranteedTailCallOpt && isTailCall)
1923 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1924 "Var args not supported with calling convention fastcc or ghc");
1926 // Analyze operands of the call, assigning locations to each operand.
1927 SmallVector<CCValAssign, 16> ArgLocs;
1928 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1929 ArgLocs, *DAG.getContext());
1930 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1932 // Get a count of how many bytes are to be pushed on the stack.
1933 unsigned NumBytes = CCInfo.getNextStackOffset();
1935 // This is a sibcall. The memory operands are available in caller's
1936 // own caller's stack.
1938 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1939 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1942 if (isTailCall && !IsSibcall) {
1943 // Lower arguments at fp - stackoffset + fpdiff.
1944 unsigned NumBytesCallerPushed =
1945 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1946 FPDiff = NumBytesCallerPushed - NumBytes;
1948 // Set the delta of movement of the returnaddr stackslot.
1949 // But only set if delta is greater than previous delta.
1950 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1951 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1955 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1957 SDValue RetAddrFrIdx;
1958 // Load return adress for tail calls.
1959 if (isTailCall && FPDiff)
1960 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1961 Is64Bit, FPDiff, dl);
1963 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1964 SmallVector<SDValue, 8> MemOpChains;
1967 // Walk the register/memloc assignments, inserting copies/loads. In the case
1968 // of tail call optimization arguments are handle later.
1969 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1970 CCValAssign &VA = ArgLocs[i];
1971 EVT RegVT = VA.getLocVT();
1972 SDValue Arg = OutVals[i];
1973 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1974 bool isByVal = Flags.isByVal();
1976 // Promote the value if needed.
1977 switch (VA.getLocInfo()) {
1978 default: llvm_unreachable("Unknown loc info!");
1979 case CCValAssign::Full: break;
1980 case CCValAssign::SExt:
1981 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1983 case CCValAssign::ZExt:
1984 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1986 case CCValAssign::AExt:
1987 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1988 // Special case: passing MMX values in XMM registers.
1989 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1990 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1991 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1993 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1995 case CCValAssign::BCvt:
1996 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1998 case CCValAssign::Indirect: {
1999 // Store the argument.
2000 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2001 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2002 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2003 PseudoSourceValue::getFixedStack(FI), 0,
2010 if (VA.isRegLoc()) {
2011 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2012 if (isVarArg && Subtarget->isTargetWin64()) {
2013 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2014 // shadow reg if callee is a varargs function.
2015 unsigned ShadowReg = 0;
2016 switch (VA.getLocReg()) {
2017 case X86::XMM0: ShadowReg = X86::RCX; break;
2018 case X86::XMM1: ShadowReg = X86::RDX; break;
2019 case X86::XMM2: ShadowReg = X86::R8; break;
2020 case X86::XMM3: ShadowReg = X86::R9; break;
2023 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2025 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2026 assert(VA.isMemLoc());
2027 if (StackPtr.getNode() == 0)
2028 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2029 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2030 dl, DAG, VA, Flags));
2034 if (!MemOpChains.empty())
2035 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2036 &MemOpChains[0], MemOpChains.size());
2038 // Build a sequence of copy-to-reg nodes chained together with token chain
2039 // and flag operands which copy the outgoing args into registers.
2041 // Tail call byval lowering might overwrite argument registers so in case of
2042 // tail call optimization the copies to registers are lowered later.
2044 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2045 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2046 RegsToPass[i].second, InFlag);
2047 InFlag = Chain.getValue(1);
2050 if (Subtarget->isPICStyleGOT()) {
2051 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2054 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2055 DAG.getNode(X86ISD::GlobalBaseReg,
2056 DebugLoc(), getPointerTy()),
2058 InFlag = Chain.getValue(1);
2060 // If we are tail calling and generating PIC/GOT style code load the
2061 // address of the callee into ECX. The value in ecx is used as target of
2062 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2063 // for tail calls on PIC/GOT architectures. Normally we would just put the
2064 // address of GOT into ebx and then call target@PLT. But for tail calls
2065 // ebx would be restored (since ebx is callee saved) before jumping to the
2068 // Note: The actual moving to ECX is done further down.
2069 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2070 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2071 !G->getGlobal()->hasProtectedVisibility())
2072 Callee = LowerGlobalAddress(Callee, DAG);
2073 else if (isa<ExternalSymbolSDNode>(Callee))
2074 Callee = LowerExternalSymbol(Callee, DAG);
2078 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
2079 // From AMD64 ABI document:
2080 // For calls that may call functions that use varargs or stdargs
2081 // (prototype-less calls or calls to functions containing ellipsis (...) in
2082 // the declaration) %al is used as hidden argument to specify the number
2083 // of SSE registers used. The contents of %al do not need to match exactly
2084 // the number of registers, but must be an ubound on the number of SSE
2085 // registers used and is in the range 0 - 8 inclusive.
2087 // Count the number of XMM registers allocated.
2088 static const unsigned XMMArgRegs[] = {
2089 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2090 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2092 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2093 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2094 && "SSE registers cannot be used when SSE is disabled");
2096 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2097 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2098 InFlag = Chain.getValue(1);
2102 // For tail calls lower the arguments to the 'real' stack slot.
2104 // Force all the incoming stack arguments to be loaded from the stack
2105 // before any new outgoing arguments are stored to the stack, because the
2106 // outgoing stack slots may alias the incoming argument stack slots, and
2107 // the alias isn't otherwise explicit. This is slightly more conservative
2108 // than necessary, because it means that each store effectively depends
2109 // on every argument instead of just those arguments it would clobber.
2110 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2112 SmallVector<SDValue, 8> MemOpChains2;
2115 // Do not flag preceeding copytoreg stuff together with the following stuff.
2117 if (GuaranteedTailCallOpt) {
2118 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2119 CCValAssign &VA = ArgLocs[i];
2122 assert(VA.isMemLoc());
2123 SDValue Arg = OutVals[i];
2124 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2125 // Create frame index.
2126 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2127 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2128 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2129 FIN = DAG.getFrameIndex(FI, getPointerTy());
2131 if (Flags.isByVal()) {
2132 // Copy relative to framepointer.
2133 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2134 if (StackPtr.getNode() == 0)
2135 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2137 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2139 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2143 // Store relative to framepointer.
2144 MemOpChains2.push_back(
2145 DAG.getStore(ArgChain, dl, Arg, FIN,
2146 PseudoSourceValue::getFixedStack(FI), 0,
2152 if (!MemOpChains2.empty())
2153 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2154 &MemOpChains2[0], MemOpChains2.size());
2156 // Copy arguments to their registers.
2157 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2158 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2159 RegsToPass[i].second, InFlag);
2160 InFlag = Chain.getValue(1);
2164 // Store the return address to the appropriate stack slot.
2165 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2169 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2170 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2171 // In the 64-bit large code model, we have to make all calls
2172 // through a register, since the call instruction's 32-bit
2173 // pc-relative offset may not be large enough to hold the whole
2175 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2176 // If the callee is a GlobalAddress node (quite common, every direct call
2177 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2180 // We should use extra load for direct calls to dllimported functions in
2182 const GlobalValue *GV = G->getGlobal();
2183 if (!GV->hasDLLImportLinkage()) {
2184 unsigned char OpFlags = 0;
2186 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2187 // external symbols most go through the PLT in PIC mode. If the symbol
2188 // has hidden or protected visibility, or if it is static or local, then
2189 // we don't need to use the PLT - we can directly call it.
2190 if (Subtarget->isTargetELF() &&
2191 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2192 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2193 OpFlags = X86II::MO_PLT;
2194 } else if (Subtarget->isPICStyleStubAny() &&
2195 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2196 Subtarget->getDarwinVers() < 9) {
2197 // PC-relative references to external symbols should go through $stub,
2198 // unless we're building with the leopard linker or later, which
2199 // automatically synthesizes these stubs.
2200 OpFlags = X86II::MO_DARWIN_STUB;
2203 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2204 G->getOffset(), OpFlags);
2206 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2207 unsigned char OpFlags = 0;
2209 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2210 // symbols should go through the PLT.
2211 if (Subtarget->isTargetELF() &&
2212 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2213 OpFlags = X86II::MO_PLT;
2214 } else if (Subtarget->isPICStyleStubAny() &&
2215 Subtarget->getDarwinVers() < 9) {
2216 // PC-relative references to external symbols should go through $stub,
2217 // unless we're building with the leopard linker or later, which
2218 // automatically synthesizes these stubs.
2219 OpFlags = X86II::MO_DARWIN_STUB;
2222 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2226 // Returns a chain & a flag for retval copy to use.
2227 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2228 SmallVector<SDValue, 8> Ops;
2230 if (!IsSibcall && isTailCall) {
2231 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2232 DAG.getIntPtrConstant(0, true), InFlag);
2233 InFlag = Chain.getValue(1);
2236 Ops.push_back(Chain);
2237 Ops.push_back(Callee);
2240 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2242 // Add argument registers to the end of the list so that they are known live
2244 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2245 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2246 RegsToPass[i].second.getValueType()));
2248 // Add an implicit use GOT pointer in EBX.
2249 if (!isTailCall && Subtarget->isPICStyleGOT())
2250 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2252 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2253 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64())
2254 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2256 if (InFlag.getNode())
2257 Ops.push_back(InFlag);
2261 //// If this is the first return lowered for this function, add the regs
2262 //// to the liveout set for the function.
2263 // This isn't right, although it's probably harmless on x86; liveouts
2264 // should be computed from returns not tail calls. Consider a void
2265 // function making a tail call to a function returning int.
2266 return DAG.getNode(X86ISD::TC_RETURN, dl,
2267 NodeTys, &Ops[0], Ops.size());
2270 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2271 InFlag = Chain.getValue(1);
2273 // Create the CALLSEQ_END node.
2274 unsigned NumBytesForCalleeToPush;
2275 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2276 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2277 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2278 // If this is a call to a struct-return function, the callee
2279 // pops the hidden struct pointer, so we have to push it back.
2280 // This is common for Darwin/X86, Linux & Mingw32 targets.
2281 NumBytesForCalleeToPush = 4;
2283 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2285 // Returns a flag for retval copy to use.
2287 Chain = DAG.getCALLSEQ_END(Chain,
2288 DAG.getIntPtrConstant(NumBytes, true),
2289 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2292 InFlag = Chain.getValue(1);
2295 // Handle result values, copying them out of physregs into vregs that we
2297 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2298 Ins, dl, DAG, InVals);
2302 //===----------------------------------------------------------------------===//
2303 // Fast Calling Convention (tail call) implementation
2304 //===----------------------------------------------------------------------===//
2306 // Like std call, callee cleans arguments, convention except that ECX is
2307 // reserved for storing the tail called function address. Only 2 registers are
2308 // free for argument passing (inreg). Tail call optimization is performed
2310 // * tailcallopt is enabled
2311 // * caller/callee are fastcc
2312 // On X86_64 architecture with GOT-style position independent code only local
2313 // (within module) calls are supported at the moment.
2314 // To keep the stack aligned according to platform abi the function
2315 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2316 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2317 // If a tail called function callee has more arguments than the caller the
2318 // caller needs to make sure that there is room to move the RETADDR to. This is
2319 // achieved by reserving an area the size of the argument delta right after the
2320 // original REtADDR, but before the saved framepointer or the spilled registers
2321 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2333 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2334 /// for a 16 byte align requirement.
2336 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2337 SelectionDAG& DAG) const {
2338 MachineFunction &MF = DAG.getMachineFunction();
2339 const TargetMachine &TM = MF.getTarget();
2340 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2341 unsigned StackAlignment = TFI.getStackAlignment();
2342 uint64_t AlignMask = StackAlignment - 1;
2343 int64_t Offset = StackSize;
2344 uint64_t SlotSize = TD->getPointerSize();
2345 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2346 // Number smaller than 12 so just add the difference.
2347 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2349 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2350 Offset = ((~AlignMask) & Offset) + StackAlignment +
2351 (StackAlignment-SlotSize);
2356 /// MatchingStackOffset - Return true if the given stack call argument is
2357 /// already available in the same position (relatively) of the caller's
2358 /// incoming argument stack.
2360 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2361 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2362 const X86InstrInfo *TII) {
2363 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2365 if (Arg.getOpcode() == ISD::CopyFromReg) {
2366 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2367 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2369 MachineInstr *Def = MRI->getVRegDef(VR);
2372 if (!Flags.isByVal()) {
2373 if (!TII->isLoadFromStackSlot(Def, FI))
2376 unsigned Opcode = Def->getOpcode();
2377 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2378 Def->getOperand(1).isFI()) {
2379 FI = Def->getOperand(1).getIndex();
2380 Bytes = Flags.getByValSize();
2384 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2385 if (Flags.isByVal())
2386 // ByVal argument is passed in as a pointer but it's now being
2387 // dereferenced. e.g.
2388 // define @foo(%struct.X* %A) {
2389 // tail call @bar(%struct.X* byval %A)
2392 SDValue Ptr = Ld->getBasePtr();
2393 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2396 FI = FINode->getIndex();
2400 assert(FI != INT_MAX);
2401 if (!MFI->isFixedObjectIndex(FI))
2403 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2406 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2407 /// for tail call optimization. Targets which want to do tail call
2408 /// optimization should implement this function.
2410 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2411 CallingConv::ID CalleeCC,
2413 bool isCalleeStructRet,
2414 bool isCallerStructRet,
2415 const SmallVectorImpl<ISD::OutputArg> &Outs,
2416 const SmallVectorImpl<SDValue> &OutVals,
2417 const SmallVectorImpl<ISD::InputArg> &Ins,
2418 SelectionDAG& DAG) const {
2419 if (!IsTailCallConvention(CalleeCC) &&
2420 CalleeCC != CallingConv::C)
2423 // If -tailcallopt is specified, make fastcc functions tail-callable.
2424 const MachineFunction &MF = DAG.getMachineFunction();
2425 const Function *CallerF = DAG.getMachineFunction().getFunction();
2426 CallingConv::ID CallerCC = CallerF->getCallingConv();
2427 bool CCMatch = CallerCC == CalleeCC;
2429 if (GuaranteedTailCallOpt) {
2430 if (IsTailCallConvention(CalleeCC) && CCMatch)
2435 // Look for obvious safe cases to perform tail call optimization that do not
2436 // require ABI changes. This is what gcc calls sibcall.
2438 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2439 // emit a special epilogue.
2440 if (RegInfo->needsStackRealignment(MF))
2443 // Do not sibcall optimize vararg calls unless the call site is not passing
2445 if (isVarArg && !Outs.empty())
2448 // Also avoid sibcall optimization if either caller or callee uses struct
2449 // return semantics.
2450 if (isCalleeStructRet || isCallerStructRet)
2453 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2454 // Therefore if it's not used by the call it is not safe to optimize this into
2456 bool Unused = false;
2457 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2464 SmallVector<CCValAssign, 16> RVLocs;
2465 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2466 RVLocs, *DAG.getContext());
2467 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2468 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2469 CCValAssign &VA = RVLocs[i];
2470 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2475 // If the calling conventions do not match, then we'd better make sure the
2476 // results are returned in the same way as what the caller expects.
2478 SmallVector<CCValAssign, 16> RVLocs1;
2479 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2480 RVLocs1, *DAG.getContext());
2481 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2483 SmallVector<CCValAssign, 16> RVLocs2;
2484 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2485 RVLocs2, *DAG.getContext());
2486 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2488 if (RVLocs1.size() != RVLocs2.size())
2490 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2491 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2493 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2495 if (RVLocs1[i].isRegLoc()) {
2496 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2499 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2505 // If the callee takes no arguments then go on to check the results of the
2507 if (!Outs.empty()) {
2508 // Check if stack adjustment is needed. For now, do not do this if any
2509 // argument is passed on the stack.
2510 SmallVector<CCValAssign, 16> ArgLocs;
2511 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2512 ArgLocs, *DAG.getContext());
2513 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2514 if (CCInfo.getNextStackOffset()) {
2515 MachineFunction &MF = DAG.getMachineFunction();
2516 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2518 if (Subtarget->isTargetWin64())
2519 // Win64 ABI has additional complications.
2522 // Check if the arguments are already laid out in the right way as
2523 // the caller's fixed stack objects.
2524 MachineFrameInfo *MFI = MF.getFrameInfo();
2525 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2526 const X86InstrInfo *TII =
2527 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2528 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2529 CCValAssign &VA = ArgLocs[i];
2530 SDValue Arg = OutVals[i];
2531 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2532 if (VA.getLocInfo() == CCValAssign::Indirect)
2534 if (!VA.isRegLoc()) {
2535 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2542 // If the tailcall address may be in a register, then make sure it's
2543 // possible to register allocate for it. In 32-bit, the call address can
2544 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2545 // callee-saved registers are restored. These happen to be the same
2546 // registers used to pass 'inreg' arguments so watch out for those.
2547 if (!Subtarget->is64Bit() &&
2548 !isa<GlobalAddressSDNode>(Callee) &&
2549 !isa<ExternalSymbolSDNode>(Callee)) {
2550 unsigned NumInRegs = 0;
2551 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2552 CCValAssign &VA = ArgLocs[i];
2555 unsigned Reg = VA.getLocReg();
2558 case X86::EAX: case X86::EDX: case X86::ECX:
2559 if (++NumInRegs == 3)
2571 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2572 return X86::createFastISel(funcInfo);
2576 //===----------------------------------------------------------------------===//
2577 // Other Lowering Hooks
2578 //===----------------------------------------------------------------------===//
2580 static bool MayFoldLoad(SDValue Op) {
2581 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2584 static bool MayFoldIntoStore(SDValue Op) {
2585 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2588 static bool isTargetShuffle(unsigned Opcode) {
2590 default: return false;
2591 case X86ISD::PSHUFD:
2592 case X86ISD::PSHUFHW:
2593 case X86ISD::PSHUFLW:
2594 case X86ISD::SHUFPD:
2595 case X86ISD::SHUFPS:
2596 case X86ISD::MOVLHPS:
2597 case X86ISD::MOVLHPD:
2598 case X86ISD::MOVHLPS:
2599 case X86ISD::MOVLPS:
2600 case X86ISD::MOVLPD:
2601 case X86ISD::MOVSHDUP:
2602 case X86ISD::MOVSLDUP:
2605 case X86ISD::UNPCKLPS:
2606 case X86ISD::UNPCKLPD:
2607 case X86ISD::PUNPCKLWD:
2608 case X86ISD::PUNPCKLBW:
2609 case X86ISD::PUNPCKLDQ:
2610 case X86ISD::PUNPCKLQDQ:
2611 case X86ISD::UNPCKHPS:
2612 case X86ISD::UNPCKHPD:
2613 case X86ISD::PUNPCKHWD:
2614 case X86ISD::PUNPCKHBW:
2615 case X86ISD::PUNPCKHDQ:
2616 case X86ISD::PUNPCKHQDQ:
2622 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2623 SDValue V1, SelectionDAG &DAG) {
2625 default: llvm_unreachable("Unknown x86 shuffle node");
2626 case X86ISD::MOVSHDUP:
2627 case X86ISD::MOVSLDUP:
2628 return DAG.getNode(Opc, dl, VT, V1);
2634 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2635 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2637 default: llvm_unreachable("Unknown x86 shuffle node");
2638 case X86ISD::PSHUFD:
2639 case X86ISD::PSHUFHW:
2640 case X86ISD::PSHUFLW:
2641 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2647 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2648 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2650 default: llvm_unreachable("Unknown x86 shuffle node");
2651 case X86ISD::SHUFPD:
2652 case X86ISD::SHUFPS:
2653 return DAG.getNode(Opc, dl, VT, V1, V2,
2654 DAG.getConstant(TargetMask, MVT::i8));
2659 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2660 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2662 default: llvm_unreachable("Unknown x86 shuffle node");
2663 case X86ISD::MOVLHPS:
2664 case X86ISD::MOVLHPD:
2665 case X86ISD::MOVHLPS:
2666 case X86ISD::MOVLPS:
2667 case X86ISD::MOVLPD:
2670 case X86ISD::UNPCKLPS:
2671 case X86ISD::UNPCKLPD:
2672 case X86ISD::PUNPCKLWD:
2673 case X86ISD::PUNPCKLBW:
2674 case X86ISD::PUNPCKLDQ:
2675 case X86ISD::PUNPCKLQDQ:
2676 case X86ISD::UNPCKHPS:
2677 case X86ISD::UNPCKHPD:
2678 case X86ISD::PUNPCKHWD:
2679 case X86ISD::PUNPCKHBW:
2680 case X86ISD::PUNPCKHDQ:
2681 case X86ISD::PUNPCKHQDQ:
2682 return DAG.getNode(Opc, dl, VT, V1, V2);
2687 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2688 MachineFunction &MF = DAG.getMachineFunction();
2689 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2690 int ReturnAddrIndex = FuncInfo->getRAIndex();
2692 if (ReturnAddrIndex == 0) {
2693 // Set up a frame object for the return address.
2694 uint64_t SlotSize = TD->getPointerSize();
2695 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2697 FuncInfo->setRAIndex(ReturnAddrIndex);
2700 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2704 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2705 bool hasSymbolicDisplacement) {
2706 // Offset should fit into 32 bit immediate field.
2707 if (!isInt<32>(Offset))
2710 // If we don't have a symbolic displacement - we don't have any extra
2712 if (!hasSymbolicDisplacement)
2715 // FIXME: Some tweaks might be needed for medium code model.
2716 if (M != CodeModel::Small && M != CodeModel::Kernel)
2719 // For small code model we assume that latest object is 16MB before end of 31
2720 // bits boundary. We may also accept pretty large negative constants knowing
2721 // that all objects are in the positive half of address space.
2722 if (M == CodeModel::Small && Offset < 16*1024*1024)
2725 // For kernel code model we know that all object resist in the negative half
2726 // of 32bits address space. We may not accept negative offsets, since they may
2727 // be just off and we may accept pretty large positive ones.
2728 if (M == CodeModel::Kernel && Offset > 0)
2734 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2735 /// specific condition code, returning the condition code and the LHS/RHS of the
2736 /// comparison to make.
2737 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2738 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2740 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2741 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2742 // X > -1 -> X == 0, jump !sign.
2743 RHS = DAG.getConstant(0, RHS.getValueType());
2744 return X86::COND_NS;
2745 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2746 // X < 0 -> X == 0, jump on sign.
2748 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2750 RHS = DAG.getConstant(0, RHS.getValueType());
2751 return X86::COND_LE;
2755 switch (SetCCOpcode) {
2756 default: llvm_unreachable("Invalid integer condition!");
2757 case ISD::SETEQ: return X86::COND_E;
2758 case ISD::SETGT: return X86::COND_G;
2759 case ISD::SETGE: return X86::COND_GE;
2760 case ISD::SETLT: return X86::COND_L;
2761 case ISD::SETLE: return X86::COND_LE;
2762 case ISD::SETNE: return X86::COND_NE;
2763 case ISD::SETULT: return X86::COND_B;
2764 case ISD::SETUGT: return X86::COND_A;
2765 case ISD::SETULE: return X86::COND_BE;
2766 case ISD::SETUGE: return X86::COND_AE;
2770 // First determine if it is required or is profitable to flip the operands.
2772 // If LHS is a foldable load, but RHS is not, flip the condition.
2773 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2774 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2775 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2776 std::swap(LHS, RHS);
2779 switch (SetCCOpcode) {
2785 std::swap(LHS, RHS);
2789 // On a floating point condition, the flags are set as follows:
2791 // 0 | 0 | 0 | X > Y
2792 // 0 | 0 | 1 | X < Y
2793 // 1 | 0 | 0 | X == Y
2794 // 1 | 1 | 1 | unordered
2795 switch (SetCCOpcode) {
2796 default: llvm_unreachable("Condcode should be pre-legalized away");
2798 case ISD::SETEQ: return X86::COND_E;
2799 case ISD::SETOLT: // flipped
2801 case ISD::SETGT: return X86::COND_A;
2802 case ISD::SETOLE: // flipped
2804 case ISD::SETGE: return X86::COND_AE;
2805 case ISD::SETUGT: // flipped
2807 case ISD::SETLT: return X86::COND_B;
2808 case ISD::SETUGE: // flipped
2810 case ISD::SETLE: return X86::COND_BE;
2812 case ISD::SETNE: return X86::COND_NE;
2813 case ISD::SETUO: return X86::COND_P;
2814 case ISD::SETO: return X86::COND_NP;
2816 case ISD::SETUNE: return X86::COND_INVALID;
2820 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2821 /// code. Current x86 isa includes the following FP cmov instructions:
2822 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2823 static bool hasFPCMov(unsigned X86CC) {
2839 /// isFPImmLegal - Returns true if the target can instruction select the
2840 /// specified FP immediate natively. If false, the legalizer will
2841 /// materialize the FP immediate as a load from a constant pool.
2842 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2843 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2844 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2850 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2851 /// the specified range (L, H].
2852 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2853 return (Val < 0) || (Val >= Low && Val < Hi);
2856 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2857 /// specified value.
2858 static bool isUndefOrEqual(int Val, int CmpVal) {
2859 if (Val < 0 || Val == CmpVal)
2864 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2865 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2866 /// the second operand.
2867 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2868 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2869 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2870 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2871 return (Mask[0] < 2 && Mask[1] < 2);
2875 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2876 SmallVector<int, 8> M;
2878 return ::isPSHUFDMask(M, N->getValueType(0));
2881 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2882 /// is suitable for input to PSHUFHW.
2883 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2884 if (VT != MVT::v8i16)
2887 // Lower quadword copied in order or undef.
2888 for (int i = 0; i != 4; ++i)
2889 if (Mask[i] >= 0 && Mask[i] != i)
2892 // Upper quadword shuffled.
2893 for (int i = 4; i != 8; ++i)
2894 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2900 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2901 SmallVector<int, 8> M;
2903 return ::isPSHUFHWMask(M, N->getValueType(0));
2906 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2907 /// is suitable for input to PSHUFLW.
2908 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2909 if (VT != MVT::v8i16)
2912 // Upper quadword copied in order.
2913 for (int i = 4; i != 8; ++i)
2914 if (Mask[i] >= 0 && Mask[i] != i)
2917 // Lower quadword shuffled.
2918 for (int i = 0; i != 4; ++i)
2925 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2926 SmallVector<int, 8> M;
2928 return ::isPSHUFLWMask(M, N->getValueType(0));
2931 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2932 /// is suitable for input to PALIGNR.
2933 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2935 int i, e = VT.getVectorNumElements();
2937 // Do not handle v2i64 / v2f64 shuffles with palignr.
2938 if (e < 4 || !hasSSSE3)
2941 for (i = 0; i != e; ++i)
2945 // All undef, not a palignr.
2949 // Determine if it's ok to perform a palignr with only the LHS, since we
2950 // don't have access to the actual shuffle elements to see if RHS is undef.
2951 bool Unary = Mask[i] < (int)e;
2952 bool NeedsUnary = false;
2954 int s = Mask[i] - i;
2956 // Check the rest of the elements to see if they are consecutive.
2957 for (++i; i != e; ++i) {
2962 Unary = Unary && (m < (int)e);
2963 NeedsUnary = NeedsUnary || (m < s);
2965 if (NeedsUnary && !Unary)
2967 if (Unary && m != ((s+i) & (e-1)))
2969 if (!Unary && m != (s+i))
2975 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2976 SmallVector<int, 8> M;
2978 return ::isPALIGNRMask(M, N->getValueType(0), true);
2981 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2982 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2983 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2984 int NumElems = VT.getVectorNumElements();
2985 if (NumElems != 2 && NumElems != 4)
2988 int Half = NumElems / 2;
2989 for (int i = 0; i < Half; ++i)
2990 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2992 for (int i = Half; i < NumElems; ++i)
2993 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2999 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3000 SmallVector<int, 8> M;
3002 return ::isSHUFPMask(M, N->getValueType(0));
3005 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3006 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3007 /// half elements to come from vector 1 (which would equal the dest.) and
3008 /// the upper half to come from vector 2.
3009 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3010 int NumElems = VT.getVectorNumElements();
3012 if (NumElems != 2 && NumElems != 4)
3015 int Half = NumElems / 2;
3016 for (int i = 0; i < Half; ++i)
3017 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3019 for (int i = Half; i < NumElems; ++i)
3020 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3025 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3026 SmallVector<int, 8> M;
3028 return isCommutedSHUFPMask(M, N->getValueType(0));
3031 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3032 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3033 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3034 if (N->getValueType(0).getVectorNumElements() != 4)
3037 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3038 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3039 isUndefOrEqual(N->getMaskElt(1), 7) &&
3040 isUndefOrEqual(N->getMaskElt(2), 2) &&
3041 isUndefOrEqual(N->getMaskElt(3), 3);
3044 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3045 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3047 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3048 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3053 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3054 isUndefOrEqual(N->getMaskElt(1), 3) &&
3055 isUndefOrEqual(N->getMaskElt(2), 2) &&
3056 isUndefOrEqual(N->getMaskElt(3), 3);
3059 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3060 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3061 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3062 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3064 if (NumElems != 2 && NumElems != 4)
3067 for (unsigned i = 0; i < NumElems/2; ++i)
3068 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3071 for (unsigned i = NumElems/2; i < NumElems; ++i)
3072 if (!isUndefOrEqual(N->getMaskElt(i), i))
3078 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3079 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3080 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3081 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3083 if (NumElems != 2 && NumElems != 4)
3086 for (unsigned i = 0; i < NumElems/2; ++i)
3087 if (!isUndefOrEqual(N->getMaskElt(i), i))
3090 for (unsigned i = 0; i < NumElems/2; ++i)
3091 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3097 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3098 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3099 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3100 bool V2IsSplat = false) {
3101 int NumElts = VT.getVectorNumElements();
3102 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3105 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3107 int BitI1 = Mask[i+1];
3108 if (!isUndefOrEqual(BitI, j))
3111 if (!isUndefOrEqual(BitI1, NumElts))
3114 if (!isUndefOrEqual(BitI1, j + NumElts))
3121 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3122 SmallVector<int, 8> M;
3124 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3127 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3128 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3129 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3130 bool V2IsSplat = false) {
3131 int NumElts = VT.getVectorNumElements();
3132 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3135 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3137 int BitI1 = Mask[i+1];
3138 if (!isUndefOrEqual(BitI, j + NumElts/2))
3141 if (isUndefOrEqual(BitI1, NumElts))
3144 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
3151 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3152 SmallVector<int, 8> M;
3154 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3157 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3158 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3160 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3161 int NumElems = VT.getVectorNumElements();
3162 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3165 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
3167 int BitI1 = Mask[i+1];
3168 if (!isUndefOrEqual(BitI, j))
3170 if (!isUndefOrEqual(BitI1, j))
3176 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3177 SmallVector<int, 8> M;
3179 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3182 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3183 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3185 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3186 int NumElems = VT.getVectorNumElements();
3187 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3190 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3192 int BitI1 = Mask[i+1];
3193 if (!isUndefOrEqual(BitI, j))
3195 if (!isUndefOrEqual(BitI1, j))
3201 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3202 SmallVector<int, 8> M;
3204 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3207 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3208 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3209 /// MOVSD, and MOVD, i.e. setting the lowest element.
3210 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3211 if (VT.getVectorElementType().getSizeInBits() < 32)
3214 int NumElts = VT.getVectorNumElements();
3216 if (!isUndefOrEqual(Mask[0], NumElts))
3219 for (int i = 1; i < NumElts; ++i)
3220 if (!isUndefOrEqual(Mask[i], i))
3226 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3227 SmallVector<int, 8> M;
3229 return ::isMOVLMask(M, N->getValueType(0));
3232 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3233 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3234 /// element of vector 2 and the other elements to come from vector 1 in order.
3235 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3236 bool V2IsSplat = false, bool V2IsUndef = false) {
3237 int NumOps = VT.getVectorNumElements();
3238 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3241 if (!isUndefOrEqual(Mask[0], 0))
3244 for (int i = 1; i < NumOps; ++i)
3245 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3246 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3247 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3253 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3254 bool V2IsUndef = false) {
3255 SmallVector<int, 8> M;
3257 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3260 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3261 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3262 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3263 if (N->getValueType(0).getVectorNumElements() != 4)
3266 // Expect 1, 1, 3, 3
3267 for (unsigned i = 0; i < 2; ++i) {
3268 int Elt = N->getMaskElt(i);
3269 if (Elt >= 0 && Elt != 1)
3274 for (unsigned i = 2; i < 4; ++i) {
3275 int Elt = N->getMaskElt(i);
3276 if (Elt >= 0 && Elt != 3)
3281 // Don't use movshdup if it can be done with a shufps.
3282 // FIXME: verify that matching u, u, 3, 3 is what we want.
3286 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3287 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3288 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3289 if (N->getValueType(0).getVectorNumElements() != 4)
3292 // Expect 0, 0, 2, 2
3293 for (unsigned i = 0; i < 2; ++i)
3294 if (N->getMaskElt(i) > 0)
3298 for (unsigned i = 2; i < 4; ++i) {
3299 int Elt = N->getMaskElt(i);
3300 if (Elt >= 0 && Elt != 2)
3305 // Don't use movsldup if it can be done with a shufps.
3309 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3310 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3311 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3312 int e = N->getValueType(0).getVectorNumElements() / 2;
3314 for (int i = 0; i < e; ++i)
3315 if (!isUndefOrEqual(N->getMaskElt(i), i))
3317 for (int i = 0; i < e; ++i)
3318 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3323 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3324 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3325 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3326 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3327 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3329 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3331 for (int i = 0; i < NumOperands; ++i) {
3332 int Val = SVOp->getMaskElt(NumOperands-i-1);
3333 if (Val < 0) Val = 0;
3334 if (Val >= NumOperands) Val -= NumOperands;
3336 if (i != NumOperands - 1)
3342 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3343 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3344 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3345 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3347 // 8 nodes, but we only care about the last 4.
3348 for (unsigned i = 7; i >= 4; --i) {
3349 int Val = SVOp->getMaskElt(i);
3358 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3359 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3360 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3361 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3363 // 8 nodes, but we only care about the first 4.
3364 for (int i = 3; i >= 0; --i) {
3365 int Val = SVOp->getMaskElt(i);
3374 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3375 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3376 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3377 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3378 EVT VVT = N->getValueType(0);
3379 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3383 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3384 Val = SVOp->getMaskElt(i);
3388 return (Val - i) * EltSize;
3391 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3393 bool X86::isZeroNode(SDValue Elt) {
3394 return ((isa<ConstantSDNode>(Elt) &&
3395 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3396 (isa<ConstantFPSDNode>(Elt) &&
3397 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3400 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3401 /// their permute mask.
3402 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3403 SelectionDAG &DAG) {
3404 EVT VT = SVOp->getValueType(0);
3405 unsigned NumElems = VT.getVectorNumElements();
3406 SmallVector<int, 8> MaskVec;
3408 for (unsigned i = 0; i != NumElems; ++i) {
3409 int idx = SVOp->getMaskElt(i);
3411 MaskVec.push_back(idx);
3412 else if (idx < (int)NumElems)
3413 MaskVec.push_back(idx + NumElems);
3415 MaskVec.push_back(idx - NumElems);
3417 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3418 SVOp->getOperand(0), &MaskVec[0]);
3421 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3422 /// the two vector operands have swapped position.
3423 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3424 unsigned NumElems = VT.getVectorNumElements();
3425 for (unsigned i = 0; i != NumElems; ++i) {
3429 else if (idx < (int)NumElems)
3430 Mask[i] = idx + NumElems;
3432 Mask[i] = idx - NumElems;
3436 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3437 /// match movhlps. The lower half elements should come from upper half of
3438 /// V1 (and in order), and the upper half elements should come from the upper
3439 /// half of V2 (and in order).
3440 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3441 if (Op->getValueType(0).getVectorNumElements() != 4)
3443 for (unsigned i = 0, e = 2; i != e; ++i)
3444 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3446 for (unsigned i = 2; i != 4; ++i)
3447 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3452 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3453 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3455 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3456 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3458 N = N->getOperand(0).getNode();
3459 if (!ISD::isNON_EXTLoad(N))
3462 *LD = cast<LoadSDNode>(N);
3466 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3467 /// match movlp{s|d}. The lower half elements should come from lower half of
3468 /// V1 (and in order), and the upper half elements should come from the upper
3469 /// half of V2 (and in order). And since V1 will become the source of the
3470 /// MOVLP, it must be either a vector load or a scalar load to vector.
3471 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3472 ShuffleVectorSDNode *Op) {
3473 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3475 // Is V2 is a vector load, don't do this transformation. We will try to use
3476 // load folding shufps op.
3477 if (ISD::isNON_EXTLoad(V2))
3480 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3482 if (NumElems != 2 && NumElems != 4)
3484 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3485 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3487 for (unsigned i = NumElems/2; i != NumElems; ++i)
3488 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3493 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3495 static bool isSplatVector(SDNode *N) {
3496 if (N->getOpcode() != ISD::BUILD_VECTOR)
3499 SDValue SplatValue = N->getOperand(0);
3500 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3501 if (N->getOperand(i) != SplatValue)
3506 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3507 /// to an zero vector.
3508 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3509 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3510 SDValue V1 = N->getOperand(0);
3511 SDValue V2 = N->getOperand(1);
3512 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3513 for (unsigned i = 0; i != NumElems; ++i) {
3514 int Idx = N->getMaskElt(i);
3515 if (Idx >= (int)NumElems) {
3516 unsigned Opc = V2.getOpcode();
3517 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3519 if (Opc != ISD::BUILD_VECTOR ||
3520 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3522 } else if (Idx >= 0) {
3523 unsigned Opc = V1.getOpcode();
3524 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3526 if (Opc != ISD::BUILD_VECTOR ||
3527 !X86::isZeroNode(V1.getOperand(Idx)))
3534 /// getZeroVector - Returns a vector of specified type with all zero elements.
3536 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3538 assert(VT.isVector() && "Expected a vector type");
3540 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted
3541 // to their dest type. This ensures they get CSE'd.
3543 if (VT.getSizeInBits() == 64) { // MMX
3544 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3545 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3546 } else if (VT.getSizeInBits() == 128) {
3547 if (HasSSE2) { // SSE2
3548 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3549 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3551 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3552 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3554 } else if (VT.getSizeInBits() == 256) { // AVX
3555 // 256-bit logic and arithmetic instructions in AVX are
3556 // all floating-point, no support for integer ops. Default
3557 // to emitting fp zeroed vectors then.
3558 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3559 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3560 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
3562 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3565 /// getOnesVector - Returns a vector of specified type with all bits set.
3567 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3568 assert(VT.isVector() && "Expected a vector type");
3570 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3571 // type. This ensures they get CSE'd.
3572 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3574 if (VT.getSizeInBits() == 64) // MMX
3575 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3577 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3578 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3582 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3583 /// that point to V2 points to its first element.
3584 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3585 EVT VT = SVOp->getValueType(0);
3586 unsigned NumElems = VT.getVectorNumElements();
3588 bool Changed = false;
3589 SmallVector<int, 8> MaskVec;
3590 SVOp->getMask(MaskVec);
3592 for (unsigned i = 0; i != NumElems; ++i) {
3593 if (MaskVec[i] > (int)NumElems) {
3594 MaskVec[i] = NumElems;
3599 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3600 SVOp->getOperand(1), &MaskVec[0]);
3601 return SDValue(SVOp, 0);
3604 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3605 /// operation of specified width.
3606 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3608 unsigned NumElems = VT.getVectorNumElements();
3609 SmallVector<int, 8> Mask;
3610 Mask.push_back(NumElems);
3611 for (unsigned i = 1; i != NumElems; ++i)
3613 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3616 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3617 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3619 unsigned NumElems = VT.getVectorNumElements();
3620 SmallVector<int, 8> Mask;
3621 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3623 Mask.push_back(i + NumElems);
3625 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3628 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3629 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3631 unsigned NumElems = VT.getVectorNumElements();
3632 unsigned Half = NumElems/2;
3633 SmallVector<int, 8> Mask;
3634 for (unsigned i = 0; i != Half; ++i) {
3635 Mask.push_back(i + Half);
3636 Mask.push_back(i + NumElems + Half);
3638 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3641 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
3642 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
3643 if (SV->getValueType(0).getVectorNumElements() <= 4)
3644 return SDValue(SV, 0);
3646 EVT PVT = MVT::v4f32;
3647 EVT VT = SV->getValueType(0);
3648 DebugLoc dl = SV->getDebugLoc();
3649 SDValue V1 = SV->getOperand(0);
3650 int NumElems = VT.getVectorNumElements();
3651 int EltNo = SV->getSplatIndex();
3653 // unpack elements to the correct location
3654 while (NumElems > 4) {
3655 if (EltNo < NumElems/2) {
3656 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3658 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3659 EltNo -= NumElems/2;
3664 // Perform the splat.
3665 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3666 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3667 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3668 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3671 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3672 /// vector of zero or undef vector. This produces a shuffle where the low
3673 /// element of V2 is swizzled into the zero/undef vector, landing at element
3674 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3675 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3676 bool isZero, bool HasSSE2,
3677 SelectionDAG &DAG) {
3678 EVT VT = V2.getValueType();
3680 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3681 unsigned NumElems = VT.getVectorNumElements();
3682 SmallVector<int, 16> MaskVec;
3683 for (unsigned i = 0; i != NumElems; ++i)
3684 // If this is the insertion idx, put the low elt of V2 here.
3685 MaskVec.push_back(i == Idx ? NumElems : i);
3686 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3689 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
3690 /// element of the result of the vector shuffle.
3691 SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
3694 return SDValue(); // Limit search depth.
3696 SDValue V = SDValue(N, 0);
3697 EVT VT = V.getValueType();
3698 unsigned Opcode = V.getOpcode();
3700 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
3701 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
3702 Index = SV->getMaskElt(Index);
3705 return DAG.getUNDEF(VT.getVectorElementType());
3707 int NumElems = VT.getVectorNumElements();
3708 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
3709 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
3712 // Recurse into target specific vector shuffles to find scalars.
3713 if (isTargetShuffle(Opcode)) {
3714 int NumElems = VT.getVectorNumElements();
3715 SmallVector<unsigned, 16> ShuffleMask;
3719 case X86ISD::SHUFPS:
3720 case X86ISD::SHUFPD:
3721 ImmN = N->getOperand(N->getNumOperands()-1);
3722 DecodeSHUFPSMask(NumElems,
3723 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3726 case X86ISD::PUNPCKHBW:
3727 case X86ISD::PUNPCKHWD:
3728 case X86ISD::PUNPCKHDQ:
3729 case X86ISD::PUNPCKHQDQ:
3730 DecodePUNPCKHMask(NumElems, ShuffleMask);
3732 case X86ISD::UNPCKHPS:
3733 case X86ISD::UNPCKHPD:
3734 DecodeUNPCKHPMask(NumElems, ShuffleMask);
3736 case X86ISD::PUNPCKLBW:
3737 case X86ISD::PUNPCKLWD:
3738 case X86ISD::PUNPCKLDQ:
3739 case X86ISD::PUNPCKLQDQ:
3740 DecodePUNPCKLMask(NumElems, ShuffleMask);
3742 case X86ISD::UNPCKLPS:
3743 case X86ISD::UNPCKLPD:
3744 DecodeUNPCKLPMask(NumElems, ShuffleMask);
3746 case X86ISD::MOVHLPS:
3747 DecodeMOVHLPSMask(NumElems, ShuffleMask);
3749 case X86ISD::MOVLHPS:
3750 DecodeMOVLHPSMask(NumElems, ShuffleMask);
3752 case X86ISD::PSHUFD:
3753 ImmN = N->getOperand(N->getNumOperands()-1);
3754 DecodePSHUFMask(NumElems,
3755 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3758 case X86ISD::PSHUFHW:
3759 ImmN = N->getOperand(N->getNumOperands()-1);
3760 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3763 case X86ISD::PSHUFLW:
3764 ImmN = N->getOperand(N->getNumOperands()-1);
3765 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3769 case X86ISD::MOVSD: {
3770 // The index 0 always comes from the first element of the second source,
3771 // this is why MOVSS and MOVSD are used in the first place. The other
3772 // elements come from the other positions of the first source vector.
3773 unsigned OpNum = (Index == 0) ? 1 : 0;
3774 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
3778 assert("not implemented for target shuffle node");
3782 Index = ShuffleMask[Index];
3784 return DAG.getUNDEF(VT.getVectorElementType());
3786 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
3787 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
3791 // Actual nodes that may contain scalar elements
3792 if (Opcode == ISD::BIT_CONVERT) {
3793 V = V.getOperand(0);
3794 EVT SrcVT = V.getValueType();
3795 unsigned NumElems = VT.getVectorNumElements();
3797 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
3801 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
3802 return (Index == 0) ? V.getOperand(0)
3803 : DAG.getUNDEF(VT.getVectorElementType());
3805 if (V.getOpcode() == ISD::BUILD_VECTOR)
3806 return V.getOperand(Index);
3811 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
3812 /// shuffle operation which come from a consecutively from a zero. The
3813 /// search can start in two diferent directions, from left or right.
3815 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
3816 bool ZerosFromLeft, SelectionDAG &DAG) {
3819 while (i < NumElems) {
3820 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
3821 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
3822 if (!(Elt.getNode() &&
3823 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
3831 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
3832 /// MaskE correspond consecutively to elements from one of the vector operands,
3833 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
3835 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
3836 int OpIdx, int NumElems, unsigned &OpNum) {
3837 bool SeenV1 = false;
3838 bool SeenV2 = false;
3840 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
3841 int Idx = SVOp->getMaskElt(i);
3842 // Ignore undef indicies
3851 // Only accept consecutive elements from the same vector
3852 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
3856 OpNum = SeenV1 ? 0 : 1;
3860 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
3861 /// logical left shift of a vector.
3862 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3863 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3864 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3865 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3866 false /* check zeros from right */, DAG);
3872 // Considering the elements in the mask that are not consecutive zeros,
3873 // check if they consecutively come from only one of the source vectors.
3875 // V1 = {X, A, B, C} 0
3877 // vector_shuffle V1, V2 <1, 2, 3, X>
3879 if (!isShuffleMaskConsecutive(SVOp,
3880 0, // Mask Start Index
3881 NumElems-NumZeros-1, // Mask End Index
3882 NumZeros, // Where to start looking in the src vector
3883 NumElems, // Number of elements in vector
3884 OpSrc)) // Which source operand ?
3889 ShVal = SVOp->getOperand(OpSrc);
3893 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
3894 /// logical left shift of a vector.
3895 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3896 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3897 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3898 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3899 true /* check zeros from left */, DAG);
3905 // Considering the elements in the mask that are not consecutive zeros,
3906 // check if they consecutively come from only one of the source vectors.
3908 // 0 { A, B, X, X } = V2
3910 // vector_shuffle V1, V2 <X, X, 4, 5>
3912 if (!isShuffleMaskConsecutive(SVOp,
3913 NumZeros, // Mask Start Index
3914 NumElems-1, // Mask End Index
3915 0, // Where to start looking in the src vector
3916 NumElems, // Number of elements in vector
3917 OpSrc)) // Which source operand ?
3922 ShVal = SVOp->getOperand(OpSrc);
3926 /// isVectorShift - Returns true if the shuffle can be implemented as a
3927 /// logical left or right shift of a vector.
3928 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3929 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3930 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
3931 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
3937 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3939 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3940 unsigned NumNonZero, unsigned NumZero,
3942 const TargetLowering &TLI) {
3946 DebugLoc dl = Op.getDebugLoc();
3949 for (unsigned i = 0; i < 16; ++i) {
3950 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3951 if (ThisIsNonZero && First) {
3953 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3955 V = DAG.getUNDEF(MVT::v8i16);
3960 SDValue ThisElt(0, 0), LastElt(0, 0);
3961 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3962 if (LastIsNonZero) {
3963 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3964 MVT::i16, Op.getOperand(i-1));
3966 if (ThisIsNonZero) {
3967 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3968 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3969 ThisElt, DAG.getConstant(8, MVT::i8));
3971 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3975 if (ThisElt.getNode())
3976 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3977 DAG.getIntPtrConstant(i/2));
3981 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3984 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3986 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3987 unsigned NumNonZero, unsigned NumZero,
3989 const TargetLowering &TLI) {
3993 DebugLoc dl = Op.getDebugLoc();
3996 for (unsigned i = 0; i < 8; ++i) {
3997 bool isNonZero = (NonZeros & (1 << i)) != 0;
4001 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4003 V = DAG.getUNDEF(MVT::v8i16);
4006 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4007 MVT::v8i16, V, Op.getOperand(i),
4008 DAG.getIntPtrConstant(i));
4015 /// getVShift - Return a vector logical shift node.
4017 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4018 unsigned NumBits, SelectionDAG &DAG,
4019 const TargetLowering &TLI, DebugLoc dl) {
4020 bool isMMX = VT.getSizeInBits() == 64;
4021 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
4022 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4023 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
4024 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4025 DAG.getNode(Opc, dl, ShVT, SrcOp,
4026 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
4030 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4031 SelectionDAG &DAG) const {
4033 // Check if the scalar load can be widened into a vector load. And if
4034 // the address is "base + cst" see if the cst can be "absorbed" into
4035 // the shuffle mask.
4036 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4037 SDValue Ptr = LD->getBasePtr();
4038 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4040 EVT PVT = LD->getValueType(0);
4041 if (PVT != MVT::i32 && PVT != MVT::f32)
4046 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4047 FI = FINode->getIndex();
4049 } else if (Ptr.getOpcode() == ISD::ADD &&
4050 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4051 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4052 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4053 Offset = Ptr.getConstantOperandVal(1);
4054 Ptr = Ptr.getOperand(0);
4059 SDValue Chain = LD->getChain();
4060 // Make sure the stack object alignment is at least 16.
4061 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4062 if (DAG.InferPtrAlignment(Ptr) < 16) {
4063 if (MFI->isFixedObjectIndex(FI)) {
4064 // Can't change the alignment. FIXME: It's possible to compute
4065 // the exact stack offset and reference FI + adjust offset instead.
4066 // If someone *really* cares about this. That's the way to implement it.
4069 MFI->setObjectAlignment(FI, 16);
4073 // (Offset % 16) must be multiple of 4. Then address is then
4074 // Ptr + (Offset & ~15).
4077 if ((Offset % 16) & 3)
4079 int64_t StartOffset = Offset & ~15;
4081 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4082 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4084 int EltNo = (Offset - StartOffset) >> 2;
4085 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
4086 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
4087 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
4089 // Canonicalize it to a v4i32 shuffle.
4090 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
4091 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4092 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
4093 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
4099 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4100 /// vector of type 'VT', see if the elements can be replaced by a single large
4101 /// load which has the same value as a build_vector whose operands are 'elts'.
4103 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4105 /// FIXME: we'd also like to handle the case where the last elements are zero
4106 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4107 /// There's even a handy isZeroNode for that purpose.
4108 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4109 DebugLoc &dl, SelectionDAG &DAG) {
4110 EVT EltVT = VT.getVectorElementType();
4111 unsigned NumElems = Elts.size();
4113 LoadSDNode *LDBase = NULL;
4114 unsigned LastLoadedElt = -1U;
4116 // For each element in the initializer, see if we've found a load or an undef.
4117 // If we don't find an initial load element, or later load elements are
4118 // non-consecutive, bail out.
4119 for (unsigned i = 0; i < NumElems; ++i) {
4120 SDValue Elt = Elts[i];
4122 if (!Elt.getNode() ||
4123 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4126 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4128 LDBase = cast<LoadSDNode>(Elt.getNode());
4132 if (Elt.getOpcode() == ISD::UNDEF)
4135 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4136 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4141 // If we have found an entire vector of loads and undefs, then return a large
4142 // load of the entire vector width starting at the base pointer. If we found
4143 // consecutive loads for the low half, generate a vzext_load node.
4144 if (LastLoadedElt == NumElems - 1) {
4145 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4146 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
4147 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
4148 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4149 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
4150 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
4151 LDBase->isVolatile(), LDBase->isNonTemporal(),
4152 LDBase->getAlignment());
4153 } else if (NumElems == 4 && LastLoadedElt == 1) {
4154 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4155 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4156 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
4157 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
4163 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4164 DebugLoc dl = Op.getDebugLoc();
4165 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1.
4166 // All one's are handled with pcmpeqd. In AVX, zero's are handled with
4167 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd
4168 // is present, so AllOnes is ignored.
4169 if (ISD::isBuildVectorAllZeros(Op.getNode()) ||
4170 (Op.getValueType().getSizeInBits() != 256 &&
4171 ISD::isBuildVectorAllOnes(Op.getNode()))) {
4172 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
4173 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
4174 // eliminated on x86-32 hosts.
4175 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
4178 if (ISD::isBuildVectorAllOnes(Op.getNode()))
4179 return getOnesVector(Op.getValueType(), DAG, dl);
4180 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4183 EVT VT = Op.getValueType();
4184 EVT ExtVT = VT.getVectorElementType();
4185 unsigned EVTBits = ExtVT.getSizeInBits();
4187 unsigned NumElems = Op.getNumOperands();
4188 unsigned NumZero = 0;
4189 unsigned NumNonZero = 0;
4190 unsigned NonZeros = 0;
4191 bool IsAllConstants = true;
4192 SmallSet<SDValue, 8> Values;
4193 for (unsigned i = 0; i < NumElems; ++i) {
4194 SDValue Elt = Op.getOperand(i);
4195 if (Elt.getOpcode() == ISD::UNDEF)
4198 if (Elt.getOpcode() != ISD::Constant &&
4199 Elt.getOpcode() != ISD::ConstantFP)
4200 IsAllConstants = false;
4201 if (X86::isZeroNode(Elt))
4204 NonZeros |= (1 << i);
4209 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4210 if (NumNonZero == 0)
4211 return DAG.getUNDEF(VT);
4213 // Special case for single non-zero, non-undef, element.
4214 if (NumNonZero == 1) {
4215 unsigned Idx = CountTrailingZeros_32(NonZeros);
4216 SDValue Item = Op.getOperand(Idx);
4218 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4219 // the value are obviously zero, truncate the value to i32 and do the
4220 // insertion that way. Only do this if the value is non-constant or if the
4221 // value is a constant being inserted into element 0. It is cheaper to do
4222 // a constant pool load than it is to do a movd + shuffle.
4223 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4224 (!IsAllConstants || Idx == 0)) {
4225 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4226 // Handle MMX and SSE both.
4227 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
4228 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
4230 // Truncate the value (which may itself be a constant) to i32, and
4231 // convert it to a vector with movd (S2V+shuffle to zero extend).
4232 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4233 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4234 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4235 Subtarget->hasSSE2(), DAG);
4237 // Now we have our 32-bit value zero extended in the low element of
4238 // a vector. If Idx != 0, swizzle it into place.
4240 SmallVector<int, 4> Mask;
4241 Mask.push_back(Idx);
4242 for (unsigned i = 1; i != VecElts; ++i)
4244 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4245 DAG.getUNDEF(Item.getValueType()),
4248 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
4252 // If we have a constant or non-constant insertion into the low element of
4253 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4254 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4255 // depending on what the source datatype is.
4258 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4259 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4260 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4261 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4262 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4263 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4265 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4266 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4267 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
4268 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4269 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4270 Subtarget->hasSSE2(), DAG);
4271 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
4275 // Is it a vector logical left shift?
4276 if (NumElems == 2 && Idx == 1 &&
4277 X86::isZeroNode(Op.getOperand(0)) &&
4278 !X86::isZeroNode(Op.getOperand(1))) {
4279 unsigned NumBits = VT.getSizeInBits();
4280 return getVShift(true, VT,
4281 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4282 VT, Op.getOperand(1)),
4283 NumBits/2, DAG, *this, dl);
4286 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4289 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4290 // is a non-constant being inserted into an element other than the low one,
4291 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4292 // movd/movss) to move this into the low element, then shuffle it into
4294 if (EVTBits == 32) {
4295 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4297 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4298 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4299 Subtarget->hasSSE2(), DAG);
4300 SmallVector<int, 8> MaskVec;
4301 for (unsigned i = 0; i < NumElems; i++)
4302 MaskVec.push_back(i == Idx ? 0 : 1);
4303 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4307 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4308 if (Values.size() == 1) {
4309 if (EVTBits == 32) {
4310 // Instead of a shuffle like this:
4311 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4312 // Check if it's possible to issue this instead.
4313 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4314 unsigned Idx = CountTrailingZeros_32(NonZeros);
4315 SDValue Item = Op.getOperand(Idx);
4316 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4317 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4322 // A vector full of immediates; various special cases are already
4323 // handled, so this is best done with a single constant-pool load.
4327 // Let legalizer expand 2-wide build_vectors.
4328 if (EVTBits == 64) {
4329 if (NumNonZero == 1) {
4330 // One half is zero or undef.
4331 unsigned Idx = CountTrailingZeros_32(NonZeros);
4332 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4333 Op.getOperand(Idx));
4334 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4335 Subtarget->hasSSE2(), DAG);
4340 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4341 if (EVTBits == 8 && NumElems == 16) {
4342 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4344 if (V.getNode()) return V;
4347 if (EVTBits == 16 && NumElems == 8) {
4348 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4350 if (V.getNode()) return V;
4353 // If element VT is == 32 bits, turn it into a number of shuffles.
4354 SmallVector<SDValue, 8> V;
4356 if (NumElems == 4 && NumZero > 0) {
4357 for (unsigned i = 0; i < 4; ++i) {
4358 bool isZero = !(NonZeros & (1 << i));
4360 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4362 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4365 for (unsigned i = 0; i < 2; ++i) {
4366 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4369 V[i] = V[i*2]; // Must be a zero vector.
4372 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4375 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4378 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4383 SmallVector<int, 8> MaskVec;
4384 bool Reverse = (NonZeros & 0x3) == 2;
4385 for (unsigned i = 0; i < 2; ++i)
4386 MaskVec.push_back(Reverse ? 1-i : i);
4387 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4388 for (unsigned i = 0; i < 2; ++i)
4389 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4390 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4393 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4394 // Check for a build vector of consecutive loads.
4395 for (unsigned i = 0; i < NumElems; ++i)
4396 V[i] = Op.getOperand(i);
4398 // Check for elements which are consecutive loads.
4399 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4403 // For SSE 4.1, use insertps to put the high elements into the low element.
4404 if (getSubtarget()->hasSSE41()) {
4406 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
4407 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
4409 Result = DAG.getUNDEF(VT);
4411 for (unsigned i = 1; i < NumElems; ++i) {
4412 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
4413 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
4414 Op.getOperand(i), DAG.getIntPtrConstant(i));
4419 // Otherwise, expand into a number of unpckl*, start by extending each of
4420 // our (non-undef) elements to the full vector width with the element in the
4421 // bottom slot of the vector (which generates no code for SSE).
4422 for (unsigned i = 0; i < NumElems; ++i) {
4423 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4424 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4426 V[i] = DAG.getUNDEF(VT);
4429 // Next, we iteratively mix elements, e.g. for v4f32:
4430 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4431 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4432 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4433 unsigned EltStride = NumElems >> 1;
4434 while (EltStride != 0) {
4435 for (unsigned i = 0; i < EltStride; ++i) {
4436 // If V[i+EltStride] is undef and this is the first round of mixing,
4437 // then it is safe to just drop this shuffle: V[i] is already in the
4438 // right place, the one element (since it's the first round) being
4439 // inserted as undef can be dropped. This isn't safe for successive
4440 // rounds because they will permute elements within both vectors.
4441 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
4442 EltStride == NumElems/2)
4445 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
4455 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4456 // We support concatenate two MMX registers and place them in a MMX
4457 // register. This is better than doing a stack convert.
4458 DebugLoc dl = Op.getDebugLoc();
4459 EVT ResVT = Op.getValueType();
4460 assert(Op.getNumOperands() == 2);
4461 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4462 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4464 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
4465 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4466 InVec = Op.getOperand(1);
4467 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4468 unsigned NumElts = ResVT.getVectorNumElements();
4469 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4470 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4471 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4473 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
4474 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4475 Mask[0] = 0; Mask[1] = 2;
4476 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4478 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4481 // v8i16 shuffles - Prefer shuffles in the following order:
4482 // 1. [all] pshuflw, pshufhw, optional move
4483 // 2. [ssse3] 1 x pshufb
4484 // 3. [ssse3] 2 x pshufb + 1 x por
4485 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4487 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
4488 SelectionDAG &DAG) const {
4489 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4490 SDValue V1 = SVOp->getOperand(0);
4491 SDValue V2 = SVOp->getOperand(1);
4492 DebugLoc dl = SVOp->getDebugLoc();
4493 SmallVector<int, 8> MaskVals;
4495 // Determine if more than 1 of the words in each of the low and high quadwords
4496 // of the result come from the same quadword of one of the two inputs. Undef
4497 // mask values count as coming from any quadword, for better codegen.
4498 SmallVector<unsigned, 4> LoQuad(4);
4499 SmallVector<unsigned, 4> HiQuad(4);
4500 BitVector InputQuads(4);
4501 for (unsigned i = 0; i < 8; ++i) {
4502 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4503 int EltIdx = SVOp->getMaskElt(i);
4504 MaskVals.push_back(EltIdx);
4513 InputQuads.set(EltIdx / 4);
4516 int BestLoQuad = -1;
4517 unsigned MaxQuad = 1;
4518 for (unsigned i = 0; i < 4; ++i) {
4519 if (LoQuad[i] > MaxQuad) {
4521 MaxQuad = LoQuad[i];
4525 int BestHiQuad = -1;
4527 for (unsigned i = 0; i < 4; ++i) {
4528 if (HiQuad[i] > MaxQuad) {
4530 MaxQuad = HiQuad[i];
4534 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4535 // of the two input vectors, shuffle them into one input vector so only a
4536 // single pshufb instruction is necessary. If There are more than 2 input
4537 // quads, disable the next transformation since it does not help SSSE3.
4538 bool V1Used = InputQuads[0] || InputQuads[1];
4539 bool V2Used = InputQuads[2] || InputQuads[3];
4540 if (Subtarget->hasSSSE3()) {
4541 if (InputQuads.count() == 2 && V1Used && V2Used) {
4542 BestLoQuad = InputQuads.find_first();
4543 BestHiQuad = InputQuads.find_next(BestLoQuad);
4545 if (InputQuads.count() > 2) {
4551 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4552 // the shuffle mask. If a quad is scored as -1, that means that it contains
4553 // words from all 4 input quadwords.
4555 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4556 SmallVector<int, 8> MaskV;
4557 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4558 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4559 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4560 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
4561 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
4562 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
4564 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4565 // source words for the shuffle, to aid later transformations.
4566 bool AllWordsInNewV = true;
4567 bool InOrder[2] = { true, true };
4568 for (unsigned i = 0; i != 8; ++i) {
4569 int idx = MaskVals[i];
4571 InOrder[i/4] = false;
4572 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4574 AllWordsInNewV = false;
4578 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4579 if (AllWordsInNewV) {
4580 for (int i = 0; i != 8; ++i) {
4581 int idx = MaskVals[i];
4584 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4585 if ((idx != i) && idx < 4)
4587 if ((idx != i) && idx > 3)
4596 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4597 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4598 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4599 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
4600 unsigned TargetMask = 0;
4601 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4602 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4603 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
4604 X86::getShufflePSHUFLWImmediate(NewV.getNode());
4605 V1 = NewV.getOperand(0);
4606 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
4610 // If we have SSSE3, and all words of the result are from 1 input vector,
4611 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4612 // is present, fall back to case 4.
4613 if (Subtarget->hasSSSE3()) {
4614 SmallVector<SDValue,16> pshufbMask;
4616 // If we have elements from both input vectors, set the high bit of the
4617 // shuffle mask element to zero out elements that come from V2 in the V1
4618 // mask, and elements that come from V1 in the V2 mask, so that the two
4619 // results can be OR'd together.
4620 bool TwoInputs = V1Used && V2Used;
4621 for (unsigned i = 0; i != 8; ++i) {
4622 int EltIdx = MaskVals[i] * 2;
4623 if (TwoInputs && (EltIdx >= 16)) {
4624 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4625 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4628 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4629 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4631 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4632 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4633 DAG.getNode(ISD::BUILD_VECTOR, dl,
4634 MVT::v16i8, &pshufbMask[0], 16));
4636 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4638 // Calculate the shuffle mask for the second input, shuffle it, and
4639 // OR it with the first shuffled input.
4641 for (unsigned i = 0; i != 8; ++i) {
4642 int EltIdx = MaskVals[i] * 2;
4644 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4645 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4648 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4649 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4651 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4652 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4653 DAG.getNode(ISD::BUILD_VECTOR, dl,
4654 MVT::v16i8, &pshufbMask[0], 16));
4655 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4656 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4659 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4660 // and update MaskVals with new element order.
4661 BitVector InOrder(8);
4662 if (BestLoQuad >= 0) {
4663 SmallVector<int, 8> MaskV;
4664 for (int i = 0; i != 4; ++i) {
4665 int idx = MaskVals[i];
4667 MaskV.push_back(-1);
4669 } else if ((idx / 4) == BestLoQuad) {
4670 MaskV.push_back(idx & 3);
4673 MaskV.push_back(-1);
4676 for (unsigned i = 4; i != 8; ++i)
4678 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4681 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4682 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
4684 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
4688 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4689 // and update MaskVals with the new element order.
4690 if (BestHiQuad >= 0) {
4691 SmallVector<int, 8> MaskV;
4692 for (unsigned i = 0; i != 4; ++i)
4694 for (unsigned i = 4; i != 8; ++i) {
4695 int idx = MaskVals[i];
4697 MaskV.push_back(-1);
4699 } else if ((idx / 4) == BestHiQuad) {
4700 MaskV.push_back((idx & 3) + 4);
4703 MaskV.push_back(-1);
4706 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4709 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4710 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
4712 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
4716 // In case BestHi & BestLo were both -1, which means each quadword has a word
4717 // from each of the four input quadwords, calculate the InOrder bitvector now
4718 // before falling through to the insert/extract cleanup.
4719 if (BestLoQuad == -1 && BestHiQuad == -1) {
4721 for (int i = 0; i != 8; ++i)
4722 if (MaskVals[i] < 0 || MaskVals[i] == i)
4726 // The other elements are put in the right place using pextrw and pinsrw.
4727 for (unsigned i = 0; i != 8; ++i) {
4730 int EltIdx = MaskVals[i];
4733 SDValue ExtOp = (EltIdx < 8)
4734 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4735 DAG.getIntPtrConstant(EltIdx))
4736 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4737 DAG.getIntPtrConstant(EltIdx - 8));
4738 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4739 DAG.getIntPtrConstant(i));
4744 // v16i8 shuffles - Prefer shuffles in the following order:
4745 // 1. [ssse3] 1 x pshufb
4746 // 2. [ssse3] 2 x pshufb + 1 x por
4747 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4749 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4751 const X86TargetLowering &TLI) {
4752 SDValue V1 = SVOp->getOperand(0);
4753 SDValue V2 = SVOp->getOperand(1);
4754 DebugLoc dl = SVOp->getDebugLoc();
4755 SmallVector<int, 16> MaskVals;
4756 SVOp->getMask(MaskVals);
4758 // If we have SSSE3, case 1 is generated when all result bytes come from
4759 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4760 // present, fall back to case 3.
4761 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4764 for (unsigned i = 0; i < 16; ++i) {
4765 int EltIdx = MaskVals[i];
4774 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4775 if (TLI.getSubtarget()->hasSSSE3()) {
4776 SmallVector<SDValue,16> pshufbMask;
4778 // If all result elements are from one input vector, then only translate
4779 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4781 // Otherwise, we have elements from both input vectors, and must zero out
4782 // elements that come from V2 in the first mask, and V1 in the second mask
4783 // so that we can OR them together.
4784 bool TwoInputs = !(V1Only || V2Only);
4785 for (unsigned i = 0; i != 16; ++i) {
4786 int EltIdx = MaskVals[i];
4787 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4788 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4791 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4793 // If all the elements are from V2, assign it to V1 and return after
4794 // building the first pshufb.
4797 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4798 DAG.getNode(ISD::BUILD_VECTOR, dl,
4799 MVT::v16i8, &pshufbMask[0], 16));
4803 // Calculate the shuffle mask for the second input, shuffle it, and
4804 // OR it with the first shuffled input.
4806 for (unsigned i = 0; i != 16; ++i) {
4807 int EltIdx = MaskVals[i];
4809 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4812 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4814 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4815 DAG.getNode(ISD::BUILD_VECTOR, dl,
4816 MVT::v16i8, &pshufbMask[0], 16));
4817 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4820 // No SSSE3 - Calculate in place words and then fix all out of place words
4821 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4822 // the 16 different words that comprise the two doublequadword input vectors.
4823 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4824 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4825 SDValue NewV = V2Only ? V2 : V1;
4826 for (int i = 0; i != 8; ++i) {
4827 int Elt0 = MaskVals[i*2];
4828 int Elt1 = MaskVals[i*2+1];
4830 // This word of the result is all undef, skip it.
4831 if (Elt0 < 0 && Elt1 < 0)
4834 // This word of the result is already in the correct place, skip it.
4835 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4837 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4840 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4841 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4844 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4845 // using a single extract together, load it and store it.
4846 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4847 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4848 DAG.getIntPtrConstant(Elt1 / 2));
4849 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4850 DAG.getIntPtrConstant(i));
4854 // If Elt1 is defined, extract it from the appropriate source. If the
4855 // source byte is not also odd, shift the extracted word left 8 bits
4856 // otherwise clear the bottom 8 bits if we need to do an or.
4858 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4859 DAG.getIntPtrConstant(Elt1 / 2));
4860 if ((Elt1 & 1) == 0)
4861 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4862 DAG.getConstant(8, TLI.getShiftAmountTy()));
4864 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4865 DAG.getConstant(0xFF00, MVT::i16));
4867 // If Elt0 is defined, extract it from the appropriate source. If the
4868 // source byte is not also even, shift the extracted word right 8 bits. If
4869 // Elt1 was also defined, OR the extracted values together before
4870 // inserting them in the result.
4872 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4873 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4874 if ((Elt0 & 1) != 0)
4875 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4876 DAG.getConstant(8, TLI.getShiftAmountTy()));
4878 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4879 DAG.getConstant(0x00FF, MVT::i16));
4880 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4883 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4884 DAG.getIntPtrConstant(i));
4886 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4889 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4890 /// ones, or rewriting v4i32 / v2i32 as 2 wide ones if possible. This can be
4891 /// done when every pair / quad of shuffle mask elements point to elements in
4892 /// the right sequence. e.g.
4893 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4895 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4897 const TargetLowering &TLI, DebugLoc dl) {
4898 EVT VT = SVOp->getValueType(0);
4899 SDValue V1 = SVOp->getOperand(0);
4900 SDValue V2 = SVOp->getOperand(1);
4901 unsigned NumElems = VT.getVectorNumElements();
4902 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4903 EVT MaskVT = (NewWidth == 4) ? MVT::v4i16 : MVT::v2i32;
4905 switch (VT.getSimpleVT().SimpleTy) {
4906 default: assert(false && "Unexpected!");
4907 case MVT::v4f32: NewVT = MVT::v2f64; break;
4908 case MVT::v4i32: NewVT = MVT::v2i64; break;
4909 case MVT::v8i16: NewVT = MVT::v4i32; break;
4910 case MVT::v16i8: NewVT = MVT::v4i32; break;
4913 if (NewWidth == 2) {
4919 int Scale = NumElems / NewWidth;
4920 SmallVector<int, 8> MaskVec;
4921 for (unsigned i = 0; i < NumElems; i += Scale) {
4923 for (int j = 0; j < Scale; ++j) {
4924 int EltIdx = SVOp->getMaskElt(i+j);
4928 StartIdx = EltIdx - (EltIdx % Scale);
4929 if (EltIdx != StartIdx + j)
4933 MaskVec.push_back(-1);
4935 MaskVec.push_back(StartIdx / Scale);
4938 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4939 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4940 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4943 /// getVZextMovL - Return a zero-extending vector move low node.
4945 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4946 SDValue SrcOp, SelectionDAG &DAG,
4947 const X86Subtarget *Subtarget, DebugLoc dl) {
4948 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4949 LoadSDNode *LD = NULL;
4950 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4951 LD = dyn_cast<LoadSDNode>(SrcOp);
4953 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4955 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4956 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4957 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4958 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4959 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4961 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4962 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4963 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4964 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4972 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4973 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4974 DAG.getNode(ISD::BIT_CONVERT, dl,
4978 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4981 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4982 SDValue V1 = SVOp->getOperand(0);
4983 SDValue V2 = SVOp->getOperand(1);
4984 DebugLoc dl = SVOp->getDebugLoc();
4985 EVT VT = SVOp->getValueType(0);
4987 SmallVector<std::pair<int, int>, 8> Locs;
4989 SmallVector<int, 8> Mask1(4U, -1);
4990 SmallVector<int, 8> PermMask;
4991 SVOp->getMask(PermMask);
4995 for (unsigned i = 0; i != 4; ++i) {
4996 int Idx = PermMask[i];
4998 Locs[i] = std::make_pair(-1, -1);
5000 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5002 Locs[i] = std::make_pair(0, NumLo);
5006 Locs[i] = std::make_pair(1, NumHi);
5008 Mask1[2+NumHi] = Idx;
5014 if (NumLo <= 2 && NumHi <= 2) {
5015 // If no more than two elements come from either vector. This can be
5016 // implemented with two shuffles. First shuffle gather the elements.
5017 // The second shuffle, which takes the first shuffle as both of its
5018 // vector operands, put the elements into the right order.
5019 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5021 SmallVector<int, 8> Mask2(4U, -1);
5023 for (unsigned i = 0; i != 4; ++i) {
5024 if (Locs[i].first == -1)
5027 unsigned Idx = (i < 2) ? 0 : 4;
5028 Idx += Locs[i].first * 2 + Locs[i].second;
5033 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5034 } else if (NumLo == 3 || NumHi == 3) {
5035 // Otherwise, we must have three elements from one vector, call it X, and
5036 // one element from the other, call it Y. First, use a shufps to build an
5037 // intermediate vector with the one element from Y and the element from X
5038 // that will be in the same half in the final destination (the indexes don't
5039 // matter). Then, use a shufps to build the final vector, taking the half
5040 // containing the element from Y from the intermediate, and the other half
5043 // Normalize it so the 3 elements come from V1.
5044 CommuteVectorShuffleMask(PermMask, VT);
5048 // Find the element from V2.
5050 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5051 int Val = PermMask[HiIndex];
5058 Mask1[0] = PermMask[HiIndex];
5060 Mask1[2] = PermMask[HiIndex^1];
5062 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5065 Mask1[0] = PermMask[0];
5066 Mask1[1] = PermMask[1];
5067 Mask1[2] = HiIndex & 1 ? 6 : 4;
5068 Mask1[3] = HiIndex & 1 ? 4 : 6;
5069 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5071 Mask1[0] = HiIndex & 1 ? 2 : 0;
5072 Mask1[1] = HiIndex & 1 ? 0 : 2;
5073 Mask1[2] = PermMask[2];
5074 Mask1[3] = PermMask[3];
5079 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5083 // Break it into (shuffle shuffle_hi, shuffle_lo).
5085 SmallVector<int,8> LoMask(4U, -1);
5086 SmallVector<int,8> HiMask(4U, -1);
5088 SmallVector<int,8> *MaskPtr = &LoMask;
5089 unsigned MaskIdx = 0;
5092 for (unsigned i = 0; i != 4; ++i) {
5099 int Idx = PermMask[i];
5101 Locs[i] = std::make_pair(-1, -1);
5102 } else if (Idx < 4) {
5103 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5104 (*MaskPtr)[LoIdx] = Idx;
5107 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5108 (*MaskPtr)[HiIdx] = Idx;
5113 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5114 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5115 SmallVector<int, 8> MaskOps;
5116 for (unsigned i = 0; i != 4; ++i) {
5117 if (Locs[i].first == -1) {
5118 MaskOps.push_back(-1);
5120 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5121 MaskOps.push_back(Idx);
5124 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5127 static bool MayFoldVectorLoad(SDValue V) {
5128 if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT)
5129 V = V.getOperand(0);
5130 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5131 V = V.getOperand(0);
5138 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
5140 SDValue V1 = Op.getOperand(0);
5141 SDValue V2 = Op.getOperand(1);
5142 EVT VT = Op.getValueType();
5144 assert(VT != MVT::v2i64 && "unsupported shuffle type");
5146 if (HasSSE2 && VT == MVT::v2f64)
5147 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
5150 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
5154 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
5155 SDValue V1 = Op.getOperand(0);
5156 SDValue V2 = Op.getOperand(1);
5157 EVT VT = Op.getValueType();
5159 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
5160 "unsupported shuffle type");
5162 if (V2.getOpcode() == ISD::UNDEF)
5166 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
5170 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
5171 SDValue V1 = Op.getOperand(0);
5172 SDValue V2 = Op.getOperand(1);
5173 EVT VT = Op.getValueType();
5174 unsigned NumElems = VT.getVectorNumElements();
5176 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
5177 // operand of these instructions is only memory, so check if there's a
5178 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
5180 bool CanFoldLoad = false;
5182 // Trivial case, when V2 comes from a load.
5183 if (MayFoldVectorLoad(V2))
5186 // When V1 is a load, it can be folded later into a store in isel, example:
5187 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
5189 // (MOVLPSmr addr:$src1, VR128:$src2)
5190 // So, recognize this potential and also use MOVLPS or MOVLPD
5191 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5195 if (HasSSE2 && NumElems == 2)
5196 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
5199 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
5202 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5203 // movl and movlp will both match v2i64, but v2i64 is never matched by
5204 // movl earlier because we make it strict to avoid messing with the movlp load
5205 // folding logic (see the code above getMOVLP call). Match it here then,
5206 // this is horrible, but will stay like this until we move all shuffle
5207 // matching to x86 specific nodes. Note that for the 1st condition all
5208 // types are matched with movsd.
5209 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
5210 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5212 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5215 assert(VT != MVT::v4i32 && "unsupported shuffle type");
5217 // Invert the operand order and use SHUFPS to match it.
5218 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
5219 X86::getShuffleSHUFImmediate(SVOp), DAG);
5222 static inline unsigned getUNPCKLOpcode(EVT VT) {
5223 switch(VT.getSimpleVT().SimpleTy) {
5224 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5225 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5226 case MVT::v4f32: return X86ISD::UNPCKLPS;
5227 case MVT::v2f64: return X86ISD::UNPCKLPD;
5228 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5229 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5231 llvm_unreachable("Unknow type for unpckl");
5236 static inline unsigned getUNPCKHOpcode(EVT VT) {
5237 switch(VT.getSimpleVT().SimpleTy) {
5238 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
5239 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
5240 case MVT::v4f32: return X86ISD::UNPCKHPS;
5241 case MVT::v2f64: return X86ISD::UNPCKHPD;
5242 case MVT::v16i8: return X86ISD::PUNPCKHBW;
5243 case MVT::v8i16: return X86ISD::PUNPCKHWD;
5245 llvm_unreachable("Unknow type for unpckh");
5251 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
5252 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5253 SDValue V1 = Op.getOperand(0);
5254 SDValue V2 = Op.getOperand(1);
5255 EVT VT = Op.getValueType();
5256 DebugLoc dl = Op.getDebugLoc();
5257 unsigned NumElems = VT.getVectorNumElements();
5258 bool isMMX = VT.getSizeInBits() == 64;
5259 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
5260 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5261 bool V1IsSplat = false;
5262 bool V2IsSplat = false;
5263 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
5264 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
5265 MachineFunction &MF = DAG.getMachineFunction();
5266 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
5268 if (isZeroShuffle(SVOp))
5269 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5271 // Promote splats to v4f32.
5272 if (SVOp->isSplat()) {
5273 if (isMMX || NumElems < 4)
5275 return PromoteSplat(SVOp, DAG);
5278 // If the shuffle can be profitably rewritten as a narrower shuffle, then
5280 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
5281 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
5282 if (NewOp.getNode())
5283 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5284 LowerVECTOR_SHUFFLE(NewOp, DAG));
5285 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
5286 // FIXME: Figure out a cleaner way to do this.
5287 // Try to make use of movq to zero out the top part.
5288 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
5289 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
5290 if (NewOp.getNode()) {
5291 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
5292 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
5293 DAG, Subtarget, dl);
5295 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
5296 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
5297 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
5298 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
5299 DAG, Subtarget, dl);
5303 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
5304 // unpckh_undef). Only use pshufd if speed is more important than size.
5305 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
5306 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5307 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5308 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
5309 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5310 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5312 if (X86::isPSHUFDMask(SVOp)) {
5313 // The actual implementation will match the mask in the if above and then
5314 // during isel it can match several different instructions, not only pshufd
5315 // as its name says, sad but true, emulate the behavior for now...
5316 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
5317 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
5319 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5321 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
5322 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
5324 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5325 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
5328 if (VT == MVT::v4f32)
5329 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
5333 // Check if this can be converted into a logical shift.
5334 bool isLeft = false;
5337 bool isShift = getSubtarget()->hasSSE2() &&
5338 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
5339 if (isShift && ShVal.hasOneUse()) {
5340 // If the shifted value has multiple uses, it may be cheaper to use
5341 // v_set0 + movlhps or movhlps, etc.
5342 EVT EltVT = VT.getVectorElementType();
5343 ShAmt *= EltVT.getSizeInBits();
5344 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5347 if (X86::isMOVLMask(SVOp)) {
5350 if (ISD::isBuildVectorAllZeros(V1.getNode()))
5351 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
5352 if (!isMMX && !X86::isMOVLPMask(SVOp)) {
5353 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5354 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5356 if (VT == MVT::v4i32 || VT == MVT::v4f32)
5357 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5361 // FIXME: fold these into legal mask.
5363 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
5364 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
5366 if (X86::isMOVHLPSMask(SVOp))
5367 return getMOVHighToLow(Op, dl, DAG);
5369 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5370 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
5372 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5373 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
5375 if (X86::isMOVLPMask(SVOp))
5376 return getMOVLP(Op, dl, DAG, HasSSE2);
5379 if (ShouldXformToMOVHLPS(SVOp) ||
5380 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
5381 return CommuteVectorShuffle(SVOp, DAG);
5384 // No better options. Use a vshl / vsrl.
5385 EVT EltVT = VT.getVectorElementType();
5386 ShAmt *= EltVT.getSizeInBits();
5387 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5390 bool Commuted = false;
5391 // FIXME: This should also accept a bitcast of a splat? Be careful, not
5392 // 1,1,1,1 -> v8i16 though.
5393 V1IsSplat = isSplatVector(V1.getNode());
5394 V2IsSplat = isSplatVector(V2.getNode());
5396 // Canonicalize the splat or undef, if present, to be on the RHS.
5397 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
5398 Op = CommuteVectorShuffle(SVOp, DAG);
5399 SVOp = cast<ShuffleVectorSDNode>(Op);
5400 V1 = SVOp->getOperand(0);
5401 V2 = SVOp->getOperand(1);
5402 std::swap(V1IsSplat, V2IsSplat);
5403 std::swap(V1IsUndef, V2IsUndef);
5407 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
5408 // Shuffling low element of v1 into undef, just return v1.
5411 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
5412 // the instruction selector will not match, so get a canonical MOVL with
5413 // swapped operands to undo the commute.
5414 return getMOVL(DAG, dl, VT, V2, V1);
5417 if (X86::isUNPCKLMask(SVOp))
5419 Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
5421 if (X86::isUNPCKHMask(SVOp))
5423 Op : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
5426 // Normalize mask so all entries that point to V2 points to its first
5427 // element then try to match unpck{h|l} again. If match, return a
5428 // new vector_shuffle with the corrected mask.
5429 SDValue NewMask = NormalizeMask(SVOp, DAG);
5430 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
5431 if (NSVOp != SVOp) {
5432 if (X86::isUNPCKLMask(NSVOp, true)) {
5434 } else if (X86::isUNPCKHMask(NSVOp, true)) {
5441 // Commute is back and try unpck* again.
5442 // FIXME: this seems wrong.
5443 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
5444 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
5446 if (X86::isUNPCKLMask(NewSVOp))
5448 NewOp : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
5450 if (X86::isUNPCKHMask(NewSVOp))
5452 NewOp : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
5455 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
5457 // Normalize the node to match x86 shuffle ops if needed
5458 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
5459 return CommuteVectorShuffle(SVOp, DAG);
5461 // The checks below are all present in isShuffleMaskLegal, but they are
5462 // inlined here right now to enable us to directly emit target specific
5463 // nodes, and remove one by one until they don't return Op anymore.
5464 SmallVector<int, 16> M;
5467 // Very little shuffling can be done for 64-bit vectors right now.
5468 if (VT.getSizeInBits() == 64)
5469 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ? Op : SDValue();
5471 // FIXME: pshufb, blends, shifts.
5472 if (VT.getVectorNumElements() == 2 ||
5473 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5474 isMOVLMask(M, VT) ||
5475 isSHUFPMask(M, VT) ||
5476 isPSHUFDMask(M, VT) ||
5477 isPSHUFHWMask(M, VT) ||
5478 isPSHUFLWMask(M, VT) ||
5479 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()))
5482 if (X86::isUNPCKL_v_undef_Mask(SVOp))
5483 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5484 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5485 if (X86::isUNPCKH_v_undef_Mask(SVOp))
5486 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5487 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5489 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
5490 if (VT == MVT::v8i16) {
5491 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
5492 if (NewOp.getNode())
5496 if (VT == MVT::v16i8) {
5497 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
5498 if (NewOp.getNode())
5502 // Handle all 4 wide cases with a number of shuffles except for MMX.
5503 if (NumElems == 4 && !isMMX)
5504 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
5510 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
5511 SelectionDAG &DAG) const {
5512 EVT VT = Op.getValueType();
5513 DebugLoc dl = Op.getDebugLoc();
5514 if (VT.getSizeInBits() == 8) {
5515 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
5516 Op.getOperand(0), Op.getOperand(1));
5517 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5518 DAG.getValueType(VT));
5519 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5520 } else if (VT.getSizeInBits() == 16) {
5521 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5522 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
5524 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5525 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5526 DAG.getNode(ISD::BIT_CONVERT, dl,
5530 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
5531 Op.getOperand(0), Op.getOperand(1));
5532 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5533 DAG.getValueType(VT));
5534 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5535 } else if (VT == MVT::f32) {
5536 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
5537 // the result back to FR32 register. It's only worth matching if the
5538 // result has a single use which is a store or a bitcast to i32. And in
5539 // the case of a store, it's not worth it if the index is a constant 0,
5540 // because a MOVSSmr can be used instead, which is smaller and faster.
5541 if (!Op.hasOneUse())
5543 SDNode *User = *Op.getNode()->use_begin();
5544 if ((User->getOpcode() != ISD::STORE ||
5545 (isa<ConstantSDNode>(Op.getOperand(1)) &&
5546 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
5547 (User->getOpcode() != ISD::BIT_CONVERT ||
5548 User->getValueType(0) != MVT::i32))
5550 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5551 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
5554 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
5555 } else if (VT == MVT::i32) {
5556 // ExtractPS works with constant index.
5557 if (isa<ConstantSDNode>(Op.getOperand(1)))
5565 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5566 SelectionDAG &DAG) const {
5567 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5570 if (Subtarget->hasSSE41()) {
5571 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
5576 EVT VT = Op.getValueType();
5577 DebugLoc dl = Op.getDebugLoc();
5578 // TODO: handle v16i8.
5579 if (VT.getSizeInBits() == 16) {
5580 SDValue Vec = Op.getOperand(0);
5581 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5583 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5584 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5585 DAG.getNode(ISD::BIT_CONVERT, dl,
5588 // Transform it so it match pextrw which produces a 32-bit result.
5589 EVT EltVT = MVT::i32;
5590 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
5591 Op.getOperand(0), Op.getOperand(1));
5592 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
5593 DAG.getValueType(VT));
5594 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5595 } else if (VT.getSizeInBits() == 32) {
5596 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5600 // SHUFPS the element to the lowest double word, then movss.
5601 int Mask[4] = { Idx, -1, -1, -1 };
5602 EVT VVT = Op.getOperand(0).getValueType();
5603 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5604 DAG.getUNDEF(VVT), Mask);
5605 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5606 DAG.getIntPtrConstant(0));
5607 } else if (VT.getSizeInBits() == 64) {
5608 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
5609 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
5610 // to match extract_elt for f64.
5611 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5615 // UNPCKHPD the element to the lowest double word, then movsd.
5616 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
5617 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
5618 int Mask[2] = { 1, -1 };
5619 EVT VVT = Op.getOperand(0).getValueType();
5620 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5621 DAG.getUNDEF(VVT), Mask);
5622 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5623 DAG.getIntPtrConstant(0));
5630 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5631 SelectionDAG &DAG) const {
5632 EVT VT = Op.getValueType();
5633 EVT EltVT = VT.getVectorElementType();
5634 DebugLoc dl = Op.getDebugLoc();
5636 SDValue N0 = Op.getOperand(0);
5637 SDValue N1 = Op.getOperand(1);
5638 SDValue N2 = Op.getOperand(2);
5640 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5641 isa<ConstantSDNode>(N2)) {
5643 if (VT == MVT::v8i16)
5644 Opc = X86ISD::PINSRW;
5645 else if (VT == MVT::v4i16)
5646 Opc = X86ISD::MMX_PINSRW;
5647 else if (VT == MVT::v16i8)
5648 Opc = X86ISD::PINSRB;
5650 Opc = X86ISD::PINSRB;
5652 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5654 if (N1.getValueType() != MVT::i32)
5655 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5656 if (N2.getValueType() != MVT::i32)
5657 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5658 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5659 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5660 // Bits [7:6] of the constant are the source select. This will always be
5661 // zero here. The DAG Combiner may combine an extract_elt index into these
5662 // bits. For example (insert (extract, 3), 2) could be matched by putting
5663 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5664 // Bits [5:4] of the constant are the destination select. This is the
5665 // value of the incoming immediate.
5666 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5667 // combine either bitwise AND or insert of float 0.0 to set these bits.
5668 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5669 // Create this as a scalar to vector..
5670 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5671 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5672 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5673 // PINSR* works with constant index.
5680 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5681 EVT VT = Op.getValueType();
5682 EVT EltVT = VT.getVectorElementType();
5684 if (Subtarget->hasSSE41())
5685 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5687 if (EltVT == MVT::i8)
5690 DebugLoc dl = Op.getDebugLoc();
5691 SDValue N0 = Op.getOperand(0);
5692 SDValue N1 = Op.getOperand(1);
5693 SDValue N2 = Op.getOperand(2);
5695 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5696 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5697 // as its second argument.
5698 if (N1.getValueType() != MVT::i32)
5699 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5700 if (N2.getValueType() != MVT::i32)
5701 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5702 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW,
5703 dl, VT, N0, N1, N2);
5709 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5710 DebugLoc dl = Op.getDebugLoc();
5712 if (Op.getValueType() == MVT::v1i64 &&
5713 Op.getOperand(0).getValueType() == MVT::i64)
5714 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5716 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5717 EVT VT = MVT::v2i32;
5718 switch (Op.getValueType().getSimpleVT().SimpleTy) {
5725 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
5726 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
5729 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5730 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5731 // one of the above mentioned nodes. It has to be wrapped because otherwise
5732 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5733 // be used to form addressing mode. These wrapped nodes will be selected
5736 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5737 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5739 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5741 unsigned char OpFlag = 0;
5742 unsigned WrapperKind = X86ISD::Wrapper;
5743 CodeModel::Model M = getTargetMachine().getCodeModel();
5745 if (Subtarget->isPICStyleRIPRel() &&
5746 (M == CodeModel::Small || M == CodeModel::Kernel))
5747 WrapperKind = X86ISD::WrapperRIP;
5748 else if (Subtarget->isPICStyleGOT())
5749 OpFlag = X86II::MO_GOTOFF;
5750 else if (Subtarget->isPICStyleStubPIC())
5751 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5753 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5755 CP->getOffset(), OpFlag);
5756 DebugLoc DL = CP->getDebugLoc();
5757 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5758 // With PIC, the address is actually $g + Offset.
5760 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5761 DAG.getNode(X86ISD::GlobalBaseReg,
5762 DebugLoc(), getPointerTy()),
5769 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5770 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5772 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5774 unsigned char OpFlag = 0;
5775 unsigned WrapperKind = X86ISD::Wrapper;
5776 CodeModel::Model M = getTargetMachine().getCodeModel();
5778 if (Subtarget->isPICStyleRIPRel() &&
5779 (M == CodeModel::Small || M == CodeModel::Kernel))
5780 WrapperKind = X86ISD::WrapperRIP;
5781 else if (Subtarget->isPICStyleGOT())
5782 OpFlag = X86II::MO_GOTOFF;
5783 else if (Subtarget->isPICStyleStubPIC())
5784 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5786 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5788 DebugLoc DL = JT->getDebugLoc();
5789 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5791 // With PIC, the address is actually $g + Offset.
5793 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5794 DAG.getNode(X86ISD::GlobalBaseReg,
5795 DebugLoc(), getPointerTy()),
5803 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5804 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5806 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5808 unsigned char OpFlag = 0;
5809 unsigned WrapperKind = X86ISD::Wrapper;
5810 CodeModel::Model M = getTargetMachine().getCodeModel();
5812 if (Subtarget->isPICStyleRIPRel() &&
5813 (M == CodeModel::Small || M == CodeModel::Kernel))
5814 WrapperKind = X86ISD::WrapperRIP;
5815 else if (Subtarget->isPICStyleGOT())
5816 OpFlag = X86II::MO_GOTOFF;
5817 else if (Subtarget->isPICStyleStubPIC())
5818 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5820 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5822 DebugLoc DL = Op.getDebugLoc();
5823 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5826 // With PIC, the address is actually $g + Offset.
5827 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5828 !Subtarget->is64Bit()) {
5829 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5830 DAG.getNode(X86ISD::GlobalBaseReg,
5831 DebugLoc(), getPointerTy()),
5839 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5840 // Create the TargetBlockAddressAddress node.
5841 unsigned char OpFlags =
5842 Subtarget->ClassifyBlockAddressReference();
5843 CodeModel::Model M = getTargetMachine().getCodeModel();
5844 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5845 DebugLoc dl = Op.getDebugLoc();
5846 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5847 /*isTarget=*/true, OpFlags);
5849 if (Subtarget->isPICStyleRIPRel() &&
5850 (M == CodeModel::Small || M == CodeModel::Kernel))
5851 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5853 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5855 // With PIC, the address is actually $g + Offset.
5856 if (isGlobalRelativeToPICBase(OpFlags)) {
5857 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5858 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5866 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5868 SelectionDAG &DAG) const {
5869 // Create the TargetGlobalAddress node, folding in the constant
5870 // offset if it is legal.
5871 unsigned char OpFlags =
5872 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5873 CodeModel::Model M = getTargetMachine().getCodeModel();
5875 if (OpFlags == X86II::MO_NO_FLAG &&
5876 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5877 // A direct static reference to a global.
5878 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
5881 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
5884 if (Subtarget->isPICStyleRIPRel() &&
5885 (M == CodeModel::Small || M == CodeModel::Kernel))
5886 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5888 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5890 // With PIC, the address is actually $g + Offset.
5891 if (isGlobalRelativeToPICBase(OpFlags)) {
5892 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5893 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5897 // For globals that require a load from a stub to get the address, emit the
5899 if (isGlobalStubReference(OpFlags))
5900 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5901 PseudoSourceValue::getGOT(), 0, false, false, 0);
5903 // If there was a non-zero offset that we didn't fold, create an explicit
5906 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5907 DAG.getConstant(Offset, getPointerTy()));
5913 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
5914 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5915 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5916 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5920 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5921 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5922 unsigned char OperandFlags) {
5923 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5924 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5925 DebugLoc dl = GA->getDebugLoc();
5926 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
5927 GA->getValueType(0),
5931 SDValue Ops[] = { Chain, TGA, *InFlag };
5932 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5934 SDValue Ops[] = { Chain, TGA };
5935 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5938 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5939 MFI->setAdjustsStack(true);
5941 SDValue Flag = Chain.getValue(1);
5942 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5945 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5947 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5950 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5951 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5952 DAG.getNode(X86ISD::GlobalBaseReg,
5953 DebugLoc(), PtrVT), InFlag);
5954 InFlag = Chain.getValue(1);
5956 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5959 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5961 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5963 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5964 X86::RAX, X86II::MO_TLSGD);
5967 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5968 // "local exec" model.
5969 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5970 const EVT PtrVT, TLSModel::Model model,
5972 DebugLoc dl = GA->getDebugLoc();
5973 // Get the Thread Pointer
5974 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5976 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5979 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5980 NULL, 0, false, false, 0);
5982 unsigned char OperandFlags = 0;
5983 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5985 unsigned WrapperKind = X86ISD::Wrapper;
5986 if (model == TLSModel::LocalExec) {
5987 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5988 } else if (is64Bit) {
5989 assert(model == TLSModel::InitialExec);
5990 OperandFlags = X86II::MO_GOTTPOFF;
5991 WrapperKind = X86ISD::WrapperRIP;
5993 assert(model == TLSModel::InitialExec);
5994 OperandFlags = X86II::MO_INDNTPOFF;
5997 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5999 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6000 GA->getValueType(0),
6001 GA->getOffset(), OperandFlags);
6002 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
6004 if (model == TLSModel::InitialExec)
6005 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
6006 PseudoSourceValue::getGOT(), 0, false, false, 0);
6008 // The address of the thread local variable is the add of the thread
6009 // pointer with the offset of the variable.
6010 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
6014 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
6016 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6017 const GlobalValue *GV = GA->getGlobal();
6019 if (Subtarget->isTargetELF()) {
6020 // TODO: implement the "local dynamic" model
6021 // TODO: implement the "initial exec"model for pic executables
6023 // If GV is an alias then use the aliasee for determining
6024 // thread-localness.
6025 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
6026 GV = GA->resolveAliasedGlobal(false);
6028 TLSModel::Model model
6029 = getTLSModel(GV, getTargetMachine().getRelocationModel());
6032 case TLSModel::GeneralDynamic:
6033 case TLSModel::LocalDynamic: // not implemented
6034 if (Subtarget->is64Bit())
6035 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
6036 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
6038 case TLSModel::InitialExec:
6039 case TLSModel::LocalExec:
6040 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
6041 Subtarget->is64Bit());
6043 } else if (Subtarget->isTargetDarwin()) {
6044 // Darwin only has one model of TLS. Lower to that.
6045 unsigned char OpFlag = 0;
6046 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
6047 X86ISD::WrapperRIP : X86ISD::Wrapper;
6049 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6051 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
6052 !Subtarget->is64Bit();
6054 OpFlag = X86II::MO_TLVP_PIC_BASE;
6056 OpFlag = X86II::MO_TLVP;
6057 DebugLoc DL = Op.getDebugLoc();
6058 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
6060 GA->getOffset(), OpFlag);
6061 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6063 // With PIC32, the address is actually $g + Offset.
6065 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6066 DAG.getNode(X86ISD::GlobalBaseReg,
6067 DebugLoc(), getPointerTy()),
6070 // Lowering the machine isd will make sure everything is in the right
6072 SDValue Args[] = { Offset };
6073 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
6075 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
6076 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6077 MFI->setAdjustsStack(true);
6079 // And our return value (tls address) is in the standard call return value
6081 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
6082 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
6086 "TLS not implemented for this target.");
6088 llvm_unreachable("Unreachable");
6093 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
6094 /// take a 2 x i32 value to shift plus a shift amount.
6095 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
6096 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
6097 EVT VT = Op.getValueType();
6098 unsigned VTBits = VT.getSizeInBits();
6099 DebugLoc dl = Op.getDebugLoc();
6100 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
6101 SDValue ShOpLo = Op.getOperand(0);
6102 SDValue ShOpHi = Op.getOperand(1);
6103 SDValue ShAmt = Op.getOperand(2);
6104 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
6105 DAG.getConstant(VTBits - 1, MVT::i8))
6106 : DAG.getConstant(0, VT);
6109 if (Op.getOpcode() == ISD::SHL_PARTS) {
6110 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
6111 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6113 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
6114 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
6117 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
6118 DAG.getConstant(VTBits, MVT::i8));
6119 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6120 AndNode, DAG.getConstant(0, MVT::i8));
6123 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6124 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
6125 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
6127 if (Op.getOpcode() == ISD::SHL_PARTS) {
6128 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6129 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6131 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6132 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6135 SDValue Ops[2] = { Lo, Hi };
6136 return DAG.getMergeValues(Ops, 2, dl);
6139 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
6140 SelectionDAG &DAG) const {
6141 EVT SrcVT = Op.getOperand(0).getValueType();
6143 if (SrcVT.isVector()) {
6144 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
6150 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
6151 "Unknown SINT_TO_FP to lower!");
6153 // These are really Legal; return the operand so the caller accepts it as
6155 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
6157 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
6158 Subtarget->is64Bit()) {
6162 DebugLoc dl = Op.getDebugLoc();
6163 unsigned Size = SrcVT.getSizeInBits()/8;
6164 MachineFunction &MF = DAG.getMachineFunction();
6165 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
6166 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6167 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6169 PseudoSourceValue::getFixedStack(SSFI), 0,
6171 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
6174 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
6176 SelectionDAG &DAG) const {
6178 DebugLoc dl = Op.getDebugLoc();
6180 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
6182 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
6184 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
6185 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
6186 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
6187 Tys, Ops, array_lengthof(Ops));
6190 Chain = Result.getValue(1);
6191 SDValue InFlag = Result.getValue(2);
6193 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
6194 // shouldn't be necessary except that RFP cannot be live across
6195 // multiple blocks. When stackifier is fixed, they can be uncoupled.
6196 MachineFunction &MF = DAG.getMachineFunction();
6197 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6198 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6199 Tys = DAG.getVTList(MVT::Other);
6201 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
6203 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
6204 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
6205 PseudoSourceValue::getFixedStack(SSFI), 0,
6212 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
6213 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
6214 SelectionDAG &DAG) const {
6215 // This algorithm is not obvious. Here it is in C code, more or less:
6217 double uint64_to_double( uint32_t hi, uint32_t lo ) {
6218 static const __m128i exp = { 0x4330000045300000ULL, 0 };
6219 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
6221 // Copy ints to xmm registers.
6222 __m128i xh = _mm_cvtsi32_si128( hi );
6223 __m128i xl = _mm_cvtsi32_si128( lo );
6225 // Combine into low half of a single xmm register.
6226 __m128i x = _mm_unpacklo_epi32( xh, xl );
6230 // Merge in appropriate exponents to give the integer bits the right
6232 x = _mm_unpacklo_epi32( x, exp );
6234 // Subtract away the biases to deal with the IEEE-754 double precision
6236 d = _mm_sub_pd( (__m128d) x, bias );
6238 // All conversions up to here are exact. The correctly rounded result is
6239 // calculated using the current rounding mode using the following
6241 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
6242 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
6243 // store doesn't really need to be here (except
6244 // maybe to zero the other double)
6249 DebugLoc dl = Op.getDebugLoc();
6250 LLVMContext *Context = DAG.getContext();
6252 // Build some magic constants.
6253 std::vector<Constant*> CV0;
6254 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
6255 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
6256 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6257 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6258 Constant *C0 = ConstantVector::get(CV0);
6259 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
6261 std::vector<Constant*> CV1;
6263 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
6265 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
6266 Constant *C1 = ConstantVector::get(CV1);
6267 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
6269 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6270 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6272 DAG.getIntPtrConstant(1)));
6273 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6274 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6276 DAG.getIntPtrConstant(0)));
6277 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
6278 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
6279 PseudoSourceValue::getConstantPool(), 0,
6281 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
6282 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
6283 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
6284 PseudoSourceValue::getConstantPool(), 0,
6286 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
6288 // Add the halves; easiest way is to swap them into another reg first.
6289 int ShufMask[2] = { 1, -1 };
6290 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
6291 DAG.getUNDEF(MVT::v2f64), ShufMask);
6292 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
6293 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
6294 DAG.getIntPtrConstant(0));
6297 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
6298 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
6299 SelectionDAG &DAG) const {
6300 DebugLoc dl = Op.getDebugLoc();
6301 // FP constant to bias correct the final result.
6302 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
6305 // Load the 32-bit value into an XMM register.
6306 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6307 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6309 DAG.getIntPtrConstant(0)));
6311 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6312 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
6313 DAG.getIntPtrConstant(0));
6315 // Or the load with the bias.
6316 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
6317 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6318 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6320 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6321 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6322 MVT::v2f64, Bias)));
6323 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6324 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
6325 DAG.getIntPtrConstant(0));
6327 // Subtract the bias.
6328 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
6330 // Handle final rounding.
6331 EVT DestVT = Op.getValueType();
6333 if (DestVT.bitsLT(MVT::f64)) {
6334 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6335 DAG.getIntPtrConstant(0));
6336 } else if (DestVT.bitsGT(MVT::f64)) {
6337 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6340 // Handle final rounding.
6344 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
6345 SelectionDAG &DAG) const {
6346 SDValue N0 = Op.getOperand(0);
6347 DebugLoc dl = Op.getDebugLoc();
6349 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
6350 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
6351 // the optimization here.
6352 if (DAG.SignBitIsZero(N0))
6353 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
6355 EVT SrcVT = N0.getValueType();
6356 EVT DstVT = Op.getValueType();
6357 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
6358 return LowerUINT_TO_FP_i64(Op, DAG);
6359 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
6360 return LowerUINT_TO_FP_i32(Op, DAG);
6362 // Make a 64-bit buffer, and use it to build an FILD.
6363 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
6364 if (SrcVT == MVT::i32) {
6365 SDValue WordOff = DAG.getConstant(4, getPointerTy());
6366 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
6367 getPointerTy(), StackSlot, WordOff);
6368 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6369 StackSlot, NULL, 0, false, false, 0);
6370 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
6371 OffsetSlot, NULL, 0, false, false, 0);
6372 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
6376 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
6377 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6378 StackSlot, NULL, 0, false, false, 0);
6379 // For i64 source, we need to add the appropriate power of 2 if the input
6380 // was negative. This is the same as the optimization in
6381 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
6382 // we must be careful to do the computation in x87 extended precision, not
6383 // in SSE. (The generic code can't know it's OK to do this, or how to.)
6384 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
6385 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
6386 SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3);
6388 APInt FF(32, 0x5F800000ULL);
6390 // Check whether the sign bit is set.
6391 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
6392 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
6395 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
6396 SDValue FudgePtr = DAG.getConstantPool(
6397 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
6400 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
6401 SDValue Zero = DAG.getIntPtrConstant(0);
6402 SDValue Four = DAG.getIntPtrConstant(4);
6403 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
6405 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
6407 // Load the value out, extending it from f32 to f80.
6408 // FIXME: Avoid the extend by constructing the right constant pool?
6409 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
6410 FudgePtr, PseudoSourceValue::getConstantPool(),
6411 0, MVT::f32, false, false, 4);
6412 // Extend everything to 80 bits to force it to be done on x87.
6413 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
6414 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
6417 std::pair<SDValue,SDValue> X86TargetLowering::
6418 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
6419 DebugLoc dl = Op.getDebugLoc();
6421 EVT DstTy = Op.getValueType();
6424 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
6428 assert(DstTy.getSimpleVT() <= MVT::i64 &&
6429 DstTy.getSimpleVT() >= MVT::i16 &&
6430 "Unknown FP_TO_SINT to lower!");
6432 // These are really Legal.
6433 if (DstTy == MVT::i32 &&
6434 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6435 return std::make_pair(SDValue(), SDValue());
6436 if (Subtarget->is64Bit() &&
6437 DstTy == MVT::i64 &&
6438 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6439 return std::make_pair(SDValue(), SDValue());
6441 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
6443 MachineFunction &MF = DAG.getMachineFunction();
6444 unsigned MemSize = DstTy.getSizeInBits()/8;
6445 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6446 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6449 switch (DstTy.getSimpleVT().SimpleTy) {
6450 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
6451 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
6452 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
6453 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
6456 SDValue Chain = DAG.getEntryNode();
6457 SDValue Value = Op.getOperand(0);
6458 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
6459 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
6460 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
6461 PseudoSourceValue::getFixedStack(SSFI), 0,
6463 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
6465 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
6467 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
6468 Chain = Value.getValue(1);
6469 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6470 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6473 // Build the FP_TO_INT*_IN_MEM
6474 SDValue Ops[] = { Chain, Value, StackSlot };
6475 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
6477 return std::make_pair(FIST, StackSlot);
6480 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
6481 SelectionDAG &DAG) const {
6482 if (Op.getValueType().isVector()) {
6483 if (Op.getValueType() == MVT::v2i32 &&
6484 Op.getOperand(0).getValueType() == MVT::v2f64) {
6490 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
6491 SDValue FIST = Vals.first, StackSlot = Vals.second;
6492 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
6493 if (FIST.getNode() == 0) return Op;
6496 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6497 FIST, StackSlot, NULL, 0, false, false, 0);
6500 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
6501 SelectionDAG &DAG) const {
6502 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
6503 SDValue FIST = Vals.first, StackSlot = Vals.second;
6504 assert(FIST.getNode() && "Unexpected failure");
6507 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6508 FIST, StackSlot, NULL, 0, false, false, 0);
6511 SDValue X86TargetLowering::LowerFABS(SDValue Op,
6512 SelectionDAG &DAG) const {
6513 LLVMContext *Context = DAG.getContext();
6514 DebugLoc dl = Op.getDebugLoc();
6515 EVT VT = Op.getValueType();
6518 EltVT = VT.getVectorElementType();
6519 std::vector<Constant*> CV;
6520 if (EltVT == MVT::f64) {
6521 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
6525 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
6531 Constant *C = ConstantVector::get(CV);
6532 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6533 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6534 PseudoSourceValue::getConstantPool(), 0,
6536 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
6539 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
6540 LLVMContext *Context = DAG.getContext();
6541 DebugLoc dl = Op.getDebugLoc();
6542 EVT VT = Op.getValueType();
6545 EltVT = VT.getVectorElementType();
6546 std::vector<Constant*> CV;
6547 if (EltVT == MVT::f64) {
6548 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
6552 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
6558 Constant *C = ConstantVector::get(CV);
6559 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6560 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6561 PseudoSourceValue::getConstantPool(), 0,
6563 if (VT.isVector()) {
6564 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6565 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
6566 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6568 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
6570 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
6574 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
6575 LLVMContext *Context = DAG.getContext();
6576 SDValue Op0 = Op.getOperand(0);
6577 SDValue Op1 = Op.getOperand(1);
6578 DebugLoc dl = Op.getDebugLoc();
6579 EVT VT = Op.getValueType();
6580 EVT SrcVT = Op1.getValueType();
6582 // If second operand is smaller, extend it first.
6583 if (SrcVT.bitsLT(VT)) {
6584 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
6587 // And if it is bigger, shrink it first.
6588 if (SrcVT.bitsGT(VT)) {
6589 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
6593 // At this point the operands and the result should have the same
6594 // type, and that won't be f80 since that is not custom lowered.
6596 // First get the sign bit of second operand.
6597 std::vector<Constant*> CV;
6598 if (SrcVT == MVT::f64) {
6599 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
6600 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6602 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
6603 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6604 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6605 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6607 Constant *C = ConstantVector::get(CV);
6608 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6609 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
6610 PseudoSourceValue::getConstantPool(), 0,
6612 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
6614 // Shift sign bit right or left if the two operands have different types.
6615 if (SrcVT.bitsGT(VT)) {
6616 // Op0 is MVT::f32, Op1 is MVT::f64.
6617 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
6618 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
6619 DAG.getConstant(32, MVT::i32));
6620 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
6621 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
6622 DAG.getIntPtrConstant(0));
6625 // Clear first operand sign bit.
6627 if (VT == MVT::f64) {
6628 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6629 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6631 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6632 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6633 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6634 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6636 C = ConstantVector::get(CV);
6637 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6638 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6639 PseudoSourceValue::getConstantPool(), 0,
6641 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6643 // Or the value with the sign bit.
6644 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6647 /// Emit nodes that will be selected as "test Op0,Op0", or something
6649 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6650 SelectionDAG &DAG) const {
6651 DebugLoc dl = Op.getDebugLoc();
6653 // CF and OF aren't always set the way we want. Determine which
6654 // of these we need.
6655 bool NeedCF = false;
6656 bool NeedOF = false;
6659 case X86::COND_A: case X86::COND_AE:
6660 case X86::COND_B: case X86::COND_BE:
6663 case X86::COND_G: case X86::COND_GE:
6664 case X86::COND_L: case X86::COND_LE:
6665 case X86::COND_O: case X86::COND_NO:
6670 // See if we can use the EFLAGS value from the operand instead of
6671 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6672 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6673 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6674 // Emit a CMP with 0, which is the TEST pattern.
6675 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6676 DAG.getConstant(0, Op.getValueType()));
6678 unsigned Opcode = 0;
6679 unsigned NumOperands = 0;
6680 switch (Op.getNode()->getOpcode()) {
6682 // Due to an isel shortcoming, be conservative if this add is likely to be
6683 // selected as part of a load-modify-store instruction. When the root node
6684 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6685 // uses of other nodes in the match, such as the ADD in this case. This
6686 // leads to the ADD being left around and reselected, with the result being
6687 // two adds in the output. Alas, even if none our users are stores, that
6688 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6689 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6690 // climbing the DAG back to the root, and it doesn't seem to be worth the
6692 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6693 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6694 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6697 if (ConstantSDNode *C =
6698 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6699 // An add of one will be selected as an INC.
6700 if (C->getAPIntValue() == 1) {
6701 Opcode = X86ISD::INC;
6706 // An add of negative one (subtract of one) will be selected as a DEC.
6707 if (C->getAPIntValue().isAllOnesValue()) {
6708 Opcode = X86ISD::DEC;
6714 // Otherwise use a regular EFLAGS-setting add.
6715 Opcode = X86ISD::ADD;
6719 // If the primary and result isn't used, don't bother using X86ISD::AND,
6720 // because a TEST instruction will be better.
6721 bool NonFlagUse = false;
6722 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6723 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6725 unsigned UOpNo = UI.getOperandNo();
6726 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6727 // Look pass truncate.
6728 UOpNo = User->use_begin().getOperandNo();
6729 User = *User->use_begin();
6732 if (User->getOpcode() != ISD::BRCOND &&
6733 User->getOpcode() != ISD::SETCC &&
6734 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6747 // Due to the ISEL shortcoming noted above, be conservative if this op is
6748 // likely to be selected as part of a load-modify-store instruction.
6749 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6750 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6751 if (UI->getOpcode() == ISD::STORE)
6754 // Otherwise use a regular EFLAGS-setting instruction.
6755 switch (Op.getNode()->getOpcode()) {
6756 default: llvm_unreachable("unexpected operator!");
6757 case ISD::SUB: Opcode = X86ISD::SUB; break;
6758 case ISD::OR: Opcode = X86ISD::OR; break;
6759 case ISD::XOR: Opcode = X86ISD::XOR; break;
6760 case ISD::AND: Opcode = X86ISD::AND; break;
6772 return SDValue(Op.getNode(), 1);
6779 // Emit a CMP with 0, which is the TEST pattern.
6780 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6781 DAG.getConstant(0, Op.getValueType()));
6783 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6784 SmallVector<SDValue, 4> Ops;
6785 for (unsigned i = 0; i != NumOperands; ++i)
6786 Ops.push_back(Op.getOperand(i));
6788 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6789 DAG.ReplaceAllUsesWith(Op, New);
6790 return SDValue(New.getNode(), 1);
6793 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6795 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6796 SelectionDAG &DAG) const {
6797 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6798 if (C->getAPIntValue() == 0)
6799 return EmitTest(Op0, X86CC, DAG);
6801 DebugLoc dl = Op0.getDebugLoc();
6802 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6805 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6806 /// if it's possible.
6807 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6808 DebugLoc dl, SelectionDAG &DAG) const {
6809 SDValue Op0 = And.getOperand(0);
6810 SDValue Op1 = And.getOperand(1);
6811 if (Op0.getOpcode() == ISD::TRUNCATE)
6812 Op0 = Op0.getOperand(0);
6813 if (Op1.getOpcode() == ISD::TRUNCATE)
6814 Op1 = Op1.getOperand(0);
6817 if (Op1.getOpcode() == ISD::SHL)
6818 std::swap(Op0, Op1);
6819 if (Op0.getOpcode() == ISD::SHL) {
6820 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6821 if (And00C->getZExtValue() == 1) {
6822 // If we looked past a truncate, check that it's only truncating away
6824 unsigned BitWidth = Op0.getValueSizeInBits();
6825 unsigned AndBitWidth = And.getValueSizeInBits();
6826 if (BitWidth > AndBitWidth) {
6827 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6828 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6829 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6833 RHS = Op0.getOperand(1);
6835 } else if (Op1.getOpcode() == ISD::Constant) {
6836 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6837 SDValue AndLHS = Op0;
6838 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6839 LHS = AndLHS.getOperand(0);
6840 RHS = AndLHS.getOperand(1);
6844 if (LHS.getNode()) {
6845 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
6846 // instruction. Since the shift amount is in-range-or-undefined, we know
6847 // that doing a bittest on the i32 value is ok. We extend to i32 because
6848 // the encoding for the i16 version is larger than the i32 version.
6849 // Also promote i16 to i32 for performance / code size reason.
6850 if (LHS.getValueType() == MVT::i8 ||
6851 LHS.getValueType() == MVT::i16)
6852 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
6854 // If the operand types disagree, extend the shift amount to match. Since
6855 // BT ignores high bits (like shifts) we can use anyextend.
6856 if (LHS.getValueType() != RHS.getValueType())
6857 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
6859 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
6860 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
6861 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6862 DAG.getConstant(Cond, MVT::i8), BT);
6868 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
6869 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
6870 SDValue Op0 = Op.getOperand(0);
6871 SDValue Op1 = Op.getOperand(1);
6872 DebugLoc dl = Op.getDebugLoc();
6873 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6875 // Optimize to BT if possible.
6876 // Lower (X & (1 << N)) == 0 to BT(X, N).
6877 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
6878 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
6879 if (Op0.getOpcode() == ISD::AND &&
6881 Op1.getOpcode() == ISD::Constant &&
6882 cast<ConstantSDNode>(Op1)->isNullValue() &&
6883 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6884 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
6885 if (NewSetCC.getNode())
6889 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
6890 if (Op0.getOpcode() == X86ISD::SETCC &&
6891 Op1.getOpcode() == ISD::Constant &&
6892 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
6893 cast<ConstantSDNode>(Op1)->isNullValue()) &&
6894 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6895 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
6896 bool Invert = (CC == ISD::SETNE) ^
6897 cast<ConstantSDNode>(Op1)->isNullValue();
6899 CCode = X86::GetOppositeBranchCondition(CCode);
6900 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6901 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
6904 bool isFP = Op1.getValueType().isFloatingPoint();
6905 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
6906 if (X86CC == X86::COND_INVALID)
6909 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
6911 // Use sbb x, x to materialize carry bit into a GPR.
6912 if (X86CC == X86::COND_B)
6913 return DAG.getNode(ISD::AND, dl, MVT::i8,
6914 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
6915 DAG.getConstant(X86CC, MVT::i8), Cond),
6916 DAG.getConstant(1, MVT::i8));
6918 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6919 DAG.getConstant(X86CC, MVT::i8), Cond);
6922 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
6924 SDValue Op0 = Op.getOperand(0);
6925 SDValue Op1 = Op.getOperand(1);
6926 SDValue CC = Op.getOperand(2);
6927 EVT VT = Op.getValueType();
6928 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6929 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
6930 DebugLoc dl = Op.getDebugLoc();
6934 EVT VT0 = Op0.getValueType();
6935 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
6936 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
6939 switch (SetCCOpcode) {
6942 case ISD::SETEQ: SSECC = 0; break;
6944 case ISD::SETGT: Swap = true; // Fallthrough
6946 case ISD::SETOLT: SSECC = 1; break;
6948 case ISD::SETGE: Swap = true; // Fallthrough
6950 case ISD::SETOLE: SSECC = 2; break;
6951 case ISD::SETUO: SSECC = 3; break;
6953 case ISD::SETNE: SSECC = 4; break;
6954 case ISD::SETULE: Swap = true;
6955 case ISD::SETUGE: SSECC = 5; break;
6956 case ISD::SETULT: Swap = true;
6957 case ISD::SETUGT: SSECC = 6; break;
6958 case ISD::SETO: SSECC = 7; break;
6961 std::swap(Op0, Op1);
6963 // In the two special cases we can't handle, emit two comparisons.
6965 if (SetCCOpcode == ISD::SETUEQ) {
6967 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
6968 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
6969 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6971 else if (SetCCOpcode == ISD::SETONE) {
6973 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6974 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6975 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6977 llvm_unreachable("Illegal FP comparison");
6979 // Handle all other FP comparisons here.
6980 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6983 // We are handling one of the integer comparisons here. Since SSE only has
6984 // GT and EQ comparisons for integer, swapping operands and multiple
6985 // operations may be required for some comparisons.
6986 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6987 bool Swap = false, Invert = false, FlipSigns = false;
6989 switch (VT.getSimpleVT().SimpleTy) {
6992 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6994 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6996 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6997 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
7000 switch (SetCCOpcode) {
7002 case ISD::SETNE: Invert = true;
7003 case ISD::SETEQ: Opc = EQOpc; break;
7004 case ISD::SETLT: Swap = true;
7005 case ISD::SETGT: Opc = GTOpc; break;
7006 case ISD::SETGE: Swap = true;
7007 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
7008 case ISD::SETULT: Swap = true;
7009 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
7010 case ISD::SETUGE: Swap = true;
7011 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
7014 std::swap(Op0, Op1);
7016 // Since SSE has no unsigned integer comparisons, we need to flip the sign
7017 // bits of the inputs before performing those operations.
7019 EVT EltVT = VT.getVectorElementType();
7020 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
7022 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
7023 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
7025 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
7026 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
7029 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
7031 // If the logical-not of the result is required, perform that now.
7033 Result = DAG.getNOT(dl, Result, VT);
7038 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
7039 static bool isX86LogicalCmp(SDValue Op) {
7040 unsigned Opc = Op.getNode()->getOpcode();
7041 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
7043 if (Op.getResNo() == 1 &&
7044 (Opc == X86ISD::ADD ||
7045 Opc == X86ISD::SUB ||
7046 Opc == X86ISD::SMUL ||
7047 Opc == X86ISD::UMUL ||
7048 Opc == X86ISD::INC ||
7049 Opc == X86ISD::DEC ||
7050 Opc == X86ISD::OR ||
7051 Opc == X86ISD::XOR ||
7052 Opc == X86ISD::AND))
7058 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7059 bool addTest = true;
7060 SDValue Cond = Op.getOperand(0);
7061 DebugLoc dl = Op.getDebugLoc();
7064 if (Cond.getOpcode() == ISD::SETCC) {
7065 SDValue NewCond = LowerSETCC(Cond, DAG);
7066 if (NewCond.getNode())
7070 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
7071 SDValue Op1 = Op.getOperand(1);
7072 SDValue Op2 = Op.getOperand(2);
7073 if (Cond.getOpcode() == X86ISD::SETCC &&
7074 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
7075 SDValue Cmp = Cond.getOperand(1);
7076 if (Cmp.getOpcode() == X86ISD::CMP) {
7077 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
7078 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
7079 ConstantSDNode *RHSC =
7080 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
7081 if (N1C && N1C->isAllOnesValue() &&
7082 N2C && N2C->isNullValue() &&
7083 RHSC && RHSC->isNullValue()) {
7084 SDValue CmpOp0 = Cmp.getOperand(0);
7085 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7086 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
7087 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
7088 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
7093 // Look pass (and (setcc_carry (cmp ...)), 1).
7094 if (Cond.getOpcode() == ISD::AND &&
7095 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7096 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7097 if (C && C->getAPIntValue() == 1)
7098 Cond = Cond.getOperand(0);
7101 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7102 // setting operand in place of the X86ISD::SETCC.
7103 if (Cond.getOpcode() == X86ISD::SETCC ||
7104 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7105 CC = Cond.getOperand(0);
7107 SDValue Cmp = Cond.getOperand(1);
7108 unsigned Opc = Cmp.getOpcode();
7109 EVT VT = Op.getValueType();
7111 bool IllegalFPCMov = false;
7112 if (VT.isFloatingPoint() && !VT.isVector() &&
7113 !isScalarFPTypeInSSEReg(VT)) // FPStack?
7114 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
7116 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
7117 Opc == X86ISD::BT) { // FIXME
7124 // Look pass the truncate.
7125 if (Cond.getOpcode() == ISD::TRUNCATE)
7126 Cond = Cond.getOperand(0);
7128 // We know the result of AND is compared against zero. Try to match
7130 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7131 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7132 if (NewSetCC.getNode()) {
7133 CC = NewSetCC.getOperand(0);
7134 Cond = NewSetCC.getOperand(1);
7141 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7142 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7145 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
7146 // condition is true.
7147 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
7148 SDValue Ops[] = { Op2, Op1, CC, Cond };
7149 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
7152 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
7153 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
7154 // from the AND / OR.
7155 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
7156 Opc = Op.getOpcode();
7157 if (Opc != ISD::OR && Opc != ISD::AND)
7159 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7160 Op.getOperand(0).hasOneUse() &&
7161 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
7162 Op.getOperand(1).hasOneUse());
7165 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
7166 // 1 and that the SETCC node has a single use.
7167 static bool isXor1OfSetCC(SDValue Op) {
7168 if (Op.getOpcode() != ISD::XOR)
7170 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7171 if (N1C && N1C->getAPIntValue() == 1) {
7172 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7173 Op.getOperand(0).hasOneUse();
7178 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
7179 bool addTest = true;
7180 SDValue Chain = Op.getOperand(0);
7181 SDValue Cond = Op.getOperand(1);
7182 SDValue Dest = Op.getOperand(2);
7183 DebugLoc dl = Op.getDebugLoc();
7186 if (Cond.getOpcode() == ISD::SETCC) {
7187 SDValue NewCond = LowerSETCC(Cond, DAG);
7188 if (NewCond.getNode())
7192 // FIXME: LowerXALUO doesn't handle these!!
7193 else if (Cond.getOpcode() == X86ISD::ADD ||
7194 Cond.getOpcode() == X86ISD::SUB ||
7195 Cond.getOpcode() == X86ISD::SMUL ||
7196 Cond.getOpcode() == X86ISD::UMUL)
7197 Cond = LowerXALUO(Cond, DAG);
7200 // Look pass (and (setcc_carry (cmp ...)), 1).
7201 if (Cond.getOpcode() == ISD::AND &&
7202 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7203 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7204 if (C && C->getAPIntValue() == 1)
7205 Cond = Cond.getOperand(0);
7208 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7209 // setting operand in place of the X86ISD::SETCC.
7210 if (Cond.getOpcode() == X86ISD::SETCC ||
7211 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7212 CC = Cond.getOperand(0);
7214 SDValue Cmp = Cond.getOperand(1);
7215 unsigned Opc = Cmp.getOpcode();
7216 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
7217 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
7221 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
7225 // These can only come from an arithmetic instruction with overflow,
7226 // e.g. SADDO, UADDO.
7227 Cond = Cond.getNode()->getOperand(1);
7234 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
7235 SDValue Cmp = Cond.getOperand(0).getOperand(1);
7236 if (CondOpc == ISD::OR) {
7237 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
7238 // two branches instead of an explicit OR instruction with a
7240 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7241 isX86LogicalCmp(Cmp)) {
7242 CC = Cond.getOperand(0).getOperand(0);
7243 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7244 Chain, Dest, CC, Cmp);
7245 CC = Cond.getOperand(1).getOperand(0);
7249 } else { // ISD::AND
7250 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
7251 // two branches instead of an explicit AND instruction with a
7252 // separate test. However, we only do this if this block doesn't
7253 // have a fall-through edge, because this requires an explicit
7254 // jmp when the condition is false.
7255 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7256 isX86LogicalCmp(Cmp) &&
7257 Op.getNode()->hasOneUse()) {
7258 X86::CondCode CCode =
7259 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7260 CCode = X86::GetOppositeBranchCondition(CCode);
7261 CC = DAG.getConstant(CCode, MVT::i8);
7262 SDNode *User = *Op.getNode()->use_begin();
7263 // Look for an unconditional branch following this conditional branch.
7264 // We need this because we need to reverse the successors in order
7265 // to implement FCMP_OEQ.
7266 if (User->getOpcode() == ISD::BR) {
7267 SDValue FalseBB = User->getOperand(1);
7269 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
7270 assert(NewBR == User);
7274 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7275 Chain, Dest, CC, Cmp);
7276 X86::CondCode CCode =
7277 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
7278 CCode = X86::GetOppositeBranchCondition(CCode);
7279 CC = DAG.getConstant(CCode, MVT::i8);
7285 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
7286 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
7287 // It should be transformed during dag combiner except when the condition
7288 // is set by a arithmetics with overflow node.
7289 X86::CondCode CCode =
7290 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7291 CCode = X86::GetOppositeBranchCondition(CCode);
7292 CC = DAG.getConstant(CCode, MVT::i8);
7293 Cond = Cond.getOperand(0).getOperand(1);
7299 // Look pass the truncate.
7300 if (Cond.getOpcode() == ISD::TRUNCATE)
7301 Cond = Cond.getOperand(0);
7303 // We know the result of AND is compared against zero. Try to match
7305 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7306 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7307 if (NewSetCC.getNode()) {
7308 CC = NewSetCC.getOperand(0);
7309 Cond = NewSetCC.getOperand(1);
7316 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7317 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7319 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7320 Chain, Dest, CC, Cond);
7324 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
7325 // Calls to _alloca is needed to probe the stack when allocating more than 4k
7326 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
7327 // that the guard pages used by the OS virtual memory manager are allocated in
7328 // correct sequence.
7330 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
7331 SelectionDAG &DAG) const {
7332 assert(Subtarget->isTargetCygMing() &&
7333 "This should be used only on Cygwin/Mingw targets");
7334 DebugLoc dl = Op.getDebugLoc();
7337 SDValue Chain = Op.getOperand(0);
7338 SDValue Size = Op.getOperand(1);
7339 // FIXME: Ensure alignment here
7343 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
7345 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
7346 Flag = Chain.getValue(1);
7348 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
7350 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
7351 Flag = Chain.getValue(1);
7353 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
7355 SDValue Ops1[2] = { Chain.getValue(0), Chain };
7356 return DAG.getMergeValues(Ops1, 2, dl);
7359 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
7360 MachineFunction &MF = DAG.getMachineFunction();
7361 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
7363 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7364 DebugLoc dl = Op.getDebugLoc();
7366 if (!Subtarget->is64Bit()) {
7367 // vastart just stores the address of the VarArgsFrameIndex slot into the
7368 // memory location argument.
7369 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7371 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
7376 // gp_offset (0 - 6 * 8)
7377 // fp_offset (48 - 48 + 8 * 16)
7378 // overflow_arg_area (point to parameters coming in memory).
7380 SmallVector<SDValue, 8> MemOps;
7381 SDValue FIN = Op.getOperand(1);
7383 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
7384 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
7386 FIN, SV, 0, false, false, 0);
7387 MemOps.push_back(Store);
7390 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7391 FIN, DAG.getIntPtrConstant(4));
7392 Store = DAG.getStore(Op.getOperand(0), dl,
7393 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
7395 FIN, SV, 4, false, false, 0);
7396 MemOps.push_back(Store);
7398 // Store ptr to overflow_arg_area
7399 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7400 FIN, DAG.getIntPtrConstant(4));
7401 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7403 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 8,
7405 MemOps.push_back(Store);
7407 // Store ptr to reg_save_area.
7408 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7409 FIN, DAG.getIntPtrConstant(8));
7410 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
7412 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 16,
7414 MemOps.push_back(Store);
7415 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7416 &MemOps[0], MemOps.size());
7419 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
7420 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7421 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
7423 report_fatal_error("VAArgInst is not yet implemented for x86-64!");
7427 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
7428 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7429 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
7430 SDValue Chain = Op.getOperand(0);
7431 SDValue DstPtr = Op.getOperand(1);
7432 SDValue SrcPtr = Op.getOperand(2);
7433 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
7434 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7435 DebugLoc dl = Op.getDebugLoc();
7437 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
7438 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
7439 false, DstSV, 0, SrcSV, 0);
7443 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
7444 DebugLoc dl = Op.getDebugLoc();
7445 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7447 default: return SDValue(); // Don't custom lower most intrinsics.
7448 // Comparison intrinsics.
7449 case Intrinsic::x86_sse_comieq_ss:
7450 case Intrinsic::x86_sse_comilt_ss:
7451 case Intrinsic::x86_sse_comile_ss:
7452 case Intrinsic::x86_sse_comigt_ss:
7453 case Intrinsic::x86_sse_comige_ss:
7454 case Intrinsic::x86_sse_comineq_ss:
7455 case Intrinsic::x86_sse_ucomieq_ss:
7456 case Intrinsic::x86_sse_ucomilt_ss:
7457 case Intrinsic::x86_sse_ucomile_ss:
7458 case Intrinsic::x86_sse_ucomigt_ss:
7459 case Intrinsic::x86_sse_ucomige_ss:
7460 case Intrinsic::x86_sse_ucomineq_ss:
7461 case Intrinsic::x86_sse2_comieq_sd:
7462 case Intrinsic::x86_sse2_comilt_sd:
7463 case Intrinsic::x86_sse2_comile_sd:
7464 case Intrinsic::x86_sse2_comigt_sd:
7465 case Intrinsic::x86_sse2_comige_sd:
7466 case Intrinsic::x86_sse2_comineq_sd:
7467 case Intrinsic::x86_sse2_ucomieq_sd:
7468 case Intrinsic::x86_sse2_ucomilt_sd:
7469 case Intrinsic::x86_sse2_ucomile_sd:
7470 case Intrinsic::x86_sse2_ucomigt_sd:
7471 case Intrinsic::x86_sse2_ucomige_sd:
7472 case Intrinsic::x86_sse2_ucomineq_sd: {
7474 ISD::CondCode CC = ISD::SETCC_INVALID;
7477 case Intrinsic::x86_sse_comieq_ss:
7478 case Intrinsic::x86_sse2_comieq_sd:
7482 case Intrinsic::x86_sse_comilt_ss:
7483 case Intrinsic::x86_sse2_comilt_sd:
7487 case Intrinsic::x86_sse_comile_ss:
7488 case Intrinsic::x86_sse2_comile_sd:
7492 case Intrinsic::x86_sse_comigt_ss:
7493 case Intrinsic::x86_sse2_comigt_sd:
7497 case Intrinsic::x86_sse_comige_ss:
7498 case Intrinsic::x86_sse2_comige_sd:
7502 case Intrinsic::x86_sse_comineq_ss:
7503 case Intrinsic::x86_sse2_comineq_sd:
7507 case Intrinsic::x86_sse_ucomieq_ss:
7508 case Intrinsic::x86_sse2_ucomieq_sd:
7509 Opc = X86ISD::UCOMI;
7512 case Intrinsic::x86_sse_ucomilt_ss:
7513 case Intrinsic::x86_sse2_ucomilt_sd:
7514 Opc = X86ISD::UCOMI;
7517 case Intrinsic::x86_sse_ucomile_ss:
7518 case Intrinsic::x86_sse2_ucomile_sd:
7519 Opc = X86ISD::UCOMI;
7522 case Intrinsic::x86_sse_ucomigt_ss:
7523 case Intrinsic::x86_sse2_ucomigt_sd:
7524 Opc = X86ISD::UCOMI;
7527 case Intrinsic::x86_sse_ucomige_ss:
7528 case Intrinsic::x86_sse2_ucomige_sd:
7529 Opc = X86ISD::UCOMI;
7532 case Intrinsic::x86_sse_ucomineq_ss:
7533 case Intrinsic::x86_sse2_ucomineq_sd:
7534 Opc = X86ISD::UCOMI;
7539 SDValue LHS = Op.getOperand(1);
7540 SDValue RHS = Op.getOperand(2);
7541 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
7542 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
7543 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
7544 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7545 DAG.getConstant(X86CC, MVT::i8), Cond);
7546 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7548 // ptest and testp intrinsics. The intrinsic these come from are designed to
7549 // return an integer value, not just an instruction so lower it to the ptest
7550 // or testp pattern and a setcc for the result.
7551 case Intrinsic::x86_sse41_ptestz:
7552 case Intrinsic::x86_sse41_ptestc:
7553 case Intrinsic::x86_sse41_ptestnzc:
7554 case Intrinsic::x86_avx_ptestz_256:
7555 case Intrinsic::x86_avx_ptestc_256:
7556 case Intrinsic::x86_avx_ptestnzc_256:
7557 case Intrinsic::x86_avx_vtestz_ps:
7558 case Intrinsic::x86_avx_vtestc_ps:
7559 case Intrinsic::x86_avx_vtestnzc_ps:
7560 case Intrinsic::x86_avx_vtestz_pd:
7561 case Intrinsic::x86_avx_vtestc_pd:
7562 case Intrinsic::x86_avx_vtestnzc_pd:
7563 case Intrinsic::x86_avx_vtestz_ps_256:
7564 case Intrinsic::x86_avx_vtestc_ps_256:
7565 case Intrinsic::x86_avx_vtestnzc_ps_256:
7566 case Intrinsic::x86_avx_vtestz_pd_256:
7567 case Intrinsic::x86_avx_vtestc_pd_256:
7568 case Intrinsic::x86_avx_vtestnzc_pd_256: {
7569 bool IsTestPacked = false;
7572 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
7573 case Intrinsic::x86_avx_vtestz_ps:
7574 case Intrinsic::x86_avx_vtestz_pd:
7575 case Intrinsic::x86_avx_vtestz_ps_256:
7576 case Intrinsic::x86_avx_vtestz_pd_256:
7577 IsTestPacked = true; // Fallthrough
7578 case Intrinsic::x86_sse41_ptestz:
7579 case Intrinsic::x86_avx_ptestz_256:
7581 X86CC = X86::COND_E;
7583 case Intrinsic::x86_avx_vtestc_ps:
7584 case Intrinsic::x86_avx_vtestc_pd:
7585 case Intrinsic::x86_avx_vtestc_ps_256:
7586 case Intrinsic::x86_avx_vtestc_pd_256:
7587 IsTestPacked = true; // Fallthrough
7588 case Intrinsic::x86_sse41_ptestc:
7589 case Intrinsic::x86_avx_ptestc_256:
7591 X86CC = X86::COND_B;
7593 case Intrinsic::x86_avx_vtestnzc_ps:
7594 case Intrinsic::x86_avx_vtestnzc_pd:
7595 case Intrinsic::x86_avx_vtestnzc_ps_256:
7596 case Intrinsic::x86_avx_vtestnzc_pd_256:
7597 IsTestPacked = true; // Fallthrough
7598 case Intrinsic::x86_sse41_ptestnzc:
7599 case Intrinsic::x86_avx_ptestnzc_256:
7601 X86CC = X86::COND_A;
7605 SDValue LHS = Op.getOperand(1);
7606 SDValue RHS = Op.getOperand(2);
7607 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
7608 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
7609 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
7610 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
7611 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7614 // Fix vector shift instructions where the last operand is a non-immediate
7616 case Intrinsic::x86_sse2_pslli_w:
7617 case Intrinsic::x86_sse2_pslli_d:
7618 case Intrinsic::x86_sse2_pslli_q:
7619 case Intrinsic::x86_sse2_psrli_w:
7620 case Intrinsic::x86_sse2_psrli_d:
7621 case Intrinsic::x86_sse2_psrli_q:
7622 case Intrinsic::x86_sse2_psrai_w:
7623 case Intrinsic::x86_sse2_psrai_d:
7624 case Intrinsic::x86_mmx_pslli_w:
7625 case Intrinsic::x86_mmx_pslli_d:
7626 case Intrinsic::x86_mmx_pslli_q:
7627 case Intrinsic::x86_mmx_psrli_w:
7628 case Intrinsic::x86_mmx_psrli_d:
7629 case Intrinsic::x86_mmx_psrli_q:
7630 case Intrinsic::x86_mmx_psrai_w:
7631 case Intrinsic::x86_mmx_psrai_d: {
7632 SDValue ShAmt = Op.getOperand(2);
7633 if (isa<ConstantSDNode>(ShAmt))
7636 unsigned NewIntNo = 0;
7637 EVT ShAmtVT = MVT::v4i32;
7639 case Intrinsic::x86_sse2_pslli_w:
7640 NewIntNo = Intrinsic::x86_sse2_psll_w;
7642 case Intrinsic::x86_sse2_pslli_d:
7643 NewIntNo = Intrinsic::x86_sse2_psll_d;
7645 case Intrinsic::x86_sse2_pslli_q:
7646 NewIntNo = Intrinsic::x86_sse2_psll_q;
7648 case Intrinsic::x86_sse2_psrli_w:
7649 NewIntNo = Intrinsic::x86_sse2_psrl_w;
7651 case Intrinsic::x86_sse2_psrli_d:
7652 NewIntNo = Intrinsic::x86_sse2_psrl_d;
7654 case Intrinsic::x86_sse2_psrli_q:
7655 NewIntNo = Intrinsic::x86_sse2_psrl_q;
7657 case Intrinsic::x86_sse2_psrai_w:
7658 NewIntNo = Intrinsic::x86_sse2_psra_w;
7660 case Intrinsic::x86_sse2_psrai_d:
7661 NewIntNo = Intrinsic::x86_sse2_psra_d;
7664 ShAmtVT = MVT::v2i32;
7666 case Intrinsic::x86_mmx_pslli_w:
7667 NewIntNo = Intrinsic::x86_mmx_psll_w;
7669 case Intrinsic::x86_mmx_pslli_d:
7670 NewIntNo = Intrinsic::x86_mmx_psll_d;
7672 case Intrinsic::x86_mmx_pslli_q:
7673 NewIntNo = Intrinsic::x86_mmx_psll_q;
7675 case Intrinsic::x86_mmx_psrli_w:
7676 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7678 case Intrinsic::x86_mmx_psrli_d:
7679 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7681 case Intrinsic::x86_mmx_psrli_q:
7682 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7684 case Intrinsic::x86_mmx_psrai_w:
7685 NewIntNo = Intrinsic::x86_mmx_psra_w;
7687 case Intrinsic::x86_mmx_psrai_d:
7688 NewIntNo = Intrinsic::x86_mmx_psra_d;
7690 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7696 // The vector shift intrinsics with scalars uses 32b shift amounts but
7697 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7701 ShOps[1] = DAG.getConstant(0, MVT::i32);
7702 if (ShAmtVT == MVT::v4i32) {
7703 ShOps[2] = DAG.getUNDEF(MVT::i32);
7704 ShOps[3] = DAG.getUNDEF(MVT::i32);
7705 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7707 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7710 EVT VT = Op.getValueType();
7711 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
7712 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7713 DAG.getConstant(NewIntNo, MVT::i32),
7714 Op.getOperand(1), ShAmt);
7719 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7720 SelectionDAG &DAG) const {
7721 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7722 MFI->setReturnAddressIsTaken(true);
7724 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7725 DebugLoc dl = Op.getDebugLoc();
7728 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7730 DAG.getConstant(TD->getPointerSize(),
7731 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7732 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7733 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7735 NULL, 0, false, false, 0);
7738 // Just load the return address.
7739 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7740 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7741 RetAddrFI, NULL, 0, false, false, 0);
7744 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7745 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7746 MFI->setFrameAddressIsTaken(true);
7748 EVT VT = Op.getValueType();
7749 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7750 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7751 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7752 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7754 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
7759 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7760 SelectionDAG &DAG) const {
7761 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7764 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
7765 MachineFunction &MF = DAG.getMachineFunction();
7766 SDValue Chain = Op.getOperand(0);
7767 SDValue Offset = Op.getOperand(1);
7768 SDValue Handler = Op.getOperand(2);
7769 DebugLoc dl = Op.getDebugLoc();
7771 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
7772 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7774 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7776 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
7777 DAG.getIntPtrConstant(TD->getPointerSize()));
7778 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7779 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
7780 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7781 MF.getRegInfo().addLiveOut(StoreAddrReg);
7783 return DAG.getNode(X86ISD::EH_RETURN, dl,
7785 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7788 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7789 SelectionDAG &DAG) const {
7790 SDValue Root = Op.getOperand(0);
7791 SDValue Trmp = Op.getOperand(1); // trampoline
7792 SDValue FPtr = Op.getOperand(2); // nested function
7793 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7794 DebugLoc dl = Op.getDebugLoc();
7796 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7798 if (Subtarget->is64Bit()) {
7799 SDValue OutChains[6];
7801 // Large code-model.
7802 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7803 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7805 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7806 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7808 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7810 // Load the pointer to the nested function into R11.
7811 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7812 SDValue Addr = Trmp;
7813 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7814 Addr, TrmpAddr, 0, false, false, 0);
7816 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7817 DAG.getConstant(2, MVT::i64));
7818 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
7821 // Load the 'nest' parameter value into R10.
7822 // R10 is specified in X86CallingConv.td
7823 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7824 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7825 DAG.getConstant(10, MVT::i64));
7826 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7827 Addr, TrmpAddr, 10, false, false, 0);
7829 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7830 DAG.getConstant(12, MVT::i64));
7831 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
7834 // Jump to the nested function.
7835 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7836 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7837 DAG.getConstant(20, MVT::i64));
7838 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7839 Addr, TrmpAddr, 20, false, false, 0);
7841 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7842 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7843 DAG.getConstant(22, MVT::i64));
7844 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7845 TrmpAddr, 22, false, false, 0);
7848 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7849 return DAG.getMergeValues(Ops, 2, dl);
7851 const Function *Func =
7852 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7853 CallingConv::ID CC = Func->getCallingConv();
7858 llvm_unreachable("Unsupported calling convention");
7859 case CallingConv::C:
7860 case CallingConv::X86_StdCall: {
7861 // Pass 'nest' parameter in ECX.
7862 // Must be kept in sync with X86CallingConv.td
7865 // Check that ECX wasn't needed by an 'inreg' parameter.
7866 const FunctionType *FTy = Func->getFunctionType();
7867 const AttrListPtr &Attrs = Func->getAttributes();
7869 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7870 unsigned InRegCount = 0;
7873 for (FunctionType::param_iterator I = FTy->param_begin(),
7874 E = FTy->param_end(); I != E; ++I, ++Idx)
7875 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7876 // FIXME: should only count parameters that are lowered to integers.
7877 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7879 if (InRegCount > 2) {
7880 report_fatal_error("Nest register in use - reduce number of inreg"
7886 case CallingConv::X86_FastCall:
7887 case CallingConv::X86_ThisCall:
7888 case CallingConv::Fast:
7889 // Pass 'nest' parameter in EAX.
7890 // Must be kept in sync with X86CallingConv.td
7895 SDValue OutChains[4];
7898 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7899 DAG.getConstant(10, MVT::i32));
7900 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7902 // This is storing the opcode for MOV32ri.
7903 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7904 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7905 OutChains[0] = DAG.getStore(Root, dl,
7906 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7907 Trmp, TrmpAddr, 0, false, false, 0);
7909 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7910 DAG.getConstant(1, MVT::i32));
7911 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
7914 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7915 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7916 DAG.getConstant(5, MVT::i32));
7917 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7918 TrmpAddr, 5, false, false, 1);
7920 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7921 DAG.getConstant(6, MVT::i32));
7922 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
7926 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7927 return DAG.getMergeValues(Ops, 2, dl);
7931 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
7932 SelectionDAG &DAG) const {
7934 The rounding mode is in bits 11:10 of FPSR, and has the following
7941 FLT_ROUNDS, on the other hand, expects the following:
7948 To perform the conversion, we do:
7949 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7952 MachineFunction &MF = DAG.getMachineFunction();
7953 const TargetMachine &TM = MF.getTarget();
7954 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7955 unsigned StackAlignment = TFI.getStackAlignment();
7956 EVT VT = Op.getValueType();
7957 DebugLoc dl = Op.getDebugLoc();
7959 // Save FP Control Word to stack slot
7960 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7961 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7963 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7964 DAG.getEntryNode(), StackSlot);
7966 // Load FP Control Word from stack slot
7967 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
7970 // Transform as necessary
7972 DAG.getNode(ISD::SRL, dl, MVT::i16,
7973 DAG.getNode(ISD::AND, dl, MVT::i16,
7974 CWD, DAG.getConstant(0x800, MVT::i16)),
7975 DAG.getConstant(11, MVT::i8));
7977 DAG.getNode(ISD::SRL, dl, MVT::i16,
7978 DAG.getNode(ISD::AND, dl, MVT::i16,
7979 CWD, DAG.getConstant(0x400, MVT::i16)),
7980 DAG.getConstant(9, MVT::i8));
7983 DAG.getNode(ISD::AND, dl, MVT::i16,
7984 DAG.getNode(ISD::ADD, dl, MVT::i16,
7985 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7986 DAG.getConstant(1, MVT::i16)),
7987 DAG.getConstant(3, MVT::i16));
7990 return DAG.getNode((VT.getSizeInBits() < 16 ?
7991 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7994 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
7995 EVT VT = Op.getValueType();
7997 unsigned NumBits = VT.getSizeInBits();
7998 DebugLoc dl = Op.getDebugLoc();
8000 Op = Op.getOperand(0);
8001 if (VT == MVT::i8) {
8002 // Zero extend to i32 since there is not an i8 bsr.
8004 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8007 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
8008 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8009 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
8011 // If src is zero (i.e. bsr sets ZF), returns NumBits.
8014 DAG.getConstant(NumBits+NumBits-1, OpVT),
8015 DAG.getConstant(X86::COND_E, MVT::i8),
8018 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8020 // Finally xor with NumBits-1.
8021 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
8024 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8028 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
8029 EVT VT = Op.getValueType();
8031 unsigned NumBits = VT.getSizeInBits();
8032 DebugLoc dl = Op.getDebugLoc();
8034 Op = Op.getOperand(0);
8035 if (VT == MVT::i8) {
8037 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8040 // Issue a bsf (scan bits forward) which also sets EFLAGS.
8041 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8042 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
8044 // If src is zero (i.e. bsf sets ZF), returns NumBits.
8047 DAG.getConstant(NumBits, OpVT),
8048 DAG.getConstant(X86::COND_E, MVT::i8),
8051 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8054 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8058 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
8059 EVT VT = Op.getValueType();
8060 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
8061 DebugLoc dl = Op.getDebugLoc();
8063 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
8064 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
8065 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
8066 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
8067 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
8069 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
8070 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
8071 // return AloBlo + AloBhi + AhiBlo;
8073 SDValue A = Op.getOperand(0);
8074 SDValue B = Op.getOperand(1);
8076 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8077 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8078 A, DAG.getConstant(32, MVT::i32));
8079 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8080 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8081 B, DAG.getConstant(32, MVT::i32));
8082 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8083 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8085 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8086 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8088 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8089 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8091 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8092 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8093 AloBhi, DAG.getConstant(32, MVT::i32));
8094 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8095 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8096 AhiBlo, DAG.getConstant(32, MVT::i32));
8097 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
8098 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
8102 SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
8103 EVT VT = Op.getValueType();
8104 DebugLoc dl = Op.getDebugLoc();
8105 SDValue R = Op.getOperand(0);
8107 LLVMContext *Context = DAG.getContext();
8109 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later");
8111 if (VT == MVT::v4i32) {
8112 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8113 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8114 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
8116 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
8118 std::vector<Constant*> CV(4, CI);
8119 Constant *C = ConstantVector::get(CV);
8120 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8121 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8122 PseudoSourceValue::getConstantPool(), 0,
8125 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
8126 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, Op);
8127 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
8128 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
8130 if (VT == MVT::v16i8) {
8132 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8133 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8134 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
8136 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
8137 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
8139 std::vector<Constant*> CVM1(16, CM1);
8140 std::vector<Constant*> CVM2(16, CM2);
8141 Constant *C = ConstantVector::get(CVM1);
8142 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8143 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8144 PseudoSourceValue::getConstantPool(), 0,
8147 // r = pblendv(r, psllw(r & (char16)15, 4), a);
8148 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8149 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8150 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8151 DAG.getConstant(4, MVT::i32));
8152 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8153 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8156 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8158 C = ConstantVector::get(CVM2);
8159 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8160 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8161 PseudoSourceValue::getConstantPool(), 0, false, false, 16);
8163 // r = pblendv(r, psllw(r & (char16)63, 2), a);
8164 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8165 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8166 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8167 DAG.getConstant(2, MVT::i32));
8168 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8169 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8172 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8174 // return pblendv(r, r+r, a);
8175 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8176 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8177 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
8183 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
8184 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
8185 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
8186 // looks for this combo and may remove the "setcc" instruction if the "setcc"
8187 // has only one use.
8188 SDNode *N = Op.getNode();
8189 SDValue LHS = N->getOperand(0);
8190 SDValue RHS = N->getOperand(1);
8191 unsigned BaseOp = 0;
8193 DebugLoc dl = Op.getDebugLoc();
8195 switch (Op.getOpcode()) {
8196 default: llvm_unreachable("Unknown ovf instruction!");
8198 // A subtract of one will be selected as a INC. Note that INC doesn't
8199 // set CF, so we can't do this for UADDO.
8200 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8201 if (C->getAPIntValue() == 1) {
8202 BaseOp = X86ISD::INC;
8206 BaseOp = X86ISD::ADD;
8210 BaseOp = X86ISD::ADD;
8214 // A subtract of one will be selected as a DEC. Note that DEC doesn't
8215 // set CF, so we can't do this for USUBO.
8216 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8217 if (C->getAPIntValue() == 1) {
8218 BaseOp = X86ISD::DEC;
8222 BaseOp = X86ISD::SUB;
8226 BaseOp = X86ISD::SUB;
8230 BaseOp = X86ISD::SMUL;
8234 BaseOp = X86ISD::UMUL;
8239 // Also sets EFLAGS.
8240 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
8241 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
8244 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
8245 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
8247 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8251 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
8252 DebugLoc dl = Op.getDebugLoc();
8254 if (!Subtarget->hasSSE2()) {
8255 SDValue Chain = Op.getOperand(0);
8256 SDValue Zero = DAG.getConstant(0,
8257 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
8259 DAG.getRegister(X86::ESP, MVT::i32), // Base
8260 DAG.getTargetConstant(1, MVT::i8), // Scale
8261 DAG.getRegister(0, MVT::i32), // Index
8262 DAG.getTargetConstant(0, MVT::i32), // Disp
8263 DAG.getRegister(0, MVT::i32), // Segment.
8268 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
8269 array_lengthof(Ops));
8270 return SDValue(Res, 0);
8273 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
8275 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
8277 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8278 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
8279 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
8280 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
8282 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
8283 if (!Op1 && !Op2 && !Op3 && Op4)
8284 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
8286 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
8287 if (Op1 && !Op2 && !Op3 && !Op4)
8288 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
8290 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
8292 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
8295 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
8296 EVT T = Op.getValueType();
8297 DebugLoc dl = Op.getDebugLoc();
8300 switch(T.getSimpleVT().SimpleTy) {
8302 assert(false && "Invalid value type!");
8303 case MVT::i8: Reg = X86::AL; size = 1; break;
8304 case MVT::i16: Reg = X86::AX; size = 2; break;
8305 case MVT::i32: Reg = X86::EAX; size = 4; break;
8307 assert(Subtarget->is64Bit() && "Node not type legal!");
8308 Reg = X86::RAX; size = 8;
8311 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
8312 Op.getOperand(2), SDValue());
8313 SDValue Ops[] = { cpIn.getValue(0),
8316 DAG.getTargetConstant(size, MVT::i8),
8318 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8319 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
8321 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
8325 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
8326 SelectionDAG &DAG) const {
8327 assert(Subtarget->is64Bit() && "Result not type legalized?");
8328 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8329 SDValue TheChain = Op.getOperand(0);
8330 DebugLoc dl = Op.getDebugLoc();
8331 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8332 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
8333 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
8335 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
8336 DAG.getConstant(32, MVT::i8));
8338 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
8341 return DAG.getMergeValues(Ops, 2, dl);
8344 SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
8345 SelectionDAG &DAG) const {
8346 EVT SrcVT = Op.getOperand(0).getValueType();
8347 EVT DstVT = Op.getValueType();
8348 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
8349 Subtarget->hasMMX() && !DisableMMX) &&
8350 "Unexpected custom BIT_CONVERT");
8351 assert((DstVT == MVT::i64 ||
8352 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
8353 "Unexpected custom BIT_CONVERT");
8354 // i64 <=> MMX conversions are Legal.
8355 if (SrcVT==MVT::i64 && DstVT.isVector())
8357 if (DstVT==MVT::i64 && SrcVT.isVector())
8359 // MMX <=> MMX conversions are Legal.
8360 if (SrcVT.isVector() && DstVT.isVector())
8362 // All other conversions need to be expanded.
8365 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
8366 SDNode *Node = Op.getNode();
8367 DebugLoc dl = Node->getDebugLoc();
8368 EVT T = Node->getValueType(0);
8369 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
8370 DAG.getConstant(0, T), Node->getOperand(2));
8371 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
8372 cast<AtomicSDNode>(Node)->getMemoryVT(),
8373 Node->getOperand(0),
8374 Node->getOperand(1), negOp,
8375 cast<AtomicSDNode>(Node)->getSrcValue(),
8376 cast<AtomicSDNode>(Node)->getAlignment());
8379 /// LowerOperation - Provide custom lowering hooks for some operations.
8381 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8382 switch (Op.getOpcode()) {
8383 default: llvm_unreachable("Should not custom lower this!");
8384 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
8385 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
8386 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
8387 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
8388 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
8389 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
8390 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8391 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
8392 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
8393 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
8394 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
8395 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
8396 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
8397 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
8398 case ISD::SHL_PARTS:
8399 case ISD::SRA_PARTS:
8400 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
8401 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
8402 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
8403 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
8404 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
8405 case ISD::FABS: return LowerFABS(Op, DAG);
8406 case ISD::FNEG: return LowerFNEG(Op, DAG);
8407 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
8408 case ISD::SETCC: return LowerSETCC(Op, DAG);
8409 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
8410 case ISD::SELECT: return LowerSELECT(Op, DAG);
8411 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
8412 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
8413 case ISD::VASTART: return LowerVASTART(Op, DAG);
8414 case ISD::VAARG: return LowerVAARG(Op, DAG);
8415 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
8416 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
8417 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8418 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8419 case ISD::FRAME_TO_ARGS_OFFSET:
8420 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
8421 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
8422 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
8423 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
8424 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
8425 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
8426 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
8427 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
8428 case ISD::SHL: return LowerSHL(Op, DAG);
8434 case ISD::UMULO: return LowerXALUO(Op, DAG);
8435 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
8436 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
8440 void X86TargetLowering::
8441 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
8442 SelectionDAG &DAG, unsigned NewOp) const {
8443 EVT T = Node->getValueType(0);
8444 DebugLoc dl = Node->getDebugLoc();
8445 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
8447 SDValue Chain = Node->getOperand(0);
8448 SDValue In1 = Node->getOperand(1);
8449 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8450 Node->getOperand(2), DAG.getIntPtrConstant(0));
8451 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8452 Node->getOperand(2), DAG.getIntPtrConstant(1));
8453 SDValue Ops[] = { Chain, In1, In2L, In2H };
8454 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
8456 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
8457 cast<MemSDNode>(Node)->getMemOperand());
8458 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
8459 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8460 Results.push_back(Result.getValue(2));
8463 /// ReplaceNodeResults - Replace a node with an illegal result type
8464 /// with a new node built out of custom code.
8465 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
8466 SmallVectorImpl<SDValue>&Results,
8467 SelectionDAG &DAG) const {
8468 DebugLoc dl = N->getDebugLoc();
8469 switch (N->getOpcode()) {
8471 assert(false && "Do not know how to custom type legalize this operation!");
8473 case ISD::FP_TO_SINT: {
8474 std::pair<SDValue,SDValue> Vals =
8475 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
8476 SDValue FIST = Vals.first, StackSlot = Vals.second;
8477 if (FIST.getNode() != 0) {
8478 EVT VT = N->getValueType(0);
8479 // Return a load from the stack slot.
8480 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
8485 case ISD::READCYCLECOUNTER: {
8486 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8487 SDValue TheChain = N->getOperand(0);
8488 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8489 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
8491 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
8493 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
8494 SDValue Ops[] = { eax, edx };
8495 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
8496 Results.push_back(edx.getValue(1));
8499 case ISD::ATOMIC_CMP_SWAP: {
8500 EVT T = N->getValueType(0);
8501 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
8502 SDValue cpInL, cpInH;
8503 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8504 DAG.getConstant(0, MVT::i32));
8505 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8506 DAG.getConstant(1, MVT::i32));
8507 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
8508 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
8510 SDValue swapInL, swapInH;
8511 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8512 DAG.getConstant(0, MVT::i32));
8513 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8514 DAG.getConstant(1, MVT::i32));
8515 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
8517 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
8518 swapInL.getValue(1));
8519 SDValue Ops[] = { swapInH.getValue(0),
8521 swapInH.getValue(1) };
8522 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8523 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
8524 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
8525 MVT::i32, Result.getValue(1));
8526 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
8527 MVT::i32, cpOutL.getValue(2));
8528 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
8529 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8530 Results.push_back(cpOutH.getValue(1));
8533 case ISD::ATOMIC_LOAD_ADD:
8534 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
8536 case ISD::ATOMIC_LOAD_AND:
8537 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
8539 case ISD::ATOMIC_LOAD_NAND:
8540 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
8542 case ISD::ATOMIC_LOAD_OR:
8543 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
8545 case ISD::ATOMIC_LOAD_SUB:
8546 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
8548 case ISD::ATOMIC_LOAD_XOR:
8549 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
8551 case ISD::ATOMIC_SWAP:
8552 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
8557 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
8559 default: return NULL;
8560 case X86ISD::BSF: return "X86ISD::BSF";
8561 case X86ISD::BSR: return "X86ISD::BSR";
8562 case X86ISD::SHLD: return "X86ISD::SHLD";
8563 case X86ISD::SHRD: return "X86ISD::SHRD";
8564 case X86ISD::FAND: return "X86ISD::FAND";
8565 case X86ISD::FOR: return "X86ISD::FOR";
8566 case X86ISD::FXOR: return "X86ISD::FXOR";
8567 case X86ISD::FSRL: return "X86ISD::FSRL";
8568 case X86ISD::FILD: return "X86ISD::FILD";
8569 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
8570 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
8571 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
8572 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
8573 case X86ISD::FLD: return "X86ISD::FLD";
8574 case X86ISD::FST: return "X86ISD::FST";
8575 case X86ISD::CALL: return "X86ISD::CALL";
8576 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
8577 case X86ISD::BT: return "X86ISD::BT";
8578 case X86ISD::CMP: return "X86ISD::CMP";
8579 case X86ISD::COMI: return "X86ISD::COMI";
8580 case X86ISD::UCOMI: return "X86ISD::UCOMI";
8581 case X86ISD::SETCC: return "X86ISD::SETCC";
8582 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
8583 case X86ISD::CMOV: return "X86ISD::CMOV";
8584 case X86ISD::BRCOND: return "X86ISD::BRCOND";
8585 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
8586 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
8587 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
8588 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
8589 case X86ISD::Wrapper: return "X86ISD::Wrapper";
8590 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
8591 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
8592 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
8593 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
8594 case X86ISD::PINSRB: return "X86ISD::PINSRB";
8595 case X86ISD::PINSRW: return "X86ISD::PINSRW";
8596 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
8597 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
8598 case X86ISD::FMAX: return "X86ISD::FMAX";
8599 case X86ISD::FMIN: return "X86ISD::FMIN";
8600 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
8601 case X86ISD::FRCP: return "X86ISD::FRCP";
8602 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
8603 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
8604 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
8605 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
8606 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
8607 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
8608 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
8609 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
8610 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
8611 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
8612 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
8613 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
8614 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
8615 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
8616 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
8617 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
8618 case X86ISD::VSHL: return "X86ISD::VSHL";
8619 case X86ISD::VSRL: return "X86ISD::VSRL";
8620 case X86ISD::CMPPD: return "X86ISD::CMPPD";
8621 case X86ISD::CMPPS: return "X86ISD::CMPPS";
8622 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
8623 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
8624 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
8625 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
8626 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
8627 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
8628 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
8629 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
8630 case X86ISD::ADD: return "X86ISD::ADD";
8631 case X86ISD::SUB: return "X86ISD::SUB";
8632 case X86ISD::SMUL: return "X86ISD::SMUL";
8633 case X86ISD::UMUL: return "X86ISD::UMUL";
8634 case X86ISD::INC: return "X86ISD::INC";
8635 case X86ISD::DEC: return "X86ISD::DEC";
8636 case X86ISD::OR: return "X86ISD::OR";
8637 case X86ISD::XOR: return "X86ISD::XOR";
8638 case X86ISD::AND: return "X86ISD::AND";
8639 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
8640 case X86ISD::PTEST: return "X86ISD::PTEST";
8641 case X86ISD::TESTP: return "X86ISD::TESTP";
8642 case X86ISD::PALIGN: return "X86ISD::PALIGN";
8643 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
8644 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
8645 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
8646 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
8647 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
8648 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
8649 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
8650 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
8651 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
8652 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
8653 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
8654 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
8655 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
8656 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
8657 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
8658 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
8659 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
8660 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
8661 case X86ISD::MOVSD: return "X86ISD::MOVSD";
8662 case X86ISD::MOVSS: return "X86ISD::MOVSS";
8663 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
8664 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
8665 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
8666 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
8667 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
8668 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
8669 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
8670 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
8671 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
8672 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
8673 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
8674 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
8675 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
8676 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
8680 // isLegalAddressingMode - Return true if the addressing mode represented
8681 // by AM is legal for this target, for a load/store of the specified type.
8682 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
8683 const Type *Ty) const {
8684 // X86 supports extremely general addressing modes.
8685 CodeModel::Model M = getTargetMachine().getCodeModel();
8686 Reloc::Model R = getTargetMachine().getRelocationModel();
8688 // X86 allows a sign-extended 32-bit immediate field as a displacement.
8689 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
8694 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
8696 // If a reference to this global requires an extra load, we can't fold it.
8697 if (isGlobalStubReference(GVFlags))
8700 // If BaseGV requires a register for the PIC base, we cannot also have a
8701 // BaseReg specified.
8702 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
8705 // If lower 4G is not available, then we must use rip-relative addressing.
8706 if ((M != CodeModel::Small || R != Reloc::Static) &&
8707 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
8717 // These scales always work.
8722 // These scales are formed with basereg+scalereg. Only accept if there is
8727 default: // Other stuff never works.
8735 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
8736 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8738 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8739 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8740 if (NumBits1 <= NumBits2)
8745 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8746 if (!VT1.isInteger() || !VT2.isInteger())
8748 unsigned NumBits1 = VT1.getSizeInBits();
8749 unsigned NumBits2 = VT2.getSizeInBits();
8750 if (NumBits1 <= NumBits2)
8755 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
8756 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8757 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
8760 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
8761 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8762 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
8765 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
8766 // i16 instructions are longer (0x66 prefix) and potentially slower.
8767 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
8770 /// isShuffleMaskLegal - Targets can use this to indicate that they only
8771 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
8772 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
8773 /// are assumed to be legal.
8775 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
8777 // Very little shuffling can be done for 64-bit vectors right now.
8778 if (VT.getSizeInBits() == 64)
8779 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
8781 // FIXME: pshufb, blends, shifts.
8782 return (VT.getVectorNumElements() == 2 ||
8783 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
8784 isMOVLMask(M, VT) ||
8785 isSHUFPMask(M, VT) ||
8786 isPSHUFDMask(M, VT) ||
8787 isPSHUFHWMask(M, VT) ||
8788 isPSHUFLWMask(M, VT) ||
8789 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
8790 isUNPCKLMask(M, VT) ||
8791 isUNPCKHMask(M, VT) ||
8792 isUNPCKL_v_undef_Mask(M, VT) ||
8793 isUNPCKH_v_undef_Mask(M, VT));
8797 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
8799 unsigned NumElts = VT.getVectorNumElements();
8800 // FIXME: This collection of masks seems suspect.
8803 if (NumElts == 4 && VT.getSizeInBits() == 128) {
8804 return (isMOVLMask(Mask, VT) ||
8805 isCommutedMOVLMask(Mask, VT, true) ||
8806 isSHUFPMask(Mask, VT) ||
8807 isCommutedSHUFPMask(Mask, VT));
8812 //===----------------------------------------------------------------------===//
8813 // X86 Scheduler Hooks
8814 //===----------------------------------------------------------------------===//
8816 // private utility function
8818 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
8819 MachineBasicBlock *MBB,
8826 TargetRegisterClass *RC,
8827 bool invSrc) const {
8828 // For the atomic bitwise operator, we generate
8831 // ld t1 = [bitinstr.addr]
8832 // op t2 = t1, [bitinstr.val]
8834 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8836 // fallthrough -->nextMBB
8837 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8838 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8839 MachineFunction::iterator MBBIter = MBB;
8842 /// First build the CFG
8843 MachineFunction *F = MBB->getParent();
8844 MachineBasicBlock *thisMBB = MBB;
8845 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8846 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8847 F->insert(MBBIter, newMBB);
8848 F->insert(MBBIter, nextMBB);
8850 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8851 nextMBB->splice(nextMBB->begin(), thisMBB,
8852 llvm::next(MachineBasicBlock::iterator(bInstr)),
8854 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8856 // Update thisMBB to fall through to newMBB
8857 thisMBB->addSuccessor(newMBB);
8859 // newMBB jumps to itself and fall through to nextMBB
8860 newMBB->addSuccessor(nextMBB);
8861 newMBB->addSuccessor(newMBB);
8863 // Insert instructions into newMBB based on incoming instruction
8864 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
8865 "unexpected number of operands");
8866 DebugLoc dl = bInstr->getDebugLoc();
8867 MachineOperand& destOper = bInstr->getOperand(0);
8868 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8869 int numArgs = bInstr->getNumOperands() - 1;
8870 for (int i=0; i < numArgs; ++i)
8871 argOpers[i] = &bInstr->getOperand(i+1);
8873 // x86 address has 4 operands: base, index, scale, and displacement
8874 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8875 int valArgIndx = lastAddrIndx + 1;
8877 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8878 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
8879 for (int i=0; i <= lastAddrIndx; ++i)
8880 (*MIB).addOperand(*argOpers[i]);
8882 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
8884 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
8889 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8890 assert((argOpers[valArgIndx]->isReg() ||
8891 argOpers[valArgIndx]->isImm()) &&
8893 if (argOpers[valArgIndx]->isReg())
8894 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
8896 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
8898 (*MIB).addOperand(*argOpers[valArgIndx]);
8900 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
8903 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
8904 for (int i=0; i <= lastAddrIndx; ++i)
8905 (*MIB).addOperand(*argOpers[i]);
8907 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8908 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8909 bInstr->memoperands_end());
8911 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
8915 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8917 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
8921 // private utility function: 64 bit atomics on 32 bit host.
8923 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
8924 MachineBasicBlock *MBB,
8929 bool invSrc) const {
8930 // For the atomic bitwise operator, we generate
8931 // thisMBB (instructions are in pairs, except cmpxchg8b)
8932 // ld t1,t2 = [bitinstr.addr]
8934 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
8935 // op t5, t6 <- out1, out2, [bitinstr.val]
8936 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
8937 // mov ECX, EBX <- t5, t6
8938 // mov EAX, EDX <- t1, t2
8939 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
8940 // mov t3, t4 <- EAX, EDX
8942 // result in out1, out2
8943 // fallthrough -->nextMBB
8945 const TargetRegisterClass *RC = X86::GR32RegisterClass;
8946 const unsigned LoadOpc = X86::MOV32rm;
8947 const unsigned NotOpc = X86::NOT32r;
8948 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8949 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8950 MachineFunction::iterator MBBIter = MBB;
8953 /// First build the CFG
8954 MachineFunction *F = MBB->getParent();
8955 MachineBasicBlock *thisMBB = MBB;
8956 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8957 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8958 F->insert(MBBIter, newMBB);
8959 F->insert(MBBIter, nextMBB);
8961 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8962 nextMBB->splice(nextMBB->begin(), thisMBB,
8963 llvm::next(MachineBasicBlock::iterator(bInstr)),
8965 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8967 // Update thisMBB to fall through to newMBB
8968 thisMBB->addSuccessor(newMBB);
8970 // newMBB jumps to itself and fall through to nextMBB
8971 newMBB->addSuccessor(nextMBB);
8972 newMBB->addSuccessor(newMBB);
8974 DebugLoc dl = bInstr->getDebugLoc();
8975 // Insert instructions into newMBB based on incoming instruction
8976 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
8977 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
8978 "unexpected number of operands");
8979 MachineOperand& dest1Oper = bInstr->getOperand(0);
8980 MachineOperand& dest2Oper = bInstr->getOperand(1);
8981 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8982 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
8983 argOpers[i] = &bInstr->getOperand(i+2);
8985 // We use some of the operands multiple times, so conservatively just
8986 // clear any kill flags that might be present.
8987 if (argOpers[i]->isReg() && argOpers[i]->isUse())
8988 argOpers[i]->setIsKill(false);
8991 // x86 address has 5 operands: base, index, scale, displacement, and segment.
8992 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8994 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8995 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
8996 for (int i=0; i <= lastAddrIndx; ++i)
8997 (*MIB).addOperand(*argOpers[i]);
8998 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8999 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
9000 // add 4 to displacement.
9001 for (int i=0; i <= lastAddrIndx-2; ++i)
9002 (*MIB).addOperand(*argOpers[i]);
9003 MachineOperand newOp3 = *(argOpers[3]);
9005 newOp3.setImm(newOp3.getImm()+4);
9007 newOp3.setOffset(newOp3.getOffset()+4);
9008 (*MIB).addOperand(newOp3);
9009 (*MIB).addOperand(*argOpers[lastAddrIndx]);
9011 // t3/4 are defined later, at the bottom of the loop
9012 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
9013 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
9014 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
9015 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
9016 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
9017 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
9019 // The subsequent operations should be using the destination registers of
9020 //the PHI instructions.
9022 t1 = F->getRegInfo().createVirtualRegister(RC);
9023 t2 = F->getRegInfo().createVirtualRegister(RC);
9024 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
9025 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
9027 t1 = dest1Oper.getReg();
9028 t2 = dest2Oper.getReg();
9031 int valArgIndx = lastAddrIndx + 1;
9032 assert((argOpers[valArgIndx]->isReg() ||
9033 argOpers[valArgIndx]->isImm()) &&
9035 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
9036 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
9037 if (argOpers[valArgIndx]->isReg())
9038 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
9040 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
9041 if (regOpcL != X86::MOV32rr)
9043 (*MIB).addOperand(*argOpers[valArgIndx]);
9044 assert(argOpers[valArgIndx + 1]->isReg() ==
9045 argOpers[valArgIndx]->isReg());
9046 assert(argOpers[valArgIndx + 1]->isImm() ==
9047 argOpers[valArgIndx]->isImm());
9048 if (argOpers[valArgIndx + 1]->isReg())
9049 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
9051 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
9052 if (regOpcH != X86::MOV32rr)
9054 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
9056 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9058 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
9061 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
9063 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
9066 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
9067 for (int i=0; i <= lastAddrIndx; ++i)
9068 (*MIB).addOperand(*argOpers[i]);
9070 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9071 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9072 bInstr->memoperands_end());
9074 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
9075 MIB.addReg(X86::EAX);
9076 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
9077 MIB.addReg(X86::EDX);
9080 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9082 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9086 // private utility function
9088 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
9089 MachineBasicBlock *MBB,
9090 unsigned cmovOpc) const {
9091 // For the atomic min/max operator, we generate
9094 // ld t1 = [min/max.addr]
9095 // mov t2 = [min/max.val]
9097 // cmov[cond] t2 = t1
9099 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9101 // fallthrough -->nextMBB
9103 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9104 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9105 MachineFunction::iterator MBBIter = MBB;
9108 /// First build the CFG
9109 MachineFunction *F = MBB->getParent();
9110 MachineBasicBlock *thisMBB = MBB;
9111 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9112 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9113 F->insert(MBBIter, newMBB);
9114 F->insert(MBBIter, nextMBB);
9116 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9117 nextMBB->splice(nextMBB->begin(), thisMBB,
9118 llvm::next(MachineBasicBlock::iterator(mInstr)),
9120 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9122 // Update thisMBB to fall through to newMBB
9123 thisMBB->addSuccessor(newMBB);
9125 // newMBB jumps to newMBB and fall through to nextMBB
9126 newMBB->addSuccessor(nextMBB);
9127 newMBB->addSuccessor(newMBB);
9129 DebugLoc dl = mInstr->getDebugLoc();
9130 // Insert instructions into newMBB based on incoming instruction
9131 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9132 "unexpected number of operands");
9133 MachineOperand& destOper = mInstr->getOperand(0);
9134 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9135 int numArgs = mInstr->getNumOperands() - 1;
9136 for (int i=0; i < numArgs; ++i)
9137 argOpers[i] = &mInstr->getOperand(i+1);
9139 // x86 address has 4 operands: base, index, scale, and displacement
9140 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9141 int valArgIndx = lastAddrIndx + 1;
9143 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9144 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
9145 for (int i=0; i <= lastAddrIndx; ++i)
9146 (*MIB).addOperand(*argOpers[i]);
9148 // We only support register and immediate values
9149 assert((argOpers[valArgIndx]->isReg() ||
9150 argOpers[valArgIndx]->isImm()) &&
9153 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9154 if (argOpers[valArgIndx]->isReg())
9155 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
9157 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
9158 (*MIB).addOperand(*argOpers[valArgIndx]);
9160 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9163 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
9168 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9169 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
9173 // Cmp and exchange if none has modified the memory location
9174 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
9175 for (int i=0; i <= lastAddrIndx; ++i)
9176 (*MIB).addOperand(*argOpers[i]);
9178 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9179 (*MIB).setMemRefs(mInstr->memoperands_begin(),
9180 mInstr->memoperands_end());
9182 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9183 MIB.addReg(X86::EAX);
9186 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9188 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
9192 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
9193 // or XMM0_V32I8 in AVX all of this code can be replaced with that
9196 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
9197 unsigned numArgs, bool memArg) const {
9199 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
9200 "Target must have SSE4.2 or AVX features enabled");
9202 DebugLoc dl = MI->getDebugLoc();
9203 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9207 if (!Subtarget->hasAVX()) {
9209 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
9211 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
9214 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
9216 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
9219 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
9221 for (unsigned i = 0; i < numArgs; ++i) {
9222 MachineOperand &Op = MI->getOperand(i+1);
9224 if (!(Op.isReg() && Op.isImplicit()))
9228 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
9231 MI->eraseFromParent();
9237 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
9239 MachineBasicBlock *MBB) const {
9240 // Emit code to save XMM registers to the stack. The ABI says that the
9241 // number of registers to save is given in %al, so it's theoretically
9242 // possible to do an indirect jump trick to avoid saving all of them,
9243 // however this code takes a simpler approach and just executes all
9244 // of the stores if %al is non-zero. It's less code, and it's probably
9245 // easier on the hardware branch predictor, and stores aren't all that
9246 // expensive anyway.
9248 // Create the new basic blocks. One block contains all the XMM stores,
9249 // and one block is the final destination regardless of whether any
9250 // stores were performed.
9251 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9252 MachineFunction *F = MBB->getParent();
9253 MachineFunction::iterator MBBIter = MBB;
9255 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
9256 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
9257 F->insert(MBBIter, XMMSaveMBB);
9258 F->insert(MBBIter, EndMBB);
9260 // Transfer the remainder of MBB and its successor edges to EndMBB.
9261 EndMBB->splice(EndMBB->begin(), MBB,
9262 llvm::next(MachineBasicBlock::iterator(MI)),
9264 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
9266 // The original block will now fall through to the XMM save block.
9267 MBB->addSuccessor(XMMSaveMBB);
9268 // The XMMSaveMBB will fall through to the end block.
9269 XMMSaveMBB->addSuccessor(EndMBB);
9271 // Now add the instructions.
9272 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9273 DebugLoc DL = MI->getDebugLoc();
9275 unsigned CountReg = MI->getOperand(0).getReg();
9276 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
9277 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
9279 if (!Subtarget->isTargetWin64()) {
9280 // If %al is 0, branch around the XMM save block.
9281 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
9282 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
9283 MBB->addSuccessor(EndMBB);
9286 // In the XMM save block, save all the XMM argument registers.
9287 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
9288 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
9289 MachineMemOperand *MMO =
9290 F->getMachineMemOperand(
9291 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
9292 MachineMemOperand::MOStore, Offset,
9293 /*Size=*/16, /*Align=*/16);
9294 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
9295 .addFrameIndex(RegSaveFrameIndex)
9296 .addImm(/*Scale=*/1)
9297 .addReg(/*IndexReg=*/0)
9298 .addImm(/*Disp=*/Offset)
9299 .addReg(/*Segment=*/0)
9300 .addReg(MI->getOperand(i).getReg())
9301 .addMemOperand(MMO);
9304 MI->eraseFromParent(); // The pseudo instruction is gone now.
9310 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
9311 MachineBasicBlock *BB) const {
9312 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9313 DebugLoc DL = MI->getDebugLoc();
9315 // To "insert" a SELECT_CC instruction, we actually have to insert the
9316 // diamond control-flow pattern. The incoming instruction knows the
9317 // destination vreg to set, the condition code register to branch on, the
9318 // true/false values to select between, and a branch opcode to use.
9319 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9320 MachineFunction::iterator It = BB;
9326 // cmpTY ccX, r1, r2
9328 // fallthrough --> copy0MBB
9329 MachineBasicBlock *thisMBB = BB;
9330 MachineFunction *F = BB->getParent();
9331 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
9332 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
9333 F->insert(It, copy0MBB);
9334 F->insert(It, sinkMBB);
9336 // If the EFLAGS register isn't dead in the terminator, then claim that it's
9337 // live into the sink and copy blocks.
9338 const MachineFunction *MF = BB->getParent();
9339 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
9340 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
9342 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
9343 const MachineOperand &MO = MI->getOperand(I);
9344 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
9345 unsigned Reg = MO.getReg();
9346 if (Reg != X86::EFLAGS) continue;
9347 copy0MBB->addLiveIn(Reg);
9348 sinkMBB->addLiveIn(Reg);
9351 // Transfer the remainder of BB and its successor edges to sinkMBB.
9352 sinkMBB->splice(sinkMBB->begin(), BB,
9353 llvm::next(MachineBasicBlock::iterator(MI)),
9355 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
9357 // Add the true and fallthrough blocks as its successors.
9358 BB->addSuccessor(copy0MBB);
9359 BB->addSuccessor(sinkMBB);
9361 // Create the conditional branch instruction.
9363 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
9364 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
9367 // %FalseValue = ...
9368 // # fallthrough to sinkMBB
9369 copy0MBB->addSuccessor(sinkMBB);
9372 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
9374 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
9375 TII->get(X86::PHI), MI->getOperand(0).getReg())
9376 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
9377 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
9379 MI->eraseFromParent(); // The pseudo instruction is gone now.
9384 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
9385 MachineBasicBlock *BB) const {
9386 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9387 DebugLoc DL = MI->getDebugLoc();
9389 // The lowering is pretty easy: we're just emitting the call to _alloca. The
9390 // non-trivial part is impdef of ESP.
9391 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
9394 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
9395 .addExternalSymbol("_alloca")
9396 .addReg(X86::EAX, RegState::Implicit)
9397 .addReg(X86::ESP, RegState::Implicit)
9398 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
9399 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
9400 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
9402 MI->eraseFromParent(); // The pseudo instruction is gone now.
9407 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
9408 MachineBasicBlock *BB) const {
9409 // This is pretty easy. We're taking the value that we received from
9410 // our load from the relocation, sticking it in either RDI (x86-64)
9411 // or EAX and doing an indirect call. The return value will then
9412 // be in the normal return register.
9413 const X86InstrInfo *TII
9414 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
9415 DebugLoc DL = MI->getDebugLoc();
9416 MachineFunction *F = BB->getParent();
9417 bool IsWin64 = Subtarget->isTargetWin64();
9419 assert(MI->getOperand(3).isGlobal() && "This should be a global");
9421 if (Subtarget->is64Bit()) {
9422 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9423 TII->get(X86::MOV64rm), X86::RDI)
9425 .addImm(0).addReg(0)
9426 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9427 MI->getOperand(3).getTargetFlags())
9429 MIB = BuildMI(*BB, MI, DL, TII->get(IsWin64 ? X86::WINCALL64m : X86::CALL64m));
9430 addDirectMem(MIB, X86::RDI);
9431 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
9432 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9433 TII->get(X86::MOV32rm), X86::EAX)
9435 .addImm(0).addReg(0)
9436 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9437 MI->getOperand(3).getTargetFlags())
9439 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
9440 addDirectMem(MIB, X86::EAX);
9442 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9443 TII->get(X86::MOV32rm), X86::EAX)
9444 .addReg(TII->getGlobalBaseReg(F))
9445 .addImm(0).addReg(0)
9446 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9447 MI->getOperand(3).getTargetFlags())
9449 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
9450 addDirectMem(MIB, X86::EAX);
9453 MI->eraseFromParent(); // The pseudo instruction is gone now.
9458 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
9459 MachineBasicBlock *BB) const {
9460 switch (MI->getOpcode()) {
9461 default: assert(false && "Unexpected instr type to insert");
9462 case X86::MINGW_ALLOCA:
9463 return EmitLoweredMingwAlloca(MI, BB);
9464 case X86::TLSCall_32:
9465 case X86::TLSCall_64:
9466 return EmitLoweredTLSCall(MI, BB);
9468 case X86::CMOV_V1I64:
9469 case X86::CMOV_FR32:
9470 case X86::CMOV_FR64:
9471 case X86::CMOV_V4F32:
9472 case X86::CMOV_V2F64:
9473 case X86::CMOV_V2I64:
9474 case X86::CMOV_GR16:
9475 case X86::CMOV_GR32:
9476 case X86::CMOV_RFP32:
9477 case X86::CMOV_RFP64:
9478 case X86::CMOV_RFP80:
9479 return EmitLoweredSelect(MI, BB);
9481 case X86::FP32_TO_INT16_IN_MEM:
9482 case X86::FP32_TO_INT32_IN_MEM:
9483 case X86::FP32_TO_INT64_IN_MEM:
9484 case X86::FP64_TO_INT16_IN_MEM:
9485 case X86::FP64_TO_INT32_IN_MEM:
9486 case X86::FP64_TO_INT64_IN_MEM:
9487 case X86::FP80_TO_INT16_IN_MEM:
9488 case X86::FP80_TO_INT32_IN_MEM:
9489 case X86::FP80_TO_INT64_IN_MEM: {
9490 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9491 DebugLoc DL = MI->getDebugLoc();
9493 // Change the floating point control register to use "round towards zero"
9494 // mode when truncating to an integer value.
9495 MachineFunction *F = BB->getParent();
9496 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
9497 addFrameReference(BuildMI(*BB, MI, DL,
9498 TII->get(X86::FNSTCW16m)), CWFrameIdx);
9500 // Load the old value of the high byte of the control word...
9502 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
9503 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
9506 // Set the high part to be round to zero...
9507 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
9510 // Reload the modified control word now...
9511 addFrameReference(BuildMI(*BB, MI, DL,
9512 TII->get(X86::FLDCW16m)), CWFrameIdx);
9514 // Restore the memory image of control word to original value
9515 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
9518 // Get the X86 opcode to use.
9520 switch (MI->getOpcode()) {
9521 default: llvm_unreachable("illegal opcode!");
9522 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
9523 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
9524 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
9525 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
9526 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
9527 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
9528 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
9529 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
9530 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
9534 MachineOperand &Op = MI->getOperand(0);
9536 AM.BaseType = X86AddressMode::RegBase;
9537 AM.Base.Reg = Op.getReg();
9539 AM.BaseType = X86AddressMode::FrameIndexBase;
9540 AM.Base.FrameIndex = Op.getIndex();
9542 Op = MI->getOperand(1);
9544 AM.Scale = Op.getImm();
9545 Op = MI->getOperand(2);
9547 AM.IndexReg = Op.getImm();
9548 Op = MI->getOperand(3);
9549 if (Op.isGlobal()) {
9550 AM.GV = Op.getGlobal();
9552 AM.Disp = Op.getImm();
9554 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
9555 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
9557 // Reload the original control word now.
9558 addFrameReference(BuildMI(*BB, MI, DL,
9559 TII->get(X86::FLDCW16m)), CWFrameIdx);
9561 MI->eraseFromParent(); // The pseudo instruction is gone now.
9564 // String/text processing lowering.
9565 case X86::PCMPISTRM128REG:
9566 case X86::VPCMPISTRM128REG:
9567 return EmitPCMP(MI, BB, 3, false /* in-mem */);
9568 case X86::PCMPISTRM128MEM:
9569 case X86::VPCMPISTRM128MEM:
9570 return EmitPCMP(MI, BB, 3, true /* in-mem */);
9571 case X86::PCMPESTRM128REG:
9572 case X86::VPCMPESTRM128REG:
9573 return EmitPCMP(MI, BB, 5, false /* in mem */);
9574 case X86::PCMPESTRM128MEM:
9575 case X86::VPCMPESTRM128MEM:
9576 return EmitPCMP(MI, BB, 5, true /* in mem */);
9579 case X86::ATOMAND32:
9580 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
9581 X86::AND32ri, X86::MOV32rm,
9583 X86::NOT32r, X86::EAX,
9584 X86::GR32RegisterClass);
9586 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
9587 X86::OR32ri, X86::MOV32rm,
9589 X86::NOT32r, X86::EAX,
9590 X86::GR32RegisterClass);
9591 case X86::ATOMXOR32:
9592 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
9593 X86::XOR32ri, X86::MOV32rm,
9595 X86::NOT32r, X86::EAX,
9596 X86::GR32RegisterClass);
9597 case X86::ATOMNAND32:
9598 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
9599 X86::AND32ri, X86::MOV32rm,
9601 X86::NOT32r, X86::EAX,
9602 X86::GR32RegisterClass, true);
9603 case X86::ATOMMIN32:
9604 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
9605 case X86::ATOMMAX32:
9606 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
9607 case X86::ATOMUMIN32:
9608 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
9609 case X86::ATOMUMAX32:
9610 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
9612 case X86::ATOMAND16:
9613 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
9614 X86::AND16ri, X86::MOV16rm,
9616 X86::NOT16r, X86::AX,
9617 X86::GR16RegisterClass);
9619 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
9620 X86::OR16ri, X86::MOV16rm,
9622 X86::NOT16r, X86::AX,
9623 X86::GR16RegisterClass);
9624 case X86::ATOMXOR16:
9625 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
9626 X86::XOR16ri, X86::MOV16rm,
9628 X86::NOT16r, X86::AX,
9629 X86::GR16RegisterClass);
9630 case X86::ATOMNAND16:
9631 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
9632 X86::AND16ri, X86::MOV16rm,
9634 X86::NOT16r, X86::AX,
9635 X86::GR16RegisterClass, true);
9636 case X86::ATOMMIN16:
9637 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
9638 case X86::ATOMMAX16:
9639 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
9640 case X86::ATOMUMIN16:
9641 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
9642 case X86::ATOMUMAX16:
9643 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
9646 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
9647 X86::AND8ri, X86::MOV8rm,
9649 X86::NOT8r, X86::AL,
9650 X86::GR8RegisterClass);
9652 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
9653 X86::OR8ri, X86::MOV8rm,
9655 X86::NOT8r, X86::AL,
9656 X86::GR8RegisterClass);
9658 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
9659 X86::XOR8ri, X86::MOV8rm,
9661 X86::NOT8r, X86::AL,
9662 X86::GR8RegisterClass);
9663 case X86::ATOMNAND8:
9664 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
9665 X86::AND8ri, X86::MOV8rm,
9667 X86::NOT8r, X86::AL,
9668 X86::GR8RegisterClass, true);
9669 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
9670 // This group is for 64-bit host.
9671 case X86::ATOMAND64:
9672 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
9673 X86::AND64ri32, X86::MOV64rm,
9675 X86::NOT64r, X86::RAX,
9676 X86::GR64RegisterClass);
9678 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
9679 X86::OR64ri32, X86::MOV64rm,
9681 X86::NOT64r, X86::RAX,
9682 X86::GR64RegisterClass);
9683 case X86::ATOMXOR64:
9684 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
9685 X86::XOR64ri32, X86::MOV64rm,
9687 X86::NOT64r, X86::RAX,
9688 X86::GR64RegisterClass);
9689 case X86::ATOMNAND64:
9690 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
9691 X86::AND64ri32, X86::MOV64rm,
9693 X86::NOT64r, X86::RAX,
9694 X86::GR64RegisterClass, true);
9695 case X86::ATOMMIN64:
9696 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
9697 case X86::ATOMMAX64:
9698 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
9699 case X86::ATOMUMIN64:
9700 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
9701 case X86::ATOMUMAX64:
9702 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
9704 // This group does 64-bit operations on a 32-bit host.
9705 case X86::ATOMAND6432:
9706 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9707 X86::AND32rr, X86::AND32rr,
9708 X86::AND32ri, X86::AND32ri,
9710 case X86::ATOMOR6432:
9711 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9712 X86::OR32rr, X86::OR32rr,
9713 X86::OR32ri, X86::OR32ri,
9715 case X86::ATOMXOR6432:
9716 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9717 X86::XOR32rr, X86::XOR32rr,
9718 X86::XOR32ri, X86::XOR32ri,
9720 case X86::ATOMNAND6432:
9721 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9722 X86::AND32rr, X86::AND32rr,
9723 X86::AND32ri, X86::AND32ri,
9725 case X86::ATOMADD6432:
9726 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9727 X86::ADD32rr, X86::ADC32rr,
9728 X86::ADD32ri, X86::ADC32ri,
9730 case X86::ATOMSUB6432:
9731 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9732 X86::SUB32rr, X86::SBB32rr,
9733 X86::SUB32ri, X86::SBB32ri,
9735 case X86::ATOMSWAP6432:
9736 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9737 X86::MOV32rr, X86::MOV32rr,
9738 X86::MOV32ri, X86::MOV32ri,
9740 case X86::VASTART_SAVE_XMM_REGS:
9741 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
9745 //===----------------------------------------------------------------------===//
9746 // X86 Optimization Hooks
9747 //===----------------------------------------------------------------------===//
9749 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
9753 const SelectionDAG &DAG,
9754 unsigned Depth) const {
9755 unsigned Opc = Op.getOpcode();
9756 assert((Opc >= ISD::BUILTIN_OP_END ||
9757 Opc == ISD::INTRINSIC_WO_CHAIN ||
9758 Opc == ISD::INTRINSIC_W_CHAIN ||
9759 Opc == ISD::INTRINSIC_VOID) &&
9760 "Should use MaskedValueIsZero if you don't know whether Op"
9761 " is a target node!");
9763 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
9775 // These nodes' second result is a boolean.
9776 if (Op.getResNo() == 0)
9780 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
9781 Mask.getBitWidth() - 1);
9786 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
9787 /// node is a GlobalAddress + offset.
9788 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
9789 const GlobalValue* &GA,
9790 int64_t &Offset) const {
9791 if (N->getOpcode() == X86ISD::Wrapper) {
9792 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
9793 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
9794 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
9798 return TargetLowering::isGAPlusOffset(N, GA, Offset);
9801 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
9802 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
9803 /// if the load addresses are consecutive, non-overlapping, and in the right
9805 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
9806 const TargetLowering &TLI) {
9807 DebugLoc dl = N->getDebugLoc();
9808 EVT VT = N->getValueType(0);
9810 if (VT.getSizeInBits() != 128)
9813 SmallVector<SDValue, 16> Elts;
9814 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
9815 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
9817 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
9820 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
9821 /// generation and convert it from being a bunch of shuffles and extracts
9822 /// to a simple store and scalar loads to extract the elements.
9823 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
9824 const TargetLowering &TLI) {
9825 SDValue InputVector = N->getOperand(0);
9827 // Only operate on vectors of 4 elements, where the alternative shuffling
9828 // gets to be more expensive.
9829 if (InputVector.getValueType() != MVT::v4i32)
9832 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
9833 // single use which is a sign-extend or zero-extend, and all elements are
9835 SmallVector<SDNode *, 4> Uses;
9836 unsigned ExtractedElements = 0;
9837 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
9838 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
9839 if (UI.getUse().getResNo() != InputVector.getResNo())
9842 SDNode *Extract = *UI;
9843 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9846 if (Extract->getValueType(0) != MVT::i32)
9848 if (!Extract->hasOneUse())
9850 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
9851 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
9853 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
9856 // Record which element was extracted.
9857 ExtractedElements |=
9858 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
9860 Uses.push_back(Extract);
9863 // If not all the elements were used, this may not be worthwhile.
9864 if (ExtractedElements != 15)
9867 // Ok, we've now decided to do the transformation.
9868 DebugLoc dl = InputVector.getDebugLoc();
9870 // Store the value to a temporary stack slot.
9871 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
9872 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL,
9873 0, false, false, 0);
9875 // Replace each use (extract) with a load of the appropriate element.
9876 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
9877 UE = Uses.end(); UI != UE; ++UI) {
9878 SDNode *Extract = *UI;
9880 // Compute the element's address.
9881 SDValue Idx = Extract->getOperand(1);
9883 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
9884 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
9885 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
9887 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
9888 OffsetVal, StackPtr);
9891 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
9892 ScalarAddr, NULL, 0, false, false, 0);
9894 // Replace the exact with the load.
9895 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
9898 // The replacement was made in place; don't return anything.
9902 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
9903 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
9904 const X86Subtarget *Subtarget) {
9905 DebugLoc DL = N->getDebugLoc();
9906 SDValue Cond = N->getOperand(0);
9907 // Get the LHS/RHS of the select.
9908 SDValue LHS = N->getOperand(1);
9909 SDValue RHS = N->getOperand(2);
9911 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
9912 // instructions match the semantics of the common C idiom x<y?x:y but not
9913 // x<=y?x:y, because of how they handle negative zero (which can be
9914 // ignored in unsafe-math mode).
9915 if (Subtarget->hasSSE2() &&
9916 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
9917 Cond.getOpcode() == ISD::SETCC) {
9918 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
9920 unsigned Opcode = 0;
9921 // Check for x CC y ? x : y.
9922 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
9923 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
9927 // Converting this to a min would handle NaNs incorrectly, and swapping
9928 // the operands would cause it to handle comparisons between positive
9929 // and negative zero incorrectly.
9930 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
9931 if (!UnsafeFPMath &&
9932 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9934 std::swap(LHS, RHS);
9936 Opcode = X86ISD::FMIN;
9939 // Converting this to a min would handle comparisons between positive
9940 // and negative zero incorrectly.
9941 if (!UnsafeFPMath &&
9942 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
9944 Opcode = X86ISD::FMIN;
9947 // Converting this to a min would handle both negative zeros and NaNs
9948 // incorrectly, but we can swap the operands to fix both.
9949 std::swap(LHS, RHS);
9953 Opcode = X86ISD::FMIN;
9957 // Converting this to a max would handle comparisons between positive
9958 // and negative zero incorrectly.
9959 if (!UnsafeFPMath &&
9960 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
9962 Opcode = X86ISD::FMAX;
9965 // Converting this to a max would handle NaNs incorrectly, and swapping
9966 // the operands would cause it to handle comparisons between positive
9967 // and negative zero incorrectly.
9968 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
9969 if (!UnsafeFPMath &&
9970 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9972 std::swap(LHS, RHS);
9974 Opcode = X86ISD::FMAX;
9977 // Converting this to a max would handle both negative zeros and NaNs
9978 // incorrectly, but we can swap the operands to fix both.
9979 std::swap(LHS, RHS);
9983 Opcode = X86ISD::FMAX;
9986 // Check for x CC y ? y : x -- a min/max with reversed arms.
9987 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
9988 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
9992 // Converting this to a min would handle comparisons between positive
9993 // and negative zero incorrectly, and swapping the operands would
9994 // cause it to handle NaNs incorrectly.
9995 if (!UnsafeFPMath &&
9996 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
9997 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
9999 std::swap(LHS, RHS);
10001 Opcode = X86ISD::FMIN;
10004 // Converting this to a min would handle NaNs incorrectly.
10005 if (!UnsafeFPMath &&
10006 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
10008 Opcode = X86ISD::FMIN;
10011 // Converting this to a min would handle both negative zeros and NaNs
10012 // incorrectly, but we can swap the operands to fix both.
10013 std::swap(LHS, RHS);
10017 Opcode = X86ISD::FMIN;
10021 // Converting this to a max would handle NaNs incorrectly.
10022 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10024 Opcode = X86ISD::FMAX;
10027 // Converting this to a max would handle comparisons between positive
10028 // and negative zero incorrectly, and swapping the operands would
10029 // cause it to handle NaNs incorrectly.
10030 if (!UnsafeFPMath &&
10031 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
10032 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10034 std::swap(LHS, RHS);
10036 Opcode = X86ISD::FMAX;
10039 // Converting this to a max would handle both negative zeros and NaNs
10040 // incorrectly, but we can swap the operands to fix both.
10041 std::swap(LHS, RHS);
10045 Opcode = X86ISD::FMAX;
10051 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
10054 // If this is a select between two integer constants, try to do some
10056 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
10057 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
10058 // Don't do this for crazy integer types.
10059 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
10060 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
10061 // so that TrueC (the true value) is larger than FalseC.
10062 bool NeedsCondInvert = false;
10064 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
10065 // Efficiently invertible.
10066 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
10067 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
10068 isa<ConstantSDNode>(Cond.getOperand(1))))) {
10069 NeedsCondInvert = true;
10070 std::swap(TrueC, FalseC);
10073 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
10074 if (FalseC->getAPIntValue() == 0 &&
10075 TrueC->getAPIntValue().isPowerOf2()) {
10076 if (NeedsCondInvert) // Invert the condition if needed.
10077 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10078 DAG.getConstant(1, Cond.getValueType()));
10080 // Zero extend the condition if needed.
10081 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
10083 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10084 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
10085 DAG.getConstant(ShAmt, MVT::i8));
10088 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
10089 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10090 if (NeedsCondInvert) // Invert the condition if needed.
10091 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10092 DAG.getConstant(1, Cond.getValueType()));
10094 // Zero extend the condition if needed.
10095 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10096 FalseC->getValueType(0), Cond);
10097 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10098 SDValue(FalseC, 0));
10101 // Optimize cases that will turn into an LEA instruction. This requires
10102 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10103 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10104 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10105 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10107 bool isFastMultiplier = false;
10109 switch ((unsigned char)Diff) {
10111 case 1: // result = add base, cond
10112 case 2: // result = lea base( , cond*2)
10113 case 3: // result = lea base(cond, cond*2)
10114 case 4: // result = lea base( , cond*4)
10115 case 5: // result = lea base(cond, cond*4)
10116 case 8: // result = lea base( , cond*8)
10117 case 9: // result = lea base(cond, cond*8)
10118 isFastMultiplier = true;
10123 if (isFastMultiplier) {
10124 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10125 if (NeedsCondInvert) // Invert the condition if needed.
10126 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10127 DAG.getConstant(1, Cond.getValueType()));
10129 // Zero extend the condition if needed.
10130 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10132 // Scale the condition by the difference.
10134 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10135 DAG.getConstant(Diff, Cond.getValueType()));
10137 // Add the base if non-zero.
10138 if (FalseC->getAPIntValue() != 0)
10139 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10140 SDValue(FalseC, 0));
10150 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
10151 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
10152 TargetLowering::DAGCombinerInfo &DCI) {
10153 DebugLoc DL = N->getDebugLoc();
10155 // If the flag operand isn't dead, don't touch this CMOV.
10156 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
10159 // If this is a select between two integer constants, try to do some
10160 // optimizations. Note that the operands are ordered the opposite of SELECT
10162 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
10163 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10164 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
10165 // larger than FalseC (the false value).
10166 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
10168 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
10169 CC = X86::GetOppositeBranchCondition(CC);
10170 std::swap(TrueC, FalseC);
10173 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
10174 // This is efficient for any integer data type (including i8/i16) and
10176 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
10177 SDValue Cond = N->getOperand(3);
10178 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10179 DAG.getConstant(CC, MVT::i8), Cond);
10181 // Zero extend the condition if needed.
10182 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
10184 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10185 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
10186 DAG.getConstant(ShAmt, MVT::i8));
10187 if (N->getNumValues() == 2) // Dead flag value?
10188 return DCI.CombineTo(N, Cond, SDValue());
10192 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
10193 // for any integer data type, including i8/i16.
10194 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10195 SDValue Cond = N->getOperand(3);
10196 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10197 DAG.getConstant(CC, MVT::i8), Cond);
10199 // Zero extend the condition if needed.
10200 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10201 FalseC->getValueType(0), Cond);
10202 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10203 SDValue(FalseC, 0));
10205 if (N->getNumValues() == 2) // Dead flag value?
10206 return DCI.CombineTo(N, Cond, SDValue());
10210 // Optimize cases that will turn into an LEA instruction. This requires
10211 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10212 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10213 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10214 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10216 bool isFastMultiplier = false;
10218 switch ((unsigned char)Diff) {
10220 case 1: // result = add base, cond
10221 case 2: // result = lea base( , cond*2)
10222 case 3: // result = lea base(cond, cond*2)
10223 case 4: // result = lea base( , cond*4)
10224 case 5: // result = lea base(cond, cond*4)
10225 case 8: // result = lea base( , cond*8)
10226 case 9: // result = lea base(cond, cond*8)
10227 isFastMultiplier = true;
10232 if (isFastMultiplier) {
10233 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10234 SDValue Cond = N->getOperand(3);
10235 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10236 DAG.getConstant(CC, MVT::i8), Cond);
10237 // Zero extend the condition if needed.
10238 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10240 // Scale the condition by the difference.
10242 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10243 DAG.getConstant(Diff, Cond.getValueType()));
10245 // Add the base if non-zero.
10246 if (FalseC->getAPIntValue() != 0)
10247 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10248 SDValue(FalseC, 0));
10249 if (N->getNumValues() == 2) // Dead flag value?
10250 return DCI.CombineTo(N, Cond, SDValue());
10260 /// PerformMulCombine - Optimize a single multiply with constant into two
10261 /// in order to implement it with two cheaper instructions, e.g.
10262 /// LEA + SHL, LEA + LEA.
10263 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
10264 TargetLowering::DAGCombinerInfo &DCI) {
10265 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
10268 EVT VT = N->getValueType(0);
10269 if (VT != MVT::i64)
10272 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
10275 uint64_t MulAmt = C->getZExtValue();
10276 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
10279 uint64_t MulAmt1 = 0;
10280 uint64_t MulAmt2 = 0;
10281 if ((MulAmt % 9) == 0) {
10283 MulAmt2 = MulAmt / 9;
10284 } else if ((MulAmt % 5) == 0) {
10286 MulAmt2 = MulAmt / 5;
10287 } else if ((MulAmt % 3) == 0) {
10289 MulAmt2 = MulAmt / 3;
10292 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
10293 DebugLoc DL = N->getDebugLoc();
10295 if (isPowerOf2_64(MulAmt2) &&
10296 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
10297 // If second multiplifer is pow2, issue it first. We want the multiply by
10298 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
10300 std::swap(MulAmt1, MulAmt2);
10303 if (isPowerOf2_64(MulAmt1))
10304 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
10305 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
10307 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
10308 DAG.getConstant(MulAmt1, VT));
10310 if (isPowerOf2_64(MulAmt2))
10311 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
10312 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
10314 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
10315 DAG.getConstant(MulAmt2, VT));
10317 // Do not add new nodes to DAG combiner worklist.
10318 DCI.CombineTo(N, NewMul, false);
10323 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
10324 SDValue N0 = N->getOperand(0);
10325 SDValue N1 = N->getOperand(1);
10326 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
10327 EVT VT = N0.getValueType();
10329 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
10330 // since the result of setcc_c is all zero's or all ones.
10331 if (N1C && N0.getOpcode() == ISD::AND &&
10332 N0.getOperand(1).getOpcode() == ISD::Constant) {
10333 SDValue N00 = N0.getOperand(0);
10334 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
10335 ((N00.getOpcode() == ISD::ANY_EXTEND ||
10336 N00.getOpcode() == ISD::ZERO_EXTEND) &&
10337 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
10338 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
10339 APInt ShAmt = N1C->getAPIntValue();
10340 Mask = Mask.shl(ShAmt);
10342 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
10343 N00, DAG.getConstant(Mask, VT));
10350 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
10352 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
10353 const X86Subtarget *Subtarget) {
10354 EVT VT = N->getValueType(0);
10355 if (!VT.isVector() && VT.isInteger() &&
10356 N->getOpcode() == ISD::SHL)
10357 return PerformSHLCombine(N, DAG);
10359 // On X86 with SSE2 support, we can transform this to a vector shift if
10360 // all elements are shifted by the same amount. We can't do this in legalize
10361 // because the a constant vector is typically transformed to a constant pool
10362 // so we have no knowledge of the shift amount.
10363 if (!Subtarget->hasSSE2())
10366 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
10369 SDValue ShAmtOp = N->getOperand(1);
10370 EVT EltVT = VT.getVectorElementType();
10371 DebugLoc DL = N->getDebugLoc();
10372 SDValue BaseShAmt = SDValue();
10373 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
10374 unsigned NumElts = VT.getVectorNumElements();
10376 for (; i != NumElts; ++i) {
10377 SDValue Arg = ShAmtOp.getOperand(i);
10378 if (Arg.getOpcode() == ISD::UNDEF) continue;
10382 for (; i != NumElts; ++i) {
10383 SDValue Arg = ShAmtOp.getOperand(i);
10384 if (Arg.getOpcode() == ISD::UNDEF) continue;
10385 if (Arg != BaseShAmt) {
10389 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
10390 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
10391 SDValue InVec = ShAmtOp.getOperand(0);
10392 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
10393 unsigned NumElts = InVec.getValueType().getVectorNumElements();
10395 for (; i != NumElts; ++i) {
10396 SDValue Arg = InVec.getOperand(i);
10397 if (Arg.getOpcode() == ISD::UNDEF) continue;
10401 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
10402 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
10403 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
10404 if (C->getZExtValue() == SplatIdx)
10405 BaseShAmt = InVec.getOperand(1);
10408 if (BaseShAmt.getNode() == 0)
10409 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
10410 DAG.getIntPtrConstant(0));
10414 // The shift amount is an i32.
10415 if (EltVT.bitsGT(MVT::i32))
10416 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
10417 else if (EltVT.bitsLT(MVT::i32))
10418 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
10420 // The shift amount is identical so we can do a vector shift.
10421 SDValue ValOp = N->getOperand(0);
10422 switch (N->getOpcode()) {
10424 llvm_unreachable("Unknown shift opcode!");
10427 if (VT == MVT::v2i64)
10428 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10429 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10431 if (VT == MVT::v4i32)
10432 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10433 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10435 if (VT == MVT::v8i16)
10436 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10437 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10441 if (VT == MVT::v4i32)
10442 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10443 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
10445 if (VT == MVT::v8i16)
10446 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10447 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
10451 if (VT == MVT::v2i64)
10452 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10453 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10455 if (VT == MVT::v4i32)
10456 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10457 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
10459 if (VT == MVT::v8i16)
10460 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10461 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10468 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
10469 TargetLowering::DAGCombinerInfo &DCI,
10470 const X86Subtarget *Subtarget) {
10471 if (DCI.isBeforeLegalizeOps())
10474 EVT VT = N->getValueType(0);
10475 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
10478 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
10479 SDValue N0 = N->getOperand(0);
10480 SDValue N1 = N->getOperand(1);
10481 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
10483 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
10485 if (!N0.hasOneUse() || !N1.hasOneUse())
10488 SDValue ShAmt0 = N0.getOperand(1);
10489 if (ShAmt0.getValueType() != MVT::i8)
10491 SDValue ShAmt1 = N1.getOperand(1);
10492 if (ShAmt1.getValueType() != MVT::i8)
10494 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
10495 ShAmt0 = ShAmt0.getOperand(0);
10496 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
10497 ShAmt1 = ShAmt1.getOperand(0);
10499 DebugLoc DL = N->getDebugLoc();
10500 unsigned Opc = X86ISD::SHLD;
10501 SDValue Op0 = N0.getOperand(0);
10502 SDValue Op1 = N1.getOperand(0);
10503 if (ShAmt0.getOpcode() == ISD::SUB) {
10504 Opc = X86ISD::SHRD;
10505 std::swap(Op0, Op1);
10506 std::swap(ShAmt0, ShAmt1);
10509 unsigned Bits = VT.getSizeInBits();
10510 if (ShAmt1.getOpcode() == ISD::SUB) {
10511 SDValue Sum = ShAmt1.getOperand(0);
10512 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
10513 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
10514 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
10515 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
10516 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
10517 return DAG.getNode(Opc, DL, VT,
10519 DAG.getNode(ISD::TRUNCATE, DL,
10522 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
10523 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
10525 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
10526 return DAG.getNode(Opc, DL, VT,
10527 N0.getOperand(0), N1.getOperand(0),
10528 DAG.getNode(ISD::TRUNCATE, DL,
10535 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
10536 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
10537 const X86Subtarget *Subtarget) {
10538 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
10539 // the FP state in cases where an emms may be missing.
10540 // A preferable solution to the general problem is to figure out the right
10541 // places to insert EMMS. This qualifies as a quick hack.
10543 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
10544 StoreSDNode *St = cast<StoreSDNode>(N);
10545 EVT VT = St->getValue().getValueType();
10546 if (VT.getSizeInBits() != 64)
10549 const Function *F = DAG.getMachineFunction().getFunction();
10550 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
10551 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
10552 && Subtarget->hasSSE2();
10553 if ((VT.isVector() ||
10554 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
10555 isa<LoadSDNode>(St->getValue()) &&
10556 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
10557 St->getChain().hasOneUse() && !St->isVolatile()) {
10558 SDNode* LdVal = St->getValue().getNode();
10559 LoadSDNode *Ld = 0;
10560 int TokenFactorIndex = -1;
10561 SmallVector<SDValue, 8> Ops;
10562 SDNode* ChainVal = St->getChain().getNode();
10563 // Must be a store of a load. We currently handle two cases: the load
10564 // is a direct child, and it's under an intervening TokenFactor. It is
10565 // possible to dig deeper under nested TokenFactors.
10566 if (ChainVal == LdVal)
10567 Ld = cast<LoadSDNode>(St->getChain());
10568 else if (St->getValue().hasOneUse() &&
10569 ChainVal->getOpcode() == ISD::TokenFactor) {
10570 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
10571 if (ChainVal->getOperand(i).getNode() == LdVal) {
10572 TokenFactorIndex = i;
10573 Ld = cast<LoadSDNode>(St->getValue());
10575 Ops.push_back(ChainVal->getOperand(i));
10579 if (!Ld || !ISD::isNormalLoad(Ld))
10582 // If this is not the MMX case, i.e. we are just turning i64 load/store
10583 // into f64 load/store, avoid the transformation if there are multiple
10584 // uses of the loaded value.
10585 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
10588 DebugLoc LdDL = Ld->getDebugLoc();
10589 DebugLoc StDL = N->getDebugLoc();
10590 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
10591 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
10593 if (Subtarget->is64Bit() || F64IsLegal) {
10594 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
10595 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
10596 Ld->getBasePtr(), Ld->getSrcValue(),
10597 Ld->getSrcValueOffset(), Ld->isVolatile(),
10598 Ld->isNonTemporal(), Ld->getAlignment());
10599 SDValue NewChain = NewLd.getValue(1);
10600 if (TokenFactorIndex != -1) {
10601 Ops.push_back(NewChain);
10602 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
10605 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
10606 St->getSrcValue(), St->getSrcValueOffset(),
10607 St->isVolatile(), St->isNonTemporal(),
10608 St->getAlignment());
10611 // Otherwise, lower to two pairs of 32-bit loads / stores.
10612 SDValue LoAddr = Ld->getBasePtr();
10613 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
10614 DAG.getConstant(4, MVT::i32));
10616 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
10617 Ld->getSrcValue(), Ld->getSrcValueOffset(),
10618 Ld->isVolatile(), Ld->isNonTemporal(),
10619 Ld->getAlignment());
10620 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
10621 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
10622 Ld->isVolatile(), Ld->isNonTemporal(),
10623 MinAlign(Ld->getAlignment(), 4));
10625 SDValue NewChain = LoLd.getValue(1);
10626 if (TokenFactorIndex != -1) {
10627 Ops.push_back(LoLd);
10628 Ops.push_back(HiLd);
10629 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
10633 LoAddr = St->getBasePtr();
10634 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
10635 DAG.getConstant(4, MVT::i32));
10637 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
10638 St->getSrcValue(), St->getSrcValueOffset(),
10639 St->isVolatile(), St->isNonTemporal(),
10640 St->getAlignment());
10641 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
10643 St->getSrcValueOffset() + 4,
10645 St->isNonTemporal(),
10646 MinAlign(St->getAlignment(), 4));
10647 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
10652 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
10653 /// X86ISD::FXOR nodes.
10654 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
10655 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
10656 // F[X]OR(0.0, x) -> x
10657 // F[X]OR(x, 0.0) -> x
10658 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
10659 if (C->getValueAPF().isPosZero())
10660 return N->getOperand(1);
10661 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
10662 if (C->getValueAPF().isPosZero())
10663 return N->getOperand(0);
10667 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
10668 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
10669 // FAND(0.0, x) -> 0.0
10670 // FAND(x, 0.0) -> 0.0
10671 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
10672 if (C->getValueAPF().isPosZero())
10673 return N->getOperand(0);
10674 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
10675 if (C->getValueAPF().isPosZero())
10676 return N->getOperand(1);
10680 static SDValue PerformBTCombine(SDNode *N,
10682 TargetLowering::DAGCombinerInfo &DCI) {
10683 // BT ignores high bits in the bit index operand.
10684 SDValue Op1 = N->getOperand(1);
10685 if (Op1.hasOneUse()) {
10686 unsigned BitWidth = Op1.getValueSizeInBits();
10687 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
10688 APInt KnownZero, KnownOne;
10689 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
10690 !DCI.isBeforeLegalizeOps());
10691 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10692 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
10693 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
10694 DCI.CommitTargetLoweringOpt(TLO);
10699 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
10700 SDValue Op = N->getOperand(0);
10701 if (Op.getOpcode() == ISD::BIT_CONVERT)
10702 Op = Op.getOperand(0);
10703 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
10704 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
10705 VT.getVectorElementType().getSizeInBits() ==
10706 OpVT.getVectorElementType().getSizeInBits()) {
10707 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
10712 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
10713 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
10714 // (and (i32 x86isd::setcc_carry), 1)
10715 // This eliminates the zext. This transformation is necessary because
10716 // ISD::SETCC is always legalized to i8.
10717 DebugLoc dl = N->getDebugLoc();
10718 SDValue N0 = N->getOperand(0);
10719 EVT VT = N->getValueType(0);
10720 if (N0.getOpcode() == ISD::AND &&
10722 N0.getOperand(0).hasOneUse()) {
10723 SDValue N00 = N0.getOperand(0);
10724 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
10726 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
10727 if (!C || C->getZExtValue() != 1)
10729 return DAG.getNode(ISD::AND, dl, VT,
10730 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
10731 N00.getOperand(0), N00.getOperand(1)),
10732 DAG.getConstant(1, VT));
10738 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
10739 DAGCombinerInfo &DCI) const {
10740 SelectionDAG &DAG = DCI.DAG;
10741 switch (N->getOpcode()) {
10743 case ISD::EXTRACT_VECTOR_ELT:
10744 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
10745 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
10746 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
10747 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
10750 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
10751 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
10752 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
10754 case X86ISD::FOR: return PerformFORCombine(N, DAG);
10755 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
10756 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
10757 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
10758 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
10759 case X86ISD::SHUFPS: // Handle all target specific shuffles
10760 case X86ISD::SHUFPD:
10761 case X86ISD::PUNPCKHBW:
10762 case X86ISD::PUNPCKHWD:
10763 case X86ISD::PUNPCKHDQ:
10764 case X86ISD::PUNPCKHQDQ:
10765 case X86ISD::UNPCKHPS:
10766 case X86ISD::UNPCKHPD:
10767 case X86ISD::PUNPCKLBW:
10768 case X86ISD::PUNPCKLWD:
10769 case X86ISD::PUNPCKLDQ:
10770 case X86ISD::PUNPCKLQDQ:
10771 case X86ISD::UNPCKLPS:
10772 case X86ISD::UNPCKLPD:
10773 case X86ISD::MOVHLPS:
10774 case X86ISD::MOVLHPS:
10775 case X86ISD::PSHUFD:
10776 case X86ISD::PSHUFHW:
10777 case X86ISD::PSHUFLW:
10778 case X86ISD::MOVSS:
10779 case X86ISD::MOVSD:
10780 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
10786 /// isTypeDesirableForOp - Return true if the target has native support for
10787 /// the specified value type and it is 'desirable' to use the type for the
10788 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
10789 /// instruction encodings are longer and some i16 instructions are slow.
10790 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
10791 if (!isTypeLegal(VT))
10793 if (VT != MVT::i16)
10800 case ISD::SIGN_EXTEND:
10801 case ISD::ZERO_EXTEND:
10802 case ISD::ANY_EXTEND:
10815 /// IsDesirableToPromoteOp - This method query the target whether it is
10816 /// beneficial for dag combiner to promote the specified node. If true, it
10817 /// should return the desired promotion type by reference.
10818 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
10819 EVT VT = Op.getValueType();
10820 if (VT != MVT::i16)
10823 bool Promote = false;
10824 bool Commute = false;
10825 switch (Op.getOpcode()) {
10828 LoadSDNode *LD = cast<LoadSDNode>(Op);
10829 // If the non-extending load has a single use and it's not live out, then it
10830 // might be folded.
10831 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
10832 Op.hasOneUse()*/) {
10833 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
10834 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
10835 // The only case where we'd want to promote LOAD (rather then it being
10836 // promoted as an operand is when it's only use is liveout.
10837 if (UI->getOpcode() != ISD::CopyToReg)
10844 case ISD::SIGN_EXTEND:
10845 case ISD::ZERO_EXTEND:
10846 case ISD::ANY_EXTEND:
10851 SDValue N0 = Op.getOperand(0);
10852 // Look out for (store (shl (load), x)).
10853 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
10866 SDValue N0 = Op.getOperand(0);
10867 SDValue N1 = Op.getOperand(1);
10868 if (!Commute && MayFoldLoad(N1))
10870 // Avoid disabling potential load folding opportunities.
10871 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
10873 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
10883 //===----------------------------------------------------------------------===//
10884 // X86 Inline Assembly Support
10885 //===----------------------------------------------------------------------===//
10887 static bool LowerToBSwap(CallInst *CI) {
10888 // FIXME: this should verify that we are targetting a 486 or better. If not,
10889 // we will turn this bswap into something that will be lowered to logical ops
10890 // instead of emitting the bswap asm. For now, we don't support 486 or lower
10891 // so don't worry about this.
10893 // Verify this is a simple bswap.
10894 if (CI->getNumArgOperands() != 1 ||
10895 CI->getType() != CI->getArgOperand(0)->getType() ||
10896 !CI->getType()->isIntegerTy())
10899 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10900 if (!Ty || Ty->getBitWidth() % 16 != 0)
10903 // Okay, we can do this xform, do so now.
10904 const Type *Tys[] = { Ty };
10905 Module *M = CI->getParent()->getParent()->getParent();
10906 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
10908 Value *Op = CI->getArgOperand(0);
10909 Op = CallInst::Create(Int, Op, CI->getName(), CI);
10911 CI->replaceAllUsesWith(Op);
10912 CI->eraseFromParent();
10916 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
10917 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10918 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
10920 std::string AsmStr = IA->getAsmString();
10922 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
10923 SmallVector<StringRef, 4> AsmPieces;
10924 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
10926 switch (AsmPieces.size()) {
10927 default: return false;
10929 AsmStr = AsmPieces[0];
10931 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
10934 if (AsmPieces.size() == 2 &&
10935 (AsmPieces[0] == "bswap" ||
10936 AsmPieces[0] == "bswapq" ||
10937 AsmPieces[0] == "bswapl") &&
10938 (AsmPieces[1] == "$0" ||
10939 AsmPieces[1] == "${0:q}")) {
10940 // No need to check constraints, nothing other than the equivalent of
10941 // "=r,0" would be valid here.
10942 return LowerToBSwap(CI);
10944 // rorw $$8, ${0:w} --> llvm.bswap.i16
10945 if (CI->getType()->isIntegerTy(16) &&
10946 AsmPieces.size() == 3 &&
10947 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
10948 AsmPieces[1] == "$$8," &&
10949 AsmPieces[2] == "${0:w}" &&
10950 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
10952 const std::string &Constraints = IA->getConstraintString();
10953 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
10954 std::sort(AsmPieces.begin(), AsmPieces.end());
10955 if (AsmPieces.size() == 4 &&
10956 AsmPieces[0] == "~{cc}" &&
10957 AsmPieces[1] == "~{dirflag}" &&
10958 AsmPieces[2] == "~{flags}" &&
10959 AsmPieces[3] == "~{fpsr}") {
10960 return LowerToBSwap(CI);
10965 if (CI->getType()->isIntegerTy(64) &&
10966 Constraints.size() >= 2 &&
10967 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
10968 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
10969 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
10970 SmallVector<StringRef, 4> Words;
10971 SplitString(AsmPieces[0], Words, " \t");
10972 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
10974 SplitString(AsmPieces[1], Words, " \t");
10975 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
10977 SplitString(AsmPieces[2], Words, " \t,");
10978 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
10979 Words[2] == "%edx") {
10980 return LowerToBSwap(CI);
10992 /// getConstraintType - Given a constraint letter, return the type of
10993 /// constraint it is for this target.
10994 X86TargetLowering::ConstraintType
10995 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
10996 if (Constraint.size() == 1) {
10997 switch (Constraint[0]) {
11009 return C_RegisterClass;
11017 return TargetLowering::getConstraintType(Constraint);
11020 /// LowerXConstraint - try to replace an X constraint, which matches anything,
11021 /// with another that has more specific requirements based on the type of the
11022 /// corresponding operand.
11023 const char *X86TargetLowering::
11024 LowerXConstraint(EVT ConstraintVT) const {
11025 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
11026 // 'f' like normal targets.
11027 if (ConstraintVT.isFloatingPoint()) {
11028 if (Subtarget->hasSSE2())
11030 if (Subtarget->hasSSE1())
11034 return TargetLowering::LowerXConstraint(ConstraintVT);
11037 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
11038 /// vector. If it is invalid, don't add anything to Ops.
11039 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
11041 std::vector<SDValue>&Ops,
11042 SelectionDAG &DAG) const {
11043 SDValue Result(0, 0);
11045 switch (Constraint) {
11048 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11049 if (C->getZExtValue() <= 31) {
11050 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11056 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11057 if (C->getZExtValue() <= 63) {
11058 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11064 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11065 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
11066 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11072 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11073 if (C->getZExtValue() <= 255) {
11074 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11080 // 32-bit signed value
11081 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11082 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
11083 C->getSExtValue())) {
11084 // Widen to 64 bits here to get it sign extended.
11085 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
11088 // FIXME gcc accepts some relocatable values here too, but only in certain
11089 // memory models; it's complicated.
11094 // 32-bit unsigned value
11095 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11096 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
11097 C->getZExtValue())) {
11098 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11102 // FIXME gcc accepts some relocatable values here too, but only in certain
11103 // memory models; it's complicated.
11107 // Literal immediates are always ok.
11108 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
11109 // Widen to 64 bits here to get it sign extended.
11110 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
11114 // In any sort of PIC mode addresses need to be computed at runtime by
11115 // adding in a register or some sort of table lookup. These can't
11116 // be used as immediates.
11117 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
11120 // If we are in non-pic codegen mode, we allow the address of a global (with
11121 // an optional displacement) to be used with 'i'.
11122 GlobalAddressSDNode *GA = 0;
11123 int64_t Offset = 0;
11125 // Match either (GA), (GA+C), (GA+C1+C2), etc.
11127 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
11128 Offset += GA->getOffset();
11130 } else if (Op.getOpcode() == ISD::ADD) {
11131 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
11132 Offset += C->getZExtValue();
11133 Op = Op.getOperand(0);
11136 } else if (Op.getOpcode() == ISD::SUB) {
11137 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
11138 Offset += -C->getZExtValue();
11139 Op = Op.getOperand(0);
11144 // Otherwise, this isn't something we can handle, reject it.
11148 const GlobalValue *GV = GA->getGlobal();
11149 // If we require an extra load to get this address, as in PIC mode, we
11150 // can't accept it.
11151 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
11152 getTargetMachine())))
11155 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
11156 GA->getValueType(0), Offset);
11161 if (Result.getNode()) {
11162 Ops.push_back(Result);
11165 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11168 std::vector<unsigned> X86TargetLowering::
11169 getRegClassForInlineAsmConstraint(const std::string &Constraint,
11171 if (Constraint.size() == 1) {
11172 // FIXME: not handling fp-stack yet!
11173 switch (Constraint[0]) { // GCC X86 Constraint Letters
11174 default: break; // Unknown constraint letter
11175 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
11176 if (Subtarget->is64Bit()) {
11177 if (VT == MVT::i32)
11178 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
11179 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
11180 X86::R10D,X86::R11D,X86::R12D,
11181 X86::R13D,X86::R14D,X86::R15D,
11182 X86::EBP, X86::ESP, 0);
11183 else if (VT == MVT::i16)
11184 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
11185 X86::SI, X86::DI, X86::R8W,X86::R9W,
11186 X86::R10W,X86::R11W,X86::R12W,
11187 X86::R13W,X86::R14W,X86::R15W,
11188 X86::BP, X86::SP, 0);
11189 else if (VT == MVT::i8)
11190 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
11191 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
11192 X86::R10B,X86::R11B,X86::R12B,
11193 X86::R13B,X86::R14B,X86::R15B,
11194 X86::BPL, X86::SPL, 0);
11196 else if (VT == MVT::i64)
11197 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
11198 X86::RSI, X86::RDI, X86::R8, X86::R9,
11199 X86::R10, X86::R11, X86::R12,
11200 X86::R13, X86::R14, X86::R15,
11201 X86::RBP, X86::RSP, 0);
11205 // 32-bit fallthrough
11206 case 'Q': // Q_REGS
11207 if (VT == MVT::i32)
11208 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
11209 else if (VT == MVT::i16)
11210 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
11211 else if (VT == MVT::i8)
11212 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
11213 else if (VT == MVT::i64)
11214 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
11219 return std::vector<unsigned>();
11222 std::pair<unsigned, const TargetRegisterClass*>
11223 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
11225 // First, see if this is a constraint that directly corresponds to an LLVM
11227 if (Constraint.size() == 1) {
11228 // GCC Constraint Letters
11229 switch (Constraint[0]) {
11231 case 'r': // GENERAL_REGS
11232 case 'l': // INDEX_REGS
11234 return std::make_pair(0U, X86::GR8RegisterClass);
11235 if (VT == MVT::i16)
11236 return std::make_pair(0U, X86::GR16RegisterClass);
11237 if (VT == MVT::i32 || !Subtarget->is64Bit())
11238 return std::make_pair(0U, X86::GR32RegisterClass);
11239 return std::make_pair(0U, X86::GR64RegisterClass);
11240 case 'R': // LEGACY_REGS
11242 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
11243 if (VT == MVT::i16)
11244 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
11245 if (VT == MVT::i32 || !Subtarget->is64Bit())
11246 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
11247 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
11248 case 'f': // FP Stack registers.
11249 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
11250 // value to the correct fpstack register class.
11251 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
11252 return std::make_pair(0U, X86::RFP32RegisterClass);
11253 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
11254 return std::make_pair(0U, X86::RFP64RegisterClass);
11255 return std::make_pair(0U, X86::RFP80RegisterClass);
11256 case 'y': // MMX_REGS if MMX allowed.
11257 if (!Subtarget->hasMMX()) break;
11258 return std::make_pair(0U, X86::VR64RegisterClass);
11259 case 'Y': // SSE_REGS if SSE2 allowed
11260 if (!Subtarget->hasSSE2()) break;
11262 case 'x': // SSE_REGS if SSE1 allowed
11263 if (!Subtarget->hasSSE1()) break;
11265 switch (VT.getSimpleVT().SimpleTy) {
11267 // Scalar SSE types.
11270 return std::make_pair(0U, X86::FR32RegisterClass);
11273 return std::make_pair(0U, X86::FR64RegisterClass);
11281 return std::make_pair(0U, X86::VR128RegisterClass);
11287 // Use the default implementation in TargetLowering to convert the register
11288 // constraint into a member of a register class.
11289 std::pair<unsigned, const TargetRegisterClass*> Res;
11290 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
11292 // Not found as a standard register?
11293 if (Res.second == 0) {
11294 // Map st(0) -> st(7) -> ST0
11295 if (Constraint.size() == 7 && Constraint[0] == '{' &&
11296 tolower(Constraint[1]) == 's' &&
11297 tolower(Constraint[2]) == 't' &&
11298 Constraint[3] == '(' &&
11299 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
11300 Constraint[5] == ')' &&
11301 Constraint[6] == '}') {
11303 Res.first = X86::ST0+Constraint[4]-'0';
11304 Res.second = X86::RFP80RegisterClass;
11308 // GCC allows "st(0)" to be called just plain "st".
11309 if (StringRef("{st}").equals_lower(Constraint)) {
11310 Res.first = X86::ST0;
11311 Res.second = X86::RFP80RegisterClass;
11316 if (StringRef("{flags}").equals_lower(Constraint)) {
11317 Res.first = X86::EFLAGS;
11318 Res.second = X86::CCRRegisterClass;
11322 // 'A' means EAX + EDX.
11323 if (Constraint == "A") {
11324 Res.first = X86::EAX;
11325 Res.second = X86::GR32_ADRegisterClass;
11331 // Otherwise, check to see if this is a register class of the wrong value
11332 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
11333 // turn into {ax},{dx}.
11334 if (Res.second->hasType(VT))
11335 return Res; // Correct type already, nothing to do.
11337 // All of the single-register GCC register classes map their values onto
11338 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
11339 // really want an 8-bit or 32-bit register, map to the appropriate register
11340 // class and return the appropriate register.
11341 if (Res.second == X86::GR16RegisterClass) {
11342 if (VT == MVT::i8) {
11343 unsigned DestReg = 0;
11344 switch (Res.first) {
11346 case X86::AX: DestReg = X86::AL; break;
11347 case X86::DX: DestReg = X86::DL; break;
11348 case X86::CX: DestReg = X86::CL; break;
11349 case X86::BX: DestReg = X86::BL; break;
11352 Res.first = DestReg;
11353 Res.second = X86::GR8RegisterClass;
11355 } else if (VT == MVT::i32) {
11356 unsigned DestReg = 0;
11357 switch (Res.first) {
11359 case X86::AX: DestReg = X86::EAX; break;
11360 case X86::DX: DestReg = X86::EDX; break;
11361 case X86::CX: DestReg = X86::ECX; break;
11362 case X86::BX: DestReg = X86::EBX; break;
11363 case X86::SI: DestReg = X86::ESI; break;
11364 case X86::DI: DestReg = X86::EDI; break;
11365 case X86::BP: DestReg = X86::EBP; break;
11366 case X86::SP: DestReg = X86::ESP; break;
11369 Res.first = DestReg;
11370 Res.second = X86::GR32RegisterClass;
11372 } else if (VT == MVT::i64) {
11373 unsigned DestReg = 0;
11374 switch (Res.first) {
11376 case X86::AX: DestReg = X86::RAX; break;
11377 case X86::DX: DestReg = X86::RDX; break;
11378 case X86::CX: DestReg = X86::RCX; break;
11379 case X86::BX: DestReg = X86::RBX; break;
11380 case X86::SI: DestReg = X86::RSI; break;
11381 case X86::DI: DestReg = X86::RDI; break;
11382 case X86::BP: DestReg = X86::RBP; break;
11383 case X86::SP: DestReg = X86::RSP; break;
11386 Res.first = DestReg;
11387 Res.second = X86::GR64RegisterClass;
11390 } else if (Res.second == X86::FR32RegisterClass ||
11391 Res.second == X86::FR64RegisterClass ||
11392 Res.second == X86::VR128RegisterClass) {
11393 // Handle references to XMM physical registers that got mapped into the
11394 // wrong class. This can happen with constraints like {xmm0} where the
11395 // target independent register mapper will just pick the first match it can
11396 // find, ignoring the required type.
11397 if (VT == MVT::f32)
11398 Res.second = X86::FR32RegisterClass;
11399 else if (VT == MVT::f64)
11400 Res.second = X86::FR64RegisterClass;
11401 else if (X86::VR128RegisterClass->hasType(VT))
11402 Res.second = X86::VR128RegisterClass;