1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86ShuffleDecodeConstantPool.h"
22 #include "X86TargetMachine.h"
23 #include "X86TargetObjectFile.h"
24 #include "llvm/ADT/SmallBitVector.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringSwitch.h"
29 #include "llvm/Analysis/EHPersonalities.h"
30 #include "llvm/CodeGen/IntrinsicLowering.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/CallSite.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalAlias.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/Instructions.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/MC/MCAsmInfo.h"
48 #include "llvm/MC/MCContext.h"
49 #include "llvm/MC/MCExpr.h"
50 #include "llvm/MC/MCSymbol.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/MathExtras.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "X86IntrinsicsInfo.h"
62 #define DEBUG_TYPE "x86-isel"
64 STATISTIC(NumTailCalls, "Number of tail calls");
66 static cl::opt<bool> ExperimentalVectorWideningLegalization(
67 "x86-experimental-vector-widening-legalization", cl::init(false),
68 cl::desc("Enable an experimental vector type legalization through widening "
69 "rather than promotion."),
72 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
73 const X86Subtarget &STI)
74 : TargetLowering(TM), Subtarget(&STI) {
75 X86ScalarSSEf64 = Subtarget->hasSSE2();
76 X86ScalarSSEf32 = Subtarget->hasSSE1();
77 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
79 // Set up the TargetLowering object.
81 // X86 is weird. It always uses i8 for shift amounts and setcc results.
82 setBooleanContents(ZeroOrOneBooleanContent);
83 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
84 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
86 // For 64-bit, since we have so many registers, use the ILP scheduler.
87 // For 32-bit, use the register pressure specific scheduling.
88 // For Atom, always use ILP scheduling.
89 if (Subtarget->isAtom())
90 setSchedulingPreference(Sched::ILP);
91 else if (Subtarget->is64Bit())
92 setSchedulingPreference(Sched::ILP);
94 setSchedulingPreference(Sched::RegPressure);
95 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
96 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
98 // Bypass expensive divides on Atom when compiling with O2.
99 if (TM.getOptLevel() >= CodeGenOpt::Default) {
100 if (Subtarget->hasSlowDivide32())
101 addBypassSlowDiv(32, 8);
102 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
103 addBypassSlowDiv(64, 16);
106 if (Subtarget->isTargetKnownWindowsMSVC()) {
107 // Setup Windows compiler runtime calls.
108 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
109 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
110 setLibcallName(RTLIB::SREM_I64, "_allrem");
111 setLibcallName(RTLIB::UREM_I64, "_aullrem");
112 setLibcallName(RTLIB::MUL_I64, "_allmul");
113 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
117 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
120 if (Subtarget->isTargetDarwin()) {
121 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
122 setUseUnderscoreSetJmp(false);
123 setUseUnderscoreLongJmp(false);
124 } else if (Subtarget->isTargetWindowsGNU()) {
125 // MS runtime is weird: it exports _setjmp, but longjmp!
126 setUseUnderscoreSetJmp(true);
127 setUseUnderscoreLongJmp(false);
129 setUseUnderscoreSetJmp(true);
130 setUseUnderscoreLongJmp(true);
133 // Set up the register classes.
134 addRegisterClass(MVT::i8, &X86::GR8RegClass);
135 addRegisterClass(MVT::i16, &X86::GR16RegClass);
136 addRegisterClass(MVT::i32, &X86::GR32RegClass);
137 if (Subtarget->is64Bit())
138 addRegisterClass(MVT::i64, &X86::GR64RegClass);
140 for (MVT VT : MVT::integer_valuetypes())
141 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
143 // We don't accept any truncstore of integer registers.
144 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
146 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
147 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
148 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
149 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
151 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
153 // SETOEQ and SETUNE require checking two conditions.
154 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
156 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
159 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
161 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
163 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
165 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
167 if (Subtarget->is64Bit()) {
168 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
169 // f32/f64 are legal, f80 is custom.
170 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
173 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
174 } else if (!Subtarget->useSoftFloat()) {
175 // We have an algorithm for SSE2->double, and we turn this into a
176 // 64-bit FILD followed by conditional FADD for other targets.
177 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
178 // We have an algorithm for SSE2, and we turn this into a 64-bit
179 // FILD or VCVTUSI2SS/SD for other targets.
180 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
183 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
185 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
186 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
188 if (!Subtarget->useSoftFloat()) {
189 // SSE has no i16 to fp conversion, only i32
190 if (X86ScalarSSEf32) {
191 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
192 // f32 and f64 cases are Legal, f80 case is not
193 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
196 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
200 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
203 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
205 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
206 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
208 if (!Subtarget->useSoftFloat()) {
209 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
210 // are Legal, f80 is custom lowered.
211 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
214 if (X86ScalarSSEf32) {
215 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
216 // f32 and f64 cases are Legal, f80 case is not
217 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
220 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
225 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
228 // Handle FP_TO_UINT by promoting the destination to a larger signed
230 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
234 if (Subtarget->is64Bit()) {
235 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
236 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
237 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
238 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
241 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
243 } else if (!Subtarget->useSoftFloat()) {
244 // Since AVX is a superset of SSE3, only check for SSE here.
245 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
246 // Expand FP_TO_UINT into a select.
247 // FIXME: We would like to use a Custom expander here eventually to do
248 // the optimal thing for SSE vs. the default expansion in the legalizer.
249 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
251 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
252 // With SSE3 we can use fisttpll to convert to a signed i64; without
253 // SSE, we're stuck with a fistpll.
254 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
256 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
259 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
260 if (!X86ScalarSSEf64) {
261 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
262 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
263 if (Subtarget->is64Bit()) {
264 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
265 // Without SSE, i64->f64 goes through memory.
266 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
270 // Scalar integer divide and remainder are lowered to use operations that
271 // produce two results, to match the available instructions. This exposes
272 // the two-result form to trivial CSE, which is able to combine x/y and x%y
273 // into a single instruction.
275 // Scalar integer multiply-high is also lowered to use two-result
276 // operations, to match the available instructions. However, plain multiply
277 // (low) operations are left as Legal, as there are single-result
278 // instructions for this in x86. Using the two-result multiply instructions
279 // when both high and low results are needed must be arranged by dagcombine.
280 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
281 setOperationAction(ISD::MULHS, VT, Expand);
282 setOperationAction(ISD::MULHU, VT, Expand);
283 setOperationAction(ISD::SDIV, VT, Expand);
284 setOperationAction(ISD::UDIV, VT, Expand);
285 setOperationAction(ISD::SREM, VT, Expand);
286 setOperationAction(ISD::UREM, VT, Expand);
288 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
289 setOperationAction(ISD::ADDC, VT, Custom);
290 setOperationAction(ISD::ADDE, VT, Custom);
291 setOperationAction(ISD::SUBC, VT, Custom);
292 setOperationAction(ISD::SUBE, VT, Custom);
295 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
296 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
297 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
298 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
299 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
300 setOperationAction(ISD::BR_CC , MVT::f128, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
302 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
303 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
304 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::f128, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
312 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
313 if (Subtarget->is64Bit())
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
315 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
317 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
318 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
320 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
321 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
322 // is. We should promote the value to 64-bits to solve this.
323 // This is what the CRT headers do - `fmodf` is an inline header
324 // function casting to f64 and calling `fmod`.
325 setOperationAction(ISD::FREM , MVT::f32 , Promote);
327 setOperationAction(ISD::FREM , MVT::f32 , Expand);
330 setOperationAction(ISD::FREM , MVT::f64 , Expand);
331 setOperationAction(ISD::FREM , MVT::f80 , Expand);
332 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
334 // Promote the i8 variants and force them on up to i32 which has a shorter
336 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
337 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
339 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
340 if (Subtarget->hasBMI()) {
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
342 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
343 if (Subtarget->is64Bit())
344 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
346 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
347 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
348 if (Subtarget->is64Bit())
349 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
352 if (Subtarget->hasLZCNT()) {
353 // When promoting the i8 variants, force them to i32 for a shorter
355 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
356 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
358 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
361 if (Subtarget->is64Bit())
362 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
364 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
365 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
366 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
367 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
368 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
370 if (Subtarget->is64Bit()) {
371 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
372 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
376 // Special handling for half-precision floating point conversions.
377 // If we don't have F16C support, then lower half float conversions
378 // into library calls.
379 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
380 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
381 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
384 // There's never any support for operations beyond MVT::f32.
385 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
386 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
387 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
388 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
390 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
391 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
392 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
393 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
394 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
395 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
397 if (Subtarget->hasPOPCNT()) {
398 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
400 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
401 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
402 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
403 if (Subtarget->is64Bit())
404 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
407 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
409 if (!Subtarget->hasMOVBE())
410 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
412 // These should be promoted to a larger select which is supported.
413 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
414 // X86 wants to expand cmov itself.
415 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
416 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
417 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
418 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
419 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
420 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
421 setOperationAction(ISD::SELECT , MVT::f128 , Custom);
422 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
423 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
424 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
425 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
426 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
427 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
428 setOperationAction(ISD::SETCC , MVT::f128 , Custom);
429 setOperationAction(ISD::SETCCE , MVT::i8 , Custom);
430 setOperationAction(ISD::SETCCE , MVT::i16 , Custom);
431 setOperationAction(ISD::SETCCE , MVT::i32 , Custom);
432 if (Subtarget->is64Bit()) {
433 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
434 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
435 setOperationAction(ISD::SETCCE , MVT::i64 , Custom);
437 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
438 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
439 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
440 // support continuation, user-level threading, and etc.. As a result, no
441 // other SjLj exception interfaces are implemented and please don't build
442 // your own exception handling based on them.
443 // LLVM/Clang supports zero-cost DWARF exception handling.
444 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
445 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
448 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
449 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
450 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
451 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
452 if (Subtarget->is64Bit())
453 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
454 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
455 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
456 if (Subtarget->is64Bit()) {
457 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
458 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
459 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
460 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
461 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
463 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
464 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
465 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
466 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
467 if (Subtarget->is64Bit()) {
468 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
469 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
470 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
473 if (Subtarget->hasSSE1())
474 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
476 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
478 // Expand certain atomics
479 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
480 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
481 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
482 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
485 if (Subtarget->hasCmpxchg16b()) {
486 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
489 // FIXME - use subtarget debug flags
490 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
491 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
492 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
495 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
496 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
498 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
499 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
501 setOperationAction(ISD::TRAP, MVT::Other, Legal);
502 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
504 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
505 setOperationAction(ISD::VASTART , MVT::Other, Custom);
506 setOperationAction(ISD::VAEND , MVT::Other, Expand);
507 if (Subtarget->is64Bit()) {
508 setOperationAction(ISD::VAARG , MVT::Other, Custom);
509 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
511 // TargetInfo::CharPtrBuiltinVaList
512 setOperationAction(ISD::VAARG , MVT::Other, Expand);
513 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
516 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
517 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
519 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
521 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
522 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
523 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
525 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
526 // f32 and f64 use SSE.
527 // Set up the FP register classes.
528 addRegisterClass(MVT::f32, &X86::FR32RegClass);
529 addRegisterClass(MVT::f64, &X86::FR64RegClass);
531 // Use ANDPD to simulate FABS.
532 setOperationAction(ISD::FABS , MVT::f64, Custom);
533 setOperationAction(ISD::FABS , MVT::f32, Custom);
535 // Use XORP to simulate FNEG.
536 setOperationAction(ISD::FNEG , MVT::f64, Custom);
537 setOperationAction(ISD::FNEG , MVT::f32, Custom);
539 // Use ANDPD and ORPD to simulate FCOPYSIGN.
540 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
541 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
543 // Lower this to FGETSIGNx86 plus an AND.
544 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
545 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
547 // We don't support sin/cos/fmod
548 setOperationAction(ISD::FSIN , MVT::f64, Expand);
549 setOperationAction(ISD::FCOS , MVT::f64, Expand);
550 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
551 setOperationAction(ISD::FSIN , MVT::f32, Expand);
552 setOperationAction(ISD::FCOS , MVT::f32, Expand);
553 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
555 // Expand FP immediates into loads from the stack, except for the special
557 addLegalFPImmediate(APFloat(+0.0)); // xorpd
558 addLegalFPImmediate(APFloat(+0.0f)); // xorps
559 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
560 // Use SSE for f32, x87 for f64.
561 // Set up the FP register classes.
562 addRegisterClass(MVT::f32, &X86::FR32RegClass);
563 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
565 // Use ANDPS to simulate FABS.
566 setOperationAction(ISD::FABS , MVT::f32, Custom);
568 // Use XORP to simulate FNEG.
569 setOperationAction(ISD::FNEG , MVT::f32, Custom);
571 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
573 // Use ANDPS and ORPS to simulate FCOPYSIGN.
574 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
575 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
577 // We don't support sin/cos/fmod
578 setOperationAction(ISD::FSIN , MVT::f32, Expand);
579 setOperationAction(ISD::FCOS , MVT::f32, Expand);
580 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
582 // Special cases we handle for FP constants.
583 addLegalFPImmediate(APFloat(+0.0f)); // xorps
584 addLegalFPImmediate(APFloat(+0.0)); // FLD0
585 addLegalFPImmediate(APFloat(+1.0)); // FLD1
586 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
587 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
589 if (!TM.Options.UnsafeFPMath) {
590 setOperationAction(ISD::FSIN , MVT::f64, Expand);
591 setOperationAction(ISD::FCOS , MVT::f64, Expand);
592 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
594 } else if (!Subtarget->useSoftFloat()) {
595 // f32 and f64 in x87.
596 // Set up the FP register classes.
597 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
598 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
600 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
601 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
602 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
603 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
605 if (!TM.Options.UnsafeFPMath) {
606 setOperationAction(ISD::FSIN , MVT::f64, Expand);
607 setOperationAction(ISD::FSIN , MVT::f32, Expand);
608 setOperationAction(ISD::FCOS , MVT::f64, Expand);
609 setOperationAction(ISD::FCOS , MVT::f32, Expand);
610 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
611 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
613 addLegalFPImmediate(APFloat(+0.0)); // FLD0
614 addLegalFPImmediate(APFloat(+1.0)); // FLD1
615 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
616 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
617 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
618 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
619 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
620 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
623 // We don't support FMA.
624 setOperationAction(ISD::FMA, MVT::f64, Expand);
625 setOperationAction(ISD::FMA, MVT::f32, Expand);
627 // Long double always uses X87, except f128 in MMX.
628 if (!Subtarget->useSoftFloat()) {
629 if (Subtarget->is64Bit() && Subtarget->hasMMX()) {
630 addRegisterClass(MVT::f128, &X86::FR128RegClass);
631 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
632 setOperationAction(ISD::FABS , MVT::f128, Custom);
633 setOperationAction(ISD::FNEG , MVT::f128, Custom);
634 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
637 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
638 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
639 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
641 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
642 addLegalFPImmediate(TmpFlt); // FLD0
644 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
647 APFloat TmpFlt2(+1.0);
648 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
650 addLegalFPImmediate(TmpFlt2); // FLD1
651 TmpFlt2.changeSign();
652 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
655 if (!TM.Options.UnsafeFPMath) {
656 setOperationAction(ISD::FSIN , MVT::f80, Expand);
657 setOperationAction(ISD::FCOS , MVT::f80, Expand);
658 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
661 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
662 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
663 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
664 setOperationAction(ISD::FRINT, MVT::f80, Expand);
665 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
666 setOperationAction(ISD::FMA, MVT::f80, Expand);
669 // Always use a library call for pow.
670 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
671 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
672 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
674 setOperationAction(ISD::FLOG, MVT::f80, Expand);
675 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
676 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
677 setOperationAction(ISD::FEXP, MVT::f80, Expand);
678 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
679 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
680 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
682 // First set operation action for all vector types to either promote
683 // (for widening) or expand (for scalarization). Then we will selectively
684 // turn on ones that can be effectively codegen'd.
685 for (MVT VT : MVT::vector_valuetypes()) {
686 setOperationAction(ISD::ADD , VT, Expand);
687 setOperationAction(ISD::SUB , VT, Expand);
688 setOperationAction(ISD::FADD, VT, Expand);
689 setOperationAction(ISD::FNEG, VT, Expand);
690 setOperationAction(ISD::FSUB, VT, Expand);
691 setOperationAction(ISD::MUL , VT, Expand);
692 setOperationAction(ISD::FMUL, VT, Expand);
693 setOperationAction(ISD::SDIV, VT, Expand);
694 setOperationAction(ISD::UDIV, VT, Expand);
695 setOperationAction(ISD::FDIV, VT, Expand);
696 setOperationAction(ISD::SREM, VT, Expand);
697 setOperationAction(ISD::UREM, VT, Expand);
698 setOperationAction(ISD::LOAD, VT, Expand);
699 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
700 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
701 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
702 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
703 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
704 setOperationAction(ISD::FABS, VT, Expand);
705 setOperationAction(ISD::FSIN, VT, Expand);
706 setOperationAction(ISD::FSINCOS, VT, Expand);
707 setOperationAction(ISD::FCOS, VT, Expand);
708 setOperationAction(ISD::FSINCOS, VT, Expand);
709 setOperationAction(ISD::FREM, VT, Expand);
710 setOperationAction(ISD::FMA, VT, Expand);
711 setOperationAction(ISD::FPOWI, VT, Expand);
712 setOperationAction(ISD::FSQRT, VT, Expand);
713 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
714 setOperationAction(ISD::FFLOOR, VT, Expand);
715 setOperationAction(ISD::FCEIL, VT, Expand);
716 setOperationAction(ISD::FTRUNC, VT, Expand);
717 setOperationAction(ISD::FRINT, VT, Expand);
718 setOperationAction(ISD::FNEARBYINT, VT, Expand);
719 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
720 setOperationAction(ISD::MULHS, VT, Expand);
721 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
722 setOperationAction(ISD::MULHU, VT, Expand);
723 setOperationAction(ISD::SDIVREM, VT, Expand);
724 setOperationAction(ISD::UDIVREM, VT, Expand);
725 setOperationAction(ISD::FPOW, VT, Expand);
726 setOperationAction(ISD::CTPOP, VT, Expand);
727 setOperationAction(ISD::CTTZ, VT, Expand);
728 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
729 setOperationAction(ISD::CTLZ, VT, Expand);
730 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
731 setOperationAction(ISD::SHL, VT, Expand);
732 setOperationAction(ISD::SRA, VT, Expand);
733 setOperationAction(ISD::SRL, VT, Expand);
734 setOperationAction(ISD::ROTL, VT, Expand);
735 setOperationAction(ISD::ROTR, VT, Expand);
736 setOperationAction(ISD::BSWAP, VT, Expand);
737 setOperationAction(ISD::SETCC, VT, Expand);
738 setOperationAction(ISD::FLOG, VT, Expand);
739 setOperationAction(ISD::FLOG2, VT, Expand);
740 setOperationAction(ISD::FLOG10, VT, Expand);
741 setOperationAction(ISD::FEXP, VT, Expand);
742 setOperationAction(ISD::FEXP2, VT, Expand);
743 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
744 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
745 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
746 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
747 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
748 setOperationAction(ISD::TRUNCATE, VT, Expand);
749 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
750 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
751 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
752 setOperationAction(ISD::VSELECT, VT, Expand);
753 setOperationAction(ISD::SELECT_CC, VT, Expand);
754 for (MVT InnerVT : MVT::vector_valuetypes()) {
755 setTruncStoreAction(InnerVT, VT, Expand);
757 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
758 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
760 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
761 // types, we have to deal with them whether we ask for Expansion or not.
762 // Setting Expand causes its own optimisation problems though, so leave
764 if (VT.getVectorElementType() == MVT::i1)
765 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
767 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
768 // split/scalarized right now.
769 if (VT.getVectorElementType() == MVT::f16)
770 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
774 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
775 // with -msoft-float, disable use of MMX as well.
776 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
777 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
778 // No operations on x86mmx supported, everything uses intrinsics.
781 // MMX-sized vectors (other than x86mmx) are expected to be expanded
782 // into smaller operations.
783 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
784 setOperationAction(ISD::MULHS, MMXTy, Expand);
785 setOperationAction(ISD::AND, MMXTy, Expand);
786 setOperationAction(ISD::OR, MMXTy, Expand);
787 setOperationAction(ISD::XOR, MMXTy, Expand);
788 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
789 setOperationAction(ISD::SELECT, MMXTy, Expand);
790 setOperationAction(ISD::BITCAST, MMXTy, Expand);
792 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
794 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
795 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
797 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
798 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
799 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
800 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
801 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
802 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
803 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
804 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
805 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
806 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
807 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
808 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
809 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
810 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
813 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
814 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
816 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
817 // registers cannot be used even for integer operations.
818 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
819 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
820 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
821 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
823 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
824 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
825 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
826 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
827 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
828 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
829 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
830 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
831 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
832 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
833 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
834 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
835 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
836 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
837 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
838 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
839 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
840 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
841 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
842 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
843 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
844 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
845 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
847 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
848 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
849 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
850 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
852 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
853 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
854 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
855 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
857 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
858 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
859 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
860 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
861 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
863 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
864 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
865 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
866 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
868 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
869 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
870 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
871 // ISD::CTTZ v2i64 - scalarization is faster.
872 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
873 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
874 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
875 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
877 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
878 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
879 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
880 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
881 setOperationAction(ISD::VSELECT, VT, Custom);
882 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
885 // We support custom legalizing of sext and anyext loads for specific
886 // memory vector types which we can load as a scalar (or sequence of
887 // scalars) and extend in-register to a legal 128-bit vector type. For sext
888 // loads these must work with a single scalar load.
889 for (MVT VT : MVT::integer_vector_valuetypes()) {
890 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
891 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
892 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
893 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
894 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
895 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
896 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
897 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
898 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
901 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
902 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
903 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
904 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
905 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
906 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
907 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
908 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
910 if (Subtarget->is64Bit()) {
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
912 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
915 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
916 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
917 setOperationAction(ISD::AND, VT, Promote);
918 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
919 setOperationAction(ISD::OR, VT, Promote);
920 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
921 setOperationAction(ISD::XOR, VT, Promote);
922 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
923 setOperationAction(ISD::LOAD, VT, Promote);
924 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
925 setOperationAction(ISD::SELECT, VT, Promote);
926 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
929 // Custom lower v2i64 and v2f64 selects.
930 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
931 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
932 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
933 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
935 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
936 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
938 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
941 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
942 // As there is no 64-bit GPR available, we need build a special custom
943 // sequence to convert from v2i32 to v2f32.
944 if (!Subtarget->is64Bit())
945 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
948 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
950 for (MVT VT : MVT::fp_vector_valuetypes())
951 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
953 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
955 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
958 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
959 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
960 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
961 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
962 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
963 setOperationAction(ISD::FRINT, RoundedTy, Legal);
964 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
967 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
968 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
969 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
970 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
971 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
972 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
973 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
974 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
976 // FIXME: Do we need to handle scalar-to-vector here?
977 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
979 // We directly match byte blends in the backend as they match the VSELECT
981 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
983 // SSE41 brings specific instructions for doing vector sign extend even in
984 // cases where we don't have SRA.
985 for (MVT VT : MVT::integer_vector_valuetypes()) {
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
988 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
991 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
997 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1004 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1006 // i8 and i16 vectors are custom because the source register and source
1007 // source memory operand types are not the same width. f32 vectors are
1008 // custom since the immediate controlling the insert encodes additional
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1013 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1018 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1020 // FIXME: these should be Legal, but that's only for the case where
1021 // the index is constant. For now custom expand to deal with that.
1022 if (Subtarget->is64Bit()) {
1023 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1024 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1028 if (Subtarget->hasSSE2()) {
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1031 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1034 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1036 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1037 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1039 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1040 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1042 // In the customized shift lowering, the legal cases in AVX2 will be
1044 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1045 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1047 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1048 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1050 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1051 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1054 if (Subtarget->hasXOP()) {
1055 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1056 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1057 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1058 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1059 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1060 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1061 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1062 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1065 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1066 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1067 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1068 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1069 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1070 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1071 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1073 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1074 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1075 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1077 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1078 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1079 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1080 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1081 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1085 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1087 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1088 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1090 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1091 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1092 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1093 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1094 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1100 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1101 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1103 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1104 // even though v8i16 is a legal type.
1105 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1106 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1107 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1109 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1110 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1111 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1113 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1114 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1116 for (MVT VT : MVT::fp_vector_valuetypes())
1117 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1119 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1120 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1122 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1123 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1125 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1126 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1128 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1129 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1130 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1131 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1133 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1134 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1135 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1137 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1138 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1139 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1140 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1141 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1142 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1143 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1144 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1145 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1146 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1147 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1148 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1150 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1151 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1152 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1153 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1155 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1156 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1157 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1158 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1159 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1160 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1161 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1162 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1164 if (Subtarget->hasAnyFMA()) {
1165 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1166 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1167 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1168 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1169 setOperationAction(ISD::FMA, MVT::f32, Legal);
1170 setOperationAction(ISD::FMA, MVT::f64, Legal);
1173 if (Subtarget->hasInt256()) {
1174 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1175 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1176 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1177 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1179 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1180 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1181 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1182 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1184 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1185 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1186 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1187 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1189 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1190 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1191 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1192 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1194 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1195 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1196 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1197 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1198 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1199 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1200 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1201 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1202 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1203 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1204 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1205 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1207 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1208 // when we have a 256bit-wide blend with immediate.
1209 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1211 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1212 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1213 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1214 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1215 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1216 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1217 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1219 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1220 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1221 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1222 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1223 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1224 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1226 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1227 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1228 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1229 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1232 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1233 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1234 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1236 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1237 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1238 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1239 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1241 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1242 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1243 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1244 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1245 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1246 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1247 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1248 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1249 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1250 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1251 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1252 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1255 // In the customized shift lowering, the legal cases in AVX2 will be
1257 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1258 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1260 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1261 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1263 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1264 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1266 // Custom lower several nodes for 256-bit types.
1267 for (MVT VT : MVT::vector_valuetypes()) {
1268 if (VT.getScalarSizeInBits() >= 32) {
1269 setOperationAction(ISD::MLOAD, VT, Legal);
1270 setOperationAction(ISD::MSTORE, VT, Legal);
1272 // Extract subvector is special because the value type
1273 // (result) is 128-bit but the source is 256-bit wide.
1274 if (VT.is128BitVector()) {
1275 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1277 // Do not attempt to custom lower other non-256-bit vectors
1278 if (!VT.is256BitVector())
1281 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1282 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1283 setOperationAction(ISD::VSELECT, VT, Custom);
1284 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1285 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1286 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1287 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1288 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1291 if (Subtarget->hasInt256())
1292 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1294 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1295 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1296 setOperationAction(ISD::AND, VT, Promote);
1297 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1298 setOperationAction(ISD::OR, VT, Promote);
1299 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1300 setOperationAction(ISD::XOR, VT, Promote);
1301 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1302 setOperationAction(ISD::LOAD, VT, Promote);
1303 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1304 setOperationAction(ISD::SELECT, VT, Promote);
1305 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1309 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1310 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1311 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1312 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1313 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1315 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1316 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1317 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1319 for (MVT VT : MVT::fp_vector_valuetypes())
1320 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1322 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1323 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1324 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1325 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1326 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1327 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1328 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1329 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1330 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1331 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1332 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1333 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1335 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1336 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1337 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1338 setOperationAction(ISD::XOR, MVT::i1, Legal);
1339 setOperationAction(ISD::OR, MVT::i1, Legal);
1340 setOperationAction(ISD::AND, MVT::i1, Legal);
1341 setOperationAction(ISD::SUB, MVT::i1, Custom);
1342 setOperationAction(ISD::ADD, MVT::i1, Custom);
1343 setOperationAction(ISD::MUL, MVT::i1, Custom);
1344 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1345 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1346 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1347 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1348 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1350 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1356 setOperationAction(ISD::FABS, MVT::v16f32, Custom);
1358 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1359 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1360 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1361 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1362 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1363 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1364 setOperationAction(ISD::FABS, MVT::v8f64, Custom);
1365 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1366 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1368 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1369 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1370 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1371 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1372 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1373 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1374 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1375 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1376 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1377 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1378 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1379 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1380 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1381 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1382 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1383 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1385 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1386 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1387 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1388 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1389 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1390 if (Subtarget->hasVLX()){
1391 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1392 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1393 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1394 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1395 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1397 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1398 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1399 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1400 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1401 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1403 setOperationAction(ISD::MLOAD, MVT::v8i32, Custom);
1404 setOperationAction(ISD::MLOAD, MVT::v8f32, Custom);
1405 setOperationAction(ISD::MSTORE, MVT::v8i32, Custom);
1406 setOperationAction(ISD::MSTORE, MVT::v8f32, Custom);
1408 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1409 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1410 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1411 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1412 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1413 if (Subtarget->hasDQI()) {
1414 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1415 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1419 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1420 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1421 if (Subtarget->hasVLX()) {
1422 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1425 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1427 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1428 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1429 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1432 if (Subtarget->hasVLX()) {
1433 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1434 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1435 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1436 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1437 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1438 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1439 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1440 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1442 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1443 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1444 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1445 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1446 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1447 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1448 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1450 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1451 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1452 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1453 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1454 if (Subtarget->hasDQI()) {
1455 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1456 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1458 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1459 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1460 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1461 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1462 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1463 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1464 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1465 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1466 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1467 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1469 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1470 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1471 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1472 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1473 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1475 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1476 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1478 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1480 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1481 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1482 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
1483 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1484 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1485 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1486 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1487 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1488 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1490 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1491 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1493 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1494 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1495 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1496 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1497 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1498 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1499 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1500 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1502 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1503 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1505 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1506 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1508 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1510 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1511 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1513 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1514 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1516 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1517 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1519 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1520 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1521 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1522 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1523 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1524 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1526 if (Subtarget->hasCDI()) {
1527 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1528 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1529 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Expand);
1530 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Expand);
1532 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1533 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1534 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1535 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1536 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Expand);
1537 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Expand);
1538 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Expand);
1539 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Expand);
1541 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1542 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1544 if (Subtarget->hasVLX()) {
1545 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1546 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1547 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1548 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1549 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Expand);
1550 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Expand);
1551 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Expand);
1552 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Expand);
1554 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1555 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1556 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1557 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1559 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1560 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1561 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1562 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1563 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Expand);
1564 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Expand);
1565 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Expand);
1566 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Expand);
1568 } // Subtarget->hasCDI()
1570 if (Subtarget->hasDQI()) {
1571 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1572 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1573 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1575 // Custom lower several nodes.
1576 for (MVT VT : MVT::vector_valuetypes()) {
1577 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1579 setOperationAction(ISD::AND, VT, Legal);
1580 setOperationAction(ISD::OR, VT, Legal);
1581 setOperationAction(ISD::XOR, VT, Legal);
1583 if ((VT.is128BitVector() || VT.is256BitVector()) && EltSize >= 32) {
1584 setOperationAction(ISD::MGATHER, VT, Custom);
1585 setOperationAction(ISD::MSCATTER, VT, Custom);
1587 // Extract subvector is special because the value type
1588 // (result) is 256/128-bit but the source is 512-bit wide.
1589 if (VT.is128BitVector() || VT.is256BitVector()) {
1590 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1592 if (VT.getVectorElementType() == MVT::i1)
1593 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1595 // Do not attempt to custom lower other non-512-bit vectors
1596 if (!VT.is512BitVector())
1599 if (EltSize >= 32) {
1600 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1601 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1602 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1603 setOperationAction(ISD::VSELECT, VT, Legal);
1604 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1605 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1606 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1607 setOperationAction(ISD::MLOAD, VT, Legal);
1608 setOperationAction(ISD::MSTORE, VT, Legal);
1609 setOperationAction(ISD::MGATHER, VT, Legal);
1610 setOperationAction(ISD::MSCATTER, VT, Custom);
1613 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1614 setOperationAction(ISD::SELECT, VT, Promote);
1615 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1619 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1620 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1621 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1623 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1624 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1626 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1627 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1628 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1629 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1630 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1631 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1632 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1633 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1634 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1635 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1636 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1637 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1638 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1639 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1640 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1641 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1642 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1643 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1644 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1645 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1646 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1647 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1648 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1649 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1650 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1651 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1652 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1653 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1654 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1655 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1656 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1657 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1658 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1659 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1660 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1661 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1662 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1663 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1664 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1665 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1666 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1667 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1669 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1670 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1671 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1672 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1673 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1674 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1675 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1676 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1678 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1679 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1680 if (Subtarget->hasVLX())
1681 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1683 if (Subtarget->hasCDI()) {
1684 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1685 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1686 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Expand);
1687 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Expand);
1690 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1691 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1692 setOperationAction(ISD::VSELECT, VT, Legal);
1693 setOperationAction(ISD::SRL, VT, Custom);
1694 setOperationAction(ISD::SHL, VT, Custom);
1695 setOperationAction(ISD::SRA, VT, Custom);
1697 setOperationAction(ISD::AND, VT, Promote);
1698 AddPromotedToType (ISD::AND, VT, MVT::v8i64);
1699 setOperationAction(ISD::OR, VT, Promote);
1700 AddPromotedToType (ISD::OR, VT, MVT::v8i64);
1701 setOperationAction(ISD::XOR, VT, Promote);
1702 AddPromotedToType (ISD::XOR, VT, MVT::v8i64);
1706 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1707 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1708 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1710 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1711 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1712 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1713 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1714 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1715 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1716 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1717 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1718 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1719 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1720 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1721 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1723 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1724 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1725 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1726 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1727 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1728 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1729 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1730 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1732 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1733 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1734 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1735 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1736 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1737 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1738 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1739 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1742 // We want to custom lower some of our intrinsics.
1743 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1744 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1745 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1746 if (!Subtarget->is64Bit()) {
1747 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1748 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1751 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1752 // handle type legalization for these operations here.
1754 // FIXME: We really should do custom legalization for addition and
1755 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1756 // than generic legalization for 64-bit multiplication-with-overflow, though.
1757 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1758 if (VT == MVT::i64 && !Subtarget->is64Bit())
1760 // Add/Sub/Mul with overflow operations are custom lowered.
1761 setOperationAction(ISD::SADDO, VT, Custom);
1762 setOperationAction(ISD::UADDO, VT, Custom);
1763 setOperationAction(ISD::SSUBO, VT, Custom);
1764 setOperationAction(ISD::USUBO, VT, Custom);
1765 setOperationAction(ISD::SMULO, VT, Custom);
1766 setOperationAction(ISD::UMULO, VT, Custom);
1769 if (!Subtarget->is64Bit()) {
1770 // These libcalls are not available in 32-bit.
1771 setLibcallName(RTLIB::SHL_I128, nullptr);
1772 setLibcallName(RTLIB::SRL_I128, nullptr);
1773 setLibcallName(RTLIB::SRA_I128, nullptr);
1776 // Combine sin / cos into one node or libcall if possible.
1777 if (Subtarget->hasSinCos()) {
1778 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1779 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1780 if (Subtarget->isTargetDarwin()) {
1781 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1782 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1783 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1784 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1788 if (Subtarget->isTargetWin64()) {
1789 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1790 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1791 setOperationAction(ISD::SREM, MVT::i128, Custom);
1792 setOperationAction(ISD::UREM, MVT::i128, Custom);
1793 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1794 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1797 // We have target-specific dag combine patterns for the following nodes:
1798 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1799 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1800 setTargetDAGCombine(ISD::BITCAST);
1801 setTargetDAGCombine(ISD::VSELECT);
1802 setTargetDAGCombine(ISD::SELECT);
1803 setTargetDAGCombine(ISD::SHL);
1804 setTargetDAGCombine(ISD::SRA);
1805 setTargetDAGCombine(ISD::SRL);
1806 setTargetDAGCombine(ISD::OR);
1807 setTargetDAGCombine(ISD::AND);
1808 setTargetDAGCombine(ISD::ADD);
1809 setTargetDAGCombine(ISD::FADD);
1810 setTargetDAGCombine(ISD::FSUB);
1811 setTargetDAGCombine(ISD::FNEG);
1812 setTargetDAGCombine(ISD::FMA);
1813 setTargetDAGCombine(ISD::FMINNUM);
1814 setTargetDAGCombine(ISD::FMAXNUM);
1815 setTargetDAGCombine(ISD::SUB);
1816 setTargetDAGCombine(ISD::LOAD);
1817 setTargetDAGCombine(ISD::MLOAD);
1818 setTargetDAGCombine(ISD::STORE);
1819 setTargetDAGCombine(ISD::MSTORE);
1820 setTargetDAGCombine(ISD::TRUNCATE);
1821 setTargetDAGCombine(ISD::ZERO_EXTEND);
1822 setTargetDAGCombine(ISD::ANY_EXTEND);
1823 setTargetDAGCombine(ISD::SIGN_EXTEND);
1824 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1825 setTargetDAGCombine(ISD::SINT_TO_FP);
1826 setTargetDAGCombine(ISD::UINT_TO_FP);
1827 setTargetDAGCombine(ISD::SETCC);
1828 setTargetDAGCombine(ISD::BUILD_VECTOR);
1829 setTargetDAGCombine(ISD::MUL);
1830 setTargetDAGCombine(ISD::XOR);
1831 setTargetDAGCombine(ISD::MSCATTER);
1832 setTargetDAGCombine(ISD::MGATHER);
1834 computeRegisterProperties(Subtarget->getRegisterInfo());
1836 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1837 MaxStoresPerMemsetOptSize = 8;
1838 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1839 MaxStoresPerMemcpyOptSize = 4;
1840 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1841 MaxStoresPerMemmoveOptSize = 4;
1842 setPrefLoopAlignment(4); // 2^4 bytes.
1844 // A predictable cmov does not hurt on an in-order CPU.
1845 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1846 PredictableSelectIsExpensive = !Subtarget->isAtom();
1847 EnableExtLdPromotion = true;
1848 setPrefFunctionAlignment(4); // 2^4 bytes.
1850 verifyIntrinsicTables();
1853 // This has so far only been implemented for 64-bit MachO.
1854 bool X86TargetLowering::useLoadStackGuardNode() const {
1855 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1858 TargetLoweringBase::LegalizeTypeAction
1859 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1860 if (ExperimentalVectorWideningLegalization &&
1861 VT.getVectorNumElements() != 1 &&
1862 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1863 return TypeWidenVector;
1865 return TargetLoweringBase::getPreferredVectorAction(VT);
1868 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1871 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1873 if (VT.isSimple()) {
1874 MVT VVT = VT.getSimpleVT();
1875 const unsigned NumElts = VVT.getVectorNumElements();
1876 const MVT EltVT = VVT.getVectorElementType();
1877 if (VVT.is512BitVector()) {
1878 if (Subtarget->hasAVX512())
1879 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1880 EltVT == MVT::f32 || EltVT == MVT::f64)
1882 case 8: return MVT::v8i1;
1883 case 16: return MVT::v16i1;
1885 if (Subtarget->hasBWI())
1886 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1888 case 32: return MVT::v32i1;
1889 case 64: return MVT::v64i1;
1893 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1894 if (Subtarget->hasVLX())
1895 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1896 EltVT == MVT::f32 || EltVT == MVT::f64)
1898 case 2: return MVT::v2i1;
1899 case 4: return MVT::v4i1;
1900 case 8: return MVT::v8i1;
1902 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1903 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1905 case 8: return MVT::v8i1;
1906 case 16: return MVT::v16i1;
1907 case 32: return MVT::v32i1;
1912 return VT.changeVectorElementTypeToInteger();
1915 /// Helper for getByValTypeAlignment to determine
1916 /// the desired ByVal argument alignment.
1917 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1920 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1921 if (VTy->getBitWidth() == 128)
1923 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1924 unsigned EltAlign = 0;
1925 getMaxByValAlign(ATy->getElementType(), EltAlign);
1926 if (EltAlign > MaxAlign)
1927 MaxAlign = EltAlign;
1928 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1929 for (auto *EltTy : STy->elements()) {
1930 unsigned EltAlign = 0;
1931 getMaxByValAlign(EltTy, EltAlign);
1932 if (EltAlign > MaxAlign)
1933 MaxAlign = EltAlign;
1940 /// Return the desired alignment for ByVal aggregate
1941 /// function arguments in the caller parameter area. For X86, aggregates
1942 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1943 /// are at 4-byte boundaries.
1944 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1945 const DataLayout &DL) const {
1946 if (Subtarget->is64Bit()) {
1947 // Max of 8 and alignment of type.
1948 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1955 if (Subtarget->hasSSE1())
1956 getMaxByValAlign(Ty, Align);
1960 /// Returns the target specific optimal type for load
1961 /// and store operations as a result of memset, memcpy, and memmove
1962 /// lowering. If DstAlign is zero that means it's safe to destination
1963 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1964 /// means there isn't a need to check it against alignment requirement,
1965 /// probably because the source does not need to be loaded. If 'IsMemset' is
1966 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1967 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1968 /// source is constant so it does not need to be loaded.
1969 /// It returns EVT::Other if the type should be determined using generic
1970 /// target-independent logic.
1972 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1973 unsigned DstAlign, unsigned SrcAlign,
1974 bool IsMemset, bool ZeroMemset,
1976 MachineFunction &MF) const {
1977 const Function *F = MF.getFunction();
1978 if ((!IsMemset || ZeroMemset) &&
1979 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1981 (!Subtarget->isUnalignedMem16Slow() ||
1982 ((DstAlign == 0 || DstAlign >= 16) &&
1983 (SrcAlign == 0 || SrcAlign >= 16)))) {
1985 // FIXME: Check if unaligned 32-byte accesses are slow.
1986 if (Subtarget->hasInt256())
1988 if (Subtarget->hasFp256())
1991 if (Subtarget->hasSSE2())
1993 if (Subtarget->hasSSE1())
1995 } else if (!MemcpyStrSrc && Size >= 8 &&
1996 !Subtarget->is64Bit() &&
1997 Subtarget->hasSSE2()) {
1998 // Do not use f64 to lower memcpy if source is string constant. It's
1999 // better to use i32 to avoid the loads.
2003 // This is a compromise. If we reach here, unaligned accesses may be slow on
2004 // this target. However, creating smaller, aligned accesses could be even
2005 // slower and would certainly be a lot more code.
2006 if (Subtarget->is64Bit() && Size >= 8)
2011 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
2013 return X86ScalarSSEf32;
2014 else if (VT == MVT::f64)
2015 return X86ScalarSSEf64;
2020 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
2025 switch (VT.getSizeInBits()) {
2027 // 8-byte and under are always assumed to be fast.
2031 *Fast = !Subtarget->isUnalignedMem16Slow();
2034 *Fast = !Subtarget->isUnalignedMem32Slow();
2036 // TODO: What about AVX-512 (512-bit) accesses?
2039 // Misaligned accesses of any size are always allowed.
2043 /// Return the entry encoding for a jump table in the
2044 /// current function. The returned value is a member of the
2045 /// MachineJumpTableInfo::JTEntryKind enum.
2046 unsigned X86TargetLowering::getJumpTableEncoding() const {
2047 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2049 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2050 Subtarget->isPICStyleGOT())
2051 return MachineJumpTableInfo::EK_Custom32;
2053 // Otherwise, use the normal jump table encoding heuristics.
2054 return TargetLowering::getJumpTableEncoding();
2057 bool X86TargetLowering::useSoftFloat() const {
2058 return Subtarget->useSoftFloat();
2062 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2063 const MachineBasicBlock *MBB,
2064 unsigned uid,MCContext &Ctx) const{
2065 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2066 Subtarget->isPICStyleGOT());
2067 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2069 return MCSymbolRefExpr::create(MBB->getSymbol(),
2070 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2073 /// Returns relocation base for the given PIC jumptable.
2074 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2075 SelectionDAG &DAG) const {
2076 if (!Subtarget->is64Bit())
2077 // This doesn't have SDLoc associated with it, but is not really the
2078 // same as a Register.
2079 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2080 getPointerTy(DAG.getDataLayout()));
2084 /// This returns the relocation base for the given PIC jumptable,
2085 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2086 const MCExpr *X86TargetLowering::
2087 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2088 MCContext &Ctx) const {
2089 // X86-64 uses RIP relative addressing based on the jump table label.
2090 if (Subtarget->isPICStyleRIPRel())
2091 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2093 // Otherwise, the reference is relative to the PIC base.
2094 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2097 std::pair<const TargetRegisterClass *, uint8_t>
2098 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2100 const TargetRegisterClass *RRC = nullptr;
2102 switch (VT.SimpleTy) {
2104 return TargetLowering::findRepresentativeClass(TRI, VT);
2105 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2106 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2109 RRC = &X86::VR64RegClass;
2111 case MVT::f32: case MVT::f64:
2112 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2113 case MVT::v4f32: case MVT::v2f64:
2114 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2116 RRC = &X86::VR128RegClass;
2119 return std::make_pair(RRC, Cost);
2122 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2123 unsigned &Offset) const {
2124 if (!Subtarget->isTargetLinux())
2127 if (Subtarget->is64Bit()) {
2128 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2130 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2142 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2143 if (!Subtarget->isTargetAndroid())
2144 return TargetLowering::getSafeStackPointerLocation(IRB);
2146 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2147 // definition of TLS_SLOT_SAFESTACK in
2148 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2149 unsigned AddressSpace, Offset;
2150 if (Subtarget->is64Bit()) {
2151 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2153 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2163 return ConstantExpr::getIntToPtr(
2164 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2165 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2168 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2169 unsigned DestAS) const {
2170 assert(SrcAS != DestAS && "Expected different address spaces!");
2172 return SrcAS < 256 && DestAS < 256;
2175 //===----------------------------------------------------------------------===//
2176 // Return Value Calling Convention Implementation
2177 //===----------------------------------------------------------------------===//
2179 #include "X86GenCallingConv.inc"
2181 bool X86TargetLowering::CanLowerReturn(
2182 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2183 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2184 SmallVector<CCValAssign, 16> RVLocs;
2185 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2186 return CCInfo.CheckReturn(Outs, RetCC_X86);
2189 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2190 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2195 X86TargetLowering::LowerReturn(SDValue Chain,
2196 CallingConv::ID CallConv, bool isVarArg,
2197 const SmallVectorImpl<ISD::OutputArg> &Outs,
2198 const SmallVectorImpl<SDValue> &OutVals,
2199 SDLoc dl, SelectionDAG &DAG) const {
2200 MachineFunction &MF = DAG.getMachineFunction();
2201 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2203 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2204 report_fatal_error("X86 interrupts may not return any value");
2206 SmallVector<CCValAssign, 16> RVLocs;
2207 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2208 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2211 SmallVector<SDValue, 6> RetOps;
2212 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2213 // Operand #1 = Bytes To Pop
2214 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2217 // Copy the result values into the output registers.
2218 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2219 CCValAssign &VA = RVLocs[i];
2220 assert(VA.isRegLoc() && "Can only return in registers!");
2221 SDValue ValToCopy = OutVals[i];
2222 EVT ValVT = ValToCopy.getValueType();
2224 // Promote values to the appropriate types.
2225 if (VA.getLocInfo() == CCValAssign::SExt)
2226 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2227 else if (VA.getLocInfo() == CCValAssign::ZExt)
2228 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2229 else if (VA.getLocInfo() == CCValAssign::AExt) {
2230 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2231 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2233 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2235 else if (VA.getLocInfo() == CCValAssign::BCvt)
2236 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2238 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2239 "Unexpected FP-extend for return value.");
2241 // If this is x86-64, and we disabled SSE, we can't return FP values,
2242 // or SSE or MMX vectors.
2243 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2244 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2245 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2246 report_fatal_error("SSE register return with SSE disabled");
2248 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2249 // llvm-gcc has never done it right and no one has noticed, so this
2250 // should be OK for now.
2251 if (ValVT == MVT::f64 &&
2252 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2253 report_fatal_error("SSE2 register return with SSE2 disabled");
2255 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2256 // the RET instruction and handled by the FP Stackifier.
2257 if (VA.getLocReg() == X86::FP0 ||
2258 VA.getLocReg() == X86::FP1) {
2259 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2260 // change the value to the FP stack register class.
2261 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2262 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2263 RetOps.push_back(ValToCopy);
2264 // Don't emit a copytoreg.
2268 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2269 // which is returned in RAX / RDX.
2270 if (Subtarget->is64Bit()) {
2271 if (ValVT == MVT::x86mmx) {
2272 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2273 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2274 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2276 // If we don't have SSE2 available, convert to v4f32 so the generated
2277 // register is legal.
2278 if (!Subtarget->hasSSE2())
2279 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2284 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2285 Flag = Chain.getValue(1);
2286 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2289 // All x86 ABIs require that for returning structs by value we copy
2290 // the sret argument into %rax/%eax (depending on ABI) for the return.
2291 // We saved the argument into a virtual register in the entry block,
2292 // so now we copy the value out and into %rax/%eax.
2294 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2295 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2296 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2297 // either case FuncInfo->setSRetReturnReg() will have been called.
2298 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2299 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2300 getPointerTy(MF.getDataLayout()));
2303 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2304 X86::RAX : X86::EAX;
2305 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2306 Flag = Chain.getValue(1);
2308 // RAX/EAX now acts like a return value.
2310 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2313 RetOps[0] = Chain; // Update chain.
2315 // Add the flag if we have it.
2317 RetOps.push_back(Flag);
2319 X86ISD::NodeType opcode = X86ISD::RET_FLAG;
2320 if (CallConv == CallingConv::X86_INTR)
2321 opcode = X86ISD::IRET;
2322 return DAG.getNode(opcode, dl, MVT::Other, RetOps);
2325 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2326 if (N->getNumValues() != 1)
2328 if (!N->hasNUsesOfValue(1, 0))
2331 SDValue TCChain = Chain;
2332 SDNode *Copy = *N->use_begin();
2333 if (Copy->getOpcode() == ISD::CopyToReg) {
2334 // If the copy has a glue operand, we conservatively assume it isn't safe to
2335 // perform a tail call.
2336 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2338 TCChain = Copy->getOperand(0);
2339 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2342 bool HasRet = false;
2343 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2345 if (UI->getOpcode() != X86ISD::RET_FLAG)
2347 // If we are returning more than one value, we can definitely
2348 // not make a tail call see PR19530
2349 if (UI->getNumOperands() > 4)
2351 if (UI->getNumOperands() == 4 &&
2352 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2365 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2366 ISD::NodeType ExtendKind) const {
2368 // TODO: Is this also valid on 32-bit?
2369 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2370 ReturnMVT = MVT::i8;
2372 ReturnMVT = MVT::i32;
2374 EVT MinVT = getRegisterType(Context, ReturnMVT);
2375 return VT.bitsLT(MinVT) ? MinVT : VT;
2378 /// Lower the result values of a call into the
2379 /// appropriate copies out of appropriate physical registers.
2382 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2383 CallingConv::ID CallConv, bool isVarArg,
2384 const SmallVectorImpl<ISD::InputArg> &Ins,
2385 SDLoc dl, SelectionDAG &DAG,
2386 SmallVectorImpl<SDValue> &InVals) const {
2388 // Assign locations to each value returned by this call.
2389 SmallVector<CCValAssign, 16> RVLocs;
2390 bool Is64Bit = Subtarget->is64Bit();
2391 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2393 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2395 // Copy all of the result registers out of their specified physreg.
2396 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2397 CCValAssign &VA = RVLocs[i];
2398 EVT CopyVT = VA.getLocVT();
2400 // If this is x86-64, and we disabled SSE, we can't return FP values
2401 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64 || CopyVT == MVT::f128) &&
2402 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2403 report_fatal_error("SSE register return with SSE disabled");
2406 // If we prefer to use the value in xmm registers, copy it out as f80 and
2407 // use a truncate to move it from fp stack reg to xmm reg.
2408 bool RoundAfterCopy = false;
2409 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2410 isScalarFPTypeInSSEReg(VA.getValVT())) {
2412 RoundAfterCopy = (CopyVT != VA.getLocVT());
2415 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2416 CopyVT, InFlag).getValue(1);
2417 SDValue Val = Chain.getValue(0);
2420 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2421 // This truncation won't change the value.
2422 DAG.getIntPtrConstant(1, dl));
2424 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2425 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2427 InFlag = Chain.getValue(2);
2428 InVals.push_back(Val);
2434 //===----------------------------------------------------------------------===//
2435 // C & StdCall & Fast Calling Convention implementation
2436 //===----------------------------------------------------------------------===//
2437 // StdCall calling convention seems to be standard for many Windows' API
2438 // routines and around. It differs from C calling convention just a little:
2439 // callee should clean up the stack, not caller. Symbols should be also
2440 // decorated in some fancy way :) It doesn't support any vector arguments.
2441 // For info on fast calling convention see Fast Calling Convention (tail call)
2442 // implementation LowerX86_32FastCCCallTo.
2444 /// CallIsStructReturn - Determines whether a call uses struct return
2446 enum StructReturnType {
2451 static StructReturnType
2452 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsMCU) {
2454 return NotStructReturn;
2456 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2457 if (!Flags.isSRet())
2458 return NotStructReturn;
2459 if (Flags.isInReg() || IsMCU)
2460 return RegStructReturn;
2461 return StackStructReturn;
2464 /// Determines whether a function uses struct return semantics.
2465 static StructReturnType
2466 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsMCU) {
2468 return NotStructReturn;
2470 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2471 if (!Flags.isSRet())
2472 return NotStructReturn;
2473 if (Flags.isInReg() || IsMCU)
2474 return RegStructReturn;
2475 return StackStructReturn;
2478 /// Make a copy of an aggregate at address specified by "Src" to address
2479 /// "Dst" with size and alignment information specified by the specific
2480 /// parameter attribute. The copy will be passed as a byval function parameter.
2482 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2483 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2485 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2487 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2488 /*isVolatile*/false, /*AlwaysInline=*/true,
2489 /*isTailCall*/false,
2490 MachinePointerInfo(), MachinePointerInfo());
2493 /// Return true if the calling convention is one that we can guarantee TCO for.
2494 static bool canGuaranteeTCO(CallingConv::ID CC) {
2495 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2496 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2499 /// Return true if we might ever do TCO for calls with this calling convention.
2500 static bool mayTailCallThisCC(CallingConv::ID CC) {
2502 // C calling conventions:
2503 case CallingConv::C:
2504 case CallingConv::X86_64_Win64:
2505 case CallingConv::X86_64_SysV:
2506 // Callee pop conventions:
2507 case CallingConv::X86_ThisCall:
2508 case CallingConv::X86_StdCall:
2509 case CallingConv::X86_VectorCall:
2510 case CallingConv::X86_FastCall:
2513 return canGuaranteeTCO(CC);
2517 /// Return true if the function is being made into a tailcall target by
2518 /// changing its ABI.
2519 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2520 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2523 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2525 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2526 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2530 CallingConv::ID CalleeCC = CS.getCallingConv();
2531 if (!mayTailCallThisCC(CalleeCC))
2538 X86TargetLowering::LowerMemArgument(SDValue Chain,
2539 CallingConv::ID CallConv,
2540 const SmallVectorImpl<ISD::InputArg> &Ins,
2541 SDLoc dl, SelectionDAG &DAG,
2542 const CCValAssign &VA,
2543 MachineFrameInfo *MFI,
2545 // Create the nodes corresponding to a load from this parameter slot.
2546 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2547 bool AlwaysUseMutable = shouldGuaranteeTCO(
2548 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2549 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2552 // If value is passed by pointer we have address passed instead of the value
2554 bool ExtendedInMem = VA.isExtInLoc() &&
2555 VA.getValVT().getScalarType() == MVT::i1;
2557 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2558 ValVT = VA.getLocVT();
2560 ValVT = VA.getValVT();
2562 // Calculate SP offset of interrupt parameter, re-arrange the slot normally
2563 // taken by a return address.
2565 if (CallConv == CallingConv::X86_INTR) {
2566 const X86Subtarget& Subtarget =
2567 static_cast<const X86Subtarget&>(DAG.getSubtarget());
2568 // X86 interrupts may take one or two arguments.
2569 // On the stack there will be no return address as in regular call.
2570 // Offset of last argument need to be set to -4/-8 bytes.
2571 // Where offset of the first argument out of two, should be set to 0 bytes.
2572 Offset = (Subtarget.is64Bit() ? 8 : 4) * ((i + 1) % Ins.size() - 1);
2575 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2576 // changed with more analysis.
2577 // In case of tail call optimization mark all arguments mutable. Since they
2578 // could be overwritten by lowering of arguments in case of a tail call.
2579 if (Flags.isByVal()) {
2580 unsigned Bytes = Flags.getByValSize();
2581 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2582 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2583 // Adjust SP offset of interrupt parameter.
2584 if (CallConv == CallingConv::X86_INTR) {
2585 MFI->setObjectOffset(FI, Offset);
2587 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2589 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2590 VA.getLocMemOffset(), isImmutable);
2591 // Adjust SP offset of interrupt parameter.
2592 if (CallConv == CallingConv::X86_INTR) {
2593 MFI->setObjectOffset(FI, Offset);
2596 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2597 SDValue Val = DAG.getLoad(
2598 ValVT, dl, Chain, FIN,
2599 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2601 return ExtendedInMem ?
2602 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2606 // FIXME: Get this from tablegen.
2607 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2608 const X86Subtarget *Subtarget) {
2609 assert(Subtarget->is64Bit());
2611 if (Subtarget->isCallingConvWin64(CallConv)) {
2612 static const MCPhysReg GPR64ArgRegsWin64[] = {
2613 X86::RCX, X86::RDX, X86::R8, X86::R9
2615 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2618 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2619 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2621 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2624 // FIXME: Get this from tablegen.
2625 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2626 CallingConv::ID CallConv,
2627 const X86Subtarget *Subtarget) {
2628 assert(Subtarget->is64Bit());
2629 if (Subtarget->isCallingConvWin64(CallConv)) {
2630 // The XMM registers which might contain var arg parameters are shadowed
2631 // in their paired GPR. So we only need to save the GPR to their home
2633 // TODO: __vectorcall will change this.
2637 const Function *Fn = MF.getFunction();
2638 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2639 bool isSoftFloat = Subtarget->useSoftFloat();
2640 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2641 "SSE register cannot be used when SSE is disabled!");
2642 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2643 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2647 static const MCPhysReg XMMArgRegs64Bit[] = {
2648 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2649 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2651 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2654 SDValue X86TargetLowering::LowerFormalArguments(
2655 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2656 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2657 SmallVectorImpl<SDValue> &InVals) const {
2658 MachineFunction &MF = DAG.getMachineFunction();
2659 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2660 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2662 const Function* Fn = MF.getFunction();
2663 if (Fn->hasExternalLinkage() &&
2664 Subtarget->isTargetCygMing() &&
2665 Fn->getName() == "main")
2666 FuncInfo->setForceFramePointer(true);
2668 MachineFrameInfo *MFI = MF.getFrameInfo();
2669 bool Is64Bit = Subtarget->is64Bit();
2670 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2672 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2673 "Var args not supported with calling convention fastcc, ghc or hipe");
2675 if (CallConv == CallingConv::X86_INTR) {
2676 bool isLegal = Ins.size() == 1 ||
2677 (Ins.size() == 2 && ((Is64Bit && Ins[1].VT == MVT::i64) ||
2678 (!Is64Bit && Ins[1].VT == MVT::i32)));
2680 report_fatal_error("X86 interrupts may take one or two arguments");
2683 // Assign locations to all of the incoming arguments.
2684 SmallVector<CCValAssign, 16> ArgLocs;
2685 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2687 // Allocate shadow area for Win64
2689 CCInfo.AllocateStack(32, 8);
2691 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2693 unsigned LastVal = ~0U;
2695 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2696 CCValAssign &VA = ArgLocs[i];
2697 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2699 assert(VA.getValNo() != LastVal &&
2700 "Don't support value assigned to multiple locs yet");
2702 LastVal = VA.getValNo();
2704 if (VA.isRegLoc()) {
2705 EVT RegVT = VA.getLocVT();
2706 const TargetRegisterClass *RC;
2707 if (RegVT == MVT::i32)
2708 RC = &X86::GR32RegClass;
2709 else if (Is64Bit && RegVT == MVT::i64)
2710 RC = &X86::GR64RegClass;
2711 else if (RegVT == MVT::f32)
2712 RC = &X86::FR32RegClass;
2713 else if (RegVT == MVT::f64)
2714 RC = &X86::FR64RegClass;
2715 else if (RegVT == MVT::f128)
2716 RC = &X86::FR128RegClass;
2717 else if (RegVT.is512BitVector())
2718 RC = &X86::VR512RegClass;
2719 else if (RegVT.is256BitVector())
2720 RC = &X86::VR256RegClass;
2721 else if (RegVT.is128BitVector())
2722 RC = &X86::VR128RegClass;
2723 else if (RegVT == MVT::x86mmx)
2724 RC = &X86::VR64RegClass;
2725 else if (RegVT == MVT::i1)
2726 RC = &X86::VK1RegClass;
2727 else if (RegVT == MVT::v8i1)
2728 RC = &X86::VK8RegClass;
2729 else if (RegVT == MVT::v16i1)
2730 RC = &X86::VK16RegClass;
2731 else if (RegVT == MVT::v32i1)
2732 RC = &X86::VK32RegClass;
2733 else if (RegVT == MVT::v64i1)
2734 RC = &X86::VK64RegClass;
2736 llvm_unreachable("Unknown argument type!");
2738 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2739 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2741 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2742 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2744 if (VA.getLocInfo() == CCValAssign::SExt)
2745 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2746 DAG.getValueType(VA.getValVT()));
2747 else if (VA.getLocInfo() == CCValAssign::ZExt)
2748 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2749 DAG.getValueType(VA.getValVT()));
2750 else if (VA.getLocInfo() == CCValAssign::BCvt)
2751 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2753 if (VA.isExtInLoc()) {
2754 // Handle MMX values passed in XMM regs.
2755 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2756 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2758 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2761 assert(VA.isMemLoc());
2762 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2765 // If value is passed via pointer - do a load.
2766 if (VA.getLocInfo() == CCValAssign::Indirect)
2767 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2768 MachinePointerInfo(), false, false, false, 0);
2770 InVals.push_back(ArgValue);
2773 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2774 // All x86 ABIs require that for returning structs by value we copy the
2775 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2776 // the argument into a virtual register so that we can access it from the
2778 if (Ins[i].Flags.isSRet()) {
2779 unsigned Reg = FuncInfo->getSRetReturnReg();
2781 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2782 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2783 FuncInfo->setSRetReturnReg(Reg);
2785 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2786 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2791 unsigned StackSize = CCInfo.getNextStackOffset();
2792 // Align stack specially for tail calls.
2793 if (shouldGuaranteeTCO(CallConv,
2794 MF.getTarget().Options.GuaranteedTailCallOpt))
2795 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2797 // If the function takes variable number of arguments, make a frame index for
2798 // the start of the first vararg value... for expansion of llvm.va_start. We
2799 // can skip this if there are no va_start calls.
2800 if (MFI->hasVAStart() &&
2801 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2802 CallConv != CallingConv::X86_ThisCall))) {
2803 FuncInfo->setVarArgsFrameIndex(
2804 MFI->CreateFixedObject(1, StackSize, true));
2807 // Figure out if XMM registers are in use.
2808 assert(!(Subtarget->useSoftFloat() &&
2809 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2810 "SSE register cannot be used when SSE is disabled!");
2812 // 64-bit calling conventions support varargs and register parameters, so we
2813 // have to do extra work to spill them in the prologue.
2814 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2815 // Find the first unallocated argument registers.
2816 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2817 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2818 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2819 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2820 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2821 "SSE register cannot be used when SSE is disabled!");
2823 // Gather all the live in physical registers.
2824 SmallVector<SDValue, 6> LiveGPRs;
2825 SmallVector<SDValue, 8> LiveXMMRegs;
2827 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2828 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2830 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2832 if (!ArgXMMs.empty()) {
2833 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2834 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2835 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2836 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2837 LiveXMMRegs.push_back(
2838 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2843 // Get to the caller-allocated home save location. Add 8 to account
2844 // for the return address.
2845 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2846 FuncInfo->setRegSaveFrameIndex(
2847 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2848 // Fixup to set vararg frame on shadow area (4 x i64).
2850 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2852 // For X86-64, if there are vararg parameters that are passed via
2853 // registers, then we must store them to their spots on the stack so
2854 // they may be loaded by deferencing the result of va_next.
2855 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2856 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2857 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2858 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2861 // Store the integer parameter registers.
2862 SmallVector<SDValue, 8> MemOps;
2863 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2864 getPointerTy(DAG.getDataLayout()));
2865 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2866 for (SDValue Val : LiveGPRs) {
2867 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2868 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2870 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2871 MachinePointerInfo::getFixedStack(
2872 DAG.getMachineFunction(),
2873 FuncInfo->getRegSaveFrameIndex(), Offset),
2875 MemOps.push_back(Store);
2879 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2880 // Now store the XMM (fp + vector) parameter registers.
2881 SmallVector<SDValue, 12> SaveXMMOps;
2882 SaveXMMOps.push_back(Chain);
2883 SaveXMMOps.push_back(ALVal);
2884 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2885 FuncInfo->getRegSaveFrameIndex(), dl));
2886 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2887 FuncInfo->getVarArgsFPOffset(), dl));
2888 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2890 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2891 MVT::Other, SaveXMMOps));
2894 if (!MemOps.empty())
2895 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2898 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2899 // Find the largest legal vector type.
2900 MVT VecVT = MVT::Other;
2901 // FIXME: Only some x86_32 calling conventions support AVX512.
2902 if (Subtarget->hasAVX512() &&
2903 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2904 CallConv == CallingConv::Intel_OCL_BI)))
2905 VecVT = MVT::v16f32;
2906 else if (Subtarget->hasAVX())
2908 else if (Subtarget->hasSSE2())
2911 // We forward some GPRs and some vector types.
2912 SmallVector<MVT, 2> RegParmTypes;
2913 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2914 RegParmTypes.push_back(IntVT);
2915 if (VecVT != MVT::Other)
2916 RegParmTypes.push_back(VecVT);
2918 // Compute the set of forwarded registers. The rest are scratch.
2919 SmallVectorImpl<ForwardedRegister> &Forwards =
2920 FuncInfo->getForwardedMustTailRegParms();
2921 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2923 // Conservatively forward AL on x86_64, since it might be used for varargs.
2924 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2925 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2926 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2929 // Copy all forwards from physical to virtual registers.
2930 for (ForwardedRegister &F : Forwards) {
2931 // FIXME: Can we use a less constrained schedule?
2932 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2933 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2934 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2938 // Some CCs need callee pop.
2939 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2940 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2941 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2942 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
2943 // X86 interrupts must pop the error code if present
2944 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 8 : 4);
2946 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2947 // If this is an sret function, the return should pop the hidden pointer.
2948 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2949 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2950 argsAreStructReturn(Ins, Subtarget->isTargetMCU()) == StackStructReturn)
2951 FuncInfo->setBytesToPopOnReturn(4);
2955 // RegSaveFrameIndex is X86-64 only.
2956 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2957 if (CallConv == CallingConv::X86_FastCall ||
2958 CallConv == CallingConv::X86_ThisCall)
2959 // fastcc functions can't have varargs.
2960 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2963 FuncInfo->setArgumentStackSize(StackSize);
2965 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
2966 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
2967 if (Personality == EHPersonality::CoreCLR) {
2969 // TODO: Add a mechanism to frame lowering that will allow us to indicate
2970 // that we'd prefer this slot be allocated towards the bottom of the frame
2971 // (i.e. near the stack pointer after allocating the frame). Every
2972 // funclet needs a copy of this slot in its (mostly empty) frame, and the
2973 // offset from the bottom of this and each funclet's frame must be the
2974 // same, so the size of funclets' (mostly empty) frames is dictated by
2975 // how far this slot is from the bottom (since they allocate just enough
2976 // space to accomodate holding this slot at the correct offset).
2977 int PSPSymFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2978 EHInfo->PSPSymFrameIdx = PSPSymFI;
2986 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2987 SDValue StackPtr, SDValue Arg,
2988 SDLoc dl, SelectionDAG &DAG,
2989 const CCValAssign &VA,
2990 ISD::ArgFlagsTy Flags) const {
2991 unsigned LocMemOffset = VA.getLocMemOffset();
2992 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2993 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2995 if (Flags.isByVal())
2996 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2998 return DAG.getStore(
2999 Chain, dl, Arg, PtrOff,
3000 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
3004 /// Emit a load of return address if tail call
3005 /// optimization is performed and it is required.
3007 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
3008 SDValue &OutRetAddr, SDValue Chain,
3009 bool IsTailCall, bool Is64Bit,
3010 int FPDiff, SDLoc dl) const {
3011 // Adjust the Return address stack slot.
3012 EVT VT = getPointerTy(DAG.getDataLayout());
3013 OutRetAddr = getReturnAddressFrameIndex(DAG);
3015 // Load the "old" Return address.
3016 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
3017 false, false, false, 0);
3018 return SDValue(OutRetAddr.getNode(), 1);
3021 /// Emit a store of the return address if tail call
3022 /// optimization is performed and it is required (FPDiff!=0).
3023 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
3024 SDValue Chain, SDValue RetAddrFrIdx,
3025 EVT PtrVT, unsigned SlotSize,
3026 int FPDiff, SDLoc dl) {
3027 // Store the return address to the appropriate stack slot.
3028 if (!FPDiff) return Chain;
3029 // Calculate the new stack slot for the return address.
3030 int NewReturnAddrFI =
3031 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
3033 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
3034 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
3035 MachinePointerInfo::getFixedStack(
3036 DAG.getMachineFunction(), NewReturnAddrFI),
3041 /// Returns a vector_shuffle mask for an movs{s|d}, movd
3042 /// operation of specified width.
3043 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
3045 unsigned NumElems = VT.getVectorNumElements();
3046 SmallVector<int, 8> Mask;
3047 Mask.push_back(NumElems);
3048 for (unsigned i = 1; i != NumElems; ++i)
3050 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3054 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3055 SmallVectorImpl<SDValue> &InVals) const {
3056 SelectionDAG &DAG = CLI.DAG;
3058 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3059 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3060 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3061 SDValue Chain = CLI.Chain;
3062 SDValue Callee = CLI.Callee;
3063 CallingConv::ID CallConv = CLI.CallConv;
3064 bool &isTailCall = CLI.IsTailCall;
3065 bool isVarArg = CLI.IsVarArg;
3067 MachineFunction &MF = DAG.getMachineFunction();
3068 bool Is64Bit = Subtarget->is64Bit();
3069 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
3070 StructReturnType SR = callIsStructReturn(Outs, Subtarget->isTargetMCU());
3071 bool IsSibcall = false;
3072 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3073 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
3075 if (CallConv == CallingConv::X86_INTR)
3076 report_fatal_error("X86 interrupts may not be called directly");
3078 if (Attr.getValueAsString() == "true")
3081 if (Subtarget->isPICStyleGOT() &&
3082 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3083 // If we are using a GOT, disable tail calls to external symbols with
3084 // default visibility. Tail calling such a symbol requires using a GOT
3085 // relocation, which forces early binding of the symbol. This breaks code
3086 // that require lazy function symbol resolution. Using musttail or
3087 // GuaranteedTailCallOpt will override this.
3088 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3089 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3090 G->getGlobal()->hasDefaultVisibility()))
3094 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3096 // Force this to be a tail call. The verifier rules are enough to ensure
3097 // that we can lower this successfully without moving the return address
3100 } else if (isTailCall) {
3101 // Check if it's really possible to do a tail call.
3102 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3103 isVarArg, SR != NotStructReturn,
3104 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3105 Outs, OutVals, Ins, DAG);
3107 // Sibcalls are automatically detected tailcalls which do not require
3109 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3116 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3117 "Var args not supported with calling convention fastcc, ghc or hipe");
3119 // Analyze operands of the call, assigning locations to each operand.
3120 SmallVector<CCValAssign, 16> ArgLocs;
3121 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3123 // Allocate shadow area for Win64
3125 CCInfo.AllocateStack(32, 8);
3127 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3129 // Get a count of how many bytes are to be pushed on the stack.
3130 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3132 // This is a sibcall. The memory operands are available in caller's
3133 // own caller's stack.
3135 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3136 canGuaranteeTCO(CallConv))
3137 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3140 if (isTailCall && !IsSibcall && !IsMustTail) {
3141 // Lower arguments at fp - stackoffset + fpdiff.
3142 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3144 FPDiff = NumBytesCallerPushed - NumBytes;
3146 // Set the delta of movement of the returnaddr stackslot.
3147 // But only set if delta is greater than previous delta.
3148 if (FPDiff < X86Info->getTCReturnAddrDelta())
3149 X86Info->setTCReturnAddrDelta(FPDiff);
3152 unsigned NumBytesToPush = NumBytes;
3153 unsigned NumBytesToPop = NumBytes;
3155 // If we have an inalloca argument, all stack space has already been allocated
3156 // for us and be right at the top of the stack. We don't support multiple
3157 // arguments passed in memory when using inalloca.
3158 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3160 if (!ArgLocs.back().isMemLoc())
3161 report_fatal_error("cannot use inalloca attribute on a register "
3163 if (ArgLocs.back().getLocMemOffset() != 0)
3164 report_fatal_error("any parameter with the inalloca attribute must be "
3165 "the only memory argument");
3169 Chain = DAG.getCALLSEQ_START(
3170 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3172 SDValue RetAddrFrIdx;
3173 // Load return address for tail calls.
3174 if (isTailCall && FPDiff)
3175 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3176 Is64Bit, FPDiff, dl);
3178 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3179 SmallVector<SDValue, 8> MemOpChains;
3182 // Walk the register/memloc assignments, inserting copies/loads. In the case
3183 // of tail call optimization arguments are handle later.
3184 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3185 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3186 // Skip inalloca arguments, they have already been written.
3187 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3188 if (Flags.isInAlloca())
3191 CCValAssign &VA = ArgLocs[i];
3192 EVT RegVT = VA.getLocVT();
3193 SDValue Arg = OutVals[i];
3194 bool isByVal = Flags.isByVal();
3196 // Promote the value if needed.
3197 switch (VA.getLocInfo()) {
3198 default: llvm_unreachable("Unknown loc info!");
3199 case CCValAssign::Full: break;
3200 case CCValAssign::SExt:
3201 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3203 case CCValAssign::ZExt:
3204 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3206 case CCValAssign::AExt:
3207 if (Arg.getValueType().isVector() &&
3208 Arg.getValueType().getVectorElementType() == MVT::i1)
3209 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3210 else if (RegVT.is128BitVector()) {
3211 // Special case: passing MMX values in XMM registers.
3212 Arg = DAG.getBitcast(MVT::i64, Arg);
3213 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3214 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3216 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3218 case CCValAssign::BCvt:
3219 Arg = DAG.getBitcast(RegVT, Arg);
3221 case CCValAssign::Indirect: {
3222 // Store the argument.
3223 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3224 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3225 Chain = DAG.getStore(
3226 Chain, dl, Arg, SpillSlot,
3227 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3234 if (VA.isRegLoc()) {
3235 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3236 if (isVarArg && IsWin64) {
3237 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3238 // shadow reg if callee is a varargs function.
3239 unsigned ShadowReg = 0;
3240 switch (VA.getLocReg()) {
3241 case X86::XMM0: ShadowReg = X86::RCX; break;
3242 case X86::XMM1: ShadowReg = X86::RDX; break;
3243 case X86::XMM2: ShadowReg = X86::R8; break;
3244 case X86::XMM3: ShadowReg = X86::R9; break;
3247 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3249 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3250 assert(VA.isMemLoc());
3251 if (!StackPtr.getNode())
3252 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3253 getPointerTy(DAG.getDataLayout()));
3254 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3255 dl, DAG, VA, Flags));
3259 if (!MemOpChains.empty())
3260 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3262 if (Subtarget->isPICStyleGOT()) {
3263 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3266 RegsToPass.push_back(std::make_pair(
3267 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3268 getPointerTy(DAG.getDataLayout()))));
3270 // If we are tail calling and generating PIC/GOT style code load the
3271 // address of the callee into ECX. The value in ecx is used as target of
3272 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3273 // for tail calls on PIC/GOT architectures. Normally we would just put the
3274 // address of GOT into ebx and then call target@PLT. But for tail calls
3275 // ebx would be restored (since ebx is callee saved) before jumping to the
3278 // Note: The actual moving to ECX is done further down.
3279 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3280 if (G && !G->getGlobal()->hasLocalLinkage() &&
3281 G->getGlobal()->hasDefaultVisibility())
3282 Callee = LowerGlobalAddress(Callee, DAG);
3283 else if (isa<ExternalSymbolSDNode>(Callee))
3284 Callee = LowerExternalSymbol(Callee, DAG);
3288 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3289 // From AMD64 ABI document:
3290 // For calls that may call functions that use varargs or stdargs
3291 // (prototype-less calls or calls to functions containing ellipsis (...) in
3292 // the declaration) %al is used as hidden argument to specify the number
3293 // of SSE registers used. The contents of %al do not need to match exactly
3294 // the number of registers, but must be an ubound on the number of SSE
3295 // registers used and is in the range 0 - 8 inclusive.
3297 // Count the number of XMM registers allocated.
3298 static const MCPhysReg XMMArgRegs[] = {
3299 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3300 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3302 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3303 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3304 && "SSE registers cannot be used when SSE is disabled");
3306 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3307 DAG.getConstant(NumXMMRegs, dl,
3311 if (isVarArg && IsMustTail) {
3312 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3313 for (const auto &F : Forwards) {
3314 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3315 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3319 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3320 // don't need this because the eligibility check rejects calls that require
3321 // shuffling arguments passed in memory.
3322 if (!IsSibcall && isTailCall) {
3323 // Force all the incoming stack arguments to be loaded from the stack
3324 // before any new outgoing arguments are stored to the stack, because the
3325 // outgoing stack slots may alias the incoming argument stack slots, and
3326 // the alias isn't otherwise explicit. This is slightly more conservative
3327 // than necessary, because it means that each store effectively depends
3328 // on every argument instead of just those arguments it would clobber.
3329 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3331 SmallVector<SDValue, 8> MemOpChains2;
3334 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3335 CCValAssign &VA = ArgLocs[i];
3338 assert(VA.isMemLoc());
3339 SDValue Arg = OutVals[i];
3340 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3341 // Skip inalloca arguments. They don't require any work.
3342 if (Flags.isInAlloca())
3344 // Create frame index.
3345 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3346 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3347 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3348 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3350 if (Flags.isByVal()) {
3351 // Copy relative to framepointer.
3352 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3353 if (!StackPtr.getNode())
3354 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3355 getPointerTy(DAG.getDataLayout()));
3356 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3359 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3363 // Store relative to framepointer.
3364 MemOpChains2.push_back(DAG.getStore(
3365 ArgChain, dl, Arg, FIN,
3366 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3371 if (!MemOpChains2.empty())
3372 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3374 // Store the return address to the appropriate stack slot.
3375 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3376 getPointerTy(DAG.getDataLayout()),
3377 RegInfo->getSlotSize(), FPDiff, dl);
3380 // Build a sequence of copy-to-reg nodes chained together with token chain
3381 // and flag operands which copy the outgoing args into registers.
3383 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3384 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3385 RegsToPass[i].second, InFlag);
3386 InFlag = Chain.getValue(1);
3389 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3390 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3391 // In the 64-bit large code model, we have to make all calls
3392 // through a register, since the call instruction's 32-bit
3393 // pc-relative offset may not be large enough to hold the whole
3395 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3396 // If the callee is a GlobalAddress node (quite common, every direct call
3397 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3399 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3401 // We should use extra load for direct calls to dllimported functions in
3403 const GlobalValue *GV = G->getGlobal();
3404 if (!GV->hasDLLImportStorageClass()) {
3405 unsigned char OpFlags = 0;
3406 bool ExtraLoad = false;
3407 unsigned WrapperKind = ISD::DELETED_NODE;
3409 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3410 // external symbols most go through the PLT in PIC mode. If the symbol
3411 // has hidden or protected visibility, or if it is static or local, then
3412 // we don't need to use the PLT - we can directly call it.
3413 if (Subtarget->isTargetELF() &&
3414 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3415 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3416 OpFlags = X86II::MO_PLT;
3417 } else if (Subtarget->isPICStyleStubAny() &&
3418 !GV->isStrongDefinitionForLinker() &&
3419 (!Subtarget->getTargetTriple().isMacOSX() ||
3420 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3421 // PC-relative references to external symbols should go through $stub,
3422 // unless we're building with the leopard linker or later, which
3423 // automatically synthesizes these stubs.
3424 OpFlags = X86II::MO_DARWIN_STUB;
3425 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3426 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3427 // If the function is marked as non-lazy, generate an indirect call
3428 // which loads from the GOT directly. This avoids runtime overhead
3429 // at the cost of eager binding (and one extra byte of encoding).
3430 OpFlags = X86II::MO_GOTPCREL;
3431 WrapperKind = X86ISD::WrapperRIP;
3435 Callee = DAG.getTargetGlobalAddress(
3436 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3438 // Add a wrapper if needed.
3439 if (WrapperKind != ISD::DELETED_NODE)
3440 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3441 getPointerTy(DAG.getDataLayout()), Callee);
3442 // Add extra indirection if needed.
3444 Callee = DAG.getLoad(
3445 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3446 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3449 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3450 unsigned char OpFlags = 0;
3452 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3453 // external symbols should go through the PLT.
3454 if (Subtarget->isTargetELF() &&
3455 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3456 OpFlags = X86II::MO_PLT;
3457 } else if (Subtarget->isPICStyleStubAny() &&
3458 (!Subtarget->getTargetTriple().isMacOSX() ||
3459 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3460 // PC-relative references to external symbols should go through $stub,
3461 // unless we're building with the leopard linker or later, which
3462 // automatically synthesizes these stubs.
3463 OpFlags = X86II::MO_DARWIN_STUB;
3466 Callee = DAG.getTargetExternalSymbol(
3467 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3468 } else if (Subtarget->isTarget64BitILP32() &&
3469 Callee->getValueType(0) == MVT::i32) {
3470 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3471 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3474 // Returns a chain & a flag for retval copy to use.
3475 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3476 SmallVector<SDValue, 8> Ops;
3478 if (!IsSibcall && isTailCall) {
3479 Chain = DAG.getCALLSEQ_END(Chain,
3480 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3481 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3482 InFlag = Chain.getValue(1);
3485 Ops.push_back(Chain);
3486 Ops.push_back(Callee);
3489 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3491 // Add argument registers to the end of the list so that they are known live
3493 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3494 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3495 RegsToPass[i].second.getValueType()));
3497 // Add a register mask operand representing the call-preserved registers.
3498 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3499 assert(Mask && "Missing call preserved mask for calling convention");
3501 // If this is an invoke in a 32-bit function using a funclet-based
3502 // personality, assume the function clobbers all registers. If an exception
3503 // is thrown, the runtime will not restore CSRs.
3504 // FIXME: Model this more precisely so that we can register allocate across
3505 // the normal edge and spill and fill across the exceptional edge.
3506 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3507 const Function *CallerFn = MF.getFunction();
3508 EHPersonality Pers =
3509 CallerFn->hasPersonalityFn()
3510 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3511 : EHPersonality::Unknown;
3512 if (isFuncletEHPersonality(Pers))
3513 Mask = RegInfo->getNoPreservedMask();
3516 Ops.push_back(DAG.getRegisterMask(Mask));
3518 if (InFlag.getNode())
3519 Ops.push_back(InFlag);
3523 //// If this is the first return lowered for this function, add the regs
3524 //// to the liveout set for the function.
3525 // This isn't right, although it's probably harmless on x86; liveouts
3526 // should be computed from returns not tail calls. Consider a void
3527 // function making a tail call to a function returning int.
3528 MF.getFrameInfo()->setHasTailCall();
3529 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3532 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3533 InFlag = Chain.getValue(1);
3535 // Create the CALLSEQ_END node.
3536 unsigned NumBytesForCalleeToPop;
3537 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3538 DAG.getTarget().Options.GuaranteedTailCallOpt))
3539 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3540 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3541 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3542 SR == StackStructReturn)
3543 // If this is a call to a struct-return function, the callee
3544 // pops the hidden struct pointer, so we have to push it back.
3545 // This is common for Darwin/X86, Linux & Mingw32 targets.
3546 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3547 NumBytesForCalleeToPop = 4;
3549 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3551 // Returns a flag for retval copy to use.
3553 Chain = DAG.getCALLSEQ_END(Chain,
3554 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3555 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3558 InFlag = Chain.getValue(1);
3561 // Handle result values, copying them out of physregs into vregs that we
3563 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3564 Ins, dl, DAG, InVals);
3567 //===----------------------------------------------------------------------===//
3568 // Fast Calling Convention (tail call) implementation
3569 //===----------------------------------------------------------------------===//
3571 // Like std call, callee cleans arguments, convention except that ECX is
3572 // reserved for storing the tail called function address. Only 2 registers are
3573 // free for argument passing (inreg). Tail call optimization is performed
3575 // * tailcallopt is enabled
3576 // * caller/callee are fastcc
3577 // On X86_64 architecture with GOT-style position independent code only local
3578 // (within module) calls are supported at the moment.
3579 // To keep the stack aligned according to platform abi the function
3580 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3581 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3582 // If a tail called function callee has more arguments than the caller the
3583 // caller needs to make sure that there is room to move the RETADDR to. This is
3584 // achieved by reserving an area the size of the argument delta right after the
3585 // original RETADDR, but before the saved framepointer or the spilled registers
3586 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3598 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3601 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3602 SelectionDAG& DAG) const {
3603 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3604 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3605 unsigned StackAlignment = TFI.getStackAlignment();
3606 uint64_t AlignMask = StackAlignment - 1;
3607 int64_t Offset = StackSize;
3608 unsigned SlotSize = RegInfo->getSlotSize();
3609 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3610 // Number smaller than 12 so just add the difference.
3611 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3613 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3614 Offset = ((~AlignMask) & Offset) + StackAlignment +
3615 (StackAlignment-SlotSize);
3620 /// Return true if the given stack call argument is already available in the
3621 /// same position (relatively) of the caller's incoming argument stack.
3623 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3624 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3625 const X86InstrInfo *TII) {
3626 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3628 if (Arg.getOpcode() == ISD::CopyFromReg) {
3629 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3630 if (!TargetRegisterInfo::isVirtualRegister(VR))
3632 MachineInstr *Def = MRI->getVRegDef(VR);
3635 if (!Flags.isByVal()) {
3636 if (!TII->isLoadFromStackSlot(Def, FI))
3639 unsigned Opcode = Def->getOpcode();
3640 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3641 Opcode == X86::LEA64_32r) &&
3642 Def->getOperand(1).isFI()) {
3643 FI = Def->getOperand(1).getIndex();
3644 Bytes = Flags.getByValSize();
3648 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3649 if (Flags.isByVal())
3650 // ByVal argument is passed in as a pointer but it's now being
3651 // dereferenced. e.g.
3652 // define @foo(%struct.X* %A) {
3653 // tail call @bar(%struct.X* byval %A)
3656 SDValue Ptr = Ld->getBasePtr();
3657 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3660 FI = FINode->getIndex();
3661 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3662 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3663 FI = FINode->getIndex();
3664 Bytes = Flags.getByValSize();
3668 assert(FI != INT_MAX);
3669 if (!MFI->isFixedObjectIndex(FI))
3671 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3674 /// Check whether the call is eligible for tail call optimization. Targets
3675 /// that want to do tail call optimization should implement this function.
3676 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3677 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3678 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3679 const SmallVectorImpl<ISD::OutputArg> &Outs,
3680 const SmallVectorImpl<SDValue> &OutVals,
3681 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3682 if (!mayTailCallThisCC(CalleeCC))
3685 // If -tailcallopt is specified, make fastcc functions tail-callable.
3686 MachineFunction &MF = DAG.getMachineFunction();
3687 const Function *CallerF = MF.getFunction();
3689 // If the function return type is x86_fp80 and the callee return type is not,
3690 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3691 // perform a tailcall optimization here.
3692 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3695 CallingConv::ID CallerCC = CallerF->getCallingConv();
3696 bool CCMatch = CallerCC == CalleeCC;
3697 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3698 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3700 // Win64 functions have extra shadow space for argument homing. Don't do the
3701 // sibcall if the caller and callee have mismatched expectations for this
3703 if (IsCalleeWin64 != IsCallerWin64)
3706 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3707 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3712 // Look for obvious safe cases to perform tail call optimization that do not
3713 // require ABI changes. This is what gcc calls sibcall.
3715 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3716 // emit a special epilogue.
3717 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3718 if (RegInfo->needsStackRealignment(MF))
3721 // Also avoid sibcall optimization if either caller or callee uses struct
3722 // return semantics.
3723 if (isCalleeStructRet || isCallerStructRet)
3726 // Do not sibcall optimize vararg calls unless all arguments are passed via
3728 if (isVarArg && !Outs.empty()) {
3729 // Optimizing for varargs on Win64 is unlikely to be safe without
3730 // additional testing.
3731 if (IsCalleeWin64 || IsCallerWin64)
3734 SmallVector<CCValAssign, 16> ArgLocs;
3735 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3738 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3739 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3740 if (!ArgLocs[i].isRegLoc())
3744 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3745 // stack. Therefore, if it's not used by the call it is not safe to optimize
3746 // this into a sibcall.
3747 bool Unused = false;
3748 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3755 SmallVector<CCValAssign, 16> RVLocs;
3756 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3758 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3759 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3760 CCValAssign &VA = RVLocs[i];
3761 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3766 // If the calling conventions do not match, then we'd better make sure the
3767 // results are returned in the same way as what the caller expects.
3769 SmallVector<CCValAssign, 16> RVLocs1;
3770 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3772 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3774 SmallVector<CCValAssign, 16> RVLocs2;
3775 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3777 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3779 if (RVLocs1.size() != RVLocs2.size())
3781 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3782 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3784 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3786 if (RVLocs1[i].isRegLoc()) {
3787 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3790 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3796 unsigned StackArgsSize = 0;
3798 // If the callee takes no arguments then go on to check the results of the
3800 if (!Outs.empty()) {
3801 // Check if stack adjustment is needed. For now, do not do this if any
3802 // argument is passed on the stack.
3803 SmallVector<CCValAssign, 16> ArgLocs;
3804 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3807 // Allocate shadow area for Win64
3809 CCInfo.AllocateStack(32, 8);
3811 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3812 StackArgsSize = CCInfo.getNextStackOffset();
3814 if (CCInfo.getNextStackOffset()) {
3815 // Check if the arguments are already laid out in the right way as
3816 // the caller's fixed stack objects.
3817 MachineFrameInfo *MFI = MF.getFrameInfo();
3818 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3819 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3820 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3821 CCValAssign &VA = ArgLocs[i];
3822 SDValue Arg = OutVals[i];
3823 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3824 if (VA.getLocInfo() == CCValAssign::Indirect)
3826 if (!VA.isRegLoc()) {
3827 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3834 // If the tailcall address may be in a register, then make sure it's
3835 // possible to register allocate for it. In 32-bit, the call address can
3836 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3837 // callee-saved registers are restored. These happen to be the same
3838 // registers used to pass 'inreg' arguments so watch out for those.
3839 if (!Subtarget->is64Bit() &&
3840 ((!isa<GlobalAddressSDNode>(Callee) &&
3841 !isa<ExternalSymbolSDNode>(Callee)) ||
3842 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3843 unsigned NumInRegs = 0;
3844 // In PIC we need an extra register to formulate the address computation
3846 unsigned MaxInRegs =
3847 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3849 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3850 CCValAssign &VA = ArgLocs[i];
3853 unsigned Reg = VA.getLocReg();
3856 case X86::EAX: case X86::EDX: case X86::ECX:
3857 if (++NumInRegs == MaxInRegs)
3865 bool CalleeWillPop =
3866 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3867 MF.getTarget().Options.GuaranteedTailCallOpt);
3869 if (unsigned BytesToPop =
3870 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3871 // If we have bytes to pop, the callee must pop them.
3872 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3873 if (!CalleePopMatches)
3875 } else if (CalleeWillPop && StackArgsSize > 0) {
3876 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3884 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3885 const TargetLibraryInfo *libInfo) const {
3886 return X86::createFastISel(funcInfo, libInfo);
3889 //===----------------------------------------------------------------------===//
3890 // Other Lowering Hooks
3891 //===----------------------------------------------------------------------===//
3893 static bool MayFoldLoad(SDValue Op) {
3894 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3897 static bool MayFoldIntoStore(SDValue Op) {
3898 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3901 static bool isTargetShuffle(unsigned Opcode) {
3903 default: return false;
3904 case X86ISD::BLENDI:
3905 case X86ISD::PSHUFB:
3906 case X86ISD::PSHUFD:
3907 case X86ISD::PSHUFHW:
3908 case X86ISD::PSHUFLW:
3910 case X86ISD::PALIGNR:
3911 case X86ISD::MOVLHPS:
3912 case X86ISD::MOVLHPD:
3913 case X86ISD::MOVHLPS:
3914 case X86ISD::MOVLPS:
3915 case X86ISD::MOVLPD:
3916 case X86ISD::MOVSHDUP:
3917 case X86ISD::MOVSLDUP:
3918 case X86ISD::MOVDDUP:
3921 case X86ISD::UNPCKL:
3922 case X86ISD::UNPCKH:
3923 case X86ISD::VPERMILPI:
3924 case X86ISD::VPERM2X128:
3925 case X86ISD::VPERMI:
3926 case X86ISD::VPERMV:
3927 case X86ISD::VPERMV3:
3932 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3933 SDValue V1, unsigned TargetMask,
3934 SelectionDAG &DAG) {
3936 default: llvm_unreachable("Unknown x86 shuffle node");
3937 case X86ISD::PSHUFD:
3938 case X86ISD::PSHUFHW:
3939 case X86ISD::PSHUFLW:
3940 case X86ISD::VPERMILPI:
3941 case X86ISD::VPERMI:
3942 return DAG.getNode(Opc, dl, VT, V1,
3943 DAG.getConstant(TargetMask, dl, MVT::i8));
3947 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3948 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3950 default: llvm_unreachable("Unknown x86 shuffle node");
3951 case X86ISD::MOVLHPS:
3952 case X86ISD::MOVLHPD:
3953 case X86ISD::MOVHLPS:
3954 case X86ISD::MOVLPS:
3955 case X86ISD::MOVLPD:
3958 case X86ISD::UNPCKL:
3959 case X86ISD::UNPCKH:
3960 return DAG.getNode(Opc, dl, VT, V1, V2);
3964 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3965 MachineFunction &MF = DAG.getMachineFunction();
3966 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3967 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3968 int ReturnAddrIndex = FuncInfo->getRAIndex();
3970 if (ReturnAddrIndex == 0) {
3971 // Set up a frame object for the return address.
3972 unsigned SlotSize = RegInfo->getSlotSize();
3973 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3976 FuncInfo->setRAIndex(ReturnAddrIndex);
3979 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3982 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3983 bool hasSymbolicDisplacement) {
3984 // Offset should fit into 32 bit immediate field.
3985 if (!isInt<32>(Offset))
3988 // If we don't have a symbolic displacement - we don't have any extra
3990 if (!hasSymbolicDisplacement)
3993 // FIXME: Some tweaks might be needed for medium code model.
3994 if (M != CodeModel::Small && M != CodeModel::Kernel)
3997 // For small code model we assume that latest object is 16MB before end of 31
3998 // bits boundary. We may also accept pretty large negative constants knowing
3999 // that all objects are in the positive half of address space.
4000 if (M == CodeModel::Small && Offset < 16*1024*1024)
4003 // For kernel code model we know that all object resist in the negative half
4004 // of 32bits address space. We may not accept negative offsets, since they may
4005 // be just off and we may accept pretty large positive ones.
4006 if (M == CodeModel::Kernel && Offset >= 0)
4012 /// Determines whether the callee is required to pop its own arguments.
4013 /// Callee pop is necessary to support tail calls.
4014 bool X86::isCalleePop(CallingConv::ID CallingConv,
4015 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
4016 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
4017 // can guarantee TCO.
4018 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
4021 switch (CallingConv) {
4024 case CallingConv::X86_StdCall:
4025 case CallingConv::X86_FastCall:
4026 case CallingConv::X86_ThisCall:
4027 case CallingConv::X86_VectorCall:
4032 /// \brief Return true if the condition is an unsigned comparison operation.
4033 static bool isX86CCUnsigned(unsigned X86CC) {
4035 default: llvm_unreachable("Invalid integer condition!");
4036 case X86::COND_E: return true;
4037 case X86::COND_G: return false;
4038 case X86::COND_GE: return false;
4039 case X86::COND_L: return false;
4040 case X86::COND_LE: return false;
4041 case X86::COND_NE: return true;
4042 case X86::COND_B: return true;
4043 case X86::COND_A: return true;
4044 case X86::COND_BE: return true;
4045 case X86::COND_AE: return true;
4049 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
4050 switch (SetCCOpcode) {
4051 default: llvm_unreachable("Invalid integer condition!");
4052 case ISD::SETEQ: return X86::COND_E;
4053 case ISD::SETGT: return X86::COND_G;
4054 case ISD::SETGE: return X86::COND_GE;
4055 case ISD::SETLT: return X86::COND_L;
4056 case ISD::SETLE: return X86::COND_LE;
4057 case ISD::SETNE: return X86::COND_NE;
4058 case ISD::SETULT: return X86::COND_B;
4059 case ISD::SETUGT: return X86::COND_A;
4060 case ISD::SETULE: return X86::COND_BE;
4061 case ISD::SETUGE: return X86::COND_AE;
4065 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
4066 /// condition code, returning the condition code and the LHS/RHS of the
4067 /// comparison to make.
4068 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
4069 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
4071 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4072 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
4073 // X > -1 -> X == 0, jump !sign.
4074 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4075 return X86::COND_NS;
4077 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
4078 // X < 0 -> X == 0, jump on sign.
4081 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4083 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4084 return X86::COND_LE;
4088 return TranslateIntegerX86CC(SetCCOpcode);
4091 // First determine if it is required or is profitable to flip the operands.
4093 // If LHS is a foldable load, but RHS is not, flip the condition.
4094 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4095 !ISD::isNON_EXTLoad(RHS.getNode())) {
4096 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4097 std::swap(LHS, RHS);
4100 switch (SetCCOpcode) {
4106 std::swap(LHS, RHS);
4110 // On a floating point condition, the flags are set as follows:
4112 // 0 | 0 | 0 | X > Y
4113 // 0 | 0 | 1 | X < Y
4114 // 1 | 0 | 0 | X == Y
4115 // 1 | 1 | 1 | unordered
4116 switch (SetCCOpcode) {
4117 default: llvm_unreachable("Condcode should be pre-legalized away");
4119 case ISD::SETEQ: return X86::COND_E;
4120 case ISD::SETOLT: // flipped
4122 case ISD::SETGT: return X86::COND_A;
4123 case ISD::SETOLE: // flipped
4125 case ISD::SETGE: return X86::COND_AE;
4126 case ISD::SETUGT: // flipped
4128 case ISD::SETLT: return X86::COND_B;
4129 case ISD::SETUGE: // flipped
4131 case ISD::SETLE: return X86::COND_BE;
4133 case ISD::SETNE: return X86::COND_NE;
4134 case ISD::SETUO: return X86::COND_P;
4135 case ISD::SETO: return X86::COND_NP;
4137 case ISD::SETUNE: return X86::COND_INVALID;
4141 /// Is there a floating point cmov for the specific X86 condition code?
4142 /// Current x86 isa includes the following FP cmov instructions:
4143 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4144 static bool hasFPCMov(unsigned X86CC) {
4160 /// Returns true if the target can instruction select the
4161 /// specified FP immediate natively. If false, the legalizer will
4162 /// materialize the FP immediate as a load from a constant pool.
4163 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4164 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4165 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4171 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4172 ISD::LoadExtType ExtTy,
4174 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4175 // relocation target a movq or addq instruction: don't let the load shrink.
4176 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4177 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4178 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4179 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4183 /// \brief Returns true if it is beneficial to convert a load of a constant
4184 /// to just the constant itself.
4185 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4187 assert(Ty->isIntegerTy());
4189 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4190 if (BitSize == 0 || BitSize > 64)
4195 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4196 unsigned Index) const {
4197 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4200 return (Index == 0 || Index == ResVT.getVectorNumElements());
4203 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4204 // Speculate cttz only if we can directly use TZCNT.
4205 return Subtarget->hasBMI();
4208 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4209 // Speculate ctlz only if we can directly use LZCNT.
4210 return Subtarget->hasLZCNT();
4213 /// Return true if every element in Mask, beginning
4214 /// from position Pos and ending in Pos+Size is undef.
4215 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4216 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4222 /// Return true if Val is undef or if its value falls within the
4223 /// specified range (L, H].
4224 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4225 return (Val < 0) || (Val >= Low && Val < Hi);
4228 /// Val is either less than zero (undef) or equal to the specified value.
4229 static bool isUndefOrEqual(int Val, int CmpVal) {
4230 return (Val < 0 || Val == CmpVal);
4233 /// Return true if every element in Mask, beginning
4234 /// from position Pos and ending in Pos+Size, falls within the specified
4235 /// sequential range (Low, Low+Size]. or is undef.
4236 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4237 unsigned Pos, unsigned Size, int Low) {
4238 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4239 if (!isUndefOrEqual(Mask[i], Low))
4244 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4245 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4246 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4247 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4248 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4251 // The index should be aligned on a vecWidth-bit boundary.
4253 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4255 MVT VT = N->getSimpleValueType(0);
4256 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4257 bool Result = (Index * ElSize) % vecWidth == 0;
4262 /// Return true if the specified INSERT_SUBVECTOR
4263 /// operand specifies a subvector insert that is suitable for input to
4264 /// insertion of 128 or 256-bit subvectors
4265 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4266 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4267 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4269 // The index should be aligned on a vecWidth-bit boundary.
4271 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4273 MVT VT = N->getSimpleValueType(0);
4274 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4275 bool Result = (Index * ElSize) % vecWidth == 0;
4280 bool X86::isVINSERT128Index(SDNode *N) {
4281 return isVINSERTIndex(N, 128);
4284 bool X86::isVINSERT256Index(SDNode *N) {
4285 return isVINSERTIndex(N, 256);
4288 bool X86::isVEXTRACT128Index(SDNode *N) {
4289 return isVEXTRACTIndex(N, 128);
4292 bool X86::isVEXTRACT256Index(SDNode *N) {
4293 return isVEXTRACTIndex(N, 256);
4296 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4297 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4298 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4299 "Illegal extract subvector for VEXTRACT");
4302 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4304 MVT VecVT = N->getOperand(0).getSimpleValueType();
4305 MVT ElVT = VecVT.getVectorElementType();
4307 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4308 return Index / NumElemsPerChunk;
4311 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4312 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4313 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4314 "Illegal insert subvector for VINSERT");
4317 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4319 MVT VecVT = N->getSimpleValueType(0);
4320 MVT ElVT = VecVT.getVectorElementType();
4322 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4323 return Index / NumElemsPerChunk;
4326 /// Return the appropriate immediate to extract the specified
4327 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4328 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4329 return getExtractVEXTRACTImmediate(N, 128);
4332 /// Return the appropriate immediate to extract the specified
4333 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4334 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4335 return getExtractVEXTRACTImmediate(N, 256);
4338 /// Return the appropriate immediate to insert at the specified
4339 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4340 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4341 return getInsertVINSERTImmediate(N, 128);
4344 /// Return the appropriate immediate to insert at the specified
4345 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4346 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4347 return getInsertVINSERTImmediate(N, 256);
4350 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4351 bool X86::isZeroNode(SDValue Elt) {
4352 return isNullConstant(Elt) || isNullFPConstant(Elt);
4355 // Build a vector of constants
4356 // Use an UNDEF node if MaskElt == -1.
4357 // Spilt 64-bit constants in the 32-bit mode.
4358 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4360 SDLoc dl, bool IsMask = false) {
4362 SmallVector<SDValue, 32> Ops;
4365 MVT ConstVecVT = VT;
4366 unsigned NumElts = VT.getVectorNumElements();
4367 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4368 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4369 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4373 MVT EltVT = ConstVecVT.getVectorElementType();
4374 for (unsigned i = 0; i < NumElts; ++i) {
4375 bool IsUndef = Values[i] < 0 && IsMask;
4376 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4377 DAG.getConstant(Values[i], dl, EltVT);
4378 Ops.push_back(OpNode);
4380 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4381 DAG.getConstant(0, dl, EltVT));
4383 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4385 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4389 /// Returns a vector of specified type with all zero elements.
4390 static SDValue getZeroVector(MVT VT, const X86Subtarget *Subtarget,
4391 SelectionDAG &DAG, SDLoc dl) {
4392 assert(VT.isVector() && "Expected a vector type");
4394 // Always build SSE zero vectors as <4 x i32> bitcasted
4395 // to their dest type. This ensures they get CSE'd.
4397 if (VT.is128BitVector()) { // SSE
4398 if (Subtarget->hasSSE2()) { // SSE2
4399 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4400 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4402 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4403 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4405 } else if (VT.is256BitVector()) { // AVX
4406 if (Subtarget->hasInt256()) { // AVX2
4407 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4408 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4409 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4411 // 256-bit logic and arithmetic instructions in AVX are all
4412 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4413 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4414 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4415 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4417 } else if (VT.is512BitVector()) { // AVX-512
4418 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4419 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4420 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4421 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4422 } else if (VT.getVectorElementType() == MVT::i1) {
4424 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4425 && "Unexpected vector type");
4426 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4427 && "Unexpected vector type");
4428 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4429 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4430 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4432 llvm_unreachable("Unexpected vector type");
4434 return DAG.getBitcast(VT, Vec);
4437 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4438 SelectionDAG &DAG, SDLoc dl,
4439 unsigned vectorWidth) {
4440 assert((vectorWidth == 128 || vectorWidth == 256) &&
4441 "Unsupported vector width");
4442 EVT VT = Vec.getValueType();
4443 EVT ElVT = VT.getVectorElementType();
4444 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4445 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4446 VT.getVectorNumElements()/Factor);
4448 // Extract from UNDEF is UNDEF.
4449 if (Vec.getOpcode() == ISD::UNDEF)
4450 return DAG.getUNDEF(ResultVT);
4452 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4453 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4454 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4456 // This is the index of the first element of the vectorWidth-bit chunk
4457 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4458 IdxVal &= ~(ElemsPerChunk - 1);
4460 // If the input is a buildvector just emit a smaller one.
4461 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4462 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4463 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4465 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4466 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4469 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4470 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4471 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4472 /// instructions or a simple subregister reference. Idx is an index in the
4473 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4474 /// lowering EXTRACT_VECTOR_ELT operations easier.
4475 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4476 SelectionDAG &DAG, SDLoc dl) {
4477 assert((Vec.getValueType().is256BitVector() ||
4478 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4479 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4482 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4483 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4484 SelectionDAG &DAG, SDLoc dl) {
4485 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4486 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4489 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4490 unsigned IdxVal, SelectionDAG &DAG,
4491 SDLoc dl, unsigned vectorWidth) {
4492 assert((vectorWidth == 128 || vectorWidth == 256) &&
4493 "Unsupported vector width");
4494 // Inserting UNDEF is Result
4495 if (Vec.getOpcode() == ISD::UNDEF)
4497 EVT VT = Vec.getValueType();
4498 EVT ElVT = VT.getVectorElementType();
4499 EVT ResultVT = Result.getValueType();
4501 // Insert the relevant vectorWidth bits.
4502 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4503 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4505 // This is the index of the first element of the vectorWidth-bit chunk
4506 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4507 IdxVal &= ~(ElemsPerChunk - 1);
4509 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4510 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4513 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4514 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4515 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4516 /// simple superregister reference. Idx is an index in the 128 bits
4517 /// we want. It need not be aligned to a 128-bit boundary. That makes
4518 /// lowering INSERT_VECTOR_ELT operations easier.
4519 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4520 SelectionDAG &DAG, SDLoc dl) {
4521 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4523 // For insertion into the zero index (low half) of a 256-bit vector, it is
4524 // more efficient to generate a blend with immediate instead of an insert*128.
4525 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4526 // extend the subvector to the size of the result vector. Make sure that
4527 // we are not recursing on that node by checking for undef here.
4528 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4529 Result.getOpcode() != ISD::UNDEF) {
4530 EVT ResultVT = Result.getValueType();
4531 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4532 SDValue Undef = DAG.getUNDEF(ResultVT);
4533 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4536 // The blend instruction, and therefore its mask, depend on the data type.
4537 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4538 if (ScalarType.isFloatingPoint()) {
4539 // Choose either vblendps (float) or vblendpd (double).
4540 unsigned ScalarSize = ScalarType.getSizeInBits();
4541 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4542 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4543 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4544 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4547 const X86Subtarget &Subtarget =
4548 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4550 // AVX2 is needed for 256-bit integer blend support.
4551 // Integers must be cast to 32-bit because there is only vpblendd;
4552 // vpblendw can't be used for this because it has a handicapped mask.
4554 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4555 // is still more efficient than using the wrong domain vinsertf128 that
4556 // will be created by InsertSubVector().
4557 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4559 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4560 Result = DAG.getBitcast(CastVT, Result);
4561 Vec256 = DAG.getBitcast(CastVT, Vec256);
4562 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4563 return DAG.getBitcast(ResultVT, Vec256);
4566 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4569 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4570 SelectionDAG &DAG, SDLoc dl) {
4571 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4572 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4575 /// Insert i1-subvector to i1-vector.
4576 static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
4579 SDValue Vec = Op.getOperand(0);
4580 SDValue SubVec = Op.getOperand(1);
4581 SDValue Idx = Op.getOperand(2);
4583 if (!isa<ConstantSDNode>(Idx))
4586 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4587 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4590 MVT OpVT = Op.getSimpleValueType();
4591 MVT SubVecVT = SubVec.getSimpleValueType();
4592 unsigned NumElems = OpVT.getVectorNumElements();
4593 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
4595 assert(IdxVal + SubVecNumElems <= NumElems &&
4596 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4597 "Unexpected index value in INSERT_SUBVECTOR");
4599 // There are 3 possible cases:
4600 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
4601 // 2. Subvector should be inserted in the upper part
4602 // (IdxVal + SubVecNumElems == NumElems)
4603 // 3. Subvector should be inserted in the middle (for example v2i1
4604 // to v16i1, index 2)
4606 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
4607 SDValue Undef = DAG.getUNDEF(OpVT);
4608 SDValue WideSubVec =
4609 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);
4611 return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4612 DAG.getConstant(IdxVal, dl, MVT::i8));
4614 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
4615 unsigned ShiftLeft = NumElems - SubVecNumElems;
4616 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4617 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4618 DAG.getConstant(ShiftLeft, dl, MVT::i8));
4619 return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,
4620 DAG.getConstant(ShiftRight, dl, MVT::i8)) : WideSubVec;
4624 // Zero lower bits of the Vec
4625 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4626 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4627 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4628 // Merge them together
4629 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4632 // Simple case when we put subvector in the upper part
4633 if (IdxVal + SubVecNumElems == NumElems) {
4634 // Zero upper bits of the Vec
4635 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,
4636 DAG.getConstant(IdxVal, dl, MVT::i8));
4637 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4638 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4639 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4640 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4642 // Subvector should be inserted in the middle - use shuffle
4643 SmallVector<int, 64> Mask;
4644 for (unsigned i = 0; i < NumElems; ++i)
4645 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
4647 return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);
4650 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4651 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4652 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4653 /// large BUILD_VECTORS.
4654 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4655 unsigned NumElems, SelectionDAG &DAG,
4657 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4658 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4661 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4662 unsigned NumElems, SelectionDAG &DAG,
4664 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4665 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4668 /// Returns a vector of specified type with all bits set.
4669 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4670 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4671 /// Then bitcast to their original type, ensuring they get CSE'd.
4672 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4673 SelectionDAG &DAG, SDLoc dl) {
4674 assert(VT.isVector() && "Expected a vector type");
4676 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4678 if (VT.is512BitVector()) {
4679 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4680 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4681 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4682 } else if (VT.is256BitVector()) {
4683 if (Subtarget->hasInt256()) { // AVX2
4684 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4685 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4687 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4688 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4690 } else if (VT.is128BitVector()) {
4691 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4693 llvm_unreachable("Unexpected vector type");
4695 return DAG.getBitcast(VT, Vec);
4698 /// Returns a vector_shuffle node for an unpackl operation.
4699 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4701 unsigned NumElems = VT.getVectorNumElements();
4702 SmallVector<int, 8> Mask;
4703 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4705 Mask.push_back(i + NumElems);
4707 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4710 /// Returns a vector_shuffle node for an unpackh operation.
4711 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4713 unsigned NumElems = VT.getVectorNumElements();
4714 SmallVector<int, 8> Mask;
4715 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4716 Mask.push_back(i + Half);
4717 Mask.push_back(i + NumElems + Half);
4719 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4722 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4723 /// This produces a shuffle where the low element of V2 is swizzled into the
4724 /// zero/undef vector, landing at element Idx.
4725 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4726 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4728 const X86Subtarget *Subtarget,
4729 SelectionDAG &DAG) {
4730 MVT VT = V2.getSimpleValueType();
4732 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4733 unsigned NumElems = VT.getVectorNumElements();
4734 SmallVector<int, 16> MaskVec;
4735 for (unsigned i = 0; i != NumElems; ++i)
4736 // If this is the insertion idx, put the low elt of V2 here.
4737 MaskVec.push_back(i == Idx ? NumElems : i);
4738 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4741 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4742 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4743 /// uses one source. Note that this will set IsUnary for shuffles which use a
4744 /// single input multiple times, and in those cases it will
4745 /// adjust the mask to only have indices within that single input.
4746 static bool getTargetShuffleMask(SDNode *N, MVT VT, bool AllowSentinelZero,
4747 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4748 unsigned NumElems = VT.getVectorNumElements();
4752 bool IsFakeUnary = false;
4753 switch(N->getOpcode()) {
4754 case X86ISD::BLENDI:
4755 ImmN = N->getOperand(N->getNumOperands()-1);
4756 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4759 ImmN = N->getOperand(N->getNumOperands()-1);
4760 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4761 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4763 case X86ISD::UNPCKH:
4764 DecodeUNPCKHMask(VT, Mask);
4765 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4767 case X86ISD::UNPCKL:
4768 DecodeUNPCKLMask(VT, Mask);
4769 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4771 case X86ISD::MOVHLPS:
4772 DecodeMOVHLPSMask(NumElems, Mask);
4773 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4775 case X86ISD::MOVLHPS:
4776 DecodeMOVLHPSMask(NumElems, Mask);
4777 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4779 case X86ISD::PALIGNR:
4780 ImmN = N->getOperand(N->getNumOperands()-1);
4781 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4783 case X86ISD::PSHUFD:
4784 case X86ISD::VPERMILPI:
4785 ImmN = N->getOperand(N->getNumOperands()-1);
4786 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4789 case X86ISD::PSHUFHW:
4790 ImmN = N->getOperand(N->getNumOperands()-1);
4791 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4794 case X86ISD::PSHUFLW:
4795 ImmN = N->getOperand(N->getNumOperands()-1);
4796 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4799 case X86ISD::PSHUFB: {
4801 SDValue MaskNode = N->getOperand(1);
4802 while (MaskNode->getOpcode() == ISD::BITCAST)
4803 MaskNode = MaskNode->getOperand(0);
4805 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4806 // If we have a build-vector, then things are easy.
4807 MVT VT = MaskNode.getSimpleValueType();
4808 assert(VT.isVector() &&
4809 "Can't produce a non-vector with a build_vector!");
4810 if (!VT.isInteger())
4813 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4815 SmallVector<uint64_t, 32> RawMask;
4816 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4817 SDValue Op = MaskNode->getOperand(i);
4818 if (Op->getOpcode() == ISD::UNDEF) {
4819 RawMask.push_back((uint64_t)SM_SentinelUndef);
4822 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4825 APInt MaskElement = CN->getAPIntValue();
4827 // We now have to decode the element which could be any integer size and
4828 // extract each byte of it.
4829 for (int j = 0; j < NumBytesPerElement; ++j) {
4830 // Note that this is x86 and so always little endian: the low byte is
4831 // the first byte of the mask.
4832 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4833 MaskElement = MaskElement.lshr(8);
4836 DecodePSHUFBMask(RawMask, Mask);
4840 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4844 SDValue Ptr = MaskLoad->getBasePtr();
4845 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4846 Ptr->getOpcode() == X86ISD::WrapperRIP)
4847 Ptr = Ptr->getOperand(0);
4849 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4850 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4853 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4854 DecodePSHUFBMask(C, Mask);
4860 case X86ISD::VPERMI:
4861 ImmN = N->getOperand(N->getNumOperands()-1);
4862 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4867 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4869 case X86ISD::VPERM2X128:
4870 ImmN = N->getOperand(N->getNumOperands()-1);
4871 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4872 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4874 case X86ISD::MOVSLDUP:
4875 DecodeMOVSLDUPMask(VT, Mask);
4878 case X86ISD::MOVSHDUP:
4879 DecodeMOVSHDUPMask(VT, Mask);
4882 case X86ISD::MOVDDUP:
4883 DecodeMOVDDUPMask(VT, Mask);
4886 case X86ISD::MOVLHPD:
4887 case X86ISD::MOVLPD:
4888 case X86ISD::MOVLPS:
4889 // Not yet implemented
4891 case X86ISD::VPERMV: {
4893 SDValue MaskNode = N->getOperand(0);
4894 while (MaskNode->getOpcode() == ISD::BITCAST)
4895 MaskNode = MaskNode->getOperand(0);
4897 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4898 SmallVector<uint64_t, 32> RawMask;
4899 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4900 // If we have a build-vector, then things are easy.
4901 assert(MaskNode.getSimpleValueType().isInteger() &&
4902 MaskNode.getSimpleValueType().getVectorNumElements() ==
4903 VT.getVectorNumElements());
4905 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4906 SDValue Op = MaskNode->getOperand(i);
4907 if (Op->getOpcode() == ISD::UNDEF)
4908 RawMask.push_back((uint64_t)SM_SentinelUndef);
4909 else if (isa<ConstantSDNode>(Op)) {
4910 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4911 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4915 DecodeVPERMVMask(RawMask, Mask);
4918 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4919 unsigned NumEltsInMask = MaskNode->getNumOperands();
4920 MaskNode = MaskNode->getOperand(0);
4921 if (auto *CN = dyn_cast<ConstantSDNode>(MaskNode)) {
4922 APInt MaskEltValue = CN->getAPIntValue();
4923 for (unsigned i = 0; i < NumEltsInMask; ++i)
4924 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4925 DecodeVPERMVMask(RawMask, Mask);
4928 // It may be a scalar load
4931 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4935 SDValue Ptr = MaskLoad->getBasePtr();
4936 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4937 Ptr->getOpcode() == X86ISD::WrapperRIP)
4938 Ptr = Ptr->getOperand(0);
4940 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4941 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4944 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4945 DecodeVPERMVMask(C, VT, Mask);
4950 case X86ISD::VPERMV3: {
4952 SDValue MaskNode = N->getOperand(1);
4953 while (MaskNode->getOpcode() == ISD::BITCAST)
4954 MaskNode = MaskNode->getOperand(1);
4956 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4957 // If we have a build-vector, then things are easy.
4958 assert(MaskNode.getSimpleValueType().isInteger() &&
4959 MaskNode.getSimpleValueType().getVectorNumElements() ==
4960 VT.getVectorNumElements());
4962 SmallVector<uint64_t, 32> RawMask;
4963 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4965 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4966 SDValue Op = MaskNode->getOperand(i);
4967 if (Op->getOpcode() == ISD::UNDEF)
4968 RawMask.push_back((uint64_t)SM_SentinelUndef);
4970 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4973 APInt MaskElement = CN->getAPIntValue();
4974 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4977 DecodeVPERMV3Mask(RawMask, Mask);
4981 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4985 SDValue Ptr = MaskLoad->getBasePtr();
4986 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4987 Ptr->getOpcode() == X86ISD::WrapperRIP)
4988 Ptr = Ptr->getOperand(0);
4990 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4991 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4994 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4995 DecodeVPERMV3Mask(C, VT, Mask);
5000 default: llvm_unreachable("unknown target shuffle node");
5003 // Empty mask indicates the decode failed.
5007 // Check if we're getting a shuffle mask with zero'd elements.
5008 if (!AllowSentinelZero)
5009 if (std::any_of(Mask.begin(), Mask.end(),
5010 [](int M){ return M == SM_SentinelZero; }))
5013 // If we have a fake unary shuffle, the shuffle mask is spread across two
5014 // inputs that are actually the same node. Re-map the mask to always point
5015 // into the first input.
5018 if (M >= (int)Mask.size())
5024 /// Returns the scalar element that will make up the ith
5025 /// element of the result of the vector shuffle.
5026 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5029 return SDValue(); // Limit search depth.
5031 SDValue V = SDValue(N, 0);
5032 EVT VT = V.getValueType();
5033 unsigned Opcode = V.getOpcode();
5035 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5036 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5037 int Elt = SV->getMaskElt(Index);
5040 return DAG.getUNDEF(VT.getVectorElementType());
5042 unsigned NumElems = VT.getVectorNumElements();
5043 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5044 : SV->getOperand(1);
5045 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5048 // Recurse into target specific vector shuffles to find scalars.
5049 if (isTargetShuffle(Opcode)) {
5050 MVT ShufVT = V.getSimpleValueType();
5051 int NumElems = (int)ShufVT.getVectorNumElements();
5052 SmallVector<int, 16> ShuffleMask;
5055 if (!getTargetShuffleMask(N, ShufVT, false, ShuffleMask, IsUnary))
5058 int Elt = ShuffleMask[Index];
5059 if (Elt == SM_SentinelUndef)
5060 return DAG.getUNDEF(ShufVT.getVectorElementType());
5062 assert(0 <= Elt && Elt < (2*NumElems) && "Shuffle index out of range");
5063 SDValue NewV = (Elt < NumElems) ? N->getOperand(0) : N->getOperand(1);
5064 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5068 // Actual nodes that may contain scalar elements
5069 if (Opcode == ISD::BITCAST) {
5070 V = V.getOperand(0);
5071 EVT SrcVT = V.getValueType();
5072 unsigned NumElems = VT.getVectorNumElements();
5074 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5078 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5079 return (Index == 0) ? V.getOperand(0)
5080 : DAG.getUNDEF(VT.getVectorElementType());
5082 if (V.getOpcode() == ISD::BUILD_VECTOR)
5083 return V.getOperand(Index);
5088 /// Custom lower build_vector of v16i8.
5089 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5090 unsigned NumNonZero, unsigned NumZero,
5092 const X86Subtarget* Subtarget,
5093 const TargetLowering &TLI) {
5101 // SSE4.1 - use PINSRB to insert each byte directly.
5102 if (Subtarget->hasSSE41()) {
5103 for (unsigned i = 0; i < 16; ++i) {
5104 bool isNonZero = (NonZeros & (1 << i)) != 0;
5108 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
5110 V = DAG.getUNDEF(MVT::v16i8);
5113 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5114 MVT::v16i8, V, Op.getOperand(i),
5115 DAG.getIntPtrConstant(i, dl));
5122 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
5123 for (unsigned i = 0; i < 16; ++i) {
5124 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5125 if (ThisIsNonZero && First) {
5127 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5129 V = DAG.getUNDEF(MVT::v8i16);
5134 SDValue ThisElt, LastElt;
5135 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5136 if (LastIsNonZero) {
5137 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5138 MVT::i16, Op.getOperand(i-1));
5140 if (ThisIsNonZero) {
5141 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5142 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5143 ThisElt, DAG.getConstant(8, dl, MVT::i8));
5145 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5149 if (ThisElt.getNode())
5150 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5151 DAG.getIntPtrConstant(i/2, dl));
5155 return DAG.getBitcast(MVT::v16i8, V);
5158 /// Custom lower build_vector of v8i16.
5159 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5160 unsigned NumNonZero, unsigned NumZero,
5162 const X86Subtarget* Subtarget,
5163 const TargetLowering &TLI) {
5170 for (unsigned i = 0; i < 8; ++i) {
5171 bool isNonZero = (NonZeros & (1 << i)) != 0;
5175 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5177 V = DAG.getUNDEF(MVT::v8i16);
5180 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5181 MVT::v8i16, V, Op.getOperand(i),
5182 DAG.getIntPtrConstant(i, dl));
5189 /// Custom lower build_vector of v4i32 or v4f32.
5190 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5191 const X86Subtarget *Subtarget,
5192 const TargetLowering &TLI) {
5193 // Find all zeroable elements.
5194 std::bitset<4> Zeroable;
5195 for (int i=0; i < 4; ++i) {
5196 SDValue Elt = Op->getOperand(i);
5197 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5199 assert(Zeroable.size() - Zeroable.count() > 1 &&
5200 "We expect at least two non-zero elements!");
5202 // We only know how to deal with build_vector nodes where elements are either
5203 // zeroable or extract_vector_elt with constant index.
5204 SDValue FirstNonZero;
5205 unsigned FirstNonZeroIdx;
5206 for (unsigned i=0; i < 4; ++i) {
5209 SDValue Elt = Op->getOperand(i);
5210 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5211 !isa<ConstantSDNode>(Elt.getOperand(1)))
5213 // Make sure that this node is extracting from a 128-bit vector.
5214 MVT VT = Elt.getOperand(0).getSimpleValueType();
5215 if (!VT.is128BitVector())
5217 if (!FirstNonZero.getNode()) {
5219 FirstNonZeroIdx = i;
5223 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5224 SDValue V1 = FirstNonZero.getOperand(0);
5225 MVT VT = V1.getSimpleValueType();
5227 // See if this build_vector can be lowered as a blend with zero.
5229 unsigned EltMaskIdx, EltIdx;
5231 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5232 if (Zeroable[EltIdx]) {
5233 // The zero vector will be on the right hand side.
5234 Mask[EltIdx] = EltIdx+4;
5238 Elt = Op->getOperand(EltIdx);
5239 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5240 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5241 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5243 Mask[EltIdx] = EltIdx;
5247 // Let the shuffle legalizer deal with blend operations.
5248 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5249 if (V1.getSimpleValueType() != VT)
5250 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5251 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5254 // See if we can lower this build_vector to a INSERTPS.
5255 if (!Subtarget->hasSSE41())
5258 SDValue V2 = Elt.getOperand(0);
5259 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5262 bool CanFold = true;
5263 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5267 SDValue Current = Op->getOperand(i);
5268 SDValue SrcVector = Current->getOperand(0);
5271 CanFold = SrcVector == V1 &&
5272 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5278 assert(V1.getNode() && "Expected at least two non-zero elements!");
5279 if (V1.getSimpleValueType() != MVT::v4f32)
5280 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5281 if (V2.getSimpleValueType() != MVT::v4f32)
5282 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5284 // Ok, we can emit an INSERTPS instruction.
5285 unsigned ZMask = Zeroable.to_ulong();
5287 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5288 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5290 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5291 DAG.getIntPtrConstant(InsertPSMask, DL));
5292 return DAG.getBitcast(VT, Result);
5295 /// Return a vector logical shift node.
5296 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5297 unsigned NumBits, SelectionDAG &DAG,
5298 const TargetLowering &TLI, SDLoc dl) {
5299 assert(VT.is128BitVector() && "Unknown type for VShift");
5300 MVT ShVT = MVT::v2i64;
5301 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5302 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5303 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5304 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5305 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5306 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5310 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5312 // Check if the scalar load can be widened into a vector load. And if
5313 // the address is "base + cst" see if the cst can be "absorbed" into
5314 // the shuffle mask.
5315 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5316 SDValue Ptr = LD->getBasePtr();
5317 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5319 EVT PVT = LD->getValueType(0);
5320 if (PVT != MVT::i32 && PVT != MVT::f32)
5325 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5326 FI = FINode->getIndex();
5328 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5329 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5330 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5331 Offset = Ptr.getConstantOperandVal(1);
5332 Ptr = Ptr.getOperand(0);
5337 // FIXME: 256-bit vector instructions don't require a strict alignment,
5338 // improve this code to support it better.
5339 unsigned RequiredAlign = VT.getSizeInBits()/8;
5340 SDValue Chain = LD->getChain();
5341 // Make sure the stack object alignment is at least 16 or 32.
5342 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5343 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5344 if (MFI->isFixedObjectIndex(FI)) {
5345 // Can't change the alignment. FIXME: It's possible to compute
5346 // the exact stack offset and reference FI + adjust offset instead.
5347 // If someone *really* cares about this. That's the way to implement it.
5350 MFI->setObjectAlignment(FI, RequiredAlign);
5354 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5355 // Ptr + (Offset & ~15).
5358 if ((Offset % RequiredAlign) & 3)
5360 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5363 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5364 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5367 int EltNo = (Offset - StartOffset) >> 2;
5368 unsigned NumElems = VT.getVectorNumElements();
5370 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5371 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5372 LD->getPointerInfo().getWithOffset(StartOffset),
5373 false, false, false, 0);
5375 SmallVector<int, 8> Mask(NumElems, EltNo);
5377 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5383 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5384 /// elements can be replaced by a single large load which has the same value as
5385 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5387 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5389 /// FIXME: we'd also like to handle the case where the last elements are zero
5390 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5391 /// There's even a handy isZeroNode for that purpose.
5392 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5393 SDLoc &DL, SelectionDAG &DAG,
5394 bool isAfterLegalize) {
5395 unsigned NumElems = Elts.size();
5397 LoadSDNode *LDBase = nullptr;
5398 unsigned LastLoadedElt = -1U;
5400 // For each element in the initializer, see if we've found a load or an undef.
5401 // If we don't find an initial load element, or later load elements are
5402 // non-consecutive, bail out.
5403 for (unsigned i = 0; i < NumElems; ++i) {
5404 SDValue Elt = Elts[i];
5405 // Look through a bitcast.
5406 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5407 Elt = Elt.getOperand(0);
5408 if (!Elt.getNode() ||
5409 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5412 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5414 LDBase = cast<LoadSDNode>(Elt.getNode());
5418 if (Elt.getOpcode() == ISD::UNDEF)
5421 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5422 EVT LdVT = Elt.getValueType();
5423 // Each loaded element must be the correct fractional portion of the
5424 // requested vector load.
5425 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5427 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5432 // If we have found an entire vector of loads and undefs, then return a large
5433 // load of the entire vector width starting at the base pointer. If we found
5434 // consecutive loads for the low half, generate a vzext_load node.
5435 if (LastLoadedElt == NumElems - 1) {
5436 assert(LDBase && "Did not find base load for merging consecutive loads");
5437 EVT EltVT = LDBase->getValueType(0);
5438 // Ensure that the input vector size for the merged loads matches the
5439 // cumulative size of the input elements.
5440 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5443 if (isAfterLegalize &&
5444 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5447 SDValue NewLd = SDValue();
5449 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5450 LDBase->getPointerInfo(), LDBase->isVolatile(),
5451 LDBase->isNonTemporal(), LDBase->isInvariant(),
5452 LDBase->getAlignment());
5454 if (LDBase->hasAnyUseOfValue(1)) {
5455 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5457 SDValue(NewLd.getNode(), 1));
5458 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5459 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5460 SDValue(NewLd.getNode(), 1));
5466 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5467 //of a v4i32 / v4f32. It's probably worth generalizing.
5468 EVT EltVT = VT.getVectorElementType();
5469 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5470 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5471 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5472 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5474 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5475 LDBase->getPointerInfo(),
5476 LDBase->getAlignment(),
5477 false/*isVolatile*/, true/*ReadMem*/,
5480 // Make sure the newly-created LOAD is in the same position as LDBase in
5481 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5482 // update uses of LDBase's output chain to use the TokenFactor.
5483 if (LDBase->hasAnyUseOfValue(1)) {
5484 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5485 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5486 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5487 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5488 SDValue(ResNode.getNode(), 1));
5491 return DAG.getBitcast(VT, ResNode);
5496 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5497 /// to generate a splat value for the following cases:
5498 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5499 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5500 /// a scalar load, or a constant.
5501 /// The VBROADCAST node is returned when a pattern is found,
5502 /// or SDValue() otherwise.
5503 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5504 SelectionDAG &DAG) {
5505 // VBROADCAST requires AVX.
5506 // TODO: Splats could be generated for non-AVX CPUs using SSE
5507 // instructions, but there's less potential gain for only 128-bit vectors.
5508 if (!Subtarget->hasAVX())
5511 MVT VT = Op.getSimpleValueType();
5514 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5515 "Unsupported vector type for broadcast.");
5520 switch (Op.getOpcode()) {
5522 // Unknown pattern found.
5525 case ISD::BUILD_VECTOR: {
5526 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5527 BitVector UndefElements;
5528 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5530 // We need a splat of a single value to use broadcast, and it doesn't
5531 // make any sense if the value is only in one element of the vector.
5532 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5536 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5537 Ld.getOpcode() == ISD::ConstantFP);
5539 // Make sure that all of the users of a non-constant load are from the
5540 // BUILD_VECTOR node.
5541 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5546 case ISD::VECTOR_SHUFFLE: {
5547 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5549 // Shuffles must have a splat mask where the first element is
5551 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5554 SDValue Sc = Op.getOperand(0);
5555 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5556 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5558 if (!Subtarget->hasInt256())
5561 // Use the register form of the broadcast instruction available on AVX2.
5562 if (VT.getSizeInBits() >= 256)
5563 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5564 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5567 Ld = Sc.getOperand(0);
5568 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5569 Ld.getOpcode() == ISD::ConstantFP);
5571 // The scalar_to_vector node and the suspected
5572 // load node must have exactly one user.
5573 // Constants may have multiple users.
5575 // AVX-512 has register version of the broadcast
5576 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5577 Ld.getValueType().getSizeInBits() >= 32;
5578 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5585 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5586 bool IsGE256 = (VT.getSizeInBits() >= 256);
5588 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5589 // instruction to save 8 or more bytes of constant pool data.
5590 // TODO: If multiple splats are generated to load the same constant,
5591 // it may be detrimental to overall size. There needs to be a way to detect
5592 // that condition to know if this is truly a size win.
5593 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5595 // Handle broadcasting a single constant scalar from the constant pool
5597 // On Sandybridge (no AVX2), it is still better to load a constant vector
5598 // from the constant pool and not to broadcast it from a scalar.
5599 // But override that restriction when optimizing for size.
5600 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5601 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5602 EVT CVT = Ld.getValueType();
5603 assert(!CVT.isVector() && "Must not broadcast a vector type");
5605 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5606 // For size optimization, also splat v2f64 and v2i64, and for size opt
5607 // with AVX2, also splat i8 and i16.
5608 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5609 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5610 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5611 const Constant *C = nullptr;
5612 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5613 C = CI->getConstantIntValue();
5614 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5615 C = CF->getConstantFPValue();
5617 assert(C && "Invalid constant type");
5619 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5621 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5622 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5624 CVT, dl, DAG.getEntryNode(), CP,
5625 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5626 false, false, Alignment);
5628 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5632 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5634 // Handle AVX2 in-register broadcasts.
5635 if (!IsLoad && Subtarget->hasInt256() &&
5636 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5637 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5639 // The scalar source must be a normal load.
5643 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5644 (Subtarget->hasVLX() && ScalarSize == 64))
5645 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5647 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5648 // double since there is no vbroadcastsd xmm
5649 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5650 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5651 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5654 // Unsupported broadcast.
5658 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5659 /// underlying vector and index.
5661 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5663 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5665 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5666 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5669 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5671 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5673 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5674 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5677 // In this case the vector is the extract_subvector expression and the index
5678 // is 2, as specified by the shuffle.
5679 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5680 SDValue ShuffleVec = SVOp->getOperand(0);
5681 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5682 assert(ShuffleVecVT.getVectorElementType() ==
5683 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5685 int ShuffleIdx = SVOp->getMaskElt(Idx);
5686 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5687 ExtractedFromVec = ShuffleVec;
5693 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5694 MVT VT = Op.getSimpleValueType();
5696 // Skip if insert_vec_elt is not supported.
5697 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5698 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5702 unsigned NumElems = Op.getNumOperands();
5706 SmallVector<unsigned, 4> InsertIndices;
5707 SmallVector<int, 8> Mask(NumElems, -1);
5709 for (unsigned i = 0; i != NumElems; ++i) {
5710 unsigned Opc = Op.getOperand(i).getOpcode();
5712 if (Opc == ISD::UNDEF)
5715 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5716 // Quit if more than 1 elements need inserting.
5717 if (InsertIndices.size() > 1)
5720 InsertIndices.push_back(i);
5724 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5725 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5726 // Quit if non-constant index.
5727 if (!isa<ConstantSDNode>(ExtIdx))
5729 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5731 // Quit if extracted from vector of different type.
5732 if (ExtractedFromVec.getValueType() != VT)
5735 if (!VecIn1.getNode())
5736 VecIn1 = ExtractedFromVec;
5737 else if (VecIn1 != ExtractedFromVec) {
5738 if (!VecIn2.getNode())
5739 VecIn2 = ExtractedFromVec;
5740 else if (VecIn2 != ExtractedFromVec)
5741 // Quit if more than 2 vectors to shuffle
5745 if (ExtractedFromVec == VecIn1)
5747 else if (ExtractedFromVec == VecIn2)
5748 Mask[i] = Idx + NumElems;
5751 if (!VecIn1.getNode())
5754 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5755 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5756 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5757 unsigned Idx = InsertIndices[i];
5758 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5759 DAG.getIntPtrConstant(Idx, DL));
5765 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5766 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5767 Op.getScalarValueSizeInBits() == 1 &&
5768 "Can not convert non-constant vector");
5769 uint64_t Immediate = 0;
5770 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5771 SDValue In = Op.getOperand(idx);
5772 if (In.getOpcode() != ISD::UNDEF)
5773 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5777 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5778 return DAG.getConstant(Immediate, dl, VT);
5780 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5782 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5784 MVT VT = Op.getSimpleValueType();
5785 assert((VT.getVectorElementType() == MVT::i1) &&
5786 "Unexpected type in LowerBUILD_VECTORvXi1!");
5789 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5790 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5791 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5792 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5795 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5796 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5797 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5798 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5801 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5802 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5803 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5804 return DAG.getBitcast(VT, Imm);
5805 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5806 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5807 DAG.getIntPtrConstant(0, dl));
5810 // Vector has one or more non-const elements
5811 uint64_t Immediate = 0;
5812 SmallVector<unsigned, 16> NonConstIdx;
5813 bool IsSplat = true;
5814 bool HasConstElts = false;
5816 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5817 SDValue In = Op.getOperand(idx);
5818 if (In.getOpcode() == ISD::UNDEF)
5820 if (!isa<ConstantSDNode>(In))
5821 NonConstIdx.push_back(idx);
5823 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5824 HasConstElts = true;
5828 else if (In != Op.getOperand(SplatIdx))
5832 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5834 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5835 DAG.getConstant(1, dl, VT),
5836 DAG.getConstant(0, dl, VT));
5838 // insert elements one by one
5842 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5843 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5845 else if (HasConstElts)
5846 Imm = DAG.getConstant(0, dl, VT);
5848 Imm = DAG.getUNDEF(VT);
5849 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5850 DstVec = DAG.getBitcast(VT, Imm);
5852 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5853 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5854 DAG.getIntPtrConstant(0, dl));
5857 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5858 unsigned InsertIdx = NonConstIdx[i];
5859 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5860 Op.getOperand(InsertIdx),
5861 DAG.getIntPtrConstant(InsertIdx, dl));
5866 /// \brief Return true if \p N implements a horizontal binop and return the
5867 /// operands for the horizontal binop into V0 and V1.
5869 /// This is a helper function of LowerToHorizontalOp().
5870 /// This function checks that the build_vector \p N in input implements a
5871 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5872 /// operation to match.
5873 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5874 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5875 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5878 /// This function only analyzes elements of \p N whose indices are
5879 /// in range [BaseIdx, LastIdx).
5880 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5882 unsigned BaseIdx, unsigned LastIdx,
5883 SDValue &V0, SDValue &V1) {
5884 EVT VT = N->getValueType(0);
5886 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5887 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5888 "Invalid Vector in input!");
5890 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5891 bool CanFold = true;
5892 unsigned ExpectedVExtractIdx = BaseIdx;
5893 unsigned NumElts = LastIdx - BaseIdx;
5894 V0 = DAG.getUNDEF(VT);
5895 V1 = DAG.getUNDEF(VT);
5897 // Check if N implements a horizontal binop.
5898 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5899 SDValue Op = N->getOperand(i + BaseIdx);
5902 if (Op->getOpcode() == ISD::UNDEF) {
5903 // Update the expected vector extract index.
5904 if (i * 2 == NumElts)
5905 ExpectedVExtractIdx = BaseIdx;
5906 ExpectedVExtractIdx += 2;
5910 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5915 SDValue Op0 = Op.getOperand(0);
5916 SDValue Op1 = Op.getOperand(1);
5918 // Try to match the following pattern:
5919 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5920 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5921 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5922 Op0.getOperand(0) == Op1.getOperand(0) &&
5923 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5924 isa<ConstantSDNode>(Op1.getOperand(1)));
5928 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5929 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5931 if (i * 2 < NumElts) {
5932 if (V0.getOpcode() == ISD::UNDEF) {
5933 V0 = Op0.getOperand(0);
5934 if (V0.getValueType() != VT)
5938 if (V1.getOpcode() == ISD::UNDEF) {
5939 V1 = Op0.getOperand(0);
5940 if (V1.getValueType() != VT)
5943 if (i * 2 == NumElts)
5944 ExpectedVExtractIdx = BaseIdx;
5947 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5948 if (I0 == ExpectedVExtractIdx)
5949 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5950 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5951 // Try to match the following dag sequence:
5952 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5953 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5957 ExpectedVExtractIdx += 2;
5963 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5964 /// a concat_vector.
5966 /// This is a helper function of LowerToHorizontalOp().
5967 /// This function expects two 256-bit vectors called V0 and V1.
5968 /// At first, each vector is split into two separate 128-bit vectors.
5969 /// Then, the resulting 128-bit vectors are used to implement two
5970 /// horizontal binary operations.
5972 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5974 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5975 /// the two new horizontal binop.
5976 /// When Mode is set, the first horizontal binop dag node would take as input
5977 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5978 /// horizontal binop dag node would take as input the lower 128-bit of V1
5979 /// and the upper 128-bit of V1.
5981 /// HADD V0_LO, V0_HI
5982 /// HADD V1_LO, V1_HI
5984 /// Otherwise, the first horizontal binop dag node takes as input the lower
5985 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5986 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5988 /// HADD V0_LO, V1_LO
5989 /// HADD V0_HI, V1_HI
5991 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5992 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5993 /// the upper 128-bits of the result.
5994 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5995 SDLoc DL, SelectionDAG &DAG,
5996 unsigned X86Opcode, bool Mode,
5997 bool isUndefLO, bool isUndefHI) {
5998 EVT VT = V0.getValueType();
5999 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6000 "Invalid nodes in input!");
6002 unsigned NumElts = VT.getVectorNumElements();
6003 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6004 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6005 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6006 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6007 EVT NewVT = V0_LO.getValueType();
6009 SDValue LO = DAG.getUNDEF(NewVT);
6010 SDValue HI = DAG.getUNDEF(NewVT);
6013 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6014 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6015 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6016 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6017 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6019 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6020 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6021 V1_LO->getOpcode() != ISD::UNDEF))
6022 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6024 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6025 V1_HI->getOpcode() != ISD::UNDEF))
6026 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6029 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6032 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
6034 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
6035 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6036 MVT VT = BV->getSimpleValueType(0);
6037 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
6038 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
6042 unsigned NumElts = VT.getVectorNumElements();
6043 SDValue InVec0 = DAG.getUNDEF(VT);
6044 SDValue InVec1 = DAG.getUNDEF(VT);
6046 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6047 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6049 // Odd-numbered elements in the input build vector are obtained from
6050 // adding two integer/float elements.
6051 // Even-numbered elements in the input build vector are obtained from
6052 // subtracting two integer/float elements.
6053 unsigned ExpectedOpcode = ISD::FSUB;
6054 unsigned NextExpectedOpcode = ISD::FADD;
6055 bool AddFound = false;
6056 bool SubFound = false;
6058 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6059 SDValue Op = BV->getOperand(i);
6061 // Skip 'undef' values.
6062 unsigned Opcode = Op.getOpcode();
6063 if (Opcode == ISD::UNDEF) {
6064 std::swap(ExpectedOpcode, NextExpectedOpcode);
6068 // Early exit if we found an unexpected opcode.
6069 if (Opcode != ExpectedOpcode)
6072 SDValue Op0 = Op.getOperand(0);
6073 SDValue Op1 = Op.getOperand(1);
6075 // Try to match the following pattern:
6076 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6077 // Early exit if we cannot match that sequence.
6078 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6079 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6080 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6081 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6082 Op0.getOperand(1) != Op1.getOperand(1))
6085 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6089 // We found a valid add/sub node. Update the information accordingly.
6095 // Update InVec0 and InVec1.
6096 if (InVec0.getOpcode() == ISD::UNDEF) {
6097 InVec0 = Op0.getOperand(0);
6098 if (InVec0.getSimpleValueType() != VT)
6101 if (InVec1.getOpcode() == ISD::UNDEF) {
6102 InVec1 = Op1.getOperand(0);
6103 if (InVec1.getSimpleValueType() != VT)
6107 // Make sure that operands in input to each add/sub node always
6108 // come from a same pair of vectors.
6109 if (InVec0 != Op0.getOperand(0)) {
6110 if (ExpectedOpcode == ISD::FSUB)
6113 // FADD is commutable. Try to commute the operands
6114 // and then test again.
6115 std::swap(Op0, Op1);
6116 if (InVec0 != Op0.getOperand(0))
6120 if (InVec1 != Op1.getOperand(0))
6123 // Update the pair of expected opcodes.
6124 std::swap(ExpectedOpcode, NextExpectedOpcode);
6127 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6128 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6129 InVec1.getOpcode() != ISD::UNDEF)
6130 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6135 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6136 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6137 const X86Subtarget *Subtarget,
6138 SelectionDAG &DAG) {
6139 MVT VT = BV->getSimpleValueType(0);
6140 unsigned NumElts = VT.getVectorNumElements();
6141 unsigned NumUndefsLO = 0;
6142 unsigned NumUndefsHI = 0;
6143 unsigned Half = NumElts/2;
6145 // Count the number of UNDEF operands in the build_vector in input.
6146 for (unsigned i = 0, e = Half; i != e; ++i)
6147 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6150 for (unsigned i = Half, e = NumElts; i != e; ++i)
6151 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6154 // Early exit if this is either a build_vector of all UNDEFs or all the
6155 // operands but one are UNDEF.
6156 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6160 SDValue InVec0, InVec1;
6161 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6162 // Try to match an SSE3 float HADD/HSUB.
6163 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6164 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6166 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6167 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6168 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6169 // Try to match an SSSE3 integer HADD/HSUB.
6170 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6171 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6173 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6174 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6177 if (!Subtarget->hasAVX())
6180 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6181 // Try to match an AVX horizontal add/sub of packed single/double
6182 // precision floating point values from 256-bit vectors.
6183 SDValue InVec2, InVec3;
6184 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6185 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6186 ((InVec0.getOpcode() == ISD::UNDEF ||
6187 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6188 ((InVec1.getOpcode() == ISD::UNDEF ||
6189 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6190 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6192 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6193 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6194 ((InVec0.getOpcode() == ISD::UNDEF ||
6195 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6196 ((InVec1.getOpcode() == ISD::UNDEF ||
6197 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6198 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6199 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6200 // Try to match an AVX2 horizontal add/sub of signed integers.
6201 SDValue InVec2, InVec3;
6203 bool CanFold = true;
6205 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6206 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6207 ((InVec0.getOpcode() == ISD::UNDEF ||
6208 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6209 ((InVec1.getOpcode() == ISD::UNDEF ||
6210 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6211 X86Opcode = X86ISD::HADD;
6212 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6213 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6214 ((InVec0.getOpcode() == ISD::UNDEF ||
6215 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6216 ((InVec1.getOpcode() == ISD::UNDEF ||
6217 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6218 X86Opcode = X86ISD::HSUB;
6223 // Fold this build_vector into a single horizontal add/sub.
6224 // Do this only if the target has AVX2.
6225 if (Subtarget->hasAVX2())
6226 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6228 // Do not try to expand this build_vector into a pair of horizontal
6229 // add/sub if we can emit a pair of scalar add/sub.
6230 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6233 // Convert this build_vector into a pair of horizontal binop followed by
6235 bool isUndefLO = NumUndefsLO == Half;
6236 bool isUndefHI = NumUndefsHI == Half;
6237 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6238 isUndefLO, isUndefHI);
6242 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6243 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6245 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6246 X86Opcode = X86ISD::HADD;
6247 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6248 X86Opcode = X86ISD::HSUB;
6249 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6250 X86Opcode = X86ISD::FHADD;
6251 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6252 X86Opcode = X86ISD::FHSUB;
6256 // Don't try to expand this build_vector into a pair of horizontal add/sub
6257 // if we can simply emit a pair of scalar add/sub.
6258 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6261 // Convert this build_vector into two horizontal add/sub followed by
6263 bool isUndefLO = NumUndefsLO == Half;
6264 bool isUndefHI = NumUndefsHI == Half;
6265 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6266 isUndefLO, isUndefHI);
6273 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6276 MVT VT = Op.getSimpleValueType();
6277 MVT ExtVT = VT.getVectorElementType();
6278 unsigned NumElems = Op.getNumOperands();
6280 // Generate vectors for predicate vectors.
6281 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6282 return LowerBUILD_VECTORvXi1(Op, DAG);
6284 // Vectors containing all zeros can be matched by pxor and xorps later
6285 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6286 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6287 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6288 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6291 return getZeroVector(VT, Subtarget, DAG, dl);
6294 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6295 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6296 // vpcmpeqd on 256-bit vectors.
6297 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6298 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6301 if (!VT.is512BitVector())
6302 return getOnesVector(VT, Subtarget, DAG, dl);
6305 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6306 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6308 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6309 return HorizontalOp;
6310 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6313 unsigned EVTBits = ExtVT.getSizeInBits();
6315 unsigned NumZero = 0;
6316 unsigned NumNonZero = 0;
6317 uint64_t NonZeros = 0;
6318 bool IsAllConstants = true;
6319 SmallSet<SDValue, 8> Values;
6320 for (unsigned i = 0; i < NumElems; ++i) {
6321 SDValue Elt = Op.getOperand(i);
6322 if (Elt.getOpcode() == ISD::UNDEF)
6325 if (Elt.getOpcode() != ISD::Constant &&
6326 Elt.getOpcode() != ISD::ConstantFP)
6327 IsAllConstants = false;
6328 if (X86::isZeroNode(Elt))
6331 assert(i < sizeof(NonZeros) * 8); // Make sure the shift is within range.
6332 NonZeros |= ((uint64_t)1 << i);
6337 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6338 if (NumNonZero == 0)
6339 return DAG.getUNDEF(VT);
6341 // Special case for single non-zero, non-undef, element.
6342 if (NumNonZero == 1) {
6343 unsigned Idx = countTrailingZeros(NonZeros);
6344 SDValue Item = Op.getOperand(Idx);
6346 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6347 // the value are obviously zero, truncate the value to i32 and do the
6348 // insertion that way. Only do this if the value is non-constant or if the
6349 // value is a constant being inserted into element 0. It is cheaper to do
6350 // a constant pool load than it is to do a movd + shuffle.
6351 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6352 (!IsAllConstants || Idx == 0)) {
6353 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6355 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6356 MVT VecVT = MVT::v4i32;
6358 // Truncate the value (which may itself be a constant) to i32, and
6359 // convert it to a vector with movd (S2V+shuffle to zero extend).
6360 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6361 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6362 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6363 Item, Idx * 2, true, Subtarget, DAG));
6367 // If we have a constant or non-constant insertion into the low element of
6368 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6369 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6370 // depending on what the source datatype is.
6373 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6375 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6376 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6377 if (VT.is512BitVector()) {
6378 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6379 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6380 Item, DAG.getIntPtrConstant(0, dl));
6382 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6383 "Expected an SSE value type!");
6384 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6385 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6386 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6389 // We can't directly insert an i8 or i16 into a vector, so zero extend
6391 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6392 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6393 if (VT.is256BitVector()) {
6394 if (Subtarget->hasAVX()) {
6395 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6396 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6398 // Without AVX, we need to extend to a 128-bit vector and then
6399 // insert into the 256-bit vector.
6400 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6401 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6402 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6405 assert(VT.is128BitVector() && "Expected an SSE value type!");
6406 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6407 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6409 return DAG.getBitcast(VT, Item);
6413 // Is it a vector logical left shift?
6414 if (NumElems == 2 && Idx == 1 &&
6415 X86::isZeroNode(Op.getOperand(0)) &&
6416 !X86::isZeroNode(Op.getOperand(1))) {
6417 unsigned NumBits = VT.getSizeInBits();
6418 return getVShift(true, VT,
6419 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6420 VT, Op.getOperand(1)),
6421 NumBits/2, DAG, *this, dl);
6424 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6427 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6428 // is a non-constant being inserted into an element other than the low one,
6429 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6430 // movd/movss) to move this into the low element, then shuffle it into
6432 if (EVTBits == 32) {
6433 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6434 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6438 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6439 if (Values.size() == 1) {
6440 if (EVTBits == 32) {
6441 // Instead of a shuffle like this:
6442 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6443 // Check if it's possible to issue this instead.
6444 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6445 unsigned Idx = countTrailingZeros(NonZeros);
6446 SDValue Item = Op.getOperand(Idx);
6447 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6448 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6453 // A vector full of immediates; various special cases are already
6454 // handled, so this is best done with a single constant-pool load.
6458 // For AVX-length vectors, see if we can use a vector load to get all of the
6459 // elements, otherwise build the individual 128-bit pieces and use
6460 // shuffles to put them in place.
6461 if (VT.is256BitVector() || VT.is512BitVector()) {
6462 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6464 // Check for a build vector of consecutive loads.
6465 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6468 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6470 // Build both the lower and upper subvector.
6471 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6472 makeArrayRef(&V[0], NumElems/2));
6473 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6474 makeArrayRef(&V[NumElems / 2], NumElems/2));
6476 // Recreate the wider vector with the lower and upper part.
6477 if (VT.is256BitVector())
6478 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6479 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6482 // Let legalizer expand 2-wide build_vectors.
6483 if (EVTBits == 64) {
6484 if (NumNonZero == 1) {
6485 // One half is zero or undef.
6486 unsigned Idx = countTrailingZeros(NonZeros);
6487 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6488 Op.getOperand(Idx));
6489 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6494 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6495 if (EVTBits == 8 && NumElems == 16)
6496 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros, NumNonZero, NumZero,
6497 DAG, Subtarget, *this))
6500 if (EVTBits == 16 && NumElems == 8)
6501 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros, NumNonZero, NumZero,
6502 DAG, Subtarget, *this))
6505 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6506 if (EVTBits == 32 && NumElems == 4)
6507 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6510 // If element VT is == 32 bits, turn it into a number of shuffles.
6511 SmallVector<SDValue, 8> V(NumElems);
6512 if (NumElems == 4 && NumZero > 0) {
6513 for (unsigned i = 0; i < 4; ++i) {
6514 bool isZero = !(NonZeros & (1ULL << i));
6516 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6518 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6521 for (unsigned i = 0; i < 2; ++i) {
6522 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6525 V[i] = V[i*2]; // Must be a zero vector.
6528 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6531 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6534 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6539 bool Reverse1 = (NonZeros & 0x3) == 2;
6540 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6544 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6545 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6547 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6550 if (Values.size() > 1 && VT.is128BitVector()) {
6551 // Check for a build vector of consecutive loads.
6552 for (unsigned i = 0; i < NumElems; ++i)
6553 V[i] = Op.getOperand(i);
6555 // Check for elements which are consecutive loads.
6556 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6559 // Check for a build vector from mostly shuffle plus few inserting.
6560 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6563 // For SSE 4.1, use insertps to put the high elements into the low element.
6564 if (Subtarget->hasSSE41()) {
6566 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6567 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6569 Result = DAG.getUNDEF(VT);
6571 for (unsigned i = 1; i < NumElems; ++i) {
6572 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6573 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6574 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6579 // Otherwise, expand into a number of unpckl*, start by extending each of
6580 // our (non-undef) elements to the full vector width with the element in the
6581 // bottom slot of the vector (which generates no code for SSE).
6582 for (unsigned i = 0; i < NumElems; ++i) {
6583 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6584 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6586 V[i] = DAG.getUNDEF(VT);
6589 // Next, we iteratively mix elements, e.g. for v4f32:
6590 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6591 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6592 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6593 unsigned EltStride = NumElems >> 1;
6594 while (EltStride != 0) {
6595 for (unsigned i = 0; i < EltStride; ++i) {
6596 // If V[i+EltStride] is undef and this is the first round of mixing,
6597 // then it is safe to just drop this shuffle: V[i] is already in the
6598 // right place, the one element (since it's the first round) being
6599 // inserted as undef can be dropped. This isn't safe for successive
6600 // rounds because they will permute elements within both vectors.
6601 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6602 EltStride == NumElems/2)
6605 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6614 // 256-bit AVX can use the vinsertf128 instruction
6615 // to create 256-bit vectors from two other 128-bit ones.
6616 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6618 MVT ResVT = Op.getSimpleValueType();
6620 assert((ResVT.is256BitVector() ||
6621 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6623 SDValue V1 = Op.getOperand(0);
6624 SDValue V2 = Op.getOperand(1);
6625 unsigned NumElems = ResVT.getVectorNumElements();
6626 if (ResVT.is256BitVector())
6627 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6629 if (Op.getNumOperands() == 4) {
6630 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6631 ResVT.getVectorNumElements()/2);
6632 SDValue V3 = Op.getOperand(2);
6633 SDValue V4 = Op.getOperand(3);
6634 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6635 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6637 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6640 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6641 const X86Subtarget *Subtarget,
6642 SelectionDAG & DAG) {
6644 MVT ResVT = Op.getSimpleValueType();
6645 unsigned NumOfOperands = Op.getNumOperands();
6647 assert(isPowerOf2_32(NumOfOperands) &&
6648 "Unexpected number of operands in CONCAT_VECTORS");
6650 SDValue Undef = DAG.getUNDEF(ResVT);
6651 if (NumOfOperands > 2) {
6652 // Specialize the cases when all, or all but one, of the operands are undef.
6653 unsigned NumOfDefinedOps = 0;
6655 for (unsigned i = 0; i < NumOfOperands; i++)
6656 if (!Op.getOperand(i).isUndef()) {
6660 if (NumOfDefinedOps == 0)
6662 if (NumOfDefinedOps == 1) {
6663 unsigned SubVecNumElts =
6664 Op.getOperand(OpIdx).getValueType().getVectorNumElements();
6665 SDValue IdxVal = DAG.getIntPtrConstant(SubVecNumElts * OpIdx, dl);
6666 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,
6667 Op.getOperand(OpIdx), IdxVal);
6670 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6671 ResVT.getVectorNumElements()/2);
6672 SmallVector<SDValue, 2> Ops;
6673 for (unsigned i = 0; i < NumOfOperands/2; i++)
6674 Ops.push_back(Op.getOperand(i));
6675 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6677 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6678 Ops.push_back(Op.getOperand(i));
6679 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6680 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6684 SDValue V1 = Op.getOperand(0);
6685 SDValue V2 = Op.getOperand(1);
6686 unsigned NumElems = ResVT.getVectorNumElements();
6687 assert(V1.getValueType() == V2.getValueType() &&
6688 V1.getValueType().getVectorNumElements() == NumElems/2 &&
6689 "Unexpected operands in CONCAT_VECTORS");
6691 if (ResVT.getSizeInBits() >= 16)
6692 return Op; // The operation is legal with KUNPCK
6694 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6695 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6696 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl);
6697 if (IsZeroV1 && IsZeroV2)
6700 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6702 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6704 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);
6706 SDValue IdxVal = DAG.getIntPtrConstant(NumElems/2, dl);
6708 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6711 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6713 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6714 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
6717 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6718 const X86Subtarget *Subtarget,
6719 SelectionDAG &DAG) {
6720 MVT VT = Op.getSimpleValueType();
6721 if (VT.getVectorElementType() == MVT::i1)
6722 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6724 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6725 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6726 Op.getNumOperands() == 4)));
6728 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6729 // from two other 128-bit ones.
6731 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6732 return LowerAVXCONCAT_VECTORS(Op, DAG);
6735 //===----------------------------------------------------------------------===//
6736 // Vector shuffle lowering
6738 // This is an experimental code path for lowering vector shuffles on x86. It is
6739 // designed to handle arbitrary vector shuffles and blends, gracefully
6740 // degrading performance as necessary. It works hard to recognize idiomatic
6741 // shuffles and lower them to optimal instruction patterns without leaving
6742 // a framework that allows reasonably efficient handling of all vector shuffle
6744 //===----------------------------------------------------------------------===//
6746 /// \brief Tiny helper function to identify a no-op mask.
6748 /// This is a somewhat boring predicate function. It checks whether the mask
6749 /// array input, which is assumed to be a single-input shuffle mask of the kind
6750 /// used by the X86 shuffle instructions (not a fully general
6751 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6752 /// in-place shuffle are 'no-op's.
6753 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6754 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6755 if (Mask[i] != -1 && Mask[i] != i)
6760 /// \brief Helper function to classify a mask as a single-input mask.
6762 /// This isn't a generic single-input test because in the vector shuffle
6763 /// lowering we canonicalize single inputs to be the first input operand. This
6764 /// means we can more quickly test for a single input by only checking whether
6765 /// an input from the second operand exists. We also assume that the size of
6766 /// mask corresponds to the size of the input vectors which isn't true in the
6767 /// fully general case.
6768 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6770 if (M >= (int)Mask.size())
6775 /// \brief Test whether there are elements crossing 128-bit lanes in this
6778 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6779 /// and we routinely test for these.
6780 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6781 int LaneSize = 128 / VT.getScalarSizeInBits();
6782 int Size = Mask.size();
6783 for (int i = 0; i < Size; ++i)
6784 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6789 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6791 /// This checks a shuffle mask to see if it is performing the same
6792 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6793 /// that it is also not lane-crossing. It may however involve a blend from the
6794 /// same lane of a second vector.
6796 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6797 /// non-trivial to compute in the face of undef lanes. The representation is
6798 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6799 /// entries from both V1 and V2 inputs to the wider mask.
6801 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6802 SmallVectorImpl<int> &RepeatedMask) {
6803 int LaneSize = 128 / VT.getScalarSizeInBits();
6804 RepeatedMask.resize(LaneSize, -1);
6805 int Size = Mask.size();
6806 for (int i = 0; i < Size; ++i) {
6809 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6810 // This entry crosses lanes, so there is no way to model this shuffle.
6813 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6814 if (RepeatedMask[i % LaneSize] == -1)
6815 // This is the first non-undef entry in this slot of a 128-bit lane.
6816 RepeatedMask[i % LaneSize] =
6817 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6818 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6819 // Found a mismatch with the repeated mask.
6825 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6828 /// This is a fast way to test a shuffle mask against a fixed pattern:
6830 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6832 /// It returns true if the mask is exactly as wide as the argument list, and
6833 /// each element of the mask is either -1 (signifying undef) or the value given
6834 /// in the argument.
6835 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6836 ArrayRef<int> ExpectedMask) {
6837 if (Mask.size() != ExpectedMask.size())
6840 int Size = Mask.size();
6842 // If the values are build vectors, we can look through them to find
6843 // equivalent inputs that make the shuffles equivalent.
6844 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6845 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6847 for (int i = 0; i < Size; ++i)
6848 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6849 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6850 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6851 if (!MaskBV || !ExpectedBV ||
6852 MaskBV->getOperand(Mask[i] % Size) !=
6853 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6860 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6862 /// This helper function produces an 8-bit shuffle immediate corresponding to
6863 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6864 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6867 /// NB: We rely heavily on "undef" masks preserving the input lane.
6868 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6869 SelectionDAG &DAG) {
6870 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6871 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6872 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6873 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6874 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6877 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6878 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6879 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6880 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6881 return DAG.getConstant(Imm, DL, MVT::i8);
6884 /// \brief Compute whether each element of a shuffle is zeroable.
6886 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6887 /// Either it is an undef element in the shuffle mask, the element of the input
6888 /// referenced is undef, or the element of the input referenced is known to be
6889 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6890 /// as many lanes with this technique as possible to simplify the remaining
6892 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6893 SDValue V1, SDValue V2) {
6894 SmallBitVector Zeroable(Mask.size(), false);
6896 while (V1.getOpcode() == ISD::BITCAST)
6897 V1 = V1->getOperand(0);
6898 while (V2.getOpcode() == ISD::BITCAST)
6899 V2 = V2->getOperand(0);
6901 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6902 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6904 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6906 // Handle the easy cases.
6907 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6912 // If this is an index into a build_vector node (which has the same number
6913 // of elements), dig out the input value and use it.
6914 SDValue V = M < Size ? V1 : V2;
6915 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6918 SDValue Input = V.getOperand(M % Size);
6919 // The UNDEF opcode check really should be dead code here, but not quite
6920 // worth asserting on (it isn't invalid, just unexpected).
6921 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6928 // X86 has dedicated unpack instructions that can handle specific blend
6929 // operations: UNPCKH and UNPCKL.
6930 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6931 SDValue V1, SDValue V2,
6932 SelectionDAG &DAG) {
6933 int NumElts = VT.getVectorNumElements();
6934 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6935 SmallVector<int, 8> Unpckl;
6936 SmallVector<int, 8> Unpckh;
6938 for (int i = 0; i < NumElts; ++i) {
6939 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6940 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6941 int HiPos = LoPos + NumEltsInLane / 2;
6942 Unpckl.push_back(LoPos);
6943 Unpckh.push_back(HiPos);
6946 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6947 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6948 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6949 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6951 // Commute and try again.
6952 ShuffleVectorSDNode::commuteMask(Unpckl);
6953 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6954 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6956 ShuffleVectorSDNode::commuteMask(Unpckh);
6957 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6958 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6963 /// \brief Try to emit a bitmask instruction for a shuffle.
6965 /// This handles cases where we can model a blend exactly as a bitmask due to
6966 /// one of the inputs being zeroable.
6967 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6968 SDValue V2, ArrayRef<int> Mask,
6969 SelectionDAG &DAG) {
6970 MVT EltVT = VT.getVectorElementType();
6971 int NumEltBits = EltVT.getSizeInBits();
6972 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6973 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6974 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6976 if (EltVT.isFloatingPoint()) {
6977 Zero = DAG.getBitcast(EltVT, Zero);
6978 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6980 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6981 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6983 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6986 if (Mask[i] % Size != i)
6987 return SDValue(); // Not a blend.
6989 V = Mask[i] < Size ? V1 : V2;
6990 else if (V != (Mask[i] < Size ? V1 : V2))
6991 return SDValue(); // Can only let one input through the mask.
6993 VMaskOps[i] = AllOnes;
6996 return SDValue(); // No non-zeroable elements!
6998 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6999 V = DAG.getNode(VT.isFloatingPoint()
7000 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
7005 /// \brief Try to emit a blend instruction for a shuffle using bit math.
7007 /// This is used as a fallback approach when first class blend instructions are
7008 /// unavailable. Currently it is only suitable for integer vectors, but could
7009 /// be generalized for floating point vectors if desirable.
7010 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
7011 SDValue V2, ArrayRef<int> Mask,
7012 SelectionDAG &DAG) {
7013 assert(VT.isInteger() && "Only supports integer vector types!");
7014 MVT EltVT = VT.getVectorElementType();
7015 int NumEltBits = EltVT.getSizeInBits();
7016 SDValue Zero = DAG.getConstant(0, DL, EltVT);
7017 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
7019 SmallVector<SDValue, 16> MaskOps;
7020 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7021 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
7022 return SDValue(); // Shuffled input!
7023 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
7026 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
7027 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
7028 // We have to cast V2 around.
7029 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
7030 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
7031 DAG.getBitcast(MaskVT, V1Mask),
7032 DAG.getBitcast(MaskVT, V2)));
7033 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
7036 /// \brief Try to emit a blend instruction for a shuffle.
7038 /// This doesn't do any checks for the availability of instructions for blending
7039 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7040 /// be matched in the backend with the type given. What it does check for is
7041 /// that the shuffle mask is a blend, or convertible into a blend with zero.
7042 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7043 SDValue V2, ArrayRef<int> Original,
7044 const X86Subtarget *Subtarget,
7045 SelectionDAG &DAG) {
7046 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7047 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7048 SmallVector<int, 8> Mask(Original.begin(), Original.end());
7049 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7050 bool ForceV1Zero = false, ForceV2Zero = false;
7052 // Attempt to generate the binary blend mask. If an input is zero then
7053 // we can use any lane.
7054 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
7055 unsigned BlendMask = 0;
7056 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7062 if (M == i + Size) {
7063 BlendMask |= 1u << i;
7074 BlendMask |= 1u << i;
7079 return SDValue(); // Shuffled input!
7082 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
7084 V1 = getZeroVector(VT, Subtarget, DAG, DL);
7086 V2 = getZeroVector(VT, Subtarget, DAG, DL);
7088 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
7089 unsigned ScaledMask = 0;
7090 for (int i = 0; i != Size; ++i)
7091 if (BlendMask & (1u << i))
7092 for (int j = 0; j != Scale; ++j)
7093 ScaledMask |= 1u << (i * Scale + j);
7097 switch (VT.SimpleTy) {
7102 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7103 DAG.getConstant(BlendMask, DL, MVT::i8));
7107 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7111 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7112 // that instruction.
7113 if (Subtarget->hasAVX2()) {
7114 // Scale the blend by the number of 32-bit dwords per element.
7115 int Scale = VT.getScalarSizeInBits() / 32;
7116 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7117 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7118 V1 = DAG.getBitcast(BlendVT, V1);
7119 V2 = DAG.getBitcast(BlendVT, V2);
7120 return DAG.getBitcast(
7121 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7122 DAG.getConstant(BlendMask, DL, MVT::i8)));
7126 // For integer shuffles we need to expand the mask and cast the inputs to
7127 // v8i16s prior to blending.
7128 int Scale = 8 / VT.getVectorNumElements();
7129 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7130 V1 = DAG.getBitcast(MVT::v8i16, V1);
7131 V2 = DAG.getBitcast(MVT::v8i16, V2);
7132 return DAG.getBitcast(VT,
7133 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7134 DAG.getConstant(BlendMask, DL, MVT::i8)));
7138 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7139 SmallVector<int, 8> RepeatedMask;
7140 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7141 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7142 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7144 for (int i = 0; i < 8; ++i)
7145 if (RepeatedMask[i] >= 16)
7146 BlendMask |= 1u << i;
7147 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7148 DAG.getConstant(BlendMask, DL, MVT::i8));
7154 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
7155 "256-bit byte-blends require AVX2 support!");
7157 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
7158 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
7161 // Scale the blend by the number of bytes per element.
7162 int Scale = VT.getScalarSizeInBits() / 8;
7164 // This form of blend is always done on bytes. Compute the byte vector
7166 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
7168 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7169 // mix of LLVM's code generator and the x86 backend. We tell the code
7170 // generator that boolean values in the elements of an x86 vector register
7171 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7172 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7173 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7174 // of the element (the remaining are ignored) and 0 in that high bit would
7175 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7176 // the LLVM model for boolean values in vector elements gets the relevant
7177 // bit set, it is set backwards and over constrained relative to x86's
7179 SmallVector<SDValue, 32> VSELECTMask;
7180 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7181 for (int j = 0; j < Scale; ++j)
7182 VSELECTMask.push_back(
7183 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7184 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7187 V1 = DAG.getBitcast(BlendVT, V1);
7188 V2 = DAG.getBitcast(BlendVT, V2);
7189 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7190 DAG.getNode(ISD::BUILD_VECTOR, DL,
7191 BlendVT, VSELECTMask),
7196 llvm_unreachable("Not a supported integer vector type!");
7200 /// \brief Try to lower as a blend of elements from two inputs followed by
7201 /// a single-input permutation.
7203 /// This matches the pattern where we can blend elements from two inputs and
7204 /// then reduce the shuffle to a single-input permutation.
7205 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7208 SelectionDAG &DAG) {
7209 // We build up the blend mask while checking whether a blend is a viable way
7210 // to reduce the shuffle.
7211 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7212 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7214 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7218 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7220 if (BlendMask[Mask[i] % Size] == -1)
7221 BlendMask[Mask[i] % Size] = Mask[i];
7222 else if (BlendMask[Mask[i] % Size] != Mask[i])
7223 return SDValue(); // Can't blend in the needed input!
7225 PermuteMask[i] = Mask[i] % Size;
7228 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7229 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7232 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7233 /// blends and permutes.
7235 /// This matches the extremely common pattern for handling combined
7236 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7237 /// operations. It will try to pick the best arrangement of shuffles and
7239 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7243 SelectionDAG &DAG) {
7244 // Shuffle the input elements into the desired positions in V1 and V2 and
7245 // blend them together.
7246 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7247 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7248 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7249 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7250 if (Mask[i] >= 0 && Mask[i] < Size) {
7251 V1Mask[i] = Mask[i];
7253 } else if (Mask[i] >= Size) {
7254 V2Mask[i] = Mask[i] - Size;
7255 BlendMask[i] = i + Size;
7258 // Try to lower with the simpler initial blend strategy unless one of the
7259 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7260 // shuffle may be able to fold with a load or other benefit. However, when
7261 // we'll have to do 2x as many shuffles in order to achieve this, blending
7262 // first is a better strategy.
7263 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7264 if (SDValue BlendPerm =
7265 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7268 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7269 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7270 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7273 /// \brief Try to lower a vector shuffle as a byte rotation.
7275 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7276 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7277 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7278 /// try to generically lower a vector shuffle through such an pattern. It
7279 /// does not check for the profitability of lowering either as PALIGNR or
7280 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7281 /// This matches shuffle vectors that look like:
7283 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7285 /// Essentially it concatenates V1 and V2, shifts right by some number of
7286 /// elements, and takes the low elements as the result. Note that while this is
7287 /// specified as a *right shift* because x86 is little-endian, it is a *left
7288 /// rotate* of the vector lanes.
7289 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7292 const X86Subtarget *Subtarget,
7293 SelectionDAG &DAG) {
7294 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7296 int NumElts = Mask.size();
7297 int NumLanes = VT.getSizeInBits() / 128;
7298 int NumLaneElts = NumElts / NumLanes;
7300 // We need to detect various ways of spelling a rotation:
7301 // [11, 12, 13, 14, 15, 0, 1, 2]
7302 // [-1, 12, 13, 14, -1, -1, 1, -1]
7303 // [-1, -1, -1, -1, -1, -1, 1, 2]
7304 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7305 // [-1, 4, 5, 6, -1, -1, 9, -1]
7306 // [-1, 4, 5, 6, -1, -1, -1, -1]
7309 for (int l = 0; l < NumElts; l += NumLaneElts) {
7310 for (int i = 0; i < NumLaneElts; ++i) {
7311 if (Mask[l + i] == -1)
7313 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7315 // Get the mod-Size index and lane correct it.
7316 int LaneIdx = (Mask[l + i] % NumElts) - l;
7317 // Make sure it was in this lane.
7318 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7321 // Determine where a rotated vector would have started.
7322 int StartIdx = i - LaneIdx;
7324 // The identity rotation isn't interesting, stop.
7327 // If we found the tail of a vector the rotation must be the missing
7328 // front. If we found the head of a vector, it must be how much of the
7330 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7333 Rotation = CandidateRotation;
7334 else if (Rotation != CandidateRotation)
7335 // The rotations don't match, so we can't match this mask.
7338 // Compute which value this mask is pointing at.
7339 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7341 // Compute which of the two target values this index should be assigned
7342 // to. This reflects whether the high elements are remaining or the low
7343 // elements are remaining.
7344 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7346 // Either set up this value if we've not encountered it before, or check
7347 // that it remains consistent.
7350 else if (TargetV != MaskV)
7351 // This may be a rotation, but it pulls from the inputs in some
7352 // unsupported interleaving.
7357 // Check that we successfully analyzed the mask, and normalize the results.
7358 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7359 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7365 // The actual rotate instruction rotates bytes, so we need to scale the
7366 // rotation based on how many bytes are in the vector lane.
7367 int Scale = 16 / NumLaneElts;
7369 // SSSE3 targets can use the palignr instruction.
7370 if (Subtarget->hasSSSE3()) {
7371 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7372 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7373 Lo = DAG.getBitcast(AlignVT, Lo);
7374 Hi = DAG.getBitcast(AlignVT, Hi);
7376 return DAG.getBitcast(
7377 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7378 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7381 assert(VT.is128BitVector() &&
7382 "Rotate-based lowering only supports 128-bit lowering!");
7383 assert(Mask.size() <= 16 &&
7384 "Can shuffle at most 16 bytes in a 128-bit vector!");
7386 // Default SSE2 implementation
7387 int LoByteShift = 16 - Rotation * Scale;
7388 int HiByteShift = Rotation * Scale;
7390 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7391 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7392 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7394 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7395 DAG.getConstant(LoByteShift, DL, MVT::i8));
7396 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7397 DAG.getConstant(HiByteShift, DL, MVT::i8));
7398 return DAG.getBitcast(VT,
7399 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7402 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7404 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7405 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7406 /// matches elements from one of the input vectors shuffled to the left or
7407 /// right with zeroable elements 'shifted in'. It handles both the strictly
7408 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7411 /// PSHL : (little-endian) left bit shift.
7412 /// [ zz, 0, zz, 2 ]
7413 /// [ -1, 4, zz, -1 ]
7414 /// PSRL : (little-endian) right bit shift.
7416 /// [ -1, -1, 7, zz]
7417 /// PSLLDQ : (little-endian) left byte shift
7418 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7419 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7420 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7421 /// PSRLDQ : (little-endian) right byte shift
7422 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7423 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7424 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7425 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7426 SDValue V2, ArrayRef<int> Mask,
7427 SelectionDAG &DAG) {
7428 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7430 int Size = Mask.size();
7431 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7433 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7434 for (int i = 0; i < Size; i += Scale)
7435 for (int j = 0; j < Shift; ++j)
7436 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7442 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7443 for (int i = 0; i != Size; i += Scale) {
7444 unsigned Pos = Left ? i + Shift : i;
7445 unsigned Low = Left ? i : i + Shift;
7446 unsigned Len = Scale - Shift;
7447 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7448 Low + (V == V1 ? 0 : Size)))
7452 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7453 bool ByteShift = ShiftEltBits > 64;
7454 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7455 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7456 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7458 // Normalize the scale for byte shifts to still produce an i64 element
7460 Scale = ByteShift ? Scale / 2 : Scale;
7462 // We need to round trip through the appropriate type for the shift.
7463 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7464 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7465 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7466 "Illegal integer vector type");
7467 V = DAG.getBitcast(ShiftVT, V);
7469 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7470 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7471 return DAG.getBitcast(VT, V);
7474 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7475 // keep doubling the size of the integer elements up to that. We can
7476 // then shift the elements of the integer vector by whole multiples of
7477 // their width within the elements of the larger integer vector. Test each
7478 // multiple to see if we can find a match with the moved element indices
7479 // and that the shifted in elements are all zeroable.
7480 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7481 for (int Shift = 1; Shift != Scale; ++Shift)
7482 for (bool Left : {true, false})
7483 if (CheckZeros(Shift, Scale, Left))
7484 for (SDValue V : {V1, V2})
7485 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7492 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7493 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7494 SDValue V2, ArrayRef<int> Mask,
7495 SelectionDAG &DAG) {
7496 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7497 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7499 int Size = Mask.size();
7500 int HalfSize = Size / 2;
7501 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7503 // Upper half must be undefined.
7504 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7507 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7508 // Remainder of lower half result is zero and upper half is all undef.
7509 auto LowerAsEXTRQ = [&]() {
7510 // Determine the extraction length from the part of the
7511 // lower half that isn't zeroable.
7513 for (; Len > 0; --Len)
7514 if (!Zeroable[Len - 1])
7516 assert(Len > 0 && "Zeroable shuffle mask");
7518 // Attempt to match first Len sequential elements from the lower half.
7521 for (int i = 0; i != Len; ++i) {
7525 SDValue &V = (M < Size ? V1 : V2);
7528 // The extracted elements must start at a valid index and all mask
7529 // elements must be in the lower half.
7530 if (i > M || M >= HalfSize)
7533 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7544 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7545 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7546 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7547 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7548 DAG.getConstant(BitLen, DL, MVT::i8),
7549 DAG.getConstant(BitIdx, DL, MVT::i8));
7552 if (SDValue ExtrQ = LowerAsEXTRQ())
7555 // INSERTQ: Extract lowest Len elements from lower half of second source and
7556 // insert over first source, starting at Idx.
7557 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7558 auto LowerAsInsertQ = [&]() {
7559 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7562 // Attempt to match first source from mask before insertion point.
7563 if (isUndefInRange(Mask, 0, Idx)) {
7565 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7567 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7573 // Extend the extraction length looking to match both the insertion of
7574 // the second source and the remaining elements of the first.
7575 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7580 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7582 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7588 // Match the remaining elements of the lower half.
7589 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7591 } else if ((!Base || (Base == V1)) &&
7592 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7594 } else if ((!Base || (Base == V2)) &&
7595 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7602 // We may not have a base (first source) - this can safely be undefined.
7604 Base = DAG.getUNDEF(VT);
7606 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7607 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7608 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7609 DAG.getConstant(BitLen, DL, MVT::i8),
7610 DAG.getConstant(BitIdx, DL, MVT::i8));
7617 if (SDValue InsertQ = LowerAsInsertQ())
7623 /// \brief Lower a vector shuffle as a zero or any extension.
7625 /// Given a specific number of elements, element bit width, and extension
7626 /// stride, produce either a zero or any extension based on the available
7627 /// features of the subtarget. The extended elements are consecutive and
7628 /// begin and can start from an offseted element index in the input; to
7629 /// avoid excess shuffling the offset must either being in the bottom lane
7630 /// or at the start of a higher lane. All extended elements must be from
7632 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7633 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7634 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7635 assert(Scale > 1 && "Need a scale to extend.");
7636 int EltBits = VT.getScalarSizeInBits();
7637 int NumElements = VT.getVectorNumElements();
7638 int NumEltsPerLane = 128 / EltBits;
7639 int OffsetLane = Offset / NumEltsPerLane;
7640 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7641 "Only 8, 16, and 32 bit elements can be extended.");
7642 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7643 assert(0 <= Offset && "Extension offset must be positive.");
7644 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7645 "Extension offset must be in the first lane or start an upper lane.");
7647 // Check that an index is in same lane as the base offset.
7648 auto SafeOffset = [&](int Idx) {
7649 return OffsetLane == (Idx / NumEltsPerLane);
7652 // Shift along an input so that the offset base moves to the first element.
7653 auto ShuffleOffset = [&](SDValue V) {
7657 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7658 for (int i = 0; i * Scale < NumElements; ++i) {
7659 int SrcIdx = i + Offset;
7660 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7662 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7665 // Found a valid zext mask! Try various lowering strategies based on the
7666 // input type and available ISA extensions.
7667 if (Subtarget->hasSSE41()) {
7668 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7669 // PUNPCK will catch this in a later shuffle match.
7670 if (Offset && Scale == 2 && VT.is128BitVector())
7672 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7673 NumElements / Scale);
7674 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7675 return DAG.getBitcast(VT, InputV);
7678 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7680 // For any extends we can cheat for larger element sizes and use shuffle
7681 // instructions that can fold with a load and/or copy.
7682 if (AnyExt && EltBits == 32) {
7683 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7685 return DAG.getBitcast(
7686 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7687 DAG.getBitcast(MVT::v4i32, InputV),
7688 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7690 if (AnyExt && EltBits == 16 && Scale > 2) {
7691 int PSHUFDMask[4] = {Offset / 2, -1,
7692 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7693 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7694 DAG.getBitcast(MVT::v4i32, InputV),
7695 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7696 int PSHUFWMask[4] = {1, -1, -1, -1};
7697 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7698 return DAG.getBitcast(
7699 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7700 DAG.getBitcast(MVT::v8i16, InputV),
7701 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7704 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7706 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7707 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7708 assert(VT.is128BitVector() && "Unexpected vector width!");
7710 int LoIdx = Offset * EltBits;
7711 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7712 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7713 DAG.getConstant(EltBits, DL, MVT::i8),
7714 DAG.getConstant(LoIdx, DL, MVT::i8)));
7716 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7717 !SafeOffset(Offset + 1))
7718 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7720 int HiIdx = (Offset + 1) * EltBits;
7721 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7722 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7723 DAG.getConstant(EltBits, DL, MVT::i8),
7724 DAG.getConstant(HiIdx, DL, MVT::i8)));
7725 return DAG.getNode(ISD::BITCAST, DL, VT,
7726 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7729 // If this would require more than 2 unpack instructions to expand, use
7730 // pshufb when available. We can only use more than 2 unpack instructions
7731 // when zero extending i8 elements which also makes it easier to use pshufb.
7732 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7733 assert(NumElements == 16 && "Unexpected byte vector width!");
7734 SDValue PSHUFBMask[16];
7735 for (int i = 0; i < 16; ++i) {
7736 int Idx = Offset + (i / Scale);
7737 PSHUFBMask[i] = DAG.getConstant(
7738 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7740 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7741 return DAG.getBitcast(VT,
7742 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7743 DAG.getNode(ISD::BUILD_VECTOR, DL,
7744 MVT::v16i8, PSHUFBMask)));
7747 // If we are extending from an offset, ensure we start on a boundary that
7748 // we can unpack from.
7749 int AlignToUnpack = Offset % (NumElements / Scale);
7750 if (AlignToUnpack) {
7751 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7752 for (int i = AlignToUnpack; i < NumElements; ++i)
7753 ShMask[i - AlignToUnpack] = i;
7754 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7755 Offset -= AlignToUnpack;
7758 // Otherwise emit a sequence of unpacks.
7760 unsigned UnpackLoHi = X86ISD::UNPCKL;
7761 if (Offset >= (NumElements / 2)) {
7762 UnpackLoHi = X86ISD::UNPCKH;
7763 Offset -= (NumElements / 2);
7766 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7767 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7768 : getZeroVector(InputVT, Subtarget, DAG, DL);
7769 InputV = DAG.getBitcast(InputVT, InputV);
7770 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7774 } while (Scale > 1);
7775 return DAG.getBitcast(VT, InputV);
7778 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7780 /// This routine will try to do everything in its power to cleverly lower
7781 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7782 /// check for the profitability of this lowering, it tries to aggressively
7783 /// match this pattern. It will use all of the micro-architectural details it
7784 /// can to emit an efficient lowering. It handles both blends with all-zero
7785 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7786 /// masking out later).
7788 /// The reason we have dedicated lowering for zext-style shuffles is that they
7789 /// are both incredibly common and often quite performance sensitive.
7790 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7791 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7792 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7793 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7795 int Bits = VT.getSizeInBits();
7796 int NumLanes = Bits / 128;
7797 int NumElements = VT.getVectorNumElements();
7798 int NumEltsPerLane = NumElements / NumLanes;
7799 assert(VT.getScalarSizeInBits() <= 32 &&
7800 "Exceeds 32-bit integer zero extension limit");
7801 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7803 // Define a helper function to check a particular ext-scale and lower to it if
7805 auto Lower = [&](int Scale) -> SDValue {
7810 for (int i = 0; i < NumElements; ++i) {
7813 continue; // Valid anywhere but doesn't tell us anything.
7814 if (i % Scale != 0) {
7815 // Each of the extended elements need to be zeroable.
7819 // We no longer are in the anyext case.
7824 // Each of the base elements needs to be consecutive indices into the
7825 // same input vector.
7826 SDValue V = M < NumElements ? V1 : V2;
7827 M = M % NumElements;
7830 Offset = M - (i / Scale);
7831 } else if (InputV != V)
7832 return SDValue(); // Flip-flopping inputs.
7834 // Offset must start in the lowest 128-bit lane or at the start of an
7836 // FIXME: Is it ever worth allowing a negative base offset?
7837 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7838 (Offset % NumEltsPerLane) == 0))
7841 // If we are offsetting, all referenced entries must come from the same
7843 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7846 if ((M % NumElements) != (Offset + (i / Scale)))
7847 return SDValue(); // Non-consecutive strided elements.
7851 // If we fail to find an input, we have a zero-shuffle which should always
7852 // have already been handled.
7853 // FIXME: Maybe handle this here in case during blending we end up with one?
7857 // If we are offsetting, don't extend if we only match a single input, we
7858 // can always do better by using a basic PSHUF or PUNPCK.
7859 if (Offset != 0 && Matches < 2)
7862 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7863 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7866 // The widest scale possible for extending is to a 64-bit integer.
7867 assert(Bits % 64 == 0 &&
7868 "The number of bits in a vector must be divisible by 64 on x86!");
7869 int NumExtElements = Bits / 64;
7871 // Each iteration, try extending the elements half as much, but into twice as
7873 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7874 assert(NumElements % NumExtElements == 0 &&
7875 "The input vector size must be divisible by the extended size.");
7876 if (SDValue V = Lower(NumElements / NumExtElements))
7880 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7884 // Returns one of the source operands if the shuffle can be reduced to a
7885 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7886 auto CanZExtLowHalf = [&]() {
7887 for (int i = NumElements / 2; i != NumElements; ++i)
7890 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7892 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7897 if (SDValue V = CanZExtLowHalf()) {
7898 V = DAG.getBitcast(MVT::v2i64, V);
7899 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7900 return DAG.getBitcast(VT, V);
7903 // No viable ext lowering found.
7907 /// \brief Try to get a scalar value for a specific element of a vector.
7909 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7910 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7911 SelectionDAG &DAG) {
7912 MVT VT = V.getSimpleValueType();
7913 MVT EltVT = VT.getVectorElementType();
7914 while (V.getOpcode() == ISD::BITCAST)
7915 V = V.getOperand(0);
7916 // If the bitcasts shift the element size, we can't extract an equivalent
7918 MVT NewVT = V.getSimpleValueType();
7919 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7922 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7923 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7924 // Ensure the scalar operand is the same size as the destination.
7925 // FIXME: Add support for scalar truncation where possible.
7926 SDValue S = V.getOperand(Idx);
7927 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7928 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7934 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7936 /// This is particularly important because the set of instructions varies
7937 /// significantly based on whether the operand is a load or not.
7938 static bool isShuffleFoldableLoad(SDValue V) {
7939 while (V.getOpcode() == ISD::BITCAST)
7940 V = V.getOperand(0);
7942 return ISD::isNON_EXTLoad(V.getNode());
7945 /// \brief Try to lower insertion of a single element into a zero vector.
7947 /// This is a common pattern that we have especially efficient patterns to lower
7948 /// across all subtarget feature sets.
7949 static SDValue lowerVectorShuffleAsElementInsertion(
7950 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7951 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7952 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7954 MVT EltVT = VT.getVectorElementType();
7956 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7957 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7959 bool IsV1Zeroable = true;
7960 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7961 if (i != V2Index && !Zeroable[i]) {
7962 IsV1Zeroable = false;
7966 // Check for a single input from a SCALAR_TO_VECTOR node.
7967 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7968 // all the smarts here sunk into that routine. However, the current
7969 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7970 // vector shuffle lowering is dead.
7971 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7973 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7974 // We need to zext the scalar if it is smaller than an i32.
7975 V2S = DAG.getBitcast(EltVT, V2S);
7976 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7977 // Using zext to expand a narrow element won't work for non-zero
7982 // Zero-extend directly to i32.
7984 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7986 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7987 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7988 EltVT == MVT::i16) {
7989 // Either not inserting from the low element of the input or the input
7990 // element size is too small to use VZEXT_MOVL to clear the high bits.
7994 if (!IsV1Zeroable) {
7995 // If V1 can't be treated as a zero vector we have fewer options to lower
7996 // this. We can't support integer vectors or non-zero targets cheaply, and
7997 // the V1 elements can't be permuted in any way.
7998 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7999 if (!VT.isFloatingPoint() || V2Index != 0)
8001 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8002 V1Mask[V2Index] = -1;
8003 if (!isNoopShuffleMask(V1Mask))
8005 // This is essentially a special case blend operation, but if we have
8006 // general purpose blend operations, they are always faster. Bail and let
8007 // the rest of the lowering handle these as blends.
8008 if (Subtarget->hasSSE41())
8011 // Otherwise, use MOVSD or MOVSS.
8012 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8013 "Only two types of floating point element types to handle!");
8014 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8018 // This lowering only works for the low element with floating point vectors.
8019 if (VT.isFloatingPoint() && V2Index != 0)
8022 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8024 V2 = DAG.getBitcast(VT, V2);
8027 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8028 // the desired position. Otherwise it is more efficient to do a vector
8029 // shift left. We know that we can do a vector shift left because all
8030 // the inputs are zero.
8031 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8032 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8033 V2Shuffle[V2Index] = 0;
8034 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8036 V2 = DAG.getBitcast(MVT::v2i64, V2);
8038 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8039 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
8040 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
8041 DAG.getDataLayout(), VT)));
8042 V2 = DAG.getBitcast(VT, V2);
8048 /// \brief Try to lower broadcast of a single - truncated - integer element,
8049 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
8051 /// This assumes we have AVX2.
8052 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
8054 const X86Subtarget *Subtarget,
8055 SelectionDAG &DAG) {
8056 assert(Subtarget->hasAVX2() &&
8057 "We can only lower integer broadcasts with AVX2!");
8059 EVT EltVT = VT.getVectorElementType();
8060 EVT V0VT = V0.getValueType();
8062 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
8063 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
8065 EVT V0EltVT = V0VT.getVectorElementType();
8066 if (!V0EltVT.isInteger())
8069 const unsigned EltSize = EltVT.getSizeInBits();
8070 const unsigned V0EltSize = V0EltVT.getSizeInBits();
8072 // This is only a truncation if the original element type is larger.
8073 if (V0EltSize <= EltSize)
8076 assert(((V0EltSize % EltSize) == 0) &&
8077 "Scalar type sizes must all be powers of 2 on x86!");
8079 const unsigned V0Opc = V0.getOpcode();
8080 const unsigned Scale = V0EltSize / EltSize;
8081 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
8083 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
8084 V0Opc != ISD::BUILD_VECTOR)
8087 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
8089 // If we're extracting non-least-significant bits, shift so we can truncate.
8090 // Hopefully, we can fold away the trunc/srl/load into the broadcast.
8091 // Even if we can't (and !isShuffleFoldableLoad(Scalar)), prefer
8092 // vpbroadcast+vmovd+shr to vpshufb(m)+vmovd.
8093 if (const int OffsetIdx = BroadcastIdx % Scale)
8094 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
8095 DAG.getConstant(OffsetIdx * EltSize, DL, Scalar.getValueType()));
8097 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
8098 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
8101 /// \brief Try to lower broadcast of a single element.
8103 /// For convenience, this code also bundles all of the subtarget feature set
8104 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8105 /// a convenient way to factor it out.
8106 /// FIXME: This is very similar to LowerVectorBroadcast - can we merge them?
8107 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
8109 const X86Subtarget *Subtarget,
8110 SelectionDAG &DAG) {
8111 if (!Subtarget->hasAVX())
8113 if (VT.isInteger() && !Subtarget->hasAVX2())
8116 // Check that the mask is a broadcast.
8117 int BroadcastIdx = -1;
8119 if (M >= 0 && BroadcastIdx == -1)
8121 else if (M >= 0 && M != BroadcastIdx)
8124 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8125 "a sorted mask where the broadcast "
8128 // Go up the chain of (vector) values to find a scalar load that we can
8129 // combine with the broadcast.
8131 switch (V.getOpcode()) {
8132 case ISD::CONCAT_VECTORS: {
8133 int OperandSize = Mask.size() / V.getNumOperands();
8134 V = V.getOperand(BroadcastIdx / OperandSize);
8135 BroadcastIdx %= OperandSize;
8139 case ISD::INSERT_SUBVECTOR: {
8140 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8141 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8145 int BeginIdx = (int)ConstantIdx->getZExtValue();
8147 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
8148 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8149 BroadcastIdx -= BeginIdx;
8160 // Check if this is a broadcast of a scalar. We special case lowering
8161 // for scalars so that we can more effectively fold with loads.
8162 // First, look through bitcast: if the original value has a larger element
8163 // type than the shuffle, the broadcast element is in essence truncated.
8164 // Make that explicit to ease folding.
8165 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
8166 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
8167 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
8168 return TruncBroadcast;
8170 // Also check the simpler case, where we can directly reuse the scalar.
8171 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8172 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8173 V = V.getOperand(BroadcastIdx);
8175 // If the scalar isn't a load, we can't broadcast from it in AVX1.
8176 // Only AVX2 has register broadcasts.
8177 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8179 } else if (MayFoldLoad(V) && !cast<LoadSDNode>(V)->isVolatile()) {
8180 // If we are broadcasting a load that is only used by the shuffle
8181 // then we can reduce the vector load to the broadcasted scalar load.
8182 LoadSDNode *Ld = cast<LoadSDNode>(V);
8183 SDValue BaseAddr = Ld->getOperand(1);
8184 EVT AddrVT = BaseAddr.getValueType();
8185 EVT SVT = VT.getScalarType();
8186 unsigned Offset = BroadcastIdx * SVT.getStoreSize();
8187 SDValue NewAddr = DAG.getNode(
8188 ISD::ADD, DL, AddrVT, BaseAddr,
8189 DAG.getConstant(Offset, DL, AddrVT));
8190 V = DAG.getLoad(SVT, DL, Ld->getChain(), NewAddr,
8191 DAG.getMachineFunction().getMachineMemOperand(
8192 Ld->getMemOperand(), Offset, SVT.getStoreSize()));
8193 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8194 // We can't broadcast from a vector register without AVX2, and we can only
8195 // broadcast from the zero-element of a vector register.
8199 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8202 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8203 // INSERTPS when the V1 elements are already in the correct locations
8204 // because otherwise we can just always use two SHUFPS instructions which
8205 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8206 // perform INSERTPS if a single V1 element is out of place and all V2
8207 // elements are zeroable.
8208 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8210 SelectionDAG &DAG) {
8211 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8212 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8213 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8214 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8216 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8219 int V1DstIndex = -1;
8220 int V2DstIndex = -1;
8221 bool V1UsedInPlace = false;
8223 for (int i = 0; i < 4; ++i) {
8224 // Synthesize a zero mask from the zeroable elements (includes undefs).
8230 // Flag if we use any V1 inputs in place.
8232 V1UsedInPlace = true;
8236 // We can only insert a single non-zeroable element.
8237 if (V1DstIndex != -1 || V2DstIndex != -1)
8241 // V1 input out of place for insertion.
8244 // V2 input for insertion.
8249 // Don't bother if we have no (non-zeroable) element for insertion.
8250 if (V1DstIndex == -1 && V2DstIndex == -1)
8253 // Determine element insertion src/dst indices. The src index is from the
8254 // start of the inserted vector, not the start of the concatenated vector.
8255 unsigned V2SrcIndex = 0;
8256 if (V1DstIndex != -1) {
8257 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8258 // and don't use the original V2 at all.
8259 V2SrcIndex = Mask[V1DstIndex];
8260 V2DstIndex = V1DstIndex;
8263 V2SrcIndex = Mask[V2DstIndex] - 4;
8266 // If no V1 inputs are used in place, then the result is created only from
8267 // the zero mask and the V2 insertion - so remove V1 dependency.
8269 V1 = DAG.getUNDEF(MVT::v4f32);
8271 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8272 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8274 // Insert the V2 element into the desired position.
8276 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8277 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8280 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8281 /// UNPCK instruction.
8283 /// This specifically targets cases where we end up with alternating between
8284 /// the two inputs, and so can permute them into something that feeds a single
8285 /// UNPCK instruction. Note that this routine only targets integer vectors
8286 /// because for floating point vectors we have a generalized SHUFPS lowering
8287 /// strategy that handles everything that doesn't *exactly* match an unpack,
8288 /// making this clever lowering unnecessary.
8289 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8290 SDValue V1, SDValue V2,
8292 SelectionDAG &DAG) {
8293 assert(!VT.isFloatingPoint() &&
8294 "This routine only supports integer vectors.");
8295 assert(!isSingleInputShuffleMask(Mask) &&
8296 "This routine should only be used when blending two inputs.");
8297 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8299 int Size = Mask.size();
8301 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8302 return M >= 0 && M % Size < Size / 2;
8304 int NumHiInputs = std::count_if(
8305 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8307 bool UnpackLo = NumLoInputs >= NumHiInputs;
8309 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8310 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8311 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8313 for (int i = 0; i < Size; ++i) {
8317 // Each element of the unpack contains Scale elements from this mask.
8318 int UnpackIdx = i / Scale;
8320 // We only handle the case where V1 feeds the first slots of the unpack.
8321 // We rely on canonicalization to ensure this is the case.
8322 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8325 // Setup the mask for this input. The indexing is tricky as we have to
8326 // handle the unpack stride.
8327 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8328 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8332 // If we will have to shuffle both inputs to use the unpack, check whether
8333 // we can just unpack first and shuffle the result. If so, skip this unpack.
8334 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8335 !isNoopShuffleMask(V2Mask))
8338 // Shuffle the inputs into place.
8339 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8340 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8342 // Cast the inputs to the type we will use to unpack them.
8343 V1 = DAG.getBitcast(UnpackVT, V1);
8344 V2 = DAG.getBitcast(UnpackVT, V2);
8346 // Unpack the inputs and cast the result back to the desired type.
8347 return DAG.getBitcast(
8348 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8352 // We try each unpack from the largest to the smallest to try and find one
8353 // that fits this mask.
8354 int OrigNumElements = VT.getVectorNumElements();
8355 int OrigScalarSize = VT.getScalarSizeInBits();
8356 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8357 int Scale = ScalarSize / OrigScalarSize;
8358 int NumElements = OrigNumElements / Scale;
8359 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8360 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8364 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8366 if (NumLoInputs == 0 || NumHiInputs == 0) {
8367 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8368 "We have to have *some* inputs!");
8369 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8371 // FIXME: We could consider the total complexity of the permute of each
8372 // possible unpacking. Or at the least we should consider how many
8373 // half-crossings are created.
8374 // FIXME: We could consider commuting the unpacks.
8376 SmallVector<int, 32> PermMask;
8377 PermMask.assign(Size, -1);
8378 for (int i = 0; i < Size; ++i) {
8382 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8385 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8387 return DAG.getVectorShuffle(
8388 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8390 DAG.getUNDEF(VT), PermMask);
8396 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8398 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8399 /// support for floating point shuffles but not integer shuffles. These
8400 /// instructions will incur a domain crossing penalty on some chips though so
8401 /// it is better to avoid lowering through this for integer vectors where
8403 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8404 const X86Subtarget *Subtarget,
8405 SelectionDAG &DAG) {
8407 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8408 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8409 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8410 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8411 ArrayRef<int> Mask = SVOp->getMask();
8412 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8414 if (isSingleInputShuffleMask(Mask)) {
8415 // Use low duplicate instructions for masks that match their pattern.
8416 if (Subtarget->hasSSE3())
8417 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8418 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8420 // Straight shuffle of a single input vector. Simulate this by using the
8421 // single input as both of the "inputs" to this instruction..
8422 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8424 if (Subtarget->hasAVX()) {
8425 // If we have AVX, we can use VPERMILPS which will allow folding a load
8426 // into the shuffle.
8427 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8428 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8431 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8432 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8434 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8435 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8437 // If we have a single input, insert that into V1 if we can do so cheaply.
8438 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8439 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8440 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8442 // Try inverting the insertion since for v2 masks it is easy to do and we
8443 // can't reliably sort the mask one way or the other.
8444 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8445 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8446 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8447 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8451 // Try to use one of the special instruction patterns to handle two common
8452 // blend patterns if a zero-blend above didn't work.
8453 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8454 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8455 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8456 // We can either use a special instruction to load over the low double or
8457 // to move just the low double.
8459 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8461 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8463 if (Subtarget->hasSSE41())
8464 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8468 // Use dedicated unpack instructions for masks that match their pattern.
8470 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8473 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8474 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8475 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8478 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8480 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8481 /// the integer unit to minimize domain crossing penalties. However, for blends
8482 /// it falls back to the floating point shuffle operation with appropriate bit
8484 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8485 const X86Subtarget *Subtarget,
8486 SelectionDAG &DAG) {
8488 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8489 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8490 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8491 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8492 ArrayRef<int> Mask = SVOp->getMask();
8493 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8495 if (isSingleInputShuffleMask(Mask)) {
8496 // Check for being able to broadcast a single element.
8497 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8498 Mask, Subtarget, DAG))
8501 // Straight shuffle of a single input vector. For everything from SSE2
8502 // onward this has a single fast instruction with no scary immediates.
8503 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8504 V1 = DAG.getBitcast(MVT::v4i32, V1);
8505 int WidenedMask[4] = {
8506 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8507 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8508 return DAG.getBitcast(
8510 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8511 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8513 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8514 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8515 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8516 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8518 // If we have a blend of two PACKUS operations an the blend aligns with the
8519 // low and half halves, we can just merge the PACKUS operations. This is
8520 // particularly important as it lets us merge shuffles that this routine itself
8522 auto GetPackNode = [](SDValue V) {
8523 while (V.getOpcode() == ISD::BITCAST)
8524 V = V.getOperand(0);
8526 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8528 if (SDValue V1Pack = GetPackNode(V1))
8529 if (SDValue V2Pack = GetPackNode(V2))
8530 return DAG.getBitcast(MVT::v2i64,
8531 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8532 Mask[0] == 0 ? V1Pack.getOperand(0)
8533 : V1Pack.getOperand(1),
8534 Mask[1] == 2 ? V2Pack.getOperand(0)
8535 : V2Pack.getOperand(1)));
8537 // Try to use shift instructions.
8539 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8542 // When loading a scalar and then shuffling it into a vector we can often do
8543 // the insertion cheaply.
8544 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8545 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8547 // Try inverting the insertion since for v2 masks it is easy to do and we
8548 // can't reliably sort the mask one way or the other.
8549 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8550 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8551 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8554 // We have different paths for blend lowering, but they all must use the
8555 // *exact* same predicate.
8556 bool IsBlendSupported = Subtarget->hasSSE41();
8557 if (IsBlendSupported)
8558 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8562 // Use dedicated unpack instructions for masks that match their pattern.
8564 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8567 // Try to use byte rotation instructions.
8568 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8569 if (Subtarget->hasSSSE3())
8570 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8571 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8574 // If we have direct support for blends, we should lower by decomposing into
8575 // a permute. That will be faster than the domain cross.
8576 if (IsBlendSupported)
8577 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8580 // We implement this with SHUFPD which is pretty lame because it will likely
8581 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8582 // However, all the alternatives are still more cycles and newer chips don't
8583 // have this problem. It would be really nice if x86 had better shuffles here.
8584 V1 = DAG.getBitcast(MVT::v2f64, V1);
8585 V2 = DAG.getBitcast(MVT::v2f64, V2);
8586 return DAG.getBitcast(MVT::v2i64,
8587 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8590 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8592 /// This is used to disable more specialized lowerings when the shufps lowering
8593 /// will happen to be efficient.
8594 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8595 // This routine only handles 128-bit shufps.
8596 assert(Mask.size() == 4 && "Unsupported mask size!");
8598 // To lower with a single SHUFPS we need to have the low half and high half
8599 // each requiring a single input.
8600 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8602 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8608 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8610 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8611 /// It makes no assumptions about whether this is the *best* lowering, it simply
8613 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8614 ArrayRef<int> Mask, SDValue V1,
8615 SDValue V2, SelectionDAG &DAG) {
8616 SDValue LowV = V1, HighV = V2;
8617 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8620 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8622 if (NumV2Elements == 1) {
8624 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8627 // Compute the index adjacent to V2Index and in the same half by toggling
8629 int V2AdjIndex = V2Index ^ 1;
8631 if (Mask[V2AdjIndex] == -1) {
8632 // Handles all the cases where we have a single V2 element and an undef.
8633 // This will only ever happen in the high lanes because we commute the
8634 // vector otherwise.
8636 std::swap(LowV, HighV);
8637 NewMask[V2Index] -= 4;
8639 // Handle the case where the V2 element ends up adjacent to a V1 element.
8640 // To make this work, blend them together as the first step.
8641 int V1Index = V2AdjIndex;
8642 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8643 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8644 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8646 // Now proceed to reconstruct the final blend as we have the necessary
8647 // high or low half formed.
8654 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8655 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8657 } else if (NumV2Elements == 2) {
8658 if (Mask[0] < 4 && Mask[1] < 4) {
8659 // Handle the easy case where we have V1 in the low lanes and V2 in the
8663 } else if (Mask[2] < 4 && Mask[3] < 4) {
8664 // We also handle the reversed case because this utility may get called
8665 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8666 // arrange things in the right direction.
8672 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8673 // trying to place elements directly, just blend them and set up the final
8674 // shuffle to place them.
8676 // The first two blend mask elements are for V1, the second two are for
8678 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8679 Mask[2] < 4 ? Mask[2] : Mask[3],
8680 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8681 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8682 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8683 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8685 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8688 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8689 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8690 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8691 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8694 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8695 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8698 /// \brief Lower 4-lane 32-bit floating point shuffles.
8700 /// Uses instructions exclusively from the floating point unit to minimize
8701 /// domain crossing penalties, as these are sufficient to implement all v4f32
8703 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8704 const X86Subtarget *Subtarget,
8705 SelectionDAG &DAG) {
8707 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8708 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8709 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8710 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8711 ArrayRef<int> Mask = SVOp->getMask();
8712 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8715 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8717 if (NumV2Elements == 0) {
8718 // Check for being able to broadcast a single element.
8719 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8720 Mask, Subtarget, DAG))
8723 // Use even/odd duplicate instructions for masks that match their pattern.
8724 if (Subtarget->hasSSE3()) {
8725 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8726 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8727 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8728 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8731 if (Subtarget->hasAVX()) {
8732 // If we have AVX, we can use VPERMILPS which will allow folding a load
8733 // into the shuffle.
8734 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8735 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8738 // Otherwise, use a straight shuffle of a single input vector. We pass the
8739 // input vector to both operands to simulate this with a SHUFPS.
8740 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8741 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8744 // There are special ways we can lower some single-element blends. However, we
8745 // have custom ways we can lower more complex single-element blends below that
8746 // we defer to if both this and BLENDPS fail to match, so restrict this to
8747 // when the V2 input is targeting element 0 of the mask -- that is the fast
8749 if (NumV2Elements == 1 && Mask[0] >= 4)
8750 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8751 Mask, Subtarget, DAG))
8754 if (Subtarget->hasSSE41()) {
8755 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8759 // Use INSERTPS if we can complete the shuffle efficiently.
8760 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8763 if (!isSingleSHUFPSMask(Mask))
8764 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8765 DL, MVT::v4f32, V1, V2, Mask, DAG))
8769 // Use dedicated unpack instructions for masks that match their pattern.
8771 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8774 // Otherwise fall back to a SHUFPS lowering strategy.
8775 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8778 /// \brief Lower 4-lane i32 vector shuffles.
8780 /// We try to handle these with integer-domain shuffles where we can, but for
8781 /// blends we use the floating point domain blend instructions.
8782 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8783 const X86Subtarget *Subtarget,
8784 SelectionDAG &DAG) {
8786 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8787 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8788 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8789 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8790 ArrayRef<int> Mask = SVOp->getMask();
8791 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8793 // Whenever we can lower this as a zext, that instruction is strictly faster
8794 // than any alternative. It also allows us to fold memory operands into the
8795 // shuffle in many cases.
8796 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8797 Mask, Subtarget, DAG))
8801 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8803 if (NumV2Elements == 0) {
8804 // Check for being able to broadcast a single element.
8805 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8806 Mask, Subtarget, DAG))
8809 // Straight shuffle of a single input vector. For everything from SSE2
8810 // onward this has a single fast instruction with no scary immediates.
8811 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8812 // but we aren't actually going to use the UNPCK instruction because doing
8813 // so prevents folding a load into this instruction or making a copy.
8814 const int UnpackLoMask[] = {0, 0, 1, 1};
8815 const int UnpackHiMask[] = {2, 2, 3, 3};
8816 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8817 Mask = UnpackLoMask;
8818 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8819 Mask = UnpackHiMask;
8821 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8822 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8825 // Try to use shift instructions.
8827 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8830 // There are special ways we can lower some single-element blends.
8831 if (NumV2Elements == 1)
8832 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8833 Mask, Subtarget, DAG))
8836 // We have different paths for blend lowering, but they all must use the
8837 // *exact* same predicate.
8838 bool IsBlendSupported = Subtarget->hasSSE41();
8839 if (IsBlendSupported)
8840 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8844 if (SDValue Masked =
8845 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8848 // Use dedicated unpack instructions for masks that match their pattern.
8850 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8853 // Try to use byte rotation instructions.
8854 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8855 if (Subtarget->hasSSSE3())
8856 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8857 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8860 // If we have direct support for blends, we should lower by decomposing into
8861 // a permute. That will be faster than the domain cross.
8862 if (IsBlendSupported)
8863 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8866 // Try to lower by permuting the inputs into an unpack instruction.
8867 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8871 // We implement this with SHUFPS because it can blend from two vectors.
8872 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8873 // up the inputs, bypassing domain shift penalties that we would encur if we
8874 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8876 return DAG.getBitcast(
8878 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8879 DAG.getBitcast(MVT::v4f32, V2), Mask));
8882 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8883 /// shuffle lowering, and the most complex part.
8885 /// The lowering strategy is to try to form pairs of input lanes which are
8886 /// targeted at the same half of the final vector, and then use a dword shuffle
8887 /// to place them onto the right half, and finally unpack the paired lanes into
8888 /// their final position.
8890 /// The exact breakdown of how to form these dword pairs and align them on the
8891 /// correct sides is really tricky. See the comments within the function for
8892 /// more of the details.
8894 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8895 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8896 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8897 /// vector, form the analogous 128-bit 8-element Mask.
8898 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8899 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8900 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8901 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8902 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8904 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8905 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8906 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8908 SmallVector<int, 4> LoInputs;
8909 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8910 [](int M) { return M >= 0; });
8911 std::sort(LoInputs.begin(), LoInputs.end());
8912 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8913 SmallVector<int, 4> HiInputs;
8914 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8915 [](int M) { return M >= 0; });
8916 std::sort(HiInputs.begin(), HiInputs.end());
8917 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8919 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8920 int NumHToL = LoInputs.size() - NumLToL;
8922 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8923 int NumHToH = HiInputs.size() - NumLToH;
8924 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8925 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8926 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8927 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8929 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8930 // such inputs we can swap two of the dwords across the half mark and end up
8931 // with <=2 inputs to each half in each half. Once there, we can fall through
8932 // to the generic code below. For example:
8934 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8935 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8937 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8938 // and an existing 2-into-2 on the other half. In this case we may have to
8939 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8940 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8941 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8942 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8943 // half than the one we target for fixing) will be fixed when we re-enter this
8944 // path. We will also combine away any sequence of PSHUFD instructions that
8945 // result into a single instruction. Here is an example of the tricky case:
8947 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8948 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8950 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8952 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8953 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8955 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8956 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8958 // The result is fine to be handled by the generic logic.
8959 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8960 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8961 int AOffset, int BOffset) {
8962 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8963 "Must call this with A having 3 or 1 inputs from the A half.");
8964 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8965 "Must call this with B having 1 or 3 inputs from the B half.");
8966 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8967 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8969 bool ThreeAInputs = AToAInputs.size() == 3;
8971 // Compute the index of dword with only one word among the three inputs in
8972 // a half by taking the sum of the half with three inputs and subtracting
8973 // the sum of the actual three inputs. The difference is the remaining
8976 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8977 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8978 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8979 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8980 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8981 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8982 int TripleNonInputIdx =
8983 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8984 TripleDWord = TripleNonInputIdx / 2;
8986 // We use xor with one to compute the adjacent DWord to whichever one the
8988 OneInputDWord = (OneInput / 2) ^ 1;
8990 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8991 // and BToA inputs. If there is also such a problem with the BToB and AToB
8992 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8993 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8994 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8995 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8996 // Compute how many inputs will be flipped by swapping these DWords. We
8998 // to balance this to ensure we don't form a 3-1 shuffle in the other
9000 int NumFlippedAToBInputs =
9001 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
9002 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
9003 int NumFlippedBToBInputs =
9004 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
9005 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
9006 if ((NumFlippedAToBInputs == 1 &&
9007 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
9008 (NumFlippedBToBInputs == 1 &&
9009 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
9010 // We choose whether to fix the A half or B half based on whether that
9011 // half has zero flipped inputs. At zero, we may not be able to fix it
9012 // with that half. We also bias towards fixing the B half because that
9013 // will more commonly be the high half, and we have to bias one way.
9014 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
9015 ArrayRef<int> Inputs) {
9016 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
9017 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
9018 PinnedIdx ^ 1) != Inputs.end();
9019 // Determine whether the free index is in the flipped dword or the
9020 // unflipped dword based on where the pinned index is. We use this bit
9021 // in an xor to conditionally select the adjacent dword.
9022 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
9023 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
9024 FixFreeIdx) != Inputs.end();
9025 if (IsFixIdxInput == IsFixFreeIdxInput)
9027 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
9028 FixFreeIdx) != Inputs.end();
9029 assert(IsFixIdxInput != IsFixFreeIdxInput &&
9030 "We need to be changing the number of flipped inputs!");
9031 int PSHUFHalfMask[] = {0, 1, 2, 3};
9032 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
9033 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
9035 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
9038 if (M != -1 && M == FixIdx)
9040 else if (M != -1 && M == FixFreeIdx)
9043 if (NumFlippedBToBInputs != 0) {
9045 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
9046 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
9048 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
9049 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
9050 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
9055 int PSHUFDMask[] = {0, 1, 2, 3};
9056 PSHUFDMask[ADWord] = BDWord;
9057 PSHUFDMask[BDWord] = ADWord;
9060 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9061 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9063 // Adjust the mask to match the new locations of A and B.
9065 if (M != -1 && M/2 == ADWord)
9066 M = 2 * BDWord + M % 2;
9067 else if (M != -1 && M/2 == BDWord)
9068 M = 2 * ADWord + M % 2;
9070 // Recurse back into this routine to re-compute state now that this isn't
9071 // a 3 and 1 problem.
9072 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
9075 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
9076 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
9077 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
9078 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
9080 // At this point there are at most two inputs to the low and high halves from
9081 // each half. That means the inputs can always be grouped into dwords and
9082 // those dwords can then be moved to the correct half with a dword shuffle.
9083 // We use at most one low and one high word shuffle to collect these paired
9084 // inputs into dwords, and finally a dword shuffle to place them.
9085 int PSHUFLMask[4] = {-1, -1, -1, -1};
9086 int PSHUFHMask[4] = {-1, -1, -1, -1};
9087 int PSHUFDMask[4] = {-1, -1, -1, -1};
9089 // First fix the masks for all the inputs that are staying in their
9090 // original halves. This will then dictate the targets of the cross-half
9092 auto fixInPlaceInputs =
9093 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
9094 MutableArrayRef<int> SourceHalfMask,
9095 MutableArrayRef<int> HalfMask, int HalfOffset) {
9096 if (InPlaceInputs.empty())
9098 if (InPlaceInputs.size() == 1) {
9099 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9100 InPlaceInputs[0] - HalfOffset;
9101 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
9104 if (IncomingInputs.empty()) {
9105 // Just fix all of the in place inputs.
9106 for (int Input : InPlaceInputs) {
9107 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
9108 PSHUFDMask[Input / 2] = Input / 2;
9113 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
9114 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9115 InPlaceInputs[0] - HalfOffset;
9116 // Put the second input next to the first so that they are packed into
9117 // a dword. We find the adjacent index by toggling the low bit.
9118 int AdjIndex = InPlaceInputs[0] ^ 1;
9119 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
9120 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
9121 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
9123 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
9124 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
9126 // Now gather the cross-half inputs and place them into a free dword of
9127 // their target half.
9128 // FIXME: This operation could almost certainly be simplified dramatically to
9129 // look more like the 3-1 fixing operation.
9130 auto moveInputsToRightHalf = [&PSHUFDMask](
9131 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
9132 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
9133 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
9135 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
9136 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
9138 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
9140 int LowWord = Word & ~1;
9141 int HighWord = Word | 1;
9142 return isWordClobbered(SourceHalfMask, LowWord) ||
9143 isWordClobbered(SourceHalfMask, HighWord);
9146 if (IncomingInputs.empty())
9149 if (ExistingInputs.empty()) {
9150 // Map any dwords with inputs from them into the right half.
9151 for (int Input : IncomingInputs) {
9152 // If the source half mask maps over the inputs, turn those into
9153 // swaps and use the swapped lane.
9154 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
9155 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
9156 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
9157 Input - SourceOffset;
9158 // We have to swap the uses in our half mask in one sweep.
9159 for (int &M : HalfMask)
9160 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
9162 else if (M == Input)
9163 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9165 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
9166 Input - SourceOffset &&
9167 "Previous placement doesn't match!");
9169 // Note that this correctly re-maps both when we do a swap and when
9170 // we observe the other side of the swap above. We rely on that to
9171 // avoid swapping the members of the input list directly.
9172 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9175 // Map the input's dword into the correct half.
9176 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
9177 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
9179 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
9181 "Previous placement doesn't match!");
9184 // And just directly shift any other-half mask elements to be same-half
9185 // as we will have mirrored the dword containing the element into the
9186 // same position within that half.
9187 for (int &M : HalfMask)
9188 if (M >= SourceOffset && M < SourceOffset + 4) {
9189 M = M - SourceOffset + DestOffset;
9190 assert(M >= 0 && "This should never wrap below zero!");
9195 // Ensure we have the input in a viable dword of its current half. This
9196 // is particularly tricky because the original position may be clobbered
9197 // by inputs being moved and *staying* in that half.
9198 if (IncomingInputs.size() == 1) {
9199 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9200 int InputFixed = std::find(std::begin(SourceHalfMask),
9201 std::end(SourceHalfMask), -1) -
9202 std::begin(SourceHalfMask) + SourceOffset;
9203 SourceHalfMask[InputFixed - SourceOffset] =
9204 IncomingInputs[0] - SourceOffset;
9205 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9207 IncomingInputs[0] = InputFixed;
9209 } else if (IncomingInputs.size() == 2) {
9210 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9211 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9212 // We have two non-adjacent or clobbered inputs we need to extract from
9213 // the source half. To do this, we need to map them into some adjacent
9214 // dword slot in the source mask.
9215 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9216 IncomingInputs[1] - SourceOffset};
9218 // If there is a free slot in the source half mask adjacent to one of
9219 // the inputs, place the other input in it. We use (Index XOR 1) to
9220 // compute an adjacent index.
9221 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9222 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9223 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9224 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9225 InputsFixed[1] = InputsFixed[0] ^ 1;
9226 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9227 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9228 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9229 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9230 InputsFixed[0] = InputsFixed[1] ^ 1;
9231 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9232 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9233 // The two inputs are in the same DWord but it is clobbered and the
9234 // adjacent DWord isn't used at all. Move both inputs to the free
9236 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9237 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9238 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9239 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9241 // The only way we hit this point is if there is no clobbering
9242 // (because there are no off-half inputs to this half) and there is no
9243 // free slot adjacent to one of the inputs. In this case, we have to
9244 // swap an input with a non-input.
9245 for (int i = 0; i < 4; ++i)
9246 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9247 "We can't handle any clobbers here!");
9248 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9249 "Cannot have adjacent inputs here!");
9251 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9252 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9254 // We also have to update the final source mask in this case because
9255 // it may need to undo the above swap.
9256 for (int &M : FinalSourceHalfMask)
9257 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9258 M = InputsFixed[1] + SourceOffset;
9259 else if (M == InputsFixed[1] + SourceOffset)
9260 M = (InputsFixed[0] ^ 1) + SourceOffset;
9262 InputsFixed[1] = InputsFixed[0] ^ 1;
9265 // Point everything at the fixed inputs.
9266 for (int &M : HalfMask)
9267 if (M == IncomingInputs[0])
9268 M = InputsFixed[0] + SourceOffset;
9269 else if (M == IncomingInputs[1])
9270 M = InputsFixed[1] + SourceOffset;
9272 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9273 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9276 llvm_unreachable("Unhandled input size!");
9279 // Now hoist the DWord down to the right half.
9280 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9281 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9282 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9283 for (int &M : HalfMask)
9284 for (int Input : IncomingInputs)
9286 M = FreeDWord * 2 + Input % 2;
9288 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9289 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9290 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9291 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9293 // Now enact all the shuffles we've computed to move the inputs into their
9295 if (!isNoopShuffleMask(PSHUFLMask))
9296 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9297 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9298 if (!isNoopShuffleMask(PSHUFHMask))
9299 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9300 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9301 if (!isNoopShuffleMask(PSHUFDMask))
9304 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9305 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9307 // At this point, each half should contain all its inputs, and we can then
9308 // just shuffle them into their final position.
9309 assert(std::count_if(LoMask.begin(), LoMask.end(),
9310 [](int M) { return M >= 4; }) == 0 &&
9311 "Failed to lift all the high half inputs to the low mask!");
9312 assert(std::count_if(HiMask.begin(), HiMask.end(),
9313 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9314 "Failed to lift all the low half inputs to the high mask!");
9316 // Do a half shuffle for the low mask.
9317 if (!isNoopShuffleMask(LoMask))
9318 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9319 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9321 // Do a half shuffle with the high mask after shifting its values down.
9322 for (int &M : HiMask)
9325 if (!isNoopShuffleMask(HiMask))
9326 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9327 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9332 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9333 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9334 SDValue V2, ArrayRef<int> Mask,
9335 SelectionDAG &DAG, bool &V1InUse,
9337 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9343 int Size = Mask.size();
9344 int Scale = 16 / Size;
9345 for (int i = 0; i < 16; ++i) {
9346 if (Mask[i / Scale] == -1) {
9347 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9349 const int ZeroMask = 0x80;
9350 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9352 int V2Idx = Mask[i / Scale] < Size
9354 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9355 if (Zeroable[i / Scale])
9356 V1Idx = V2Idx = ZeroMask;
9357 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9358 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9359 V1InUse |= (ZeroMask != V1Idx);
9360 V2InUse |= (ZeroMask != V2Idx);
9365 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9366 DAG.getBitcast(MVT::v16i8, V1),
9367 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9369 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9370 DAG.getBitcast(MVT::v16i8, V2),
9371 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9373 // If we need shuffled inputs from both, blend the two.
9375 if (V1InUse && V2InUse)
9376 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9378 V = V1InUse ? V1 : V2;
9380 // Cast the result back to the correct type.
9381 return DAG.getBitcast(VT, V);
9384 /// \brief Generic lowering of 8-lane i16 shuffles.
9386 /// This handles both single-input shuffles and combined shuffle/blends with
9387 /// two inputs. The single input shuffles are immediately delegated to
9388 /// a dedicated lowering routine.
9390 /// The blends are lowered in one of three fundamental ways. If there are few
9391 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9392 /// of the input is significantly cheaper when lowered as an interleaving of
9393 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9394 /// halves of the inputs separately (making them have relatively few inputs)
9395 /// and then concatenate them.
9396 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9397 const X86Subtarget *Subtarget,
9398 SelectionDAG &DAG) {
9400 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9401 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9402 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9403 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9404 ArrayRef<int> OrigMask = SVOp->getMask();
9405 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9406 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9407 MutableArrayRef<int> Mask(MaskStorage);
9409 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9411 // Whenever we can lower this as a zext, that instruction is strictly faster
9412 // than any alternative.
9413 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9414 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9417 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9419 auto isV2 = [](int M) { return M >= 8; };
9421 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9423 if (NumV2Inputs == 0) {
9424 // Check for being able to broadcast a single element.
9425 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9426 Mask, Subtarget, DAG))
9429 // Try to use shift instructions.
9431 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9434 // Use dedicated unpack instructions for masks that match their pattern.
9436 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9439 // Try to use byte rotation instructions.
9440 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9441 Mask, Subtarget, DAG))
9444 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9448 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9449 "All single-input shuffles should be canonicalized to be V1-input "
9452 // Try to use shift instructions.
9454 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9457 // See if we can use SSE4A Extraction / Insertion.
9458 if (Subtarget->hasSSE4A())
9459 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9462 // There are special ways we can lower some single-element blends.
9463 if (NumV2Inputs == 1)
9464 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9465 Mask, Subtarget, DAG))
9468 // We have different paths for blend lowering, but they all must use the
9469 // *exact* same predicate.
9470 bool IsBlendSupported = Subtarget->hasSSE41();
9471 if (IsBlendSupported)
9472 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9476 if (SDValue Masked =
9477 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9480 // Use dedicated unpack instructions for masks that match their pattern.
9482 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9485 // Try to use byte rotation instructions.
9486 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9487 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9490 if (SDValue BitBlend =
9491 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9494 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9498 // If we can't directly blend but can use PSHUFB, that will be better as it
9499 // can both shuffle and set up the inefficient blend.
9500 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9501 bool V1InUse, V2InUse;
9502 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9506 // We can always bit-blend if we have to so the fallback strategy is to
9507 // decompose into single-input permutes and blends.
9508 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9512 /// \brief Check whether a compaction lowering can be done by dropping even
9513 /// elements and compute how many times even elements must be dropped.
9515 /// This handles shuffles which take every Nth element where N is a power of
9516 /// two. Example shuffle masks:
9518 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9519 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9520 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9521 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9522 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9523 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9525 /// Any of these lanes can of course be undef.
9527 /// This routine only supports N <= 3.
9528 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9531 /// \returns N above, or the number of times even elements must be dropped if
9532 /// there is such a number. Otherwise returns zero.
9533 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9534 // Figure out whether we're looping over two inputs or just one.
9535 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9537 // The modulus for the shuffle vector entries is based on whether this is
9538 // a single input or not.
9539 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9540 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9541 "We should only be called with masks with a power-of-2 size!");
9543 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9545 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9546 // and 2^3 simultaneously. This is because we may have ambiguity with
9547 // partially undef inputs.
9548 bool ViableForN[3] = {true, true, true};
9550 for (int i = 0, e = Mask.size(); i < e; ++i) {
9551 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9556 bool IsAnyViable = false;
9557 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9558 if (ViableForN[j]) {
9561 // The shuffle mask must be equal to (i * 2^N) % M.
9562 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9565 ViableForN[j] = false;
9567 // Early exit if we exhaust the possible powers of two.
9572 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9576 // Return 0 as there is no viable power of two.
9580 /// \brief Generic lowering of v16i8 shuffles.
9582 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9583 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9584 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9585 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9587 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9588 const X86Subtarget *Subtarget,
9589 SelectionDAG &DAG) {
9591 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9592 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9593 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9594 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9595 ArrayRef<int> Mask = SVOp->getMask();
9596 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9598 // Try to use shift instructions.
9600 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9603 // Try to use byte rotation instructions.
9604 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9605 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9608 // Try to use a zext lowering.
9609 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9610 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9613 // See if we can use SSE4A Extraction / Insertion.
9614 if (Subtarget->hasSSE4A())
9615 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9619 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9621 // For single-input shuffles, there are some nicer lowering tricks we can use.
9622 if (NumV2Elements == 0) {
9623 // Check for being able to broadcast a single element.
9624 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9625 Mask, Subtarget, DAG))
9628 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9629 // Notably, this handles splat and partial-splat shuffles more efficiently.
9630 // However, it only makes sense if the pre-duplication shuffle simplifies
9631 // things significantly. Currently, this means we need to be able to
9632 // express the pre-duplication shuffle as an i16 shuffle.
9634 // FIXME: We should check for other patterns which can be widened into an
9635 // i16 shuffle as well.
9636 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9637 for (int i = 0; i < 16; i += 2)
9638 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9643 auto tryToWidenViaDuplication = [&]() -> SDValue {
9644 if (!canWidenViaDuplication(Mask))
9646 SmallVector<int, 4> LoInputs;
9647 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9648 [](int M) { return M >= 0 && M < 8; });
9649 std::sort(LoInputs.begin(), LoInputs.end());
9650 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9652 SmallVector<int, 4> HiInputs;
9653 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9654 [](int M) { return M >= 8; });
9655 std::sort(HiInputs.begin(), HiInputs.end());
9656 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9659 bool TargetLo = LoInputs.size() >= HiInputs.size();
9660 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9661 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9663 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9664 SmallDenseMap<int, int, 8> LaneMap;
9665 for (int I : InPlaceInputs) {
9666 PreDupI16Shuffle[I/2] = I/2;
9669 int j = TargetLo ? 0 : 4, je = j + 4;
9670 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9671 // Check if j is already a shuffle of this input. This happens when
9672 // there are two adjacent bytes after we move the low one.
9673 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9674 // If we haven't yet mapped the input, search for a slot into which
9676 while (j < je && PreDupI16Shuffle[j] != -1)
9680 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9683 // Map this input with the i16 shuffle.
9684 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9687 // Update the lane map based on the mapping we ended up with.
9688 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9690 V1 = DAG.getBitcast(
9692 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9693 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9695 // Unpack the bytes to form the i16s that will be shuffled into place.
9696 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9697 MVT::v16i8, V1, V1);
9699 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9700 for (int i = 0; i < 16; ++i)
9701 if (Mask[i] != -1) {
9702 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9703 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9704 if (PostDupI16Shuffle[i / 2] == -1)
9705 PostDupI16Shuffle[i / 2] = MappedMask;
9707 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9708 "Conflicting entrties in the original shuffle!");
9710 return DAG.getBitcast(
9712 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9713 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9715 if (SDValue V = tryToWidenViaDuplication())
9719 if (SDValue Masked =
9720 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9723 // Use dedicated unpack instructions for masks that match their pattern.
9725 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9728 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9729 // with PSHUFB. It is important to do this before we attempt to generate any
9730 // blends but after all of the single-input lowerings. If the single input
9731 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9732 // want to preserve that and we can DAG combine any longer sequences into
9733 // a PSHUFB in the end. But once we start blending from multiple inputs,
9734 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9735 // and there are *very* few patterns that would actually be faster than the
9736 // PSHUFB approach because of its ability to zero lanes.
9738 // FIXME: The only exceptions to the above are blends which are exact
9739 // interleavings with direct instructions supporting them. We currently don't
9740 // handle those well here.
9741 if (Subtarget->hasSSSE3()) {
9742 bool V1InUse = false;
9743 bool V2InUse = false;
9745 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9746 DAG, V1InUse, V2InUse);
9748 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9749 // do so. This avoids using them to handle blends-with-zero which is
9750 // important as a single pshufb is significantly faster for that.
9751 if (V1InUse && V2InUse) {
9752 if (Subtarget->hasSSE41())
9753 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9754 Mask, Subtarget, DAG))
9757 // We can use an unpack to do the blending rather than an or in some
9758 // cases. Even though the or may be (very minorly) more efficient, we
9759 // preference this lowering because there are common cases where part of
9760 // the complexity of the shuffles goes away when we do the final blend as
9762 // FIXME: It might be worth trying to detect if the unpack-feeding
9763 // shuffles will both be pshufb, in which case we shouldn't bother with
9765 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9766 DL, MVT::v16i8, V1, V2, Mask, DAG))
9773 // There are special ways we can lower some single-element blends.
9774 if (NumV2Elements == 1)
9775 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9776 Mask, Subtarget, DAG))
9779 if (SDValue BitBlend =
9780 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9783 // Check whether a compaction lowering can be done. This handles shuffles
9784 // which take every Nth element for some even N. See the helper function for
9787 // We special case these as they can be particularly efficiently handled with
9788 // the PACKUSB instruction on x86 and they show up in common patterns of
9789 // rearranging bytes to truncate wide elements.
9790 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9791 // NumEvenDrops is the power of two stride of the elements. Another way of
9792 // thinking about it is that we need to drop the even elements this many
9793 // times to get the original input.
9794 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9796 // First we need to zero all the dropped bytes.
9797 assert(NumEvenDrops <= 3 &&
9798 "No support for dropping even elements more than 3 times.");
9799 // We use the mask type to pick which bytes are preserved based on how many
9800 // elements are dropped.
9801 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9802 SDValue ByteClearMask = DAG.getBitcast(
9803 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9804 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9806 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9808 // Now pack things back together.
9809 V1 = DAG.getBitcast(MVT::v8i16, V1);
9810 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9811 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9812 for (int i = 1; i < NumEvenDrops; ++i) {
9813 Result = DAG.getBitcast(MVT::v8i16, Result);
9814 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9820 // Handle multi-input cases by blending single-input shuffles.
9821 if (NumV2Elements > 0)
9822 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9825 // The fallback path for single-input shuffles widens this into two v8i16
9826 // vectors with unpacks, shuffles those, and then pulls them back together
9830 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9831 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9832 for (int i = 0; i < 16; ++i)
9834 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9836 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9838 SDValue VLoHalf, VHiHalf;
9839 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9840 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9842 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9843 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9844 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9845 [](int M) { return M >= 0 && M % 2 == 1; })) {
9846 // Use a mask to drop the high bytes.
9847 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9848 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9849 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9851 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9852 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9854 // Squash the masks to point directly into VLoHalf.
9855 for (int &M : LoBlendMask)
9858 for (int &M : HiBlendMask)
9862 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9863 // VHiHalf so that we can blend them as i16s.
9864 VLoHalf = DAG.getBitcast(
9865 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9866 VHiHalf = DAG.getBitcast(
9867 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9870 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9871 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9873 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9876 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9878 /// This routine breaks down the specific type of 128-bit shuffle and
9879 /// dispatches to the lowering routines accordingly.
9880 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9881 MVT VT, const X86Subtarget *Subtarget,
9882 SelectionDAG &DAG) {
9883 switch (VT.SimpleTy) {
9885 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9887 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9889 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9891 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9893 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9895 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9898 llvm_unreachable("Unimplemented!");
9902 /// \brief Helper function to test whether a shuffle mask could be
9903 /// simplified by widening the elements being shuffled.
9905 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9906 /// leaves it in an unspecified state.
9908 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9909 /// shuffle masks. The latter have the special property of a '-2' representing
9910 /// a zero-ed lane of a vector.
9911 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9912 SmallVectorImpl<int> &WidenedMask) {
9913 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9914 // If both elements are undef, its trivial.
9915 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9916 WidenedMask.push_back(SM_SentinelUndef);
9920 // Check for an undef mask and a mask value properly aligned to fit with
9921 // a pair of values. If we find such a case, use the non-undef mask's value.
9922 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9923 WidenedMask.push_back(Mask[i + 1] / 2);
9926 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9927 WidenedMask.push_back(Mask[i] / 2);
9931 // When zeroing, we need to spread the zeroing across both lanes to widen.
9932 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9933 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9934 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9935 WidenedMask.push_back(SM_SentinelZero);
9941 // Finally check if the two mask values are adjacent and aligned with
9943 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9944 WidenedMask.push_back(Mask[i] / 2);
9948 // Otherwise we can't safely widen the elements used in this shuffle.
9951 assert(WidenedMask.size() == Mask.size() / 2 &&
9952 "Incorrect size of mask after widening the elements!");
9957 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9959 /// This routine just extracts two subvectors, shuffles them independently, and
9960 /// then concatenates them back together. This should work effectively with all
9961 /// AVX vector shuffle types.
9962 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9963 SDValue V2, ArrayRef<int> Mask,
9964 SelectionDAG &DAG) {
9965 assert(VT.getSizeInBits() >= 256 &&
9966 "Only for 256-bit or wider vector shuffles!");
9967 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9968 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9970 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9971 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9973 int NumElements = VT.getVectorNumElements();
9974 int SplitNumElements = NumElements / 2;
9975 MVT ScalarVT = VT.getVectorElementType();
9976 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9978 // Rather than splitting build-vectors, just build two narrower build
9979 // vectors. This helps shuffling with splats and zeros.
9980 auto SplitVector = [&](SDValue V) {
9981 while (V.getOpcode() == ISD::BITCAST)
9982 V = V->getOperand(0);
9984 MVT OrigVT = V.getSimpleValueType();
9985 int OrigNumElements = OrigVT.getVectorNumElements();
9986 int OrigSplitNumElements = OrigNumElements / 2;
9987 MVT OrigScalarVT = OrigVT.getVectorElementType();
9988 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9992 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9994 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9995 DAG.getIntPtrConstant(0, DL));
9996 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9997 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
10000 SmallVector<SDValue, 16> LoOps, HiOps;
10001 for (int i = 0; i < OrigSplitNumElements; ++i) {
10002 LoOps.push_back(BV->getOperand(i));
10003 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
10005 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
10006 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
10008 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
10009 DAG.getBitcast(SplitVT, HiV));
10012 SDValue LoV1, HiV1, LoV2, HiV2;
10013 std::tie(LoV1, HiV1) = SplitVector(V1);
10014 std::tie(LoV2, HiV2) = SplitVector(V2);
10016 // Now create two 4-way blends of these half-width vectors.
10017 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
10018 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
10019 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
10020 for (int i = 0; i < SplitNumElements; ++i) {
10021 int M = HalfMask[i];
10022 if (M >= NumElements) {
10023 if (M >= NumElements + SplitNumElements)
10027 V2BlendMask.push_back(M - NumElements);
10028 V1BlendMask.push_back(-1);
10029 BlendMask.push_back(SplitNumElements + i);
10030 } else if (M >= 0) {
10031 if (M >= SplitNumElements)
10035 V2BlendMask.push_back(-1);
10036 V1BlendMask.push_back(M);
10037 BlendMask.push_back(i);
10039 V2BlendMask.push_back(-1);
10040 V1BlendMask.push_back(-1);
10041 BlendMask.push_back(-1);
10045 // Because the lowering happens after all combining takes place, we need to
10046 // manually combine these blend masks as much as possible so that we create
10047 // a minimal number of high-level vector shuffle nodes.
10049 // First try just blending the halves of V1 or V2.
10050 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
10051 return DAG.getUNDEF(SplitVT);
10052 if (!UseLoV2 && !UseHiV2)
10053 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
10054 if (!UseLoV1 && !UseHiV1)
10055 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
10057 SDValue V1Blend, V2Blend;
10058 if (UseLoV1 && UseHiV1) {
10060 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
10062 // We only use half of V1 so map the usage down into the final blend mask.
10063 V1Blend = UseLoV1 ? LoV1 : HiV1;
10064 for (int i = 0; i < SplitNumElements; ++i)
10065 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
10066 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
10068 if (UseLoV2 && UseHiV2) {
10070 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
10072 // We only use half of V2 so map the usage down into the final blend mask.
10073 V2Blend = UseLoV2 ? LoV2 : HiV2;
10074 for (int i = 0; i < SplitNumElements; ++i)
10075 if (BlendMask[i] >= SplitNumElements)
10076 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
10078 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
10080 SDValue Lo = HalfBlend(LoMask);
10081 SDValue Hi = HalfBlend(HiMask);
10082 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
10085 /// \brief Either split a vector in halves or decompose the shuffles and the
10088 /// This is provided as a good fallback for many lowerings of non-single-input
10089 /// shuffles with more than one 128-bit lane. In those cases, we want to select
10090 /// between splitting the shuffle into 128-bit components and stitching those
10091 /// back together vs. extracting the single-input shuffles and blending those
10093 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
10094 SDValue V2, ArrayRef<int> Mask,
10095 SelectionDAG &DAG) {
10096 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
10097 "lower single-input shuffles as it "
10098 "could then recurse on itself.");
10099 int Size = Mask.size();
10101 // If this can be modeled as a broadcast of two elements followed by a blend,
10102 // prefer that lowering. This is especially important because broadcasts can
10103 // often fold with memory operands.
10104 auto DoBothBroadcast = [&] {
10105 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
10108 if (V2BroadcastIdx == -1)
10109 V2BroadcastIdx = M - Size;
10110 else if (M - Size != V2BroadcastIdx)
10112 } else if (M >= 0) {
10113 if (V1BroadcastIdx == -1)
10114 V1BroadcastIdx = M;
10115 else if (M != V1BroadcastIdx)
10120 if (DoBothBroadcast())
10121 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10124 // If the inputs all stem from a single 128-bit lane of each input, then we
10125 // split them rather than blending because the split will decompose to
10126 // unusually few instructions.
10127 int LaneCount = VT.getSizeInBits() / 128;
10128 int LaneSize = Size / LaneCount;
10129 SmallBitVector LaneInputs[2];
10130 LaneInputs[0].resize(LaneCount, false);
10131 LaneInputs[1].resize(LaneCount, false);
10132 for (int i = 0; i < Size; ++i)
10134 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10135 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10136 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10138 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10139 // that the decomposed single-input shuffles don't end up here.
10140 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10143 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10144 /// a permutation and blend of those lanes.
10146 /// This essentially blends the out-of-lane inputs to each lane into the lane
10147 /// from a permuted copy of the vector. This lowering strategy results in four
10148 /// instructions in the worst case for a single-input cross lane shuffle which
10149 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10150 /// of. Special cases for each particular shuffle pattern should be handled
10151 /// prior to trying this lowering.
10152 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10153 SDValue V1, SDValue V2,
10154 ArrayRef<int> Mask,
10155 SelectionDAG &DAG) {
10156 // FIXME: This should probably be generalized for 512-bit vectors as well.
10157 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
10158 int LaneSize = Mask.size() / 2;
10160 // If there are only inputs from one 128-bit lane, splitting will in fact be
10161 // less expensive. The flags track whether the given lane contains an element
10162 // that crosses to another lane.
10163 bool LaneCrossing[2] = {false, false};
10164 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10165 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10166 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10167 if (!LaneCrossing[0] || !LaneCrossing[1])
10168 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10170 if (isSingleInputShuffleMask(Mask)) {
10171 SmallVector<int, 32> FlippedBlendMask;
10172 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10173 FlippedBlendMask.push_back(
10174 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10176 : Mask[i] % LaneSize +
10177 (i / LaneSize) * LaneSize + Size));
10179 // Flip the vector, and blend the results which should now be in-lane. The
10180 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10181 // 5 for the high source. The value 3 selects the high half of source 2 and
10182 // the value 2 selects the low half of source 2. We only use source 2 to
10183 // allow folding it into a memory operand.
10184 unsigned PERMMask = 3 | 2 << 4;
10185 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10186 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
10187 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10190 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10191 // will be handled by the above logic and a blend of the results, much like
10192 // other patterns in AVX.
10193 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10196 /// \brief Handle lowering 2-lane 128-bit shuffles.
10197 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10198 SDValue V2, ArrayRef<int> Mask,
10199 const X86Subtarget *Subtarget,
10200 SelectionDAG &DAG) {
10201 // TODO: If minimizing size and one of the inputs is a zero vector and the
10202 // the zero vector has only one use, we could use a VPERM2X128 to save the
10203 // instruction bytes needed to explicitly generate the zero vector.
10205 // Blends are faster and handle all the non-lane-crossing cases.
10206 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10210 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10211 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10213 // If either input operand is a zero vector, use VPERM2X128 because its mask
10214 // allows us to replace the zero input with an implicit zero.
10215 if (!IsV1Zero && !IsV2Zero) {
10216 // Check for patterns which can be matched with a single insert of a 128-bit
10218 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10219 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10220 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10221 VT.getVectorNumElements() / 2);
10222 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10223 DAG.getIntPtrConstant(0, DL));
10224 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10225 OnlyUsesV1 ? V1 : V2,
10226 DAG.getIntPtrConstant(0, DL));
10227 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10231 // Otherwise form a 128-bit permutation. After accounting for undefs,
10232 // convert the 64-bit shuffle mask selection values into 128-bit
10233 // selection bits by dividing the indexes by 2 and shifting into positions
10234 // defined by a vperm2*128 instruction's immediate control byte.
10236 // The immediate permute control byte looks like this:
10237 // [1:0] - select 128 bits from sources for low half of destination
10239 // [3] - zero low half of destination
10240 // [5:4] - select 128 bits from sources for high half of destination
10242 // [7] - zero high half of destination
10244 int MaskLO = Mask[0];
10245 if (MaskLO == SM_SentinelUndef)
10246 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10248 int MaskHI = Mask[2];
10249 if (MaskHI == SM_SentinelUndef)
10250 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10252 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10254 // If either input is a zero vector, replace it with an undef input.
10255 // Shuffle mask values < 4 are selecting elements of V1.
10256 // Shuffle mask values >= 4 are selecting elements of V2.
10257 // Adjust each half of the permute mask by clearing the half that was
10258 // selecting the zero vector and setting the zero mask bit.
10260 V1 = DAG.getUNDEF(VT);
10262 PermMask = (PermMask & 0xf0) | 0x08;
10264 PermMask = (PermMask & 0x0f) | 0x80;
10267 V2 = DAG.getUNDEF(VT);
10269 PermMask = (PermMask & 0xf0) | 0x08;
10271 PermMask = (PermMask & 0x0f) | 0x80;
10274 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10275 DAG.getConstant(PermMask, DL, MVT::i8));
10278 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10279 /// shuffling each lane.
10281 /// This will only succeed when the result of fixing the 128-bit lanes results
10282 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10283 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10284 /// the lane crosses early and then use simpler shuffles within each lane.
10286 /// FIXME: It might be worthwhile at some point to support this without
10287 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10288 /// in x86 only floating point has interesting non-repeating shuffles, and even
10289 /// those are still *marginally* more expensive.
10290 static SDValue lowerVectorShuffleByMerging128BitLanes(
10291 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10292 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10293 assert(!isSingleInputShuffleMask(Mask) &&
10294 "This is only useful with multiple inputs.");
10296 int Size = Mask.size();
10297 int LaneSize = 128 / VT.getScalarSizeInBits();
10298 int NumLanes = Size / LaneSize;
10299 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10301 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10302 // check whether the in-128-bit lane shuffles share a repeating pattern.
10303 SmallVector<int, 4> Lanes;
10304 Lanes.resize(NumLanes, -1);
10305 SmallVector<int, 4> InLaneMask;
10306 InLaneMask.resize(LaneSize, -1);
10307 for (int i = 0; i < Size; ++i) {
10311 int j = i / LaneSize;
10313 if (Lanes[j] < 0) {
10314 // First entry we've seen for this lane.
10315 Lanes[j] = Mask[i] / LaneSize;
10316 } else if (Lanes[j] != Mask[i] / LaneSize) {
10317 // This doesn't match the lane selected previously!
10321 // Check that within each lane we have a consistent shuffle mask.
10322 int k = i % LaneSize;
10323 if (InLaneMask[k] < 0) {
10324 InLaneMask[k] = Mask[i] % LaneSize;
10325 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10326 // This doesn't fit a repeating in-lane mask.
10331 // First shuffle the lanes into place.
10332 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10333 VT.getSizeInBits() / 64);
10334 SmallVector<int, 8> LaneMask;
10335 LaneMask.resize(NumLanes * 2, -1);
10336 for (int i = 0; i < NumLanes; ++i)
10337 if (Lanes[i] >= 0) {
10338 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10339 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10342 V1 = DAG.getBitcast(LaneVT, V1);
10343 V2 = DAG.getBitcast(LaneVT, V2);
10344 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10346 // Cast it back to the type we actually want.
10347 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10349 // Now do a simple shuffle that isn't lane crossing.
10350 SmallVector<int, 8> NewMask;
10351 NewMask.resize(Size, -1);
10352 for (int i = 0; i < Size; ++i)
10354 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10355 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10356 "Must not introduce lane crosses at this point!");
10358 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10361 /// Lower shuffles where an entire half of a 256-bit vector is UNDEF.
10362 /// This allows for fast cases such as subvector extraction/insertion
10363 /// or shuffling smaller vector types which can lower more efficiently.
10364 static SDValue lowerVectorShuffleWithUndefHalf(SDLoc DL, MVT VT, SDValue V1,
10365 SDValue V2, ArrayRef<int> Mask,
10366 const X86Subtarget *Subtarget,
10367 SelectionDAG &DAG) {
10368 assert(VT.getSizeInBits() == 256 && "Expected 256-bit vector");
10370 unsigned NumElts = VT.getVectorNumElements();
10371 unsigned HalfNumElts = NumElts / 2;
10372 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(), HalfNumElts);
10374 bool UndefLower = isUndefInRange(Mask, 0, HalfNumElts);
10375 bool UndefUpper = isUndefInRange(Mask, HalfNumElts, HalfNumElts);
10376 if (!UndefLower && !UndefUpper)
10379 // Upper half is undef and lower half is whole upper subvector.
10380 // e.g. vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
10382 isSequentialOrUndefInRange(Mask, 0, HalfNumElts, HalfNumElts)) {
10383 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1,
10384 DAG.getIntPtrConstant(HalfNumElts, DL));
10385 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi,
10386 DAG.getIntPtrConstant(0, DL));
10389 // Lower half is undef and upper half is whole lower subvector.
10390 // e.g. vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
10392 isSequentialOrUndefInRange(Mask, HalfNumElts, HalfNumElts, 0)) {
10393 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1,
10394 DAG.getIntPtrConstant(0, DL));
10395 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi,
10396 DAG.getIntPtrConstant(HalfNumElts, DL));
10399 // AVX2 supports efficient immediate 64-bit element cross-lane shuffles.
10400 if (UndefLower && Subtarget->hasAVX2() &&
10401 (VT == MVT::v4f64 || VT == MVT::v4i64))
10404 // If the shuffle only uses the lower halves of the input operands,
10405 // then extract them and perform the 'half' shuffle at half width.
10406 // e.g. vector_shuffle <X, X, X, X, u, u, u, u> or <X, X, u, u>
10407 int HalfIdx1 = -1, HalfIdx2 = -1;
10408 SmallVector<int, 8> HalfMask;
10409 unsigned Offset = UndefLower ? HalfNumElts : 0;
10410 for (unsigned i = 0; i != HalfNumElts; ++i) {
10411 int M = Mask[i + Offset];
10413 HalfMask.push_back(M);
10417 // Determine which of the 4 half vectors this element is from.
10418 // i.e. 0 = Lower V1, 1 = Upper V1, 2 = Lower V2, 3 = Upper V2.
10419 int HalfIdx = M / HalfNumElts;
10421 // Only shuffle using the lower halves of the inputs.
10422 // TODO: Investigate usefulness of shuffling with upper halves.
10423 if (HalfIdx != 0 && HalfIdx != 2)
10426 // Determine the element index into its half vector source.
10427 int HalfElt = M % HalfNumElts;
10429 // We can shuffle with up to 2 half vectors, set the new 'half'
10430 // shuffle mask accordingly.
10431 if (-1 == HalfIdx1 || HalfIdx1 == HalfIdx) {
10432 HalfMask.push_back(HalfElt);
10433 HalfIdx1 = HalfIdx;
10436 if (-1 == HalfIdx2 || HalfIdx2 == HalfIdx) {
10437 HalfMask.push_back(HalfElt + HalfNumElts);
10438 HalfIdx2 = HalfIdx;
10442 // Too many half vectors referenced.
10445 assert(HalfMask.size() == HalfNumElts && "Unexpected shuffle mask length");
10447 auto GetHalfVector = [&](int HalfIdx) {
10449 return DAG.getUNDEF(HalfVT);
10450 SDValue V = (HalfIdx < 2 ? V1 : V2);
10451 HalfIdx = (HalfIdx % 2) * HalfNumElts;
10452 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V,
10453 DAG.getIntPtrConstant(HalfIdx, DL));
10456 SDValue Half1 = GetHalfVector(HalfIdx1);
10457 SDValue Half2 = GetHalfVector(HalfIdx2);
10458 SDValue V = DAG.getVectorShuffle(HalfVT, DL, Half1, Half2, HalfMask);
10459 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V,
10460 DAG.getIntPtrConstant(Offset, DL));
10463 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10466 /// This returns true if the elements from a particular input are already in the
10467 /// slot required by the given mask and require no permutation.
10468 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10469 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10470 int Size = Mask.size();
10471 for (int i = 0; i < Size; ++i)
10472 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10478 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10479 ArrayRef<int> Mask, SDValue V1,
10480 SDValue V2, SelectionDAG &DAG) {
10482 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10483 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10484 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10485 int NumElts = VT.getVectorNumElements();
10486 bool ShufpdMask = true;
10487 bool CommutableMask = true;
10488 unsigned Immediate = 0;
10489 for (int i = 0; i < NumElts; ++i) {
10492 int Val = (i & 6) + NumElts * (i & 1);
10493 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10494 if (Mask[i] < Val || Mask[i] > Val + 1)
10495 ShufpdMask = false;
10496 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10497 CommutableMask = false;
10498 Immediate |= (Mask[i] % 2) << i;
10501 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10502 DAG.getConstant(Immediate, DL, MVT::i8));
10503 if (CommutableMask)
10504 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10505 DAG.getConstant(Immediate, DL, MVT::i8));
10509 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10511 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10512 /// isn't available.
10513 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10514 const X86Subtarget *Subtarget,
10515 SelectionDAG &DAG) {
10517 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10518 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10519 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10520 ArrayRef<int> Mask = SVOp->getMask();
10521 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10523 SmallVector<int, 4> WidenedMask;
10524 if (canWidenShuffleElements(Mask, WidenedMask))
10525 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10528 if (isSingleInputShuffleMask(Mask)) {
10529 // Check for being able to broadcast a single element.
10530 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10531 Mask, Subtarget, DAG))
10534 // Use low duplicate instructions for masks that match their pattern.
10535 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10536 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10538 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10539 // Non-half-crossing single input shuffles can be lowerid with an
10540 // interleaved permutation.
10541 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10542 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10543 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10544 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10547 // With AVX2 we have direct support for this permutation.
10548 if (Subtarget->hasAVX2())
10549 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10550 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10552 // Otherwise, fall back.
10553 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10557 // Use dedicated unpack instructions for masks that match their pattern.
10559 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10562 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10566 // Check if the blend happens to exactly fit that of SHUFPD.
10568 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10571 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10572 // shuffle. However, if we have AVX2 and either inputs are already in place,
10573 // we will be able to shuffle even across lanes the other input in a single
10574 // instruction so skip this pattern.
10575 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10576 isShuffleMaskInputInPlace(1, Mask))))
10577 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10578 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10581 // If we have AVX2 then we always want to lower with a blend because an v4 we
10582 // can fully permute the elements.
10583 if (Subtarget->hasAVX2())
10584 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10587 // Otherwise fall back on generic lowering.
10588 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10591 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10593 /// This routine is only called when we have AVX2 and thus a reasonable
10594 /// instruction set for v4i64 shuffling..
10595 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10596 const X86Subtarget *Subtarget,
10597 SelectionDAG &DAG) {
10599 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10600 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10601 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10602 ArrayRef<int> Mask = SVOp->getMask();
10603 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10604 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10606 SmallVector<int, 4> WidenedMask;
10607 if (canWidenShuffleElements(Mask, WidenedMask))
10608 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10611 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10615 // Check for being able to broadcast a single element.
10616 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10617 Mask, Subtarget, DAG))
10620 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10621 // use lower latency instructions that will operate on both 128-bit lanes.
10622 SmallVector<int, 2> RepeatedMask;
10623 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10624 if (isSingleInputShuffleMask(Mask)) {
10625 int PSHUFDMask[] = {-1, -1, -1, -1};
10626 for (int i = 0; i < 2; ++i)
10627 if (RepeatedMask[i] >= 0) {
10628 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10629 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10631 return DAG.getBitcast(
10633 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10634 DAG.getBitcast(MVT::v8i32, V1),
10635 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10639 // AVX2 provides a direct instruction for permuting a single input across
10641 if (isSingleInputShuffleMask(Mask))
10642 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10643 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10645 // Try to use shift instructions.
10646 if (SDValue Shift =
10647 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10650 // Use dedicated unpack instructions for masks that match their pattern.
10652 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10655 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10656 // shuffle. However, if we have AVX2 and either inputs are already in place,
10657 // we will be able to shuffle even across lanes the other input in a single
10658 // instruction so skip this pattern.
10659 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10660 isShuffleMaskInputInPlace(1, Mask))))
10661 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10662 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10665 // Otherwise fall back on generic blend lowering.
10666 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10670 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10672 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10673 /// isn't available.
10674 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10675 const X86Subtarget *Subtarget,
10676 SelectionDAG &DAG) {
10678 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10679 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10680 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10681 ArrayRef<int> Mask = SVOp->getMask();
10682 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10684 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10688 // Check for being able to broadcast a single element.
10689 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10690 Mask, Subtarget, DAG))
10693 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10694 // options to efficiently lower the shuffle.
10695 SmallVector<int, 4> RepeatedMask;
10696 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10697 assert(RepeatedMask.size() == 4 &&
10698 "Repeated masks must be half the mask width!");
10700 // Use even/odd duplicate instructions for masks that match their pattern.
10701 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10702 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10703 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10704 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10706 if (isSingleInputShuffleMask(Mask))
10707 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10708 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10710 // Use dedicated unpack instructions for masks that match their pattern.
10712 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10715 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10716 // have already handled any direct blends. We also need to squash the
10717 // repeated mask into a simulated v4f32 mask.
10718 for (int i = 0; i < 4; ++i)
10719 if (RepeatedMask[i] >= 8)
10720 RepeatedMask[i] -= 4;
10721 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10724 // If we have a single input shuffle with different shuffle patterns in the
10725 // two 128-bit lanes use the variable mask to VPERMILPS.
10726 if (isSingleInputShuffleMask(Mask)) {
10727 SDValue VPermMask[8];
10728 for (int i = 0; i < 8; ++i)
10729 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10730 : DAG.getConstant(Mask[i], DL, MVT::i32);
10731 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10732 return DAG.getNode(
10733 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10734 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10736 if (Subtarget->hasAVX2())
10737 return DAG.getNode(
10738 X86ISD::VPERMV, DL, MVT::v8f32,
10739 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10741 // Otherwise, fall back.
10742 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10746 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10748 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10749 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10752 // If we have AVX2 then we always want to lower with a blend because at v8 we
10753 // can fully permute the elements.
10754 if (Subtarget->hasAVX2())
10755 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10758 // Otherwise fall back on generic lowering.
10759 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10762 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10764 /// This routine is only called when we have AVX2 and thus a reasonable
10765 /// instruction set for v8i32 shuffling..
10766 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10767 const X86Subtarget *Subtarget,
10768 SelectionDAG &DAG) {
10770 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10771 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10772 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10773 ArrayRef<int> Mask = SVOp->getMask();
10774 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10775 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10777 // Whenever we can lower this as a zext, that instruction is strictly faster
10778 // than any alternative. It also allows us to fold memory operands into the
10779 // shuffle in many cases.
10780 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10781 Mask, Subtarget, DAG))
10784 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10788 // Check for being able to broadcast a single element.
10789 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10790 Mask, Subtarget, DAG))
10793 // If the shuffle mask is repeated in each 128-bit lane we can use more
10794 // efficient instructions that mirror the shuffles across the two 128-bit
10796 SmallVector<int, 4> RepeatedMask;
10797 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10798 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10799 if (isSingleInputShuffleMask(Mask))
10800 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10801 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10803 // Use dedicated unpack instructions for masks that match their pattern.
10805 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10809 // Try to use shift instructions.
10810 if (SDValue Shift =
10811 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10814 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10815 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10818 // If the shuffle patterns aren't repeated but it is a single input, directly
10819 // generate a cross-lane VPERMD instruction.
10820 if (isSingleInputShuffleMask(Mask)) {
10821 SDValue VPermMask[8];
10822 for (int i = 0; i < 8; ++i)
10823 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10824 : DAG.getConstant(Mask[i], DL, MVT::i32);
10825 return DAG.getNode(
10826 X86ISD::VPERMV, DL, MVT::v8i32,
10827 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10830 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10832 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10833 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10836 // Otherwise fall back on generic blend lowering.
10837 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10841 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10843 /// This routine is only called when we have AVX2 and thus a reasonable
10844 /// instruction set for v16i16 shuffling..
10845 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10846 const X86Subtarget *Subtarget,
10847 SelectionDAG &DAG) {
10849 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10850 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10851 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10852 ArrayRef<int> Mask = SVOp->getMask();
10853 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10854 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10856 // Whenever we can lower this as a zext, that instruction is strictly faster
10857 // than any alternative. It also allows us to fold memory operands into the
10858 // shuffle in many cases.
10859 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10860 Mask, Subtarget, DAG))
10863 // Check for being able to broadcast a single element.
10864 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10865 Mask, Subtarget, DAG))
10868 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10872 // Use dedicated unpack instructions for masks that match their pattern.
10874 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10877 // Try to use shift instructions.
10878 if (SDValue Shift =
10879 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10882 // Try to use byte rotation instructions.
10883 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10884 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10887 if (isSingleInputShuffleMask(Mask)) {
10888 // There are no generalized cross-lane shuffle operations available on i16
10890 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10891 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10894 SmallVector<int, 8> RepeatedMask;
10895 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10896 // As this is a single-input shuffle, the repeated mask should be
10897 // a strictly valid v8i16 mask that we can pass through to the v8i16
10898 // lowering to handle even the v16 case.
10899 return lowerV8I16GeneralSingleInputVectorShuffle(
10900 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10903 SDValue PSHUFBMask[32];
10904 for (int i = 0; i < 16; ++i) {
10905 if (Mask[i] == -1) {
10906 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10910 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10911 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10912 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10913 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10915 return DAG.getBitcast(MVT::v16i16,
10916 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10917 DAG.getBitcast(MVT::v32i8, V1),
10918 DAG.getNode(ISD::BUILD_VECTOR, DL,
10919 MVT::v32i8, PSHUFBMask)));
10922 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10924 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10925 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10928 // Otherwise fall back on generic lowering.
10929 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10932 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10934 /// This routine is only called when we have AVX2 and thus a reasonable
10935 /// instruction set for v32i8 shuffling..
10936 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10937 const X86Subtarget *Subtarget,
10938 SelectionDAG &DAG) {
10940 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10941 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10942 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10943 ArrayRef<int> Mask = SVOp->getMask();
10944 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10945 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10947 // Whenever we can lower this as a zext, that instruction is strictly faster
10948 // than any alternative. It also allows us to fold memory operands into the
10949 // shuffle in many cases.
10950 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10951 Mask, Subtarget, DAG))
10954 // Check for being able to broadcast a single element.
10955 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10956 Mask, Subtarget, DAG))
10959 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10963 // Use dedicated unpack instructions for masks that match their pattern.
10965 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10968 // Try to use shift instructions.
10969 if (SDValue Shift =
10970 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10973 // Try to use byte rotation instructions.
10974 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10975 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10978 if (isSingleInputShuffleMask(Mask)) {
10979 // There are no generalized cross-lane shuffle operations available on i8
10981 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10982 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10985 SDValue PSHUFBMask[32];
10986 for (int i = 0; i < 32; ++i)
10989 ? DAG.getUNDEF(MVT::i8)
10990 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10993 return DAG.getNode(
10994 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10995 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10998 // Try to simplify this by merging 128-bit lanes to enable a lane-based
11000 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
11001 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
11004 // Otherwise fall back on generic lowering.
11005 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
11008 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
11010 /// This routine either breaks down the specific type of a 256-bit x86 vector
11011 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
11012 /// together based on the available instructions.
11013 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11014 MVT VT, const X86Subtarget *Subtarget,
11015 SelectionDAG &DAG) {
11017 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11018 ArrayRef<int> Mask = SVOp->getMask();
11020 // If we have a single input to the zero element, insert that into V1 if we
11021 // can do so cheaply.
11022 int NumElts = VT.getVectorNumElements();
11023 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
11024 return M >= NumElts;
11027 if (NumV2Elements == 1 && Mask[0] >= NumElts)
11028 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
11029 DL, VT, V1, V2, Mask, Subtarget, DAG))
11032 // Handle special cases where the lower or upper half is UNDEF.
11034 lowerVectorShuffleWithUndefHalf(DL, VT, V1, V2, Mask, Subtarget, DAG))
11037 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
11038 // can check for those subtargets here and avoid much of the subtarget
11039 // querying in the per-vector-type lowering routines. With AVX1 we have
11040 // essentially *zero* ability to manipulate a 256-bit vector with integer
11041 // types. Since we'll use floating point types there eventually, just
11042 // immediately cast everything to a float and operate entirely in that domain.
11043 if (VT.isInteger() && !Subtarget->hasAVX2()) {
11044 int ElementBits = VT.getScalarSizeInBits();
11045 if (ElementBits < 32)
11046 // No floating point type available, decompose into 128-bit vectors.
11047 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11049 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
11050 VT.getVectorNumElements());
11051 V1 = DAG.getBitcast(FpVT, V1);
11052 V2 = DAG.getBitcast(FpVT, V2);
11053 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
11056 switch (VT.SimpleTy) {
11058 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11060 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11062 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11064 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11066 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11068 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11071 llvm_unreachable("Not a valid 256-bit x86 vector type!");
11075 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
11076 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
11077 ArrayRef<int> Mask,
11078 SDValue V1, SDValue V2,
11079 SelectionDAG &DAG) {
11080 assert(VT.getScalarSizeInBits() == 64 &&
11081 "Unexpected element type size for 128bit shuffle.");
11083 // To handle 256 bit vector requires VLX and most probably
11084 // function lowerV2X128VectorShuffle() is better solution.
11085 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
11087 SmallVector<int, 4> WidenedMask;
11088 if (!canWidenShuffleElements(Mask, WidenedMask))
11091 // Form a 128-bit permutation.
11092 // Convert the 64-bit shuffle mask selection values into 128-bit selection
11093 // bits defined by a vshuf64x2 instruction's immediate control byte.
11094 unsigned PermMask = 0, Imm = 0;
11095 unsigned ControlBitsNum = WidenedMask.size() / 2;
11097 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
11098 if (WidenedMask[i] == SM_SentinelZero)
11101 // Use first element in place of undef mask.
11102 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
11103 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
11106 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
11107 DAG.getConstant(PermMask, DL, MVT::i8));
11110 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
11111 ArrayRef<int> Mask, SDValue V1,
11112 SDValue V2, SelectionDAG &DAG) {
11114 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
11116 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
11117 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
11119 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
11120 if (isSingleInputShuffleMask(Mask))
11121 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
11123 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
11126 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
11127 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11128 const X86Subtarget *Subtarget,
11129 SelectionDAG &DAG) {
11131 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
11132 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
11133 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11134 ArrayRef<int> Mask = SVOp->getMask();
11135 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
11137 if (SDValue Shuf128 =
11138 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
11141 if (SDValue Unpck =
11142 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
11145 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
11148 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
11149 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11150 const X86Subtarget *Subtarget,
11151 SelectionDAG &DAG) {
11153 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
11154 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
11155 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11156 ArrayRef<int> Mask = SVOp->getMask();
11157 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11159 if (SDValue Unpck =
11160 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
11163 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
11166 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
11167 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11168 const X86Subtarget *Subtarget,
11169 SelectionDAG &DAG) {
11171 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
11172 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
11173 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11174 ArrayRef<int> Mask = SVOp->getMask();
11175 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
11177 if (SDValue Shuf128 =
11178 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
11181 if (SDValue Unpck =
11182 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
11185 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
11188 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
11189 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11190 const X86Subtarget *Subtarget,
11191 SelectionDAG &DAG) {
11193 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11194 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11195 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11196 ArrayRef<int> Mask = SVOp->getMask();
11197 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11199 if (SDValue Unpck =
11200 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
11203 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
11206 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
11207 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11208 const X86Subtarget *Subtarget,
11209 SelectionDAG &DAG) {
11211 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11212 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11213 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11214 ArrayRef<int> Mask = SVOp->getMask();
11215 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
11216 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
11218 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
11221 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
11222 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11223 const X86Subtarget *Subtarget,
11224 SelectionDAG &DAG) {
11226 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11227 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11228 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11229 ArrayRef<int> Mask = SVOp->getMask();
11230 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
11231 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
11233 // FIXME: Implement direct support for this type!
11234 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
11237 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
11239 /// This routine either breaks down the specific type of a 512-bit x86 vector
11240 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
11241 /// together based on the available instructions.
11242 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11243 MVT VT, const X86Subtarget *Subtarget,
11244 SelectionDAG &DAG) {
11246 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11247 ArrayRef<int> Mask = SVOp->getMask();
11248 assert(Subtarget->hasAVX512() &&
11249 "Cannot lower 512-bit vectors w/ basic ISA!");
11251 // Check for being able to broadcast a single element.
11252 if (SDValue Broadcast =
11253 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
11256 // Dispatch to each element type for lowering. If we don't have supprot for
11257 // specific element type shuffles at 512 bits, immediately split them and
11258 // lower them. Each lowering routine of a given type is allowed to assume that
11259 // the requisite ISA extensions for that element type are available.
11260 switch (VT.SimpleTy) {
11262 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11264 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11266 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11268 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11270 if (Subtarget->hasBWI())
11271 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11274 if (Subtarget->hasBWI())
11275 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11279 llvm_unreachable("Not a valid 512-bit x86 vector type!");
11282 // Otherwise fall back on splitting.
11283 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11286 // Lower vXi1 vector shuffles.
11287 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
11288 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
11289 // vector, shuffle and then truncate it back.
11290 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11291 MVT VT, const X86Subtarget *Subtarget,
11292 SelectionDAG &DAG) {
11294 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11295 ArrayRef<int> Mask = SVOp->getMask();
11296 assert(Subtarget->hasAVX512() &&
11297 "Cannot lower 512-bit vectors w/o basic ISA!");
11299 switch (VT.SimpleTy) {
11301 llvm_unreachable("Expected a vector of i1 elements");
11303 ExtVT = MVT::v2i64;
11306 ExtVT = MVT::v4i32;
11309 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11312 ExtVT = MVT::v16i32;
11315 ExtVT = MVT::v32i16;
11318 ExtVT = MVT::v64i8;
11322 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11323 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11324 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11325 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11327 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11330 V2 = DAG.getUNDEF(ExtVT);
11331 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11332 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11333 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11334 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11336 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11337 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11338 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11340 /// \brief Top-level lowering for x86 vector shuffles.
11342 /// This handles decomposition, canonicalization, and lowering of all x86
11343 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11344 /// above in helper routines. The canonicalization attempts to widen shuffles
11345 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11346 /// s.t. only one of the two inputs needs to be tested, etc.
11347 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11348 SelectionDAG &DAG) {
11349 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11350 ArrayRef<int> Mask = SVOp->getMask();
11351 SDValue V1 = Op.getOperand(0);
11352 SDValue V2 = Op.getOperand(1);
11353 MVT VT = Op.getSimpleValueType();
11354 int NumElements = VT.getVectorNumElements();
11356 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11358 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11359 "Can't lower MMX shuffles");
11361 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11362 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11363 if (V1IsUndef && V2IsUndef)
11364 return DAG.getUNDEF(VT);
11366 // When we create a shuffle node we put the UNDEF node to second operand,
11367 // but in some cases the first operand may be transformed to UNDEF.
11368 // In this case we should just commute the node.
11370 return DAG.getCommutedVectorShuffle(*SVOp);
11372 // Check for non-undef masks pointing at an undef vector and make the masks
11373 // undef as well. This makes it easier to match the shuffle based solely on
11377 if (M >= NumElements) {
11378 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11379 for (int &M : NewMask)
11380 if (M >= NumElements)
11382 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11385 // We actually see shuffles that are entirely re-arrangements of a set of
11386 // zero inputs. This mostly happens while decomposing complex shuffles into
11387 // simple ones. Directly lower these as a buildvector of zeros.
11388 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11389 if (Zeroable.all())
11390 return getZeroVector(VT, Subtarget, DAG, dl);
11392 // Try to collapse shuffles into using a vector type with fewer elements but
11393 // wider element types. We cap this to not form integers or floating point
11394 // elements wider than 64 bits, but it might be interesting to form i128
11395 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11396 SmallVector<int, 16> WidenedMask;
11397 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11398 canWidenShuffleElements(Mask, WidenedMask)) {
11399 MVT NewEltVT = VT.isFloatingPoint()
11400 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11401 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11402 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11403 // Make sure that the new vector type is legal. For example, v2f64 isn't
11405 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11406 V1 = DAG.getBitcast(NewVT, V1);
11407 V2 = DAG.getBitcast(NewVT, V2);
11408 return DAG.getBitcast(
11409 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11413 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11414 for (int M : SVOp->getMask())
11416 ++NumUndefElements;
11417 else if (M < NumElements)
11422 // Commute the shuffle as needed such that more elements come from V1 than
11423 // V2. This allows us to match the shuffle pattern strictly on how many
11424 // elements come from V1 without handling the symmetric cases.
11425 if (NumV2Elements > NumV1Elements)
11426 return DAG.getCommutedVectorShuffle(*SVOp);
11428 // When the number of V1 and V2 elements are the same, try to minimize the
11429 // number of uses of V2 in the low half of the vector. When that is tied,
11430 // ensure that the sum of indices for V1 is equal to or lower than the sum
11431 // indices for V2. When those are equal, try to ensure that the number of odd
11432 // indices for V1 is lower than the number of odd indices for V2.
11433 if (NumV1Elements == NumV2Elements) {
11434 int LowV1Elements = 0, LowV2Elements = 0;
11435 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11436 if (M >= NumElements)
11440 if (LowV2Elements > LowV1Elements) {
11441 return DAG.getCommutedVectorShuffle(*SVOp);
11442 } else if (LowV2Elements == LowV1Elements) {
11443 int SumV1Indices = 0, SumV2Indices = 0;
11444 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11445 if (SVOp->getMask()[i] >= NumElements)
11447 else if (SVOp->getMask()[i] >= 0)
11449 if (SumV2Indices < SumV1Indices) {
11450 return DAG.getCommutedVectorShuffle(*SVOp);
11451 } else if (SumV2Indices == SumV1Indices) {
11452 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11453 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11454 if (SVOp->getMask()[i] >= NumElements)
11455 NumV2OddIndices += i % 2;
11456 else if (SVOp->getMask()[i] >= 0)
11457 NumV1OddIndices += i % 2;
11458 if (NumV2OddIndices < NumV1OddIndices)
11459 return DAG.getCommutedVectorShuffle(*SVOp);
11464 // For each vector width, delegate to a specialized lowering routine.
11465 if (VT.is128BitVector())
11466 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11468 if (VT.is256BitVector())
11469 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11471 if (VT.is512BitVector())
11472 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11475 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11476 llvm_unreachable("Unimplemented!");
11479 // This function assumes its argument is a BUILD_VECTOR of constants or
11480 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11482 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11483 unsigned &MaskValue) {
11485 unsigned NumElems = BuildVector->getNumOperands();
11487 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11488 // We don't handle the >2 lanes case right now.
11489 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11493 unsigned NumElemsInLane = NumElems / NumLanes;
11495 // Blend for v16i16 should be symmetric for the both lanes.
11496 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11497 SDValue EltCond = BuildVector->getOperand(i);
11498 SDValue SndLaneEltCond =
11499 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11501 int Lane1Cond = -1, Lane2Cond = -1;
11502 if (isa<ConstantSDNode>(EltCond))
11503 Lane1Cond = !isNullConstant(EltCond);
11504 if (isa<ConstantSDNode>(SndLaneEltCond))
11505 Lane2Cond = !isNullConstant(SndLaneEltCond);
11507 unsigned LaneMask = 0;
11508 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11509 // Lane1Cond != 0, means we want the first argument.
11510 // Lane1Cond == 0, means we want the second argument.
11511 // The encoding of this argument is 0 for the first argument, 1
11512 // for the second. Therefore, invert the condition.
11513 LaneMask = !Lane1Cond << i;
11514 else if (Lane1Cond < 0)
11515 LaneMask = !Lane2Cond << i;
11519 MaskValue |= LaneMask;
11521 MaskValue |= LaneMask << NumElemsInLane;
11526 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11527 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11528 const X86Subtarget *Subtarget,
11529 SelectionDAG &DAG) {
11530 SDValue Cond = Op.getOperand(0);
11531 SDValue LHS = Op.getOperand(1);
11532 SDValue RHS = Op.getOperand(2);
11534 MVT VT = Op.getSimpleValueType();
11536 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11538 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11540 // Only non-legal VSELECTs reach this lowering, convert those into generic
11541 // shuffles and re-use the shuffle lowering path for blends.
11542 SmallVector<int, 32> Mask;
11543 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11544 SDValue CondElt = CondBV->getOperand(i);
11546 isa<ConstantSDNode>(CondElt) ? i + (isNullConstant(CondElt) ? Size : 0)
11549 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11552 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11553 // A vselect where all conditions and data are constants can be optimized into
11554 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11555 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11556 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11557 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11560 // Try to lower this to a blend-style vector shuffle. This can handle all
11561 // constant condition cases.
11562 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11565 // Variable blends are only legal from SSE4.1 onward.
11566 if (!Subtarget->hasSSE41())
11569 // Only some types will be legal on some subtargets. If we can emit a legal
11570 // VSELECT-matching blend, return Op, and but if we need to expand, return
11572 switch (Op.getSimpleValueType().SimpleTy) {
11574 // Most of the vector types have blends past SSE4.1.
11578 // The byte blends for AVX vectors were introduced only in AVX2.
11579 if (Subtarget->hasAVX2())
11586 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11587 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11590 // FIXME: We should custom lower this by fixing the condition and using i8
11596 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11597 MVT VT = Op.getSimpleValueType();
11600 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11603 if (VT.getSizeInBits() == 8) {
11604 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11605 Op.getOperand(0), Op.getOperand(1));
11606 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11607 DAG.getValueType(VT));
11608 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11611 if (VT.getSizeInBits() == 16) {
11612 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11613 if (isNullConstant(Op.getOperand(1)))
11614 return DAG.getNode(
11615 ISD::TRUNCATE, dl, MVT::i16,
11616 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11617 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11618 Op.getOperand(1)));
11619 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11620 Op.getOperand(0), Op.getOperand(1));
11621 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11622 DAG.getValueType(VT));
11623 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11626 if (VT == MVT::f32) {
11627 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11628 // the result back to FR32 register. It's only worth matching if the
11629 // result has a single use which is a store or a bitcast to i32. And in
11630 // the case of a store, it's not worth it if the index is a constant 0,
11631 // because a MOVSSmr can be used instead, which is smaller and faster.
11632 if (!Op.hasOneUse())
11634 SDNode *User = *Op.getNode()->use_begin();
11635 if ((User->getOpcode() != ISD::STORE ||
11636 isNullConstant(Op.getOperand(1))) &&
11637 (User->getOpcode() != ISD::BITCAST ||
11638 User->getValueType(0) != MVT::i32))
11640 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11641 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11643 return DAG.getBitcast(MVT::f32, Extract);
11646 if (VT == MVT::i32 || VT == MVT::i64) {
11647 // ExtractPS/pextrq works with constant index.
11648 if (isa<ConstantSDNode>(Op.getOperand(1)))
11654 /// Extract one bit from mask vector, like v16i1 or v8i1.
11655 /// AVX-512 feature.
11657 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11658 SDValue Vec = Op.getOperand(0);
11660 MVT VecVT = Vec.getSimpleValueType();
11661 SDValue Idx = Op.getOperand(1);
11662 MVT EltVT = Op.getSimpleValueType();
11664 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11665 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11666 "Unexpected vector type in ExtractBitFromMaskVector");
11668 // variable index can't be handled in mask registers,
11669 // extend vector to VR512
11670 if (!isa<ConstantSDNode>(Idx)) {
11671 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11672 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11673 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11674 ExtVT.getVectorElementType(), Ext, Idx);
11675 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11678 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11679 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11680 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11681 rc = getRegClassFor(MVT::v16i1);
11682 unsigned MaxSift = rc->getSize()*8 - 1;
11683 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11684 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11685 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11686 DAG.getConstant(MaxSift, dl, MVT::i8));
11687 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11688 DAG.getIntPtrConstant(0, dl));
11692 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11693 SelectionDAG &DAG) const {
11695 SDValue Vec = Op.getOperand(0);
11696 MVT VecVT = Vec.getSimpleValueType();
11697 SDValue Idx = Op.getOperand(1);
11699 if (Op.getSimpleValueType() == MVT::i1)
11700 return ExtractBitFromMaskVector(Op, DAG);
11702 if (!isa<ConstantSDNode>(Idx)) {
11703 if (VecVT.is512BitVector() ||
11704 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11705 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11708 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11709 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11710 MaskEltVT.getSizeInBits());
11712 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11713 auto PtrVT = getPointerTy(DAG.getDataLayout());
11714 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11715 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11716 DAG.getConstant(0, dl, PtrVT));
11717 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11718 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11719 DAG.getConstant(0, dl, PtrVT));
11724 // If this is a 256-bit vector result, first extract the 128-bit vector and
11725 // then extract the element from the 128-bit vector.
11726 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11728 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11729 // Get the 128-bit vector.
11730 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11731 MVT EltVT = VecVT.getVectorElementType();
11733 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11734 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11736 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11737 // this can be done with a mask.
11738 IdxVal &= ElemsPerChunk - 1;
11739 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11740 DAG.getConstant(IdxVal, dl, MVT::i32));
11743 assert(VecVT.is128BitVector() && "Unexpected vector length");
11745 if (Subtarget->hasSSE41())
11746 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11749 MVT VT = Op.getSimpleValueType();
11750 // TODO: handle v16i8.
11751 if (VT.getSizeInBits() == 16) {
11752 SDValue Vec = Op.getOperand(0);
11753 if (isNullConstant(Op.getOperand(1)))
11754 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11755 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11756 DAG.getBitcast(MVT::v4i32, Vec),
11757 Op.getOperand(1)));
11758 // Transform it so it match pextrw which produces a 32-bit result.
11759 MVT EltVT = MVT::i32;
11760 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11761 Op.getOperand(0), Op.getOperand(1));
11762 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11763 DAG.getValueType(VT));
11764 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11767 if (VT.getSizeInBits() == 32) {
11768 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11772 // SHUFPS the element to the lowest double word, then movss.
11773 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11774 MVT VVT = Op.getOperand(0).getSimpleValueType();
11775 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11776 DAG.getUNDEF(VVT), Mask);
11777 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11778 DAG.getIntPtrConstant(0, dl));
11781 if (VT.getSizeInBits() == 64) {
11782 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11783 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11784 // to match extract_elt for f64.
11785 if (isNullConstant(Op.getOperand(1)))
11788 // UNPCKHPD the element to the lowest double word, then movsd.
11789 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11790 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11791 int Mask[2] = { 1, -1 };
11792 MVT VVT = Op.getOperand(0).getSimpleValueType();
11793 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11794 DAG.getUNDEF(VVT), Mask);
11795 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11796 DAG.getIntPtrConstant(0, dl));
11802 /// Insert one bit to mask vector, like v16i1 or v8i1.
11803 /// AVX-512 feature.
11805 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11807 SDValue Vec = Op.getOperand(0);
11808 SDValue Elt = Op.getOperand(1);
11809 SDValue Idx = Op.getOperand(2);
11810 MVT VecVT = Vec.getSimpleValueType();
11812 if (!isa<ConstantSDNode>(Idx)) {
11813 // Non constant index. Extend source and destination,
11814 // insert element and then truncate the result.
11815 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11816 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11817 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11818 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11819 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11820 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11823 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11824 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11826 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11827 DAG.getConstant(IdxVal, dl, MVT::i8));
11828 if (Vec.getOpcode() == ISD::UNDEF)
11830 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11833 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11834 SelectionDAG &DAG) const {
11835 MVT VT = Op.getSimpleValueType();
11836 MVT EltVT = VT.getVectorElementType();
11838 if (EltVT == MVT::i1)
11839 return InsertBitToMaskVector(Op, DAG);
11842 SDValue N0 = Op.getOperand(0);
11843 SDValue N1 = Op.getOperand(1);
11844 SDValue N2 = Op.getOperand(2);
11845 if (!isa<ConstantSDNode>(N2))
11847 auto *N2C = cast<ConstantSDNode>(N2);
11848 unsigned IdxVal = N2C->getZExtValue();
11850 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11851 // into that, and then insert the subvector back into the result.
11852 if (VT.is256BitVector() || VT.is512BitVector()) {
11853 // With a 256-bit vector, we can insert into the zero element efficiently
11854 // using a blend if we have AVX or AVX2 and the right data type.
11855 if (VT.is256BitVector() && IdxVal == 0) {
11856 // TODO: It is worthwhile to cast integer to floating point and back
11857 // and incur a domain crossing penalty if that's what we'll end up
11858 // doing anyway after extracting to a 128-bit vector.
11859 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11860 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11861 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11862 N2 = DAG.getIntPtrConstant(1, dl);
11863 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11867 // Get the desired 128-bit vector chunk.
11868 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11870 // Insert the element into the desired chunk.
11871 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11872 assert(isPowerOf2_32(NumEltsIn128));
11873 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11874 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11876 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11877 DAG.getConstant(IdxIn128, dl, MVT::i32));
11879 // Insert the changed part back into the bigger vector
11880 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11882 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11884 if (Subtarget->hasSSE41()) {
11885 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11887 if (VT == MVT::v8i16) {
11888 Opc = X86ISD::PINSRW;
11890 assert(VT == MVT::v16i8);
11891 Opc = X86ISD::PINSRB;
11894 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11896 if (N1.getValueType() != MVT::i32)
11897 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11898 if (N2.getValueType() != MVT::i32)
11899 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11900 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11903 if (EltVT == MVT::f32) {
11904 // Bits [7:6] of the constant are the source select. This will always be
11905 // zero here. The DAG Combiner may combine an extract_elt index into
11906 // these bits. For example (insert (extract, 3), 2) could be matched by
11907 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11908 // Bits [5:4] of the constant are the destination select. This is the
11909 // value of the incoming immediate.
11910 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11911 // combine either bitwise AND or insert of float 0.0 to set these bits.
11913 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11914 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11915 // If this is an insertion of 32-bits into the low 32-bits of
11916 // a vector, we prefer to generate a blend with immediate rather
11917 // than an insertps. Blends are simpler operations in hardware and so
11918 // will always have equal or better performance than insertps.
11919 // But if optimizing for size and there's a load folding opportunity,
11920 // generate insertps because blendps does not have a 32-bit memory
11922 N2 = DAG.getIntPtrConstant(1, dl);
11923 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11924 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11926 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11927 // Create this as a scalar to vector..
11928 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11929 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11932 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11933 // PINSR* works with constant index.
11938 if (EltVT == MVT::i8)
11941 if (EltVT.getSizeInBits() == 16) {
11942 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11943 // as its second argument.
11944 if (N1.getValueType() != MVT::i32)
11945 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11946 if (N2.getValueType() != MVT::i32)
11947 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11948 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11953 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11955 MVT OpVT = Op.getSimpleValueType();
11957 // If this is a 256-bit vector result, first insert into a 128-bit
11958 // vector and then insert into the 256-bit vector.
11959 if (!OpVT.is128BitVector()) {
11960 // Insert into a 128-bit vector.
11961 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11962 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11963 OpVT.getVectorNumElements() / SizeFactor);
11965 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11967 // Insert the 128-bit vector.
11968 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11971 if (OpVT == MVT::v1i64 &&
11972 Op.getOperand(0).getValueType() == MVT::i64)
11973 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11975 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11976 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11977 return DAG.getBitcast(
11978 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11981 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11982 // a simple subregister reference or explicit instructions to grab
11983 // upper bits of a vector.
11984 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11985 SelectionDAG &DAG) {
11987 SDValue In = Op.getOperand(0);
11988 SDValue Idx = Op.getOperand(1);
11989 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11990 MVT ResVT = Op.getSimpleValueType();
11991 MVT InVT = In.getSimpleValueType();
11993 if (Subtarget->hasFp256()) {
11994 if (ResVT.is128BitVector() &&
11995 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11996 isa<ConstantSDNode>(Idx)) {
11997 return Extract128BitVector(In, IdxVal, DAG, dl);
11999 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12000 isa<ConstantSDNode>(Idx)) {
12001 return Extract256BitVector(In, IdxVal, DAG, dl);
12007 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12008 // simple superregister reference or explicit instructions to insert
12009 // the upper bits of a vector.
12010 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12011 SelectionDAG &DAG) {
12012 if (!Subtarget->hasAVX())
12016 SDValue Vec = Op.getOperand(0);
12017 SDValue SubVec = Op.getOperand(1);
12018 SDValue Idx = Op.getOperand(2);
12020 if (!isa<ConstantSDNode>(Idx))
12023 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12024 MVT OpVT = Op.getSimpleValueType();
12025 MVT SubVecVT = SubVec.getSimpleValueType();
12027 // Fold two 16-byte subvector loads into one 32-byte load:
12028 // (insert_subvector (insert_subvector undef, (load addr), 0),
12029 // (load addr + 16), Elts/2)
12031 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
12032 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
12033 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
12034 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
12035 if (Idx2 && Idx2->getZExtValue() == 0) {
12036 SDValue SubVec2 = Vec.getOperand(1);
12037 // If needed, look through a bitcast to get to the load.
12038 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
12039 SubVec2 = SubVec2.getOperand(0);
12041 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
12043 unsigned Alignment = FirstLd->getAlignment();
12044 unsigned AS = FirstLd->getAddressSpace();
12045 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
12046 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
12047 OpVT, AS, Alignment, &Fast) && Fast) {
12048 SDValue Ops[] = { SubVec2, SubVec };
12049 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
12056 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
12057 SubVecVT.is128BitVector())
12058 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12060 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
12061 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12063 if (OpVT.getVectorElementType() == MVT::i1)
12064 return Insert1BitVector(Op, DAG);
12069 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12070 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12071 // one of the above mentioned nodes. It has to be wrapped because otherwise
12072 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12073 // be used to form addressing mode. These wrapped nodes will be selected
12076 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12077 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12079 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12080 // global base reg.
12081 unsigned char OpFlag = 0;
12082 unsigned WrapperKind = X86ISD::Wrapper;
12083 CodeModel::Model M = DAG.getTarget().getCodeModel();
12085 if (Subtarget->isPICStyleRIPRel() &&
12086 (M == CodeModel::Small || M == CodeModel::Kernel))
12087 WrapperKind = X86ISD::WrapperRIP;
12088 else if (Subtarget->isPICStyleGOT())
12089 OpFlag = X86II::MO_GOTOFF;
12090 else if (Subtarget->isPICStyleStubPIC())
12091 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12093 auto PtrVT = getPointerTy(DAG.getDataLayout());
12094 SDValue Result = DAG.getTargetConstantPool(
12095 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
12097 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12098 // With PIC, the address is actually $g + Offset.
12101 DAG.getNode(ISD::ADD, DL, PtrVT,
12102 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
12108 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12109 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12111 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12112 // global base reg.
12113 unsigned char OpFlag = 0;
12114 unsigned WrapperKind = X86ISD::Wrapper;
12115 CodeModel::Model M = DAG.getTarget().getCodeModel();
12117 if (Subtarget->isPICStyleRIPRel() &&
12118 (M == CodeModel::Small || M == CodeModel::Kernel))
12119 WrapperKind = X86ISD::WrapperRIP;
12120 else if (Subtarget->isPICStyleGOT())
12121 OpFlag = X86II::MO_GOTOFF;
12122 else if (Subtarget->isPICStyleStubPIC())
12123 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12125 auto PtrVT = getPointerTy(DAG.getDataLayout());
12126 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
12128 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12130 // With PIC, the address is actually $g + Offset.
12133 DAG.getNode(ISD::ADD, DL, PtrVT,
12134 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
12140 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12141 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12143 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12144 // global base reg.
12145 unsigned char OpFlag = 0;
12146 unsigned WrapperKind = X86ISD::Wrapper;
12147 CodeModel::Model M = DAG.getTarget().getCodeModel();
12149 if (Subtarget->isPICStyleRIPRel() &&
12150 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12151 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12152 OpFlag = X86II::MO_GOTPCREL;
12153 WrapperKind = X86ISD::WrapperRIP;
12154 } else if (Subtarget->isPICStyleGOT()) {
12155 OpFlag = X86II::MO_GOT;
12156 } else if (Subtarget->isPICStyleStubPIC()) {
12157 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12158 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12159 OpFlag = X86II::MO_DARWIN_NONLAZY;
12162 auto PtrVT = getPointerTy(DAG.getDataLayout());
12163 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
12166 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12168 // With PIC, the address is actually $g + Offset.
12169 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12170 !Subtarget->is64Bit()) {
12172 DAG.getNode(ISD::ADD, DL, PtrVT,
12173 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
12176 // For symbols that require a load from a stub to get the address, emit the
12178 if (isGlobalStubReference(OpFlag))
12179 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
12180 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12181 false, false, false, 0);
12187 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12188 // Create the TargetBlockAddressAddress node.
12189 unsigned char OpFlags =
12190 Subtarget->ClassifyBlockAddressReference();
12191 CodeModel::Model M = DAG.getTarget().getCodeModel();
12192 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12193 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12195 auto PtrVT = getPointerTy(DAG.getDataLayout());
12196 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
12198 if (Subtarget->isPICStyleRIPRel() &&
12199 (M == CodeModel::Small || M == CodeModel::Kernel))
12200 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12202 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12204 // With PIC, the address is actually $g + Offset.
12205 if (isGlobalRelativeToPICBase(OpFlags)) {
12206 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12207 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12214 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12215 int64_t Offset, SelectionDAG &DAG) const {
12216 // Create the TargetGlobalAddress node, folding in the constant
12217 // offset if it is legal.
12218 unsigned char OpFlags =
12219 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12220 CodeModel::Model M = DAG.getTarget().getCodeModel();
12221 auto PtrVT = getPointerTy(DAG.getDataLayout());
12223 if (OpFlags == X86II::MO_NO_FLAG &&
12224 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12225 // A direct static reference to a global.
12226 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
12229 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
12232 if (Subtarget->isPICStyleRIPRel() &&
12233 (M == CodeModel::Small || M == CodeModel::Kernel))
12234 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12236 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12238 // With PIC, the address is actually $g + Offset.
12239 if (isGlobalRelativeToPICBase(OpFlags)) {
12240 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12241 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12244 // For globals that require a load from a stub to get the address, emit the
12246 if (isGlobalStubReference(OpFlags))
12247 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
12248 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12249 false, false, false, 0);
12251 // If there was a non-zero offset that we didn't fold, create an explicit
12252 // addition for it.
12254 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
12255 DAG.getConstant(Offset, dl, PtrVT));
12261 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12262 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12263 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12264 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12268 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12269 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12270 unsigned char OperandFlags, bool LocalDynamic = false) {
12271 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12272 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12274 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12275 GA->getValueType(0),
12279 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12283 SDValue Ops[] = { Chain, TGA, *InFlag };
12284 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12286 SDValue Ops[] = { Chain, TGA };
12287 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12290 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12291 MFI->setAdjustsStack(true);
12292 MFI->setHasCalls(true);
12294 SDValue Flag = Chain.getValue(1);
12295 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12298 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12300 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12303 SDLoc dl(GA); // ? function entry point might be better
12304 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12305 DAG.getNode(X86ISD::GlobalBaseReg,
12306 SDLoc(), PtrVT), InFlag);
12307 InFlag = Chain.getValue(1);
12309 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12312 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12314 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12316 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12317 X86::RAX, X86II::MO_TLSGD);
12320 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12326 // Get the start address of the TLS block for this module.
12327 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12328 .getInfo<X86MachineFunctionInfo>();
12329 MFI->incNumLocalDynamicTLSAccesses();
12333 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12334 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12337 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12338 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12339 InFlag = Chain.getValue(1);
12340 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12341 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12344 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12348 unsigned char OperandFlags = X86II::MO_DTPOFF;
12349 unsigned WrapperKind = X86ISD::Wrapper;
12350 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12351 GA->getValueType(0),
12352 GA->getOffset(), OperandFlags);
12353 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12355 // Add x@dtpoff with the base.
12356 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12359 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12360 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12361 const EVT PtrVT, TLSModel::Model model,
12362 bool is64Bit, bool isPIC) {
12365 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12366 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12367 is64Bit ? 257 : 256));
12369 SDValue ThreadPointer =
12370 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12371 MachinePointerInfo(Ptr), false, false, false, 0);
12373 unsigned char OperandFlags = 0;
12374 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12376 unsigned WrapperKind = X86ISD::Wrapper;
12377 if (model == TLSModel::LocalExec) {
12378 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12379 } else if (model == TLSModel::InitialExec) {
12381 OperandFlags = X86II::MO_GOTTPOFF;
12382 WrapperKind = X86ISD::WrapperRIP;
12384 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12387 llvm_unreachable("Unexpected model");
12390 // emit "addl x@ntpoff,%eax" (local exec)
12391 // or "addl x@indntpoff,%eax" (initial exec)
12392 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12394 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12395 GA->getOffset(), OperandFlags);
12396 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12398 if (model == TLSModel::InitialExec) {
12399 if (isPIC && !is64Bit) {
12400 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12401 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12405 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12406 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12407 false, false, false, 0);
12410 // The address of the thread local variable is the add of the thread
12411 // pointer with the offset of the variable.
12412 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12416 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12418 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12420 // Cygwin uses emutls.
12421 // FIXME: It may be EmulatedTLS-generic also for X86-Android.
12422 if (Subtarget->isTargetWindowsCygwin())
12423 return LowerToTLSEmulatedModel(GA, DAG);
12425 const GlobalValue *GV = GA->getGlobal();
12426 auto PtrVT = getPointerTy(DAG.getDataLayout());
12428 if (Subtarget->isTargetELF()) {
12429 if (DAG.getTarget().Options.EmulatedTLS)
12430 return LowerToTLSEmulatedModel(GA, DAG);
12431 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12433 case TLSModel::GeneralDynamic:
12434 if (Subtarget->is64Bit())
12435 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12436 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12437 case TLSModel::LocalDynamic:
12438 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12439 Subtarget->is64Bit());
12440 case TLSModel::InitialExec:
12441 case TLSModel::LocalExec:
12442 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12443 DAG.getTarget().getRelocationModel() ==
12446 llvm_unreachable("Unknown TLS model.");
12449 if (Subtarget->isTargetDarwin()) {
12450 // Darwin only has one model of TLS. Lower to that.
12451 unsigned char OpFlag = 0;
12452 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12453 X86ISD::WrapperRIP : X86ISD::Wrapper;
12455 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12456 // global base reg.
12457 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12458 !Subtarget->is64Bit();
12460 OpFlag = X86II::MO_TLVP_PIC_BASE;
12462 OpFlag = X86II::MO_TLVP;
12464 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12465 GA->getValueType(0),
12466 GA->getOffset(), OpFlag);
12467 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12469 // With PIC32, the address is actually $g + Offset.
12471 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12472 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12475 // Lowering the machine isd will make sure everything is in the right
12477 SDValue Chain = DAG.getEntryNode();
12478 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12479 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, DL, true), DL);
12480 SDValue Args[] = { Chain, Offset };
12481 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12483 DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, DL, true),
12484 DAG.getIntPtrConstant(0, DL, true), SDValue(), DL);
12486 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12487 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12488 MFI->setAdjustsStack(true);
12490 // And our return value (tls address) is in the standard call return value
12492 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12493 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12496 if (Subtarget->isTargetKnownWindowsMSVC() ||
12497 Subtarget->isTargetWindowsGNU()) {
12498 // Just use the implicit TLS architecture
12499 // Need to generate someting similar to:
12500 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12502 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12503 // mov rcx, qword [rdx+rcx*8]
12504 // mov eax, .tls$:tlsvar
12505 // [rax+rcx] contains the address
12506 // Windows 64bit: gs:0x58
12507 // Windows 32bit: fs:__tls_array
12510 SDValue Chain = DAG.getEntryNode();
12512 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12513 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12514 // use its literal value of 0x2C.
12515 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12516 ? Type::getInt8PtrTy(*DAG.getContext(),
12518 : Type::getInt32PtrTy(*DAG.getContext(),
12521 SDValue TlsArray = Subtarget->is64Bit()
12522 ? DAG.getIntPtrConstant(0x58, dl)
12523 : (Subtarget->isTargetWindowsGNU()
12524 ? DAG.getIntPtrConstant(0x2C, dl)
12525 : DAG.getExternalSymbol("_tls_array", PtrVT));
12527 SDValue ThreadPointer =
12528 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12532 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12533 res = ThreadPointer;
12535 // Load the _tls_index variable
12536 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12537 if (Subtarget->is64Bit())
12538 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12539 MachinePointerInfo(), MVT::i32, false, false,
12542 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12545 auto &DL = DAG.getDataLayout();
12547 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12548 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12550 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12553 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12556 // Get the offset of start of .tls section
12557 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12558 GA->getValueType(0),
12559 GA->getOffset(), X86II::MO_SECREL);
12560 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12562 // The address of the thread local variable is the add of the thread
12563 // pointer with the offset of the variable.
12564 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12567 llvm_unreachable("TLS not implemented for this target.");
12570 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12571 /// and take a 2 x i32 value to shift plus a shift amount.
12572 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12573 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12574 MVT VT = Op.getSimpleValueType();
12575 unsigned VTBits = VT.getSizeInBits();
12577 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12578 SDValue ShOpLo = Op.getOperand(0);
12579 SDValue ShOpHi = Op.getOperand(1);
12580 SDValue ShAmt = Op.getOperand(2);
12581 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12582 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12584 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12585 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12586 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12587 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12588 : DAG.getConstant(0, dl, VT);
12590 SDValue Tmp2, Tmp3;
12591 if (Op.getOpcode() == ISD::SHL_PARTS) {
12592 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12593 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12595 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12596 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12599 // If the shift amount is larger or equal than the width of a part we can't
12600 // rely on the results of shld/shrd. Insert a test and select the appropriate
12601 // values for large shift amounts.
12602 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12603 DAG.getConstant(VTBits, dl, MVT::i8));
12604 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12605 AndNode, DAG.getConstant(0, dl, MVT::i8));
12608 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12609 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12610 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12612 if (Op.getOpcode() == ISD::SHL_PARTS) {
12613 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12614 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12616 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12617 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12620 SDValue Ops[2] = { Lo, Hi };
12621 return DAG.getMergeValues(Ops, dl);
12624 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12625 SelectionDAG &DAG) const {
12626 SDValue Src = Op.getOperand(0);
12627 MVT SrcVT = Src.getSimpleValueType();
12628 MVT VT = Op.getSimpleValueType();
12631 if (SrcVT.isVector()) {
12632 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12633 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12634 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12635 DAG.getUNDEF(SrcVT)));
12637 if (SrcVT.getVectorElementType() == MVT::i1) {
12638 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12639 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12640 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12645 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12646 "Unknown SINT_TO_FP to lower!");
12648 // These are really Legal; return the operand so the caller accepts it as
12650 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12652 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12653 Subtarget->is64Bit()) {
12657 unsigned Size = SrcVT.getSizeInBits()/8;
12658 MachineFunction &MF = DAG.getMachineFunction();
12659 auto PtrVT = getPointerTy(MF.getDataLayout());
12660 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12661 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12662 SDValue Chain = DAG.getStore(
12663 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12664 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12666 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12669 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12671 SelectionDAG &DAG) const {
12675 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12677 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12679 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12681 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12683 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12684 MachineMemOperand *MMO;
12686 int SSFI = FI->getIndex();
12687 MMO = DAG.getMachineFunction().getMachineMemOperand(
12688 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12689 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12691 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12692 StackSlot = StackSlot.getOperand(1);
12694 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12695 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12697 Tys, Ops, SrcVT, MMO);
12700 Chain = Result.getValue(1);
12701 SDValue InFlag = Result.getValue(2);
12703 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12704 // shouldn't be necessary except that RFP cannot be live across
12705 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12706 MachineFunction &MF = DAG.getMachineFunction();
12707 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12708 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12709 auto PtrVT = getPointerTy(MF.getDataLayout());
12710 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12711 Tys = DAG.getVTList(MVT::Other);
12713 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12715 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12716 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12717 MachineMemOperand::MOStore, SSFISize, SSFISize);
12719 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12720 Ops, Op.getValueType(), MMO);
12721 Result = DAG.getLoad(
12722 Op.getValueType(), DL, Chain, StackSlot,
12723 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12724 false, false, false, 0);
12730 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12731 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12732 SelectionDAG &DAG) const {
12733 // This algorithm is not obvious. Here it is what we're trying to output:
12736 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12737 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12739 haddpd %xmm0, %xmm0
12741 pshufd $0x4e, %xmm0, %xmm1
12747 LLVMContext *Context = DAG.getContext();
12749 // Build some magic constants.
12750 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12751 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12752 auto PtrVT = getPointerTy(DAG.getDataLayout());
12753 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12755 SmallVector<Constant*,2> CV1;
12757 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12758 APInt(64, 0x4330000000000000ULL))));
12760 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12761 APInt(64, 0x4530000000000000ULL))));
12762 Constant *C1 = ConstantVector::get(CV1);
12763 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12765 // Load the 64-bit value into an XMM register.
12766 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12769 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12770 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12771 false, false, false, 16);
12773 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12776 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12777 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12778 false, false, false, 16);
12779 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12780 // TODO: Are there any fast-math-flags to propagate here?
12781 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12784 if (Subtarget->hasSSE3()) {
12785 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12786 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12788 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12789 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12791 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12792 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12795 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12796 DAG.getIntPtrConstant(0, dl));
12799 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12800 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12801 SelectionDAG &DAG) const {
12803 // FP constant to bias correct the final result.
12804 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12807 // Load the 32-bit value into an XMM register.
12808 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12811 // Zero out the upper parts of the register.
12812 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12814 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12815 DAG.getBitcast(MVT::v2f64, Load),
12816 DAG.getIntPtrConstant(0, dl));
12818 // Or the load with the bias.
12819 SDValue Or = DAG.getNode(
12820 ISD::OR, dl, MVT::v2i64,
12821 DAG.getBitcast(MVT::v2i64,
12822 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12823 DAG.getBitcast(MVT::v2i64,
12824 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12826 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12827 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12829 // Subtract the bias.
12830 // TODO: Are there any fast-math-flags to propagate here?
12831 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12833 // Handle final rounding.
12834 MVT DestVT = Op.getSimpleValueType();
12836 if (DestVT.bitsLT(MVT::f64))
12837 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12838 DAG.getIntPtrConstant(0, dl));
12839 if (DestVT.bitsGT(MVT::f64))
12840 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12842 // Handle final rounding.
12846 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12847 const X86Subtarget &Subtarget) {
12848 // The algorithm is the following:
12849 // #ifdef __SSE4_1__
12850 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12851 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12852 // (uint4) 0x53000000, 0xaa);
12854 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12855 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12857 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12858 // return (float4) lo + fhi;
12860 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12861 // reassociate the two FADDs, and if we do that, the algorithm fails
12862 // spectacularly (PR24512).
12863 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12864 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12865 // there's also the MachineCombiner reassociations happening on Machine IR.
12866 if (DAG.getTarget().Options.UnsafeFPMath)
12870 SDValue V = Op->getOperand(0);
12871 MVT VecIntVT = V.getSimpleValueType();
12872 bool Is128 = VecIntVT == MVT::v4i32;
12873 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12874 // If we convert to something else than the supported type, e.g., to v4f64,
12876 if (VecFloatVT != Op->getSimpleValueType(0))
12879 unsigned NumElts = VecIntVT.getVectorNumElements();
12880 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12881 "Unsupported custom type");
12882 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12884 // In the #idef/#else code, we have in common:
12885 // - The vector of constants:
12891 // Create the splat vector for 0x4b000000.
12892 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12893 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12894 CstLow, CstLow, CstLow, CstLow};
12895 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12896 makeArrayRef(&CstLowArray[0], NumElts));
12897 // Create the splat vector for 0x53000000.
12898 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12899 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12900 CstHigh, CstHigh, CstHigh, CstHigh};
12901 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12902 makeArrayRef(&CstHighArray[0], NumElts));
12904 // Create the right shift.
12905 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12906 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12907 CstShift, CstShift, CstShift, CstShift};
12908 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12909 makeArrayRef(&CstShiftArray[0], NumElts));
12910 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12913 if (Subtarget.hasSSE41()) {
12914 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12915 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12916 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12917 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12918 // Low will be bitcasted right away, so do not bother bitcasting back to its
12920 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12921 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12922 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12923 // (uint4) 0x53000000, 0xaa);
12924 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12925 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12926 // High will be bitcasted right away, so do not bother bitcasting back to
12927 // its original type.
12928 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12929 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12931 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12932 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12933 CstMask, CstMask, CstMask);
12934 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12935 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12936 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12938 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12939 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12942 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12943 SDValue CstFAdd = DAG.getConstantFP(
12944 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12945 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12946 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12947 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12948 makeArrayRef(&CstFAddArray[0], NumElts));
12950 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12951 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12952 // TODO: Are there any fast-math-flags to propagate here?
12954 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12955 // return (float4) lo + fhi;
12956 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12957 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12960 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12961 SelectionDAG &DAG) const {
12962 SDValue N0 = Op.getOperand(0);
12963 MVT SVT = N0.getSimpleValueType();
12966 switch (SVT.SimpleTy) {
12968 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12973 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12974 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12975 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12979 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12982 assert(Subtarget->hasAVX512());
12983 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12984 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12988 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12989 SelectionDAG &DAG) const {
12990 SDValue N0 = Op.getOperand(0);
12992 auto PtrVT = getPointerTy(DAG.getDataLayout());
12994 if (Op.getSimpleValueType().isVector())
12995 return lowerUINT_TO_FP_vec(Op, DAG);
12997 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12998 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12999 // the optimization here.
13000 if (DAG.SignBitIsZero(N0))
13001 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13003 MVT SrcVT = N0.getSimpleValueType();
13004 MVT DstVT = Op.getSimpleValueType();
13006 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
13007 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
13008 // Conversions from unsigned i32 to f32/f64 are legal,
13009 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
13013 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13014 return LowerUINT_TO_FP_i64(Op, DAG);
13015 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13016 return LowerUINT_TO_FP_i32(Op, DAG);
13017 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13020 // Make a 64-bit buffer, and use it to build an FILD.
13021 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13022 if (SrcVT == MVT::i32) {
13023 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
13024 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
13025 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13026 StackSlot, MachinePointerInfo(),
13028 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
13029 OffsetSlot, MachinePointerInfo(),
13031 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13035 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13036 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13037 StackSlot, MachinePointerInfo(),
13039 // For i64 source, we need to add the appropriate power of 2 if the input
13040 // was negative. This is the same as the optimization in
13041 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13042 // we must be careful to do the computation in x87 extended precision, not
13043 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13044 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13045 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
13046 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
13047 MachineMemOperand::MOLoad, 8, 8);
13049 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13050 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13051 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13054 APInt FF(32, 0x5F800000ULL);
13056 // Check whether the sign bit is set.
13057 SDValue SignSet = DAG.getSetCC(
13058 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
13059 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
13061 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13062 SDValue FudgePtr = DAG.getConstantPool(
13063 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
13065 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13066 SDValue Zero = DAG.getIntPtrConstant(0, dl);
13067 SDValue Four = DAG.getIntPtrConstant(4, dl);
13068 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13070 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
13072 // Load the value out, extending it from f32 to f80.
13073 // FIXME: Avoid the extend by constructing the right constant pool?
13074 SDValue Fudge = DAG.getExtLoad(
13075 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
13076 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
13077 false, false, false, 4);
13078 // Extend everything to 80 bits to force it to be done on x87.
13079 // TODO: Are there any fast-math-flags to propagate here?
13080 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13081 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
13082 DAG.getIntPtrConstant(0, dl));
13085 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
13086 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
13087 // just return an <SDValue(), SDValue()> pair.
13088 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
13089 // to i16, i32 or i64, and we lower it to a legal sequence.
13090 // If lowered to the final integer result we return a <result, SDValue()> pair.
13091 // Otherwise we lower it to a sequence ending with a FIST, return a
13092 // <FIST, StackSlot> pair, and the caller is responsible for loading
13093 // the final integer result from StackSlot.
13094 std::pair<SDValue,SDValue>
13095 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13096 bool IsSigned, bool IsReplace) const {
13099 EVT DstTy = Op.getValueType();
13100 EVT TheVT = Op.getOperand(0).getValueType();
13101 auto PtrVT = getPointerTy(DAG.getDataLayout());
13103 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
13104 // f16 must be promoted before using the lowering in this routine.
13105 // fp128 does not use this lowering.
13106 return std::make_pair(SDValue(), SDValue());
13109 // If using FIST to compute an unsigned i64, we'll need some fixup
13110 // to handle values above the maximum signed i64. A FIST is always
13111 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
13112 bool UnsignedFixup = !IsSigned &&
13113 DstTy == MVT::i64 &&
13114 (!Subtarget->is64Bit() ||
13115 !isScalarFPTypeInSSEReg(TheVT));
13117 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
13118 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
13119 // The low 32 bits of the fist result will have the correct uint32 result.
13120 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13124 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13125 DstTy.getSimpleVT() >= MVT::i16 &&
13126 "Unknown FP_TO_INT to lower!");
13128 // These are really Legal.
13129 if (DstTy == MVT::i32 &&
13130 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13131 return std::make_pair(SDValue(), SDValue());
13132 if (Subtarget->is64Bit() &&
13133 DstTy == MVT::i64 &&
13134 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13135 return std::make_pair(SDValue(), SDValue());
13137 // We lower FP->int64 into FISTP64 followed by a load from a temporary
13139 MachineFunction &MF = DAG.getMachineFunction();
13140 unsigned MemSize = DstTy.getSizeInBits()/8;
13141 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13142 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13145 switch (DstTy.getSimpleVT().SimpleTy) {
13146 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13147 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13148 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13149 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13152 SDValue Chain = DAG.getEntryNode();
13153 SDValue Value = Op.getOperand(0);
13154 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
13156 if (UnsignedFixup) {
13158 // Conversion to unsigned i64 is implemented with a select,
13159 // depending on whether the source value fits in the range
13160 // of a signed i64. Let Thresh be the FP equivalent of
13161 // 0x8000000000000000ULL.
13163 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
13164 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
13165 // Fist-to-mem64 FistSrc
13166 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
13167 // to XOR'ing the high 32 bits with Adjust.
13169 // Being a power of 2, Thresh is exactly representable in all FP formats.
13170 // For X87 we'd like to use the smallest FP type for this constant, but
13171 // for DAG type consistency we have to match the FP operand type.
13173 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
13174 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
13175 bool LosesInfo = false;
13176 if (TheVT == MVT::f64)
13177 // The rounding mode is irrelevant as the conversion should be exact.
13178 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
13180 else if (TheVT == MVT::f80)
13181 Status = Thresh.convert(APFloat::x87DoubleExtended,
13182 APFloat::rmNearestTiesToEven, &LosesInfo);
13184 assert(Status == APFloat::opOK && !LosesInfo &&
13185 "FP conversion should have been exact");
13187 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
13189 SDValue Cmp = DAG.getSetCC(DL,
13190 getSetCCResultType(DAG.getDataLayout(),
13191 *DAG.getContext(), TheVT),
13192 Value, ThreshVal, ISD::SETLT);
13193 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
13194 DAG.getConstant(0, DL, MVT::i32),
13195 DAG.getConstant(0x80000000, DL, MVT::i32));
13196 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
13197 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
13198 *DAG.getContext(), TheVT),
13199 Value, ThreshVal, ISD::SETLT);
13200 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
13203 // FIXME This causes a redundant load/store if the SSE-class value is already
13204 // in memory, such as if it is on the callstack.
13205 if (isScalarFPTypeInSSEReg(TheVT)) {
13206 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13207 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13208 MachinePointerInfo::getFixedStack(MF, SSFI), false,
13210 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13212 Chain, StackSlot, DAG.getValueType(TheVT)
13215 MachineMemOperand *MMO =
13216 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13217 MachineMemOperand::MOLoad, MemSize, MemSize);
13218 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13219 Chain = Value.getValue(1);
13220 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13221 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13224 MachineMemOperand *MMO =
13225 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13226 MachineMemOperand::MOStore, MemSize, MemSize);
13228 if (UnsignedFixup) {
13230 // Insert the FIST, load its result as two i32's,
13231 // and XOR the high i32 with Adjust.
13233 SDValue FistOps[] = { Chain, Value, StackSlot };
13234 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13235 FistOps, DstTy, MMO);
13237 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
13238 MachinePointerInfo(),
13239 false, false, false, 0);
13240 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
13241 DAG.getConstant(4, DL, PtrVT));
13243 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
13244 MachinePointerInfo(),
13245 false, false, false, 0);
13246 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
13248 if (Subtarget->is64Bit()) {
13249 // Join High32 and Low32 into a 64-bit result.
13250 // (High32 << 32) | Low32
13251 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
13252 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
13253 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
13254 DAG.getConstant(32, DL, MVT::i8));
13255 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
13256 return std::make_pair(Result, SDValue());
13259 SDValue ResultOps[] = { Low32, High32 };
13261 SDValue pair = IsReplace
13262 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
13263 : DAG.getMergeValues(ResultOps, DL);
13264 return std::make_pair(pair, SDValue());
13266 // Build the FP_TO_INT*_IN_MEM
13267 SDValue Ops[] = { Chain, Value, StackSlot };
13268 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13270 return std::make_pair(FIST, StackSlot);
13274 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13275 const X86Subtarget *Subtarget) {
13276 MVT VT = Op->getSimpleValueType(0);
13277 SDValue In = Op->getOperand(0);
13278 MVT InVT = In.getSimpleValueType();
13281 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13282 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13284 // Optimize vectors in AVX mode:
13287 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13288 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13289 // Concat upper and lower parts.
13292 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13293 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13294 // Concat upper and lower parts.
13297 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13298 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13299 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13302 if (Subtarget->hasInt256())
13303 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13305 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13306 SDValue Undef = DAG.getUNDEF(InVT);
13307 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13308 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13309 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13311 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13312 VT.getVectorNumElements()/2);
13314 OpLo = DAG.getBitcast(HVT, OpLo);
13315 OpHi = DAG.getBitcast(HVT, OpHi);
13317 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13320 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13321 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13322 MVT VT = Op->getSimpleValueType(0);
13323 SDValue In = Op->getOperand(0);
13324 MVT InVT = In.getSimpleValueType();
13326 unsigned int NumElts = VT.getVectorNumElements();
13327 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13330 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13331 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13333 assert(InVT.getVectorElementType() == MVT::i1);
13334 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13336 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13338 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13340 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13341 if (VT.is512BitVector())
13343 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13346 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13347 SelectionDAG &DAG) {
13348 if (Subtarget->hasFp256())
13349 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13355 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13356 SelectionDAG &DAG) {
13358 MVT VT = Op.getSimpleValueType();
13359 SDValue In = Op.getOperand(0);
13360 MVT SVT = In.getSimpleValueType();
13362 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13363 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13365 if (Subtarget->hasFp256())
13366 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13369 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13370 VT.getVectorNumElements() != SVT.getVectorNumElements());
13374 static SDValue LowerTruncateVecI1(SDValue Op, SelectionDAG &DAG,
13375 const X86Subtarget *Subtarget) {
13378 MVT VT = Op.getSimpleValueType();
13379 SDValue In = Op.getOperand(0);
13380 MVT InVT = In.getSimpleValueType();
13382 assert(VT.getVectorElementType() == MVT::i1 && "Unexected vector type.");
13384 // Shift LSB to MSB and use VPMOVB2M - SKX.
13385 unsigned ShiftInx = InVT.getScalarSizeInBits() - 1;
13386 if ((InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13387 Subtarget->hasBWI()) || // legal, will go to VPMOVB2M, VPMOVW2M
13388 ((InVT.is256BitVector() || InVT.is128BitVector()) &&
13389 InVT.getScalarSizeInBits() <= 16 && Subtarget->hasBWI() &&
13390 Subtarget->hasVLX())) { // legal, will go to VPMOVB2M, VPMOVW2M
13391 // Shift packed bytes not supported natively, bitcast to dword
13392 MVT ExtVT = MVT::getVectorVT(MVT::i16, InVT.getSizeInBits()/16);
13393 SDValue ShiftNode = DAG.getNode(ISD::SHL, DL, ExtVT,
13394 DAG.getBitcast(ExtVT, In),
13395 DAG.getConstant(ShiftInx, DL, ExtVT));
13396 ShiftNode = DAG.getBitcast(InVT, ShiftNode);
13397 return DAG.getNode(X86ISD::CVT2MASK, DL, VT, ShiftNode);
13399 if ((InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13400 Subtarget->hasDQI()) || // legal, will go to VPMOVD2M, VPMOVQ2M
13401 ((InVT.is256BitVector() || InVT.is128BitVector()) &&
13402 InVT.getScalarSizeInBits() >= 32 && Subtarget->hasDQI() &&
13403 Subtarget->hasVLX())) { // legal, will go to VPMOVD2M, VPMOVQ2M
13405 SDValue ShiftNode = DAG.getNode(ISD::SHL, DL, InVT, In,
13406 DAG.getConstant(ShiftInx, DL, InVT));
13407 return DAG.getNode(X86ISD::CVT2MASK, DL, VT, ShiftNode);
13410 // Shift LSB to MSB, extend if necessary and use TESTM.
13411 unsigned NumElts = InVT.getVectorNumElements();
13412 if (InVT.getSizeInBits() < 512 &&
13413 (InVT.getScalarType() == MVT::i8 || InVT.getScalarType() == MVT::i16 ||
13414 !Subtarget->hasVLX())) {
13415 assert((NumElts == 8 || NumElts == 16) && "Unexected vector type.");
13417 // TESTD/Q should be used (if BW supported we use CVT2MASK above),
13418 // so vector should be extended to packed dword/qword.
13419 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(512/NumElts), NumElts);
13420 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13422 ShiftInx = InVT.getScalarSizeInBits() - 1;
13425 SDValue ShiftNode = DAG.getNode(ISD::SHL, DL, InVT, In,
13426 DAG.getConstant(ShiftInx, DL, InVT));
13427 return DAG.getNode(X86ISD::TESTM, DL, VT, ShiftNode, ShiftNode);
13430 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13432 MVT VT = Op.getSimpleValueType();
13433 SDValue In = Op.getOperand(0);
13434 MVT InVT = In.getSimpleValueType();
13436 if (VT == MVT::i1) {
13437 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13438 "Invalid scalar TRUNCATE operation");
13439 if (InVT.getSizeInBits() >= 32)
13441 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13442 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13444 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13445 "Invalid TRUNCATE operation");
13447 if (VT.getVectorElementType() == MVT::i1)
13448 return LowerTruncateVecI1(Op, DAG, Subtarget);
13450 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13451 if (Subtarget->hasAVX512()) {
13452 // word to byte only under BWI
13453 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13454 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13455 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13456 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13458 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13459 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13460 if (Subtarget->hasInt256()) {
13461 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13462 In = DAG.getBitcast(MVT::v8i32, In);
13463 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13465 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13466 DAG.getIntPtrConstant(0, DL));
13469 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13470 DAG.getIntPtrConstant(0, DL));
13471 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13472 DAG.getIntPtrConstant(2, DL));
13473 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13474 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13475 static const int ShufMask[] = {0, 2, 4, 6};
13476 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13479 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13480 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13481 if (Subtarget->hasInt256()) {
13482 In = DAG.getBitcast(MVT::v32i8, In);
13484 SmallVector<SDValue,32> pshufbMask;
13485 for (unsigned i = 0; i < 2; ++i) {
13486 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13487 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13488 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13489 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13490 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13491 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13492 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13493 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13494 for (unsigned j = 0; j < 8; ++j)
13495 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13497 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13498 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13499 In = DAG.getBitcast(MVT::v4i64, In);
13501 static const int ShufMask[] = {0, 2, -1, -1};
13502 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13504 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13505 DAG.getIntPtrConstant(0, DL));
13506 return DAG.getBitcast(VT, In);
13509 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13510 DAG.getIntPtrConstant(0, DL));
13512 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13513 DAG.getIntPtrConstant(4, DL));
13515 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13516 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13518 // The PSHUFB mask:
13519 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13520 -1, -1, -1, -1, -1, -1, -1, -1};
13522 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13523 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13524 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13526 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13527 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13529 // The MOVLHPS Mask:
13530 static const int ShufMask2[] = {0, 1, 4, 5};
13531 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13532 return DAG.getBitcast(MVT::v8i16, res);
13535 // Handle truncation of V256 to V128 using shuffles.
13536 if (!VT.is128BitVector() || !InVT.is256BitVector())
13539 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13541 unsigned NumElems = VT.getVectorNumElements();
13542 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13544 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13545 // Prepare truncation shuffle mask
13546 for (unsigned i = 0; i != NumElems; ++i)
13547 MaskVec[i] = i * 2;
13548 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13549 DAG.getUNDEF(NVT), &MaskVec[0]);
13550 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13551 DAG.getIntPtrConstant(0, DL));
13554 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13555 SelectionDAG &DAG) const {
13556 assert(!Op.getSimpleValueType().isVector());
13558 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13559 /*IsSigned=*/ true, /*IsReplace=*/ false);
13560 SDValue FIST = Vals.first, StackSlot = Vals.second;
13561 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13562 if (!FIST.getNode())
13565 if (StackSlot.getNode())
13566 // Load the result.
13567 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13568 FIST, StackSlot, MachinePointerInfo(),
13569 false, false, false, 0);
13571 // The node is the result.
13575 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13576 SelectionDAG &DAG) const {
13577 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13578 /*IsSigned=*/ false, /*IsReplace=*/ false);
13579 SDValue FIST = Vals.first, StackSlot = Vals.second;
13580 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13581 if (!FIST.getNode())
13584 if (StackSlot.getNode())
13585 // Load the result.
13586 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13587 FIST, StackSlot, MachinePointerInfo(),
13588 false, false, false, 0);
13590 // The node is the result.
13594 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13596 MVT VT = Op.getSimpleValueType();
13597 SDValue In = Op.getOperand(0);
13598 MVT SVT = In.getSimpleValueType();
13600 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13602 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13603 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13604 In, DAG.getUNDEF(SVT)));
13607 /// The only differences between FABS and FNEG are the mask and the logic op.
13608 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13609 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13610 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13611 "Wrong opcode for lowering FABS or FNEG.");
13613 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13615 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13616 // into an FNABS. We'll lower the FABS after that if it is still in use.
13618 for (SDNode *User : Op->uses())
13619 if (User->getOpcode() == ISD::FNEG)
13623 MVT VT = Op.getSimpleValueType();
13625 bool IsF128 = (VT == MVT::f128);
13627 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13628 // decide if we should generate a 16-byte constant mask when we only need 4 or
13629 // 8 bytes for the scalar case.
13635 if (VT.isVector()) {
13637 EltVT = VT.getVectorElementType();
13638 NumElts = VT.getVectorNumElements();
13639 } else if (IsF128) {
13640 // SSE instructions are used for optimized f128 logical operations.
13641 LogicVT = MVT::f128;
13645 // There are no scalar bitwise logical SSE/AVX instructions, so we
13646 // generate a 16-byte vector constant and logic op even for the scalar case.
13647 // Using a 16-byte mask allows folding the load of the mask with
13648 // the logic op, so it can save (~4 bytes) on code size.
13649 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13651 NumElts = (VT == MVT::f64) ? 2 : 4;
13654 unsigned EltBits = EltVT.getSizeInBits();
13655 LLVMContext *Context = DAG.getContext();
13656 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13658 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13659 Constant *C = ConstantInt::get(*Context, MaskElt);
13660 C = ConstantVector::getSplat(NumElts, C);
13661 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13662 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13663 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13665 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13666 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13667 false, false, false, Alignment);
13669 SDValue Op0 = Op.getOperand(0);
13670 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13672 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13673 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13675 if (VT.isVector() || IsF128)
13676 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13678 // For the scalar case extend to a 128-bit vector, perform the logic op,
13679 // and extract the scalar result back out.
13680 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13681 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13682 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13683 DAG.getIntPtrConstant(0, dl));
13686 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13687 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13688 LLVMContext *Context = DAG.getContext();
13689 SDValue Op0 = Op.getOperand(0);
13690 SDValue Op1 = Op.getOperand(1);
13692 MVT VT = Op.getSimpleValueType();
13693 MVT SrcVT = Op1.getSimpleValueType();
13694 bool IsF128 = (VT == MVT::f128);
13696 // If second operand is smaller, extend it first.
13697 if (SrcVT.bitsLT(VT)) {
13698 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13701 // And if it is bigger, shrink it first.
13702 if (SrcVT.bitsGT(VT)) {
13703 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13707 // At this point the operands and the result should have the same
13708 // type, and that won't be f80 since that is not custom lowered.
13709 assert((VT == MVT::f64 || VT == MVT::f32 || IsF128) &&
13710 "Unexpected type in LowerFCOPYSIGN");
13712 const fltSemantics &Sem =
13713 VT == MVT::f64 ? APFloat::IEEEdouble :
13714 (IsF128 ? APFloat::IEEEquad : APFloat::IEEEsingle);
13715 const unsigned SizeInBits = VT.getSizeInBits();
13717 SmallVector<Constant *, 4> CV(
13718 VT == MVT::f64 ? 2 : (IsF128 ? 1 : 4),
13719 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13721 // First, clear all bits but the sign bit from the second operand (sign).
13722 CV[0] = ConstantFP::get(*Context,
13723 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13724 Constant *C = ConstantVector::get(CV);
13725 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13726 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13728 // Perform all logic operations as 16-byte vectors because there are no
13729 // scalar FP logic instructions in SSE. This allows load folding of the
13730 // constants into the logic instructions.
13731 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : (IsF128 ? MVT::f128 : MVT::v4f32);
13733 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13734 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13735 false, false, false, 16);
13737 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13738 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13740 // Next, clear the sign bit from the first operand (magnitude).
13741 // If it's a constant, we can clear it here.
13742 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13743 APFloat APF = Op0CN->getValueAPF();
13744 // If the magnitude is a positive zero, the sign bit alone is enough.
13745 if (APF.isPosZero())
13746 return IsF128 ? SignBit :
13747 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13748 DAG.getIntPtrConstant(0, dl));
13750 CV[0] = ConstantFP::get(*Context, APF);
13752 CV[0] = ConstantFP::get(
13754 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13756 C = ConstantVector::get(CV);
13757 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13759 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13760 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13761 false, false, false, 16);
13762 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13763 if (!isa<ConstantFPSDNode>(Op0)) {
13765 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13766 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13768 // OR the magnitude value with the sign bit.
13769 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13770 return IsF128 ? Val :
13771 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13772 DAG.getIntPtrConstant(0, dl));
13775 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13776 SDValue N0 = Op.getOperand(0);
13778 MVT VT = Op.getSimpleValueType();
13780 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13781 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13782 DAG.getConstant(1, dl, VT));
13783 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13786 // Check whether an OR'd tree is PTEST-able.
13787 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13788 SelectionDAG &DAG) {
13789 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13791 if (!Subtarget->hasSSE41())
13794 if (!Op->hasOneUse())
13797 SDNode *N = Op.getNode();
13800 SmallVector<SDValue, 8> Opnds;
13801 DenseMap<SDValue, unsigned> VecInMap;
13802 SmallVector<SDValue, 8> VecIns;
13803 EVT VT = MVT::Other;
13805 // Recognize a special case where a vector is casted into wide integer to
13807 Opnds.push_back(N->getOperand(0));
13808 Opnds.push_back(N->getOperand(1));
13810 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13811 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13812 // BFS traverse all OR'd operands.
13813 if (I->getOpcode() == ISD::OR) {
13814 Opnds.push_back(I->getOperand(0));
13815 Opnds.push_back(I->getOperand(1));
13816 // Re-evaluate the number of nodes to be traversed.
13817 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13821 // Quit if a non-EXTRACT_VECTOR_ELT
13822 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13825 // Quit if without a constant index.
13826 SDValue Idx = I->getOperand(1);
13827 if (!isa<ConstantSDNode>(Idx))
13830 SDValue ExtractedFromVec = I->getOperand(0);
13831 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13832 if (M == VecInMap.end()) {
13833 VT = ExtractedFromVec.getValueType();
13834 // Quit if not 128/256-bit vector.
13835 if (!VT.is128BitVector() && !VT.is256BitVector())
13837 // Quit if not the same type.
13838 if (VecInMap.begin() != VecInMap.end() &&
13839 VT != VecInMap.begin()->first.getValueType())
13841 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13842 VecIns.push_back(ExtractedFromVec);
13844 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13847 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13848 "Not extracted from 128-/256-bit vector.");
13850 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13852 for (DenseMap<SDValue, unsigned>::const_iterator
13853 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13854 // Quit if not all elements are used.
13855 if (I->second != FullMask)
13859 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13861 // Cast all vectors into TestVT for PTEST.
13862 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13863 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13865 // If more than one full vectors are evaluated, OR them first before PTEST.
13866 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13867 // Each iteration will OR 2 nodes and append the result until there is only
13868 // 1 node left, i.e. the final OR'd value of all vectors.
13869 SDValue LHS = VecIns[Slot];
13870 SDValue RHS = VecIns[Slot + 1];
13871 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13874 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13875 VecIns.back(), VecIns.back());
13878 /// \brief return true if \c Op has a use that doesn't just read flags.
13879 static bool hasNonFlagsUse(SDValue Op) {
13880 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13882 SDNode *User = *UI;
13883 unsigned UOpNo = UI.getOperandNo();
13884 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13885 // Look pass truncate.
13886 UOpNo = User->use_begin().getOperandNo();
13887 User = *User->use_begin();
13890 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13891 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13897 /// Emit nodes that will be selected as "test Op0,Op0", or something
13899 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13900 SelectionDAG &DAG) const {
13901 if (Op.getValueType() == MVT::i1) {
13902 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13903 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13904 DAG.getConstant(0, dl, MVT::i8));
13906 // CF and OF aren't always set the way we want. Determine which
13907 // of these we need.
13908 bool NeedCF = false;
13909 bool NeedOF = false;
13912 case X86::COND_A: case X86::COND_AE:
13913 case X86::COND_B: case X86::COND_BE:
13916 case X86::COND_G: case X86::COND_GE:
13917 case X86::COND_L: case X86::COND_LE:
13918 case X86::COND_O: case X86::COND_NO: {
13919 // Check if we really need to set the
13920 // Overflow flag. If NoSignedWrap is present
13921 // that is not actually needed.
13922 switch (Op->getOpcode()) {
13927 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13928 if (BinNode->Flags.hasNoSignedWrap())
13938 // See if we can use the EFLAGS value from the operand instead of
13939 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13940 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13941 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13942 // Emit a CMP with 0, which is the TEST pattern.
13943 //if (Op.getValueType() == MVT::i1)
13944 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13945 // DAG.getConstant(0, MVT::i1));
13946 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13947 DAG.getConstant(0, dl, Op.getValueType()));
13949 unsigned Opcode = 0;
13950 unsigned NumOperands = 0;
13952 // Truncate operations may prevent the merge of the SETCC instruction
13953 // and the arithmetic instruction before it. Attempt to truncate the operands
13954 // of the arithmetic instruction and use a reduced bit-width instruction.
13955 bool NeedTruncation = false;
13956 SDValue ArithOp = Op;
13957 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13958 SDValue Arith = Op->getOperand(0);
13959 // Both the trunc and the arithmetic op need to have one user each.
13960 if (Arith->hasOneUse())
13961 switch (Arith.getOpcode()) {
13968 NeedTruncation = true;
13974 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13975 // which may be the result of a CAST. We use the variable 'Op', which is the
13976 // non-casted variable when we check for possible users.
13977 switch (ArithOp.getOpcode()) {
13979 // Due to an isel shortcoming, be conservative if this add is likely to be
13980 // selected as part of a load-modify-store instruction. When the root node
13981 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13982 // uses of other nodes in the match, such as the ADD in this case. This
13983 // leads to the ADD being left around and reselected, with the result being
13984 // two adds in the output. Alas, even if none our users are stores, that
13985 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13986 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13987 // climbing the DAG back to the root, and it doesn't seem to be worth the
13989 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13990 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13991 if (UI->getOpcode() != ISD::CopyToReg &&
13992 UI->getOpcode() != ISD::SETCC &&
13993 UI->getOpcode() != ISD::STORE)
13996 if (ConstantSDNode *C =
13997 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13998 // An add of one will be selected as an INC.
13999 if (C->isOne() && !Subtarget->slowIncDec()) {
14000 Opcode = X86ISD::INC;
14005 // An add of negative one (subtract of one) will be selected as a DEC.
14006 if (C->isAllOnesValue() && !Subtarget->slowIncDec()) {
14007 Opcode = X86ISD::DEC;
14013 // Otherwise use a regular EFLAGS-setting add.
14014 Opcode = X86ISD::ADD;
14019 // If we have a constant logical shift that's only used in a comparison
14020 // against zero turn it into an equivalent AND. This allows turning it into
14021 // a TEST instruction later.
14022 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14023 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14024 EVT VT = Op.getValueType();
14025 unsigned BitWidth = VT.getSizeInBits();
14026 unsigned ShAmt = Op->getConstantOperandVal(1);
14027 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14029 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14030 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14031 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14032 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14034 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14035 DAG.getConstant(Mask, dl, VT));
14036 DAG.ReplaceAllUsesWith(Op, New);
14042 // If the primary and result isn't used, don't bother using X86ISD::AND,
14043 // because a TEST instruction will be better.
14044 if (!hasNonFlagsUse(Op))
14050 // Due to the ISEL shortcoming noted above, be conservative if this op is
14051 // likely to be selected as part of a load-modify-store instruction.
14052 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14053 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14054 if (UI->getOpcode() == ISD::STORE)
14057 // Otherwise use a regular EFLAGS-setting instruction.
14058 switch (ArithOp.getOpcode()) {
14059 default: llvm_unreachable("unexpected operator!");
14060 case ISD::SUB: Opcode = X86ISD::SUB; break;
14061 case ISD::XOR: Opcode = X86ISD::XOR; break;
14062 case ISD::AND: Opcode = X86ISD::AND; break;
14064 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14065 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14066 if (EFLAGS.getNode())
14069 Opcode = X86ISD::OR;
14083 return SDValue(Op.getNode(), 1);
14089 // If we found that truncation is beneficial, perform the truncation and
14091 if (NeedTruncation) {
14092 EVT VT = Op.getValueType();
14093 SDValue WideVal = Op->getOperand(0);
14094 EVT WideVT = WideVal.getValueType();
14095 unsigned ConvertedOp = 0;
14096 // Use a target machine opcode to prevent further DAGCombine
14097 // optimizations that may separate the arithmetic operations
14098 // from the setcc node.
14099 switch (WideVal.getOpcode()) {
14101 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14102 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14103 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14104 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14105 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14109 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14110 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14111 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14112 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14113 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14119 // Emit a CMP with 0, which is the TEST pattern.
14120 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14121 DAG.getConstant(0, dl, Op.getValueType()));
14123 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14124 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
14126 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14127 DAG.ReplaceAllUsesWith(Op, New);
14128 return SDValue(New.getNode(), 1);
14131 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14133 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14134 SDLoc dl, SelectionDAG &DAG) const {
14135 if (isNullConstant(Op1))
14136 return EmitTest(Op0, X86CC, dl, DAG);
14138 assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
14139 "Unexpected comparison operation for MVT::i1 operands");
14141 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14142 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14143 // Do the comparison at i32 if it's smaller, besides the Atom case.
14144 // This avoids subregister aliasing issues. Keep the smaller reference
14145 // if we're optimizing for size, however, as that'll allow better folding
14146 // of memory operations.
14147 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14148 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
14149 !Subtarget->isAtom()) {
14150 unsigned ExtendOp =
14151 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14152 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14153 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14155 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14156 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14157 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14159 return SDValue(Sub.getNode(), 1);
14161 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14164 /// Convert a comparison if required by the subtarget.
14165 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14166 SelectionDAG &DAG) const {
14167 // If the subtarget does not support the FUCOMI instruction, floating-point
14168 // comparisons have to be converted.
14169 if (Subtarget->hasCMov() ||
14170 Cmp.getOpcode() != X86ISD::CMP ||
14171 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14172 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14175 // The instruction selector will select an FUCOM instruction instead of
14176 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14177 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14178 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14180 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14181 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14182 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14183 DAG.getConstant(8, dl, MVT::i8));
14184 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14186 // Some 64-bit targets lack SAHF support, but they do support FCOMI.
14187 assert(Subtarget->hasLAHFSAHF() && "Target doesn't support SAHF or FCOMI?");
14188 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14191 /// The minimum architected relative accuracy is 2^-12. We need one
14192 /// Newton-Raphson step to have a good float result (24 bits of precision).
14193 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14194 DAGCombinerInfo &DCI,
14195 unsigned &RefinementSteps,
14196 bool &UseOneConstNR) const {
14197 EVT VT = Op.getValueType();
14198 const char *RecipOp;
14200 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
14201 // TODO: Add support for AVX512 (v16f32).
14202 // It is likely not profitable to do this for f64 because a double-precision
14203 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14204 // instructions: convert to single, rsqrtss, convert back to double, refine
14205 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14206 // along with FMA, this could be a throughput win.
14207 if (VT == MVT::f32 && Subtarget->hasSSE1())
14209 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
14210 (VT == MVT::v8f32 && Subtarget->hasAVX()))
14211 RecipOp = "vec-sqrtf";
14215 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14216 if (!Recips.isEnabled(RecipOp))
14219 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14220 UseOneConstNR = false;
14221 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14224 /// The minimum architected relative accuracy is 2^-12. We need one
14225 /// Newton-Raphson step to have a good float result (24 bits of precision).
14226 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14227 DAGCombinerInfo &DCI,
14228 unsigned &RefinementSteps) const {
14229 EVT VT = Op.getValueType();
14230 const char *RecipOp;
14232 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14233 // TODO: Add support for AVX512 (v16f32).
14234 // It is likely not profitable to do this for f64 because a double-precision
14235 // reciprocal estimate with refinement on x86 prior to FMA requires
14236 // 15 instructions: convert to single, rcpss, convert back to double, refine
14237 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14238 // along with FMA, this could be a throughput win.
14239 if (VT == MVT::f32 && Subtarget->hasSSE1())
14241 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
14242 (VT == MVT::v8f32 && Subtarget->hasAVX()))
14243 RecipOp = "vec-divf";
14247 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14248 if (!Recips.isEnabled(RecipOp))
14251 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14252 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14255 /// If we have at least two divisions that use the same divisor, convert to
14256 /// multplication by a reciprocal. This may need to be adjusted for a given
14257 /// CPU if a division's cost is not at least twice the cost of a multiplication.
14258 /// This is because we still need one division to calculate the reciprocal and
14259 /// then we need two multiplies by that reciprocal as replacements for the
14260 /// original divisions.
14261 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
14265 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14266 /// if it's possible.
14267 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14268 SDLoc dl, SelectionDAG &DAG) const {
14269 SDValue Op0 = And.getOperand(0);
14270 SDValue Op1 = And.getOperand(1);
14271 if (Op0.getOpcode() == ISD::TRUNCATE)
14272 Op0 = Op0.getOperand(0);
14273 if (Op1.getOpcode() == ISD::TRUNCATE)
14274 Op1 = Op1.getOperand(0);
14277 if (Op1.getOpcode() == ISD::SHL)
14278 std::swap(Op0, Op1);
14279 if (Op0.getOpcode() == ISD::SHL) {
14280 if (isOneConstant(Op0.getOperand(0))) {
14281 // If we looked past a truncate, check that it's only truncating away
14283 unsigned BitWidth = Op0.getValueSizeInBits();
14284 unsigned AndBitWidth = And.getValueSizeInBits();
14285 if (BitWidth > AndBitWidth) {
14287 DAG.computeKnownBits(Op0, Zeros, Ones);
14288 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14292 RHS = Op0.getOperand(1);
14294 } else if (Op1.getOpcode() == ISD::Constant) {
14295 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14296 uint64_t AndRHSVal = AndRHS->getZExtValue();
14297 SDValue AndLHS = Op0;
14299 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14300 LHS = AndLHS.getOperand(0);
14301 RHS = AndLHS.getOperand(1);
14304 // Use BT if the immediate can't be encoded in a TEST instruction.
14305 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14307 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
14311 if (LHS.getNode()) {
14312 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14313 // instruction. Since the shift amount is in-range-or-undefined, we know
14314 // that doing a bittest on the i32 value is ok. We extend to i32 because
14315 // the encoding for the i16 version is larger than the i32 version.
14316 // Also promote i16 to i32 for performance / code size reason.
14317 if (LHS.getValueType() == MVT::i8 ||
14318 LHS.getValueType() == MVT::i16)
14319 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14321 // If the operand types disagree, extend the shift amount to match. Since
14322 // BT ignores high bits (like shifts) we can use anyextend.
14323 if (LHS.getValueType() != RHS.getValueType())
14324 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14326 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14327 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14328 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14329 DAG.getConstant(Cond, dl, MVT::i8), BT);
14335 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14337 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14342 // SSE Condition code mapping:
14351 switch (SetCCOpcode) {
14352 default: llvm_unreachable("Unexpected SETCC condition");
14354 case ISD::SETEQ: SSECC = 0; break;
14356 case ISD::SETGT: Swap = true; // Fallthrough
14358 case ISD::SETOLT: SSECC = 1; break;
14360 case ISD::SETGE: Swap = true; // Fallthrough
14362 case ISD::SETOLE: SSECC = 2; break;
14363 case ISD::SETUO: SSECC = 3; break;
14365 case ISD::SETNE: SSECC = 4; break;
14366 case ISD::SETULE: Swap = true; // Fallthrough
14367 case ISD::SETUGE: SSECC = 5; break;
14368 case ISD::SETULT: Swap = true; // Fallthrough
14369 case ISD::SETUGT: SSECC = 6; break;
14370 case ISD::SETO: SSECC = 7; break;
14372 case ISD::SETONE: SSECC = 8; break;
14375 std::swap(Op0, Op1);
14380 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14381 // ones, and then concatenate the result back.
14382 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14383 MVT VT = Op.getSimpleValueType();
14385 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14386 "Unsupported value type for operation");
14388 unsigned NumElems = VT.getVectorNumElements();
14390 SDValue CC = Op.getOperand(2);
14392 // Extract the LHS vectors
14393 SDValue LHS = Op.getOperand(0);
14394 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14395 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14397 // Extract the RHS vectors
14398 SDValue RHS = Op.getOperand(1);
14399 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14400 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14402 // Issue the operation on the smaller types and concatenate the result back
14403 MVT EltVT = VT.getVectorElementType();
14404 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14405 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14406 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14407 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14410 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14411 SDValue Op0 = Op.getOperand(0);
14412 SDValue Op1 = Op.getOperand(1);
14413 SDValue CC = Op.getOperand(2);
14414 MVT VT = Op.getSimpleValueType();
14417 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14418 "Unexpected type for boolean compare operation");
14419 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14420 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14421 DAG.getConstant(-1, dl, VT));
14422 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14423 DAG.getConstant(-1, dl, VT));
14424 switch (SetCCOpcode) {
14425 default: llvm_unreachable("Unexpected SETCC condition");
14427 // (x == y) -> ~(x ^ y)
14428 return DAG.getNode(ISD::XOR, dl, VT,
14429 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14430 DAG.getConstant(-1, dl, VT));
14432 // (x != y) -> (x ^ y)
14433 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14436 // (x > y) -> (x & ~y)
14437 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14440 // (x < y) -> (~x & y)
14441 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14444 // (x <= y) -> (~x | y)
14445 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14448 // (x >=y) -> (x | ~y)
14449 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14453 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14454 const X86Subtarget *Subtarget) {
14455 SDValue Op0 = Op.getOperand(0);
14456 SDValue Op1 = Op.getOperand(1);
14457 SDValue CC = Op.getOperand(2);
14458 MVT VT = Op.getSimpleValueType();
14461 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14462 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14463 "Cannot set masked compare for this operation");
14465 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14467 bool Unsigned = false;
14470 switch (SetCCOpcode) {
14471 default: llvm_unreachable("Unexpected SETCC condition");
14472 case ISD::SETNE: SSECC = 4; break;
14473 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14474 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14475 case ISD::SETLT: Swap = true; //fall-through
14476 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14477 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14478 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14479 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14480 case ISD::SETULE: Unsigned = true; //fall-through
14481 case ISD::SETLE: SSECC = 2; break;
14485 std::swap(Op0, Op1);
14487 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14488 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14489 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14490 DAG.getConstant(SSECC, dl, MVT::i8));
14493 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14494 /// operand \p Op1. If non-trivial (for example because it's not constant)
14495 /// return an empty value.
14496 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14498 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14502 MVT VT = Op1.getSimpleValueType();
14503 MVT EVT = VT.getVectorElementType();
14504 unsigned n = VT.getVectorNumElements();
14505 SmallVector<SDValue, 8> ULTOp1;
14507 for (unsigned i = 0; i < n; ++i) {
14508 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14509 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14512 // Avoid underflow.
14513 APInt Val = Elt->getAPIntValue();
14517 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14520 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14523 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14524 SelectionDAG &DAG) {
14525 SDValue Op0 = Op.getOperand(0);
14526 SDValue Op1 = Op.getOperand(1);
14527 SDValue CC = Op.getOperand(2);
14528 MVT VT = Op.getSimpleValueType();
14529 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14530 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14535 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14536 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14539 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14540 unsigned Opc = X86ISD::CMPP;
14541 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14542 assert(VT.getVectorNumElements() <= 16);
14543 Opc = X86ISD::CMPM;
14545 // In the two special cases we can't handle, emit two comparisons.
14548 unsigned CombineOpc;
14549 if (SetCCOpcode == ISD::SETUEQ) {
14550 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14552 assert(SetCCOpcode == ISD::SETONE);
14553 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14556 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14557 DAG.getConstant(CC0, dl, MVT::i8));
14558 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14559 DAG.getConstant(CC1, dl, MVT::i8));
14560 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14562 // Handle all other FP comparisons here.
14563 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14564 DAG.getConstant(SSECC, dl, MVT::i8));
14567 MVT VTOp0 = Op0.getSimpleValueType();
14568 assert(VTOp0 == Op1.getSimpleValueType() &&
14569 "Expected operands with same type!");
14570 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14571 "Invalid number of packed elements for source and destination!");
14573 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14574 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14575 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14576 // legalizer firstly checks if the first operand in input to the setcc has
14577 // a legal type. If so, then it promotes the return type to that same type.
14578 // Otherwise, the return type is promoted to the 'next legal type' which,
14579 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14581 // We reach this code only if the following two conditions are met:
14582 // 1. Both return type and operand type have been promoted to wider types
14583 // by the type legalizer.
14584 // 2. The original operand type has been promoted to a 256-bit vector.
14586 // Note that condition 2. only applies for AVX targets.
14587 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14588 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14591 // The non-AVX512 code below works under the assumption that source and
14592 // destination types are the same.
14593 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14594 "Value types for source and destination must be the same!");
14596 // Break 256-bit integer vector compare into smaller ones.
14597 if (VT.is256BitVector() && !Subtarget->hasInt256())
14598 return Lower256IntVSETCC(Op, DAG);
14600 MVT OpVT = Op1.getSimpleValueType();
14601 if (OpVT.getVectorElementType() == MVT::i1)
14602 return LowerBoolVSETCC_AVX512(Op, DAG);
14604 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14605 if (Subtarget->hasAVX512()) {
14606 if (Op1.getSimpleValueType().is512BitVector() ||
14607 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14608 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14609 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14611 // In AVX-512 architecture setcc returns mask with i1 elements,
14612 // But there is no compare instruction for i8 and i16 elements in KNL.
14613 // We are not talking about 512-bit operands in this case, these
14614 // types are illegal.
14616 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14617 OpVT.getVectorElementType().getSizeInBits() >= 8))
14618 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14619 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14622 // Lower using XOP integer comparisons.
14623 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14624 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14625 // Translate compare code to XOP PCOM compare mode.
14626 unsigned CmpMode = 0;
14627 switch (SetCCOpcode) {
14628 default: llvm_unreachable("Unexpected SETCC condition");
14630 case ISD::SETLT: CmpMode = 0x00; break;
14632 case ISD::SETLE: CmpMode = 0x01; break;
14634 case ISD::SETGT: CmpMode = 0x02; break;
14636 case ISD::SETGE: CmpMode = 0x03; break;
14637 case ISD::SETEQ: CmpMode = 0x04; break;
14638 case ISD::SETNE: CmpMode = 0x05; break;
14641 // Are we comparing unsigned or signed integers?
14642 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14643 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14645 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14646 DAG.getConstant(CmpMode, dl, MVT::i8));
14649 // We are handling one of the integer comparisons here. Since SSE only has
14650 // GT and EQ comparisons for integer, swapping operands and multiple
14651 // operations may be required for some comparisons.
14653 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14654 bool Subus = false;
14656 switch (SetCCOpcode) {
14657 default: llvm_unreachable("Unexpected SETCC condition");
14658 case ISD::SETNE: Invert = true;
14659 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14660 case ISD::SETLT: Swap = true;
14661 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14662 case ISD::SETGE: Swap = true;
14663 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14664 Invert = true; break;
14665 case ISD::SETULT: Swap = true;
14666 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14667 FlipSigns = true; break;
14668 case ISD::SETUGE: Swap = true;
14669 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14670 FlipSigns = true; Invert = true; break;
14673 // Special case: Use min/max operations for SETULE/SETUGE
14674 MVT VET = VT.getVectorElementType();
14676 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14677 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14680 switch (SetCCOpcode) {
14682 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14683 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14686 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14689 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14690 if (!MinMax && hasSubus) {
14691 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14693 // t = psubus Op0, Op1
14694 // pcmpeq t, <0..0>
14695 switch (SetCCOpcode) {
14697 case ISD::SETULT: {
14698 // If the comparison is against a constant we can turn this into a
14699 // setule. With psubus, setule does not require a swap. This is
14700 // beneficial because the constant in the register is no longer
14701 // destructed as the destination so it can be hoisted out of a loop.
14702 // Only do this pre-AVX since vpcmp* is no longer destructive.
14703 if (Subtarget->hasAVX())
14705 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14706 if (ULEOp1.getNode()) {
14708 Subus = true; Invert = false; Swap = false;
14712 // Psubus is better than flip-sign because it requires no inversion.
14713 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14714 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14718 Opc = X86ISD::SUBUS;
14724 std::swap(Op0, Op1);
14726 // Check that the operation in question is available (most are plain SSE2,
14727 // but PCMPGTQ and PCMPEQQ have different requirements).
14728 if (VT == MVT::v2i64) {
14729 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14730 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14732 // First cast everything to the right type.
14733 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14734 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14736 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14737 // bits of the inputs before performing those operations. The lower
14738 // compare is always unsigned.
14741 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14743 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14744 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14745 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14746 Sign, Zero, Sign, Zero);
14748 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14749 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14751 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14752 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14753 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14755 // Create masks for only the low parts/high parts of the 64 bit integers.
14756 static const int MaskHi[] = { 1, 1, 3, 3 };
14757 static const int MaskLo[] = { 0, 0, 2, 2 };
14758 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14759 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14760 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14762 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14763 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14766 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14768 return DAG.getBitcast(VT, Result);
14771 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14772 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14773 // pcmpeqd + pshufd + pand.
14774 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14776 // First cast everything to the right type.
14777 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14778 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14781 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14783 // Make sure the lower and upper halves are both all-ones.
14784 static const int Mask[] = { 1, 0, 3, 2 };
14785 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14786 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14789 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14791 return DAG.getBitcast(VT, Result);
14795 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14796 // bits of the inputs before performing those operations.
14798 MVT EltVT = VT.getVectorElementType();
14799 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14801 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14802 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14805 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14807 // If the logical-not of the result is required, perform that now.
14809 Result = DAG.getNOT(dl, Result, VT);
14812 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14815 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14816 getZeroVector(VT, Subtarget, DAG, dl));
14821 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14823 MVT VT = Op.getSimpleValueType();
14825 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14827 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14828 && "SetCC type must be 8-bit or 1-bit integer");
14829 SDValue Op0 = Op.getOperand(0);
14830 SDValue Op1 = Op.getOperand(1);
14832 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14834 // Optimize to BT if possible.
14835 // Lower (X & (1 << N)) == 0 to BT(X, N).
14836 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14837 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14838 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14839 isNullConstant(Op1) &&
14840 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14841 if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
14843 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14848 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14850 if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
14851 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14853 // If the input is a setcc, then reuse the input setcc or use a new one with
14854 // the inverted condition.
14855 if (Op0.getOpcode() == X86ISD::SETCC) {
14856 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14857 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
14861 CCode = X86::GetOppositeBranchCondition(CCode);
14862 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14863 DAG.getConstant(CCode, dl, MVT::i8),
14864 Op0.getOperand(1));
14866 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14870 if ((Op0.getValueType() == MVT::i1) && isOneConstant(Op1) &&
14871 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14873 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14874 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14877 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14878 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14879 if (X86CC == X86::COND_INVALID)
14882 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14883 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14884 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14885 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14887 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14891 SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
14892 SDValue LHS = Op.getOperand(0);
14893 SDValue RHS = Op.getOperand(1);
14894 SDValue Carry = Op.getOperand(2);
14895 SDValue Cond = Op.getOperand(3);
14898 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
14899 X86::CondCode CC = TranslateIntegerX86CC(cast<CondCodeSDNode>(Cond)->get());
14901 assert(Carry.getOpcode() != ISD::CARRY_FALSE);
14902 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14903 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry);
14904 return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
14905 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
14908 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14909 static bool isX86LogicalCmp(SDValue Op) {
14910 unsigned Opc = Op.getNode()->getOpcode();
14911 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14912 Opc == X86ISD::SAHF)
14914 if (Op.getResNo() == 1 &&
14915 (Opc == X86ISD::ADD ||
14916 Opc == X86ISD::SUB ||
14917 Opc == X86ISD::ADC ||
14918 Opc == X86ISD::SBB ||
14919 Opc == X86ISD::SMUL ||
14920 Opc == X86ISD::UMUL ||
14921 Opc == X86ISD::INC ||
14922 Opc == X86ISD::DEC ||
14923 Opc == X86ISD::OR ||
14924 Opc == X86ISD::XOR ||
14925 Opc == X86ISD::AND))
14928 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14934 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14935 if (V.getOpcode() != ISD::TRUNCATE)
14938 SDValue VOp0 = V.getOperand(0);
14939 unsigned InBits = VOp0.getValueSizeInBits();
14940 unsigned Bits = V.getValueSizeInBits();
14941 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14944 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14945 bool addTest = true;
14946 SDValue Cond = Op.getOperand(0);
14947 SDValue Op1 = Op.getOperand(1);
14948 SDValue Op2 = Op.getOperand(2);
14950 MVT VT = Op1.getSimpleValueType();
14953 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14954 // are available or VBLENDV if AVX is available.
14955 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14956 if (Cond.getOpcode() == ISD::SETCC &&
14957 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14958 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14959 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14960 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14961 int SSECC = translateX86FSETCC(
14962 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14965 if (Subtarget->hasAVX512()) {
14966 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14967 DAG.getConstant(SSECC, DL, MVT::i8));
14968 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14971 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14972 DAG.getConstant(SSECC, DL, MVT::i8));
14974 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14975 // of 3 logic instructions for size savings and potentially speed.
14976 // Unfortunately, there is no scalar form of VBLENDV.
14978 // If either operand is a constant, don't try this. We can expect to
14979 // optimize away at least one of the logic instructions later in that
14980 // case, so that sequence would be faster than a variable blend.
14982 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14983 // uses XMM0 as the selection register. That may need just as many
14984 // instructions as the AND/ANDN/OR sequence due to register moves, so
14987 if (Subtarget->hasAVX() &&
14988 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14990 // Convert to vectors, do a VSELECT, and convert back to scalar.
14991 // All of the conversions should be optimized away.
14993 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14994 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14995 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14996 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14998 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14999 VCmp = DAG.getBitcast(VCmpVT, VCmp);
15001 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
15003 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
15004 VSel, DAG.getIntPtrConstant(0, DL));
15006 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15007 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15008 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15012 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
15014 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
15015 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
15016 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
15017 Op1Scalar = Op1.getOperand(0);
15019 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
15020 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
15021 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
15022 Op2Scalar = Op2.getOperand(0);
15023 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
15024 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
15025 Op1Scalar.getValueType(),
15026 Cond, Op1Scalar, Op2Scalar);
15027 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
15028 return DAG.getBitcast(VT, newSelect);
15029 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
15030 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
15031 DAG.getIntPtrConstant(0, DL));
15035 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
15036 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
15037 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
15038 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
15039 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
15040 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
15041 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
15043 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
15046 if (Cond.getOpcode() == ISD::SETCC) {
15047 SDValue NewCond = LowerSETCC(Cond, DAG);
15048 if (NewCond.getNode())
15052 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15053 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15054 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15055 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15056 if (Cond.getOpcode() == X86ISD::SETCC &&
15057 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15058 isNullConstant(Cond.getOperand(1).getOperand(1))) {
15059 SDValue Cmp = Cond.getOperand(1);
15061 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15063 if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
15064 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15065 SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
15067 SDValue CmpOp0 = Cmp.getOperand(0);
15068 // Apply further optimizations for special cases
15069 // (select (x != 0), -1, 0) -> neg & sbb
15070 // (select (x == 0), 0, -1) -> neg & sbb
15071 if (isNullConstant(Y) &&
15072 (isAllOnesConstant(Op1) == (CondCode == X86::COND_NE))) {
15073 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15074 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15075 DAG.getConstant(0, DL,
15076 CmpOp0.getValueType()),
15078 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15079 DAG.getConstant(X86::COND_B, DL, MVT::i8),
15080 SDValue(Neg.getNode(), 1));
15084 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15085 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
15086 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15088 SDValue Res = // Res = 0 or -1.
15089 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15090 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
15092 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_E))
15093 Res = DAG.getNOT(DL, Res, Res.getValueType());
15095 if (!isNullConstant(Op2))
15096 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15101 // Look past (and (setcc_carry (cmp ...)), 1).
15102 if (Cond.getOpcode() == ISD::AND &&
15103 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
15104 isOneConstant(Cond.getOperand(1)))
15105 Cond = Cond.getOperand(0);
15107 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15108 // setting operand in place of the X86ISD::SETCC.
15109 unsigned CondOpcode = Cond.getOpcode();
15110 if (CondOpcode == X86ISD::SETCC ||
15111 CondOpcode == X86ISD::SETCC_CARRY) {
15112 CC = Cond.getOperand(0);
15114 SDValue Cmp = Cond.getOperand(1);
15115 unsigned Opc = Cmp.getOpcode();
15116 MVT VT = Op.getSimpleValueType();
15118 bool IllegalFPCMov = false;
15119 if (VT.isFloatingPoint() && !VT.isVector() &&
15120 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15121 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15123 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15124 Opc == X86ISD::BT) { // FIXME
15128 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15129 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15130 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15131 Cond.getOperand(0).getValueType() != MVT::i8)) {
15132 SDValue LHS = Cond.getOperand(0);
15133 SDValue RHS = Cond.getOperand(1);
15134 unsigned X86Opcode;
15137 switch (CondOpcode) {
15138 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15139 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15140 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15141 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15142 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15143 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15144 default: llvm_unreachable("unexpected overflowing operator");
15146 if (CondOpcode == ISD::UMULO)
15147 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15150 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15152 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15154 if (CondOpcode == ISD::UMULO)
15155 Cond = X86Op.getValue(2);
15157 Cond = X86Op.getValue(1);
15159 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
15164 // Look past the truncate if the high bits are known zero.
15165 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15166 Cond = Cond.getOperand(0);
15168 // We know the result of AND is compared against zero. Try to match
15170 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15171 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
15172 CC = NewSetCC.getOperand(0);
15173 Cond = NewSetCC.getOperand(1);
15180 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
15181 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15184 // a < b ? -1 : 0 -> RES = ~setcc_carry
15185 // a < b ? 0 : -1 -> RES = setcc_carry
15186 // a >= b ? -1 : 0 -> RES = setcc_carry
15187 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15188 if (Cond.getOpcode() == X86ISD::SUB) {
15189 Cond = ConvertCmpIfNecessary(Cond, DAG);
15190 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15192 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15193 (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
15194 (isNullConstant(Op1) || isNullConstant(Op2))) {
15195 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15196 DAG.getConstant(X86::COND_B, DL, MVT::i8),
15198 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_B))
15199 return DAG.getNOT(DL, Res, Res.getValueType());
15204 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15205 // widen the cmov and push the truncate through. This avoids introducing a new
15206 // branch during isel and doesn't add any extensions.
15207 if (Op.getValueType() == MVT::i8 &&
15208 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15209 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15210 if (T1.getValueType() == T2.getValueType() &&
15211 // Blacklist CopyFromReg to avoid partial register stalls.
15212 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15213 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15214 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15215 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15219 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15220 // condition is true.
15221 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15222 SDValue Ops[] = { Op2, Op1, CC, Cond };
15223 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15226 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
15227 const X86Subtarget *Subtarget,
15228 SelectionDAG &DAG) {
15229 MVT VT = Op->getSimpleValueType(0);
15230 SDValue In = Op->getOperand(0);
15231 MVT InVT = In.getSimpleValueType();
15232 MVT VTElt = VT.getVectorElementType();
15233 MVT InVTElt = InVT.getVectorElementType();
15237 if ((InVTElt == MVT::i1) &&
15238 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15239 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15241 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15242 VTElt.getSizeInBits() <= 16)) ||
15244 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15245 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15247 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15248 VTElt.getSizeInBits() >= 32))))
15249 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15251 unsigned int NumElts = VT.getVectorNumElements();
15253 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
15256 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15257 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15258 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15259 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15262 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15263 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
15265 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
15268 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
15270 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
15271 if (VT.is512BitVector())
15273 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
15276 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
15277 const X86Subtarget *Subtarget,
15278 SelectionDAG &DAG) {
15279 SDValue In = Op->getOperand(0);
15280 MVT VT = Op->getSimpleValueType(0);
15281 MVT InVT = In.getSimpleValueType();
15282 assert(VT.getSizeInBits() == InVT.getSizeInBits());
15284 MVT InSVT = InVT.getVectorElementType();
15285 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
15287 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
15289 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
15294 // SSE41 targets can use the pmovsx* instructions directly.
15295 if (Subtarget->hasSSE41())
15296 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15298 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
15302 // As SRAI is only available on i16/i32 types, we expand only up to i32
15303 // and handle i64 separately.
15304 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
15305 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
15306 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
15307 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
15308 Curr = DAG.getBitcast(CurrVT, Curr);
15311 SDValue SignExt = Curr;
15312 if (CurrVT != InVT) {
15313 unsigned SignExtShift =
15314 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
15315 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15316 DAG.getConstant(SignExtShift, dl, MVT::i8));
15322 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15323 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15324 DAG.getConstant(31, dl, MVT::i8));
15325 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15326 return DAG.getBitcast(VT, Ext);
15332 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15333 SelectionDAG &DAG) {
15334 MVT VT = Op->getSimpleValueType(0);
15335 SDValue In = Op->getOperand(0);
15336 MVT InVT = In.getSimpleValueType();
15339 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15340 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15342 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15343 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15344 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15347 if (Subtarget->hasInt256())
15348 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15350 // Optimize vectors in AVX mode
15351 // Sign extend v8i16 to v8i32 and
15354 // Divide input vector into two parts
15355 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15356 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15357 // concat the vectors to original VT
15359 unsigned NumElems = InVT.getVectorNumElements();
15360 SDValue Undef = DAG.getUNDEF(InVT);
15362 SmallVector<int,8> ShufMask1(NumElems, -1);
15363 for (unsigned i = 0; i != NumElems/2; ++i)
15366 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15368 SmallVector<int,8> ShufMask2(NumElems, -1);
15369 for (unsigned i = 0; i != NumElems/2; ++i)
15370 ShufMask2[i] = i + NumElems/2;
15372 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15374 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15375 VT.getVectorNumElements()/2);
15377 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15378 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15380 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15383 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15384 // may emit an illegal shuffle but the expansion is still better than scalar
15385 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15386 // we'll emit a shuffle and a arithmetic shift.
15387 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15388 // TODO: It is possible to support ZExt by zeroing the undef values during
15389 // the shuffle phase or after the shuffle.
15390 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15391 SelectionDAG &DAG) {
15392 MVT RegVT = Op.getSimpleValueType();
15393 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15394 assert(RegVT.isInteger() &&
15395 "We only custom lower integer vector sext loads.");
15397 // Nothing useful we can do without SSE2 shuffles.
15398 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15400 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15402 EVT MemVT = Ld->getMemoryVT();
15403 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15404 unsigned RegSz = RegVT.getSizeInBits();
15406 ISD::LoadExtType Ext = Ld->getExtensionType();
15408 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15409 && "Only anyext and sext are currently implemented.");
15410 assert(MemVT != RegVT && "Cannot extend to the same type");
15411 assert(MemVT.isVector() && "Must load a vector from memory");
15413 unsigned NumElems = RegVT.getVectorNumElements();
15414 unsigned MemSz = MemVT.getSizeInBits();
15415 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15417 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15418 // The only way in which we have a legal 256-bit vector result but not the
15419 // integer 256-bit operations needed to directly lower a sextload is if we
15420 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15421 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15422 // correctly legalized. We do this late to allow the canonical form of
15423 // sextload to persist throughout the rest of the DAG combiner -- it wants
15424 // to fold together any extensions it can, and so will fuse a sign_extend
15425 // of an sextload into a sextload targeting a wider value.
15427 if (MemSz == 128) {
15428 // Just switch this to a normal load.
15429 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15430 "it must be a legal 128-bit vector "
15432 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15433 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15434 Ld->isInvariant(), Ld->getAlignment());
15436 assert(MemSz < 128 &&
15437 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15438 // Do an sext load to a 128-bit vector type. We want to use the same
15439 // number of elements, but elements half as wide. This will end up being
15440 // recursively lowered by this routine, but will succeed as we definitely
15441 // have all the necessary features if we're using AVX1.
15443 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15444 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15446 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15447 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15448 Ld->isNonTemporal(), Ld->isInvariant(),
15449 Ld->getAlignment());
15452 // Replace chain users with the new chain.
15453 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15454 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15456 // Finally, do a normal sign-extend to the desired register.
15457 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15460 // All sizes must be a power of two.
15461 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15462 "Non-power-of-two elements are not custom lowered!");
15464 // Attempt to load the original value using scalar loads.
15465 // Find the largest scalar type that divides the total loaded size.
15466 MVT SclrLoadTy = MVT::i8;
15467 for (MVT Tp : MVT::integer_valuetypes()) {
15468 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15473 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15474 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15476 SclrLoadTy = MVT::f64;
15478 // Calculate the number of scalar loads that we need to perform
15479 // in order to load our vector from memory.
15480 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15482 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15483 "Can only lower sext loads with a single scalar load!");
15485 unsigned loadRegZize = RegSz;
15486 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15489 // Represent our vector as a sequence of elements which are the
15490 // largest scalar that we can load.
15491 EVT LoadUnitVecVT = EVT::getVectorVT(
15492 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15494 // Represent the data using the same element type that is stored in
15495 // memory. In practice, we ''widen'' MemVT.
15497 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15498 loadRegZize / MemVT.getScalarSizeInBits());
15500 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15501 "Invalid vector type");
15503 // We can't shuffle using an illegal type.
15504 assert(TLI.isTypeLegal(WideVecVT) &&
15505 "We only lower types that form legal widened vector types");
15507 SmallVector<SDValue, 8> Chains;
15508 SDValue Ptr = Ld->getBasePtr();
15509 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15510 TLI.getPointerTy(DAG.getDataLayout()));
15511 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15513 for (unsigned i = 0; i < NumLoads; ++i) {
15514 // Perform a single load.
15515 SDValue ScalarLoad =
15516 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15517 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15518 Ld->getAlignment());
15519 Chains.push_back(ScalarLoad.getValue(1));
15520 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15521 // another round of DAGCombining.
15523 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15525 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15526 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15528 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15531 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15533 // Bitcast the loaded value to a vector of the original element type, in
15534 // the size of the target vector type.
15535 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15536 unsigned SizeRatio = RegSz / MemSz;
15538 if (Ext == ISD::SEXTLOAD) {
15539 // If we have SSE4.1, we can directly emit a VSEXT node.
15540 if (Subtarget->hasSSE41()) {
15541 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15542 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15546 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15548 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15549 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15551 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15552 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15556 // Redistribute the loaded elements into the different locations.
15557 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15558 for (unsigned i = 0; i != NumElems; ++i)
15559 ShuffleVec[i * SizeRatio] = i;
15561 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15562 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15564 // Bitcast to the requested type.
15565 Shuff = DAG.getBitcast(RegVT, Shuff);
15566 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15570 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15571 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15572 // from the AND / OR.
15573 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15574 Opc = Op.getOpcode();
15575 if (Opc != ISD::OR && Opc != ISD::AND)
15577 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15578 Op.getOperand(0).hasOneUse() &&
15579 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15580 Op.getOperand(1).hasOneUse());
15583 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15584 // 1 and that the SETCC node has a single use.
15585 static bool isXor1OfSetCC(SDValue Op) {
15586 if (Op.getOpcode() != ISD::XOR)
15588 if (isOneConstant(Op.getOperand(1)))
15589 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15590 Op.getOperand(0).hasOneUse();
15594 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15595 bool addTest = true;
15596 SDValue Chain = Op.getOperand(0);
15597 SDValue Cond = Op.getOperand(1);
15598 SDValue Dest = Op.getOperand(2);
15601 bool Inverted = false;
15603 if (Cond.getOpcode() == ISD::SETCC) {
15604 // Check for setcc([su]{add,sub,mul}o == 0).
15605 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15606 isNullConstant(Cond.getOperand(1)) &&
15607 Cond.getOperand(0).getResNo() == 1 &&
15608 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15609 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15610 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15611 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15612 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15613 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15615 Cond = Cond.getOperand(0);
15617 SDValue NewCond = LowerSETCC(Cond, DAG);
15618 if (NewCond.getNode())
15623 // FIXME: LowerXALUO doesn't handle these!!
15624 else if (Cond.getOpcode() == X86ISD::ADD ||
15625 Cond.getOpcode() == X86ISD::SUB ||
15626 Cond.getOpcode() == X86ISD::SMUL ||
15627 Cond.getOpcode() == X86ISD::UMUL)
15628 Cond = LowerXALUO(Cond, DAG);
15631 // Look pass (and (setcc_carry (cmp ...)), 1).
15632 if (Cond.getOpcode() == ISD::AND &&
15633 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
15634 isOneConstant(Cond.getOperand(1)))
15635 Cond = Cond.getOperand(0);
15637 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15638 // setting operand in place of the X86ISD::SETCC.
15639 unsigned CondOpcode = Cond.getOpcode();
15640 if (CondOpcode == X86ISD::SETCC ||
15641 CondOpcode == X86ISD::SETCC_CARRY) {
15642 CC = Cond.getOperand(0);
15644 SDValue Cmp = Cond.getOperand(1);
15645 unsigned Opc = Cmp.getOpcode();
15646 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15647 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15651 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15655 // These can only come from an arithmetic instruction with overflow,
15656 // e.g. SADDO, UADDO.
15657 Cond = Cond.getNode()->getOperand(1);
15663 CondOpcode = Cond.getOpcode();
15664 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15665 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15666 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15667 Cond.getOperand(0).getValueType() != MVT::i8)) {
15668 SDValue LHS = Cond.getOperand(0);
15669 SDValue RHS = Cond.getOperand(1);
15670 unsigned X86Opcode;
15673 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15674 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15676 switch (CondOpcode) {
15677 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15679 if (isOneConstant(RHS)) {
15680 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15683 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15684 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15686 if (isOneConstant(RHS)) {
15687 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15690 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15691 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15692 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15693 default: llvm_unreachable("unexpected overflowing operator");
15696 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15697 if (CondOpcode == ISD::UMULO)
15698 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15701 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15703 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15705 if (CondOpcode == ISD::UMULO)
15706 Cond = X86Op.getValue(2);
15708 Cond = X86Op.getValue(1);
15710 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15714 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15715 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15716 if (CondOpc == ISD::OR) {
15717 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15718 // two branches instead of an explicit OR instruction with a
15720 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15721 isX86LogicalCmp(Cmp)) {
15722 CC = Cond.getOperand(0).getOperand(0);
15723 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15724 Chain, Dest, CC, Cmp);
15725 CC = Cond.getOperand(1).getOperand(0);
15729 } else { // ISD::AND
15730 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15731 // two branches instead of an explicit AND instruction with a
15732 // separate test. However, we only do this if this block doesn't
15733 // have a fall-through edge, because this requires an explicit
15734 // jmp when the condition is false.
15735 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15736 isX86LogicalCmp(Cmp) &&
15737 Op.getNode()->hasOneUse()) {
15738 X86::CondCode CCode =
15739 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15740 CCode = X86::GetOppositeBranchCondition(CCode);
15741 CC = DAG.getConstant(CCode, dl, MVT::i8);
15742 SDNode *User = *Op.getNode()->use_begin();
15743 // Look for an unconditional branch following this conditional branch.
15744 // We need this because we need to reverse the successors in order
15745 // to implement FCMP_OEQ.
15746 if (User->getOpcode() == ISD::BR) {
15747 SDValue FalseBB = User->getOperand(1);
15749 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15750 assert(NewBR == User);
15754 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15755 Chain, Dest, CC, Cmp);
15756 X86::CondCode CCode =
15757 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15758 CCode = X86::GetOppositeBranchCondition(CCode);
15759 CC = DAG.getConstant(CCode, dl, MVT::i8);
15765 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15766 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15767 // It should be transformed during dag combiner except when the condition
15768 // is set by a arithmetics with overflow node.
15769 X86::CondCode CCode =
15770 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15771 CCode = X86::GetOppositeBranchCondition(CCode);
15772 CC = DAG.getConstant(CCode, dl, MVT::i8);
15773 Cond = Cond.getOperand(0).getOperand(1);
15775 } else if (Cond.getOpcode() == ISD::SETCC &&
15776 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15777 // For FCMP_OEQ, we can emit
15778 // two branches instead of an explicit AND instruction with a
15779 // separate test. However, we only do this if this block doesn't
15780 // have a fall-through edge, because this requires an explicit
15781 // jmp when the condition is false.
15782 if (Op.getNode()->hasOneUse()) {
15783 SDNode *User = *Op.getNode()->use_begin();
15784 // Look for an unconditional branch following this conditional branch.
15785 // We need this because we need to reverse the successors in order
15786 // to implement FCMP_OEQ.
15787 if (User->getOpcode() == ISD::BR) {
15788 SDValue FalseBB = User->getOperand(1);
15790 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15791 assert(NewBR == User);
15795 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15796 Cond.getOperand(0), Cond.getOperand(1));
15797 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15798 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15799 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15800 Chain, Dest, CC, Cmp);
15801 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15806 } else if (Cond.getOpcode() == ISD::SETCC &&
15807 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15808 // For FCMP_UNE, we can emit
15809 // two branches instead of an explicit AND instruction with a
15810 // separate test. However, we only do this if this block doesn't
15811 // have a fall-through edge, because this requires an explicit
15812 // jmp when the condition is false.
15813 if (Op.getNode()->hasOneUse()) {
15814 SDNode *User = *Op.getNode()->use_begin();
15815 // Look for an unconditional branch following this conditional branch.
15816 // We need this because we need to reverse the successors in order
15817 // to implement FCMP_UNE.
15818 if (User->getOpcode() == ISD::BR) {
15819 SDValue FalseBB = User->getOperand(1);
15821 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15822 assert(NewBR == User);
15825 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15826 Cond.getOperand(0), Cond.getOperand(1));
15827 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15828 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15829 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15830 Chain, Dest, CC, Cmp);
15831 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15841 // Look pass the truncate if the high bits are known zero.
15842 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15843 Cond = Cond.getOperand(0);
15845 // We know the result of AND is compared against zero. Try to match
15847 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15848 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
15849 CC = NewSetCC.getOperand(0);
15850 Cond = NewSetCC.getOperand(1);
15857 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15858 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15859 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15861 Cond = ConvertCmpIfNecessary(Cond, DAG);
15862 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15863 Chain, Dest, CC, Cond);
15866 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15867 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15868 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15869 // that the guard pages used by the OS virtual memory manager are allocated in
15870 // correct sequence.
15872 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15873 SelectionDAG &DAG) const {
15874 MachineFunction &MF = DAG.getMachineFunction();
15875 bool SplitStack = MF.shouldSplitStack();
15876 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15881 SDNode *Node = Op.getNode();
15882 SDValue Chain = Op.getOperand(0);
15883 SDValue Size = Op.getOperand(1);
15884 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15885 EVT VT = Node->getValueType(0);
15887 // Chain the dynamic stack allocation so that it doesn't modify the stack
15888 // pointer when other instructions are using the stack.
15889 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
15891 bool Is64Bit = Subtarget->is64Bit();
15892 MVT SPTy = getPointerTy(DAG.getDataLayout());
15896 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15897 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15898 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15899 " not tell us which reg is the stack pointer!");
15900 EVT VT = Node->getValueType(0);
15901 SDValue Tmp3 = Node->getOperand(2);
15903 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15904 Chain = SP.getValue(1);
15905 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15906 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15907 unsigned StackAlign = TFI.getStackAlignment();
15908 Result = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15909 if (Align > StackAlign)
15910 Result = DAG.getNode(ISD::AND, dl, VT, Result,
15911 DAG.getConstant(-(uint64_t)Align, dl, VT));
15912 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Result); // Output chain
15913 } else if (SplitStack) {
15914 MachineRegisterInfo &MRI = MF.getRegInfo();
15917 // The 64 bit implementation of segmented stacks needs to clobber both r10
15918 // r11. This makes it impossible to use it along with nested parameters.
15919 const Function *F = MF.getFunction();
15921 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15923 if (I->hasNestAttr())
15924 report_fatal_error("Cannot use segmented stacks with functions that "
15925 "have nested arguments.");
15928 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15929 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15930 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15931 Result = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15932 DAG.getRegister(Vreg, SPTy));
15935 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15937 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15938 Flag = Chain.getValue(1);
15939 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15941 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15943 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15944 unsigned SPReg = RegInfo->getStackRegister();
15945 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15946 Chain = SP.getValue(1);
15949 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15950 DAG.getConstant(-(uint64_t)Align, dl, VT));
15951 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15957 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15958 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
15960 SDValue Ops[2] = {Result, Chain};
15961 return DAG.getMergeValues(Ops, dl);
15964 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15965 MachineFunction &MF = DAG.getMachineFunction();
15966 auto PtrVT = getPointerTy(MF.getDataLayout());
15967 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15969 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15972 if (!Subtarget->is64Bit() ||
15973 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15974 // vastart just stores the address of the VarArgsFrameIndex slot into the
15975 // memory location argument.
15976 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15977 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15978 MachinePointerInfo(SV), false, false, 0);
15982 // gp_offset (0 - 6 * 8)
15983 // fp_offset (48 - 48 + 8 * 16)
15984 // overflow_arg_area (point to parameters coming in memory).
15986 SmallVector<SDValue, 8> MemOps;
15987 SDValue FIN = Op.getOperand(1);
15989 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15990 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15992 FIN, MachinePointerInfo(SV), false, false, 0);
15993 MemOps.push_back(Store);
15996 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15997 Store = DAG.getStore(Op.getOperand(0), DL,
15998 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
16000 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16001 MemOps.push_back(Store);
16003 // Store ptr to overflow_arg_area
16004 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
16005 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
16006 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16007 MachinePointerInfo(SV, 8),
16009 MemOps.push_back(Store);
16011 // Store ptr to reg_save_area.
16012 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
16013 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
16014 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
16015 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
16016 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
16017 MemOps.push_back(Store);
16018 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16021 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16022 assert(Subtarget->is64Bit() &&
16023 "LowerVAARG only handles 64-bit va_arg!");
16024 assert(Op.getNode()->getNumOperands() == 4);
16026 MachineFunction &MF = DAG.getMachineFunction();
16027 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
16028 // The Win64 ABI uses char* instead of a structure.
16029 return DAG.expandVAArg(Op.getNode());
16031 SDValue Chain = Op.getOperand(0);
16032 SDValue SrcPtr = Op.getOperand(1);
16033 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16034 unsigned Align = Op.getConstantOperandVal(3);
16037 EVT ArgVT = Op.getNode()->getValueType(0);
16038 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16039 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
16042 // Decide which area this value should be read from.
16043 // TODO: Implement the AMD64 ABI in its entirety. This simple
16044 // selection mechanism works only for the basic types.
16045 if (ArgVT == MVT::f80) {
16046 llvm_unreachable("va_arg for f80 not yet implemented");
16047 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16048 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16049 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16050 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16052 llvm_unreachable("Unhandled argument type in LowerVAARG");
16055 if (ArgMode == 2) {
16056 // Sanity Check: Make sure using fp_offset makes sense.
16057 assert(!Subtarget->useSoftFloat() &&
16058 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
16059 Subtarget->hasSSE1());
16062 // Insert VAARG_64 node into the DAG
16063 // VAARG_64 returns two values: Variable Argument Address, Chain
16064 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
16065 DAG.getConstant(ArgMode, dl, MVT::i8),
16066 DAG.getConstant(Align, dl, MVT::i32)};
16067 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
16068 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16069 VTs, InstOps, MVT::i64,
16070 MachinePointerInfo(SV),
16072 /*Volatile=*/false,
16074 /*WriteMem=*/true);
16075 Chain = VAARG.getValue(1);
16077 // Load the next argument and return it
16078 return DAG.getLoad(ArgVT, dl,
16081 MachinePointerInfo(),
16082 false, false, false, 0);
16085 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16086 SelectionDAG &DAG) {
16087 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
16088 // where a va_list is still an i8*.
16089 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16090 if (Subtarget->isCallingConvWin64(
16091 DAG.getMachineFunction().getFunction()->getCallingConv()))
16092 // Probably a Win64 va_copy.
16093 return DAG.expandVACopy(Op.getNode());
16095 SDValue Chain = Op.getOperand(0);
16096 SDValue DstPtr = Op.getOperand(1);
16097 SDValue SrcPtr = Op.getOperand(2);
16098 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16099 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16102 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16103 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
16105 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16108 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16109 // amount is a constant. Takes immediate version of shift as input.
16110 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16111 SDValue SrcOp, uint64_t ShiftAmt,
16112 SelectionDAG &DAG) {
16113 MVT ElementType = VT.getVectorElementType();
16115 // Fold this packed shift into its first operand if ShiftAmt is 0.
16119 // Check for ShiftAmt >= element width
16120 if (ShiftAmt >= ElementType.getSizeInBits()) {
16121 if (Opc == X86ISD::VSRAI)
16122 ShiftAmt = ElementType.getSizeInBits() - 1;
16124 return DAG.getConstant(0, dl, VT);
16127 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16128 && "Unknown target vector shift-by-constant node");
16130 // Fold this packed vector shift into a build vector if SrcOp is a
16131 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16132 if (VT == SrcOp.getSimpleValueType() &&
16133 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16134 SmallVector<SDValue, 8> Elts;
16135 unsigned NumElts = SrcOp->getNumOperands();
16136 ConstantSDNode *ND;
16139 default: llvm_unreachable(nullptr);
16140 case X86ISD::VSHLI:
16141 for (unsigned i=0; i!=NumElts; ++i) {
16142 SDValue CurrentOp = SrcOp->getOperand(i);
16143 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16144 Elts.push_back(CurrentOp);
16147 ND = cast<ConstantSDNode>(CurrentOp);
16148 const APInt &C = ND->getAPIntValue();
16149 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
16152 case X86ISD::VSRLI:
16153 for (unsigned i=0; i!=NumElts; ++i) {
16154 SDValue CurrentOp = SrcOp->getOperand(i);
16155 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16156 Elts.push_back(CurrentOp);
16159 ND = cast<ConstantSDNode>(CurrentOp);
16160 const APInt &C = ND->getAPIntValue();
16161 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
16164 case X86ISD::VSRAI:
16165 for (unsigned i=0; i!=NumElts; ++i) {
16166 SDValue CurrentOp = SrcOp->getOperand(i);
16167 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16168 Elts.push_back(CurrentOp);
16171 ND = cast<ConstantSDNode>(CurrentOp);
16172 const APInt &C = ND->getAPIntValue();
16173 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
16178 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16181 return DAG.getNode(Opc, dl, VT, SrcOp,
16182 DAG.getConstant(ShiftAmt, dl, MVT::i8));
16185 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16186 // may or may not be a constant. Takes immediate version of shift as input.
16187 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16188 SDValue SrcOp, SDValue ShAmt,
16189 SelectionDAG &DAG) {
16190 MVT SVT = ShAmt.getSimpleValueType();
16191 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16193 // Catch shift-by-constant.
16194 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16195 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16196 CShAmt->getZExtValue(), DAG);
16198 // Change opcode to non-immediate version
16200 default: llvm_unreachable("Unknown target vector shift node");
16201 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16202 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16203 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16206 const X86Subtarget &Subtarget =
16207 static_cast<const X86Subtarget &>(DAG.getSubtarget());
16208 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16209 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16210 // Let the shuffle legalizer expand this shift amount node.
16211 SDValue Op0 = ShAmt.getOperand(0);
16212 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16213 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16215 // Need to build a vector containing shift amount.
16216 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16217 SmallVector<SDValue, 4> ShOps;
16218 ShOps.push_back(ShAmt);
16219 if (SVT == MVT::i32) {
16220 ShOps.push_back(DAG.getConstant(0, dl, SVT));
16221 ShOps.push_back(DAG.getUNDEF(SVT));
16223 ShOps.push_back(DAG.getUNDEF(SVT));
16225 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16226 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16229 // The return type has to be a 128-bit type with the same element
16230 // type as the input type.
16231 MVT EltVT = VT.getVectorElementType();
16232 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16234 ShAmt = DAG.getBitcast(ShVT, ShAmt);
16235 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16238 /// \brief Return Mask with the necessary casting or extending
16239 /// for \p Mask according to \p MaskVT when lowering masking intrinsics
16240 static SDValue getMaskNode(SDValue Mask, MVT MaskVT,
16241 const X86Subtarget *Subtarget,
16242 SelectionDAG &DAG, SDLoc dl) {
16244 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
16245 // Mask should be extended
16246 Mask = DAG.getNode(ISD::ANY_EXTEND, dl,
16247 MVT::getIntegerVT(MaskVT.getSizeInBits()), Mask);
16250 if (Mask.getSimpleValueType() == MVT::i64 && Subtarget->is32Bit()) {
16251 if (MaskVT == MVT::v64i1) {
16252 assert(Subtarget->hasBWI() && "Expected AVX512BW target!");
16253 // In case 32bit mode, bitcast i64 is illegal, extend/split it.
16255 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16256 DAG.getConstant(0, dl, MVT::i32));
16257 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16258 DAG.getConstant(1, dl, MVT::i32));
16260 Lo = DAG.getBitcast(MVT::v32i1, Lo);
16261 Hi = DAG.getBitcast(MVT::v32i1, Hi);
16263 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi);
16265 // MaskVT require < 64bit. Truncate mask (should succeed in any case),
16267 MVT TruncVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
16268 return DAG.getBitcast(MaskVT,
16269 DAG.getNode(ISD::TRUNCATE, dl, TruncVT, Mask));
16273 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16274 Mask.getSimpleValueType().getSizeInBits());
16275 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16276 // are extracted by EXTRACT_SUBVECTOR.
16277 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16278 DAG.getBitcast(BitcastVT, Mask),
16279 DAG.getIntPtrConstant(0, dl));
16283 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16284 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16285 /// necessary casting or extending for \p Mask when lowering masking intrinsics
16286 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16287 SDValue PreservedSrc,
16288 const X86Subtarget *Subtarget,
16289 SelectionDAG &DAG) {
16290 MVT VT = Op.getSimpleValueType();
16291 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16292 unsigned OpcodeSelect = ISD::VSELECT;
16295 if (isAllOnesConstant(Mask))
16298 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16300 switch (Op.getOpcode()) {
16302 case X86ISD::PCMPEQM:
16303 case X86ISD::PCMPGTM:
16305 case X86ISD::CMPMU:
16306 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16307 case X86ISD::VFPCLASS:
16308 case X86ISD::VFPCLASSS:
16309 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
16310 case X86ISD::VTRUNC:
16311 case X86ISD::VTRUNCS:
16312 case X86ISD::VTRUNCUS:
16313 // We can't use ISD::VSELECT here because it is not always "Legal"
16314 // for the destination type. For example vpmovqb require only AVX512
16315 // and vselect that can operate on byte element type require BWI
16316 OpcodeSelect = X86ISD::SELECT;
16319 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16320 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16321 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
16324 /// \brief Creates an SDNode for a predicated scalar operation.
16325 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16326 /// The mask is coming as MVT::i8 and it should be truncated
16327 /// to MVT::i1 while lowering masking intrinsics.
16328 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16329 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16330 /// for a scalar instruction.
16331 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16332 SDValue PreservedSrc,
16333 const X86Subtarget *Subtarget,
16334 SelectionDAG &DAG) {
16335 if (isAllOnesConstant(Mask))
16338 MVT VT = Op.getSimpleValueType();
16340 // The mask should be of type MVT::i1
16341 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16343 if (Op.getOpcode() == X86ISD::FSETCC)
16344 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16345 if (Op.getOpcode() == X86ISD::VFPCLASS ||
16346 Op.getOpcode() == X86ISD::VFPCLASSS)
16347 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16349 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16350 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16351 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16354 static int getSEHRegistrationNodeSize(const Function *Fn) {
16355 if (!Fn->hasPersonalityFn())
16356 report_fatal_error(
16357 "querying registration node size for function without personality");
16358 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16359 // WinEHStatePass for the full struct definition.
16360 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16361 case EHPersonality::MSVC_X86SEH: return 24;
16362 case EHPersonality::MSVC_CXX: return 16;
16365 report_fatal_error(
16366 "can only recover FP for 32-bit MSVC EH personality functions");
16369 /// When the MSVC runtime transfers control to us, either to an outlined
16370 /// function or when returning to a parent frame after catching an exception, we
16371 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16372 /// Here's the math:
16373 /// RegNodeBase = EntryEBP - RegNodeSize
16374 /// ParentFP = RegNodeBase - ParentFrameOffset
16375 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16376 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16377 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16378 SDValue EntryEBP) {
16379 MachineFunction &MF = DAG.getMachineFunction();
16382 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16383 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16385 // It's possible that the parent function no longer has a personality function
16386 // if the exceptional code was optimized away, in which case we just return
16387 // the incoming EBP.
16388 if (!Fn->hasPersonalityFn())
16391 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16392 // registration, or the .set_setframe offset.
16393 MCSymbol *OffsetSym =
16394 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16395 GlobalValue::getRealLinkageName(Fn->getName()));
16396 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16397 SDValue ParentFrameOffset =
16398 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16400 // Return EntryEBP + ParentFrameOffset for x64. This adjusts from RSP after
16401 // prologue to RBP in the parent function.
16402 const X86Subtarget &Subtarget =
16403 static_cast<const X86Subtarget &>(DAG.getSubtarget());
16404 if (Subtarget.is64Bit())
16405 return DAG.getNode(ISD::ADD, dl, PtrVT, EntryEBP, ParentFrameOffset);
16407 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16408 // RegNodeBase = EntryEBP - RegNodeSize
16409 // ParentFP = RegNodeBase - ParentFrameOffset
16410 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16411 DAG.getConstant(RegNodeSize, dl, PtrVT));
16412 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, ParentFrameOffset);
16415 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16416 SelectionDAG &DAG) {
16418 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16419 MVT VT = Op.getSimpleValueType();
16420 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16422 switch(IntrData->Type) {
16423 case INTR_TYPE_1OP:
16424 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16425 case INTR_TYPE_2OP:
16426 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16428 case INTR_TYPE_2OP_IMM8:
16429 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16430 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16431 case INTR_TYPE_3OP:
16432 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16433 Op.getOperand(2), Op.getOperand(3));
16434 case INTR_TYPE_4OP:
16435 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16436 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16437 case INTR_TYPE_1OP_MASK_RM: {
16438 SDValue Src = Op.getOperand(1);
16439 SDValue PassThru = Op.getOperand(2);
16440 SDValue Mask = Op.getOperand(3);
16441 SDValue RoundingMode;
16442 // We allways add rounding mode to the Node.
16443 // If the rounding mode is not specified, we add the
16444 // "current direction" mode.
16445 if (Op.getNumOperands() == 4)
16447 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16449 RoundingMode = Op.getOperand(4);
16450 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16451 if (IntrWithRoundingModeOpcode != 0)
16452 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16453 X86::STATIC_ROUNDING::CUR_DIRECTION)
16454 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16455 dl, Op.getValueType(), Src, RoundingMode),
16456 Mask, PassThru, Subtarget, DAG);
16457 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16459 Mask, PassThru, Subtarget, DAG);
16461 case INTR_TYPE_1OP_MASK: {
16462 SDValue Src = Op.getOperand(1);
16463 SDValue PassThru = Op.getOperand(2);
16464 SDValue Mask = Op.getOperand(3);
16465 // We add rounding mode to the Node when
16466 // - RM Opcode is specified and
16467 // - RM is not "current direction".
16468 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16469 if (IntrWithRoundingModeOpcode != 0) {
16470 SDValue Rnd = Op.getOperand(4);
16471 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16472 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16473 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16474 dl, Op.getValueType(),
16476 Mask, PassThru, Subtarget, DAG);
16479 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16480 Mask, PassThru, Subtarget, DAG);
16482 case INTR_TYPE_SCALAR_MASK: {
16483 SDValue Src1 = Op.getOperand(1);
16484 SDValue Src2 = Op.getOperand(2);
16485 SDValue passThru = Op.getOperand(3);
16486 SDValue Mask = Op.getOperand(4);
16487 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16488 Mask, passThru, Subtarget, DAG);
16490 case INTR_TYPE_SCALAR_MASK_RM: {
16491 SDValue Src1 = Op.getOperand(1);
16492 SDValue Src2 = Op.getOperand(2);
16493 SDValue Src0 = Op.getOperand(3);
16494 SDValue Mask = Op.getOperand(4);
16495 // There are 2 kinds of intrinsics in this group:
16496 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16497 // (2) With rounding mode and sae - 7 operands.
16498 if (Op.getNumOperands() == 6) {
16499 SDValue Sae = Op.getOperand(5);
16500 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16501 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16503 Mask, Src0, Subtarget, DAG);
16505 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16506 SDValue RoundingMode = Op.getOperand(5);
16507 SDValue Sae = Op.getOperand(6);
16508 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16509 RoundingMode, Sae),
16510 Mask, Src0, Subtarget, DAG);
16512 case INTR_TYPE_2OP_MASK:
16513 case INTR_TYPE_2OP_IMM8_MASK: {
16514 SDValue Src1 = Op.getOperand(1);
16515 SDValue Src2 = Op.getOperand(2);
16516 SDValue PassThru = Op.getOperand(3);
16517 SDValue Mask = Op.getOperand(4);
16519 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16520 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16522 // We specify 2 possible opcodes for intrinsics with rounding modes.
16523 // First, we check if the intrinsic may have non-default rounding mode,
16524 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16525 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16526 if (IntrWithRoundingModeOpcode != 0) {
16527 SDValue Rnd = Op.getOperand(5);
16528 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16529 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16530 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16531 dl, Op.getValueType(),
16533 Mask, PassThru, Subtarget, DAG);
16536 // TODO: Intrinsics should have fast-math-flags to propagate.
16537 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16538 Mask, PassThru, Subtarget, DAG);
16540 case INTR_TYPE_2OP_MASK_RM: {
16541 SDValue Src1 = Op.getOperand(1);
16542 SDValue Src2 = Op.getOperand(2);
16543 SDValue PassThru = Op.getOperand(3);
16544 SDValue Mask = Op.getOperand(4);
16545 // We specify 2 possible modes for intrinsics, with/without rounding
16547 // First, we check if the intrinsic have rounding mode (6 operands),
16548 // if not, we set rounding mode to "current".
16550 if (Op.getNumOperands() == 6)
16551 Rnd = Op.getOperand(5);
16553 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16554 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16556 Mask, PassThru, Subtarget, DAG);
16558 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16559 SDValue Src1 = Op.getOperand(1);
16560 SDValue Src2 = Op.getOperand(2);
16561 SDValue Src3 = Op.getOperand(3);
16562 SDValue PassThru = Op.getOperand(4);
16563 SDValue Mask = Op.getOperand(5);
16564 SDValue Sae = Op.getOperand(6);
16566 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16568 Mask, PassThru, Subtarget, DAG);
16570 case INTR_TYPE_3OP_MASK_RM: {
16571 SDValue Src1 = Op.getOperand(1);
16572 SDValue Src2 = Op.getOperand(2);
16573 SDValue Imm = Op.getOperand(3);
16574 SDValue PassThru = Op.getOperand(4);
16575 SDValue Mask = Op.getOperand(5);
16576 // We specify 2 possible modes for intrinsics, with/without rounding
16578 // First, we check if the intrinsic have rounding mode (7 operands),
16579 // if not, we set rounding mode to "current".
16581 if (Op.getNumOperands() == 7)
16582 Rnd = Op.getOperand(6);
16584 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16585 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16586 Src1, Src2, Imm, Rnd),
16587 Mask, PassThru, Subtarget, DAG);
16589 case INTR_TYPE_3OP_IMM8_MASK:
16590 case INTR_TYPE_3OP_MASK:
16591 case INSERT_SUBVEC: {
16592 SDValue Src1 = Op.getOperand(1);
16593 SDValue Src2 = Op.getOperand(2);
16594 SDValue Src3 = Op.getOperand(3);
16595 SDValue PassThru = Op.getOperand(4);
16596 SDValue Mask = Op.getOperand(5);
16598 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16599 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16600 else if (IntrData->Type == INSERT_SUBVEC) {
16601 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16602 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16603 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16604 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16605 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16608 // We specify 2 possible opcodes for intrinsics with rounding modes.
16609 // First, we check if the intrinsic may have non-default rounding mode,
16610 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16611 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16612 if (IntrWithRoundingModeOpcode != 0) {
16613 SDValue Rnd = Op.getOperand(6);
16614 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16615 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16616 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16617 dl, Op.getValueType(),
16618 Src1, Src2, Src3, Rnd),
16619 Mask, PassThru, Subtarget, DAG);
16622 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16624 Mask, PassThru, Subtarget, DAG);
16626 case VPERM_3OP_MASKZ:
16627 case VPERM_3OP_MASK:{
16628 // Src2 is the PassThru
16629 SDValue Src1 = Op.getOperand(1);
16630 SDValue Src2 = Op.getOperand(2);
16631 SDValue Src3 = Op.getOperand(3);
16632 SDValue Mask = Op.getOperand(4);
16633 MVT VT = Op.getSimpleValueType();
16634 SDValue PassThru = SDValue();
16636 // set PassThru element
16637 if (IntrData->Type == VPERM_3OP_MASKZ)
16638 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16640 PassThru = DAG.getBitcast(VT, Src2);
16642 // Swap Src1 and Src2 in the node creation
16643 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16644 dl, Op.getValueType(),
16646 Mask, PassThru, Subtarget, DAG);
16650 case FMA_OP_MASK: {
16651 SDValue Src1 = Op.getOperand(1);
16652 SDValue Src2 = Op.getOperand(2);
16653 SDValue Src3 = Op.getOperand(3);
16654 SDValue Mask = Op.getOperand(4);
16655 MVT VT = Op.getSimpleValueType();
16656 SDValue PassThru = SDValue();
16658 // set PassThru element
16659 if (IntrData->Type == FMA_OP_MASKZ)
16660 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16661 else if (IntrData->Type == FMA_OP_MASK3)
16666 // We specify 2 possible opcodes for intrinsics with rounding modes.
16667 // First, we check if the intrinsic may have non-default rounding mode,
16668 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16669 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16670 if (IntrWithRoundingModeOpcode != 0) {
16671 SDValue Rnd = Op.getOperand(5);
16672 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16673 X86::STATIC_ROUNDING::CUR_DIRECTION)
16674 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16675 dl, Op.getValueType(),
16676 Src1, Src2, Src3, Rnd),
16677 Mask, PassThru, Subtarget, DAG);
16679 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16680 dl, Op.getValueType(),
16682 Mask, PassThru, Subtarget, DAG);
16684 case TERLOG_OP_MASK:
16685 case TERLOG_OP_MASKZ: {
16686 SDValue Src1 = Op.getOperand(1);
16687 SDValue Src2 = Op.getOperand(2);
16688 SDValue Src3 = Op.getOperand(3);
16689 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16690 SDValue Mask = Op.getOperand(5);
16691 MVT VT = Op.getSimpleValueType();
16692 SDValue PassThru = Src1;
16693 // Set PassThru element.
16694 if (IntrData->Type == TERLOG_OP_MASKZ)
16695 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16697 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16698 Src1, Src2, Src3, Src4),
16699 Mask, PassThru, Subtarget, DAG);
16702 // FPclass intrinsics with mask
16703 SDValue Src1 = Op.getOperand(1);
16704 MVT VT = Src1.getSimpleValueType();
16705 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16706 SDValue Imm = Op.getOperand(2);
16707 SDValue Mask = Op.getOperand(3);
16708 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16709 Mask.getSimpleValueType().getSizeInBits());
16710 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16711 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16712 DAG.getTargetConstant(0, dl, MaskVT),
16714 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16715 DAG.getUNDEF(BitcastVT), FPclassMask,
16716 DAG.getIntPtrConstant(0, dl));
16717 return DAG.getBitcast(Op.getValueType(), Res);
16720 SDValue Src1 = Op.getOperand(1);
16721 SDValue Imm = Op.getOperand(2);
16722 SDValue Mask = Op.getOperand(3);
16723 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16724 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16725 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16726 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16729 case CMP_MASK_CC: {
16730 // Comparison intrinsics with masks.
16731 // Example of transformation:
16732 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16733 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16735 // (v8i1 (insert_subvector undef,
16736 // (v2i1 (and (PCMPEQM %a, %b),
16737 // (extract_subvector
16738 // (v8i1 (bitcast %mask)), 0))), 0))))
16739 MVT VT = Op.getOperand(1).getSimpleValueType();
16740 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16741 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16742 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16743 Mask.getSimpleValueType().getSizeInBits());
16745 if (IntrData->Type == CMP_MASK_CC) {
16746 SDValue CC = Op.getOperand(3);
16747 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16748 // We specify 2 possible opcodes for intrinsics with rounding modes.
16749 // First, we check if the intrinsic may have non-default rounding mode,
16750 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16751 if (IntrData->Opc1 != 0) {
16752 SDValue Rnd = Op.getOperand(5);
16753 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16754 X86::STATIC_ROUNDING::CUR_DIRECTION)
16755 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16756 Op.getOperand(2), CC, Rnd);
16758 //default rounding mode
16760 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16761 Op.getOperand(2), CC);
16764 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16765 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16768 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16769 DAG.getTargetConstant(0, dl,
16772 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16773 DAG.getUNDEF(BitcastVT), CmpMask,
16774 DAG.getIntPtrConstant(0, dl));
16775 return DAG.getBitcast(Op.getValueType(), Res);
16777 case CMP_MASK_SCALAR_CC: {
16778 SDValue Src1 = Op.getOperand(1);
16779 SDValue Src2 = Op.getOperand(2);
16780 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16781 SDValue Mask = Op.getOperand(4);
16784 if (IntrData->Opc1 != 0) {
16785 SDValue Rnd = Op.getOperand(5);
16786 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16787 X86::STATIC_ROUNDING::CUR_DIRECTION)
16788 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16790 //default rounding mode
16792 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16794 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16795 DAG.getTargetConstant(0, dl,
16799 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16800 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16801 DAG.getValueType(MVT::i1));
16803 case COMI: { // Comparison intrinsics
16804 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16805 SDValue LHS = Op.getOperand(1);
16806 SDValue RHS = Op.getOperand(2);
16807 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16808 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16809 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16810 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16811 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16812 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16814 case COMI_RM: { // Comparison intrinsics with Sae
16815 SDValue LHS = Op.getOperand(1);
16816 SDValue RHS = Op.getOperand(2);
16817 SDValue CC = Op.getOperand(3);
16818 SDValue Sae = Op.getOperand(4);
16819 auto ComiType = TranslateX86ConstCondToX86CC(CC);
16820 // choose between ordered and unordered (comi/ucomi)
16821 unsigned comiOp = std::get<0>(ComiType) ? IntrData->Opc0 : IntrData->Opc1;
16823 if (cast<ConstantSDNode>(Sae)->getZExtValue() !=
16824 X86::STATIC_ROUNDING::CUR_DIRECTION)
16825 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS, Sae);
16827 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS);
16828 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16829 DAG.getConstant(std::get<1>(ComiType), dl, MVT::i8), Cond);
16830 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16833 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16834 Op.getOperand(1), Op.getOperand(2), DAG);
16836 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16837 Op.getSimpleValueType(),
16839 Op.getOperand(2), DAG),
16840 Op.getOperand(4), Op.getOperand(3), Subtarget,
16842 case COMPRESS_EXPAND_IN_REG: {
16843 SDValue Mask = Op.getOperand(3);
16844 SDValue DataToCompress = Op.getOperand(1);
16845 SDValue PassThru = Op.getOperand(2);
16846 if (isAllOnesConstant(Mask)) // return data as is
16847 return Op.getOperand(1);
16849 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16851 Mask, PassThru, Subtarget, DAG);
16854 SDValue Mask = Op.getOperand(1);
16855 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16856 Mask.getSimpleValueType().getSizeInBits());
16857 Mask = DAG.getBitcast(MaskVT, Mask);
16858 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Mask);
16861 SDValue Mask = Op.getOperand(3);
16862 MVT VT = Op.getSimpleValueType();
16863 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16864 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16865 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16869 MVT VT = Op.getSimpleValueType();
16870 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getSizeInBits()/2);
16872 SDValue Src1 = getMaskNode(Op.getOperand(1), MaskVT, Subtarget, DAG, dl);
16873 SDValue Src2 = getMaskNode(Op.getOperand(2), MaskVT, Subtarget, DAG, dl);
16874 // Arguments should be swapped.
16875 SDValue Res = DAG.getNode(IntrData->Opc0, dl,
16876 MVT::getVectorVT(MVT::i1, VT.getSizeInBits()),
16878 return DAG.getBitcast(VT, Res);
16880 case CONVERT_TO_MASK: {
16881 MVT SrcVT = Op.getOperand(1).getSimpleValueType();
16882 MVT MaskVT = MVT::getVectorVT(MVT::i1, SrcVT.getVectorNumElements());
16883 MVT BitcastVT = MVT::getVectorVT(MVT::i1, VT.getSizeInBits());
16885 SDValue CvtMask = DAG.getNode(IntrData->Opc0, dl, MaskVT,
16887 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16888 DAG.getUNDEF(BitcastVT), CvtMask,
16889 DAG.getIntPtrConstant(0, dl));
16890 return DAG.getBitcast(Op.getValueType(), Res);
16892 case CONVERT_MASK_TO_VEC: {
16893 SDValue Mask = Op.getOperand(1);
16894 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16895 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16896 return DAG.getNode(IntrData->Opc0, dl, VT, VMask);
16898 case BRCST_SUBVEC_TO_VEC: {
16899 SDValue Src = Op.getOperand(1);
16900 SDValue Passthru = Op.getOperand(2);
16901 SDValue Mask = Op.getOperand(3);
16902 EVT resVT = Passthru.getValueType();
16903 SDValue subVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, resVT,
16904 DAG.getUNDEF(resVT), Src,
16905 DAG.getIntPtrConstant(0, dl));
16907 if (Src.getSimpleValueType().is256BitVector() && resVT.is512BitVector())
16908 immVal = DAG.getConstant(0x44, dl, MVT::i8);
16910 immVal = DAG.getConstant(0, dl, MVT::i8);
16911 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16912 subVec, subVec, immVal),
16913 Mask, Passthru, Subtarget, DAG);
16921 default: return SDValue(); // Don't custom lower most intrinsics.
16923 case Intrinsic::x86_avx2_permd:
16924 case Intrinsic::x86_avx2_permps:
16925 // Operands intentionally swapped. Mask is last operand to intrinsic,
16926 // but second operand for node/instruction.
16927 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16928 Op.getOperand(2), Op.getOperand(1));
16930 // ptest and testp intrinsics. The intrinsic these come from are designed to
16931 // return an integer value, not just an instruction so lower it to the ptest
16932 // or testp pattern and a setcc for the result.
16933 case Intrinsic::x86_sse41_ptestz:
16934 case Intrinsic::x86_sse41_ptestc:
16935 case Intrinsic::x86_sse41_ptestnzc:
16936 case Intrinsic::x86_avx_ptestz_256:
16937 case Intrinsic::x86_avx_ptestc_256:
16938 case Intrinsic::x86_avx_ptestnzc_256:
16939 case Intrinsic::x86_avx_vtestz_ps:
16940 case Intrinsic::x86_avx_vtestc_ps:
16941 case Intrinsic::x86_avx_vtestnzc_ps:
16942 case Intrinsic::x86_avx_vtestz_pd:
16943 case Intrinsic::x86_avx_vtestc_pd:
16944 case Intrinsic::x86_avx_vtestnzc_pd:
16945 case Intrinsic::x86_avx_vtestz_ps_256:
16946 case Intrinsic::x86_avx_vtestc_ps_256:
16947 case Intrinsic::x86_avx_vtestnzc_ps_256:
16948 case Intrinsic::x86_avx_vtestz_pd_256:
16949 case Intrinsic::x86_avx_vtestc_pd_256:
16950 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16951 bool IsTestPacked = false;
16954 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16955 case Intrinsic::x86_avx_vtestz_ps:
16956 case Intrinsic::x86_avx_vtestz_pd:
16957 case Intrinsic::x86_avx_vtestz_ps_256:
16958 case Intrinsic::x86_avx_vtestz_pd_256:
16959 IsTestPacked = true; // Fallthrough
16960 case Intrinsic::x86_sse41_ptestz:
16961 case Intrinsic::x86_avx_ptestz_256:
16963 X86CC = X86::COND_E;
16965 case Intrinsic::x86_avx_vtestc_ps:
16966 case Intrinsic::x86_avx_vtestc_pd:
16967 case Intrinsic::x86_avx_vtestc_ps_256:
16968 case Intrinsic::x86_avx_vtestc_pd_256:
16969 IsTestPacked = true; // Fallthrough
16970 case Intrinsic::x86_sse41_ptestc:
16971 case Intrinsic::x86_avx_ptestc_256:
16973 X86CC = X86::COND_B;
16975 case Intrinsic::x86_avx_vtestnzc_ps:
16976 case Intrinsic::x86_avx_vtestnzc_pd:
16977 case Intrinsic::x86_avx_vtestnzc_ps_256:
16978 case Intrinsic::x86_avx_vtestnzc_pd_256:
16979 IsTestPacked = true; // Fallthrough
16980 case Intrinsic::x86_sse41_ptestnzc:
16981 case Intrinsic::x86_avx_ptestnzc_256:
16983 X86CC = X86::COND_A;
16987 SDValue LHS = Op.getOperand(1);
16988 SDValue RHS = Op.getOperand(2);
16989 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16990 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16991 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16992 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16993 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16995 case Intrinsic::x86_avx512_kortestz_w:
16996 case Intrinsic::x86_avx512_kortestc_w: {
16997 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16998 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16999 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
17000 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
17001 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17002 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17003 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17006 case Intrinsic::x86_sse42_pcmpistria128:
17007 case Intrinsic::x86_sse42_pcmpestria128:
17008 case Intrinsic::x86_sse42_pcmpistric128:
17009 case Intrinsic::x86_sse42_pcmpestric128:
17010 case Intrinsic::x86_sse42_pcmpistrio128:
17011 case Intrinsic::x86_sse42_pcmpestrio128:
17012 case Intrinsic::x86_sse42_pcmpistris128:
17013 case Intrinsic::x86_sse42_pcmpestris128:
17014 case Intrinsic::x86_sse42_pcmpistriz128:
17015 case Intrinsic::x86_sse42_pcmpestriz128: {
17019 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17020 case Intrinsic::x86_sse42_pcmpistria128:
17021 Opcode = X86ISD::PCMPISTRI;
17022 X86CC = X86::COND_A;
17024 case Intrinsic::x86_sse42_pcmpestria128:
17025 Opcode = X86ISD::PCMPESTRI;
17026 X86CC = X86::COND_A;
17028 case Intrinsic::x86_sse42_pcmpistric128:
17029 Opcode = X86ISD::PCMPISTRI;
17030 X86CC = X86::COND_B;
17032 case Intrinsic::x86_sse42_pcmpestric128:
17033 Opcode = X86ISD::PCMPESTRI;
17034 X86CC = X86::COND_B;
17036 case Intrinsic::x86_sse42_pcmpistrio128:
17037 Opcode = X86ISD::PCMPISTRI;
17038 X86CC = X86::COND_O;
17040 case Intrinsic::x86_sse42_pcmpestrio128:
17041 Opcode = X86ISD::PCMPESTRI;
17042 X86CC = X86::COND_O;
17044 case Intrinsic::x86_sse42_pcmpistris128:
17045 Opcode = X86ISD::PCMPISTRI;
17046 X86CC = X86::COND_S;
17048 case Intrinsic::x86_sse42_pcmpestris128:
17049 Opcode = X86ISD::PCMPESTRI;
17050 X86CC = X86::COND_S;
17052 case Intrinsic::x86_sse42_pcmpistriz128:
17053 Opcode = X86ISD::PCMPISTRI;
17054 X86CC = X86::COND_E;
17056 case Intrinsic::x86_sse42_pcmpestriz128:
17057 Opcode = X86ISD::PCMPESTRI;
17058 X86CC = X86::COND_E;
17061 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17062 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17063 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17064 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17065 DAG.getConstant(X86CC, dl, MVT::i8),
17066 SDValue(PCMP.getNode(), 1));
17067 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17070 case Intrinsic::x86_sse42_pcmpistri128:
17071 case Intrinsic::x86_sse42_pcmpestri128: {
17073 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17074 Opcode = X86ISD::PCMPISTRI;
17076 Opcode = X86ISD::PCMPESTRI;
17078 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17079 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17080 return DAG.getNode(Opcode, dl, VTs, NewOps);
17083 case Intrinsic::x86_seh_lsda: {
17084 // Compute the symbol for the LSDA. We know it'll get emitted later.
17085 MachineFunction &MF = DAG.getMachineFunction();
17086 SDValue Op1 = Op.getOperand(1);
17087 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
17088 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
17089 GlobalValue::getRealLinkageName(Fn->getName()));
17091 // Generate a simple absolute symbol reference. This intrinsic is only
17092 // supported on 32-bit Windows, which isn't PIC.
17093 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
17094 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
17097 case Intrinsic::x86_seh_recoverfp: {
17098 SDValue FnOp = Op.getOperand(1);
17099 SDValue IncomingFPOp = Op.getOperand(2);
17100 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
17101 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
17103 report_fatal_error(
17104 "llvm.x86.seh.recoverfp must take a function as the first argument");
17105 return recoverFramePointer(DAG, Fn, IncomingFPOp);
17108 case Intrinsic::localaddress: {
17109 // Returns one of the stack, base, or frame pointer registers, depending on
17110 // which is used to reference local variables.
17111 MachineFunction &MF = DAG.getMachineFunction();
17112 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17114 if (RegInfo->hasBasePointer(MF))
17115 Reg = RegInfo->getBaseRegister();
17116 else // This function handles the SP or FP case.
17117 Reg = RegInfo->getPtrSizedFrameRegister(MF);
17118 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
17123 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17124 SDValue Src, SDValue Mask, SDValue Base,
17125 SDValue Index, SDValue ScaleOp, SDValue Chain,
17126 const X86Subtarget * Subtarget) {
17128 auto *C = cast<ConstantSDNode>(ScaleOp);
17129 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
17130 MVT MaskVT = MVT::getVectorVT(MVT::i1,
17131 Index.getSimpleValueType().getVectorNumElements());
17133 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17135 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
17137 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17138 Mask.getSimpleValueType().getSizeInBits());
17140 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17141 // are extracted by EXTRACT_SUBVECTOR.
17142 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17143 DAG.getBitcast(BitcastVT, Mask),
17144 DAG.getIntPtrConstant(0, dl));
17146 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17147 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
17148 SDValue Segment = DAG.getRegister(0, MVT::i32);
17149 if (Src.getOpcode() == ISD::UNDEF)
17150 Src = getZeroVector(Op.getSimpleValueType(), Subtarget, DAG, dl);
17151 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17152 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17153 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17154 return DAG.getMergeValues(RetOps, dl);
17157 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17158 SDValue Src, SDValue Mask, SDValue Base,
17159 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17161 auto *C = cast<ConstantSDNode>(ScaleOp);
17162 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
17163 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
17164 SDValue Segment = DAG.getRegister(0, MVT::i32);
17165 MVT MaskVT = MVT::getVectorVT(MVT::i1,
17166 Index.getSimpleValueType().getVectorNumElements());
17168 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17170 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
17172 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17173 Mask.getSimpleValueType().getSizeInBits());
17175 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17176 // are extracted by EXTRACT_SUBVECTOR.
17177 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17178 DAG.getBitcast(BitcastVT, Mask),
17179 DAG.getIntPtrConstant(0, dl));
17181 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17182 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17183 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17184 return SDValue(Res, 1);
17187 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17188 SDValue Mask, SDValue Base, SDValue Index,
17189 SDValue ScaleOp, SDValue Chain) {
17191 auto *C = cast<ConstantSDNode>(ScaleOp);
17192 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
17193 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
17194 SDValue Segment = DAG.getRegister(0, MVT::i32);
17196 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17198 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17200 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
17202 MaskInReg = DAG.getBitcast(MaskVT, Mask);
17203 //SDVTList VTs = DAG.getVTList(MVT::Other);
17204 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17205 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17206 return SDValue(Res, 0);
17209 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17210 // read performance monitor counters (x86_rdpmc).
17211 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17212 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17213 SmallVectorImpl<SDValue> &Results) {
17214 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17215 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17218 // The ECX register is used to select the index of the performance counter
17220 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17222 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17224 // Reads the content of a 64-bit performance counter and returns it in the
17225 // registers EDX:EAX.
17226 if (Subtarget->is64Bit()) {
17227 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17228 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17231 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17232 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17235 Chain = HI.getValue(1);
17237 if (Subtarget->is64Bit()) {
17238 // The EAX register is loaded with the low-order 32 bits. The EDX register
17239 // is loaded with the supported high-order bits of the counter.
17240 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17241 DAG.getConstant(32, DL, MVT::i8));
17242 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17243 Results.push_back(Chain);
17247 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17248 SDValue Ops[] = { LO, HI };
17249 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17250 Results.push_back(Pair);
17251 Results.push_back(Chain);
17254 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17255 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17256 // also used to custom lower READCYCLECOUNTER nodes.
17257 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17258 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17259 SmallVectorImpl<SDValue> &Results) {
17260 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17261 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17264 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17265 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17266 // and the EAX register is loaded with the low-order 32 bits.
17267 if (Subtarget->is64Bit()) {
17268 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17269 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17272 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17273 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17276 SDValue Chain = HI.getValue(1);
17278 if (Opcode == X86ISD::RDTSCP_DAG) {
17279 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17281 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17282 // the ECX register. Add 'ecx' explicitly to the chain.
17283 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17285 // Explicitly store the content of ECX at the location passed in input
17286 // to the 'rdtscp' intrinsic.
17287 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17288 MachinePointerInfo(), false, false, 0);
17291 if (Subtarget->is64Bit()) {
17292 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17293 // the EAX register is loaded with the low-order 32 bits.
17294 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17295 DAG.getConstant(32, DL, MVT::i8));
17296 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17297 Results.push_back(Chain);
17301 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17302 SDValue Ops[] = { LO, HI };
17303 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17304 Results.push_back(Pair);
17305 Results.push_back(Chain);
17308 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17309 SelectionDAG &DAG) {
17310 SmallVector<SDValue, 2> Results;
17312 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17314 return DAG.getMergeValues(Results, DL);
17317 static SDValue MarkEHRegistrationNode(SDValue Op, SelectionDAG &DAG) {
17318 MachineFunction &MF = DAG.getMachineFunction();
17319 SDValue Chain = Op.getOperand(0);
17320 SDValue RegNode = Op.getOperand(2);
17321 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
17323 report_fatal_error("EH registrations only live in functions using WinEH");
17325 // Cast the operand to an alloca, and remember the frame index.
17326 auto *FINode = dyn_cast<FrameIndexSDNode>(RegNode);
17328 report_fatal_error("llvm.x86.seh.ehregnode expects a static alloca");
17329 EHInfo->EHRegNodeFrameIndex = FINode->getIndex();
17331 // Return the chain operand without making any DAG nodes.
17335 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
17336 /// return truncate Store/MaskedStore Node
17337 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
17341 SDValue Mask = Op.getOperand(4);
17342 SDValue DataToTruncate = Op.getOperand(3);
17343 SDValue Addr = Op.getOperand(2);
17344 SDValue Chain = Op.getOperand(0);
17346 MVT VT = DataToTruncate.getSimpleValueType();
17347 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
17349 if (isAllOnesConstant(Mask)) // return just a truncate store
17350 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
17351 MachinePointerInfo(), SVT, false, false,
17352 SVT.getScalarSizeInBits()/8);
17354 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
17355 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17356 Mask.getSimpleValueType().getSizeInBits());
17357 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17358 // are extracted by EXTRACT_SUBVECTOR.
17359 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17360 DAG.getBitcast(BitcastVT, Mask),
17361 DAG.getIntPtrConstant(0, dl));
17363 MachineMemOperand *MMO = DAG.getMachineFunction().
17364 getMachineMemOperand(MachinePointerInfo(),
17365 MachineMemOperand::MOStore, SVT.getStoreSize(),
17366 SVT.getScalarSizeInBits()/8);
17368 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17369 VMask, SVT, MMO, true);
17372 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17373 SelectionDAG &DAG) {
17374 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17376 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17378 if (IntNo == llvm::Intrinsic::x86_seh_ehregnode)
17379 return MarkEHRegistrationNode(Op, DAG);
17380 if (IntNo == llvm::Intrinsic::x86_flags_read_u32 ||
17381 IntNo == llvm::Intrinsic::x86_flags_read_u64 ||
17382 IntNo == llvm::Intrinsic::x86_flags_write_u32 ||
17383 IntNo == llvm::Intrinsic::x86_flags_write_u64) {
17384 // We need a frame pointer because this will get lowered to a PUSH/POP
17386 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17387 MFI->setHasOpaqueSPAdjustment(true);
17388 // Don't do anything here, we will expand these intrinsics out later
17389 // during ExpandISelPseudos in EmitInstrWithCustomInserter.
17396 switch(IntrData->Type) {
17397 default: llvm_unreachable("Unknown Intrinsic Type");
17400 // Emit the node with the right value type.
17401 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17402 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17404 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17405 // Otherwise return the value from Rand, which is always 0, casted to i32.
17406 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17407 DAG.getConstant(1, dl, Op->getValueType(1)),
17408 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17409 SDValue(Result.getNode(), 1) };
17410 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17411 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17414 // Return { result, isValid, chain }.
17415 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17416 SDValue(Result.getNode(), 2));
17419 //gather(v1, mask, index, base, scale);
17420 SDValue Chain = Op.getOperand(0);
17421 SDValue Src = Op.getOperand(2);
17422 SDValue Base = Op.getOperand(3);
17423 SDValue Index = Op.getOperand(4);
17424 SDValue Mask = Op.getOperand(5);
17425 SDValue Scale = Op.getOperand(6);
17426 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17430 //scatter(base, mask, index, v1, scale);
17431 SDValue Chain = Op.getOperand(0);
17432 SDValue Base = Op.getOperand(2);
17433 SDValue Mask = Op.getOperand(3);
17434 SDValue Index = Op.getOperand(4);
17435 SDValue Src = Op.getOperand(5);
17436 SDValue Scale = Op.getOperand(6);
17437 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17441 SDValue Hint = Op.getOperand(6);
17442 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17443 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17444 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17445 SDValue Chain = Op.getOperand(0);
17446 SDValue Mask = Op.getOperand(2);
17447 SDValue Index = Op.getOperand(3);
17448 SDValue Base = Op.getOperand(4);
17449 SDValue Scale = Op.getOperand(5);
17450 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17452 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17454 SmallVector<SDValue, 2> Results;
17455 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17457 return DAG.getMergeValues(Results, dl);
17459 // Read Performance Monitoring Counters.
17461 SmallVector<SDValue, 2> Results;
17462 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17463 return DAG.getMergeValues(Results, dl);
17465 // XTEST intrinsics.
17467 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17468 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17469 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17470 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17472 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17473 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17474 Ret, SDValue(InTrans.getNode(), 1));
17478 SmallVector<SDValue, 2> Results;
17479 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17480 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17481 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17482 DAG.getConstant(-1, dl, MVT::i8));
17483 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17484 Op.getOperand(4), GenCF.getValue(1));
17485 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17486 Op.getOperand(5), MachinePointerInfo(),
17488 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17489 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17491 Results.push_back(SetCC);
17492 Results.push_back(Store);
17493 return DAG.getMergeValues(Results, dl);
17495 case COMPRESS_TO_MEM: {
17497 SDValue Mask = Op.getOperand(4);
17498 SDValue DataToCompress = Op.getOperand(3);
17499 SDValue Addr = Op.getOperand(2);
17500 SDValue Chain = Op.getOperand(0);
17502 MVT VT = DataToCompress.getSimpleValueType();
17503 if (isAllOnesConstant(Mask)) // return just a store
17504 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17505 MachinePointerInfo(), false, false,
17506 VT.getScalarSizeInBits()/8);
17508 SDValue Compressed =
17509 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17510 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17511 return DAG.getStore(Chain, dl, Compressed, Addr,
17512 MachinePointerInfo(), false, false,
17513 VT.getScalarSizeInBits()/8);
17515 case TRUNCATE_TO_MEM_VI8:
17516 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17517 case TRUNCATE_TO_MEM_VI16:
17518 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17519 case TRUNCATE_TO_MEM_VI32:
17520 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17521 case EXPAND_FROM_MEM: {
17523 SDValue Mask = Op.getOperand(4);
17524 SDValue PassThru = Op.getOperand(3);
17525 SDValue Addr = Op.getOperand(2);
17526 SDValue Chain = Op.getOperand(0);
17527 MVT VT = Op.getSimpleValueType();
17529 if (isAllOnesConstant(Mask)) // return just a load
17530 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17531 false, VT.getScalarSizeInBits()/8);
17533 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17534 false, false, false,
17535 VT.getScalarSizeInBits()/8);
17537 SDValue Results[] = {
17538 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17539 Mask, PassThru, Subtarget, DAG), Chain};
17540 return DAG.getMergeValues(Results, dl);
17545 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17546 SelectionDAG &DAG) const {
17547 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17548 MFI->setReturnAddressIsTaken(true);
17550 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17553 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17555 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17558 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17559 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17560 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17561 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17562 DAG.getNode(ISD::ADD, dl, PtrVT,
17563 FrameAddr, Offset),
17564 MachinePointerInfo(), false, false, false, 0);
17567 // Just load the return address.
17568 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17569 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17570 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17573 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17574 MachineFunction &MF = DAG.getMachineFunction();
17575 MachineFrameInfo *MFI = MF.getFrameInfo();
17576 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17577 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17578 EVT VT = Op.getValueType();
17580 MFI->setFrameAddressIsTaken(true);
17582 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17583 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17584 // is not possible to crawl up the stack without looking at the unwind codes
17586 int FrameAddrIndex = FuncInfo->getFAIndex();
17587 if (!FrameAddrIndex) {
17588 // Set up a frame object for the return address.
17589 unsigned SlotSize = RegInfo->getSlotSize();
17590 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17591 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17592 FuncInfo->setFAIndex(FrameAddrIndex);
17594 return DAG.getFrameIndex(FrameAddrIndex, VT);
17597 unsigned FrameReg =
17598 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17599 SDLoc dl(Op); // FIXME probably not meaningful
17600 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17601 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17602 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17603 "Invalid Frame Register!");
17604 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17606 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17607 MachinePointerInfo(),
17608 false, false, false, 0);
17612 // FIXME? Maybe this could be a TableGen attribute on some registers and
17613 // this table could be generated automatically from RegInfo.
17614 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17615 SelectionDAG &DAG) const {
17616 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17617 const MachineFunction &MF = DAG.getMachineFunction();
17619 unsigned Reg = StringSwitch<unsigned>(RegName)
17620 .Case("esp", X86::ESP)
17621 .Case("rsp", X86::RSP)
17622 .Case("ebp", X86::EBP)
17623 .Case("rbp", X86::RBP)
17626 if (Reg == X86::EBP || Reg == X86::RBP) {
17627 if (!TFI.hasFP(MF))
17628 report_fatal_error("register " + StringRef(RegName) +
17629 " is allocatable: function has no frame pointer");
17632 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17633 unsigned FrameReg =
17634 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17635 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17636 "Invalid Frame Register!");
17644 report_fatal_error("Invalid register name global variable");
17647 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17648 SelectionDAG &DAG) const {
17649 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17650 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17653 unsigned X86TargetLowering::getExceptionPointerRegister(
17654 const Constant *PersonalityFn) const {
17655 if (classifyEHPersonality(PersonalityFn) == EHPersonality::CoreCLR)
17656 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17658 return Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
17661 unsigned X86TargetLowering::getExceptionSelectorRegister(
17662 const Constant *PersonalityFn) const {
17663 // Funclet personalities don't use selectors (the runtime does the selection).
17664 assert(!isFuncletEHPersonality(classifyEHPersonality(PersonalityFn)));
17665 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17668 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17669 SDValue Chain = Op.getOperand(0);
17670 SDValue Offset = Op.getOperand(1);
17671 SDValue Handler = Op.getOperand(2);
17674 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17675 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17676 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17677 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17678 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17679 "Invalid Frame Register!");
17680 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17681 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17683 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17684 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17686 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17687 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17689 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17691 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17692 DAG.getRegister(StoreAddrReg, PtrVT));
17695 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17696 SelectionDAG &DAG) const {
17698 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17699 DAG.getVTList(MVT::i32, MVT::Other),
17700 Op.getOperand(0), Op.getOperand(1));
17703 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17704 SelectionDAG &DAG) const {
17706 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17707 Op.getOperand(0), Op.getOperand(1));
17710 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17711 return Op.getOperand(0);
17714 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17715 SelectionDAG &DAG) const {
17716 SDValue Root = Op.getOperand(0);
17717 SDValue Trmp = Op.getOperand(1); // trampoline
17718 SDValue FPtr = Op.getOperand(2); // nested function
17719 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17722 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17723 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17725 if (Subtarget->is64Bit()) {
17726 SDValue OutChains[6];
17728 // Large code-model.
17729 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17730 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17732 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17733 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17735 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17737 // Load the pointer to the nested function into R11.
17738 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17739 SDValue Addr = Trmp;
17740 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17741 Addr, MachinePointerInfo(TrmpAddr),
17744 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17745 DAG.getConstant(2, dl, MVT::i64));
17746 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17747 MachinePointerInfo(TrmpAddr, 2),
17750 // Load the 'nest' parameter value into R10.
17751 // R10 is specified in X86CallingConv.td
17752 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17753 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17754 DAG.getConstant(10, dl, MVT::i64));
17755 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17756 Addr, MachinePointerInfo(TrmpAddr, 10),
17759 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17760 DAG.getConstant(12, dl, MVT::i64));
17761 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17762 MachinePointerInfo(TrmpAddr, 12),
17765 // Jump to the nested function.
17766 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17767 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17768 DAG.getConstant(20, dl, MVT::i64));
17769 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17770 Addr, MachinePointerInfo(TrmpAddr, 20),
17773 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17774 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17775 DAG.getConstant(22, dl, MVT::i64));
17776 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17777 Addr, MachinePointerInfo(TrmpAddr, 22),
17780 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17782 const Function *Func =
17783 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17784 CallingConv::ID CC = Func->getCallingConv();
17789 llvm_unreachable("Unsupported calling convention");
17790 case CallingConv::C:
17791 case CallingConv::X86_StdCall: {
17792 // Pass 'nest' parameter in ECX.
17793 // Must be kept in sync with X86CallingConv.td
17794 NestReg = X86::ECX;
17796 // Check that ECX wasn't needed by an 'inreg' parameter.
17797 FunctionType *FTy = Func->getFunctionType();
17798 const AttributeSet &Attrs = Func->getAttributes();
17800 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17801 unsigned InRegCount = 0;
17804 for (FunctionType::param_iterator I = FTy->param_begin(),
17805 E = FTy->param_end(); I != E; ++I, ++Idx)
17806 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17807 auto &DL = DAG.getDataLayout();
17808 // FIXME: should only count parameters that are lowered to integers.
17809 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17812 if (InRegCount > 2) {
17813 report_fatal_error("Nest register in use - reduce number of inreg"
17819 case CallingConv::X86_FastCall:
17820 case CallingConv::X86_ThisCall:
17821 case CallingConv::Fast:
17822 // Pass 'nest' parameter in EAX.
17823 // Must be kept in sync with X86CallingConv.td
17824 NestReg = X86::EAX;
17828 SDValue OutChains[4];
17829 SDValue Addr, Disp;
17831 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17832 DAG.getConstant(10, dl, MVT::i32));
17833 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17835 // This is storing the opcode for MOV32ri.
17836 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17837 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17838 OutChains[0] = DAG.getStore(Root, dl,
17839 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17840 Trmp, MachinePointerInfo(TrmpAddr),
17843 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17844 DAG.getConstant(1, dl, MVT::i32));
17845 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17846 MachinePointerInfo(TrmpAddr, 1),
17849 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17850 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17851 DAG.getConstant(5, dl, MVT::i32));
17852 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17853 Addr, MachinePointerInfo(TrmpAddr, 5),
17856 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17857 DAG.getConstant(6, dl, MVT::i32));
17858 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17859 MachinePointerInfo(TrmpAddr, 6),
17862 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17866 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17867 SelectionDAG &DAG) const {
17869 The rounding mode is in bits 11:10 of FPSR, and has the following
17871 00 Round to nearest
17876 FLT_ROUNDS, on the other hand, expects the following:
17883 To perform the conversion, we do:
17884 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17887 MachineFunction &MF = DAG.getMachineFunction();
17888 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17889 unsigned StackAlignment = TFI.getStackAlignment();
17890 MVT VT = Op.getSimpleValueType();
17893 // Save FP Control Word to stack slot
17894 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17895 SDValue StackSlot =
17896 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17898 MachineMemOperand *MMO =
17899 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17900 MachineMemOperand::MOStore, 2, 2);
17902 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17903 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17904 DAG.getVTList(MVT::Other),
17905 Ops, MVT::i16, MMO);
17907 // Load FP Control Word from stack slot
17908 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17909 MachinePointerInfo(), false, false, false, 0);
17911 // Transform as necessary
17913 DAG.getNode(ISD::SRL, DL, MVT::i16,
17914 DAG.getNode(ISD::AND, DL, MVT::i16,
17915 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17916 DAG.getConstant(11, DL, MVT::i8));
17918 DAG.getNode(ISD::SRL, DL, MVT::i16,
17919 DAG.getNode(ISD::AND, DL, MVT::i16,
17920 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17921 DAG.getConstant(9, DL, MVT::i8));
17924 DAG.getNode(ISD::AND, DL, MVT::i16,
17925 DAG.getNode(ISD::ADD, DL, MVT::i16,
17926 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17927 DAG.getConstant(1, DL, MVT::i16)),
17928 DAG.getConstant(3, DL, MVT::i16));
17930 return DAG.getNode((VT.getSizeInBits() < 16 ?
17931 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17934 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17936 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17937 // to 512-bit vector.
17938 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17939 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17940 // split the vector, perform operation on it's Lo a Hi part and
17941 // concatenate the results.
17942 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17944 MVT VT = Op.getSimpleValueType();
17945 MVT EltVT = VT.getVectorElementType();
17946 unsigned NumElems = VT.getVectorNumElements();
17948 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17949 // Extend to 512 bit vector.
17950 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17951 "Unsupported value type for operation");
17953 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17954 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17955 DAG.getUNDEF(NewVT),
17957 DAG.getIntPtrConstant(0, dl));
17958 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17960 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17961 DAG.getIntPtrConstant(0, dl));
17964 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17965 "Unsupported element type");
17967 if (16 < NumElems) {
17968 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17970 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17971 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17973 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17974 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17976 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17979 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17981 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17982 "Unsupported value type for operation");
17984 // Use native supported vector instruction vplzcntd.
17985 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17986 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17987 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17988 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17990 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17993 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17994 SelectionDAG &DAG) {
17995 MVT VT = Op.getSimpleValueType();
17997 unsigned NumBits = VT.getSizeInBits();
18000 if (VT.isVector() && Subtarget->hasAVX512())
18001 return LowerVectorCTLZ_AVX512(Op, DAG);
18003 Op = Op.getOperand(0);
18004 if (VT == MVT::i8) {
18005 // Zero extend to i32 since there is not an i8 bsr.
18007 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18010 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
18011 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18012 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18014 // If src is zero (i.e. bsr sets ZF), returns NumBits.
18017 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
18018 DAG.getConstant(X86::COND_E, dl, MVT::i8),
18021 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
18023 // Finally xor with NumBits-1.
18024 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
18025 DAG.getConstant(NumBits - 1, dl, OpVT));
18028 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18032 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
18033 SelectionDAG &DAG) {
18034 MVT VT = Op.getSimpleValueType();
18036 unsigned NumBits = VT.getSizeInBits();
18039 Op = Op.getOperand(0);
18040 if (VT == MVT::i8) {
18041 // Zero extend to i32 since there is not an i8 bsr.
18043 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18046 // Issue a bsr (scan bits in reverse).
18047 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18048 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18050 // And xor with NumBits-1.
18051 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
18052 DAG.getConstant(NumBits - 1, dl, OpVT));
18055 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18059 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18060 MVT VT = Op.getSimpleValueType();
18061 unsigned NumBits = VT.getScalarSizeInBits();
18064 if (VT.isVector()) {
18065 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18067 SDValue N0 = Op.getOperand(0);
18068 SDValue Zero = DAG.getConstant(0, dl, VT);
18070 // lsb(x) = (x & -x)
18071 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
18072 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
18074 // cttz_undef(x) = (width - 1) - ctlz(lsb)
18075 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
18076 TLI.isOperationLegal(ISD::CTLZ, VT)) {
18077 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
18078 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
18079 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
18082 // cttz(x) = ctpop(lsb - 1)
18083 SDValue One = DAG.getConstant(1, dl, VT);
18084 return DAG.getNode(ISD::CTPOP, dl, VT,
18085 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
18088 assert(Op.getOpcode() == ISD::CTTZ &&
18089 "Only scalar CTTZ requires custom lowering");
18091 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18092 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18093 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
18095 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18098 DAG.getConstant(NumBits, dl, VT),
18099 DAG.getConstant(X86::COND_E, dl, MVT::i8),
18102 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18105 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18106 // ones, and then concatenate the result back.
18107 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18108 MVT VT = Op.getSimpleValueType();
18110 assert(VT.is256BitVector() && VT.isInteger() &&
18111 "Unsupported value type for operation");
18113 unsigned NumElems = VT.getVectorNumElements();
18116 // Extract the LHS vectors
18117 SDValue LHS = Op.getOperand(0);
18118 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18119 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18121 // Extract the RHS vectors
18122 SDValue RHS = Op.getOperand(1);
18123 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18124 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18126 MVT EltVT = VT.getVectorElementType();
18127 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18129 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18130 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18131 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18134 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18135 if (Op.getValueType() == MVT::i1)
18136 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
18137 Op.getOperand(0), Op.getOperand(1));
18138 assert(Op.getSimpleValueType().is256BitVector() &&
18139 Op.getSimpleValueType().isInteger() &&
18140 "Only handle AVX 256-bit vector integer operation");
18141 return Lower256IntArith(Op, DAG);
18144 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18145 if (Op.getValueType() == MVT::i1)
18146 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
18147 Op.getOperand(0), Op.getOperand(1));
18148 assert(Op.getSimpleValueType().is256BitVector() &&
18149 Op.getSimpleValueType().isInteger() &&
18150 "Only handle AVX 256-bit vector integer operation");
18151 return Lower256IntArith(Op, DAG);
18154 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
18155 assert(Op.getSimpleValueType().is256BitVector() &&
18156 Op.getSimpleValueType().isInteger() &&
18157 "Only handle AVX 256-bit vector integer operation");
18158 return Lower256IntArith(Op, DAG);
18161 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18162 SelectionDAG &DAG) {
18164 MVT VT = Op.getSimpleValueType();
18167 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
18169 // Decompose 256-bit ops into smaller 128-bit ops.
18170 if (VT.is256BitVector() && !Subtarget->hasInt256())
18171 return Lower256IntArith(Op, DAG);
18173 SDValue A = Op.getOperand(0);
18174 SDValue B = Op.getOperand(1);
18176 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
18177 // pairs, multiply and truncate.
18178 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
18179 if (Subtarget->hasInt256()) {
18180 if (VT == MVT::v32i8) {
18181 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
18182 SDValue Lo = DAG.getIntPtrConstant(0, dl);
18183 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
18184 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
18185 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
18186 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
18187 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
18188 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18189 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
18190 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
18193 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
18194 return DAG.getNode(
18195 ISD::TRUNCATE, dl, VT,
18196 DAG.getNode(ISD::MUL, dl, ExVT,
18197 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
18198 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
18201 assert(VT == MVT::v16i8 &&
18202 "Pre-AVX2 support only supports v16i8 multiplication");
18203 MVT ExVT = MVT::v8i16;
18205 // Extract the lo parts and sign extend to i16
18207 if (Subtarget->hasSSE41()) {
18208 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
18209 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
18211 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
18212 -1, 4, -1, 5, -1, 6, -1, 7};
18213 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18214 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18215 ALo = DAG.getBitcast(ExVT, ALo);
18216 BLo = DAG.getBitcast(ExVT, BLo);
18217 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
18218 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
18221 // Extract the hi parts and sign extend to i16
18223 if (Subtarget->hasSSE41()) {
18224 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
18225 -1, -1, -1, -1, -1, -1, -1, -1};
18226 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18227 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18228 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
18229 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
18231 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
18232 -1, 12, -1, 13, -1, 14, -1, 15};
18233 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18234 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18235 AHi = DAG.getBitcast(ExVT, AHi);
18236 BHi = DAG.getBitcast(ExVT, BHi);
18237 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
18238 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
18241 // Multiply, mask the lower 8bits of the lo/hi results and pack
18242 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
18243 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
18244 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
18245 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
18246 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18249 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18250 if (VT == MVT::v4i32) {
18251 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18252 "Should not custom lower when pmuldq is available!");
18254 // Extract the odd parts.
18255 static const int UnpackMask[] = { 1, -1, 3, -1 };
18256 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18257 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18259 // Multiply the even parts.
18260 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18261 // Now multiply odd parts.
18262 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18264 Evens = DAG.getBitcast(VT, Evens);
18265 Odds = DAG.getBitcast(VT, Odds);
18267 // Merge the two vectors back together with a shuffle. This expands into 2
18269 static const int ShufMask[] = { 0, 4, 2, 6 };
18270 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18273 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18274 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18276 // Ahi = psrlqi(a, 32);
18277 // Bhi = psrlqi(b, 32);
18279 // AloBlo = pmuludq(a, b);
18280 // AloBhi = pmuludq(a, Bhi);
18281 // AhiBlo = pmuludq(Ahi, b);
18283 // AloBhi = psllqi(AloBhi, 32);
18284 // AhiBlo = psllqi(AhiBlo, 32);
18285 // return AloBlo + AloBhi + AhiBlo;
18287 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18288 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18290 SDValue AhiBlo = Ahi;
18291 SDValue AloBhi = Bhi;
18292 // Bit cast to 32-bit vectors for MULUDQ
18293 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18294 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18295 A = DAG.getBitcast(MulVT, A);
18296 B = DAG.getBitcast(MulVT, B);
18297 Ahi = DAG.getBitcast(MulVT, Ahi);
18298 Bhi = DAG.getBitcast(MulVT, Bhi);
18300 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18301 // After shifting right const values the result may be all-zero.
18302 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
18303 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18304 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18306 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
18307 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18308 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18311 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18312 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18315 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18316 assert(Subtarget->isTargetWin64() && "Unexpected target");
18317 EVT VT = Op.getValueType();
18318 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18319 "Unexpected return type for lowering");
18323 switch (Op->getOpcode()) {
18324 default: llvm_unreachable("Unexpected request for libcall!");
18325 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18326 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18327 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18328 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18329 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18330 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18334 SDValue InChain = DAG.getEntryNode();
18336 TargetLowering::ArgListTy Args;
18337 TargetLowering::ArgListEntry Entry;
18338 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18339 EVT ArgVT = Op->getOperand(i).getValueType();
18340 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18341 "Unexpected argument type for lowering");
18342 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18343 Entry.Node = StackPtr;
18344 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18346 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18347 Entry.Ty = PointerType::get(ArgTy,0);
18348 Entry.isSExt = false;
18349 Entry.isZExt = false;
18350 Args.push_back(Entry);
18353 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18354 getPointerTy(DAG.getDataLayout()));
18356 TargetLowering::CallLoweringInfo CLI(DAG);
18357 CLI.setDebugLoc(dl).setChain(InChain)
18358 .setCallee(getLibcallCallingConv(LC),
18359 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18360 Callee, std::move(Args), 0)
18361 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18363 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18364 return DAG.getBitcast(VT, CallInfo.first);
18367 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18368 SelectionDAG &DAG) {
18369 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18370 MVT VT = Op0.getSimpleValueType();
18373 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18374 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18376 // PMULxD operations multiply each even value (starting at 0) of LHS with
18377 // the related value of RHS and produce a widen result.
18378 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18379 // => <2 x i64> <ae|cg>
18381 // In other word, to have all the results, we need to perform two PMULxD:
18382 // 1. one with the even values.
18383 // 2. one with the odd values.
18384 // To achieve #2, with need to place the odd values at an even position.
18386 // Place the odd value at an even position (basically, shift all values 1
18387 // step to the left):
18388 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18389 // <a|b|c|d> => <b|undef|d|undef>
18390 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18391 // <e|f|g|h> => <f|undef|h|undef>
18392 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18394 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18396 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18397 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18399 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18400 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18401 // => <2 x i64> <ae|cg>
18402 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18403 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18404 // => <2 x i64> <bf|dh>
18405 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18407 // Shuffle it back into the right order.
18408 SDValue Highs, Lows;
18409 if (VT == MVT::v8i32) {
18410 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18411 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18412 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18413 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18415 const int HighMask[] = {1, 5, 3, 7};
18416 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18417 const int LowMask[] = {0, 4, 2, 6};
18418 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18421 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18422 // unsigned multiply.
18423 if (IsSigned && !Subtarget->hasSSE41()) {
18424 SDValue ShAmt = DAG.getConstant(
18426 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18427 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18428 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18429 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18430 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18432 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18433 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18436 // The first result of MUL_LOHI is actually the low value, followed by the
18438 SDValue Ops[] = {Lows, Highs};
18439 return DAG.getMergeValues(Ops, dl);
18442 // Return true if the required (according to Opcode) shift-imm form is natively
18443 // supported by the Subtarget
18444 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18446 if (VT.getScalarSizeInBits() < 16)
18449 if (VT.is512BitVector() &&
18450 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18453 bool LShift = VT.is128BitVector() ||
18454 (VT.is256BitVector() && Subtarget->hasInt256());
18456 bool AShift = LShift && (Subtarget->hasVLX() ||
18457 (VT != MVT::v2i64 && VT != MVT::v4i64));
18458 return (Opcode == ISD::SRA) ? AShift : LShift;
18461 // The shift amount is a variable, but it is the same for all vector lanes.
18462 // These instructions are defined together with shift-immediate.
18464 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18466 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18469 // Return true if the required (according to Opcode) variable-shift form is
18470 // natively supported by the Subtarget
18471 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18474 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18477 // vXi16 supported only on AVX-512, BWI
18478 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18481 if (VT.is512BitVector() || Subtarget->hasVLX())
18484 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18485 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18486 return (Opcode == ISD::SRA) ? AShift : LShift;
18489 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18490 const X86Subtarget *Subtarget) {
18491 MVT VT = Op.getSimpleValueType();
18493 SDValue R = Op.getOperand(0);
18494 SDValue Amt = Op.getOperand(1);
18496 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18497 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18499 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18500 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18501 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18502 SDValue Ex = DAG.getBitcast(ExVT, R);
18504 if (ShiftAmt >= 32) {
18505 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18507 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18508 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18509 ShiftAmt - 32, DAG);
18510 if (VT == MVT::v2i64)
18511 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18512 if (VT == MVT::v4i64)
18513 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18514 {9, 1, 11, 3, 13, 5, 15, 7});
18516 // SRA upper i32, SHL whole i64 and select lower i32.
18517 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18520 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18521 Lower = DAG.getBitcast(ExVT, Lower);
18522 if (VT == MVT::v2i64)
18523 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18524 if (VT == MVT::v4i64)
18525 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18526 {8, 1, 10, 3, 12, 5, 14, 7});
18528 return DAG.getBitcast(VT, Ex);
18531 // Optimize shl/srl/sra with constant shift amount.
18532 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18533 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18534 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18536 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18537 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18539 // i64 SRA needs to be performed as partial shifts.
18540 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18541 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18542 return ArithmeticShiftRight64(ShiftAmt);
18544 if (VT == MVT::v16i8 ||
18545 (Subtarget->hasInt256() && VT == MVT::v32i8) ||
18546 VT == MVT::v64i8) {
18547 unsigned NumElts = VT.getVectorNumElements();
18548 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18550 // Simple i8 add case
18551 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18552 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18554 // ashr(R, 7) === cmp_slt(R, 0)
18555 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18556 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18557 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18560 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18561 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18564 if (Op.getOpcode() == ISD::SHL) {
18565 // Make a large shift.
18566 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18568 SHL = DAG.getBitcast(VT, SHL);
18569 // Zero out the rightmost bits.
18570 return DAG.getNode(ISD::AND, dl, VT, SHL,
18571 DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, VT));
18573 if (Op.getOpcode() == ISD::SRL) {
18574 // Make a large shift.
18575 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18577 SRL = DAG.getBitcast(VT, SRL);
18578 // Zero out the leftmost bits.
18579 return DAG.getNode(ISD::AND, dl, VT, SRL,
18580 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, VT));
18582 if (Op.getOpcode() == ISD::SRA) {
18583 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18584 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18586 SDValue Mask = DAG.getConstant(128 >> ShiftAmt, dl, VT);
18587 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18588 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18591 llvm_unreachable("Unknown shift opcode.");
18596 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18597 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18598 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18600 // Peek through any splat that was introduced for i64 shift vectorization.
18601 int SplatIndex = -1;
18602 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18603 if (SVN->isSplat()) {
18604 SplatIndex = SVN->getSplatIndex();
18605 Amt = Amt.getOperand(0);
18606 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18607 "Splat shuffle referencing second operand");
18610 if (Amt.getOpcode() != ISD::BITCAST ||
18611 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18614 Amt = Amt.getOperand(0);
18615 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18616 VT.getVectorNumElements();
18617 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18618 uint64_t ShiftAmt = 0;
18619 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18620 for (unsigned i = 0; i != Ratio; ++i) {
18621 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18625 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18628 // Check remaining shift amounts (if not a splat).
18629 if (SplatIndex < 0) {
18630 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18631 uint64_t ShAmt = 0;
18632 for (unsigned j = 0; j != Ratio; ++j) {
18633 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18637 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18639 if (ShAmt != ShiftAmt)
18644 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18645 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18647 if (Op.getOpcode() == ISD::SRA)
18648 return ArithmeticShiftRight64(ShiftAmt);
18654 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18655 const X86Subtarget* Subtarget) {
18656 MVT VT = Op.getSimpleValueType();
18658 SDValue R = Op.getOperand(0);
18659 SDValue Amt = Op.getOperand(1);
18661 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18662 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18664 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18665 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18667 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18669 MVT EltVT = VT.getVectorElementType();
18671 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18672 // Check if this build_vector node is doing a splat.
18673 // If so, then set BaseShAmt equal to the splat value.
18674 BaseShAmt = BV->getSplatValue();
18675 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18676 BaseShAmt = SDValue();
18678 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18679 Amt = Amt.getOperand(0);
18681 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18682 if (SVN && SVN->isSplat()) {
18683 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18684 SDValue InVec = Amt.getOperand(0);
18685 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18686 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18687 "Unexpected shuffle index found!");
18688 BaseShAmt = InVec.getOperand(SplatIdx);
18689 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18690 if (ConstantSDNode *C =
18691 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18692 if (C->getZExtValue() == SplatIdx)
18693 BaseShAmt = InVec.getOperand(1);
18698 // Avoid introducing an extract element from a shuffle.
18699 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18700 DAG.getIntPtrConstant(SplatIdx, dl));
18704 if (BaseShAmt.getNode()) {
18705 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18706 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18707 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18708 else if (EltVT.bitsLT(MVT::i32))
18709 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18711 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18715 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18716 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18717 Amt.getOpcode() == ISD::BITCAST &&
18718 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18719 Amt = Amt.getOperand(0);
18720 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18721 VT.getVectorNumElements();
18722 std::vector<SDValue> Vals(Ratio);
18723 for (unsigned i = 0; i != Ratio; ++i)
18724 Vals[i] = Amt.getOperand(i);
18725 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18726 for (unsigned j = 0; j != Ratio; ++j)
18727 if (Vals[j] != Amt.getOperand(i + j))
18731 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18732 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18737 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18738 SelectionDAG &DAG) {
18739 MVT VT = Op.getSimpleValueType();
18741 SDValue R = Op.getOperand(0);
18742 SDValue Amt = Op.getOperand(1);
18744 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18745 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18747 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18750 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18753 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18756 // XOP has 128-bit variable logical/arithmetic shifts.
18757 // +ve/-ve Amt = shift left/right.
18758 if (Subtarget->hasXOP() &&
18759 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18760 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18761 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18762 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18763 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18765 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18766 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18767 if (Op.getOpcode() == ISD::SRA)
18768 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18771 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18772 // shifts per-lane and then shuffle the partial results back together.
18773 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18774 // Splat the shift amounts so the scalar shifts above will catch it.
18775 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18776 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18777 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18778 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18779 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18782 // i64 vector arithmetic shift can be emulated with the transform:
18783 // M = lshr(SIGN_BIT, Amt)
18784 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18785 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18786 Op.getOpcode() == ISD::SRA) {
18787 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18788 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18789 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18790 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18791 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18795 // If possible, lower this packed shift into a vector multiply instead of
18796 // expanding it into a sequence of scalar shifts.
18797 // Do this only if the vector shift count is a constant build_vector.
18798 if (Op.getOpcode() == ISD::SHL &&
18799 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18800 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18801 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18802 SmallVector<SDValue, 8> Elts;
18803 MVT SVT = VT.getVectorElementType();
18804 unsigned SVTBits = SVT.getSizeInBits();
18805 APInt One(SVTBits, 1);
18806 unsigned NumElems = VT.getVectorNumElements();
18808 for (unsigned i=0; i !=NumElems; ++i) {
18809 SDValue Op = Amt->getOperand(i);
18810 if (Op->getOpcode() == ISD::UNDEF) {
18811 Elts.push_back(Op);
18815 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18816 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18817 uint64_t ShAmt = C.getZExtValue();
18818 if (ShAmt >= SVTBits) {
18819 Elts.push_back(DAG.getUNDEF(SVT));
18822 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18824 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18825 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18828 // Lower SHL with variable shift amount.
18829 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18830 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18832 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18833 DAG.getConstant(0x3f800000U, dl, VT));
18834 Op = DAG.getBitcast(MVT::v4f32, Op);
18835 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18836 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18839 // If possible, lower this shift as a sequence of two shifts by
18840 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18842 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18844 // Could be rewritten as:
18845 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18847 // The advantage is that the two shifts from the example would be
18848 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18849 // the vector shift into four scalar shifts plus four pairs of vector
18851 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18852 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18853 unsigned TargetOpcode = X86ISD::MOVSS;
18854 bool CanBeSimplified;
18855 // The splat value for the first packed shift (the 'X' from the example).
18856 SDValue Amt1 = Amt->getOperand(0);
18857 // The splat value for the second packed shift (the 'Y' from the example).
18858 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18859 Amt->getOperand(2);
18861 // See if it is possible to replace this node with a sequence of
18862 // two shifts followed by a MOVSS/MOVSD
18863 if (VT == MVT::v4i32) {
18864 // Check if it is legal to use a MOVSS.
18865 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18866 Amt2 == Amt->getOperand(3);
18867 if (!CanBeSimplified) {
18868 // Otherwise, check if we can still simplify this node using a MOVSD.
18869 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18870 Amt->getOperand(2) == Amt->getOperand(3);
18871 TargetOpcode = X86ISD::MOVSD;
18872 Amt2 = Amt->getOperand(2);
18875 // Do similar checks for the case where the machine value type
18877 CanBeSimplified = Amt1 == Amt->getOperand(1);
18878 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18879 CanBeSimplified = Amt2 == Amt->getOperand(i);
18881 if (!CanBeSimplified) {
18882 TargetOpcode = X86ISD::MOVSD;
18883 CanBeSimplified = true;
18884 Amt2 = Amt->getOperand(4);
18885 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18886 CanBeSimplified = Amt1 == Amt->getOperand(i);
18887 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18888 CanBeSimplified = Amt2 == Amt->getOperand(j);
18892 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18893 isa<ConstantSDNode>(Amt2)) {
18894 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18895 MVT CastVT = MVT::v4i32;
18897 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18898 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18900 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18901 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18902 if (TargetOpcode == X86ISD::MOVSD)
18903 CastVT = MVT::v2i64;
18904 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18905 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18906 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18908 return DAG.getBitcast(VT, Result);
18912 // v4i32 Non Uniform Shifts.
18913 // If the shift amount is constant we can shift each lane using the SSE2
18914 // immediate shifts, else we need to zero-extend each lane to the lower i64
18915 // and shift using the SSE2 variable shifts.
18916 // The separate results can then be blended together.
18917 if (VT == MVT::v4i32) {
18918 unsigned Opc = Op.getOpcode();
18919 SDValue Amt0, Amt1, Amt2, Amt3;
18920 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18921 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18922 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18923 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18924 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18926 // ISD::SHL is handled above but we include it here for completeness.
18929 llvm_unreachable("Unknown target vector shift node");
18931 Opc = X86ISD::VSHL;
18934 Opc = X86ISD::VSRL;
18937 Opc = X86ISD::VSRA;
18940 // The SSE2 shifts use the lower i64 as the same shift amount for
18941 // all lanes and the upper i64 is ignored. These shuffle masks
18942 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18943 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18944 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18945 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18946 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18947 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18950 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18951 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18952 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18953 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18954 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18955 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18956 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18959 if (VT == MVT::v16i8 ||
18960 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18961 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18962 unsigned ShiftOpcode = Op->getOpcode();
18964 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18965 // On SSE41 targets we make use of the fact that VSELECT lowers
18966 // to PBLENDVB which selects bytes based just on the sign bit.
18967 if (Subtarget->hasSSE41()) {
18968 V0 = DAG.getBitcast(VT, V0);
18969 V1 = DAG.getBitcast(VT, V1);
18970 Sel = DAG.getBitcast(VT, Sel);
18971 return DAG.getBitcast(SelVT,
18972 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18974 // On pre-SSE41 targets we test for the sign bit by comparing to
18975 // zero - a negative value will set all bits of the lanes to true
18976 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18977 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18978 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18979 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18982 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18983 // We can safely do this using i16 shifts as we're only interested in
18984 // the 3 lower bits of each byte.
18985 Amt = DAG.getBitcast(ExtVT, Amt);
18986 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18987 Amt = DAG.getBitcast(VT, Amt);
18989 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18990 // r = VSELECT(r, shift(r, 4), a);
18992 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18993 R = SignBitSelect(VT, Amt, M, R);
18996 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18998 // r = VSELECT(r, shift(r, 2), a);
18999 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
19000 R = SignBitSelect(VT, Amt, M, R);
19003 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
19005 // return VSELECT(r, shift(r, 1), a);
19006 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
19007 R = SignBitSelect(VT, Amt, M, R);
19011 if (Op->getOpcode() == ISD::SRA) {
19012 // For SRA we need to unpack each byte to the higher byte of a i16 vector
19013 // so we can correctly sign extend. We don't care what happens to the
19015 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
19016 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
19017 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
19018 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
19019 ALo = DAG.getBitcast(ExtVT, ALo);
19020 AHi = DAG.getBitcast(ExtVT, AHi);
19021 RLo = DAG.getBitcast(ExtVT, RLo);
19022 RHi = DAG.getBitcast(ExtVT, RHi);
19024 // r = VSELECT(r, shift(r, 4), a);
19025 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
19026 DAG.getConstant(4, dl, ExtVT));
19027 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
19028 DAG.getConstant(4, dl, ExtVT));
19029 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
19030 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
19033 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
19034 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
19036 // r = VSELECT(r, shift(r, 2), a);
19037 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
19038 DAG.getConstant(2, dl, ExtVT));
19039 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
19040 DAG.getConstant(2, dl, ExtVT));
19041 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
19042 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
19045 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
19046 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
19048 // r = VSELECT(r, shift(r, 1), a);
19049 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
19050 DAG.getConstant(1, dl, ExtVT));
19051 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
19052 DAG.getConstant(1, dl, ExtVT));
19053 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
19054 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
19056 // Logical shift the result back to the lower byte, leaving a zero upper
19058 // meaning that we can safely pack with PACKUSWB.
19060 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
19062 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
19063 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
19067 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
19068 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
19069 // solution better.
19070 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
19071 MVT ExtVT = MVT::v8i32;
19073 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
19074 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
19075 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
19076 return DAG.getNode(ISD::TRUNCATE, dl, VT,
19077 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
19080 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
19081 MVT ExtVT = MVT::v8i32;
19082 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
19083 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
19084 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
19085 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
19086 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
19087 ALo = DAG.getBitcast(ExtVT, ALo);
19088 AHi = DAG.getBitcast(ExtVT, AHi);
19089 RLo = DAG.getBitcast(ExtVT, RLo);
19090 RHi = DAG.getBitcast(ExtVT, RHi);
19091 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
19092 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
19093 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
19094 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
19095 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
19098 if (VT == MVT::v8i16) {
19099 unsigned ShiftOpcode = Op->getOpcode();
19101 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
19102 // On SSE41 targets we make use of the fact that VSELECT lowers
19103 // to PBLENDVB which selects bytes based just on the sign bit.
19104 if (Subtarget->hasSSE41()) {
19105 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
19106 V0 = DAG.getBitcast(ExtVT, V0);
19107 V1 = DAG.getBitcast(ExtVT, V1);
19108 Sel = DAG.getBitcast(ExtVT, Sel);
19109 return DAG.getBitcast(
19110 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
19112 // On pre-SSE41 targets we splat the sign bit - a negative value will
19113 // set all bits of the lanes to true and VSELECT uses that in
19114 // its OR(AND(V0,C),AND(V1,~C)) lowering.
19116 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
19117 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
19120 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
19121 if (Subtarget->hasSSE41()) {
19122 // On SSE41 targets we need to replicate the shift mask in both
19123 // bytes for PBLENDVB.
19126 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
19127 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
19129 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
19132 // r = VSELECT(r, shift(r, 8), a);
19133 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
19134 R = SignBitSelect(Amt, M, R);
19137 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
19139 // r = VSELECT(r, shift(r, 4), a);
19140 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
19141 R = SignBitSelect(Amt, M, R);
19144 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
19146 // r = VSELECT(r, shift(r, 2), a);
19147 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
19148 R = SignBitSelect(Amt, M, R);
19151 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
19153 // return VSELECT(r, shift(r, 1), a);
19154 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
19155 R = SignBitSelect(Amt, M, R);
19159 // Decompose 256-bit shifts into smaller 128-bit shifts.
19160 if (VT.is256BitVector()) {
19161 unsigned NumElems = VT.getVectorNumElements();
19162 MVT EltVT = VT.getVectorElementType();
19163 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
19165 // Extract the two vectors
19166 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
19167 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
19169 // Recreate the shift amount vectors
19170 SDValue Amt1, Amt2;
19171 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
19172 // Constant shift amount
19173 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
19174 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
19175 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
19177 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
19178 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
19180 // Variable shift amount
19181 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
19182 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
19185 // Issue new vector shifts for the smaller types
19186 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
19187 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
19189 // Concatenate the result back
19190 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
19196 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
19197 SelectionDAG &DAG) {
19198 MVT VT = Op.getSimpleValueType();
19200 SDValue R = Op.getOperand(0);
19201 SDValue Amt = Op.getOperand(1);
19203 assert(VT.isVector() && "Custom lowering only for vector rotates!");
19204 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
19205 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
19207 // XOP has 128-bit vector variable + immediate rotates.
19208 // +ve/-ve Amt = rotate left/right.
19210 // Split 256-bit integers.
19211 if (VT.is256BitVector())
19212 return Lower256IntArith(Op, DAG);
19214 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
19216 // Attempt to rotate by immediate.
19217 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
19218 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
19219 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
19220 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
19221 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
19222 DAG.getConstant(RotateAmt, DL, MVT::i8));
19226 // Use general rotate by variable (per-element).
19227 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
19230 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
19231 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
19232 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
19233 // looks for this combo and may remove the "setcc" instruction if the "setcc"
19234 // has only one use.
19235 SDNode *N = Op.getNode();
19236 SDValue LHS = N->getOperand(0);
19237 SDValue RHS = N->getOperand(1);
19238 unsigned BaseOp = 0;
19241 switch (Op.getOpcode()) {
19242 default: llvm_unreachable("Unknown ovf instruction!");
19244 // A subtract of one will be selected as a INC. Note that INC doesn't
19245 // set CF, so we can't do this for UADDO.
19246 if (isOneConstant(RHS)) {
19247 BaseOp = X86ISD::INC;
19248 Cond = X86::COND_O;
19251 BaseOp = X86ISD::ADD;
19252 Cond = X86::COND_O;
19255 BaseOp = X86ISD::ADD;
19256 Cond = X86::COND_B;
19259 // A subtract of one will be selected as a DEC. Note that DEC doesn't
19260 // set CF, so we can't do this for USUBO.
19261 if (isOneConstant(RHS)) {
19262 BaseOp = X86ISD::DEC;
19263 Cond = X86::COND_O;
19266 BaseOp = X86ISD::SUB;
19267 Cond = X86::COND_O;
19270 BaseOp = X86ISD::SUB;
19271 Cond = X86::COND_B;
19274 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
19275 Cond = X86::COND_O;
19277 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
19278 if (N->getValueType(0) == MVT::i8) {
19279 BaseOp = X86ISD::UMUL8;
19280 Cond = X86::COND_O;
19283 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
19285 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
19288 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19289 DAG.getConstant(X86::COND_O, DL, MVT::i32),
19290 SDValue(Sum.getNode(), 2));
19292 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19296 // Also sets EFLAGS.
19297 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
19298 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
19301 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19302 DAG.getConstant(Cond, DL, MVT::i32),
19303 SDValue(Sum.getNode(), 1));
19305 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19308 /// Returns true if the operand type is exactly twice the native width, and
19309 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19310 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19311 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19312 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
19313 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19316 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19317 else if (OpWidth == 128)
19318 return Subtarget->hasCmpxchg16b();
19323 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19324 return needsCmpXchgNb(SI->getValueOperand()->getType());
19327 // Note: this turns large loads into lock cmpxchg8b/16b.
19328 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19329 TargetLowering::AtomicExpansionKind
19330 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19331 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19332 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
19333 : AtomicExpansionKind::None;
19336 TargetLowering::AtomicExpansionKind
19337 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19338 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19339 Type *MemType = AI->getType();
19341 // If the operand is too big, we must see if cmpxchg8/16b is available
19342 // and default to library calls otherwise.
19343 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
19344 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
19345 : AtomicExpansionKind::None;
19348 AtomicRMWInst::BinOp Op = AI->getOperation();
19351 llvm_unreachable("Unknown atomic operation");
19352 case AtomicRMWInst::Xchg:
19353 case AtomicRMWInst::Add:
19354 case AtomicRMWInst::Sub:
19355 // It's better to use xadd, xsub or xchg for these in all cases.
19356 return AtomicExpansionKind::None;
19357 case AtomicRMWInst::Or:
19358 case AtomicRMWInst::And:
19359 case AtomicRMWInst::Xor:
19360 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19361 // prefix to a normal instruction for these operations.
19362 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
19363 : AtomicExpansionKind::None;
19364 case AtomicRMWInst::Nand:
19365 case AtomicRMWInst::Max:
19366 case AtomicRMWInst::Min:
19367 case AtomicRMWInst::UMax:
19368 case AtomicRMWInst::UMin:
19369 // These always require a non-trivial set of data operations on x86. We must
19370 // use a cmpxchg loop.
19371 return AtomicExpansionKind::CmpXChg;
19375 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19376 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19377 // no-sse2). There isn't any reason to disable it if the target processor
19379 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19383 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19384 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19385 Type *MemType = AI->getType();
19386 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19387 // there is no benefit in turning such RMWs into loads, and it is actually
19388 // harmful as it introduces a mfence.
19389 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19392 auto Builder = IRBuilder<>(AI);
19393 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19394 auto SynchScope = AI->getSynchScope();
19395 // We must restrict the ordering to avoid generating loads with Release or
19396 // ReleaseAcquire orderings.
19397 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19398 auto Ptr = AI->getPointerOperand();
19400 // Before the load we need a fence. Here is an example lifted from
19401 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19404 // x.store(1, relaxed);
19405 // r1 = y.fetch_add(0, release);
19407 // y.fetch_add(42, acquire);
19408 // r2 = x.load(relaxed);
19409 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19410 // lowered to just a load without a fence. A mfence flushes the store buffer,
19411 // making the optimization clearly correct.
19412 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19413 // otherwise, we might be able to be more aggressive on relaxed idempotent
19414 // rmw. In practice, they do not look useful, so we don't try to be
19415 // especially clever.
19416 if (SynchScope == SingleThread)
19417 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19418 // the IR level, so we must wrap it in an intrinsic.
19421 if (!hasMFENCE(*Subtarget))
19422 // FIXME: it might make sense to use a locked operation here but on a
19423 // different cache-line to prevent cache-line bouncing. In practice it
19424 // is probably a small win, and x86 processors without mfence are rare
19425 // enough that we do not bother.
19429 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19430 Builder.CreateCall(MFence, {});
19432 // Finally we can emit the atomic load.
19433 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19434 AI->getType()->getPrimitiveSizeInBits());
19435 Loaded->setAtomic(Order, SynchScope);
19436 AI->replaceAllUsesWith(Loaded);
19437 AI->eraseFromParent();
19441 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19442 SelectionDAG &DAG) {
19444 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19445 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19446 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19447 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19449 // The only fence that needs an instruction is a sequentially-consistent
19450 // cross-thread fence.
19451 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19452 if (hasMFENCE(*Subtarget))
19453 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19455 SDValue Chain = Op.getOperand(0);
19456 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19458 DAG.getRegister(X86::ESP, MVT::i32), // Base
19459 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19460 DAG.getRegister(0, MVT::i32), // Index
19461 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19462 DAG.getRegister(0, MVT::i32), // Segment.
19466 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19467 return SDValue(Res, 0);
19470 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19471 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19474 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19475 SelectionDAG &DAG) {
19476 MVT T = Op.getSimpleValueType();
19480 switch(T.SimpleTy) {
19481 default: llvm_unreachable("Invalid value type!");
19482 case MVT::i8: Reg = X86::AL; size = 1; break;
19483 case MVT::i16: Reg = X86::AX; size = 2; break;
19484 case MVT::i32: Reg = X86::EAX; size = 4; break;
19486 assert(Subtarget->is64Bit() && "Node not type legal!");
19487 Reg = X86::RAX; size = 8;
19490 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19491 Op.getOperand(2), SDValue());
19492 SDValue Ops[] = { cpIn.getValue(0),
19495 DAG.getTargetConstant(size, DL, MVT::i8),
19496 cpIn.getValue(1) };
19497 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19498 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19499 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19503 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19504 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19505 MVT::i32, cpOut.getValue(2));
19506 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19507 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19510 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19511 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19512 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19516 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19517 SelectionDAG &DAG) {
19518 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19519 MVT DstVT = Op.getSimpleValueType();
19521 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19522 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19523 if (DstVT != MVT::f64)
19524 // This conversion needs to be expanded.
19527 SDValue InVec = Op->getOperand(0);
19529 unsigned NumElts = SrcVT.getVectorNumElements();
19530 MVT SVT = SrcVT.getVectorElementType();
19532 // Widen the vector in input in the case of MVT::v2i32.
19533 // Example: from MVT::v2i32 to MVT::v4i32.
19534 SmallVector<SDValue, 16> Elts;
19535 for (unsigned i = 0, e = NumElts; i != e; ++i)
19536 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19537 DAG.getIntPtrConstant(i, dl)));
19539 // Explicitly mark the extra elements as Undef.
19540 Elts.append(NumElts, DAG.getUNDEF(SVT));
19542 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19543 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19544 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19545 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19546 DAG.getIntPtrConstant(0, dl));
19549 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19550 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19551 assert((DstVT == MVT::i64 ||
19552 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19553 "Unexpected custom BITCAST");
19554 // i64 <=> MMX conversions are Legal.
19555 if (SrcVT==MVT::i64 && DstVT.isVector())
19557 if (DstVT==MVT::i64 && SrcVT.isVector())
19559 // MMX <=> MMX conversions are Legal.
19560 if (SrcVT.isVector() && DstVT.isVector())
19562 // All other conversions need to be expanded.
19566 /// Compute the horizontal sum of bytes in V for the elements of VT.
19568 /// Requires V to be a byte vector and VT to be an integer vector type with
19569 /// wider elements than V's type. The width of the elements of VT determines
19570 /// how many bytes of V are summed horizontally to produce each element of the
19572 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19573 const X86Subtarget *Subtarget,
19574 SelectionDAG &DAG) {
19576 MVT ByteVecVT = V.getSimpleValueType();
19577 MVT EltVT = VT.getVectorElementType();
19578 int NumElts = VT.getVectorNumElements();
19579 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19580 "Expected value to have byte element type.");
19581 assert(EltVT != MVT::i8 &&
19582 "Horizontal byte sum only makes sense for wider elements!");
19583 unsigned VecSize = VT.getSizeInBits();
19584 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19586 // PSADBW instruction horizontally add all bytes and leave the result in i64
19587 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19588 if (EltVT == MVT::i64) {
19589 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19590 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19591 V = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT, V, Zeros);
19592 return DAG.getBitcast(VT, V);
19595 if (EltVT == MVT::i32) {
19596 // We unpack the low half and high half into i32s interleaved with zeros so
19597 // that we can use PSADBW to horizontally sum them. The most useful part of
19598 // this is that it lines up the results of two PSADBW instructions to be
19599 // two v2i64 vectors which concatenated are the 4 population counts. We can
19600 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19601 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19602 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19603 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19605 // Do the horizontal sums into two v2i64s.
19606 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19607 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19608 Low = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19609 DAG.getBitcast(ByteVecVT, Low), Zeros);
19610 High = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19611 DAG.getBitcast(ByteVecVT, High), Zeros);
19613 // Merge them together.
19614 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19615 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19616 DAG.getBitcast(ShortVecVT, Low),
19617 DAG.getBitcast(ShortVecVT, High));
19619 return DAG.getBitcast(VT, V);
19622 // The only element type left is i16.
19623 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19625 // To obtain pop count for each i16 element starting from the pop count for
19626 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19627 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19628 // directly supported.
19629 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19630 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19631 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19632 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19633 DAG.getBitcast(ByteVecVT, V));
19634 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19637 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19638 const X86Subtarget *Subtarget,
19639 SelectionDAG &DAG) {
19640 MVT VT = Op.getSimpleValueType();
19641 MVT EltVT = VT.getVectorElementType();
19642 unsigned VecSize = VT.getSizeInBits();
19644 // Implement a lookup table in register by using an algorithm based on:
19645 // http://wm.ite.pl/articles/sse-popcount.html
19647 // The general idea is that every lower byte nibble in the input vector is an
19648 // index into a in-register pre-computed pop count table. We then split up the
19649 // input vector in two new ones: (1) a vector with only the shifted-right
19650 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19651 // masked out higher ones) for each byte. PSHUB is used separately with both
19652 // to index the in-register table. Next, both are added and the result is a
19653 // i8 vector where each element contains the pop count for input byte.
19655 // To obtain the pop count for elements != i8, we follow up with the same
19656 // approach and use additional tricks as described below.
19658 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19659 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19660 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19661 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19663 int NumByteElts = VecSize / 8;
19664 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19665 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19666 SmallVector<SDValue, 16> LUTVec;
19667 for (int i = 0; i < NumByteElts; ++i)
19668 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19669 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19670 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19671 DAG.getConstant(0x0F, DL, MVT::i8));
19672 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19675 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19676 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19677 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19680 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19682 // The input vector is used as the shuffle mask that index elements into the
19683 // LUT. After counting low and high nibbles, add the vector to obtain the
19684 // final pop count per i8 element.
19685 SDValue HighPopCnt =
19686 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19687 SDValue LowPopCnt =
19688 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19689 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19691 if (EltVT == MVT::i8)
19694 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19697 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19698 const X86Subtarget *Subtarget,
19699 SelectionDAG &DAG) {
19700 MVT VT = Op.getSimpleValueType();
19701 assert(VT.is128BitVector() &&
19702 "Only 128-bit vector bitmath lowering supported.");
19704 int VecSize = VT.getSizeInBits();
19705 MVT EltVT = VT.getVectorElementType();
19706 int Len = EltVT.getSizeInBits();
19708 // This is the vectorized version of the "best" algorithm from
19709 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19710 // with a minor tweak to use a series of adds + shifts instead of vector
19711 // multiplications. Implemented for all integer vector types. We only use
19712 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19713 // much faster, even faster than using native popcnt instructions.
19715 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19716 MVT VT = V.getSimpleValueType();
19717 SmallVector<SDValue, 32> Shifters(
19718 VT.getVectorNumElements(),
19719 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19720 return DAG.getNode(OpCode, DL, VT, V,
19721 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19723 auto GetMask = [&](SDValue V, APInt Mask) {
19724 MVT VT = V.getSimpleValueType();
19725 SmallVector<SDValue, 32> Masks(
19726 VT.getVectorNumElements(),
19727 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19728 return DAG.getNode(ISD::AND, DL, VT, V,
19729 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19732 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19733 // x86, so set the SRL type to have elements at least i16 wide. This is
19734 // correct because all of our SRLs are followed immediately by a mask anyways
19735 // that handles any bits that sneak into the high bits of the byte elements.
19736 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19740 // v = v - ((v >> 1) & 0x55555555...)
19742 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19743 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19744 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19746 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19747 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19748 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19749 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19750 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19752 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19753 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19754 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19755 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19757 // At this point, V contains the byte-wise population count, and we are
19758 // merely doing a horizontal sum if necessary to get the wider element
19760 if (EltVT == MVT::i8)
19763 return LowerHorizontalByteSum(
19764 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19768 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19769 SelectionDAG &DAG) {
19770 MVT VT = Op.getSimpleValueType();
19771 // FIXME: Need to add AVX-512 support here!
19772 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19773 "Unknown CTPOP type to handle");
19774 SDLoc DL(Op.getNode());
19775 SDValue Op0 = Op.getOperand(0);
19777 if (!Subtarget->hasSSSE3()) {
19778 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19779 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19780 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19783 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19784 unsigned NumElems = VT.getVectorNumElements();
19786 // Extract each 128-bit vector, compute pop count and concat the result.
19787 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19788 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19790 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19791 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19792 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19795 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19798 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19799 SelectionDAG &DAG) {
19800 assert(Op.getSimpleValueType().isVector() &&
19801 "We only do custom lowering for vector population count.");
19802 return LowerVectorCTPOP(Op, Subtarget, DAG);
19805 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19806 SDNode *Node = Op.getNode();
19808 EVT T = Node->getValueType(0);
19809 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19810 DAG.getConstant(0, dl, T), Node->getOperand(2));
19811 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19812 cast<AtomicSDNode>(Node)->getMemoryVT(),
19813 Node->getOperand(0),
19814 Node->getOperand(1), negOp,
19815 cast<AtomicSDNode>(Node)->getMemOperand(),
19816 cast<AtomicSDNode>(Node)->getOrdering(),
19817 cast<AtomicSDNode>(Node)->getSynchScope());
19820 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19821 SDNode *Node = Op.getNode();
19823 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19825 // Convert seq_cst store -> xchg
19826 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19827 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19828 // (The only way to get a 16-byte store is cmpxchg16b)
19829 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19830 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19831 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19832 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19833 cast<AtomicSDNode>(Node)->getMemoryVT(),
19834 Node->getOperand(0),
19835 Node->getOperand(1), Node->getOperand(2),
19836 cast<AtomicSDNode>(Node)->getMemOperand(),
19837 cast<AtomicSDNode>(Node)->getOrdering(),
19838 cast<AtomicSDNode>(Node)->getSynchScope());
19839 return Swap.getValue(1);
19841 // Other atomic stores have a simple pattern.
19845 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19846 MVT VT = Op.getNode()->getSimpleValueType(0);
19848 // Let legalize expand this if it isn't a legal type yet.
19849 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19852 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19855 bool ExtraOp = false;
19856 switch (Op.getOpcode()) {
19857 default: llvm_unreachable("Invalid code");
19858 case ISD::ADDC: Opc = X86ISD::ADD; break;
19859 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19860 case ISD::SUBC: Opc = X86ISD::SUB; break;
19861 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19865 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19867 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19868 Op.getOperand(1), Op.getOperand(2));
19871 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19872 SelectionDAG &DAG) {
19873 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19875 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19876 // which returns the values as { float, float } (in XMM0) or
19877 // { double, double } (which is returned in XMM0, XMM1).
19879 SDValue Arg = Op.getOperand(0);
19880 EVT ArgVT = Arg.getValueType();
19881 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19883 TargetLowering::ArgListTy Args;
19884 TargetLowering::ArgListEntry Entry;
19888 Entry.isSExt = false;
19889 Entry.isZExt = false;
19890 Args.push_back(Entry);
19892 bool isF64 = ArgVT == MVT::f64;
19893 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19894 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19895 // the results are returned via SRet in memory.
19896 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19897 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19899 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19901 Type *RetTy = isF64
19902 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19903 : (Type*)VectorType::get(ArgTy, 4);
19905 TargetLowering::CallLoweringInfo CLI(DAG);
19906 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19907 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19909 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19912 // Returned in xmm0 and xmm1.
19913 return CallResult.first;
19915 // Returned in bits 0:31 and 32:64 xmm0.
19916 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19917 CallResult.first, DAG.getIntPtrConstant(0, dl));
19918 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19919 CallResult.first, DAG.getIntPtrConstant(1, dl));
19920 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19921 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19924 /// Widen a vector input to a vector of NVT. The
19925 /// input vector must have the same element type as NVT.
19926 static SDValue ExtendToType(SDValue InOp, MVT NVT, SelectionDAG &DAG,
19927 bool FillWithZeroes = false) {
19928 // Check if InOp already has the right width.
19929 MVT InVT = InOp.getSimpleValueType();
19933 if (InOp.isUndef())
19934 return DAG.getUNDEF(NVT);
19936 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
19937 "input and widen element type must match");
19939 unsigned InNumElts = InVT.getVectorNumElements();
19940 unsigned WidenNumElts = NVT.getVectorNumElements();
19941 assert(WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0 &&
19942 "Unexpected request for vector widening");
19944 EVT EltVT = NVT.getVectorElementType();
19947 if (InOp.getOpcode() == ISD::CONCAT_VECTORS &&
19948 InOp.getNumOperands() == 2) {
19949 SDValue N1 = InOp.getOperand(1);
19950 if ((ISD::isBuildVectorAllZeros(N1.getNode()) && FillWithZeroes) ||
19952 InOp = InOp.getOperand(0);
19953 InVT = InOp.getSimpleValueType();
19954 InNumElts = InVT.getVectorNumElements();
19957 if (ISD::isBuildVectorOfConstantSDNodes(InOp.getNode()) ||
19958 ISD::isBuildVectorOfConstantFPSDNodes(InOp.getNode())) {
19959 SmallVector<SDValue, 16> Ops;
19960 for (unsigned i = 0; i < InNumElts; ++i)
19961 Ops.push_back(InOp.getOperand(i));
19963 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
19964 DAG.getUNDEF(EltVT);
19965 for (unsigned i = 0; i < WidenNumElts - InNumElts; ++i)
19966 Ops.push_back(FillVal);
19967 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);
19969 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, NVT) :
19971 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NVT, FillVal,
19972 InOp, DAG.getIntPtrConstant(0, dl));
19975 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19976 SelectionDAG &DAG) {
19977 assert(Subtarget->hasAVX512() &&
19978 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19980 // X86 scatter kills mask register, so its type should be added to
19981 // the list of return values.
19982 // If the "scatter" has 2 return values, it is already handled.
19983 if (Op.getNode()->getNumValues() == 2)
19986 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19987 SDValue Src = N->getValue();
19988 MVT VT = Src.getSimpleValueType();
19989 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19992 SDValue NewScatter;
19993 SDValue Index = N->getIndex();
19994 SDValue Mask = N->getMask();
19995 SDValue Chain = N->getChain();
19996 SDValue BasePtr = N->getBasePtr();
19997 MVT MemVT = N->getMemoryVT().getSimpleVT();
19998 MVT IndexVT = Index.getSimpleValueType();
19999 MVT MaskVT = Mask.getSimpleValueType();
20001 if (MemVT.getScalarSizeInBits() < VT.getScalarSizeInBits()) {
20002 // The v2i32 value was promoted to v2i64.
20003 // Now we "redo" the type legalizer's work and widen the original
20004 // v2i32 value to v4i32. The original v2i32 is retrieved from v2i64
20006 assert((MemVT == MVT::v2i32 && VT == MVT::v2i64) &&
20007 "Unexpected memory type");
20008 int ShuffleMask[] = {0, 2, -1, -1};
20009 Src = DAG.getVectorShuffle(MVT::v4i32, dl, DAG.getBitcast(MVT::v4i32, Src),
20010 DAG.getUNDEF(MVT::v4i32), ShuffleMask);
20011 // Now we have 4 elements instead of 2.
20012 // Expand the index.
20013 MVT NewIndexVT = MVT::getVectorVT(IndexVT.getScalarType(), 4);
20014 Index = ExtendToType(Index, NewIndexVT, DAG);
20016 // Expand the mask with zeroes
20017 // Mask may be <2 x i64> or <2 x i1> at this moment
20018 assert((MaskVT == MVT::v2i1 || MaskVT == MVT::v2i64) &&
20019 "Unexpected mask type");
20020 MVT ExtMaskVT = MVT::getVectorVT(MaskVT.getScalarType(), 4);
20021 Mask = ExtendToType(Mask, ExtMaskVT, DAG, true);
20025 unsigned NumElts = VT.getVectorNumElements();
20026 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
20027 !Index.getSimpleValueType().is512BitVector()) {
20028 // AVX512F supports only 512-bit vectors. Or data or index should
20029 // be 512 bit wide. If now the both index and data are 256-bit, but
20030 // the vector contains 8 elements, we just sign-extend the index
20031 if (IndexVT == MVT::v8i32)
20032 // Just extend index
20033 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
20035 // The minimal number of elts in scatter is 8
20038 MVT NewIndexVT = MVT::getVectorVT(IndexVT.getScalarType(), NumElts);
20039 // Use original index here, do not modify the index twice
20040 Index = ExtendToType(N->getIndex(), NewIndexVT, DAG);
20041 if (IndexVT.getScalarType() == MVT::i32)
20042 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
20045 // At this point we have promoted mask operand
20046 assert(MaskVT.getScalarSizeInBits() >= 32 && "unexpected mask type");
20047 MVT ExtMaskVT = MVT::getVectorVT(MaskVT.getScalarType(), NumElts);
20048 // Use the original mask here, do not modify the mask twice
20049 Mask = ExtendToType(N->getMask(), ExtMaskVT, DAG, true);
20051 // The value that should be stored
20052 MVT NewVT = MVT::getVectorVT(VT.getScalarType(), NumElts);
20053 Src = ExtendToType(Src, NewVT, DAG);
20056 // If the mask is "wide" at this point - truncate it to i1 vector
20057 MVT BitMaskVT = MVT::getVectorVT(MVT::i1, NumElts);
20058 Mask = DAG.getNode(ISD::TRUNCATE, dl, BitMaskVT, Mask);
20060 // The mask is killed by scatter, add it to the values
20061 SDVTList VTs = DAG.getVTList(BitMaskVT, MVT::Other);
20062 SDValue Ops[] = {Chain, Src, Mask, BasePtr, Index};
20063 NewScatter = DAG.getMaskedScatter(VTs, N->getMemoryVT(), dl, Ops,
20064 N->getMemOperand());
20065 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
20066 return SDValue(NewScatter.getNode(), 0);
20069 static SDValue LowerMLOAD(SDValue Op, const X86Subtarget *Subtarget,
20070 SelectionDAG &DAG) {
20072 MaskedLoadSDNode *N = cast<MaskedLoadSDNode>(Op.getNode());
20073 MVT VT = Op.getSimpleValueType();
20074 SDValue Mask = N->getMask();
20077 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
20078 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
20079 // This operation is legal for targets with VLX, but without
20080 // VLX the vector should be widened to 512 bit
20081 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
20082 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
20083 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
20084 SDValue Src0 = N->getSrc0();
20085 Src0 = ExtendToType(Src0, WideDataVT, DAG);
20086 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
20087 SDValue NewLoad = DAG.getMaskedLoad(WideDataVT, dl, N->getChain(),
20088 N->getBasePtr(), Mask, Src0,
20089 N->getMemoryVT(), N->getMemOperand(),
20090 N->getExtensionType());
20092 SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
20093 NewLoad.getValue(0),
20094 DAG.getIntPtrConstant(0, dl));
20095 SDValue RetOps[] = {Exract, NewLoad.getValue(1)};
20096 return DAG.getMergeValues(RetOps, dl);
20101 static SDValue LowerMSTORE(SDValue Op, const X86Subtarget *Subtarget,
20102 SelectionDAG &DAG) {
20103 MaskedStoreSDNode *N = cast<MaskedStoreSDNode>(Op.getNode());
20104 SDValue DataToStore = N->getValue();
20105 MVT VT = DataToStore.getSimpleValueType();
20106 SDValue Mask = N->getMask();
20109 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
20110 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
20111 // This operation is legal for targets with VLX, but without
20112 // VLX the vector should be widened to 512 bit
20113 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
20114 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
20115 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
20116 DataToStore = ExtendToType(DataToStore, WideDataVT, DAG);
20117 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
20118 return DAG.getMaskedStore(N->getChain(), dl, DataToStore, N->getBasePtr(),
20119 Mask, N->getMemoryVT(), N->getMemOperand(),
20120 N->isTruncatingStore());
20125 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
20126 SelectionDAG &DAG) {
20127 assert(Subtarget->hasAVX512() &&
20128 "MGATHER/MSCATTER are supported on AVX-512 arch only");
20130 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
20132 MVT VT = Op.getSimpleValueType();
20133 SDValue Index = N->getIndex();
20134 SDValue Mask = N->getMask();
20135 SDValue Src0 = N->getValue();
20136 MVT IndexVT = Index.getSimpleValueType();
20137 MVT MaskVT = Mask.getSimpleValueType();
20139 unsigned NumElts = VT.getVectorNumElements();
20140 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
20142 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
20143 !Index.getSimpleValueType().is512BitVector()) {
20144 // AVX512F supports only 512-bit vectors. Or data or index should
20145 // be 512 bit wide. If now the both index and data are 256-bit, but
20146 // the vector contains 8 elements, we just sign-extend the index
20147 if (NumElts == 8) {
20148 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
20149 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
20150 N->getOperand(3), Index };
20151 DAG.UpdateNodeOperands(N, Ops);
20155 // Minimal number of elements in Gather
20158 MVT NewIndexVT = MVT::getVectorVT(IndexVT.getScalarType(), NumElts);
20159 Index = ExtendToType(Index, NewIndexVT, DAG);
20160 if (IndexVT.getScalarType() == MVT::i32)
20161 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
20164 MVT MaskBitVT = MVT::getVectorVT(MVT::i1, NumElts);
20165 // At this point we have promoted mask operand
20166 assert(MaskVT.getScalarSizeInBits() >= 32 && "unexpected mask type");
20167 MVT ExtMaskVT = MVT::getVectorVT(MaskVT.getScalarType(), NumElts);
20168 Mask = ExtendToType(Mask, ExtMaskVT, DAG, true);
20169 Mask = DAG.getNode(ISD::TRUNCATE, dl, MaskBitVT, Mask);
20171 // The pass-thru value
20172 MVT NewVT = MVT::getVectorVT(VT.getScalarType(), NumElts);
20173 Src0 = ExtendToType(Src0, NewVT, DAG);
20175 SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };
20176 SDValue NewGather = DAG.getMaskedGather(DAG.getVTList(NewVT, MVT::Other),
20177 N->getMemoryVT(), dl, Ops,
20178 N->getMemOperand());
20179 SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
20180 NewGather.getValue(0),
20181 DAG.getIntPtrConstant(0, dl));
20182 SDValue RetOps[] = {Exract, NewGather.getValue(1)};
20183 return DAG.getMergeValues(RetOps, dl);
20188 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
20189 SelectionDAG &DAG) const {
20190 // TODO: Eventually, the lowering of these nodes should be informed by or
20191 // deferred to the GC strategy for the function in which they appear. For
20192 // now, however, they must be lowered to something. Since they are logically
20193 // no-ops in the case of a null GC strategy (or a GC strategy which does not
20194 // require special handling for these nodes), lower them as literal NOOPs for
20196 SmallVector<SDValue, 2> Ops;
20198 Ops.push_back(Op.getOperand(0));
20199 if (Op->getGluedNode())
20200 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
20203 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
20204 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
20209 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
20210 SelectionDAG &DAG) const {
20211 // TODO: Eventually, the lowering of these nodes should be informed by or
20212 // deferred to the GC strategy for the function in which they appear. For
20213 // now, however, they must be lowered to something. Since they are logically
20214 // no-ops in the case of a null GC strategy (or a GC strategy which does not
20215 // require special handling for these nodes), lower them as literal NOOPs for
20217 SmallVector<SDValue, 2> Ops;
20219 Ops.push_back(Op.getOperand(0));
20220 if (Op->getGluedNode())
20221 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
20224 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
20225 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
20230 /// LowerOperation - Provide custom lowering hooks for some operations.
20232 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
20233 switch (Op.getOpcode()) {
20234 default: llvm_unreachable("Should not custom lower this!");
20235 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
20236 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
20237 return LowerCMP_SWAP(Op, Subtarget, DAG);
20238 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
20239 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
20240 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
20241 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
20242 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
20243 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
20244 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
20245 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
20246 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
20247 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
20248 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
20249 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
20250 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
20251 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
20252 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
20253 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
20254 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
20255 case ISD::SHL_PARTS:
20256 case ISD::SRA_PARTS:
20257 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
20258 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
20259 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
20260 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
20261 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
20262 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
20263 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
20264 case ISD::SIGN_EXTEND_VECTOR_INREG:
20265 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
20266 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
20267 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
20268 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
20269 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
20271 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
20272 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
20273 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
20274 case ISD::SETCC: return LowerSETCC(Op, DAG);
20275 case ISD::SETCCE: return LowerSETCCE(Op, DAG);
20276 case ISD::SELECT: return LowerSELECT(Op, DAG);
20277 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
20278 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
20279 case ISD::VASTART: return LowerVASTART(Op, DAG);
20280 case ISD::VAARG: return LowerVAARG(Op, DAG);
20281 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
20282 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
20283 case ISD::INTRINSIC_VOID:
20284 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
20285 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
20286 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
20287 case ISD::FRAME_TO_ARGS_OFFSET:
20288 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
20289 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
20290 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
20291 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
20292 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
20293 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
20294 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
20295 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
20296 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
20297 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
20299 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
20300 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
20301 case ISD::UMUL_LOHI:
20302 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
20303 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
20306 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
20312 case ISD::UMULO: return LowerXALUO(Op, DAG);
20313 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
20314 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
20318 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
20319 case ISD::ADD: return LowerADD(Op, DAG);
20320 case ISD::SUB: return LowerSUB(Op, DAG);
20324 case ISD::UMIN: return LowerMINMAX(Op, DAG);
20325 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
20326 case ISD::MLOAD: return LowerMLOAD(Op, Subtarget, DAG);
20327 case ISD::MSTORE: return LowerMSTORE(Op, Subtarget, DAG);
20328 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
20329 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
20330 case ISD::GC_TRANSITION_START:
20331 return LowerGC_TRANSITION_START(Op, DAG);
20332 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
20336 /// ReplaceNodeResults - Replace a node with an illegal result type
20337 /// with a new node built out of custom code.
20338 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
20339 SmallVectorImpl<SDValue>&Results,
20340 SelectionDAG &DAG) const {
20342 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20343 switch (N->getOpcode()) {
20345 llvm_unreachable("Do not know how to custom type legalize this operation!");
20346 case X86ISD::AVG: {
20347 // Legalize types for X86ISD::AVG by expanding vectors.
20348 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20350 auto InVT = N->getValueType(0);
20351 auto InVTSize = InVT.getSizeInBits();
20352 const unsigned RegSize =
20353 (InVTSize > 128) ? ((InVTSize > 256) ? 512 : 256) : 128;
20354 assert((!Subtarget->hasAVX512() || RegSize < 512) &&
20355 "512-bit vector requires AVX512");
20356 assert((!Subtarget->hasAVX2() || RegSize < 256) &&
20357 "256-bit vector requires AVX2");
20359 auto ElemVT = InVT.getVectorElementType();
20360 auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT,
20361 RegSize / ElemVT.getSizeInBits());
20362 assert(RegSize % InVT.getSizeInBits() == 0);
20363 unsigned NumConcat = RegSize / InVT.getSizeInBits();
20365 SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
20366 Ops[0] = N->getOperand(0);
20367 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20368 Ops[0] = N->getOperand(1);
20369 SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20371 SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1);
20372 Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res,
20373 DAG.getIntPtrConstant(0, dl)));
20376 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
20377 case X86ISD::FMINC:
20379 case X86ISD::FMAXC:
20380 case X86ISD::FMAX: {
20381 EVT VT = N->getValueType(0);
20382 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
20383 SDValue UNDEF = DAG.getUNDEF(VT);
20384 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20385 N->getOperand(0), UNDEF);
20386 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20387 N->getOperand(1), UNDEF);
20388 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
20391 case ISD::SIGN_EXTEND_INREG:
20396 // We don't want to expand or promote these.
20403 case ISD::UDIVREM: {
20404 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
20405 Results.push_back(V);
20408 case ISD::FP_TO_SINT:
20409 case ISD::FP_TO_UINT: {
20410 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
20412 std::pair<SDValue,SDValue> Vals =
20413 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
20414 SDValue FIST = Vals.first, StackSlot = Vals.second;
20415 if (FIST.getNode()) {
20416 EVT VT = N->getValueType(0);
20417 // Return a load from the stack slot.
20418 if (StackSlot.getNode())
20419 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
20420 MachinePointerInfo(),
20421 false, false, false, 0));
20423 Results.push_back(FIST);
20427 case ISD::UINT_TO_FP: {
20428 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20429 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
20430 N->getValueType(0) != MVT::v2f32)
20432 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
20434 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
20436 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
20437 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
20438 DAG.getBitcast(MVT::v2i64, VBias));
20439 Or = DAG.getBitcast(MVT::v2f64, Or);
20440 // TODO: Are there any fast-math-flags to propagate here?
20441 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
20442 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
20445 case ISD::FP_ROUND: {
20446 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
20448 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
20449 Results.push_back(V);
20452 case ISD::FP_EXTEND: {
20453 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
20454 // No other ValueType for FP_EXTEND should reach this point.
20455 assert(N->getValueType(0) == MVT::v2f32 &&
20456 "Do not know how to legalize this Node");
20459 case ISD::INTRINSIC_W_CHAIN: {
20460 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
20462 default : llvm_unreachable("Do not know how to custom type "
20463 "legalize this intrinsic operation!");
20464 case Intrinsic::x86_rdtsc:
20465 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20467 case Intrinsic::x86_rdtscp:
20468 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
20470 case Intrinsic::x86_rdpmc:
20471 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
20474 case ISD::INTRINSIC_WO_CHAIN: {
20475 if (SDValue V = LowerINTRINSIC_WO_CHAIN(SDValue(N, 0), Subtarget, DAG))
20476 Results.push_back(V);
20479 case ISD::READCYCLECOUNTER: {
20480 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20483 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
20484 EVT T = N->getValueType(0);
20485 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
20486 bool Regs64bit = T == MVT::i128;
20487 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
20488 SDValue cpInL, cpInH;
20489 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20490 DAG.getConstant(0, dl, HalfT));
20491 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20492 DAG.getConstant(1, dl, HalfT));
20493 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
20494 Regs64bit ? X86::RAX : X86::EAX,
20496 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
20497 Regs64bit ? X86::RDX : X86::EDX,
20498 cpInH, cpInL.getValue(1));
20499 SDValue swapInL, swapInH;
20500 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20501 DAG.getConstant(0, dl, HalfT));
20502 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20503 DAG.getConstant(1, dl, HalfT));
20504 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
20505 Regs64bit ? X86::RBX : X86::EBX,
20506 swapInL, cpInH.getValue(1));
20507 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
20508 Regs64bit ? X86::RCX : X86::ECX,
20509 swapInH, swapInL.getValue(1));
20510 SDValue Ops[] = { swapInH.getValue(0),
20512 swapInH.getValue(1) };
20513 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
20514 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
20515 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
20516 X86ISD::LCMPXCHG8_DAG;
20517 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
20518 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
20519 Regs64bit ? X86::RAX : X86::EAX,
20520 HalfT, Result.getValue(1));
20521 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
20522 Regs64bit ? X86::RDX : X86::EDX,
20523 HalfT, cpOutL.getValue(2));
20524 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
20526 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
20527 MVT::i32, cpOutH.getValue(2));
20529 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
20530 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
20531 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
20533 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
20534 Results.push_back(Success);
20535 Results.push_back(EFLAGS.getValue(1));
20538 case ISD::ATOMIC_SWAP:
20539 case ISD::ATOMIC_LOAD_ADD:
20540 case ISD::ATOMIC_LOAD_SUB:
20541 case ISD::ATOMIC_LOAD_AND:
20542 case ISD::ATOMIC_LOAD_OR:
20543 case ISD::ATOMIC_LOAD_XOR:
20544 case ISD::ATOMIC_LOAD_NAND:
20545 case ISD::ATOMIC_LOAD_MIN:
20546 case ISD::ATOMIC_LOAD_MAX:
20547 case ISD::ATOMIC_LOAD_UMIN:
20548 case ISD::ATOMIC_LOAD_UMAX:
20549 case ISD::ATOMIC_LOAD: {
20550 // Delegate to generic TypeLegalization. Situations we can really handle
20551 // should have already been dealt with by AtomicExpandPass.cpp.
20554 case ISD::BITCAST: {
20555 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20556 EVT DstVT = N->getValueType(0);
20557 EVT SrcVT = N->getOperand(0)->getValueType(0);
20559 if (SrcVT != MVT::f64 ||
20560 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
20563 unsigned NumElts = DstVT.getVectorNumElements();
20564 EVT SVT = DstVT.getVectorElementType();
20565 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
20566 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
20567 MVT::v2f64, N->getOperand(0));
20568 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
20570 if (ExperimentalVectorWideningLegalization) {
20571 // If we are legalizing vectors by widening, we already have the desired
20572 // legal vector type, just return it.
20573 Results.push_back(ToVecInt);
20577 SmallVector<SDValue, 8> Elts;
20578 for (unsigned i = 0, e = NumElts; i != e; ++i)
20579 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
20580 ToVecInt, DAG.getIntPtrConstant(i, dl)));
20582 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
20587 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
20588 switch ((X86ISD::NodeType)Opcode) {
20589 case X86ISD::FIRST_NUMBER: break;
20590 case X86ISD::BSF: return "X86ISD::BSF";
20591 case X86ISD::BSR: return "X86ISD::BSR";
20592 case X86ISD::SHLD: return "X86ISD::SHLD";
20593 case X86ISD::SHRD: return "X86ISD::SHRD";
20594 case X86ISD::FAND: return "X86ISD::FAND";
20595 case X86ISD::FANDN: return "X86ISD::FANDN";
20596 case X86ISD::FOR: return "X86ISD::FOR";
20597 case X86ISD::FXOR: return "X86ISD::FXOR";
20598 case X86ISD::FILD: return "X86ISD::FILD";
20599 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
20600 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
20601 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
20602 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
20603 case X86ISD::FLD: return "X86ISD::FLD";
20604 case X86ISD::FST: return "X86ISD::FST";
20605 case X86ISD::CALL: return "X86ISD::CALL";
20606 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
20607 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
20608 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
20609 case X86ISD::BT: return "X86ISD::BT";
20610 case X86ISD::CMP: return "X86ISD::CMP";
20611 case X86ISD::COMI: return "X86ISD::COMI";
20612 case X86ISD::UCOMI: return "X86ISD::UCOMI";
20613 case X86ISD::CMPM: return "X86ISD::CMPM";
20614 case X86ISD::CMPMU: return "X86ISD::CMPMU";
20615 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
20616 case X86ISD::SETCC: return "X86ISD::SETCC";
20617 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
20618 case X86ISD::FSETCC: return "X86ISD::FSETCC";
20619 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
20620 case X86ISD::CMOV: return "X86ISD::CMOV";
20621 case X86ISD::BRCOND: return "X86ISD::BRCOND";
20622 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
20623 case X86ISD::IRET: return "X86ISD::IRET";
20624 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
20625 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
20626 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
20627 case X86ISD::Wrapper: return "X86ISD::Wrapper";
20628 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
20629 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
20630 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
20631 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
20632 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
20633 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
20634 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
20635 case X86ISD::PINSRB: return "X86ISD::PINSRB";
20636 case X86ISD::PINSRW: return "X86ISD::PINSRW";
20637 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
20638 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
20639 case X86ISD::ANDNP: return "X86ISD::ANDNP";
20640 case X86ISD::PSIGN: return "X86ISD::PSIGN";
20641 case X86ISD::BLENDI: return "X86ISD::BLENDI";
20642 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
20643 case X86ISD::ADDUS: return "X86ISD::ADDUS";
20644 case X86ISD::SUBUS: return "X86ISD::SUBUS";
20645 case X86ISD::HADD: return "X86ISD::HADD";
20646 case X86ISD::HSUB: return "X86ISD::HSUB";
20647 case X86ISD::FHADD: return "X86ISD::FHADD";
20648 case X86ISD::FHSUB: return "X86ISD::FHSUB";
20649 case X86ISD::ABS: return "X86ISD::ABS";
20650 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20651 case X86ISD::FMAX: return "X86ISD::FMAX";
20652 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20653 case X86ISD::FMIN: return "X86ISD::FMIN";
20654 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20655 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20656 case X86ISD::FMINC: return "X86ISD::FMINC";
20657 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20658 case X86ISD::FRCP: return "X86ISD::FRCP";
20659 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20660 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20661 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20662 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20663 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20664 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20665 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20666 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20667 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20668 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20669 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20670 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20671 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20672 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20673 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20674 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20675 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20676 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20677 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20678 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20679 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20680 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20681 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20682 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20683 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20684 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20685 case X86ISD::CVT2MASK: return "X86ISD::CVT2MASK";
20686 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20687 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20688 case X86ISD::VSHL: return "X86ISD::VSHL";
20689 case X86ISD::VSRL: return "X86ISD::VSRL";
20690 case X86ISD::VSRA: return "X86ISD::VSRA";
20691 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20692 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20693 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20694 case X86ISD::CMPP: return "X86ISD::CMPP";
20695 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20696 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20697 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20698 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20699 case X86ISD::ADD: return "X86ISD::ADD";
20700 case X86ISD::SUB: return "X86ISD::SUB";
20701 case X86ISD::ADC: return "X86ISD::ADC";
20702 case X86ISD::SBB: return "X86ISD::SBB";
20703 case X86ISD::SMUL: return "X86ISD::SMUL";
20704 case X86ISD::UMUL: return "X86ISD::UMUL";
20705 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20706 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20707 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20708 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20709 case X86ISD::INC: return "X86ISD::INC";
20710 case X86ISD::DEC: return "X86ISD::DEC";
20711 case X86ISD::OR: return "X86ISD::OR";
20712 case X86ISD::XOR: return "X86ISD::XOR";
20713 case X86ISD::AND: return "X86ISD::AND";
20714 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20715 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20716 case X86ISD::PTEST: return "X86ISD::PTEST";
20717 case X86ISD::TESTP: return "X86ISD::TESTP";
20718 case X86ISD::TESTM: return "X86ISD::TESTM";
20719 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20720 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20721 case X86ISD::KTEST: return "X86ISD::KTEST";
20722 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20723 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20724 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20725 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20726 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20727 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20728 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20729 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20730 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20731 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20732 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20733 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20734 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20735 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20736 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20737 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20738 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20739 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20740 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20741 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20742 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20743 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20744 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20745 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20746 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20747 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20748 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20749 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20750 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20751 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20752 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20753 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20754 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20755 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20756 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20757 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20758 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20759 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20760 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20761 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20762 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20763 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20764 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20765 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20766 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20767 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20768 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20769 case X86ISD::SAHF: return "X86ISD::SAHF";
20770 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20771 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20772 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20773 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20774 case X86ISD::VPROT: return "X86ISD::VPROT";
20775 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20776 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20777 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20778 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20779 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20780 case X86ISD::FMADD: return "X86ISD::FMADD";
20781 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20782 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20783 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20784 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20785 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20786 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20787 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20788 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20789 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20790 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20791 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20792 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20793 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20794 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20795 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20796 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20797 case X86ISD::XTEST: return "X86ISD::XTEST";
20798 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20799 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20800 case X86ISD::SELECT: return "X86ISD::SELECT";
20801 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20802 case X86ISD::RCP28: return "X86ISD::RCP28";
20803 case X86ISD::EXP2: return "X86ISD::EXP2";
20804 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20805 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20806 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20807 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20808 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20809 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20810 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20811 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20812 case X86ISD::ADDS: return "X86ISD::ADDS";
20813 case X86ISD::SUBS: return "X86ISD::SUBS";
20814 case X86ISD::AVG: return "X86ISD::AVG";
20815 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20816 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20817 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20818 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20819 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20820 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20821 case X86ISD::VFPCLASSS: return "X86ISD::VFPCLASSS";
20826 // isLegalAddressingMode - Return true if the addressing mode represented
20827 // by AM is legal for this target, for a load/store of the specified type.
20828 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20829 const AddrMode &AM, Type *Ty,
20830 unsigned AS) const {
20831 // X86 supports extremely general addressing modes.
20832 CodeModel::Model M = getTargetMachine().getCodeModel();
20833 Reloc::Model R = getTargetMachine().getRelocationModel();
20835 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20836 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20841 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20843 // If a reference to this global requires an extra load, we can't fold it.
20844 if (isGlobalStubReference(GVFlags))
20847 // If BaseGV requires a register for the PIC base, we cannot also have a
20848 // BaseReg specified.
20849 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20852 // If lower 4G is not available, then we must use rip-relative addressing.
20853 if ((M != CodeModel::Small || R != Reloc::Static) &&
20854 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20858 switch (AM.Scale) {
20864 // These scales always work.
20869 // These scales are formed with basereg+scalereg. Only accept if there is
20874 default: // Other stuff never works.
20881 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20882 unsigned Bits = Ty->getScalarSizeInBits();
20884 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20885 // particularly cheaper than those without.
20889 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20890 // variable shifts just as cheap as scalar ones.
20891 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20894 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20895 // fully general vector.
20899 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20900 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20902 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20903 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20904 return NumBits1 > NumBits2;
20907 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20908 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20911 if (!isTypeLegal(EVT::getEVT(Ty1)))
20914 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20916 // Assuming the caller doesn't have a zeroext or signext return parameter,
20917 // truncation all the way down to i1 is valid.
20921 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20922 return isInt<32>(Imm);
20925 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20926 // Can also use sub to handle negated immediates.
20927 return isInt<32>(Imm);
20930 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20931 if (!VT1.isInteger() || !VT2.isInteger())
20933 unsigned NumBits1 = VT1.getSizeInBits();
20934 unsigned NumBits2 = VT2.getSizeInBits();
20935 return NumBits1 > NumBits2;
20938 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20939 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20940 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20943 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20944 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20945 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20948 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20949 EVT VT1 = Val.getValueType();
20950 if (isZExtFree(VT1, VT2))
20953 if (Val.getOpcode() != ISD::LOAD)
20956 if (!VT1.isSimple() || !VT1.isInteger() ||
20957 !VT2.isSimple() || !VT2.isInteger())
20960 switch (VT1.getSimpleVT().SimpleTy) {
20965 // X86 has 8, 16, and 32-bit zero-extending loads.
20972 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20975 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20976 if (!Subtarget->hasAnyFMA())
20979 VT = VT.getScalarType();
20981 if (!VT.isSimple())
20984 switch (VT.getSimpleVT().SimpleTy) {
20995 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20996 // i16 instructions are longer (0x66 prefix) and potentially slower.
20997 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
21000 /// isShuffleMaskLegal - Targets can use this to indicate that they only
21001 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
21002 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
21003 /// are assumed to be legal.
21005 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
21007 if (!VT.isSimple())
21010 // Not for i1 vectors
21011 if (VT.getSimpleVT().getScalarType() == MVT::i1)
21014 // Very little shuffling can be done for 64-bit vectors right now.
21015 if (VT.getSimpleVT().getSizeInBits() == 64)
21018 // We only care that the types being shuffled are legal. The lowering can
21019 // handle any possible shuffle mask that results.
21020 return isTypeLegal(VT.getSimpleVT());
21024 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
21026 // Just delegate to the generic legality, clear masks aren't special.
21027 return isShuffleMaskLegal(Mask, VT);
21030 //===----------------------------------------------------------------------===//
21031 // X86 Scheduler Hooks
21032 //===----------------------------------------------------------------------===//
21034 /// Utility function to emit xbegin specifying the start of an RTM region.
21035 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
21036 const TargetInstrInfo *TII) {
21037 DebugLoc DL = MI->getDebugLoc();
21039 const BasicBlock *BB = MBB->getBasicBlock();
21040 MachineFunction::iterator I = ++MBB->getIterator();
21042 // For the v = xbegin(), we generate
21053 MachineBasicBlock *thisMBB = MBB;
21054 MachineFunction *MF = MBB->getParent();
21055 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21056 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21057 MF->insert(I, mainMBB);
21058 MF->insert(I, sinkMBB);
21060 // Transfer the remainder of BB and its successor edges to sinkMBB.
21061 sinkMBB->splice(sinkMBB->begin(), MBB,
21062 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21063 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21067 // # fallthrough to mainMBB
21068 // # abortion to sinkMBB
21069 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
21070 thisMBB->addSuccessor(mainMBB);
21071 thisMBB->addSuccessor(sinkMBB);
21075 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
21076 mainMBB->addSuccessor(sinkMBB);
21079 // EAX is live into the sinkMBB
21080 sinkMBB->addLiveIn(X86::EAX);
21081 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21082 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
21085 MI->eraseFromParent();
21089 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
21090 // or XMM0_V32I8 in AVX all of this code can be replaced with that
21091 // in the .td file.
21092 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
21093 const TargetInstrInfo *TII) {
21095 switch (MI->getOpcode()) {
21096 default: llvm_unreachable("illegal opcode!");
21097 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
21098 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
21099 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
21100 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
21101 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
21102 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
21103 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
21104 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
21107 DebugLoc dl = MI->getDebugLoc();
21108 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
21110 unsigned NumArgs = MI->getNumOperands();
21111 for (unsigned i = 1; i < NumArgs; ++i) {
21112 MachineOperand &Op = MI->getOperand(i);
21113 if (!(Op.isReg() && Op.isImplicit()))
21114 MIB.addOperand(Op);
21116 if (MI->hasOneMemOperand())
21117 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
21119 BuildMI(*BB, MI, dl,
21120 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
21121 .addReg(X86::XMM0);
21123 MI->eraseFromParent();
21127 // FIXME: Custom handling because TableGen doesn't support multiple implicit
21128 // defs in an instruction pattern
21129 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
21130 const TargetInstrInfo *TII) {
21132 switch (MI->getOpcode()) {
21133 default: llvm_unreachable("illegal opcode!");
21134 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
21135 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
21136 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
21137 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
21138 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
21139 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
21140 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
21141 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
21144 DebugLoc dl = MI->getDebugLoc();
21145 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
21147 unsigned NumArgs = MI->getNumOperands(); // remove the results
21148 for (unsigned i = 1; i < NumArgs; ++i) {
21149 MachineOperand &Op = MI->getOperand(i);
21150 if (!(Op.isReg() && Op.isImplicit()))
21151 MIB.addOperand(Op);
21153 if (MI->hasOneMemOperand())
21154 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
21156 BuildMI(*BB, MI, dl,
21157 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
21160 MI->eraseFromParent();
21164 static MachineBasicBlock *EmitWRPKRU(MachineInstr *MI, MachineBasicBlock *BB,
21165 const X86Subtarget *Subtarget) {
21166 DebugLoc dl = MI->getDebugLoc();
21167 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21169 // insert input VAL into EAX
21170 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
21171 .addReg(MI->getOperand(0).getReg());
21172 // insert zero to ECX
21173 BuildMI(*BB, MI, dl, TII->get(X86::XOR32rr), X86::ECX)
21176 // insert zero to EDX
21177 BuildMI(*BB, MI, dl, TII->get(X86::XOR32rr), X86::EDX)
21180 // insert WRPKRU instruction
21181 BuildMI(*BB, MI, dl, TII->get(X86::WRPKRUr));
21183 MI->eraseFromParent(); // The pseudo is gone now.
21187 static MachineBasicBlock *EmitRDPKRU(MachineInstr *MI, MachineBasicBlock *BB,
21188 const X86Subtarget *Subtarget) {
21189 DebugLoc dl = MI->getDebugLoc();
21190 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21192 // insert zero to ECX
21193 BuildMI(*BB, MI, dl, TII->get(X86::XOR32rr), X86::ECX)
21196 // insert RDPKRU instruction
21197 BuildMI(*BB, MI, dl, TII->get(X86::RDPKRUr));
21198 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
21201 MI->eraseFromParent(); // The pseudo is gone now.
21205 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
21206 const X86Subtarget *Subtarget) {
21207 DebugLoc dl = MI->getDebugLoc();
21208 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21209 // Address into RAX/EAX, other two args into ECX, EDX.
21210 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
21211 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
21212 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
21213 for (int i = 0; i < X86::AddrNumOperands; ++i)
21214 MIB.addOperand(MI->getOperand(i));
21216 unsigned ValOps = X86::AddrNumOperands;
21217 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
21218 .addReg(MI->getOperand(ValOps).getReg());
21219 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
21220 .addReg(MI->getOperand(ValOps+1).getReg());
21222 // The instruction doesn't actually take any operands though.
21223 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
21225 MI->eraseFromParent(); // The pseudo is gone now.
21229 MachineBasicBlock *
21230 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
21231 MachineBasicBlock *MBB) const {
21232 // Emit va_arg instruction on X86-64.
21234 // Operands to this pseudo-instruction:
21235 // 0 ) Output : destination address (reg)
21236 // 1-5) Input : va_list address (addr, i64mem)
21237 // 6 ) ArgSize : Size (in bytes) of vararg type
21238 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
21239 // 8 ) Align : Alignment of type
21240 // 9 ) EFLAGS (implicit-def)
21242 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
21243 static_assert(X86::AddrNumOperands == 5,
21244 "VAARG_64 assumes 5 address operands");
21246 unsigned DestReg = MI->getOperand(0).getReg();
21247 MachineOperand &Base = MI->getOperand(1);
21248 MachineOperand &Scale = MI->getOperand(2);
21249 MachineOperand &Index = MI->getOperand(3);
21250 MachineOperand &Disp = MI->getOperand(4);
21251 MachineOperand &Segment = MI->getOperand(5);
21252 unsigned ArgSize = MI->getOperand(6).getImm();
21253 unsigned ArgMode = MI->getOperand(7).getImm();
21254 unsigned Align = MI->getOperand(8).getImm();
21256 // Memory Reference
21257 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
21258 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21259 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21261 // Machine Information
21262 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21263 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
21264 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
21265 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
21266 DebugLoc DL = MI->getDebugLoc();
21268 // struct va_list {
21271 // i64 overflow_area (address)
21272 // i64 reg_save_area (address)
21274 // sizeof(va_list) = 24
21275 // alignment(va_list) = 8
21277 unsigned TotalNumIntRegs = 6;
21278 unsigned TotalNumXMMRegs = 8;
21279 bool UseGPOffset = (ArgMode == 1);
21280 bool UseFPOffset = (ArgMode == 2);
21281 unsigned MaxOffset = TotalNumIntRegs * 8 +
21282 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
21284 /* Align ArgSize to a multiple of 8 */
21285 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
21286 bool NeedsAlign = (Align > 8);
21288 MachineBasicBlock *thisMBB = MBB;
21289 MachineBasicBlock *overflowMBB;
21290 MachineBasicBlock *offsetMBB;
21291 MachineBasicBlock *endMBB;
21293 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
21294 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
21295 unsigned OffsetReg = 0;
21297 if (!UseGPOffset && !UseFPOffset) {
21298 // If we only pull from the overflow region, we don't create a branch.
21299 // We don't need to alter control flow.
21300 OffsetDestReg = 0; // unused
21301 OverflowDestReg = DestReg;
21303 offsetMBB = nullptr;
21304 overflowMBB = thisMBB;
21307 // First emit code to check if gp_offset (or fp_offset) is below the bound.
21308 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
21309 // If not, pull from overflow_area. (branch to overflowMBB)
21314 // offsetMBB overflowMBB
21319 // Registers for the PHI in endMBB
21320 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
21321 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
21323 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
21324 MachineFunction *MF = MBB->getParent();
21325 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21326 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21327 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21329 MachineFunction::iterator MBBIter = ++MBB->getIterator();
21331 // Insert the new basic blocks
21332 MF->insert(MBBIter, offsetMBB);
21333 MF->insert(MBBIter, overflowMBB);
21334 MF->insert(MBBIter, endMBB);
21336 // Transfer the remainder of MBB and its successor edges to endMBB.
21337 endMBB->splice(endMBB->begin(), thisMBB,
21338 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
21339 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
21341 // Make offsetMBB and overflowMBB successors of thisMBB
21342 thisMBB->addSuccessor(offsetMBB);
21343 thisMBB->addSuccessor(overflowMBB);
21345 // endMBB is a successor of both offsetMBB and overflowMBB
21346 offsetMBB->addSuccessor(endMBB);
21347 overflowMBB->addSuccessor(endMBB);
21349 // Load the offset value into a register
21350 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
21351 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
21355 .addDisp(Disp, UseFPOffset ? 4 : 0)
21356 .addOperand(Segment)
21357 .setMemRefs(MMOBegin, MMOEnd);
21359 // Check if there is enough room left to pull this argument.
21360 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
21362 .addImm(MaxOffset + 8 - ArgSizeA8);
21364 // Branch to "overflowMBB" if offset >= max
21365 // Fall through to "offsetMBB" otherwise
21366 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
21367 .addMBB(overflowMBB);
21370 // In offsetMBB, emit code to use the reg_save_area.
21372 assert(OffsetReg != 0);
21374 // Read the reg_save_area address.
21375 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
21376 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
21381 .addOperand(Segment)
21382 .setMemRefs(MMOBegin, MMOEnd);
21384 // Zero-extend the offset
21385 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
21386 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
21389 .addImm(X86::sub_32bit);
21391 // Add the offset to the reg_save_area to get the final address.
21392 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
21393 .addReg(OffsetReg64)
21394 .addReg(RegSaveReg);
21396 // Compute the offset for the next argument
21397 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
21398 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
21400 .addImm(UseFPOffset ? 16 : 8);
21402 // Store it back into the va_list.
21403 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
21407 .addDisp(Disp, UseFPOffset ? 4 : 0)
21408 .addOperand(Segment)
21409 .addReg(NextOffsetReg)
21410 .setMemRefs(MMOBegin, MMOEnd);
21413 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
21418 // Emit code to use overflow area
21421 // Load the overflow_area address into a register.
21422 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
21423 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
21428 .addOperand(Segment)
21429 .setMemRefs(MMOBegin, MMOEnd);
21431 // If we need to align it, do so. Otherwise, just copy the address
21432 // to OverflowDestReg.
21434 // Align the overflow address
21435 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
21436 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
21438 // aligned_addr = (addr + (align-1)) & ~(align-1)
21439 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
21440 .addReg(OverflowAddrReg)
21443 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
21445 .addImm(~(uint64_t)(Align-1));
21447 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
21448 .addReg(OverflowAddrReg);
21451 // Compute the next overflow address after this argument.
21452 // (the overflow address should be kept 8-byte aligned)
21453 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
21454 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
21455 .addReg(OverflowDestReg)
21456 .addImm(ArgSizeA8);
21458 // Store the new overflow address.
21459 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
21464 .addOperand(Segment)
21465 .addReg(NextAddrReg)
21466 .setMemRefs(MMOBegin, MMOEnd);
21468 // If we branched, emit the PHI to the front of endMBB.
21470 BuildMI(*endMBB, endMBB->begin(), DL,
21471 TII->get(X86::PHI), DestReg)
21472 .addReg(OffsetDestReg).addMBB(offsetMBB)
21473 .addReg(OverflowDestReg).addMBB(overflowMBB);
21476 // Erase the pseudo instruction
21477 MI->eraseFromParent();
21482 MachineBasicBlock *
21483 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
21485 MachineBasicBlock *MBB) const {
21486 // Emit code to save XMM registers to the stack. The ABI says that the
21487 // number of registers to save is given in %al, so it's theoretically
21488 // possible to do an indirect jump trick to avoid saving all of them,
21489 // however this code takes a simpler approach and just executes all
21490 // of the stores if %al is non-zero. It's less code, and it's probably
21491 // easier on the hardware branch predictor, and stores aren't all that
21492 // expensive anyway.
21494 // Create the new basic blocks. One block contains all the XMM stores,
21495 // and one block is the final destination regardless of whether any
21496 // stores were performed.
21497 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
21498 MachineFunction *F = MBB->getParent();
21499 MachineFunction::iterator MBBIter = ++MBB->getIterator();
21500 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
21501 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
21502 F->insert(MBBIter, XMMSaveMBB);
21503 F->insert(MBBIter, EndMBB);
21505 // Transfer the remainder of MBB and its successor edges to EndMBB.
21506 EndMBB->splice(EndMBB->begin(), MBB,
21507 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21508 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
21510 // The original block will now fall through to the XMM save block.
21511 MBB->addSuccessor(XMMSaveMBB);
21512 // The XMMSaveMBB will fall through to the end block.
21513 XMMSaveMBB->addSuccessor(EndMBB);
21515 // Now add the instructions.
21516 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21517 DebugLoc DL = MI->getDebugLoc();
21519 unsigned CountReg = MI->getOperand(0).getReg();
21520 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
21521 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
21523 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
21524 // If %al is 0, branch around the XMM save block.
21525 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
21526 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
21527 MBB->addSuccessor(EndMBB);
21530 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
21531 // that was just emitted, but clearly shouldn't be "saved".
21532 assert((MI->getNumOperands() <= 3 ||
21533 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
21534 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
21535 && "Expected last argument to be EFLAGS");
21536 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
21537 // In the XMM save block, save all the XMM argument registers.
21538 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
21539 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
21540 MachineMemOperand *MMO = F->getMachineMemOperand(
21541 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
21542 MachineMemOperand::MOStore,
21543 /*Size=*/16, /*Align=*/16);
21544 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
21545 .addFrameIndex(RegSaveFrameIndex)
21546 .addImm(/*Scale=*/1)
21547 .addReg(/*IndexReg=*/0)
21548 .addImm(/*Disp=*/Offset)
21549 .addReg(/*Segment=*/0)
21550 .addReg(MI->getOperand(i).getReg())
21551 .addMemOperand(MMO);
21554 MI->eraseFromParent(); // The pseudo instruction is gone now.
21559 // The EFLAGS operand of SelectItr might be missing a kill marker
21560 // because there were multiple uses of EFLAGS, and ISel didn't know
21561 // which to mark. Figure out whether SelectItr should have had a
21562 // kill marker, and set it if it should. Returns the correct kill
21564 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
21565 MachineBasicBlock* BB,
21566 const TargetRegisterInfo* TRI) {
21567 // Scan forward through BB for a use/def of EFLAGS.
21568 MachineBasicBlock::iterator miI(std::next(SelectItr));
21569 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
21570 const MachineInstr& mi = *miI;
21571 if (mi.readsRegister(X86::EFLAGS))
21573 if (mi.definesRegister(X86::EFLAGS))
21574 break; // Should have kill-flag - update below.
21577 // If we hit the end of the block, check whether EFLAGS is live into a
21579 if (miI == BB->end()) {
21580 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
21581 sEnd = BB->succ_end();
21582 sItr != sEnd; ++sItr) {
21583 MachineBasicBlock* succ = *sItr;
21584 if (succ->isLiveIn(X86::EFLAGS))
21589 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
21590 // out. SelectMI should have a kill flag on EFLAGS.
21591 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
21595 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
21596 // together with other CMOV pseudo-opcodes into a single basic-block with
21597 // conditional jump around it.
21598 static bool isCMOVPseudo(MachineInstr *MI) {
21599 switch (MI->getOpcode()) {
21600 case X86::CMOV_FR32:
21601 case X86::CMOV_FR64:
21602 case X86::CMOV_GR8:
21603 case X86::CMOV_GR16:
21604 case X86::CMOV_GR32:
21605 case X86::CMOV_RFP32:
21606 case X86::CMOV_RFP64:
21607 case X86::CMOV_RFP80:
21608 case X86::CMOV_V2F64:
21609 case X86::CMOV_V2I64:
21610 case X86::CMOV_V4F32:
21611 case X86::CMOV_V4F64:
21612 case X86::CMOV_V4I64:
21613 case X86::CMOV_V16F32:
21614 case X86::CMOV_V8F32:
21615 case X86::CMOV_V8F64:
21616 case X86::CMOV_V8I64:
21617 case X86::CMOV_V8I1:
21618 case X86::CMOV_V16I1:
21619 case X86::CMOV_V32I1:
21620 case X86::CMOV_V64I1:
21628 MachineBasicBlock *
21629 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
21630 MachineBasicBlock *BB) const {
21631 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21632 DebugLoc DL = MI->getDebugLoc();
21634 // To "insert" a SELECT_CC instruction, we actually have to insert the
21635 // diamond control-flow pattern. The incoming instruction knows the
21636 // destination vreg to set, the condition code register to branch on, the
21637 // true/false values to select between, and a branch opcode to use.
21638 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21639 MachineFunction::iterator It = ++BB->getIterator();
21644 // cmpTY ccX, r1, r2
21646 // fallthrough --> copy0MBB
21647 MachineBasicBlock *thisMBB = BB;
21648 MachineFunction *F = BB->getParent();
21650 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
21651 // as described above, by inserting a BB, and then making a PHI at the join
21652 // point to select the true and false operands of the CMOV in the PHI.
21654 // The code also handles two different cases of multiple CMOV opcodes
21658 // In this case, there are multiple CMOVs in a row, all which are based on
21659 // the same condition setting (or the exact opposite condition setting).
21660 // In this case we can lower all the CMOVs using a single inserted BB, and
21661 // then make a number of PHIs at the join point to model the CMOVs. The only
21662 // trickiness here, is that in a case like:
21664 // t2 = CMOV cond1 t1, f1
21665 // t3 = CMOV cond1 t2, f2
21667 // when rewriting this into PHIs, we have to perform some renaming on the
21668 // temps since you cannot have a PHI operand refer to a PHI result earlier
21669 // in the same block. The "simple" but wrong lowering would be:
21671 // t2 = PHI t1(BB1), f1(BB2)
21672 // t3 = PHI t2(BB1), f2(BB2)
21674 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
21675 // renaming is to note that on the path through BB1, t2 is really just a
21676 // copy of t1, and do that renaming, properly generating:
21678 // t2 = PHI t1(BB1), f1(BB2)
21679 // t3 = PHI t1(BB1), f2(BB2)
21681 // Case 2, we lower cascaded CMOVs such as
21683 // (CMOV (CMOV F, T, cc1), T, cc2)
21685 // to two successives branches. For that, we look for another CMOV as the
21686 // following instruction.
21688 // Without this, we would add a PHI between the two jumps, which ends up
21689 // creating a few copies all around. For instance, for
21691 // (sitofp (zext (fcmp une)))
21693 // we would generate:
21695 // ucomiss %xmm1, %xmm0
21696 // movss <1.0f>, %xmm0
21697 // movaps %xmm0, %xmm1
21699 // xorps %xmm1, %xmm1
21702 // movaps %xmm1, %xmm0
21706 // because this custom-inserter would have generated:
21718 // A: X = ...; Y = ...
21720 // C: Z = PHI [X, A], [Y, B]
21722 // E: PHI [X, C], [Z, D]
21724 // If we lower both CMOVs in a single step, we can instead generate:
21736 // A: X = ...; Y = ...
21738 // E: PHI [X, A], [X, C], [Y, D]
21740 // Which, in our sitofp/fcmp example, gives us something like:
21742 // ucomiss %xmm1, %xmm0
21743 // movss <1.0f>, %xmm0
21746 // xorps %xmm0, %xmm0
21750 MachineInstr *CascadedCMOV = nullptr;
21751 MachineInstr *LastCMOV = MI;
21752 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21753 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21754 MachineBasicBlock::iterator NextMIIt =
21755 std::next(MachineBasicBlock::iterator(MI));
21757 // Check for case 1, where there are multiple CMOVs with the same condition
21758 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21759 // number of jumps the most.
21761 if (isCMOVPseudo(MI)) {
21762 // See if we have a string of CMOVS with the same condition.
21763 while (NextMIIt != BB->end() &&
21764 isCMOVPseudo(NextMIIt) &&
21765 (NextMIIt->getOperand(3).getImm() == CC ||
21766 NextMIIt->getOperand(3).getImm() == OppCC)) {
21767 LastCMOV = &*NextMIIt;
21772 // This checks for case 2, but only do this if we didn't already find
21773 // case 1, as indicated by LastCMOV == MI.
21774 if (LastCMOV == MI &&
21775 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21776 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21777 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21778 CascadedCMOV = &*NextMIIt;
21781 MachineBasicBlock *jcc1MBB = nullptr;
21783 // If we have a cascaded CMOV, we lower it to two successive branches to
21784 // the same block. EFLAGS is used by both, so mark it as live in the second.
21785 if (CascadedCMOV) {
21786 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21787 F->insert(It, jcc1MBB);
21788 jcc1MBB->addLiveIn(X86::EFLAGS);
21791 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21792 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21793 F->insert(It, copy0MBB);
21794 F->insert(It, sinkMBB);
21796 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21797 // live into the sink and copy blocks.
21798 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21800 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21801 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21802 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21803 copy0MBB->addLiveIn(X86::EFLAGS);
21804 sinkMBB->addLiveIn(X86::EFLAGS);
21807 // Transfer the remainder of BB and its successor edges to sinkMBB.
21808 sinkMBB->splice(sinkMBB->begin(), BB,
21809 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21810 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21812 // Add the true and fallthrough blocks as its successors.
21813 if (CascadedCMOV) {
21814 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21815 BB->addSuccessor(jcc1MBB);
21817 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21818 // jump to the sinkMBB.
21819 jcc1MBB->addSuccessor(copy0MBB);
21820 jcc1MBB->addSuccessor(sinkMBB);
21822 BB->addSuccessor(copy0MBB);
21825 // The true block target of the first (or only) branch is always sinkMBB.
21826 BB->addSuccessor(sinkMBB);
21828 // Create the conditional branch instruction.
21829 unsigned Opc = X86::GetCondBranchFromCond(CC);
21830 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21832 if (CascadedCMOV) {
21833 unsigned Opc2 = X86::GetCondBranchFromCond(
21834 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21835 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21839 // %FalseValue = ...
21840 // # fallthrough to sinkMBB
21841 copy0MBB->addSuccessor(sinkMBB);
21844 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21846 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21847 MachineBasicBlock::iterator MIItEnd =
21848 std::next(MachineBasicBlock::iterator(LastCMOV));
21849 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21850 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21851 MachineInstrBuilder MIB;
21853 // As we are creating the PHIs, we have to be careful if there is more than
21854 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21855 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21856 // That also means that PHI construction must work forward from earlier to
21857 // later, and that the code must maintain a mapping from earlier PHI's
21858 // destination registers, and the registers that went into the PHI.
21860 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21861 unsigned DestReg = MIIt->getOperand(0).getReg();
21862 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21863 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21865 // If this CMOV we are generating is the opposite condition from
21866 // the jump we generated, then we have to swap the operands for the
21867 // PHI that is going to be generated.
21868 if (MIIt->getOperand(3).getImm() == OppCC)
21869 std::swap(Op1Reg, Op2Reg);
21871 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21872 Op1Reg = RegRewriteTable[Op1Reg].first;
21874 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21875 Op2Reg = RegRewriteTable[Op2Reg].second;
21877 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21878 TII->get(X86::PHI), DestReg)
21879 .addReg(Op1Reg).addMBB(copy0MBB)
21880 .addReg(Op2Reg).addMBB(thisMBB);
21882 // Add this PHI to the rewrite table.
21883 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21886 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21887 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21888 if (CascadedCMOV) {
21889 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21890 // Copy the PHI result to the register defined by the second CMOV.
21891 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21892 DL, TII->get(TargetOpcode::COPY),
21893 CascadedCMOV->getOperand(0).getReg())
21894 .addReg(MI->getOperand(0).getReg());
21895 CascadedCMOV->eraseFromParent();
21898 // Now remove the CMOV(s).
21899 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21900 (MIIt++)->eraseFromParent();
21905 MachineBasicBlock *
21906 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21907 MachineBasicBlock *BB) const {
21908 // Combine the following atomic floating-point modification pattern:
21909 // a.store(reg OP a.load(acquire), release)
21910 // Transform them into:
21911 // OPss (%gpr), %xmm
21912 // movss %xmm, (%gpr)
21913 // Or sd equivalent for 64-bit operations.
21915 switch (MI->getOpcode()) {
21916 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21917 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21918 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21920 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21921 DebugLoc DL = MI->getDebugLoc();
21922 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21923 MachineOperand MSrc = MI->getOperand(0);
21924 unsigned VSrc = MI->getOperand(5).getReg();
21925 const MachineOperand &Disp = MI->getOperand(3);
21926 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21927 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21928 if (hasDisp && MSrc.isReg())
21929 MSrc.setIsKill(false);
21930 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21931 .addOperand(/*Base=*/MSrc)
21932 .addImm(/*Scale=*/1)
21933 .addReg(/*Index=*/0)
21934 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21936 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21937 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21939 .addOperand(/*Base=*/MSrc)
21940 .addImm(/*Scale=*/1)
21941 .addReg(/*Index=*/0)
21942 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21943 .addReg(/*Segment=*/0);
21944 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21945 MI->eraseFromParent(); // The pseudo instruction is gone now.
21949 MachineBasicBlock *
21950 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21951 MachineBasicBlock *BB) const {
21952 MachineFunction *MF = BB->getParent();
21953 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21954 DebugLoc DL = MI->getDebugLoc();
21955 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21957 assert(MF->shouldSplitStack());
21959 const bool Is64Bit = Subtarget->is64Bit();
21960 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21962 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21963 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21966 // ... [Till the alloca]
21967 // If stacklet is not large enough, jump to mallocMBB
21970 // Allocate by subtracting from RSP
21971 // Jump to continueMBB
21974 // Allocate by call to runtime
21978 // [rest of original BB]
21981 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21982 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21983 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21985 MachineRegisterInfo &MRI = MF->getRegInfo();
21986 const TargetRegisterClass *AddrRegClass =
21987 getRegClassFor(getPointerTy(MF->getDataLayout()));
21989 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21990 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21991 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21992 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21993 sizeVReg = MI->getOperand(1).getReg(),
21994 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21996 MachineFunction::iterator MBBIter = ++BB->getIterator();
21998 MF->insert(MBBIter, bumpMBB);
21999 MF->insert(MBBIter, mallocMBB);
22000 MF->insert(MBBIter, continueMBB);
22002 continueMBB->splice(continueMBB->begin(), BB,
22003 std::next(MachineBasicBlock::iterator(MI)), BB->end());
22004 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
22006 // Add code to the main basic block to check if the stack limit has been hit,
22007 // and if so, jump to mallocMBB otherwise to bumpMBB.
22008 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
22009 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
22010 .addReg(tmpSPVReg).addReg(sizeVReg);
22011 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
22012 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
22013 .addReg(SPLimitVReg);
22014 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
22016 // bumpMBB simply decreases the stack pointer, since we know the current
22017 // stacklet has enough space.
22018 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
22019 .addReg(SPLimitVReg);
22020 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
22021 .addReg(SPLimitVReg);
22022 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
22024 // Calls into a routine in libgcc to allocate more space from the heap.
22025 const uint32_t *RegMask =
22026 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
22028 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
22030 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
22031 .addExternalSymbol("__morestack_allocate_stack_space")
22032 .addRegMask(RegMask)
22033 .addReg(X86::RDI, RegState::Implicit)
22034 .addReg(X86::RAX, RegState::ImplicitDefine);
22035 } else if (Is64Bit) {
22036 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
22038 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
22039 .addExternalSymbol("__morestack_allocate_stack_space")
22040 .addRegMask(RegMask)
22041 .addReg(X86::EDI, RegState::Implicit)
22042 .addReg(X86::EAX, RegState::ImplicitDefine);
22044 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
22046 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
22047 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
22048 .addExternalSymbol("__morestack_allocate_stack_space")
22049 .addRegMask(RegMask)
22050 .addReg(X86::EAX, RegState::ImplicitDefine);
22054 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
22057 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
22058 .addReg(IsLP64 ? X86::RAX : X86::EAX);
22059 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
22061 // Set up the CFG correctly.
22062 BB->addSuccessor(bumpMBB);
22063 BB->addSuccessor(mallocMBB);
22064 mallocMBB->addSuccessor(continueMBB);
22065 bumpMBB->addSuccessor(continueMBB);
22067 // Take care of the PHI nodes.
22068 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
22069 MI->getOperand(0).getReg())
22070 .addReg(mallocPtrVReg).addMBB(mallocMBB)
22071 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
22073 // Delete the original pseudo instruction.
22074 MI->eraseFromParent();
22077 return continueMBB;
22080 MachineBasicBlock *
22081 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
22082 MachineBasicBlock *BB) const {
22083 assert(!Subtarget->isTargetMachO());
22084 DebugLoc DL = MI->getDebugLoc();
22085 MachineInstr *ResumeMI = Subtarget->getFrameLowering()->emitStackProbe(
22086 *BB->getParent(), *BB, MI, DL, false);
22087 MachineBasicBlock *ResumeBB = ResumeMI->getParent();
22088 MI->eraseFromParent(); // The pseudo instruction is gone now.
22092 MachineBasicBlock *
22093 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
22094 MachineBasicBlock *BB) const {
22095 MachineFunction *MF = BB->getParent();
22096 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
22097 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
22098 DebugLoc DL = MI->getDebugLoc();
22100 assert(!isAsynchronousEHPersonality(
22101 classifyEHPersonality(MF->getFunction()->getPersonalityFn())) &&
22102 "SEH does not use catchret!");
22104 // Only 32-bit EH needs to worry about manually restoring stack pointers.
22105 if (!Subtarget->is32Bit())
22108 // C++ EH creates a new target block to hold the restore code, and wires up
22109 // the new block to the return destination with a normal JMP_4.
22110 MachineBasicBlock *RestoreMBB =
22111 MF->CreateMachineBasicBlock(BB->getBasicBlock());
22112 assert(BB->succ_size() == 1);
22113 MF->insert(std::next(BB->getIterator()), RestoreMBB);
22114 RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
22115 BB->addSuccessor(RestoreMBB);
22116 MI->getOperand(0).setMBB(RestoreMBB);
22118 auto RestoreMBBI = RestoreMBB->begin();
22119 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
22120 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
22124 MachineBasicBlock *
22125 X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
22126 MachineBasicBlock *BB) const {
22127 MachineFunction *MF = BB->getParent();
22128 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
22129 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
22130 // Only 32-bit SEH requires special handling for catchpad.
22131 if (IsSEH && Subtarget->is32Bit()) {
22132 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
22133 DebugLoc DL = MI->getDebugLoc();
22134 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
22136 MI->eraseFromParent();
22140 MachineBasicBlock *
22141 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
22142 MachineBasicBlock *BB) const {
22143 // This is pretty easy. We're taking the value that we received from
22144 // our load from the relocation, sticking it in either RDI (x86-64)
22145 // or EAX and doing an indirect call. The return value will then
22146 // be in the normal return register.
22147 MachineFunction *F = BB->getParent();
22148 const X86InstrInfo *TII = Subtarget->getInstrInfo();
22149 DebugLoc DL = MI->getDebugLoc();
22151 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
22152 assert(MI->getOperand(3).isGlobal() && "This should be a global");
22154 // Get a register mask for the lowered call.
22155 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
22156 // proper register mask.
22157 const uint32_t *RegMask =
22158 Subtarget->is64Bit() ?
22159 Subtarget->getRegisterInfo()->getDarwinTLSCallPreservedMask() :
22160 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
22161 if (Subtarget->is64Bit()) {
22162 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
22163 TII->get(X86::MOV64rm), X86::RDI)
22165 .addImm(0).addReg(0)
22166 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
22167 MI->getOperand(3).getTargetFlags())
22169 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
22170 addDirectMem(MIB, X86::RDI);
22171 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
22172 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
22173 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
22174 TII->get(X86::MOV32rm), X86::EAX)
22176 .addImm(0).addReg(0)
22177 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
22178 MI->getOperand(3).getTargetFlags())
22180 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
22181 addDirectMem(MIB, X86::EAX);
22182 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
22184 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
22185 TII->get(X86::MOV32rm), X86::EAX)
22186 .addReg(TII->getGlobalBaseReg(F))
22187 .addImm(0).addReg(0)
22188 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
22189 MI->getOperand(3).getTargetFlags())
22191 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
22192 addDirectMem(MIB, X86::EAX);
22193 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
22196 MI->eraseFromParent(); // The pseudo instruction is gone now.
22200 MachineBasicBlock *
22201 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
22202 MachineBasicBlock *MBB) const {
22203 DebugLoc DL = MI->getDebugLoc();
22204 MachineFunction *MF = MBB->getParent();
22205 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22206 MachineRegisterInfo &MRI = MF->getRegInfo();
22208 const BasicBlock *BB = MBB->getBasicBlock();
22209 MachineFunction::iterator I = ++MBB->getIterator();
22211 // Memory Reference
22212 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
22213 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
22216 unsigned MemOpndSlot = 0;
22218 unsigned CurOp = 0;
22220 DstReg = MI->getOperand(CurOp++).getReg();
22221 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
22222 assert(RC->hasType(MVT::i32) && "Invalid destination!");
22223 unsigned mainDstReg = MRI.createVirtualRegister(RC);
22224 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
22226 MemOpndSlot = CurOp;
22228 MVT PVT = getPointerTy(MF->getDataLayout());
22229 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
22230 "Invalid Pointer Size!");
22232 // For v = setjmp(buf), we generate
22235 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
22236 // SjLjSetup restoreMBB
22242 // v = phi(main, restore)
22245 // if base pointer being used, load it from frame
22248 MachineBasicBlock *thisMBB = MBB;
22249 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
22250 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
22251 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
22252 MF->insert(I, mainMBB);
22253 MF->insert(I, sinkMBB);
22254 MF->push_back(restoreMBB);
22255 restoreMBB->setHasAddressTaken();
22257 MachineInstrBuilder MIB;
22259 // Transfer the remainder of BB and its successor edges to sinkMBB.
22260 sinkMBB->splice(sinkMBB->begin(), MBB,
22261 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
22262 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
22265 unsigned PtrStoreOpc = 0;
22266 unsigned LabelReg = 0;
22267 const int64_t LabelOffset = 1 * PVT.getStoreSize();
22268 Reloc::Model RM = MF->getTarget().getRelocationModel();
22269 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
22270 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
22272 // Prepare IP either in reg or imm.
22273 if (!UseImmLabel) {
22274 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
22275 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
22276 LabelReg = MRI.createVirtualRegister(PtrRC);
22277 if (Subtarget->is64Bit()) {
22278 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
22282 .addMBB(restoreMBB)
22285 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
22286 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
22287 .addReg(XII->getGlobalBaseReg(MF))
22290 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
22294 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
22296 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
22297 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22298 if (i == X86::AddrDisp)
22299 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
22301 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
22304 MIB.addReg(LabelReg);
22306 MIB.addMBB(restoreMBB);
22307 MIB.setMemRefs(MMOBegin, MMOEnd);
22309 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
22310 .addMBB(restoreMBB);
22312 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
22313 MIB.addRegMask(RegInfo->getNoPreservedMask());
22314 thisMBB->addSuccessor(mainMBB);
22315 thisMBB->addSuccessor(restoreMBB);
22319 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
22320 mainMBB->addSuccessor(sinkMBB);
22323 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
22324 TII->get(X86::PHI), DstReg)
22325 .addReg(mainDstReg).addMBB(mainMBB)
22326 .addReg(restoreDstReg).addMBB(restoreMBB);
22329 if (RegInfo->hasBasePointer(*MF)) {
22330 const bool Uses64BitFramePtr =
22331 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
22332 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
22333 X86FI->setRestoreBasePointer(MF);
22334 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
22335 unsigned BasePtr = RegInfo->getBaseRegister();
22336 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
22337 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
22338 FramePtr, true, X86FI->getRestoreBasePointerOffset())
22339 .setMIFlag(MachineInstr::FrameSetup);
22341 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
22342 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
22343 restoreMBB->addSuccessor(sinkMBB);
22345 MI->eraseFromParent();
22349 MachineBasicBlock *
22350 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
22351 MachineBasicBlock *MBB) const {
22352 DebugLoc DL = MI->getDebugLoc();
22353 MachineFunction *MF = MBB->getParent();
22354 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22355 MachineRegisterInfo &MRI = MF->getRegInfo();
22357 // Memory Reference
22358 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
22359 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
22361 MVT PVT = getPointerTy(MF->getDataLayout());
22362 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
22363 "Invalid Pointer Size!");
22365 const TargetRegisterClass *RC =
22366 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
22367 unsigned Tmp = MRI.createVirtualRegister(RC);
22368 // Since FP is only updated here but NOT referenced, it's treated as GPR.
22369 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
22370 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
22371 unsigned SP = RegInfo->getStackRegister();
22373 MachineInstrBuilder MIB;
22375 const int64_t LabelOffset = 1 * PVT.getStoreSize();
22376 const int64_t SPOffset = 2 * PVT.getStoreSize();
22378 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
22379 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
22382 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
22383 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
22384 MIB.addOperand(MI->getOperand(i));
22385 MIB.setMemRefs(MMOBegin, MMOEnd);
22387 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
22388 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22389 if (i == X86::AddrDisp)
22390 MIB.addDisp(MI->getOperand(i), LabelOffset);
22392 MIB.addOperand(MI->getOperand(i));
22394 MIB.setMemRefs(MMOBegin, MMOEnd);
22396 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
22397 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22398 if (i == X86::AddrDisp)
22399 MIB.addDisp(MI->getOperand(i), SPOffset);
22401 MIB.addOperand(MI->getOperand(i));
22403 MIB.setMemRefs(MMOBegin, MMOEnd);
22405 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
22407 MI->eraseFromParent();
22411 // Replace 213-type (isel default) FMA3 instructions with 231-type for
22412 // accumulator loops. Writing back to the accumulator allows the coalescer
22413 // to remove extra copies in the loop.
22414 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
22415 MachineBasicBlock *
22416 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
22417 MachineBasicBlock *MBB) const {
22418 MachineOperand &AddendOp = MI->getOperand(3);
22420 // Bail out early if the addend isn't a register - we can't switch these.
22421 if (!AddendOp.isReg())
22424 MachineFunction &MF = *MBB->getParent();
22425 MachineRegisterInfo &MRI = MF.getRegInfo();
22427 // Check whether the addend is defined by a PHI:
22428 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
22429 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
22430 if (!AddendDef.isPHI())
22433 // Look for the following pattern:
22435 // %addend = phi [%entry, 0], [%loop, %result]
22437 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
22441 // %addend = phi [%entry, 0], [%loop, %result]
22443 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
22445 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
22446 assert(AddendDef.getOperand(i).isReg());
22447 MachineOperand PHISrcOp = AddendDef.getOperand(i);
22448 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
22449 if (&PHISrcInst == MI) {
22450 // Found a matching instruction.
22451 unsigned NewFMAOpc = 0;
22452 switch (MI->getOpcode()) {
22453 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
22454 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
22455 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
22456 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
22457 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
22458 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
22459 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
22460 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
22461 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
22462 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
22463 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
22464 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
22465 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
22466 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
22467 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
22468 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
22469 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
22470 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
22471 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
22472 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
22474 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
22475 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
22476 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
22477 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
22478 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
22479 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
22480 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
22481 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
22482 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
22483 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
22484 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
22485 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
22486 default: llvm_unreachable("Unrecognized FMA variant.");
22489 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
22490 MachineInstrBuilder MIB =
22491 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
22492 .addOperand(MI->getOperand(0))
22493 .addOperand(MI->getOperand(3))
22494 .addOperand(MI->getOperand(2))
22495 .addOperand(MI->getOperand(1));
22496 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
22497 MI->eraseFromParent();
22504 MachineBasicBlock *
22505 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
22506 MachineBasicBlock *BB) const {
22507 switch (MI->getOpcode()) {
22508 default: llvm_unreachable("Unexpected instr type to insert");
22509 case X86::TAILJMPd64:
22510 case X86::TAILJMPr64:
22511 case X86::TAILJMPm64:
22512 case X86::TAILJMPd64_REX:
22513 case X86::TAILJMPr64_REX:
22514 case X86::TAILJMPm64_REX:
22515 llvm_unreachable("TAILJMP64 would not be touched here.");
22516 case X86::TCRETURNdi64:
22517 case X86::TCRETURNri64:
22518 case X86::TCRETURNmi64:
22520 case X86::WIN_ALLOCA:
22521 return EmitLoweredWinAlloca(MI, BB);
22522 case X86::CATCHRET:
22523 return EmitLoweredCatchRet(MI, BB);
22524 case X86::CATCHPAD:
22525 return EmitLoweredCatchPad(MI, BB);
22526 case X86::SEG_ALLOCA_32:
22527 case X86::SEG_ALLOCA_64:
22528 return EmitLoweredSegAlloca(MI, BB);
22529 case X86::TLSCall_32:
22530 case X86::TLSCall_64:
22531 return EmitLoweredTLSCall(MI, BB);
22532 case X86::CMOV_FR32:
22533 case X86::CMOV_FR64:
22534 case X86::CMOV_FR128:
22535 case X86::CMOV_GR8:
22536 case X86::CMOV_GR16:
22537 case X86::CMOV_GR32:
22538 case X86::CMOV_RFP32:
22539 case X86::CMOV_RFP64:
22540 case X86::CMOV_RFP80:
22541 case X86::CMOV_V2F64:
22542 case X86::CMOV_V2I64:
22543 case X86::CMOV_V4F32:
22544 case X86::CMOV_V4F64:
22545 case X86::CMOV_V4I64:
22546 case X86::CMOV_V16F32:
22547 case X86::CMOV_V8F32:
22548 case X86::CMOV_V8F64:
22549 case X86::CMOV_V8I64:
22550 case X86::CMOV_V8I1:
22551 case X86::CMOV_V16I1:
22552 case X86::CMOV_V32I1:
22553 case X86::CMOV_V64I1:
22554 return EmitLoweredSelect(MI, BB);
22556 case X86::RDFLAGS32:
22557 case X86::RDFLAGS64: {
22558 DebugLoc DL = MI->getDebugLoc();
22559 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22561 MI->getOpcode() == X86::RDFLAGS32 ? X86::PUSHF32 : X86::PUSHF64;
22563 MI->getOpcode() == X86::RDFLAGS32 ? X86::POP32r : X86::POP64r;
22564 BuildMI(*BB, MI, DL, TII->get(PushF));
22565 BuildMI(*BB, MI, DL, TII->get(Pop), MI->getOperand(0).getReg());
22567 MI->eraseFromParent(); // The pseudo is gone now.
22571 case X86::WRFLAGS32:
22572 case X86::WRFLAGS64: {
22573 DebugLoc DL = MI->getDebugLoc();
22574 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22576 MI->getOpcode() == X86::WRFLAGS32 ? X86::PUSH32r : X86::PUSH64r;
22578 MI->getOpcode() == X86::WRFLAGS32 ? X86::POPF32 : X86::POPF64;
22579 BuildMI(*BB, MI, DL, TII->get(Push)).addReg(MI->getOperand(0).getReg());
22580 BuildMI(*BB, MI, DL, TII->get(PopF));
22582 MI->eraseFromParent(); // The pseudo is gone now.
22586 case X86::RELEASE_FADD32mr:
22587 case X86::RELEASE_FADD64mr:
22588 return EmitLoweredAtomicFP(MI, BB);
22590 case X86::FP32_TO_INT16_IN_MEM:
22591 case X86::FP32_TO_INT32_IN_MEM:
22592 case X86::FP32_TO_INT64_IN_MEM:
22593 case X86::FP64_TO_INT16_IN_MEM:
22594 case X86::FP64_TO_INT32_IN_MEM:
22595 case X86::FP64_TO_INT64_IN_MEM:
22596 case X86::FP80_TO_INT16_IN_MEM:
22597 case X86::FP80_TO_INT32_IN_MEM:
22598 case X86::FP80_TO_INT64_IN_MEM: {
22599 MachineFunction *F = BB->getParent();
22600 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22601 DebugLoc DL = MI->getDebugLoc();
22603 // Change the floating point control register to use "round towards zero"
22604 // mode when truncating to an integer value.
22605 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
22606 addFrameReference(BuildMI(*BB, MI, DL,
22607 TII->get(X86::FNSTCW16m)), CWFrameIdx);
22609 // Load the old value of the high byte of the control word...
22611 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
22612 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
22615 // Set the high part to be round to zero...
22616 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
22619 // Reload the modified control word now...
22620 addFrameReference(BuildMI(*BB, MI, DL,
22621 TII->get(X86::FLDCW16m)), CWFrameIdx);
22623 // Restore the memory image of control word to original value
22624 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
22627 // Get the X86 opcode to use.
22629 switch (MI->getOpcode()) {
22630 default: llvm_unreachable("illegal opcode!");
22631 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
22632 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
22633 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
22634 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
22635 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
22636 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
22637 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
22638 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
22639 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
22643 MachineOperand &Op = MI->getOperand(0);
22645 AM.BaseType = X86AddressMode::RegBase;
22646 AM.Base.Reg = Op.getReg();
22648 AM.BaseType = X86AddressMode::FrameIndexBase;
22649 AM.Base.FrameIndex = Op.getIndex();
22651 Op = MI->getOperand(1);
22653 AM.Scale = Op.getImm();
22654 Op = MI->getOperand(2);
22656 AM.IndexReg = Op.getImm();
22657 Op = MI->getOperand(3);
22658 if (Op.isGlobal()) {
22659 AM.GV = Op.getGlobal();
22661 AM.Disp = Op.getImm();
22663 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
22664 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
22666 // Reload the original control word now.
22667 addFrameReference(BuildMI(*BB, MI, DL,
22668 TII->get(X86::FLDCW16m)), CWFrameIdx);
22670 MI->eraseFromParent(); // The pseudo instruction is gone now.
22673 // String/text processing lowering.
22674 case X86::PCMPISTRM128REG:
22675 case X86::VPCMPISTRM128REG:
22676 case X86::PCMPISTRM128MEM:
22677 case X86::VPCMPISTRM128MEM:
22678 case X86::PCMPESTRM128REG:
22679 case X86::VPCMPESTRM128REG:
22680 case X86::PCMPESTRM128MEM:
22681 case X86::VPCMPESTRM128MEM:
22682 assert(Subtarget->hasSSE42() &&
22683 "Target must have SSE4.2 or AVX features enabled");
22684 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
22686 // String/text processing lowering.
22687 case X86::PCMPISTRIREG:
22688 case X86::VPCMPISTRIREG:
22689 case X86::PCMPISTRIMEM:
22690 case X86::VPCMPISTRIMEM:
22691 case X86::PCMPESTRIREG:
22692 case X86::VPCMPESTRIREG:
22693 case X86::PCMPESTRIMEM:
22694 case X86::VPCMPESTRIMEM:
22695 assert(Subtarget->hasSSE42() &&
22696 "Target must have SSE4.2 or AVX features enabled");
22697 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
22699 // Thread synchronization.
22701 return EmitMonitor(MI, BB, Subtarget);
22704 return EmitWRPKRU(MI, BB, Subtarget);
22706 return EmitRDPKRU(MI, BB, Subtarget);
22709 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
22711 case X86::VASTART_SAVE_XMM_REGS:
22712 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
22714 case X86::VAARG_64:
22715 return EmitVAARG64WithCustomInserter(MI, BB);
22717 case X86::EH_SjLj_SetJmp32:
22718 case X86::EH_SjLj_SetJmp64:
22719 return emitEHSjLjSetJmp(MI, BB);
22721 case X86::EH_SjLj_LongJmp32:
22722 case X86::EH_SjLj_LongJmp64:
22723 return emitEHSjLjLongJmp(MI, BB);
22725 case TargetOpcode::STATEPOINT:
22726 // As an implementation detail, STATEPOINT shares the STACKMAP format at
22727 // this point in the process. We diverge later.
22728 return emitPatchPoint(MI, BB);
22730 case TargetOpcode::STACKMAP:
22731 case TargetOpcode::PATCHPOINT:
22732 return emitPatchPoint(MI, BB);
22734 case X86::VFMADDPDr213r:
22735 case X86::VFMADDPSr213r:
22736 case X86::VFMADDSDr213r:
22737 case X86::VFMADDSSr213r:
22738 case X86::VFMSUBPDr213r:
22739 case X86::VFMSUBPSr213r:
22740 case X86::VFMSUBSDr213r:
22741 case X86::VFMSUBSSr213r:
22742 case X86::VFNMADDPDr213r:
22743 case X86::VFNMADDPSr213r:
22744 case X86::VFNMADDSDr213r:
22745 case X86::VFNMADDSSr213r:
22746 case X86::VFNMSUBPDr213r:
22747 case X86::VFNMSUBPSr213r:
22748 case X86::VFNMSUBSDr213r:
22749 case X86::VFNMSUBSSr213r:
22750 case X86::VFMADDSUBPDr213r:
22751 case X86::VFMADDSUBPSr213r:
22752 case X86::VFMSUBADDPDr213r:
22753 case X86::VFMSUBADDPSr213r:
22754 case X86::VFMADDPDr213rY:
22755 case X86::VFMADDPSr213rY:
22756 case X86::VFMSUBPDr213rY:
22757 case X86::VFMSUBPSr213rY:
22758 case X86::VFNMADDPDr213rY:
22759 case X86::VFNMADDPSr213rY:
22760 case X86::VFNMSUBPDr213rY:
22761 case X86::VFNMSUBPSr213rY:
22762 case X86::VFMADDSUBPDr213rY:
22763 case X86::VFMADDSUBPSr213rY:
22764 case X86::VFMSUBADDPDr213rY:
22765 case X86::VFMSUBADDPSr213rY:
22766 return emitFMA3Instr(MI, BB);
22770 //===----------------------------------------------------------------------===//
22771 // X86 Optimization Hooks
22772 //===----------------------------------------------------------------------===//
22774 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22777 const SelectionDAG &DAG,
22778 unsigned Depth) const {
22779 unsigned BitWidth = KnownZero.getBitWidth();
22780 unsigned Opc = Op.getOpcode();
22781 assert((Opc >= ISD::BUILTIN_OP_END ||
22782 Opc == ISD::INTRINSIC_WO_CHAIN ||
22783 Opc == ISD::INTRINSIC_W_CHAIN ||
22784 Opc == ISD::INTRINSIC_VOID) &&
22785 "Should use MaskedValueIsZero if you don't know whether Op"
22786 " is a target node!");
22788 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22802 // These nodes' second result is a boolean.
22803 if (Op.getResNo() == 0)
22806 case X86ISD::SETCC:
22807 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22809 case ISD::INTRINSIC_WO_CHAIN: {
22810 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22811 unsigned NumLoBits = 0;
22814 case Intrinsic::x86_sse_movmsk_ps:
22815 case Intrinsic::x86_avx_movmsk_ps_256:
22816 case Intrinsic::x86_sse2_movmsk_pd:
22817 case Intrinsic::x86_avx_movmsk_pd_256:
22818 case Intrinsic::x86_mmx_pmovmskb:
22819 case Intrinsic::x86_sse2_pmovmskb_128:
22820 case Intrinsic::x86_avx2_pmovmskb: {
22821 // High bits of movmskp{s|d}, pmovmskb are known zero.
22823 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22824 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22825 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22826 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22827 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22828 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22829 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22830 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22832 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22841 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22843 const SelectionDAG &,
22844 unsigned Depth) const {
22845 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22846 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22847 return Op.getValueType().getScalarSizeInBits();
22853 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22854 /// node is a GlobalAddress + offset.
22855 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22856 const GlobalValue* &GA,
22857 int64_t &Offset) const {
22858 if (N->getOpcode() == X86ISD::Wrapper) {
22859 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22860 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22861 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22865 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22868 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22869 /// FIXME: This could be expanded to support 512 bit vectors as well.
22870 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22871 TargetLowering::DAGCombinerInfo &DCI,
22872 const X86Subtarget* Subtarget) {
22874 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22875 SDValue V1 = SVOp->getOperand(0);
22876 SDValue V2 = SVOp->getOperand(1);
22877 MVT VT = SVOp->getSimpleValueType(0);
22878 unsigned NumElems = VT.getVectorNumElements();
22880 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22881 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22885 // V UNDEF BUILD_VECTOR UNDEF
22887 // CONCAT_VECTOR CONCAT_VECTOR
22890 // RESULT: V + zero extended
22892 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22893 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22894 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22897 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22900 // To match the shuffle mask, the first half of the mask should
22901 // be exactly the first vector, and all the rest a splat with the
22902 // first element of the second one.
22903 for (unsigned i = 0; i != NumElems/2; ++i)
22904 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22905 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22908 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22909 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22910 if (Ld->hasNUsesOfValue(1, 0)) {
22911 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22912 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22914 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22916 Ld->getPointerInfo(),
22917 Ld->getAlignment(),
22918 false/*isVolatile*/, true/*ReadMem*/,
22919 false/*WriteMem*/);
22921 // Make sure the newly-created LOAD is in the same position as Ld in
22922 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22923 // and update uses of Ld's output chain to use the TokenFactor.
22924 if (Ld->hasAnyUseOfValue(1)) {
22925 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22926 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22927 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22928 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22929 SDValue(ResNode.getNode(), 1));
22932 return DAG.getBitcast(VT, ResNode);
22936 // Emit a zeroed vector and insert the desired subvector on its
22938 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22939 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22940 return DCI.CombineTo(N, InsV);
22946 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22949 /// This is the leaf of the recursive combinine below. When we have found some
22950 /// chain of single-use x86 shuffle instructions and accumulated the combined
22951 /// shuffle mask represented by them, this will try to pattern match that mask
22952 /// into either a single instruction if there is a special purpose instruction
22953 /// for this operation, or into a PSHUFB instruction which is a fully general
22954 /// instruction but should only be used to replace chains over a certain depth.
22955 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22956 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22957 TargetLowering::DAGCombinerInfo &DCI,
22958 const X86Subtarget *Subtarget) {
22959 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22961 // Find the operand that enters the chain. Note that multiple uses are OK
22962 // here, we're not going to remove the operand we find.
22963 SDValue Input = Op.getOperand(0);
22964 while (Input.getOpcode() == ISD::BITCAST)
22965 Input = Input.getOperand(0);
22967 MVT VT = Input.getSimpleValueType();
22968 MVT RootVT = Root.getSimpleValueType();
22971 if (Mask.size() == 1) {
22972 int Index = Mask[0];
22973 assert((Index >= 0 || Index == SM_SentinelUndef ||
22974 Index == SM_SentinelZero) &&
22975 "Invalid shuffle index found!");
22977 // We may end up with an accumulated mask of size 1 as a result of
22978 // widening of shuffle operands (see function canWidenShuffleElements).
22979 // If the only shuffle index is equal to SM_SentinelZero then propagate
22980 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22981 // mask, and therefore the entire chain of shuffles can be folded away.
22982 if (Index == SM_SentinelZero)
22983 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22985 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22990 // Use the float domain if the operand type is a floating point type.
22991 bool FloatDomain = VT.isFloatingPoint();
22993 // For floating point shuffles, we don't have free copies in the shuffle
22994 // instructions or the ability to load as part of the instruction, so
22995 // canonicalize their shuffles to UNPCK or MOV variants.
22997 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22998 // vectors because it can have a load folded into it that UNPCK cannot. This
22999 // doesn't preclude something switching to the shorter encoding post-RA.
23001 // FIXME: Should teach these routines about AVX vector widths.
23002 if (FloatDomain && VT.is128BitVector()) {
23003 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
23004 bool Lo = Mask.equals({0, 0});
23007 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
23008 // is no slower than UNPCKLPD but has the option to fold the input operand
23009 // into even an unaligned memory load.
23010 if (Lo && Subtarget->hasSSE3()) {
23011 Shuffle = X86ISD::MOVDDUP;
23012 ShuffleVT = MVT::v2f64;
23014 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
23015 // than the UNPCK variants.
23016 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
23017 ShuffleVT = MVT::v4f32;
23019 if (Depth == 1 && Root->getOpcode() == Shuffle)
23020 return false; // Nothing to do!
23021 Op = DAG.getBitcast(ShuffleVT, Input);
23022 DCI.AddToWorklist(Op.getNode());
23023 if (Shuffle == X86ISD::MOVDDUP)
23024 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
23026 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
23027 DCI.AddToWorklist(Op.getNode());
23028 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
23032 if (Subtarget->hasSSE3() &&
23033 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
23034 bool Lo = Mask.equals({0, 0, 2, 2});
23035 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
23036 MVT ShuffleVT = MVT::v4f32;
23037 if (Depth == 1 && Root->getOpcode() == Shuffle)
23038 return false; // Nothing to do!
23039 Op = DAG.getBitcast(ShuffleVT, Input);
23040 DCI.AddToWorklist(Op.getNode());
23041 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
23042 DCI.AddToWorklist(Op.getNode());
23043 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
23047 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
23048 bool Lo = Mask.equals({0, 0, 1, 1});
23049 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
23050 MVT ShuffleVT = MVT::v4f32;
23051 if (Depth == 1 && Root->getOpcode() == Shuffle)
23052 return false; // Nothing to do!
23053 Op = DAG.getBitcast(ShuffleVT, Input);
23054 DCI.AddToWorklist(Op.getNode());
23055 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
23056 DCI.AddToWorklist(Op.getNode());
23057 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
23063 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
23064 // variants as none of these have single-instruction variants that are
23065 // superior to the UNPCK formulation.
23066 if (!FloatDomain && VT.is128BitVector() &&
23067 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23068 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
23069 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
23071 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
23072 bool Lo = Mask[0] == 0;
23073 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
23074 if (Depth == 1 && Root->getOpcode() == Shuffle)
23075 return false; // Nothing to do!
23077 switch (Mask.size()) {
23079 ShuffleVT = MVT::v8i16;
23082 ShuffleVT = MVT::v16i8;
23085 llvm_unreachable("Impossible mask size!");
23087 Op = DAG.getBitcast(ShuffleVT, Input);
23088 DCI.AddToWorklist(Op.getNode());
23089 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
23090 DCI.AddToWorklist(Op.getNode());
23091 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
23096 // Don't try to re-form single instruction chains under any circumstances now
23097 // that we've done encoding canonicalization for them.
23101 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
23102 // can replace them with a single PSHUFB instruction profitably. Intel's
23103 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
23104 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
23105 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
23106 SmallVector<SDValue, 16> PSHUFBMask;
23107 int NumBytes = VT.getSizeInBits() / 8;
23108 int Ratio = NumBytes / Mask.size();
23109 for (int i = 0; i < NumBytes; ++i) {
23110 if (Mask[i / Ratio] == SM_SentinelUndef) {
23111 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
23114 int M = Mask[i / Ratio] != SM_SentinelZero
23115 ? Ratio * Mask[i / Ratio] + i % Ratio
23117 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
23119 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
23120 Op = DAG.getBitcast(ByteVT, Input);
23121 DCI.AddToWorklist(Op.getNode());
23122 SDValue PSHUFBMaskOp =
23123 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
23124 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
23125 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
23126 DCI.AddToWorklist(Op.getNode());
23127 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
23132 // Failed to find any combines.
23136 /// \brief Fully generic combining of x86 shuffle instructions.
23138 /// This should be the last combine run over the x86 shuffle instructions. Once
23139 /// they have been fully optimized, this will recursively consider all chains
23140 /// of single-use shuffle instructions, build a generic model of the cumulative
23141 /// shuffle operation, and check for simpler instructions which implement this
23142 /// operation. We use this primarily for two purposes:
23144 /// 1) Collapse generic shuffles to specialized single instructions when
23145 /// equivalent. In most cases, this is just an encoding size win, but
23146 /// sometimes we will collapse multiple generic shuffles into a single
23147 /// special-purpose shuffle.
23148 /// 2) Look for sequences of shuffle instructions with 3 or more total
23149 /// instructions, and replace them with the slightly more expensive SSSE3
23150 /// PSHUFB instruction if available. We do this as the last combining step
23151 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
23152 /// a suitable short sequence of other instructions. The PHUFB will either
23153 /// use a register or have to read from memory and so is slightly (but only
23154 /// slightly) more expensive than the other shuffle instructions.
23156 /// Because this is inherently a quadratic operation (for each shuffle in
23157 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
23158 /// This should never be an issue in practice as the shuffle lowering doesn't
23159 /// produce sequences of more than 8 instructions.
23161 /// FIXME: We will currently miss some cases where the redundant shuffling
23162 /// would simplify under the threshold for PSHUFB formation because of
23163 /// combine-ordering. To fix this, we should do the redundant instruction
23164 /// combining in this recursive walk.
23165 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
23166 ArrayRef<int> RootMask,
23167 int Depth, bool HasPSHUFB,
23169 TargetLowering::DAGCombinerInfo &DCI,
23170 const X86Subtarget *Subtarget) {
23171 // Bound the depth of our recursive combine because this is ultimately
23172 // quadratic in nature.
23176 // Directly rip through bitcasts to find the underlying operand.
23177 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
23178 Op = Op.getOperand(0);
23180 MVT VT = Op.getSimpleValueType();
23181 if (!VT.isVector())
23182 return false; // Bail if we hit a non-vector.
23184 assert(Root.getSimpleValueType().isVector() &&
23185 "Shuffles operate on vector types!");
23186 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
23187 "Can only combine shuffles of the same vector register size.");
23189 if (!isTargetShuffle(Op.getOpcode()))
23191 SmallVector<int, 16> OpMask;
23193 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, true, OpMask, IsUnary);
23194 // We only can combine unary shuffles which we can decode the mask for.
23195 if (!HaveMask || !IsUnary)
23198 assert(VT.getVectorNumElements() == OpMask.size() &&
23199 "Different mask size from vector size!");
23200 assert(((RootMask.size() > OpMask.size() &&
23201 RootMask.size() % OpMask.size() == 0) ||
23202 (OpMask.size() > RootMask.size() &&
23203 OpMask.size() % RootMask.size() == 0) ||
23204 OpMask.size() == RootMask.size()) &&
23205 "The smaller number of elements must divide the larger.");
23206 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
23207 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
23208 assert(((RootRatio == 1 && OpRatio == 1) ||
23209 (RootRatio == 1) != (OpRatio == 1)) &&
23210 "Must not have a ratio for both incoming and op masks!");
23212 SmallVector<int, 16> Mask;
23213 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
23215 // Merge this shuffle operation's mask into our accumulated mask. Note that
23216 // this shuffle's mask will be the first applied to the input, followed by the
23217 // root mask to get us all the way to the root value arrangement. The reason
23218 // for this order is that we are recursing up the operation chain.
23219 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
23220 int RootIdx = i / RootRatio;
23221 if (RootMask[RootIdx] < 0) {
23222 // This is a zero or undef lane, we're done.
23223 Mask.push_back(RootMask[RootIdx]);
23227 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
23228 int OpIdx = RootMaskedIdx / OpRatio;
23229 if (OpMask[OpIdx] < 0) {
23230 // The incoming lanes are zero or undef, it doesn't matter which ones we
23232 Mask.push_back(OpMask[OpIdx]);
23236 // Ok, we have non-zero lanes, map them through.
23237 Mask.push_back(OpMask[OpIdx] * OpRatio +
23238 RootMaskedIdx % OpRatio);
23241 // See if we can recurse into the operand to combine more things.
23242 switch (Op.getOpcode()) {
23243 case X86ISD::PSHUFB:
23245 case X86ISD::PSHUFD:
23246 case X86ISD::PSHUFHW:
23247 case X86ISD::PSHUFLW:
23248 if (Op.getOperand(0).hasOneUse() &&
23249 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
23250 HasPSHUFB, DAG, DCI, Subtarget))
23254 case X86ISD::UNPCKL:
23255 case X86ISD::UNPCKH:
23256 assert(Op.getOperand(0) == Op.getOperand(1) &&
23257 "We only combine unary shuffles!");
23258 // We can't check for single use, we have to check that this shuffle is the
23260 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
23261 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
23262 HasPSHUFB, DAG, DCI, Subtarget))
23267 // Minor canonicalization of the accumulated shuffle mask to make it easier
23268 // to match below. All this does is detect masks with squential pairs of
23269 // elements, and shrink them to the half-width mask. It does this in a loop
23270 // so it will reduce the size of the mask to the minimal width mask which
23271 // performs an equivalent shuffle.
23272 SmallVector<int, 16> WidenedMask;
23273 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
23274 Mask = std::move(WidenedMask);
23275 WidenedMask.clear();
23278 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
23282 /// \brief Get the PSHUF-style mask from PSHUF node.
23284 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
23285 /// PSHUF-style masks that can be reused with such instructions.
23286 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
23287 MVT VT = N.getSimpleValueType();
23288 SmallVector<int, 4> Mask;
23290 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, false, Mask, IsUnary);
23294 // If we have more than 128-bits, only the low 128-bits of shuffle mask
23295 // matter. Check that the upper masks are repeats and remove them.
23296 if (VT.getSizeInBits() > 128) {
23297 int LaneElts = 128 / VT.getScalarSizeInBits();
23299 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
23300 for (int j = 0; j < LaneElts; ++j)
23301 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
23302 "Mask doesn't repeat in high 128-bit lanes!");
23304 Mask.resize(LaneElts);
23307 switch (N.getOpcode()) {
23308 case X86ISD::PSHUFD:
23310 case X86ISD::PSHUFLW:
23313 case X86ISD::PSHUFHW:
23314 Mask.erase(Mask.begin(), Mask.begin() + 4);
23315 for (int &M : Mask)
23319 llvm_unreachable("No valid shuffle instruction found!");
23323 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
23325 /// We walk up the chain and look for a combinable shuffle, skipping over
23326 /// shuffles that we could hoist this shuffle's transformation past without
23327 /// altering anything.
23329 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
23331 TargetLowering::DAGCombinerInfo &DCI) {
23332 assert(N.getOpcode() == X86ISD::PSHUFD &&
23333 "Called with something other than an x86 128-bit half shuffle!");
23336 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
23337 // of the shuffles in the chain so that we can form a fresh chain to replace
23339 SmallVector<SDValue, 8> Chain;
23340 SDValue V = N.getOperand(0);
23341 for (; V.hasOneUse(); V = V.getOperand(0)) {
23342 switch (V.getOpcode()) {
23344 return SDValue(); // Nothing combined!
23347 // Skip bitcasts as we always know the type for the target specific
23351 case X86ISD::PSHUFD:
23352 // Found another dword shuffle.
23355 case X86ISD::PSHUFLW:
23356 // Check that the low words (being shuffled) are the identity in the
23357 // dword shuffle, and the high words are self-contained.
23358 if (Mask[0] != 0 || Mask[1] != 1 ||
23359 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
23362 Chain.push_back(V);
23365 case X86ISD::PSHUFHW:
23366 // Check that the high words (being shuffled) are the identity in the
23367 // dword shuffle, and the low words are self-contained.
23368 if (Mask[2] != 2 || Mask[3] != 3 ||
23369 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
23372 Chain.push_back(V);
23375 case X86ISD::UNPCKL:
23376 case X86ISD::UNPCKH:
23377 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
23378 // shuffle into a preceding word shuffle.
23379 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
23380 V.getSimpleValueType().getVectorElementType() != MVT::i16)
23383 // Search for a half-shuffle which we can combine with.
23384 unsigned CombineOp =
23385 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
23386 if (V.getOperand(0) != V.getOperand(1) ||
23387 !V->isOnlyUserOf(V.getOperand(0).getNode()))
23389 Chain.push_back(V);
23390 V = V.getOperand(0);
23392 switch (V.getOpcode()) {
23394 return SDValue(); // Nothing to combine.
23396 case X86ISD::PSHUFLW:
23397 case X86ISD::PSHUFHW:
23398 if (V.getOpcode() == CombineOp)
23401 Chain.push_back(V);
23405 V = V.getOperand(0);
23409 } while (V.hasOneUse());
23412 // Break out of the loop if we break out of the switch.
23416 if (!V.hasOneUse())
23417 // We fell out of the loop without finding a viable combining instruction.
23420 // Merge this node's mask and our incoming mask.
23421 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23422 for (int &M : Mask)
23424 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
23425 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23427 // Rebuild the chain around this new shuffle.
23428 while (!Chain.empty()) {
23429 SDValue W = Chain.pop_back_val();
23431 if (V.getValueType() != W.getOperand(0).getValueType())
23432 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
23434 switch (W.getOpcode()) {
23436 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
23438 case X86ISD::UNPCKL:
23439 case X86ISD::UNPCKH:
23440 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
23443 case X86ISD::PSHUFD:
23444 case X86ISD::PSHUFLW:
23445 case X86ISD::PSHUFHW:
23446 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
23450 if (V.getValueType() != N.getValueType())
23451 V = DAG.getBitcast(N.getValueType(), V);
23453 // Return the new chain to replace N.
23457 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
23460 /// We walk up the chain, skipping shuffles of the other half and looking
23461 /// through shuffles which switch halves trying to find a shuffle of the same
23462 /// pair of dwords.
23463 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
23465 TargetLowering::DAGCombinerInfo &DCI) {
23467 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
23468 "Called with something other than an x86 128-bit half shuffle!");
23470 unsigned CombineOpcode = N.getOpcode();
23472 // Walk up a single-use chain looking for a combinable shuffle.
23473 SDValue V = N.getOperand(0);
23474 for (; V.hasOneUse(); V = V.getOperand(0)) {
23475 switch (V.getOpcode()) {
23477 return false; // Nothing combined!
23480 // Skip bitcasts as we always know the type for the target specific
23484 case X86ISD::PSHUFLW:
23485 case X86ISD::PSHUFHW:
23486 if (V.getOpcode() == CombineOpcode)
23489 // Other-half shuffles are no-ops.
23492 // Break out of the loop if we break out of the switch.
23496 if (!V.hasOneUse())
23497 // We fell out of the loop without finding a viable combining instruction.
23500 // Combine away the bottom node as its shuffle will be accumulated into
23501 // a preceding shuffle.
23502 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23504 // Record the old value.
23507 // Merge this node's mask and our incoming mask (adjusted to account for all
23508 // the pshufd instructions encountered).
23509 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23510 for (int &M : Mask)
23512 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
23513 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23515 // Check that the shuffles didn't cancel each other out. If not, we need to
23516 // combine to the new one.
23518 // Replace the combinable shuffle with the combined one, updating all users
23519 // so that we re-evaluate the chain here.
23520 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
23525 /// \brief Try to combine x86 target specific shuffles.
23526 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
23527 TargetLowering::DAGCombinerInfo &DCI,
23528 const X86Subtarget *Subtarget) {
23530 MVT VT = N.getSimpleValueType();
23531 SmallVector<int, 4> Mask;
23533 switch (N.getOpcode()) {
23534 case X86ISD::PSHUFD:
23535 case X86ISD::PSHUFLW:
23536 case X86ISD::PSHUFHW:
23537 Mask = getPSHUFShuffleMask(N);
23538 assert(Mask.size() == 4);
23540 case X86ISD::UNPCKL: {
23541 // Combine X86ISD::UNPCKL and ISD::VECTOR_SHUFFLE into X86ISD::UNPCKH, in
23542 // which X86ISD::UNPCKL has a ISD::UNDEF operand, and ISD::VECTOR_SHUFFLE
23543 // moves upper half elements into the lower half part. For example:
23545 // t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1,
23547 // t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2
23549 // will be combined to:
23551 // t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1
23553 // This is only for 128-bit vectors. From SSE4.1 onward this combine may not
23554 // happen due to advanced instructions.
23555 if (!VT.is128BitVector())
23558 auto Op0 = N.getOperand(0);
23559 auto Op1 = N.getOperand(1);
23560 if (Op0.getOpcode() == ISD::UNDEF &&
23561 Op1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE) {
23562 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op1.getNode())->getMask();
23564 unsigned NumElts = VT.getVectorNumElements();
23565 SmallVector<int, 8> ExpectedMask(NumElts, -1);
23566 std::iota(ExpectedMask.begin(), ExpectedMask.begin() + NumElts / 2,
23569 auto ShufOp = Op1.getOperand(0);
23570 if (isShuffleEquivalent(Op1, ShufOp, Mask, ExpectedMask))
23571 return DAG.getNode(X86ISD::UNPCKH, DL, VT, N.getOperand(0), ShufOp);
23575 case X86ISD::BLENDI: {
23576 SDValue V0 = N->getOperand(0);
23577 SDValue V1 = N->getOperand(1);
23578 assert(VT == V0.getSimpleValueType() && VT == V1.getSimpleValueType() &&
23579 "Unexpected input vector types");
23581 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
23582 // operands and changing the mask to 1. This saves us a bunch of
23583 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
23584 // x86InstrInfo knows how to commute this back after instruction selection
23585 // if it would help register allocation.
23587 // TODO: If optimizing for size or a processor that doesn't suffer from
23588 // partial register update stalls, this should be transformed into a MOVSD
23589 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
23591 if (VT == MVT::v2f64)
23592 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
23593 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
23594 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
23595 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
23604 // Nuke no-op shuffles that show up after combining.
23605 if (isNoopShuffleMask(Mask))
23606 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23608 // Look for simplifications involving one or two shuffle instructions.
23609 SDValue V = N.getOperand(0);
23610 switch (N.getOpcode()) {
23613 case X86ISD::PSHUFLW:
23614 case X86ISD::PSHUFHW:
23615 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
23617 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
23618 return SDValue(); // We combined away this shuffle, so we're done.
23620 // See if this reduces to a PSHUFD which is no more expensive and can
23621 // combine with more operations. Note that it has to at least flip the
23622 // dwords as otherwise it would have been removed as a no-op.
23623 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
23624 int DMask[] = {0, 1, 2, 3};
23625 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
23626 DMask[DOffset + 0] = DOffset + 1;
23627 DMask[DOffset + 1] = DOffset + 0;
23628 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
23629 V = DAG.getBitcast(DVT, V);
23630 DCI.AddToWorklist(V.getNode());
23631 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
23632 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
23633 DCI.AddToWorklist(V.getNode());
23634 return DAG.getBitcast(VT, V);
23637 // Look for shuffle patterns which can be implemented as a single unpack.
23638 // FIXME: This doesn't handle the location of the PSHUFD generically, and
23639 // only works when we have a PSHUFD followed by two half-shuffles.
23640 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
23641 (V.getOpcode() == X86ISD::PSHUFLW ||
23642 V.getOpcode() == X86ISD::PSHUFHW) &&
23643 V.getOpcode() != N.getOpcode() &&
23645 SDValue D = V.getOperand(0);
23646 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
23647 D = D.getOperand(0);
23648 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
23649 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23650 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
23651 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23652 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23654 for (int i = 0; i < 4; ++i) {
23655 WordMask[i + NOffset] = Mask[i] + NOffset;
23656 WordMask[i + VOffset] = VMask[i] + VOffset;
23658 // Map the word mask through the DWord mask.
23660 for (int i = 0; i < 8; ++i)
23661 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
23662 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23663 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
23664 // We can replace all three shuffles with an unpack.
23665 V = DAG.getBitcast(VT, D.getOperand(0));
23666 DCI.AddToWorklist(V.getNode());
23667 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
23676 case X86ISD::PSHUFD:
23677 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
23686 /// \brief Try to combine a shuffle into a target-specific add-sub node.
23688 /// We combine this directly on the abstract vector shuffle nodes so it is
23689 /// easier to generically match. We also insert dummy vector shuffle nodes for
23690 /// the operands which explicitly discard the lanes which are unused by this
23691 /// operation to try to flow through the rest of the combiner the fact that
23692 /// they're unused.
23693 static SDValue combineShuffleToAddSub(SDNode *N, const X86Subtarget *Subtarget,
23694 SelectionDAG &DAG) {
23696 EVT VT = N->getValueType(0);
23697 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
23698 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
23701 // We only handle target-independent shuffles.
23702 // FIXME: It would be easy and harmless to use the target shuffle mask
23703 // extraction tool to support more.
23704 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
23707 auto *SVN = cast<ShuffleVectorSDNode>(N);
23708 SmallVector<int, 8> Mask;
23709 for (int M : SVN->getMask())
23712 SDValue V1 = N->getOperand(0);
23713 SDValue V2 = N->getOperand(1);
23715 // We require the first shuffle operand to be the FSUB node, and the second to
23716 // be the FADD node.
23717 if (V1.getOpcode() == ISD::FADD && V2.getOpcode() == ISD::FSUB) {
23718 ShuffleVectorSDNode::commuteMask(Mask);
23720 } else if (V1.getOpcode() != ISD::FSUB || V2.getOpcode() != ISD::FADD)
23723 // If there are other uses of these operations we can't fold them.
23724 if (!V1->hasOneUse() || !V2->hasOneUse())
23727 // Ensure that both operations have the same operands. Note that we can
23728 // commute the FADD operands.
23729 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
23730 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
23731 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
23734 // We're looking for blends between FADD and FSUB nodes. We insist on these
23735 // nodes being lined up in a specific expected pattern.
23736 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
23737 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
23738 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
23741 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
23744 /// PerformShuffleCombine - Performs several different shuffle combines.
23745 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23746 TargetLowering::DAGCombinerInfo &DCI,
23747 const X86Subtarget *Subtarget) {
23749 SDValue N0 = N->getOperand(0);
23750 SDValue N1 = N->getOperand(1);
23751 EVT VT = N->getValueType(0);
23753 // Don't create instructions with illegal types after legalize types has run.
23754 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23755 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23758 // If we have legalized the vector types, look for blends of FADD and FSUB
23759 // nodes that we can fuse into an ADDSUB node.
23760 if (TLI.isTypeLegal(VT))
23761 if (SDValue AddSub = combineShuffleToAddSub(N, Subtarget, DAG))
23764 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23765 if (TLI.isTypeLegal(VT) && Subtarget->hasFp256() && VT.is256BitVector() &&
23766 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23767 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23769 // During Type Legalization, when promoting illegal vector types,
23770 // the backend might introduce new shuffle dag nodes and bitcasts.
23772 // This code performs the following transformation:
23773 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23774 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23776 // We do this only if both the bitcast and the BINOP dag nodes have
23777 // one use. Also, perform this transformation only if the new binary
23778 // operation is legal. This is to avoid introducing dag nodes that
23779 // potentially need to be further expanded (or custom lowered) into a
23780 // less optimal sequence of dag nodes.
23781 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23782 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23783 N0.getOpcode() == ISD::BITCAST) {
23784 SDValue BC0 = N0.getOperand(0);
23785 EVT SVT = BC0.getValueType();
23786 unsigned Opcode = BC0.getOpcode();
23787 unsigned NumElts = VT.getVectorNumElements();
23789 if (BC0.hasOneUse() && SVT.isVector() &&
23790 SVT.getVectorNumElements() * 2 == NumElts &&
23791 TLI.isOperationLegal(Opcode, VT)) {
23792 bool CanFold = false;
23804 unsigned SVTNumElts = SVT.getVectorNumElements();
23805 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23806 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23807 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23808 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23809 CanFold = SVOp->getMaskElt(i) < 0;
23812 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23813 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23814 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23815 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23820 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23821 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23822 // consecutive, non-overlapping, and in the right order.
23823 SmallVector<SDValue, 16> Elts;
23824 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23825 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23827 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23830 if (isTargetShuffle(N->getOpcode())) {
23832 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23833 if (Shuffle.getNode())
23836 // Try recursively combining arbitrary sequences of x86 shuffle
23837 // instructions into higher-order shuffles. We do this after combining
23838 // specific PSHUF instruction sequences into their minimal form so that we
23839 // can evaluate how many specialized shuffle instructions are involved in
23840 // a particular chain.
23841 SmallVector<int, 1> NonceMask; // Just a placeholder.
23842 NonceMask.push_back(0);
23843 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23844 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23846 return SDValue(); // This routine will use CombineTo to replace N.
23852 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23853 /// specific shuffle of a load can be folded into a single element load.
23854 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23855 /// shuffles have been custom lowered so we need to handle those here.
23856 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23857 TargetLowering::DAGCombinerInfo &DCI) {
23858 if (DCI.isBeforeLegalizeOps())
23861 SDValue InVec = N->getOperand(0);
23862 SDValue EltNo = N->getOperand(1);
23864 if (!isa<ConstantSDNode>(EltNo))
23867 EVT OriginalVT = InVec.getValueType();
23869 if (InVec.getOpcode() == ISD::BITCAST) {
23870 // Don't duplicate a load with other uses.
23871 if (!InVec.hasOneUse())
23873 EVT BCVT = InVec.getOperand(0).getValueType();
23874 if (!BCVT.isVector() ||
23875 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23877 InVec = InVec.getOperand(0);
23880 EVT CurrentVT = InVec.getValueType();
23882 if (!isTargetShuffle(InVec.getOpcode()))
23885 // Don't duplicate a load with other uses.
23886 if (!InVec.hasOneUse())
23889 SmallVector<int, 16> ShuffleMask;
23891 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23892 false, ShuffleMask, UnaryShuffle))
23895 // Select the input vector, guarding against out of range extract vector.
23896 unsigned NumElems = CurrentVT.getVectorNumElements();
23897 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23898 int Idx = (Elt > (int)NumElems) ? SM_SentinelUndef : ShuffleMask[Elt];
23899 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23900 : InVec.getOperand(1);
23902 // If inputs to shuffle are the same for both ops, then allow 2 uses
23903 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23904 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23906 if (LdNode.getOpcode() == ISD::BITCAST) {
23907 // Don't duplicate a load with other uses.
23908 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23911 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23912 LdNode = LdNode.getOperand(0);
23915 if (!ISD::isNormalLoad(LdNode.getNode()))
23918 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23920 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23923 EVT EltVT = N->getValueType(0);
23924 // If there's a bitcast before the shuffle, check if the load type and
23925 // alignment is valid.
23926 unsigned Align = LN0->getAlignment();
23927 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23928 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23929 EltVT.getTypeForEVT(*DAG.getContext()));
23931 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23934 // All checks match so transform back to vector_shuffle so that DAG combiner
23935 // can finish the job
23938 // Create shuffle node taking into account the case that its a unary shuffle
23939 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23940 : InVec.getOperand(1);
23941 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23942 InVec.getOperand(0), Shuffle,
23944 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23945 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23949 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23950 const X86Subtarget *Subtarget) {
23951 SDValue N0 = N->getOperand(0);
23952 EVT VT = N->getValueType(0);
23954 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23955 // special and don't usually play with other vector types, it's better to
23956 // handle them early to be sure we emit efficient code by avoiding
23957 // store-load conversions.
23958 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23959 N0.getValueType() == MVT::v2i32 &&
23960 isNullConstant(N0.getOperand(1))) {
23961 SDValue N00 = N0->getOperand(0);
23962 if (N00.getValueType() == MVT::i32)
23963 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23966 // Convert a bitcasted integer logic operation that has one bitcasted
23967 // floating-point operand and one constant operand into a floating-point
23968 // logic operation. This may create a load of the constant, but that is
23969 // cheaper than materializing the constant in an integer register and
23970 // transferring it to an SSE register or transferring the SSE operand to
23971 // integer register and back.
23973 switch (N0.getOpcode()) {
23974 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23975 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23976 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23977 default: return SDValue();
23979 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23980 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23981 isa<ConstantSDNode>(N0.getOperand(1)) &&
23982 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23983 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23984 SDValue N000 = N0.getOperand(0).getOperand(0);
23985 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23986 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23992 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23993 /// generation and convert it from being a bunch of shuffles and extracts
23994 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23995 /// storing the value and loading scalars back, while for x64 we should
23996 /// use 64-bit extracts and shifts.
23997 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23998 TargetLowering::DAGCombinerInfo &DCI) {
23999 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
24002 SDValue InputVector = N->getOperand(0);
24003 SDLoc dl(InputVector);
24004 // Detect mmx to i32 conversion through a v2i32 elt extract.
24005 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
24006 N->getValueType(0) == MVT::i32 &&
24007 InputVector.getValueType() == MVT::v2i32) {
24009 // The bitcast source is a direct mmx result.
24010 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
24011 if (MMXSrc.getValueType() == MVT::x86mmx)
24012 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
24013 N->getValueType(0),
24014 InputVector.getNode()->getOperand(0));
24016 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
24017 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
24018 MMXSrc.getValueType() == MVT::i64) {
24019 SDValue MMXSrcOp = MMXSrc.getOperand(0);
24020 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
24021 MMXSrcOp.getValueType() == MVT::v1i64 &&
24022 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
24023 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
24024 N->getValueType(0), MMXSrcOp.getOperand(0));
24028 EVT VT = N->getValueType(0);
24030 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
24031 InputVector.getOpcode() == ISD::BITCAST &&
24032 isa<ConstantSDNode>(InputVector.getOperand(0))) {
24033 uint64_t ExtractedElt =
24034 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
24035 uint64_t InputValue =
24036 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
24037 uint64_t Res = (InputValue >> ExtractedElt) & 1;
24038 return DAG.getConstant(Res, dl, MVT::i1);
24040 // Only operate on vectors of 4 elements, where the alternative shuffling
24041 // gets to be more expensive.
24042 if (InputVector.getValueType() != MVT::v4i32)
24045 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
24046 // single use which is a sign-extend or zero-extend, and all elements are
24048 SmallVector<SDNode *, 4> Uses;
24049 unsigned ExtractedElements = 0;
24050 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
24051 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
24052 if (UI.getUse().getResNo() != InputVector.getResNo())
24055 SDNode *Extract = *UI;
24056 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
24059 if (Extract->getValueType(0) != MVT::i32)
24061 if (!Extract->hasOneUse())
24063 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
24064 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
24066 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
24069 // Record which element was extracted.
24070 ExtractedElements |=
24071 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
24073 Uses.push_back(Extract);
24076 // If not all the elements were used, this may not be worthwhile.
24077 if (ExtractedElements != 15)
24080 // Ok, we've now decided to do the transformation.
24081 // If 64-bit shifts are legal, use the extract-shift sequence,
24082 // otherwise bounce the vector off the cache.
24083 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24086 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
24087 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
24088 auto &DL = DAG.getDataLayout();
24089 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
24090 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
24091 DAG.getConstant(0, dl, VecIdxTy));
24092 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
24093 DAG.getConstant(1, dl, VecIdxTy));
24095 SDValue ShAmt = DAG.getConstant(
24096 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
24097 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
24098 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
24099 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
24100 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
24101 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
24102 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
24104 // Store the value to a temporary stack slot.
24105 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
24106 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
24107 MachinePointerInfo(), false, false, 0);
24109 EVT ElementType = InputVector.getValueType().getVectorElementType();
24110 unsigned EltSize = ElementType.getSizeInBits() / 8;
24112 // Replace each use (extract) with a load of the appropriate element.
24113 for (unsigned i = 0; i < 4; ++i) {
24114 uint64_t Offset = EltSize * i;
24115 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
24116 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
24118 SDValue ScalarAddr =
24119 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
24121 // Load the scalar.
24122 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
24123 ScalarAddr, MachinePointerInfo(),
24124 false, false, false, 0);
24129 // Replace the extracts
24130 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
24131 UE = Uses.end(); UI != UE; ++UI) {
24132 SDNode *Extract = *UI;
24134 SDValue Idx = Extract->getOperand(1);
24135 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
24136 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
24139 // The replacement was made in place; don't return anything.
24144 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
24145 const X86Subtarget *Subtarget) {
24147 SDValue Cond = N->getOperand(0);
24148 SDValue LHS = N->getOperand(1);
24149 SDValue RHS = N->getOperand(2);
24151 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
24152 SDValue CondSrc = Cond->getOperand(0);
24153 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
24154 Cond = CondSrc->getOperand(0);
24157 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
24160 // A vselect where all conditions and data are constants can be optimized into
24161 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
24162 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
24163 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
24166 unsigned MaskValue = 0;
24167 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
24170 MVT VT = N->getSimpleValueType(0);
24171 unsigned NumElems = VT.getVectorNumElements();
24172 SmallVector<int, 8> ShuffleMask(NumElems, -1);
24173 for (unsigned i = 0; i < NumElems; ++i) {
24174 // Be sure we emit undef where we can.
24175 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
24176 ShuffleMask[i] = -1;
24178 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
24181 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24182 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
24184 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
24187 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
24189 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
24190 TargetLowering::DAGCombinerInfo &DCI,
24191 const X86Subtarget *Subtarget) {
24193 SDValue Cond = N->getOperand(0);
24194 // Get the LHS/RHS of the select.
24195 SDValue LHS = N->getOperand(1);
24196 SDValue RHS = N->getOperand(2);
24197 EVT VT = LHS.getValueType();
24198 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24200 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
24201 // instructions match the semantics of the common C idiom x<y?x:y but not
24202 // x<=y?x:y, because of how they handle negative zero (which can be
24203 // ignored in unsafe-math mode).
24204 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
24205 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
24206 VT != MVT::f80 && VT != MVT::f128 &&
24207 (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
24208 (Subtarget->hasSSE2() ||
24209 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
24210 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24212 unsigned Opcode = 0;
24213 // Check for x CC y ? x : y.
24214 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
24215 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
24219 // Converting this to a min would handle NaNs incorrectly, and swapping
24220 // the operands would cause it to handle comparisons between positive
24221 // and negative zero incorrectly.
24222 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
24223 if (!DAG.getTarget().Options.UnsafeFPMath &&
24224 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
24226 std::swap(LHS, RHS);
24228 Opcode = X86ISD::FMIN;
24231 // Converting this to a min would handle comparisons between positive
24232 // and negative zero incorrectly.
24233 if (!DAG.getTarget().Options.UnsafeFPMath &&
24234 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
24236 Opcode = X86ISD::FMIN;
24239 // Converting this to a min would handle both negative zeros and NaNs
24240 // incorrectly, but we can swap the operands to fix both.
24241 std::swap(LHS, RHS);
24245 Opcode = X86ISD::FMIN;
24249 // Converting this to a max would handle comparisons between positive
24250 // and negative zero incorrectly.
24251 if (!DAG.getTarget().Options.UnsafeFPMath &&
24252 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
24254 Opcode = X86ISD::FMAX;
24257 // Converting this to a max would handle NaNs incorrectly, and swapping
24258 // the operands would cause it to handle comparisons between positive
24259 // and negative zero incorrectly.
24260 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
24261 if (!DAG.getTarget().Options.UnsafeFPMath &&
24262 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
24264 std::swap(LHS, RHS);
24266 Opcode = X86ISD::FMAX;
24269 // Converting this to a max would handle both negative zeros and NaNs
24270 // incorrectly, but we can swap the operands to fix both.
24271 std::swap(LHS, RHS);
24275 Opcode = X86ISD::FMAX;
24278 // Check for x CC y ? y : x -- a min/max with reversed arms.
24279 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
24280 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
24284 // Converting this to a min would handle comparisons between positive
24285 // and negative zero incorrectly, and swapping the operands would
24286 // cause it to handle NaNs incorrectly.
24287 if (!DAG.getTarget().Options.UnsafeFPMath &&
24288 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
24289 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
24291 std::swap(LHS, RHS);
24293 Opcode = X86ISD::FMIN;
24296 // Converting this to a min would handle NaNs incorrectly.
24297 if (!DAG.getTarget().Options.UnsafeFPMath &&
24298 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
24300 Opcode = X86ISD::FMIN;
24303 // Converting this to a min would handle both negative zeros and NaNs
24304 // incorrectly, but we can swap the operands to fix both.
24305 std::swap(LHS, RHS);
24309 Opcode = X86ISD::FMIN;
24313 // Converting this to a max would handle NaNs incorrectly.
24314 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
24316 Opcode = X86ISD::FMAX;
24319 // Converting this to a max would handle comparisons between positive
24320 // and negative zero incorrectly, and swapping the operands would
24321 // cause it to handle NaNs incorrectly.
24322 if (!DAG.getTarget().Options.UnsafeFPMath &&
24323 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
24324 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
24326 std::swap(LHS, RHS);
24328 Opcode = X86ISD::FMAX;
24331 // Converting this to a max would handle both negative zeros and NaNs
24332 // incorrectly, but we can swap the operands to fix both.
24333 std::swap(LHS, RHS);
24337 Opcode = X86ISD::FMAX;
24343 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
24346 EVT CondVT = Cond.getValueType();
24347 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
24348 CondVT.getVectorElementType() == MVT::i1) {
24349 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
24350 // lowering on KNL. In this case we convert it to
24351 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
24352 // The same situation for all 128 and 256-bit vectors of i8 and i16.
24353 // Since SKX these selects have a proper lowering.
24354 EVT OpVT = LHS.getValueType();
24355 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
24356 (OpVT.getVectorElementType() == MVT::i8 ||
24357 OpVT.getVectorElementType() == MVT::i16) &&
24358 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
24359 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
24360 DCI.AddToWorklist(Cond.getNode());
24361 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
24364 // If this is a select between two integer constants, try to do some
24366 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
24367 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
24368 // Don't do this for crazy integer types.
24369 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
24370 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
24371 // so that TrueC (the true value) is larger than FalseC.
24372 bool NeedsCondInvert = false;
24374 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
24375 // Efficiently invertible.
24376 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
24377 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
24378 isa<ConstantSDNode>(Cond.getOperand(1))))) {
24379 NeedsCondInvert = true;
24380 std::swap(TrueC, FalseC);
24383 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
24384 if (FalseC->getAPIntValue() == 0 &&
24385 TrueC->getAPIntValue().isPowerOf2()) {
24386 if (NeedsCondInvert) // Invert the condition if needed.
24387 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24388 DAG.getConstant(1, DL, Cond.getValueType()));
24390 // Zero extend the condition if needed.
24391 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
24393 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24394 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
24395 DAG.getConstant(ShAmt, DL, MVT::i8));
24398 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
24399 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24400 if (NeedsCondInvert) // Invert the condition if needed.
24401 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24402 DAG.getConstant(1, DL, Cond.getValueType()));
24404 // Zero extend the condition if needed.
24405 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24406 FalseC->getValueType(0), Cond);
24407 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24408 SDValue(FalseC, 0));
24411 // Optimize cases that will turn into an LEA instruction. This requires
24412 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24413 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24414 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24415 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24417 bool isFastMultiplier = false;
24419 switch ((unsigned char)Diff) {
24421 case 1: // result = add base, cond
24422 case 2: // result = lea base( , cond*2)
24423 case 3: // result = lea base(cond, cond*2)
24424 case 4: // result = lea base( , cond*4)
24425 case 5: // result = lea base(cond, cond*4)
24426 case 8: // result = lea base( , cond*8)
24427 case 9: // result = lea base(cond, cond*8)
24428 isFastMultiplier = true;
24433 if (isFastMultiplier) {
24434 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24435 if (NeedsCondInvert) // Invert the condition if needed.
24436 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24437 DAG.getConstant(1, DL, Cond.getValueType()));
24439 // Zero extend the condition if needed.
24440 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24442 // Scale the condition by the difference.
24444 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24445 DAG.getConstant(Diff, DL,
24446 Cond.getValueType()));
24448 // Add the base if non-zero.
24449 if (FalseC->getAPIntValue() != 0)
24450 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24451 SDValue(FalseC, 0));
24458 // Canonicalize max and min:
24459 // (x > y) ? x : y -> (x >= y) ? x : y
24460 // (x < y) ? x : y -> (x <= y) ? x : y
24461 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
24462 // the need for an extra compare
24463 // against zero. e.g.
24464 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
24466 // testl %edi, %edi
24468 // cmovgl %edi, %eax
24472 // cmovsl %eax, %edi
24473 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
24474 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
24475 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
24476 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24481 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
24482 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
24483 Cond.getOperand(0), Cond.getOperand(1), NewCC);
24484 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
24489 // Early exit check
24490 if (!TLI.isTypeLegal(VT))
24493 // Match VSELECTs into subs with unsigned saturation.
24494 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
24495 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
24496 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
24497 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
24498 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24500 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
24501 // left side invert the predicate to simplify logic below.
24503 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
24505 CC = ISD::getSetCCInverse(CC, true);
24506 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
24510 if (Other.getNode() && Other->getNumOperands() == 2 &&
24511 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
24512 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
24513 SDValue CondRHS = Cond->getOperand(1);
24515 // Look for a general sub with unsigned saturation first.
24516 // x >= y ? x-y : 0 --> subus x, y
24517 // x > y ? x-y : 0 --> subus x, y
24518 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
24519 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
24520 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
24522 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
24523 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
24524 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
24525 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
24526 // If the RHS is a constant we have to reverse the const
24527 // canonicalization.
24528 // x > C-1 ? x+-C : 0 --> subus x, C
24529 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
24530 CondRHSConst->getAPIntValue() ==
24531 (-OpRHSConst->getAPIntValue() - 1))
24532 return DAG.getNode(
24533 X86ISD::SUBUS, DL, VT, OpLHS,
24534 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
24536 // Another special case: If C was a sign bit, the sub has been
24537 // canonicalized into a xor.
24538 // FIXME: Would it be better to use computeKnownBits to determine
24539 // whether it's safe to decanonicalize the xor?
24540 // x s< 0 ? x^C : 0 --> subus x, C
24541 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
24542 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
24543 OpRHSConst->getAPIntValue().isSignBit())
24544 // Note that we have to rebuild the RHS constant here to ensure we
24545 // don't rely on particular values of undef lanes.
24546 return DAG.getNode(
24547 X86ISD::SUBUS, DL, VT, OpLHS,
24548 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
24553 // Simplify vector selection if condition value type matches vselect
24555 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
24556 assert(Cond.getValueType().isVector() &&
24557 "vector select expects a vector selector!");
24559 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
24560 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
24562 // Try invert the condition if true value is not all 1s and false value
24564 if (!TValIsAllOnes && !FValIsAllZeros &&
24565 // Check if the selector will be produced by CMPP*/PCMP*
24566 Cond.getOpcode() == ISD::SETCC &&
24567 // Check if SETCC has already been promoted
24568 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
24570 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
24571 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
24573 if (TValIsAllZeros || FValIsAllOnes) {
24574 SDValue CC = Cond.getOperand(2);
24575 ISD::CondCode NewCC =
24576 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
24577 Cond.getOperand(0).getValueType().isInteger());
24578 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
24579 std::swap(LHS, RHS);
24580 TValIsAllOnes = FValIsAllOnes;
24581 FValIsAllZeros = TValIsAllZeros;
24585 if (TValIsAllOnes || FValIsAllZeros) {
24588 if (TValIsAllOnes && FValIsAllZeros)
24590 else if (TValIsAllOnes)
24592 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
24593 else if (FValIsAllZeros)
24594 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
24595 DAG.getBitcast(CondVT, LHS));
24597 return DAG.getBitcast(VT, Ret);
24601 // We should generate an X86ISD::BLENDI from a vselect if its argument
24602 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
24603 // constants. This specific pattern gets generated when we split a
24604 // selector for a 512 bit vector in a machine without AVX512 (but with
24605 // 256-bit vectors), during legalization:
24607 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
24609 // Iff we find this pattern and the build_vectors are built from
24610 // constants, we translate the vselect into a shuffle_vector that we
24611 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
24612 if ((N->getOpcode() == ISD::VSELECT ||
24613 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
24614 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
24615 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
24616 if (Shuffle.getNode())
24620 // If this is a *dynamic* select (non-constant condition) and we can match
24621 // this node with one of the variable blend instructions, restructure the
24622 // condition so that the blends can use the high bit of each element and use
24623 // SimplifyDemandedBits to simplify the condition operand.
24624 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
24625 !DCI.isBeforeLegalize() &&
24626 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
24627 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
24629 // Don't optimize vector selects that map to mask-registers.
24633 // We can only handle the cases where VSELECT is directly legal on the
24634 // subtarget. We custom lower VSELECT nodes with constant conditions and
24635 // this makes it hard to see whether a dynamic VSELECT will correctly
24636 // lower, so we both check the operation's status and explicitly handle the
24637 // cases where a *dynamic* blend will fail even though a constant-condition
24638 // blend could be custom lowered.
24639 // FIXME: We should find a better way to handle this class of problems.
24640 // Potentially, we should combine constant-condition vselect nodes
24641 // pre-legalization into shuffles and not mark as many types as custom
24643 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
24645 // FIXME: We don't support i16-element blends currently. We could and
24646 // should support them by making *all* the bits in the condition be set
24647 // rather than just the high bit and using an i8-element blend.
24648 if (VT.getVectorElementType() == MVT::i16)
24650 // Dynamic blending was only available from SSE4.1 onward.
24651 if (VT.is128BitVector() && !Subtarget->hasSSE41())
24653 // Byte blends are only available in AVX2
24654 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
24657 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
24658 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
24660 APInt KnownZero, KnownOne;
24661 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
24662 DCI.isBeforeLegalizeOps());
24663 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
24664 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
24666 // If we changed the computation somewhere in the DAG, this change
24667 // will affect all users of Cond.
24668 // Make sure it is fine and update all the nodes so that we do not
24669 // use the generic VSELECT anymore. Otherwise, we may perform
24670 // wrong optimizations as we messed up with the actual expectation
24671 // for the vector boolean values.
24672 if (Cond != TLO.Old) {
24673 // Check all uses of that condition operand to check whether it will be
24674 // consumed by non-BLEND instructions, which may depend on all bits are
24676 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24678 if (I->getOpcode() != ISD::VSELECT)
24679 // TODO: Add other opcodes eventually lowered into BLEND.
24682 // Update all the users of the condition, before committing the change,
24683 // so that the VSELECT optimizations that expect the correct vector
24684 // boolean value will not be triggered.
24685 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24687 DAG.ReplaceAllUsesOfValueWith(
24689 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
24690 Cond, I->getOperand(1), I->getOperand(2)));
24691 DCI.CommitTargetLoweringOpt(TLO);
24694 // At this point, only Cond is changed. Change the condition
24695 // just for N to keep the opportunity to optimize all other
24696 // users their own way.
24697 DAG.ReplaceAllUsesOfValueWith(
24699 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
24700 TLO.New, N->getOperand(1), N->getOperand(2)));
24708 // Check whether a boolean test is testing a boolean value generated by
24709 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
24712 // Simplify the following patterns:
24713 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
24714 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
24715 // to (Op EFLAGS Cond)
24717 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
24718 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
24719 // to (Op EFLAGS !Cond)
24721 // where Op could be BRCOND or CMOV.
24723 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
24724 // Quit if not CMP and SUB with its value result used.
24725 if (Cmp.getOpcode() != X86ISD::CMP &&
24726 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
24729 // Quit if not used as a boolean value.
24730 if (CC != X86::COND_E && CC != X86::COND_NE)
24733 // Check CMP operands. One of them should be 0 or 1 and the other should be
24734 // an SetCC or extended from it.
24735 SDValue Op1 = Cmp.getOperand(0);
24736 SDValue Op2 = Cmp.getOperand(1);
24739 const ConstantSDNode* C = nullptr;
24740 bool needOppositeCond = (CC == X86::COND_E);
24741 bool checkAgainstTrue = false; // Is it a comparison against 1?
24743 if ((C = dyn_cast<ConstantSDNode>(Op1)))
24745 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
24747 else // Quit if all operands are not constants.
24750 if (C->getZExtValue() == 1) {
24751 needOppositeCond = !needOppositeCond;
24752 checkAgainstTrue = true;
24753 } else if (C->getZExtValue() != 0)
24754 // Quit if the constant is neither 0 or 1.
24757 bool truncatedToBoolWithAnd = false;
24758 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
24759 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24760 SetCC.getOpcode() == ISD::TRUNCATE ||
24761 SetCC.getOpcode() == ISD::AND) {
24762 if (SetCC.getOpcode() == ISD::AND) {
24764 if (isOneConstant(SetCC.getOperand(0)))
24766 if (isOneConstant(SetCC.getOperand(1)))
24770 SetCC = SetCC.getOperand(OpIdx);
24771 truncatedToBoolWithAnd = true;
24773 SetCC = SetCC.getOperand(0);
24776 switch (SetCC.getOpcode()) {
24777 case X86ISD::SETCC_CARRY:
24778 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24779 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24780 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24781 // truncated to i1 using 'and'.
24782 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24784 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24785 "Invalid use of SETCC_CARRY!");
24787 case X86ISD::SETCC:
24788 // Set the condition code or opposite one if necessary.
24789 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24790 if (needOppositeCond)
24791 CC = X86::GetOppositeBranchCondition(CC);
24792 return SetCC.getOperand(1);
24793 case X86ISD::CMOV: {
24794 // Check whether false/true value has canonical one, i.e. 0 or 1.
24795 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24796 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24797 // Quit if true value is not a constant.
24800 // Quit if false value is not a constant.
24802 SDValue Op = SetCC.getOperand(0);
24803 // Skip 'zext' or 'trunc' node.
24804 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24805 Op.getOpcode() == ISD::TRUNCATE)
24806 Op = Op.getOperand(0);
24807 // A special case for rdrand/rdseed, where 0 is set if false cond is
24809 if ((Op.getOpcode() != X86ISD::RDRAND &&
24810 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24813 // Quit if false value is not the constant 0 or 1.
24814 bool FValIsFalse = true;
24815 if (FVal && FVal->getZExtValue() != 0) {
24816 if (FVal->getZExtValue() != 1)
24818 // If FVal is 1, opposite cond is needed.
24819 needOppositeCond = !needOppositeCond;
24820 FValIsFalse = false;
24822 // Quit if TVal is not the constant opposite of FVal.
24823 if (FValIsFalse && TVal->getZExtValue() != 1)
24825 if (!FValIsFalse && TVal->getZExtValue() != 0)
24827 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24828 if (needOppositeCond)
24829 CC = X86::GetOppositeBranchCondition(CC);
24830 return SetCC.getOperand(3);
24837 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24839 /// (X86or (X86setcc) (X86setcc))
24840 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24841 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24842 X86::CondCode &CC1, SDValue &Flags,
24844 if (Cond->getOpcode() == X86ISD::CMP) {
24845 if (!isNullConstant(Cond->getOperand(1)))
24848 Cond = Cond->getOperand(0);
24853 SDValue SetCC0, SetCC1;
24854 switch (Cond->getOpcode()) {
24855 default: return false;
24862 SetCC0 = Cond->getOperand(0);
24863 SetCC1 = Cond->getOperand(1);
24867 // Make sure we have SETCC nodes, using the same flags value.
24868 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24869 SetCC1.getOpcode() != X86ISD::SETCC ||
24870 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24873 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24874 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24875 Flags = SetCC0->getOperand(1);
24879 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24880 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24881 TargetLowering::DAGCombinerInfo &DCI,
24882 const X86Subtarget *Subtarget) {
24885 // If the flag operand isn't dead, don't touch this CMOV.
24886 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24889 SDValue FalseOp = N->getOperand(0);
24890 SDValue TrueOp = N->getOperand(1);
24891 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24892 SDValue Cond = N->getOperand(3);
24894 if (CC == X86::COND_E || CC == X86::COND_NE) {
24895 switch (Cond.getOpcode()) {
24899 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24900 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24901 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24907 Flags = checkBoolTestSetCCCombine(Cond, CC);
24908 if (Flags.getNode() &&
24909 // Extra check as FCMOV only supports a subset of X86 cond.
24910 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24911 SDValue Ops[] = { FalseOp, TrueOp,
24912 DAG.getConstant(CC, DL, MVT::i8), Flags };
24913 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24916 // If this is a select between two integer constants, try to do some
24917 // optimizations. Note that the operands are ordered the opposite of SELECT
24919 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24920 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24921 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24922 // larger than FalseC (the false value).
24923 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24924 CC = X86::GetOppositeBranchCondition(CC);
24925 std::swap(TrueC, FalseC);
24926 std::swap(TrueOp, FalseOp);
24929 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24930 // This is efficient for any integer data type (including i8/i16) and
24932 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24933 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24934 DAG.getConstant(CC, DL, MVT::i8), Cond);
24936 // Zero extend the condition if needed.
24937 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24939 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24940 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24941 DAG.getConstant(ShAmt, DL, MVT::i8));
24942 if (N->getNumValues() == 2) // Dead flag value?
24943 return DCI.CombineTo(N, Cond, SDValue());
24947 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24948 // for any integer data type, including i8/i16.
24949 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24950 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24951 DAG.getConstant(CC, DL, MVT::i8), Cond);
24953 // Zero extend the condition if needed.
24954 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24955 FalseC->getValueType(0), Cond);
24956 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24957 SDValue(FalseC, 0));
24959 if (N->getNumValues() == 2) // Dead flag value?
24960 return DCI.CombineTo(N, Cond, SDValue());
24964 // Optimize cases that will turn into an LEA instruction. This requires
24965 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24966 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24967 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24968 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24970 bool isFastMultiplier = false;
24972 switch ((unsigned char)Diff) {
24974 case 1: // result = add base, cond
24975 case 2: // result = lea base( , cond*2)
24976 case 3: // result = lea base(cond, cond*2)
24977 case 4: // result = lea base( , cond*4)
24978 case 5: // result = lea base(cond, cond*4)
24979 case 8: // result = lea base( , cond*8)
24980 case 9: // result = lea base(cond, cond*8)
24981 isFastMultiplier = true;
24986 if (isFastMultiplier) {
24987 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24988 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24989 DAG.getConstant(CC, DL, MVT::i8), Cond);
24990 // Zero extend the condition if needed.
24991 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24993 // Scale the condition by the difference.
24995 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24996 DAG.getConstant(Diff, DL, Cond.getValueType()));
24998 // Add the base if non-zero.
24999 if (FalseC->getAPIntValue() != 0)
25000 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
25001 SDValue(FalseC, 0));
25002 if (N->getNumValues() == 2) // Dead flag value?
25003 return DCI.CombineTo(N, Cond, SDValue());
25010 // Handle these cases:
25011 // (select (x != c), e, c) -> select (x != c), e, x),
25012 // (select (x == c), c, e) -> select (x == c), x, e)
25013 // where the c is an integer constant, and the "select" is the combination
25014 // of CMOV and CMP.
25016 // The rationale for this change is that the conditional-move from a constant
25017 // needs two instructions, however, conditional-move from a register needs
25018 // only one instruction.
25020 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
25021 // some instruction-combining opportunities. This opt needs to be
25022 // postponed as late as possible.
25024 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
25025 // the DCI.xxxx conditions are provided to postpone the optimization as
25026 // late as possible.
25028 ConstantSDNode *CmpAgainst = nullptr;
25029 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
25030 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
25031 !isa<ConstantSDNode>(Cond.getOperand(0))) {
25033 if (CC == X86::COND_NE &&
25034 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
25035 CC = X86::GetOppositeBranchCondition(CC);
25036 std::swap(TrueOp, FalseOp);
25039 if (CC == X86::COND_E &&
25040 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
25041 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
25042 DAG.getConstant(CC, DL, MVT::i8), Cond };
25043 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
25048 // Fold and/or of setcc's to double CMOV:
25049 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
25050 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
25052 // This combine lets us generate:
25053 // cmovcc1 (jcc1 if we don't have CMOV)
25059 // cmovne (jne if we don't have CMOV)
25060 // When we can't use the CMOV instruction, it might increase branch
25062 // When we can use CMOV, or when there is no mispredict, this improves
25063 // throughput and reduces register pressure.
25065 if (CC == X86::COND_NE) {
25067 X86::CondCode CC0, CC1;
25069 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
25071 std::swap(FalseOp, TrueOp);
25072 CC0 = X86::GetOppositeBranchCondition(CC0);
25073 CC1 = X86::GetOppositeBranchCondition(CC1);
25076 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
25078 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
25079 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
25080 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
25081 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
25089 /// PerformMulCombine - Optimize a single multiply with constant into two
25090 /// in order to implement it with two cheaper instructions, e.g.
25091 /// LEA + SHL, LEA + LEA.
25092 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
25093 TargetLowering::DAGCombinerInfo &DCI) {
25094 // An imul is usually smaller than the alternative sequence.
25095 if (DAG.getMachineFunction().getFunction()->optForMinSize())
25098 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
25101 EVT VT = N->getValueType(0);
25102 if (VT != MVT::i64 && VT != MVT::i32)
25105 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
25108 uint64_t MulAmt = C->getZExtValue();
25109 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
25112 uint64_t MulAmt1 = 0;
25113 uint64_t MulAmt2 = 0;
25114 if ((MulAmt % 9) == 0) {
25116 MulAmt2 = MulAmt / 9;
25117 } else if ((MulAmt % 5) == 0) {
25119 MulAmt2 = MulAmt / 5;
25120 } else if ((MulAmt % 3) == 0) {
25122 MulAmt2 = MulAmt / 3;
25128 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
25130 if (isPowerOf2_64(MulAmt2) &&
25131 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
25132 // If second multiplifer is pow2, issue it first. We want the multiply by
25133 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
25135 std::swap(MulAmt1, MulAmt2);
25137 if (isPowerOf2_64(MulAmt1))
25138 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
25139 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
25141 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
25142 DAG.getConstant(MulAmt1, DL, VT));
25144 if (isPowerOf2_64(MulAmt2))
25145 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
25146 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
25148 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
25149 DAG.getConstant(MulAmt2, DL, VT));
25153 assert(MulAmt != 0 && MulAmt != (VT == MVT::i64 ? UINT64_MAX : UINT32_MAX)
25154 && "Both cases that could cause potential overflows should have "
25155 "already been handled.");
25156 if (isPowerOf2_64(MulAmt - 1))
25157 // (mul x, 2^N + 1) => (add (shl x, N), x)
25158 NewMul = DAG.getNode(ISD::ADD, DL, VT, N->getOperand(0),
25159 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
25160 DAG.getConstant(Log2_64(MulAmt - 1), DL,
25163 else if (isPowerOf2_64(MulAmt + 1))
25164 // (mul x, 2^N - 1) => (sub (shl x, N), x)
25165 NewMul = DAG.getNode(ISD::SUB, DL, VT, DAG.getNode(ISD::SHL, DL, VT,
25167 DAG.getConstant(Log2_64(MulAmt + 1),
25168 DL, MVT::i8)), N->getOperand(0));
25172 // Do not add new nodes to DAG combiner worklist.
25173 DCI.CombineTo(N, NewMul, false);
25178 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
25179 SDValue N0 = N->getOperand(0);
25180 SDValue N1 = N->getOperand(1);
25181 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
25182 EVT VT = N0.getValueType();
25184 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
25185 // since the result of setcc_c is all zero's or all ones.
25186 if (VT.isInteger() && !VT.isVector() &&
25187 N1C && N0.getOpcode() == ISD::AND &&
25188 N0.getOperand(1).getOpcode() == ISD::Constant) {
25189 SDValue N00 = N0.getOperand(0);
25190 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
25191 APInt ShAmt = N1C->getAPIntValue();
25192 Mask = Mask.shl(ShAmt);
25193 bool MaskOK = false;
25194 // We can handle cases concerning bit-widening nodes containing setcc_c if
25195 // we carefully interrogate the mask to make sure we are semantics
25197 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
25198 // of the underlying setcc_c operation if the setcc_c was zero extended.
25199 // Consider the following example:
25200 // zext(setcc_c) -> i32 0x0000FFFF
25201 // c1 -> i32 0x0000FFFF
25202 // c2 -> i32 0x00000001
25203 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
25204 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
25205 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25207 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
25208 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
25210 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
25211 N00.getOpcode() == ISD::ANY_EXTEND) &&
25212 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
25213 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
25215 if (MaskOK && Mask != 0) {
25217 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
25221 // Hardware support for vector shifts is sparse which makes us scalarize the
25222 // vector operations in many cases. Also, on sandybridge ADD is faster than
25224 // (shl V, 1) -> add V,V
25225 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
25226 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
25227 assert(N0.getValueType().isVector() && "Invalid vector shift type");
25228 // We shift all of the values by one. In many cases we do not have
25229 // hardware support for this operation. This is better expressed as an ADD
25231 if (N1SplatC->getAPIntValue() == 1)
25232 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
25238 static SDValue PerformSRACombine(SDNode *N, SelectionDAG &DAG) {
25239 SDValue N0 = N->getOperand(0);
25240 SDValue N1 = N->getOperand(1);
25241 EVT VT = N0.getValueType();
25242 unsigned Size = VT.getSizeInBits();
25244 // fold (ashr (shl, a, [56,48,32,24,16]), SarConst)
25245 // into (shl, (sext (a), [56,48,32,24,16] - SarConst)) or
25246 // into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
25247 // depending on sign of (SarConst - [56,48,32,24,16])
25249 // sexts in X86 are MOVs. The MOVs have the same code size
25250 // as above SHIFTs (only SHIFT on 1 has lower code size).
25251 // However the MOVs have 2 advantages to a SHIFT:
25252 // 1. MOVs can write to a register that differs from source
25253 // 2. MOVs accept memory operands
25255 if (!VT.isInteger() || VT.isVector() || N1.getOpcode() != ISD::Constant ||
25256 N0.getOpcode() != ISD::SHL || !N0.hasOneUse() ||
25257 N0.getOperand(1).getOpcode() != ISD::Constant)
25260 SDValue N00 = N0.getOperand(0);
25261 SDValue N01 = N0.getOperand(1);
25262 APInt ShlConst = (cast<ConstantSDNode>(N01))->getAPIntValue();
25263 APInt SarConst = (cast<ConstantSDNode>(N1))->getAPIntValue();
25264 EVT CVT = N1.getValueType();
25266 if (SarConst.isNegative())
25269 for (MVT SVT : MVT::integer_valuetypes()) {
25270 unsigned ShiftSize = SVT.getSizeInBits();
25271 // skipping types without corresponding sext/zext and
25272 // ShlConst that is not one of [56,48,32,24,16]
25273 if (ShiftSize < 8 || ShiftSize > 64 || ShlConst != Size - ShiftSize)
25277 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, N00, DAG.getValueType(SVT));
25278 SarConst = SarConst - (Size - ShiftSize);
25281 else if (SarConst.isNegative())
25282 return DAG.getNode(ISD::SHL, DL, VT, NN,
25283 DAG.getConstant(-SarConst, DL, CVT));
25285 return DAG.getNode(ISD::SRA, DL, VT, NN,
25286 DAG.getConstant(SarConst, DL, CVT));
25291 /// \brief Returns a vector of 0s if the node in input is a vector logical
25292 /// shift by a constant amount which is known to be bigger than or equal
25293 /// to the vector element size in bits.
25294 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
25295 const X86Subtarget *Subtarget) {
25296 EVT VT = N->getValueType(0);
25298 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
25299 (!Subtarget->hasInt256() ||
25300 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
25303 SDValue Amt = N->getOperand(1);
25305 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
25306 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
25307 APInt ShiftAmt = AmtSplat->getAPIntValue();
25308 unsigned MaxAmount =
25309 VT.getSimpleVT().getVectorElementType().getSizeInBits();
25311 // SSE2/AVX2 logical shifts always return a vector of 0s
25312 // if the shift amount is bigger than or equal to
25313 // the element size. The constant shift amount will be
25314 // encoded as a 8-bit immediate.
25315 if (ShiftAmt.trunc(8).uge(MaxAmount))
25316 return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, DL);
25322 /// PerformShiftCombine - Combine shifts.
25323 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
25324 TargetLowering::DAGCombinerInfo &DCI,
25325 const X86Subtarget *Subtarget) {
25326 if (N->getOpcode() == ISD::SHL)
25327 if (SDValue V = PerformSHLCombine(N, DAG))
25330 if (N->getOpcode() == ISD::SRA)
25331 if (SDValue V = PerformSRACombine(N, DAG))
25334 // Try to fold this logical shift into a zero vector.
25335 if (N->getOpcode() != ISD::SRA)
25336 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
25342 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
25343 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
25344 // and friends. Likewise for OR -> CMPNEQSS.
25345 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
25346 TargetLowering::DAGCombinerInfo &DCI,
25347 const X86Subtarget *Subtarget) {
25350 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
25351 // we're requiring SSE2 for both.
25352 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
25353 SDValue N0 = N->getOperand(0);
25354 SDValue N1 = N->getOperand(1);
25355 SDValue CMP0 = N0->getOperand(1);
25356 SDValue CMP1 = N1->getOperand(1);
25359 // The SETCCs should both refer to the same CMP.
25360 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
25363 SDValue CMP00 = CMP0->getOperand(0);
25364 SDValue CMP01 = CMP0->getOperand(1);
25365 EVT VT = CMP00.getValueType();
25367 if (VT == MVT::f32 || VT == MVT::f64) {
25368 bool ExpectingFlags = false;
25369 // Check for any users that want flags:
25370 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
25371 !ExpectingFlags && UI != UE; ++UI)
25372 switch (UI->getOpcode()) {
25377 ExpectingFlags = true;
25379 case ISD::CopyToReg:
25380 case ISD::SIGN_EXTEND:
25381 case ISD::ZERO_EXTEND:
25382 case ISD::ANY_EXTEND:
25386 if (!ExpectingFlags) {
25387 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
25388 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
25390 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
25391 X86::CondCode tmp = cc0;
25396 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
25397 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
25398 // FIXME: need symbolic constants for these magic numbers.
25399 // See X86ATTInstPrinter.cpp:printSSECC().
25400 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
25401 if (Subtarget->hasAVX512()) {
25402 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
25404 DAG.getConstant(x86cc, DL, MVT::i8));
25405 if (N->getValueType(0) != MVT::i1)
25406 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
25410 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
25411 CMP00.getValueType(), CMP00, CMP01,
25412 DAG.getConstant(x86cc, DL,
25415 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
25416 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
25418 if (is64BitFP && !Subtarget->is64Bit()) {
25419 // On a 32-bit target, we cannot bitcast the 64-bit float to a
25420 // 64-bit integer, since that's not a legal type. Since
25421 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
25422 // bits, but can do this little dance to extract the lowest 32 bits
25423 // and work with those going forward.
25424 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
25426 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
25427 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
25428 Vector32, DAG.getIntPtrConstant(0, DL));
25432 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
25433 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
25434 DAG.getConstant(1, DL, IntVT));
25435 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
25437 return OneBitOfTruth;
25445 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
25446 /// so it can be folded inside ANDNP.
25447 static bool CanFoldXORWithAllOnes(const SDNode *N) {
25448 EVT VT = N->getValueType(0);
25450 // Match direct AllOnes for 128 and 256-bit vectors
25451 if (ISD::isBuildVectorAllOnes(N))
25454 // Look through a bit convert.
25455 if (N->getOpcode() == ISD::BITCAST)
25456 N = N->getOperand(0).getNode();
25458 // Sometimes the operand may come from a insert_subvector building a 256-bit
25460 if (VT.is256BitVector() &&
25461 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
25462 SDValue V1 = N->getOperand(0);
25463 SDValue V2 = N->getOperand(1);
25465 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
25466 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
25467 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
25468 ISD::isBuildVectorAllOnes(V2.getNode()))
25475 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
25476 // register. In most cases we actually compare or select YMM-sized registers
25477 // and mixing the two types creates horrible code. This method optimizes
25478 // some of the transition sequences.
25479 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
25480 TargetLowering::DAGCombinerInfo &DCI,
25481 const X86Subtarget *Subtarget) {
25482 EVT VT = N->getValueType(0);
25483 if (!VT.is256BitVector())
25486 assert((N->getOpcode() == ISD::ANY_EXTEND ||
25487 N->getOpcode() == ISD::ZERO_EXTEND ||
25488 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
25490 SDValue Narrow = N->getOperand(0);
25491 EVT NarrowVT = Narrow->getValueType(0);
25492 if (!NarrowVT.is128BitVector())
25495 if (Narrow->getOpcode() != ISD::XOR &&
25496 Narrow->getOpcode() != ISD::AND &&
25497 Narrow->getOpcode() != ISD::OR)
25500 SDValue N0 = Narrow->getOperand(0);
25501 SDValue N1 = Narrow->getOperand(1);
25504 // The Left side has to be a trunc.
25505 if (N0.getOpcode() != ISD::TRUNCATE)
25508 // The type of the truncated inputs.
25509 EVT WideVT = N0->getOperand(0)->getValueType(0);
25513 // The right side has to be a 'trunc' or a constant vector.
25514 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
25515 ConstantSDNode *RHSConstSplat = nullptr;
25516 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
25517 RHSConstSplat = RHSBV->getConstantSplatNode();
25518 if (!RHSTrunc && !RHSConstSplat)
25521 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25523 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
25526 // Set N0 and N1 to hold the inputs to the new wide operation.
25527 N0 = N0->getOperand(0);
25528 if (RHSConstSplat) {
25529 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
25530 SDValue(RHSConstSplat, 0));
25531 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
25532 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
25533 } else if (RHSTrunc) {
25534 N1 = N1->getOperand(0);
25537 // Generate the wide operation.
25538 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
25539 unsigned Opcode = N->getOpcode();
25541 case ISD::ANY_EXTEND:
25543 case ISD::ZERO_EXTEND: {
25544 unsigned InBits = NarrowVT.getScalarSizeInBits();
25545 APInt Mask = APInt::getAllOnesValue(InBits);
25546 Mask = Mask.zext(VT.getScalarSizeInBits());
25547 return DAG.getNode(ISD::AND, DL, VT,
25548 Op, DAG.getConstant(Mask, DL, VT));
25550 case ISD::SIGN_EXTEND:
25551 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
25552 Op, DAG.getValueType(NarrowVT));
25554 llvm_unreachable("Unexpected opcode");
25558 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
25559 TargetLowering::DAGCombinerInfo &DCI,
25560 const X86Subtarget *Subtarget) {
25561 SDValue N0 = N->getOperand(0);
25562 SDValue N1 = N->getOperand(1);
25565 // A vector zext_in_reg may be represented as a shuffle,
25566 // feeding into a bitcast (this represents anyext) feeding into
25567 // an and with a mask.
25568 // We'd like to try to combine that into a shuffle with zero
25569 // plus a bitcast, removing the and.
25570 if (N0.getOpcode() != ISD::BITCAST ||
25571 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
25574 // The other side of the AND should be a splat of 2^C, where C
25575 // is the number of bits in the source type.
25576 if (N1.getOpcode() == ISD::BITCAST)
25577 N1 = N1.getOperand(0);
25578 if (N1.getOpcode() != ISD::BUILD_VECTOR)
25580 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
25582 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
25583 EVT SrcType = Shuffle->getValueType(0);
25585 // We expect a single-source shuffle
25586 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
25589 unsigned SrcSize = SrcType.getScalarSizeInBits();
25591 APInt SplatValue, SplatUndef;
25592 unsigned SplatBitSize;
25594 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
25595 SplatBitSize, HasAnyUndefs))
25598 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
25599 // Make sure the splat matches the mask we expect
25600 if (SplatBitSize > ResSize ||
25601 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
25604 // Make sure the input and output size make sense
25605 if (SrcSize >= ResSize || ResSize % SrcSize)
25608 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
25609 // The number of u's between each two values depends on the ratio between
25610 // the source and dest type.
25611 unsigned ZextRatio = ResSize / SrcSize;
25612 bool IsZext = true;
25613 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
25614 if (i % ZextRatio) {
25615 if (Shuffle->getMaskElt(i) > 0) {
25621 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
25622 // Expected element number
25632 // Ok, perform the transformation - replace the shuffle with
25633 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
25634 // (instead of undef) where the k elements come from the zero vector.
25635 SmallVector<int, 8> Mask;
25636 unsigned NumElems = SrcType.getVectorNumElements();
25637 for (unsigned i = 0; i < NumElems; ++i)
25639 Mask.push_back(NumElems);
25641 Mask.push_back(i / ZextRatio);
25643 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
25644 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
25645 return DAG.getBitcast(N0.getValueType(), NewShuffle);
25648 /// If both input operands of a logic op are being cast from floating point
25649 /// types, try to convert this into a floating point logic node to avoid
25650 /// unnecessary moves from SSE to integer registers.
25651 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
25652 const X86Subtarget *Subtarget) {
25653 unsigned FPOpcode = ISD::DELETED_NODE;
25654 if (N->getOpcode() == ISD::AND)
25655 FPOpcode = X86ISD::FAND;
25656 else if (N->getOpcode() == ISD::OR)
25657 FPOpcode = X86ISD::FOR;
25658 else if (N->getOpcode() == ISD::XOR)
25659 FPOpcode = X86ISD::FXOR;
25661 assert(FPOpcode != ISD::DELETED_NODE &&
25662 "Unexpected input node for FP logic conversion");
25664 EVT VT = N->getValueType(0);
25665 SDValue N0 = N->getOperand(0);
25666 SDValue N1 = N->getOperand(1);
25668 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
25669 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
25670 (Subtarget->hasSSE2() && VT == MVT::i64))) {
25671 SDValue N00 = N0.getOperand(0);
25672 SDValue N10 = N1.getOperand(0);
25673 EVT N00Type = N00.getValueType();
25674 EVT N10Type = N10.getValueType();
25675 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
25676 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
25677 return DAG.getBitcast(VT, FPLogic);
25683 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
25684 TargetLowering::DAGCombinerInfo &DCI,
25685 const X86Subtarget *Subtarget) {
25686 if (DCI.isBeforeLegalizeOps())
25689 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
25692 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25695 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25698 EVT VT = N->getValueType(0);
25699 SDValue N0 = N->getOperand(0);
25700 SDValue N1 = N->getOperand(1);
25703 // Create BEXTR instructions
25704 // BEXTR is ((X >> imm) & (2**size-1))
25705 if (VT == MVT::i32 || VT == MVT::i64) {
25706 // Check for BEXTR.
25707 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
25708 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
25709 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
25710 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25711 if (MaskNode && ShiftNode) {
25712 uint64_t Mask = MaskNode->getZExtValue();
25713 uint64_t Shift = ShiftNode->getZExtValue();
25714 if (isMask_64(Mask)) {
25715 uint64_t MaskSize = countPopulation(Mask);
25716 if (Shift + MaskSize <= VT.getSizeInBits())
25717 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
25718 DAG.getConstant(Shift | (MaskSize << 8), DL,
25727 // Want to form ANDNP nodes:
25728 // 1) In the hopes of then easily combining them with OR and AND nodes
25729 // to form PBLEND/PSIGN.
25730 // 2) To match ANDN packed intrinsics
25731 if (VT != MVT::v2i64 && VT != MVT::v4i64)
25734 // Check LHS for vnot
25735 if (N0.getOpcode() == ISD::XOR &&
25736 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
25737 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
25738 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
25740 // Check RHS for vnot
25741 if (N1.getOpcode() == ISD::XOR &&
25742 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
25743 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
25744 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
25749 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
25750 TargetLowering::DAGCombinerInfo &DCI,
25751 const X86Subtarget *Subtarget) {
25752 if (DCI.isBeforeLegalizeOps())
25755 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25758 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25761 SDValue N0 = N->getOperand(0);
25762 SDValue N1 = N->getOperand(1);
25763 EVT VT = N->getValueType(0);
25765 // look for psign/blend
25766 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
25767 if (!Subtarget->hasSSSE3() ||
25768 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
25771 // Canonicalize pandn to RHS
25772 if (N0.getOpcode() == X86ISD::ANDNP)
25774 // or (and (m, y), (pandn m, x))
25775 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
25776 SDValue Mask = N1.getOperand(0);
25777 SDValue X = N1.getOperand(1);
25779 if (N0.getOperand(0) == Mask)
25780 Y = N0.getOperand(1);
25781 if (N0.getOperand(1) == Mask)
25782 Y = N0.getOperand(0);
25784 // Check to see if the mask appeared in both the AND and ANDNP and
25788 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
25789 // Look through mask bitcast.
25790 if (Mask.getOpcode() == ISD::BITCAST)
25791 Mask = Mask.getOperand(0);
25792 if (X.getOpcode() == ISD::BITCAST)
25793 X = X.getOperand(0);
25794 if (Y.getOpcode() == ISD::BITCAST)
25795 Y = Y.getOperand(0);
25797 EVT MaskVT = Mask.getValueType();
25799 // Validate that the Mask operand is a vector sra node.
25800 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
25801 // there is no psrai.b
25802 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
25803 unsigned SraAmt = ~0;
25804 if (Mask.getOpcode() == ISD::SRA) {
25805 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
25806 if (auto *AmtConst = AmtBV->getConstantSplatNode())
25807 SraAmt = AmtConst->getZExtValue();
25808 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
25809 SDValue SraC = Mask.getOperand(1);
25810 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
25812 if ((SraAmt + 1) != EltBits)
25817 // Now we know we at least have a plendvb with the mask val. See if
25818 // we can form a psignb/w/d.
25819 // psign = x.type == y.type == mask.type && y = sub(0, x);
25820 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25821 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
25822 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
25823 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
25824 "Unsupported VT for PSIGN");
25825 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
25826 return DAG.getBitcast(VT, Mask);
25828 // PBLENDVB only available on SSE 4.1
25829 if (!Subtarget->hasSSE41())
25832 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
25834 X = DAG.getBitcast(BlendVT, X);
25835 Y = DAG.getBitcast(BlendVT, Y);
25836 Mask = DAG.getBitcast(BlendVT, Mask);
25837 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
25838 return DAG.getBitcast(VT, Mask);
25842 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
25845 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
25846 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
25848 // SHLD/SHRD instructions have lower register pressure, but on some
25849 // platforms they have higher latency than the equivalent
25850 // series of shifts/or that would otherwise be generated.
25851 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25852 // have higher latencies and we are not optimizing for size.
25853 if (!OptForSize && Subtarget->isSHLDSlow())
25856 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25858 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25860 if (!N0.hasOneUse() || !N1.hasOneUse())
25863 SDValue ShAmt0 = N0.getOperand(1);
25864 if (ShAmt0.getValueType() != MVT::i8)
25866 SDValue ShAmt1 = N1.getOperand(1);
25867 if (ShAmt1.getValueType() != MVT::i8)
25869 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25870 ShAmt0 = ShAmt0.getOperand(0);
25871 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25872 ShAmt1 = ShAmt1.getOperand(0);
25875 unsigned Opc = X86ISD::SHLD;
25876 SDValue Op0 = N0.getOperand(0);
25877 SDValue Op1 = N1.getOperand(0);
25878 if (ShAmt0.getOpcode() == ISD::SUB) {
25879 Opc = X86ISD::SHRD;
25880 std::swap(Op0, Op1);
25881 std::swap(ShAmt0, ShAmt1);
25884 unsigned Bits = VT.getSizeInBits();
25885 if (ShAmt1.getOpcode() == ISD::SUB) {
25886 SDValue Sum = ShAmt1.getOperand(0);
25887 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25888 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25889 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25890 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25891 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25892 return DAG.getNode(Opc, DL, VT,
25894 DAG.getNode(ISD::TRUNCATE, DL,
25897 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25898 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25900 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25901 return DAG.getNode(Opc, DL, VT,
25902 N0.getOperand(0), N1.getOperand(0),
25903 DAG.getNode(ISD::TRUNCATE, DL,
25910 // Generate NEG and CMOV for integer abs.
25911 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25912 EVT VT = N->getValueType(0);
25914 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25915 // 8-bit integer abs to NEG and CMOV.
25916 if (VT.isInteger() && VT.getSizeInBits() == 8)
25919 SDValue N0 = N->getOperand(0);
25920 SDValue N1 = N->getOperand(1);
25923 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25924 // and change it to SUB and CMOV.
25925 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25926 N0.getOpcode() == ISD::ADD &&
25927 N0.getOperand(1) == N1 &&
25928 N1.getOpcode() == ISD::SRA &&
25929 N1.getOperand(0) == N0.getOperand(0))
25930 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25931 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25932 // Generate SUB & CMOV.
25933 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25934 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25936 SDValue Ops[] = { N0.getOperand(0), Neg,
25937 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25938 SDValue(Neg.getNode(), 1) };
25939 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25944 // Try to turn tests against the signbit in the form of:
25945 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25948 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25949 // This is only worth doing if the output type is i8.
25950 if (N->getValueType(0) != MVT::i8)
25953 SDValue N0 = N->getOperand(0);
25954 SDValue N1 = N->getOperand(1);
25956 // We should be performing an xor against a truncated shift.
25957 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25960 // Make sure we are performing an xor against one.
25961 if (!isOneConstant(N1))
25964 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25965 SDValue Shift = N0.getOperand(0);
25966 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25969 // Make sure we are truncating from one of i16, i32 or i64.
25970 EVT ShiftTy = Shift.getValueType();
25971 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25974 // Make sure the shift amount extracts the sign bit.
25975 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25976 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25979 // Create a greater-than comparison against -1.
25980 // N.B. Using SETGE against 0 works but we want a canonical looking
25981 // comparison, using SETGT matches up with what TranslateX86CC.
25983 SDValue ShiftOp = Shift.getOperand(0);
25984 EVT ShiftOpTy = ShiftOp.getValueType();
25985 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25986 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25990 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25991 TargetLowering::DAGCombinerInfo &DCI,
25992 const X86Subtarget *Subtarget) {
25993 if (DCI.isBeforeLegalizeOps())
25996 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25999 if (Subtarget->hasCMov())
26000 if (SDValue RV = performIntegerAbsCombine(N, DAG))
26003 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
26009 /// This function detects the AVG pattern between vectors of unsigned i8/i16,
26010 /// which is c = (a + b + 1) / 2, and replace this operation with the efficient
26011 /// X86ISD::AVG instruction.
26012 static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
26013 const X86Subtarget *Subtarget, SDLoc DL) {
26014 if (!VT.isVector() || !VT.isSimple())
26016 EVT InVT = In.getValueType();
26017 unsigned NumElems = VT.getVectorNumElements();
26019 EVT ScalarVT = VT.getVectorElementType();
26020 if (!((ScalarVT == MVT::i8 || ScalarVT == MVT::i16) &&
26021 isPowerOf2_32(NumElems)))
26024 // InScalarVT is the intermediate type in AVG pattern and it should be greater
26025 // than the original input type (i8/i16).
26026 EVT InScalarVT = InVT.getVectorElementType();
26027 if (InScalarVT.getSizeInBits() <= ScalarVT.getSizeInBits())
26030 if (Subtarget->hasAVX512()) {
26031 if (VT.getSizeInBits() > 512)
26033 } else if (Subtarget->hasAVX2()) {
26034 if (VT.getSizeInBits() > 256)
26037 if (VT.getSizeInBits() > 128)
26041 // Detect the following pattern:
26043 // %1 = zext <N x i8> %a to <N x i32>
26044 // %2 = zext <N x i8> %b to <N x i32>
26045 // %3 = add nuw nsw <N x i32> %1, <i32 1 x N>
26046 // %4 = add nuw nsw <N x i32> %3, %2
26047 // %5 = lshr <N x i32> %N, <i32 1 x N>
26048 // %6 = trunc <N x i32> %5 to <N x i8>
26050 // In AVX512, the last instruction can also be a trunc store.
26052 if (In.getOpcode() != ISD::SRL)
26055 // A lambda checking the given SDValue is a constant vector and each element
26056 // is in the range [Min, Max].
26057 auto IsConstVectorInRange = [](SDValue V, unsigned Min, unsigned Max) {
26058 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(V);
26059 if (!BV || !BV->isConstant())
26061 for (unsigned i = 0, e = V.getNumOperands(); i < e; i++) {
26062 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(i));
26065 uint64_t Val = C->getZExtValue();
26066 if (Val < Min || Val > Max)
26072 // Check if each element of the vector is left-shifted by one.
26073 auto LHS = In.getOperand(0);
26074 auto RHS = In.getOperand(1);
26075 if (!IsConstVectorInRange(RHS, 1, 1))
26077 if (LHS.getOpcode() != ISD::ADD)
26080 // Detect a pattern of a + b + 1 where the order doesn't matter.
26081 SDValue Operands[3];
26082 Operands[0] = LHS.getOperand(0);
26083 Operands[1] = LHS.getOperand(1);
26085 // Take care of the case when one of the operands is a constant vector whose
26086 // element is in the range [1, 256].
26087 if (IsConstVectorInRange(Operands[1], 1, ScalarVT == MVT::i8 ? 256 : 65536) &&
26088 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
26089 Operands[0].getOperand(0).getValueType() == VT) {
26090 // The pattern is detected. Subtract one from the constant vector, then
26091 // demote it and emit X86ISD::AVG instruction.
26092 SDValue One = DAG.getConstant(1, DL, InScalarVT);
26093 SDValue Ones = DAG.getNode(ISD::BUILD_VECTOR, DL, InVT,
26094 SmallVector<SDValue, 8>(NumElems, One));
26095 Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], Ones);
26096 Operands[1] = DAG.getNode(ISD::TRUNCATE, DL, VT, Operands[1]);
26097 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
26101 if (Operands[0].getOpcode() == ISD::ADD)
26102 std::swap(Operands[0], Operands[1]);
26103 else if (Operands[1].getOpcode() != ISD::ADD)
26105 Operands[2] = Operands[1].getOperand(0);
26106 Operands[1] = Operands[1].getOperand(1);
26108 // Now we have three operands of two additions. Check that one of them is a
26109 // constant vector with ones, and the other two are promoted from i8/i16.
26110 for (int i = 0; i < 3; ++i) {
26111 if (!IsConstVectorInRange(Operands[i], 1, 1))
26113 std::swap(Operands[i], Operands[2]);
26115 // Check if Operands[0] and Operands[1] are results of type promotion.
26116 for (int j = 0; j < 2; ++j)
26117 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
26118 Operands[j].getOperand(0).getValueType() != VT)
26121 // The pattern is detected, emit X86ISD::AVG instruction.
26122 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
26123 Operands[1].getOperand(0));
26129 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
26130 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
26131 TargetLowering::DAGCombinerInfo &DCI,
26132 const X86Subtarget *Subtarget) {
26133 LoadSDNode *Ld = cast<LoadSDNode>(N);
26134 EVT RegVT = Ld->getValueType(0);
26135 EVT MemVT = Ld->getMemoryVT();
26137 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26139 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
26140 // into two 16-byte operations.
26141 ISD::LoadExtType Ext = Ld->getExtensionType();
26143 unsigned AddressSpace = Ld->getAddressSpace();
26144 unsigned Alignment = Ld->getAlignment();
26145 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
26146 Ext == ISD::NON_EXTLOAD &&
26147 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
26148 AddressSpace, Alignment, &Fast) && !Fast) {
26149 unsigned NumElems = RegVT.getVectorNumElements();
26153 SDValue Ptr = Ld->getBasePtr();
26154 SDValue Increment =
26155 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
26157 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
26159 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
26160 Ld->getPointerInfo(), Ld->isVolatile(),
26161 Ld->isNonTemporal(), Ld->isInvariant(),
26163 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
26164 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
26165 Ld->getPointerInfo(), Ld->isVolatile(),
26166 Ld->isNonTemporal(), Ld->isInvariant(),
26167 std::min(16U, Alignment));
26168 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
26170 Load2.getValue(1));
26172 SDValue NewVec = DAG.getUNDEF(RegVT);
26173 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
26174 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
26175 return DCI.CombineTo(N, NewVec, TF, true);
26181 /// PerformMLOADCombine - Resolve extending loads
26182 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
26183 TargetLowering::DAGCombinerInfo &DCI,
26184 const X86Subtarget *Subtarget) {
26185 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
26186 if (Mld->getExtensionType() != ISD::SEXTLOAD)
26189 EVT VT = Mld->getValueType(0);
26190 unsigned NumElems = VT.getVectorNumElements();
26191 EVT LdVT = Mld->getMemoryVT();
26194 assert(LdVT != VT && "Cannot extend to the same type");
26195 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
26196 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
26197 // From, To sizes and ElemCount must be pow of two
26198 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
26199 "Unexpected size for extending masked load");
26201 unsigned SizeRatio = ToSz / FromSz;
26202 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
26204 // Create a type on which we perform the shuffle
26205 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
26206 LdVT.getScalarType(), NumElems*SizeRatio);
26207 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
26209 // Convert Src0 value
26210 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
26211 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
26212 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
26213 for (unsigned i = 0; i != NumElems; ++i)
26214 ShuffleVec[i] = i * SizeRatio;
26216 // Can't shuffle using an illegal type.
26217 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
26218 "WideVecVT should be legal");
26219 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
26220 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
26222 // Prepare the new mask
26224 SDValue Mask = Mld->getMask();
26225 if (Mask.getValueType() == VT) {
26226 // Mask and original value have the same type
26227 NewMask = DAG.getBitcast(WideVecVT, Mask);
26228 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
26229 for (unsigned i = 0; i != NumElems; ++i)
26230 ShuffleVec[i] = i * SizeRatio;
26231 for (unsigned i = NumElems; i != NumElems * SizeRatio; ++i)
26232 ShuffleVec[i] = NumElems * SizeRatio;
26233 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
26234 DAG.getConstant(0, dl, WideVecVT),
26238 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
26239 unsigned WidenNumElts = NumElems*SizeRatio;
26240 unsigned MaskNumElts = VT.getVectorNumElements();
26241 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
26244 unsigned NumConcat = WidenNumElts / MaskNumElts;
26245 SmallVector<SDValue, 16> Ops(NumConcat);
26246 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
26248 for (unsigned i = 1; i != NumConcat; ++i)
26251 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
26254 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
26255 Mld->getBasePtr(), NewMask, WideSrc0,
26256 Mld->getMemoryVT(), Mld->getMemOperand(),
26258 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
26259 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
26261 /// PerformMSTORECombine - Resolve truncating stores
26262 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
26263 const X86Subtarget *Subtarget) {
26264 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
26265 if (!Mst->isTruncatingStore())
26268 EVT VT = Mst->getValue().getValueType();
26269 unsigned NumElems = VT.getVectorNumElements();
26270 EVT StVT = Mst->getMemoryVT();
26273 assert(StVT != VT && "Cannot truncate to the same type");
26274 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
26275 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
26277 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26279 // The truncating store is legal in some cases. For example
26280 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
26281 // are designated for truncate store.
26282 // In this case we don't need any further transformations.
26283 if (TLI.isTruncStoreLegal(VT, StVT))
26286 // From, To sizes and ElemCount must be pow of two
26287 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
26288 "Unexpected size for truncating masked store");
26289 // We are going to use the original vector elt for storing.
26290 // Accumulated smaller vector elements must be a multiple of the store size.
26291 assert (((NumElems * FromSz) % ToSz) == 0 &&
26292 "Unexpected ratio for truncating masked store");
26294 unsigned SizeRatio = FromSz / ToSz;
26295 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
26297 // Create a type on which we perform the shuffle
26298 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
26299 StVT.getScalarType(), NumElems*SizeRatio);
26301 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
26303 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
26304 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
26305 for (unsigned i = 0; i != NumElems; ++i)
26306 ShuffleVec[i] = i * SizeRatio;
26308 // Can't shuffle using an illegal type.
26309 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
26310 "WideVecVT should be legal");
26312 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
26313 DAG.getUNDEF(WideVecVT),
26317 SDValue Mask = Mst->getMask();
26318 if (Mask.getValueType() == VT) {
26319 // Mask and original value have the same type
26320 NewMask = DAG.getBitcast(WideVecVT, Mask);
26321 for (unsigned i = 0; i != NumElems; ++i)
26322 ShuffleVec[i] = i * SizeRatio;
26323 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
26324 ShuffleVec[i] = NumElems*SizeRatio;
26325 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
26326 DAG.getConstant(0, dl, WideVecVT),
26330 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
26331 unsigned WidenNumElts = NumElems*SizeRatio;
26332 unsigned MaskNumElts = VT.getVectorNumElements();
26333 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
26336 unsigned NumConcat = WidenNumElts / MaskNumElts;
26337 SmallVector<SDValue, 16> Ops(NumConcat);
26338 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
26340 for (unsigned i = 1; i != NumConcat; ++i)
26343 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
26346 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal,
26347 Mst->getBasePtr(), NewMask, StVT,
26348 Mst->getMemOperand(), false);
26350 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
26351 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
26352 const X86Subtarget *Subtarget) {
26353 StoreSDNode *St = cast<StoreSDNode>(N);
26354 EVT VT = St->getValue().getValueType();
26355 EVT StVT = St->getMemoryVT();
26357 SDValue StoredVal = St->getOperand(1);
26358 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26360 // If we are saving a concatenation of two XMM registers and 32-byte stores
26361 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
26363 unsigned AddressSpace = St->getAddressSpace();
26364 unsigned Alignment = St->getAlignment();
26365 if (VT.is256BitVector() && StVT == VT &&
26366 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
26367 AddressSpace, Alignment, &Fast) && !Fast) {
26368 unsigned NumElems = VT.getVectorNumElements();
26372 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
26373 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
26376 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
26377 SDValue Ptr0 = St->getBasePtr();
26378 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
26380 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
26381 St->getPointerInfo(), St->isVolatile(),
26382 St->isNonTemporal(), Alignment);
26383 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
26384 St->getPointerInfo(), St->isVolatile(),
26385 St->isNonTemporal(),
26386 std::min(16U, Alignment));
26387 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
26390 // Optimize trunc store (of multiple scalars) to shuffle and store.
26391 // First, pack all of the elements in one place. Next, store to memory
26392 // in fewer chunks.
26393 if (St->isTruncatingStore() && VT.isVector()) {
26394 // Check if we can detect an AVG pattern from the truncation. If yes,
26395 // replace the trunc store by a normal store with the result of X86ISD::AVG
26398 detectAVGPattern(St->getValue(), St->getMemoryVT(), DAG, Subtarget, dl);
26400 return DAG.getStore(St->getChain(), dl, Avg, St->getBasePtr(),
26401 St->getPointerInfo(), St->isVolatile(),
26402 St->isNonTemporal(), St->getAlignment());
26404 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26405 unsigned NumElems = VT.getVectorNumElements();
26406 assert(StVT != VT && "Cannot truncate to the same type");
26407 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
26408 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
26410 // The truncating store is legal in some cases. For example
26411 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
26412 // are designated for truncate store.
26413 // In this case we don't need any further transformations.
26414 if (TLI.isTruncStoreLegal(VT, StVT))
26417 // From, To sizes and ElemCount must be pow of two
26418 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
26419 // We are going to use the original vector elt for storing.
26420 // Accumulated smaller vector elements must be a multiple of the store size.
26421 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
26423 unsigned SizeRatio = FromSz / ToSz;
26425 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
26427 // Create a type on which we perform the shuffle
26428 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
26429 StVT.getScalarType(), NumElems*SizeRatio);
26431 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
26433 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
26434 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
26435 for (unsigned i = 0; i != NumElems; ++i)
26436 ShuffleVec[i] = i * SizeRatio;
26438 // Can't shuffle using an illegal type.
26439 if (!TLI.isTypeLegal(WideVecVT))
26442 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
26443 DAG.getUNDEF(WideVecVT),
26445 // At this point all of the data is stored at the bottom of the
26446 // register. We now need to save it to mem.
26448 // Find the largest store unit
26449 MVT StoreType = MVT::i8;
26450 for (MVT Tp : MVT::integer_valuetypes()) {
26451 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
26455 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
26456 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
26457 (64 <= NumElems * ToSz))
26458 StoreType = MVT::f64;
26460 // Bitcast the original vector into a vector of store-size units
26461 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
26462 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
26463 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
26464 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
26465 SmallVector<SDValue, 8> Chains;
26466 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
26467 TLI.getPointerTy(DAG.getDataLayout()));
26468 SDValue Ptr = St->getBasePtr();
26470 // Perform one or more big stores into memory.
26471 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
26472 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
26473 StoreType, ShuffWide,
26474 DAG.getIntPtrConstant(i, dl));
26475 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
26476 St->getPointerInfo(), St->isVolatile(),
26477 St->isNonTemporal(), St->getAlignment());
26478 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
26479 Chains.push_back(Ch);
26482 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
26485 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
26486 // the FP state in cases where an emms may be missing.
26487 // A preferable solution to the general problem is to figure out the right
26488 // places to insert EMMS. This qualifies as a quick hack.
26490 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
26491 if (VT.getSizeInBits() != 64)
26494 const Function *F = DAG.getMachineFunction().getFunction();
26495 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
26497 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
26498 if ((VT.isVector() ||
26499 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
26500 isa<LoadSDNode>(St->getValue()) &&
26501 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
26502 St->getChain().hasOneUse() && !St->isVolatile()) {
26503 SDNode* LdVal = St->getValue().getNode();
26504 LoadSDNode *Ld = nullptr;
26505 int TokenFactorIndex = -1;
26506 SmallVector<SDValue, 8> Ops;
26507 SDNode* ChainVal = St->getChain().getNode();
26508 // Must be a store of a load. We currently handle two cases: the load
26509 // is a direct child, and it's under an intervening TokenFactor. It is
26510 // possible to dig deeper under nested TokenFactors.
26511 if (ChainVal == LdVal)
26512 Ld = cast<LoadSDNode>(St->getChain());
26513 else if (St->getValue().hasOneUse() &&
26514 ChainVal->getOpcode() == ISD::TokenFactor) {
26515 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
26516 if (ChainVal->getOperand(i).getNode() == LdVal) {
26517 TokenFactorIndex = i;
26518 Ld = cast<LoadSDNode>(St->getValue());
26520 Ops.push_back(ChainVal->getOperand(i));
26524 if (!Ld || !ISD::isNormalLoad(Ld))
26527 // If this is not the MMX case, i.e. we are just turning i64 load/store
26528 // into f64 load/store, avoid the transformation if there are multiple
26529 // uses of the loaded value.
26530 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
26535 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
26536 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
26538 if (Subtarget->is64Bit() || F64IsLegal) {
26539 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
26540 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
26541 Ld->getPointerInfo(), Ld->isVolatile(),
26542 Ld->isNonTemporal(), Ld->isInvariant(),
26543 Ld->getAlignment());
26544 SDValue NewChain = NewLd.getValue(1);
26545 if (TokenFactorIndex != -1) {
26546 Ops.push_back(NewChain);
26547 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26549 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
26550 St->getPointerInfo(),
26551 St->isVolatile(), St->isNonTemporal(),
26552 St->getAlignment());
26555 // Otherwise, lower to two pairs of 32-bit loads / stores.
26556 SDValue LoAddr = Ld->getBasePtr();
26557 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
26558 DAG.getConstant(4, LdDL, MVT::i32));
26560 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
26561 Ld->getPointerInfo(),
26562 Ld->isVolatile(), Ld->isNonTemporal(),
26563 Ld->isInvariant(), Ld->getAlignment());
26564 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
26565 Ld->getPointerInfo().getWithOffset(4),
26566 Ld->isVolatile(), Ld->isNonTemporal(),
26568 MinAlign(Ld->getAlignment(), 4));
26570 SDValue NewChain = LoLd.getValue(1);
26571 if (TokenFactorIndex != -1) {
26572 Ops.push_back(LoLd);
26573 Ops.push_back(HiLd);
26574 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26577 LoAddr = St->getBasePtr();
26578 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
26579 DAG.getConstant(4, StDL, MVT::i32));
26581 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
26582 St->getPointerInfo(),
26583 St->isVolatile(), St->isNonTemporal(),
26584 St->getAlignment());
26585 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
26586 St->getPointerInfo().getWithOffset(4),
26588 St->isNonTemporal(),
26589 MinAlign(St->getAlignment(), 4));
26590 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
26593 // This is similar to the above case, but here we handle a scalar 64-bit
26594 // integer store that is extracted from a vector on a 32-bit target.
26595 // If we have SSE2, then we can treat it like a floating-point double
26596 // to get past legalization. The execution dependencies fixup pass will
26597 // choose the optimal machine instruction for the store if this really is
26598 // an integer or v2f32 rather than an f64.
26599 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
26600 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
26601 SDValue OldExtract = St->getOperand(1);
26602 SDValue ExtOp0 = OldExtract.getOperand(0);
26603 unsigned VecSize = ExtOp0.getValueSizeInBits();
26604 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
26605 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
26606 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
26607 BitCast, OldExtract.getOperand(1));
26608 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
26609 St->getPointerInfo(), St->isVolatile(),
26610 St->isNonTemporal(), St->getAlignment());
26616 /// Return 'true' if this vector operation is "horizontal"
26617 /// and return the operands for the horizontal operation in LHS and RHS. A
26618 /// horizontal operation performs the binary operation on successive elements
26619 /// of its first operand, then on successive elements of its second operand,
26620 /// returning the resulting values in a vector. For example, if
26621 /// A = < float a0, float a1, float a2, float a3 >
26623 /// B = < float b0, float b1, float b2, float b3 >
26624 /// then the result of doing a horizontal operation on A and B is
26625 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
26626 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
26627 /// A horizontal-op B, for some already available A and B, and if so then LHS is
26628 /// set to A, RHS to B, and the routine returns 'true'.
26629 /// Note that the binary operation should have the property that if one of the
26630 /// operands is UNDEF then the result is UNDEF.
26631 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
26632 // Look for the following pattern: if
26633 // A = < float a0, float a1, float a2, float a3 >
26634 // B = < float b0, float b1, float b2, float b3 >
26636 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
26637 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
26638 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
26639 // which is A horizontal-op B.
26641 // At least one of the operands should be a vector shuffle.
26642 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
26643 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
26646 MVT VT = LHS.getSimpleValueType();
26648 assert((VT.is128BitVector() || VT.is256BitVector()) &&
26649 "Unsupported vector type for horizontal add/sub");
26651 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
26652 // operate independently on 128-bit lanes.
26653 unsigned NumElts = VT.getVectorNumElements();
26654 unsigned NumLanes = VT.getSizeInBits()/128;
26655 unsigned NumLaneElts = NumElts / NumLanes;
26656 assert((NumLaneElts % 2 == 0) &&
26657 "Vector type should have an even number of elements in each lane");
26658 unsigned HalfLaneElts = NumLaneElts/2;
26660 // View LHS in the form
26661 // LHS = VECTOR_SHUFFLE A, B, LMask
26662 // If LHS is not a shuffle then pretend it is the shuffle
26663 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
26664 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
26667 SmallVector<int, 16> LMask(NumElts);
26668 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26669 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
26670 A = LHS.getOperand(0);
26671 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
26672 B = LHS.getOperand(1);
26673 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
26674 std::copy(Mask.begin(), Mask.end(), LMask.begin());
26676 if (LHS.getOpcode() != ISD::UNDEF)
26678 for (unsigned i = 0; i != NumElts; ++i)
26682 // Likewise, view RHS in the form
26683 // RHS = VECTOR_SHUFFLE C, D, RMask
26685 SmallVector<int, 16> RMask(NumElts);
26686 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26687 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
26688 C = RHS.getOperand(0);
26689 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
26690 D = RHS.getOperand(1);
26691 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
26692 std::copy(Mask.begin(), Mask.end(), RMask.begin());
26694 if (RHS.getOpcode() != ISD::UNDEF)
26696 for (unsigned i = 0; i != NumElts; ++i)
26700 // Check that the shuffles are both shuffling the same vectors.
26701 if (!(A == C && B == D) && !(A == D && B == C))
26704 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
26705 if (!A.getNode() && !B.getNode())
26708 // If A and B occur in reverse order in RHS, then "swap" them (which means
26709 // rewriting the mask).
26711 ShuffleVectorSDNode::commuteMask(RMask);
26713 // At this point LHS and RHS are equivalent to
26714 // LHS = VECTOR_SHUFFLE A, B, LMask
26715 // RHS = VECTOR_SHUFFLE A, B, RMask
26716 // Check that the masks correspond to performing a horizontal operation.
26717 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
26718 for (unsigned i = 0; i != NumLaneElts; ++i) {
26719 int LIdx = LMask[i+l], RIdx = RMask[i+l];
26721 // Ignore any UNDEF components.
26722 if (LIdx < 0 || RIdx < 0 ||
26723 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
26724 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
26727 // Check that successive elements are being operated on. If not, this is
26728 // not a horizontal operation.
26729 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
26730 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
26731 if (!(LIdx == Index && RIdx == Index + 1) &&
26732 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
26737 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
26738 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
26742 /// Do target-specific dag combines on floating point adds.
26743 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
26744 const X86Subtarget *Subtarget) {
26745 EVT VT = N->getValueType(0);
26746 SDValue LHS = N->getOperand(0);
26747 SDValue RHS = N->getOperand(1);
26749 // Try to synthesize horizontal adds from adds of shuffles.
26750 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26751 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26752 isHorizontalBinOp(LHS, RHS, true))
26753 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
26757 /// Do target-specific dag combines on floating point subs.
26758 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
26759 const X86Subtarget *Subtarget) {
26760 EVT VT = N->getValueType(0);
26761 SDValue LHS = N->getOperand(0);
26762 SDValue RHS = N->getOperand(1);
26764 // Try to synthesize horizontal subs from subs of shuffles.
26765 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26766 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26767 isHorizontalBinOp(LHS, RHS, false))
26768 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
26772 /// Truncate a group of v4i32 into v16i8/v8i16 using X86ISD::PACKUS.
26774 combineVectorTruncationWithPACKUS(SDNode *N, SelectionDAG &DAG,
26775 SmallVector<SDValue, 8> &Regs) {
26776 assert(Regs.size() > 0 && (Regs[0].getValueType() == MVT::v4i32 ||
26777 Regs[0].getValueType() == MVT::v2i64));
26778 EVT OutVT = N->getValueType(0);
26779 EVT OutSVT = OutVT.getVectorElementType();
26780 EVT InVT = Regs[0].getValueType();
26781 EVT InSVT = InVT.getVectorElementType();
26784 // First, use mask to unset all bits that won't appear in the result.
26785 assert((OutSVT == MVT::i8 || OutSVT == MVT::i16) &&
26786 "OutSVT can only be either i8 or i16.");
26788 DAG.getConstant(OutSVT == MVT::i8 ? 0xFF : 0xFFFF, DL, InSVT);
26789 SDValue MaskVec = DAG.getNode(
26790 ISD::BUILD_VECTOR, DL, InVT,
26791 SmallVector<SDValue, 8>(InVT.getVectorNumElements(), MaskVal));
26792 for (auto &Reg : Regs)
26793 Reg = DAG.getNode(ISD::AND, DL, InVT, MaskVec, Reg);
26795 MVT UnpackedVT, PackedVT;
26796 if (OutSVT == MVT::i8) {
26797 UnpackedVT = MVT::v8i16;
26798 PackedVT = MVT::v16i8;
26800 UnpackedVT = MVT::v4i32;
26801 PackedVT = MVT::v8i16;
26804 // In each iteration, truncate the type by a half size.
26805 auto RegNum = Regs.size();
26806 for (unsigned j = 1, e = InSVT.getSizeInBits() / OutSVT.getSizeInBits();
26807 j < e; j *= 2, RegNum /= 2) {
26808 for (unsigned i = 0; i < RegNum; i++)
26809 Regs[i] = DAG.getNode(ISD::BITCAST, DL, UnpackedVT, Regs[i]);
26810 for (unsigned i = 0; i < RegNum / 2; i++)
26811 Regs[i] = DAG.getNode(X86ISD::PACKUS, DL, PackedVT, Regs[i * 2],
26815 // If the type of the result is v8i8, we need do one more X86ISD::PACKUS, and
26816 // then extract a subvector as the result since v8i8 is not a legal type.
26817 if (OutVT == MVT::v8i8) {
26818 Regs[0] = DAG.getNode(X86ISD::PACKUS, DL, PackedVT, Regs[0], Regs[0]);
26819 Regs[0] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, Regs[0],
26820 DAG.getIntPtrConstant(0, DL));
26822 } else if (RegNum > 1) {
26823 Regs.resize(RegNum);
26824 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Regs);
26829 /// Truncate a group of v4i32 into v8i16 using X86ISD::PACKSS.
26831 combineVectorTruncationWithPACKSS(SDNode *N, SelectionDAG &DAG,
26832 SmallVector<SDValue, 8> &Regs) {
26833 assert(Regs.size() > 0 && Regs[0].getValueType() == MVT::v4i32);
26834 EVT OutVT = N->getValueType(0);
26837 // Shift left by 16 bits, then arithmetic-shift right by 16 bits.
26838 SDValue ShAmt = DAG.getConstant(16, DL, MVT::i32);
26839 for (auto &Reg : Regs) {
26840 Reg = getTargetVShiftNode(X86ISD::VSHLI, DL, MVT::v4i32, Reg, ShAmt, DAG);
26841 Reg = getTargetVShiftNode(X86ISD::VSRAI, DL, MVT::v4i32, Reg, ShAmt, DAG);
26844 for (unsigned i = 0, e = Regs.size() / 2; i < e; i++)
26845 Regs[i] = DAG.getNode(X86ISD::PACKSS, DL, MVT::v8i16, Regs[i * 2],
26848 if (Regs.size() > 2) {
26849 Regs.resize(Regs.size() / 2);
26850 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Regs);
26855 /// This function transforms truncation from vXi32/vXi64 to vXi8/vXi16 into
26856 /// X86ISD::PACKUS/X86ISD::PACKSS operations. We do it here because after type
26857 /// legalization the truncation will be translated into a BUILD_VECTOR with each
26858 /// element that is extracted from a vector and then truncated, and it is
26859 /// diffcult to do this optimization based on them.
26860 static SDValue combineVectorTruncation(SDNode *N, SelectionDAG &DAG,
26861 const X86Subtarget *Subtarget) {
26862 EVT OutVT = N->getValueType(0);
26863 if (!OutVT.isVector())
26866 SDValue In = N->getOperand(0);
26867 if (!In.getValueType().isSimple())
26870 EVT InVT = In.getValueType();
26871 unsigned NumElems = OutVT.getVectorNumElements();
26873 // TODO: On AVX2, the behavior of X86ISD::PACKUS is different from that on
26874 // SSE2, and we need to take care of it specially.
26875 // AVX512 provides vpmovdb.
26876 if (!Subtarget->hasSSE2() || Subtarget->hasAVX2())
26879 EVT OutSVT = OutVT.getVectorElementType();
26880 EVT InSVT = InVT.getVectorElementType();
26881 if (!((InSVT == MVT::i32 || InSVT == MVT::i64) &&
26882 (OutSVT == MVT::i8 || OutSVT == MVT::i16) && isPowerOf2_32(NumElems) &&
26886 // SSSE3's pshufb results in less instructions in the cases below.
26887 if (Subtarget->hasSSSE3() && NumElems == 8 &&
26888 ((OutSVT == MVT::i8 && InSVT != MVT::i64) ||
26889 (InSVT == MVT::i32 && OutSVT == MVT::i16)))
26894 // Split a long vector into vectors of legal type.
26895 unsigned RegNum = InVT.getSizeInBits() / 128;
26896 SmallVector<SDValue, 8> SubVec(RegNum);
26897 if (InSVT == MVT::i32) {
26898 for (unsigned i = 0; i < RegNum; i++)
26899 SubVec[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
26900 DAG.getIntPtrConstant(i * 4, DL));
26902 for (unsigned i = 0; i < RegNum; i++)
26903 SubVec[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
26904 DAG.getIntPtrConstant(i * 2, DL));
26907 // SSE2 provides PACKUS for only 2 x v8i16 -> v16i8 and SSE4.1 provides PAKCUS
26908 // for 2 x v4i32 -> v8i16. For SSSE3 and below, we need to use PACKSS to
26909 // truncate 2 x v4i32 to v8i16.
26910 if (Subtarget->hasSSE41() || OutSVT == MVT::i8)
26911 return combineVectorTruncationWithPACKUS(N, DAG, SubVec);
26912 else if (InSVT == MVT::i32)
26913 return combineVectorTruncationWithPACKSS(N, DAG, SubVec);
26918 static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
26919 const X86Subtarget *Subtarget) {
26920 // Try to detect AVG pattern first.
26921 SDValue Avg = detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG,
26922 Subtarget, SDLoc(N));
26926 return combineVectorTruncation(N, DAG, Subtarget);
26929 /// Do target-specific dag combines on floating point negations.
26930 static SDValue PerformFNEGCombine(SDNode *N, SelectionDAG &DAG,
26931 const X86Subtarget *Subtarget) {
26932 EVT VT = N->getValueType(0);
26933 EVT SVT = VT.getScalarType();
26934 SDValue Arg = N->getOperand(0);
26937 // Let legalize expand this if it isn't a legal type yet.
26938 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26941 // If we're negating a FMUL node on a target with FMA, then we can avoid the
26942 // use of a constant by performing (-0 - A*B) instead.
26943 // FIXME: Check rounding control flags as well once it becomes available.
26944 if (Arg.getOpcode() == ISD::FMUL && (SVT == MVT::f32 || SVT == MVT::f64) &&
26945 Arg->getFlags()->hasNoSignedZeros() && Subtarget->hasAnyFMA()) {
26946 SDValue Zero = DAG.getConstantFP(0.0, DL, VT);
26947 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26948 Arg.getOperand(1), Zero);
26951 // If we're negating a FMA node, then we can adjust the
26952 // instruction to include the extra negation.
26953 if (Arg.hasOneUse()) {
26954 switch (Arg.getOpcode()) {
26955 case X86ISD::FMADD:
26956 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26957 Arg.getOperand(1), Arg.getOperand(2));
26958 case X86ISD::FMSUB:
26959 return DAG.getNode(X86ISD::FNMADD, DL, VT, Arg.getOperand(0),
26960 Arg.getOperand(1), Arg.getOperand(2));
26961 case X86ISD::FNMADD:
26962 return DAG.getNode(X86ISD::FMSUB, DL, VT, Arg.getOperand(0),
26963 Arg.getOperand(1), Arg.getOperand(2));
26964 case X86ISD::FNMSUB:
26965 return DAG.getNode(X86ISD::FMADD, DL, VT, Arg.getOperand(0),
26966 Arg.getOperand(1), Arg.getOperand(2));
26972 static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
26973 const X86Subtarget *Subtarget) {
26974 EVT VT = N->getValueType(0);
26975 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
26976 // VXORPS, VORPS, VANDPS, VANDNPS are supported only under DQ extention.
26977 // These logic operations may be executed in the integer domain.
26979 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
26980 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
26982 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
26983 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
26984 unsigned IntOpcode = 0;
26985 switch (N->getOpcode()) {
26986 default: llvm_unreachable("Unexpected FP logic op");
26987 case X86ISD::FOR: IntOpcode = ISD::OR; break;
26988 case X86ISD::FXOR: IntOpcode = ISD::XOR; break;
26989 case X86ISD::FAND: IntOpcode = ISD::AND; break;
26990 case X86ISD::FANDN: IntOpcode = X86ISD::ANDNP; break;
26992 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
26993 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
26997 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
26998 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
26999 const X86Subtarget *Subtarget) {
27000 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
27002 // F[X]OR(0.0, x) -> x
27003 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
27004 if (C->getValueAPF().isPosZero())
27005 return N->getOperand(1);
27007 // F[X]OR(x, 0.0) -> x
27008 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
27009 if (C->getValueAPF().isPosZero())
27010 return N->getOperand(0);
27012 return lowerX86FPLogicOp(N, DAG, Subtarget);
27015 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
27016 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
27017 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
27019 // Only perform optimizations if UnsafeMath is used.
27020 if (!DAG.getTarget().Options.UnsafeFPMath)
27023 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
27024 // into FMINC and FMAXC, which are Commutative operations.
27025 unsigned NewOp = 0;
27026 switch (N->getOpcode()) {
27027 default: llvm_unreachable("unknown opcode");
27028 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
27029 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
27032 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
27033 N->getOperand(0), N->getOperand(1));
27036 static SDValue performFMinNumFMaxNumCombine(SDNode *N, SelectionDAG &DAG,
27037 const X86Subtarget *Subtarget) {
27038 if (Subtarget->useSoftFloat())
27041 // TODO: Check for global or instruction-level "nnan". In that case, we
27042 // should be able to lower to FMAX/FMIN alone.
27043 // TODO: If an operand is already known to be a NaN or not a NaN, this
27044 // should be an optional swap and FMAX/FMIN.
27046 EVT VT = N->getValueType(0);
27047 if (!((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
27048 (Subtarget->hasSSE2() && (VT == MVT::f64 || VT == MVT::v2f64)) ||
27049 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))))
27052 // This takes at least 3 instructions, so favor a library call when operating
27053 // on a scalar and minimizing code size.
27054 if (!VT.isVector() && DAG.getMachineFunction().getFunction()->optForMinSize())
27057 SDValue Op0 = N->getOperand(0);
27058 SDValue Op1 = N->getOperand(1);
27060 EVT SetCCType = DAG.getTargetLoweringInfo().getSetCCResultType(
27061 DAG.getDataLayout(), *DAG.getContext(), VT);
27063 // There are 4 possibilities involving NaN inputs, and these are the required
27067 // ----------------
27068 // Num | Max | Op0 |
27069 // Op0 ----------------
27070 // NaN | Op1 | NaN |
27071 // ----------------
27073 // The SSE FP max/min instructions were not designed for this case, but rather
27075 // Min = Op1 < Op0 ? Op1 : Op0
27076 // Max = Op1 > Op0 ? Op1 : Op0
27078 // So they always return Op0 if either input is a NaN. However, we can still
27079 // use those instructions for fmaxnum by selecting away a NaN input.
27081 // If either operand is NaN, the 2nd source operand (Op0) is passed through.
27082 auto MinMaxOp = N->getOpcode() == ISD::FMAXNUM ? X86ISD::FMAX : X86ISD::FMIN;
27083 SDValue MinOrMax = DAG.getNode(MinMaxOp, DL, VT, Op1, Op0);
27084 SDValue IsOp0Nan = DAG.getSetCC(DL, SetCCType , Op0, Op0, ISD::SETUO);
27086 // If Op0 is a NaN, select Op1. Otherwise, select the max. If both operands
27087 // are NaN, the NaN value of Op1 is the result.
27088 auto SelectOpcode = VT.isVector() ? ISD::VSELECT : ISD::SELECT;
27089 return DAG.getNode(SelectOpcode, DL, VT, IsOp0Nan, Op1, MinOrMax);
27092 /// Do target-specific dag combines on X86ISD::FAND nodes.
27093 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG,
27094 const X86Subtarget *Subtarget) {
27095 // FAND(0.0, x) -> 0.0
27096 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
27097 if (C->getValueAPF().isPosZero())
27098 return N->getOperand(0);
27100 // FAND(x, 0.0) -> 0.0
27101 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
27102 if (C->getValueAPF().isPosZero())
27103 return N->getOperand(1);
27105 return lowerX86FPLogicOp(N, DAG, Subtarget);
27108 /// Do target-specific dag combines on X86ISD::FANDN nodes
27109 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG,
27110 const X86Subtarget *Subtarget) {
27111 // FANDN(0.0, x) -> x
27112 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
27113 if (C->getValueAPF().isPosZero())
27114 return N->getOperand(1);
27116 // FANDN(x, 0.0) -> 0.0
27117 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
27118 if (C->getValueAPF().isPosZero())
27119 return N->getOperand(1);
27121 return lowerX86FPLogicOp(N, DAG, Subtarget);
27124 static SDValue PerformBTCombine(SDNode *N,
27126 TargetLowering::DAGCombinerInfo &DCI) {
27127 // BT ignores high bits in the bit index operand.
27128 SDValue Op1 = N->getOperand(1);
27129 if (Op1.hasOneUse()) {
27130 unsigned BitWidth = Op1.getValueSizeInBits();
27131 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
27132 APInt KnownZero, KnownOne;
27133 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
27134 !DCI.isBeforeLegalizeOps());
27135 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
27136 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
27137 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
27138 DCI.CommitTargetLoweringOpt(TLO);
27143 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
27144 SDValue Op = N->getOperand(0);
27145 if (Op.getOpcode() == ISD::BITCAST)
27146 Op = Op.getOperand(0);
27147 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
27148 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
27149 VT.getVectorElementType().getSizeInBits() ==
27150 OpVT.getVectorElementType().getSizeInBits()) {
27151 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
27156 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
27157 const X86Subtarget *Subtarget) {
27158 EVT VT = N->getValueType(0);
27159 if (!VT.isVector())
27162 SDValue N0 = N->getOperand(0);
27163 SDValue N1 = N->getOperand(1);
27164 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
27167 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
27168 // both SSE and AVX2 since there is no sign-extended shift right
27169 // operation on a vector with 64-bit elements.
27170 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
27171 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
27172 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
27173 N0.getOpcode() == ISD::SIGN_EXTEND)) {
27174 SDValue N00 = N0.getOperand(0);
27176 // EXTLOAD has a better solution on AVX2,
27177 // it may be replaced with X86ISD::VSEXT node.
27178 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
27179 if (!ISD::isNormalLoad(N00.getNode()))
27182 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
27183 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
27185 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
27191 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
27192 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
27193 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
27194 /// eliminate extend, add, and shift instructions.
27195 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
27196 const X86Subtarget *Subtarget) {
27197 // TODO: This should be valid for other integer types.
27198 EVT VT = Sext->getValueType(0);
27199 if (VT != MVT::i64)
27202 // We need an 'add nsw' feeding into the 'sext'.
27203 SDValue Add = Sext->getOperand(0);
27204 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
27207 // Having a constant operand to the 'add' ensures that we are not increasing
27208 // the instruction count because the constant is extended for free below.
27209 // A constant operand can also become the displacement field of an LEA.
27210 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
27214 // Don't make the 'add' bigger if there's no hope of combining it with some
27215 // other 'add' or 'shl' instruction.
27216 // TODO: It may be profitable to generate simpler LEA instructions in place
27217 // of single 'add' instructions, but the cost model for selecting an LEA
27218 // currently has a high threshold.
27219 bool HasLEAPotential = false;
27220 for (auto *User : Sext->uses()) {
27221 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
27222 HasLEAPotential = true;
27226 if (!HasLEAPotential)
27229 // Everything looks good, so pull the 'sext' ahead of the 'add'.
27230 int64_t AddConstant = AddOp1->getSExtValue();
27231 SDValue AddOp0 = Add.getOperand(0);
27232 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
27233 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
27235 // The wider add is guaranteed to not wrap because both operands are
27238 Flags.setNoSignedWrap(true);
27239 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
27242 /// (i8,i32 {s/z}ext ({s/u}divrem (i8 x, i8 y)) ->
27243 /// (i8,i32 ({s/u}divrem_sext_hreg (i8 x, i8 y)
27244 /// This exposes the {s/z}ext to the sdivrem lowering, so that it directly
27245 /// extends from AH (which we otherwise need to do contortions to access).
27246 static SDValue getDivRem8(SDNode *N, SelectionDAG &DAG) {
27247 SDValue N0 = N->getOperand(0);
27248 auto OpcodeN = N->getOpcode();
27249 auto OpcodeN0 = N0.getOpcode();
27250 if (!((OpcodeN == ISD::SIGN_EXTEND && OpcodeN0 == ISD::SDIVREM) ||
27251 (OpcodeN == ISD::ZERO_EXTEND && OpcodeN0 == ISD::UDIVREM)))
27254 EVT VT = N->getValueType(0);
27255 EVT InVT = N0.getValueType();
27256 if (N0.getResNo() != 1 || InVT != MVT::i8 || VT != MVT::i32)
27259 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
27260 auto DivRemOpcode = OpcodeN0 == ISD::SDIVREM ? X86ISD::SDIVREM8_SEXT_HREG
27261 : X86ISD::UDIVREM8_ZEXT_HREG;
27262 SDValue R = DAG.getNode(DivRemOpcode, SDLoc(N), NodeTys, N0.getOperand(0),
27264 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
27265 return R.getValue(1);
27268 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
27269 TargetLowering::DAGCombinerInfo &DCI,
27270 const X86Subtarget *Subtarget) {
27271 SDValue N0 = N->getOperand(0);
27272 EVT VT = N->getValueType(0);
27273 EVT SVT = VT.getScalarType();
27274 EVT InVT = N0.getValueType();
27275 EVT InSVT = InVT.getScalarType();
27278 if (SDValue DivRem8 = getDivRem8(N, DAG))
27281 if (!DCI.isBeforeLegalizeOps()) {
27282 if (InVT == MVT::i1) {
27283 SDValue Zero = DAG.getConstant(0, DL, VT);
27285 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
27286 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
27291 if (VT.isVector() && Subtarget->hasSSE2()) {
27292 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
27293 EVT InVT = N.getValueType();
27294 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
27295 Size / InVT.getScalarSizeInBits());
27296 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
27297 DAG.getUNDEF(InVT));
27299 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
27302 // If target-size is less than 128-bits, extend to a type that would extend
27303 // to 128 bits, extend that and extract the original target vector.
27304 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
27305 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
27306 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
27307 unsigned Scale = 128 / VT.getSizeInBits();
27309 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
27310 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
27311 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
27312 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
27313 DAG.getIntPtrConstant(0, DL));
27316 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
27317 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
27318 if (VT.getSizeInBits() == 128 &&
27319 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
27320 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
27321 SDValue ExOp = ExtendVecSize(DL, N0, 128);
27322 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
27325 // On pre-AVX2 targets, split into 128-bit nodes of
27326 // ISD::SIGN_EXTEND_VECTOR_INREG.
27327 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
27328 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
27329 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
27330 unsigned NumVecs = VT.getSizeInBits() / 128;
27331 unsigned NumSubElts = 128 / SVT.getSizeInBits();
27332 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
27333 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
27335 SmallVector<SDValue, 8> Opnds;
27336 for (unsigned i = 0, Offset = 0; i != NumVecs;
27337 ++i, Offset += NumSubElts) {
27338 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
27339 DAG.getIntPtrConstant(Offset, DL));
27340 SrcVec = ExtendVecSize(DL, SrcVec, 128);
27341 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
27342 Opnds.push_back(SrcVec);
27344 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
27348 if (Subtarget->hasAVX() && VT.is256BitVector())
27349 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
27352 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
27358 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
27359 const X86Subtarget* Subtarget) {
27361 EVT VT = N->getValueType(0);
27363 // Let legalize expand this if it isn't a legal type yet.
27364 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
27367 EVT ScalarVT = VT.getScalarType();
27368 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget->hasAnyFMA())
27371 SDValue A = N->getOperand(0);
27372 SDValue B = N->getOperand(1);
27373 SDValue C = N->getOperand(2);
27375 bool NegA = (A.getOpcode() == ISD::FNEG);
27376 bool NegB = (B.getOpcode() == ISD::FNEG);
27377 bool NegC = (C.getOpcode() == ISD::FNEG);
27379 // Negative multiplication when NegA xor NegB
27380 bool NegMul = (NegA != NegB);
27382 A = A.getOperand(0);
27384 B = B.getOperand(0);
27386 C = C.getOperand(0);
27390 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
27392 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
27394 return DAG.getNode(Opcode, dl, VT, A, B, C);
27397 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
27398 TargetLowering::DAGCombinerInfo &DCI,
27399 const X86Subtarget *Subtarget) {
27400 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
27401 // (and (i32 x86isd::setcc_carry), 1)
27402 // This eliminates the zext. This transformation is necessary because
27403 // ISD::SETCC is always legalized to i8.
27405 SDValue N0 = N->getOperand(0);
27406 EVT VT = N->getValueType(0);
27408 if (N0.getOpcode() == ISD::AND &&
27410 N0.getOperand(0).hasOneUse()) {
27411 SDValue N00 = N0.getOperand(0);
27412 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
27413 if (!isOneConstant(N0.getOperand(1)))
27415 return DAG.getNode(ISD::AND, dl, VT,
27416 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
27417 N00.getOperand(0), N00.getOperand(1)),
27418 DAG.getConstant(1, dl, VT));
27422 if (N0.getOpcode() == ISD::TRUNCATE &&
27424 N0.getOperand(0).hasOneUse()) {
27425 SDValue N00 = N0.getOperand(0);
27426 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
27427 return DAG.getNode(ISD::AND, dl, VT,
27428 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
27429 N00.getOperand(0), N00.getOperand(1)),
27430 DAG.getConstant(1, dl, VT));
27434 if (VT.is256BitVector())
27435 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
27438 if (SDValue DivRem8 = getDivRem8(N, DAG))
27444 // Optimize x == -y --> x+y == 0
27445 // x != -y --> x+y != 0
27446 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
27447 const X86Subtarget* Subtarget) {
27448 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
27449 SDValue LHS = N->getOperand(0);
27450 SDValue RHS = N->getOperand(1);
27451 EVT VT = N->getValueType(0);
27454 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
27455 if (isNullConstant(LHS.getOperand(0)) && LHS.hasOneUse()) {
27456 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
27457 LHS.getOperand(1));
27458 return DAG.getSetCC(DL, N->getValueType(0), addV,
27459 DAG.getConstant(0, DL, addV.getValueType()), CC);
27461 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
27462 if (isNullConstant(RHS.getOperand(0)) && RHS.hasOneUse()) {
27463 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
27464 RHS.getOperand(1));
27465 return DAG.getSetCC(DL, N->getValueType(0), addV,
27466 DAG.getConstant(0, DL, addV.getValueType()), CC);
27469 if (VT.getScalarType() == MVT::i1 &&
27470 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
27472 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
27473 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
27474 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
27476 if (!IsSEXT0 || !IsVZero1) {
27477 // Swap the operands and update the condition code.
27478 std::swap(LHS, RHS);
27479 CC = ISD::getSetCCSwappedOperands(CC);
27481 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
27482 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
27483 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
27486 if (IsSEXT0 && IsVZero1) {
27487 assert(VT == LHS.getOperand(0).getValueType() &&
27488 "Uexpected operand type");
27489 if (CC == ISD::SETGT)
27490 return DAG.getConstant(0, DL, VT);
27491 if (CC == ISD::SETLE)
27492 return DAG.getConstant(1, DL, VT);
27493 if (CC == ISD::SETEQ || CC == ISD::SETGE)
27494 return DAG.getNOT(DL, LHS.getOperand(0), VT);
27496 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
27497 "Unexpected condition code!");
27498 return LHS.getOperand(0);
27505 static SDValue PerformGatherScatterCombine(SDNode *N, SelectionDAG &DAG) {
27507 // Gather and Scatter instructions use k-registers for masks. The type of
27508 // the masks is v*i1. So the mask will be truncated anyway.
27509 // The SIGN_EXTEND_INREG my be dropped.
27510 SDValue Mask = N->getOperand(2);
27511 if (Mask.getOpcode() == ISD::SIGN_EXTEND_INREG) {
27512 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
27513 NewOps[2] = Mask.getOperand(0);
27514 DAG.UpdateNodeOperands(N, NewOps);
27519 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
27520 // as "sbb reg,reg", since it can be extended without zext and produces
27521 // an all-ones bit which is more useful than 0/1 in some cases.
27522 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
27525 return DAG.getNode(ISD::AND, DL, VT,
27526 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
27527 DAG.getConstant(X86::COND_B, DL, MVT::i8),
27529 DAG.getConstant(1, DL, VT));
27530 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
27531 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
27532 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
27533 DAG.getConstant(X86::COND_B, DL, MVT::i8),
27537 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
27538 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
27539 TargetLowering::DAGCombinerInfo &DCI,
27540 const X86Subtarget *Subtarget) {
27542 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
27543 SDValue EFLAGS = N->getOperand(1);
27545 if (CC == X86::COND_A) {
27546 // Try to convert COND_A into COND_B in an attempt to facilitate
27547 // materializing "setb reg".
27549 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
27550 // cannot take an immediate as its first operand.
27552 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
27553 EFLAGS.getValueType().isInteger() &&
27554 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
27555 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
27556 EFLAGS.getNode()->getVTList(),
27557 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
27558 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
27559 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
27563 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
27564 // a zext and produces an all-ones bit which is more useful than 0/1 in some
27566 if (CC == X86::COND_B)
27567 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
27569 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
27570 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
27571 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
27577 // Optimize branch condition evaluation.
27579 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
27580 TargetLowering::DAGCombinerInfo &DCI,
27581 const X86Subtarget *Subtarget) {
27583 SDValue Chain = N->getOperand(0);
27584 SDValue Dest = N->getOperand(1);
27585 SDValue EFLAGS = N->getOperand(3);
27586 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
27588 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
27589 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
27590 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
27597 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
27598 SelectionDAG &DAG) {
27599 // Take advantage of vector comparisons producing 0 or -1 in each lane to
27600 // optimize away operation when it's from a constant.
27602 // The general transformation is:
27603 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
27604 // AND(VECTOR_CMP(x,y), constant2)
27605 // constant2 = UNARYOP(constant)
27607 // Early exit if this isn't a vector operation, the operand of the
27608 // unary operation isn't a bitwise AND, or if the sizes of the operations
27609 // aren't the same.
27610 EVT VT = N->getValueType(0);
27611 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
27612 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
27613 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
27616 // Now check that the other operand of the AND is a constant. We could
27617 // make the transformation for non-constant splats as well, but it's unclear
27618 // that would be a benefit as it would not eliminate any operations, just
27619 // perform one more step in scalar code before moving to the vector unit.
27620 if (BuildVectorSDNode *BV =
27621 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
27622 // Bail out if the vector isn't a constant.
27623 if (!BV->isConstant())
27626 // Everything checks out. Build up the new and improved node.
27628 EVT IntVT = BV->getValueType(0);
27629 // Create a new constant of the appropriate type for the transformed
27631 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
27632 // The AND node needs bitcasts to/from an integer vector type around it.
27633 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
27634 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
27635 N->getOperand(0)->getOperand(0), MaskConst);
27636 SDValue Res = DAG.getBitcast(VT, NewAnd);
27643 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
27644 const X86Subtarget *Subtarget) {
27645 SDValue Op0 = N->getOperand(0);
27646 EVT VT = N->getValueType(0);
27647 EVT InVT = Op0.getValueType();
27648 EVT InSVT = InVT.getScalarType();
27649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
27651 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
27652 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
27653 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
27655 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
27656 InVT.getVectorNumElements());
27657 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
27659 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
27660 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
27662 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
27668 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
27669 const X86Subtarget *Subtarget) {
27670 // First try to optimize away the conversion entirely when it's
27671 // conditionally from a constant. Vectors only.
27672 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
27675 // Now move on to more general possibilities.
27676 SDValue Op0 = N->getOperand(0);
27677 EVT VT = N->getValueType(0);
27678 EVT InVT = Op0.getValueType();
27679 EVT InSVT = InVT.getScalarType();
27681 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
27682 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
27683 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
27685 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
27686 InVT.getVectorNumElements());
27687 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
27688 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
27691 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
27692 // a 32-bit target where SSE doesn't support i64->FP operations.
27693 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
27694 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
27695 EVT LdVT = Ld->getValueType(0);
27697 // This transformation is not supported if the result type is f16
27698 if (VT == MVT::f16)
27701 if (!Ld->isVolatile() && !VT.isVector() &&
27702 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
27703 !Subtarget->is64Bit() && LdVT == MVT::i64) {
27704 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
27705 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
27706 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
27713 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
27714 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
27715 X86TargetLowering::DAGCombinerInfo &DCI) {
27716 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
27717 // the result is either zero or one (depending on the input carry bit).
27718 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
27719 if (X86::isZeroNode(N->getOperand(0)) &&
27720 X86::isZeroNode(N->getOperand(1)) &&
27721 // We don't have a good way to replace an EFLAGS use, so only do this when
27723 SDValue(N, 1).use_empty()) {
27725 EVT VT = N->getValueType(0);
27726 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
27727 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
27728 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
27729 DAG.getConstant(X86::COND_B, DL,
27732 DAG.getConstant(1, DL, VT));
27733 return DCI.CombineTo(N, Res1, CarryOut);
27739 // fold (add Y, (sete X, 0)) -> adc 0, Y
27740 // (add Y, (setne X, 0)) -> sbb -1, Y
27741 // (sub (sete X, 0), Y) -> sbb 0, Y
27742 // (sub (setne X, 0), Y) -> adc -1, Y
27743 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
27746 // Look through ZExts.
27747 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
27748 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
27751 SDValue SetCC = Ext.getOperand(0);
27752 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
27755 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
27756 if (CC != X86::COND_E && CC != X86::COND_NE)
27759 SDValue Cmp = SetCC.getOperand(1);
27760 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
27761 !X86::isZeroNode(Cmp.getOperand(1)) ||
27762 !Cmp.getOperand(0).getValueType().isInteger())
27765 SDValue CmpOp0 = Cmp.getOperand(0);
27766 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
27767 DAG.getConstant(1, DL, CmpOp0.getValueType()));
27769 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
27770 if (CC == X86::COND_NE)
27771 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
27772 DL, OtherVal.getValueType(), OtherVal,
27773 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
27775 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
27776 DL, OtherVal.getValueType(), OtherVal,
27777 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
27780 /// PerformADDCombine - Do target-specific dag combines on integer adds.
27781 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
27782 const X86Subtarget *Subtarget) {
27783 EVT VT = N->getValueType(0);
27784 SDValue Op0 = N->getOperand(0);
27785 SDValue Op1 = N->getOperand(1);
27787 // Try to synthesize horizontal adds from adds of shuffles.
27788 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27789 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27790 isHorizontalBinOp(Op0, Op1, true))
27791 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
27793 return OptimizeConditionalInDecrement(N, DAG);
27796 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
27797 const X86Subtarget *Subtarget) {
27798 SDValue Op0 = N->getOperand(0);
27799 SDValue Op1 = N->getOperand(1);
27801 // X86 can't encode an immediate LHS of a sub. See if we can push the
27802 // negation into a preceding instruction.
27803 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
27804 // If the RHS of the sub is a XOR with one use and a constant, invert the
27805 // immediate. Then add one to the LHS of the sub so we can turn
27806 // X-Y -> X+~Y+1, saving one register.
27807 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
27808 isa<ConstantSDNode>(Op1.getOperand(1))) {
27809 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
27810 EVT VT = Op0.getValueType();
27811 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
27813 DAG.getConstant(~XorC, SDLoc(Op1), VT));
27814 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
27815 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
27819 // Try to synthesize horizontal adds from adds of shuffles.
27820 EVT VT = N->getValueType(0);
27821 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27822 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27823 isHorizontalBinOp(Op0, Op1, true))
27824 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
27826 return OptimizeConditionalInDecrement(N, DAG);
27829 /// performVZEXTCombine - Performs build vector combines
27830 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
27831 TargetLowering::DAGCombinerInfo &DCI,
27832 const X86Subtarget *Subtarget) {
27834 MVT VT = N->getSimpleValueType(0);
27835 SDValue Op = N->getOperand(0);
27836 MVT OpVT = Op.getSimpleValueType();
27837 MVT OpEltVT = OpVT.getVectorElementType();
27838 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
27840 // (vzext (bitcast (vzext (x)) -> (vzext x)
27842 while (V.getOpcode() == ISD::BITCAST)
27843 V = V.getOperand(0);
27845 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
27846 MVT InnerVT = V.getSimpleValueType();
27847 MVT InnerEltVT = InnerVT.getVectorElementType();
27849 // If the element sizes match exactly, we can just do one larger vzext. This
27850 // is always an exact type match as vzext operates on integer types.
27851 if (OpEltVT == InnerEltVT) {
27852 assert(OpVT == InnerVT && "Types must match for vzext!");
27853 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
27856 // The only other way we can combine them is if only a single element of the
27857 // inner vzext is used in the input to the outer vzext.
27858 if (InnerEltVT.getSizeInBits() < InputBits)
27861 // In this case, the inner vzext is completely dead because we're going to
27862 // only look at bits inside of the low element. Just do the outer vzext on
27863 // a bitcast of the input to the inner.
27864 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
27867 // Check if we can bypass extracting and re-inserting an element of an input
27868 // vector. Essentially:
27869 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
27870 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
27871 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
27872 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
27873 SDValue ExtractedV = V.getOperand(0);
27874 SDValue OrigV = ExtractedV.getOperand(0);
27875 if (isNullConstant(ExtractedV.getOperand(1))) {
27876 MVT OrigVT = OrigV.getSimpleValueType();
27877 // Extract a subvector if necessary...
27878 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
27879 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
27880 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
27881 OrigVT.getVectorNumElements() / Ratio);
27882 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
27883 DAG.getIntPtrConstant(0, DL));
27885 Op = DAG.getBitcast(OpVT, OrigV);
27886 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
27893 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
27894 DAGCombinerInfo &DCI) const {
27895 SelectionDAG &DAG = DCI.DAG;
27896 switch (N->getOpcode()) {
27898 case ISD::EXTRACT_VECTOR_ELT:
27899 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
27902 case X86ISD::SHRUNKBLEND:
27903 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
27904 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
27905 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
27906 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
27907 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
27908 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
27909 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
27912 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
27913 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
27914 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
27915 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
27916 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
27917 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
27918 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
27919 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
27920 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
27921 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
27922 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
27923 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
27924 case ISD::FNEG: return PerformFNEGCombine(N, DAG, Subtarget);
27925 case ISD::TRUNCATE: return PerformTRUNCATECombine(N, DAG, Subtarget);
27927 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
27929 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
27931 case ISD::FMAXNUM: return performFMinNumFMaxNumCombine(N, DAG,
27933 case X86ISD::FAND: return PerformFANDCombine(N, DAG, Subtarget);
27934 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG, Subtarget);
27935 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
27936 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
27937 case ISD::ANY_EXTEND:
27938 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
27939 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
27940 case ISD::SIGN_EXTEND_INREG:
27941 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
27942 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
27943 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
27944 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
27945 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
27946 case X86ISD::SHUFP: // Handle all target specific shuffles
27947 case X86ISD::PALIGNR:
27948 case X86ISD::BLENDI:
27949 case X86ISD::UNPCKH:
27950 case X86ISD::UNPCKL:
27951 case X86ISD::MOVHLPS:
27952 case X86ISD::MOVLHPS:
27953 case X86ISD::PSHUFB:
27954 case X86ISD::PSHUFD:
27955 case X86ISD::PSHUFHW:
27956 case X86ISD::PSHUFLW:
27957 case X86ISD::MOVSS:
27958 case X86ISD::MOVSD:
27959 case X86ISD::VPERMILPI:
27960 case X86ISD::VPERM2X128:
27961 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
27962 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
27964 case ISD::MSCATTER: return PerformGatherScatterCombine(N, DAG);
27970 /// isTypeDesirableForOp - Return true if the target has native support for
27971 /// the specified value type and it is 'desirable' to use the type for the
27972 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
27973 /// instruction encodings are longer and some i16 instructions are slow.
27974 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
27975 if (!isTypeLegal(VT))
27977 if (VT != MVT::i16)
27984 case ISD::SIGN_EXTEND:
27985 case ISD::ZERO_EXTEND:
27986 case ISD::ANY_EXTEND:
27999 /// This function checks if any of the users of EFLAGS copies the EFLAGS. We
28000 /// know that the code that lowers COPY of EFLAGS has to use the stack, and if
28001 /// we don't adjust the stack we clobber the first frame index.
28002 /// See X86InstrInfo::copyPhysReg.
28003 bool X86TargetLowering::hasCopyImplyingStackAdjustment(
28004 MachineFunction *MF) const {
28005 const MachineRegisterInfo &MRI = MF->getRegInfo();
28007 return any_of(MRI.reg_instructions(X86::EFLAGS),
28008 [](const MachineInstr &RI) { return RI.isCopy(); });
28011 /// IsDesirableToPromoteOp - This method query the target whether it is
28012 /// beneficial for dag combiner to promote the specified node. If true, it
28013 /// should return the desired promotion type by reference.
28014 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
28015 EVT VT = Op.getValueType();
28016 if (VT != MVT::i16)
28019 bool Promote = false;
28020 bool Commute = false;
28021 switch (Op.getOpcode()) {
28024 LoadSDNode *LD = cast<LoadSDNode>(Op);
28025 // If the non-extending load has a single use and it's not live out, then it
28026 // might be folded.
28027 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
28028 Op.hasOneUse()*/) {
28029 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
28030 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
28031 // The only case where we'd want to promote LOAD (rather then it being
28032 // promoted as an operand is when it's only use is liveout.
28033 if (UI->getOpcode() != ISD::CopyToReg)
28040 case ISD::SIGN_EXTEND:
28041 case ISD::ZERO_EXTEND:
28042 case ISD::ANY_EXTEND:
28047 SDValue N0 = Op.getOperand(0);
28048 // Look out for (store (shl (load), x)).
28049 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
28062 SDValue N0 = Op.getOperand(0);
28063 SDValue N1 = Op.getOperand(1);
28064 if (!Commute && MayFoldLoad(N1))
28066 // Avoid disabling potential load folding opportunities.
28067 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
28069 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
28079 //===----------------------------------------------------------------------===//
28080 // X86 Inline Assembly Support
28081 //===----------------------------------------------------------------------===//
28083 // Helper to match a string separated by whitespace.
28084 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
28085 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
28087 for (StringRef Piece : Pieces) {
28088 if (!S.startswith(Piece)) // Check if the piece matches.
28091 S = S.substr(Piece.size());
28092 StringRef::size_type Pos = S.find_first_not_of(" \t");
28093 if (Pos == 0) // We matched a prefix.
28102 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
28104 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
28105 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
28106 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
28107 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
28109 if (AsmPieces.size() == 3)
28111 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
28118 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
28119 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
28121 std::string AsmStr = IA->getAsmString();
28123 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
28124 if (!Ty || Ty->getBitWidth() % 16 != 0)
28127 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
28128 SmallVector<StringRef, 4> AsmPieces;
28129 SplitString(AsmStr, AsmPieces, ";\n");
28131 switch (AsmPieces.size()) {
28132 default: return false;
28134 // FIXME: this should verify that we are targeting a 486 or better. If not,
28135 // we will turn this bswap into something that will be lowered to logical
28136 // ops instead of emitting the bswap asm. For now, we don't support 486 or
28137 // lower so don't worry about this.
28139 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
28140 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
28141 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
28142 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
28143 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
28144 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
28145 // No need to check constraints, nothing other than the equivalent of
28146 // "=r,0" would be valid here.
28147 return IntrinsicLowering::LowerToByteSwap(CI);
28150 // rorw $$8, ${0:w} --> llvm.bswap.i16
28151 if (CI->getType()->isIntegerTy(16) &&
28152 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
28153 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
28154 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
28156 StringRef ConstraintsStr = IA->getConstraintString();
28157 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
28158 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
28159 if (clobbersFlagRegisters(AsmPieces))
28160 return IntrinsicLowering::LowerToByteSwap(CI);
28164 if (CI->getType()->isIntegerTy(32) &&
28165 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
28166 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
28167 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
28168 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
28170 StringRef ConstraintsStr = IA->getConstraintString();
28171 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
28172 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
28173 if (clobbersFlagRegisters(AsmPieces))
28174 return IntrinsicLowering::LowerToByteSwap(CI);
28177 if (CI->getType()->isIntegerTy(64)) {
28178 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
28179 if (Constraints.size() >= 2 &&
28180 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
28181 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
28182 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
28183 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
28184 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
28185 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
28186 return IntrinsicLowering::LowerToByteSwap(CI);
28194 /// getConstraintType - Given a constraint letter, return the type of
28195 /// constraint it is for this target.
28196 X86TargetLowering::ConstraintType
28197 X86TargetLowering::getConstraintType(StringRef Constraint) const {
28198 if (Constraint.size() == 1) {
28199 switch (Constraint[0]) {
28210 return C_RegisterClass;
28234 return TargetLowering::getConstraintType(Constraint);
28237 /// Examine constraint type and operand type and determine a weight value.
28238 /// This object must already have been set up with the operand type
28239 /// and the current alternative constraint selected.
28240 TargetLowering::ConstraintWeight
28241 X86TargetLowering::getSingleConstraintMatchWeight(
28242 AsmOperandInfo &info, const char *constraint) const {
28243 ConstraintWeight weight = CW_Invalid;
28244 Value *CallOperandVal = info.CallOperandVal;
28245 // If we don't have a value, we can't do a match,
28246 // but allow it at the lowest weight.
28247 if (!CallOperandVal)
28249 Type *type = CallOperandVal->getType();
28250 // Look at the constraint type.
28251 switch (*constraint) {
28253 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
28264 if (CallOperandVal->getType()->isIntegerTy())
28265 weight = CW_SpecificReg;
28270 if (type->isFloatingPointTy())
28271 weight = CW_SpecificReg;
28274 if (type->isX86_MMXTy() && Subtarget->hasMMX())
28275 weight = CW_SpecificReg;
28279 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
28280 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
28281 weight = CW_Register;
28284 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
28285 if (C->getZExtValue() <= 31)
28286 weight = CW_Constant;
28290 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28291 if (C->getZExtValue() <= 63)
28292 weight = CW_Constant;
28296 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28297 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
28298 weight = CW_Constant;
28302 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28303 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
28304 weight = CW_Constant;
28308 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28309 if (C->getZExtValue() <= 3)
28310 weight = CW_Constant;
28314 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28315 if (C->getZExtValue() <= 0xff)
28316 weight = CW_Constant;
28321 if (isa<ConstantFP>(CallOperandVal)) {
28322 weight = CW_Constant;
28326 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28327 if ((C->getSExtValue() >= -0x80000000LL) &&
28328 (C->getSExtValue() <= 0x7fffffffLL))
28329 weight = CW_Constant;
28333 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28334 if (C->getZExtValue() <= 0xffffffff)
28335 weight = CW_Constant;
28342 /// LowerXConstraint - try to replace an X constraint, which matches anything,
28343 /// with another that has more specific requirements based on the type of the
28344 /// corresponding operand.
28345 const char *X86TargetLowering::
28346 LowerXConstraint(EVT ConstraintVT) const {
28347 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
28348 // 'f' like normal targets.
28349 if (ConstraintVT.isFloatingPoint()) {
28350 if (Subtarget->hasSSE2())
28352 if (Subtarget->hasSSE1())
28356 return TargetLowering::LowerXConstraint(ConstraintVT);
28359 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
28360 /// vector. If it is invalid, don't add anything to Ops.
28361 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
28362 std::string &Constraint,
28363 std::vector<SDValue>&Ops,
28364 SelectionDAG &DAG) const {
28367 // Only support length 1 constraints for now.
28368 if (Constraint.length() > 1) return;
28370 char ConstraintLetter = Constraint[0];
28371 switch (ConstraintLetter) {
28374 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28375 if (C->getZExtValue() <= 31) {
28376 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28377 Op.getValueType());
28383 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28384 if (C->getZExtValue() <= 63) {
28385 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28386 Op.getValueType());
28392 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28393 if (isInt<8>(C->getSExtValue())) {
28394 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28395 Op.getValueType());
28401 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28402 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
28403 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
28404 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
28405 Op.getValueType());
28411 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28412 if (C->getZExtValue() <= 3) {
28413 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28414 Op.getValueType());
28420 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28421 if (C->getZExtValue() <= 255) {
28422 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28423 Op.getValueType());
28429 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28430 if (C->getZExtValue() <= 127) {
28431 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28432 Op.getValueType());
28438 // 32-bit signed value
28439 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28440 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
28441 C->getSExtValue())) {
28442 // Widen to 64 bits here to get it sign extended.
28443 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
28446 // FIXME gcc accepts some relocatable values here too, but only in certain
28447 // memory models; it's complicated.
28452 // 32-bit unsigned value
28453 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28454 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
28455 C->getZExtValue())) {
28456 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28457 Op.getValueType());
28461 // FIXME gcc accepts some relocatable values here too, but only in certain
28462 // memory models; it's complicated.
28466 // Literal immediates are always ok.
28467 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
28468 // Widen to 64 bits here to get it sign extended.
28469 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
28473 // In any sort of PIC mode addresses need to be computed at runtime by
28474 // adding in a register or some sort of table lookup. These can't
28475 // be used as immediates.
28476 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
28479 // If we are in non-pic codegen mode, we allow the address of a global (with
28480 // an optional displacement) to be used with 'i'.
28481 GlobalAddressSDNode *GA = nullptr;
28482 int64_t Offset = 0;
28484 // Match either (GA), (GA+C), (GA+C1+C2), etc.
28486 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
28487 Offset += GA->getOffset();
28489 } else if (Op.getOpcode() == ISD::ADD) {
28490 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
28491 Offset += C->getZExtValue();
28492 Op = Op.getOperand(0);
28495 } else if (Op.getOpcode() == ISD::SUB) {
28496 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
28497 Offset += -C->getZExtValue();
28498 Op = Op.getOperand(0);
28503 // Otherwise, this isn't something we can handle, reject it.
28507 const GlobalValue *GV = GA->getGlobal();
28508 // If we require an extra load to get this address, as in PIC mode, we
28509 // can't accept it.
28510 if (isGlobalStubReference(
28511 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
28514 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
28515 GA->getValueType(0), Offset);
28520 if (Result.getNode()) {
28521 Ops.push_back(Result);
28524 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
28527 std::pair<unsigned, const TargetRegisterClass *>
28528 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
28529 StringRef Constraint,
28531 // First, see if this is a constraint that directly corresponds to an LLVM
28533 if (Constraint.size() == 1) {
28534 // GCC Constraint Letters
28535 switch (Constraint[0]) {
28537 // TODO: Slight differences here in allocation order and leaving
28538 // RIP in the class. Do they matter any more here than they do
28539 // in the normal allocation?
28540 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
28541 if (Subtarget->is64Bit()) {
28542 if (VT == MVT::i32 || VT == MVT::f32)
28543 return std::make_pair(0U, &X86::GR32RegClass);
28544 if (VT == MVT::i16)
28545 return std::make_pair(0U, &X86::GR16RegClass);
28546 if (VT == MVT::i8 || VT == MVT::i1)
28547 return std::make_pair(0U, &X86::GR8RegClass);
28548 if (VT == MVT::i64 || VT == MVT::f64)
28549 return std::make_pair(0U, &X86::GR64RegClass);
28552 // 32-bit fallthrough
28553 case 'Q': // Q_REGS
28554 if (VT == MVT::i32 || VT == MVT::f32)
28555 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
28556 if (VT == MVT::i16)
28557 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
28558 if (VT == MVT::i8 || VT == MVT::i1)
28559 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
28560 if (VT == MVT::i64)
28561 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
28563 case 'r': // GENERAL_REGS
28564 case 'l': // INDEX_REGS
28565 if (VT == MVT::i8 || VT == MVT::i1)
28566 return std::make_pair(0U, &X86::GR8RegClass);
28567 if (VT == MVT::i16)
28568 return std::make_pair(0U, &X86::GR16RegClass);
28569 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
28570 return std::make_pair(0U, &X86::GR32RegClass);
28571 return std::make_pair(0U, &X86::GR64RegClass);
28572 case 'R': // LEGACY_REGS
28573 if (VT == MVT::i8 || VT == MVT::i1)
28574 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
28575 if (VT == MVT::i16)
28576 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
28577 if (VT == MVT::i32 || !Subtarget->is64Bit())
28578 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
28579 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
28580 case 'f': // FP Stack registers.
28581 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
28582 // value to the correct fpstack register class.
28583 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
28584 return std::make_pair(0U, &X86::RFP32RegClass);
28585 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
28586 return std::make_pair(0U, &X86::RFP64RegClass);
28587 return std::make_pair(0U, &X86::RFP80RegClass);
28588 case 'y': // MMX_REGS if MMX allowed.
28589 if (!Subtarget->hasMMX()) break;
28590 return std::make_pair(0U, &X86::VR64RegClass);
28591 case 'Y': // SSE_REGS if SSE2 allowed
28592 if (!Subtarget->hasSSE2()) break;
28594 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
28595 if (!Subtarget->hasSSE1()) break;
28597 switch (VT.SimpleTy) {
28599 // Scalar SSE types.
28602 return std::make_pair(0U, &X86::FR32RegClass);
28605 return std::make_pair(0U, &X86::FR64RegClass);
28606 // TODO: Handle f128 and i128 in FR128RegClass after it is tested well.
28614 return std::make_pair(0U, &X86::VR128RegClass);
28622 return std::make_pair(0U, &X86::VR256RegClass);
28627 return std::make_pair(0U, &X86::VR512RegClass);
28633 // Use the default implementation in TargetLowering to convert the register
28634 // constraint into a member of a register class.
28635 std::pair<unsigned, const TargetRegisterClass*> Res;
28636 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
28638 // Not found as a standard register?
28640 // Map st(0) -> st(7) -> ST0
28641 if (Constraint.size() == 7 && Constraint[0] == '{' &&
28642 tolower(Constraint[1]) == 's' &&
28643 tolower(Constraint[2]) == 't' &&
28644 Constraint[3] == '(' &&
28645 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
28646 Constraint[5] == ')' &&
28647 Constraint[6] == '}') {
28649 Res.first = X86::FP0+Constraint[4]-'0';
28650 Res.second = &X86::RFP80RegClass;
28654 // GCC allows "st(0)" to be called just plain "st".
28655 if (StringRef("{st}").equals_lower(Constraint)) {
28656 Res.first = X86::FP0;
28657 Res.second = &X86::RFP80RegClass;
28662 if (StringRef("{flags}").equals_lower(Constraint)) {
28663 Res.first = X86::EFLAGS;
28664 Res.second = &X86::CCRRegClass;
28668 // 'A' means EAX + EDX.
28669 if (Constraint == "A") {
28670 Res.first = X86::EAX;
28671 Res.second = &X86::GR32_ADRegClass;
28677 // Otherwise, check to see if this is a register class of the wrong value
28678 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
28679 // turn into {ax},{dx}.
28680 // MVT::Other is used to specify clobber names.
28681 if (Res.second->hasType(VT) || VT == MVT::Other)
28682 return Res; // Correct type already, nothing to do.
28684 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
28685 // return "eax". This should even work for things like getting 64bit integer
28686 // registers when given an f64 type.
28687 const TargetRegisterClass *Class = Res.second;
28688 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
28689 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
28690 unsigned Size = VT.getSizeInBits();
28691 if (Size == 1) Size = 8;
28692 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, Size);
28694 Res.first = DestReg;
28695 Res.second = Size == 8 ? &X86::GR8RegClass
28696 : Size == 16 ? &X86::GR16RegClass
28697 : Size == 32 ? &X86::GR32RegClass
28698 : &X86::GR64RegClass;
28699 assert(Res.second->contains(Res.first) && "Register in register class");
28701 // No register found/type mismatch.
28703 Res.second = nullptr;
28705 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
28706 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
28707 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
28708 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
28709 Class == &X86::VR512RegClass) {
28710 // Handle references to XMM physical registers that got mapped into the
28711 // wrong class. This can happen with constraints like {xmm0} where the
28712 // target independent register mapper will just pick the first match it can
28713 // find, ignoring the required type.
28715 // TODO: Handle f128 and i128 in FR128RegClass after it is tested well.
28716 if (VT == MVT::f32 || VT == MVT::i32)
28717 Res.second = &X86::FR32RegClass;
28718 else if (VT == MVT::f64 || VT == MVT::i64)
28719 Res.second = &X86::FR64RegClass;
28720 else if (X86::VR128RegClass.hasType(VT))
28721 Res.second = &X86::VR128RegClass;
28722 else if (X86::VR256RegClass.hasType(VT))
28723 Res.second = &X86::VR256RegClass;
28724 else if (X86::VR512RegClass.hasType(VT))
28725 Res.second = &X86::VR512RegClass;
28727 // Type mismatch and not a clobber: Return an error;
28729 Res.second = nullptr;
28736 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
28737 const AddrMode &AM, Type *Ty,
28738 unsigned AS) const {
28739 // Scaling factors are not free at all.
28740 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
28741 // will take 2 allocations in the out of order engine instead of 1
28742 // for plain addressing mode, i.e. inst (reg1).
28744 // vaddps (%rsi,%drx), %ymm0, %ymm1
28745 // Requires two allocations (one for the load, one for the computation)
28747 // vaddps (%rsi), %ymm0, %ymm1
28748 // Requires just 1 allocation, i.e., freeing allocations for other operations
28749 // and having less micro operations to execute.
28751 // For some X86 architectures, this is even worse because for instance for
28752 // stores, the complex addressing mode forces the instruction to use the
28753 // "load" ports instead of the dedicated "store" port.
28754 // E.g., on Haswell:
28755 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
28756 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
28757 if (isLegalAddressingMode(DL, AM, Ty, AS))
28758 // Scale represents reg2 * scale, thus account for 1
28759 // as soon as we use a second register.
28760 return AM.Scale != 0;
28764 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
28765 // Integer division on x86 is expensive. However, when aggressively optimizing
28766 // for code size, we prefer to use a div instruction, as it is usually smaller
28767 // than the alternative sequence.
28768 // The exception to this is vector division. Since x86 doesn't have vector
28769 // integer division, leaving the division as-is is a loss even in terms of
28770 // size, because it will have to be scalarized, while the alternative code
28771 // sequence can be performed in vector form.
28772 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
28773 Attribute::MinSize);
28774 return OptSize && !VT.isVector();