1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/StringExtras.h"
41 #include "llvm/Support/CommandLine.h"
45 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
47 // Forward declarations.
48 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl);
50 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
51 : TargetLowering(TM) {
52 Subtarget = &TM.getSubtarget<X86Subtarget>();
53 X86ScalarSSEf64 = Subtarget->hasSSE2();
54 X86ScalarSSEf32 = Subtarget->hasSSE1();
55 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
59 RegInfo = TM.getRegisterInfo();
62 // Set up the TargetLowering object.
64 // X86 is weird, it always uses i8 for shift amounts and setcc results.
65 setShiftAmountType(MVT::i8);
66 setBooleanContents(ZeroOrOneBooleanContent);
67 setSchedulingPreference(SchedulingForRegPressure);
68 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
69 setStackPointerRegisterToSaveRestore(X86StackPtr);
71 if (Subtarget->isTargetDarwin()) {
72 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(false);
74 setUseUnderscoreLongJmp(false);
75 } else if (Subtarget->isTargetMingw()) {
76 // MS runtime is weird: it exports _setjmp, but longjmp!
77 setUseUnderscoreSetJmp(true);
78 setUseUnderscoreLongJmp(false);
80 setUseUnderscoreSetJmp(true);
81 setUseUnderscoreLongJmp(true);
84 // Set up the register classes.
85 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
86 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
87 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
88 if (Subtarget->is64Bit())
89 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 // We don't accept any truncstore of integer registers.
94 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
95 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
96 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
97 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
98 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
99 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
101 // SETOEQ and SETUNE require checking two conditions.
102 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
103 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
104 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
105 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
106 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
107 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
109 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
111 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
112 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
113 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
115 if (Subtarget->is64Bit()) {
116 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
117 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
119 if (X86ScalarSSEf64) {
120 // We have an impenetrably clever algorithm for ui64->double only.
121 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
123 // We have faster algorithm for ui32->single only.
124 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
126 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
129 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
131 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
132 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
133 // SSE has no i16 to fp conversion, only i32
134 if (X86ScalarSSEf32) {
135 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
136 // f32 and f64 cases are Legal, f80 case is not
137 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
139 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
140 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
143 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
144 // are Legal, f80 is custom lowered.
145 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
146 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
148 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
150 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
151 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
153 if (X86ScalarSSEf32) {
154 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
155 // f32 and f64 cases are Legal, f80 case is not
156 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
158 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
159 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
162 // Handle FP_TO_UINT by promoting the destination to a larger signed
164 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
165 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
166 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
168 if (Subtarget->is64Bit()) {
169 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
170 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
172 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
173 // Expand FP_TO_UINT into a select.
174 // FIXME: We would like to use a Custom expander here eventually to do
175 // the optimal thing for SSE vs. the default expansion in the legalizer.
176 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
178 // With SSE3 we can use fisttpll to convert to a signed i64.
179 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
182 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
183 if (!X86ScalarSSEf64) {
184 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
185 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
188 // Scalar integer divide and remainder are lowered to use operations that
189 // produce two results, to match the available instructions. This exposes
190 // the two-result form to trivial CSE, which is able to combine x/y and x%y
191 // into a single instruction.
193 // Scalar integer multiply-high is also lowered to use two-result
194 // operations, to match the available instructions. However, plain multiply
195 // (low) operations are left as Legal, as there are single-result
196 // instructions for this in x86. Using the two-result multiply instructions
197 // when both high and low results are needed must be arranged by dagcombine.
198 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
199 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
200 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
201 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
202 setOperationAction(ISD::SREM , MVT::i8 , Expand);
203 setOperationAction(ISD::UREM , MVT::i8 , Expand);
204 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
205 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
206 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
207 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
208 setOperationAction(ISD::SREM , MVT::i16 , Expand);
209 setOperationAction(ISD::UREM , MVT::i16 , Expand);
210 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
211 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
212 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
213 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
214 setOperationAction(ISD::SREM , MVT::i32 , Expand);
215 setOperationAction(ISD::UREM , MVT::i32 , Expand);
216 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
217 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
218 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
219 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
220 setOperationAction(ISD::SREM , MVT::i64 , Expand);
221 setOperationAction(ISD::UREM , MVT::i64 , Expand);
223 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
224 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
225 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
226 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
227 if (Subtarget->is64Bit())
228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
232 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
233 setOperationAction(ISD::FREM , MVT::f32 , Expand);
234 setOperationAction(ISD::FREM , MVT::f64 , Expand);
235 setOperationAction(ISD::FREM , MVT::f80 , Expand);
236 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
238 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
239 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
240 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
241 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
242 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
243 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
244 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
245 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
246 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
247 if (Subtarget->is64Bit()) {
248 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
249 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
250 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
253 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
254 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
256 // These should be promoted to a larger select which is supported.
257 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
258 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
259 // X86 wants to expand cmov itself.
260 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
261 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
262 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
263 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
264 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
265 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
266 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
267 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
268 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
269 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
270 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
271 if (Subtarget->is64Bit()) {
272 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
273 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
275 // X86 ret instruction may pop stack.
276 setOperationAction(ISD::RET , MVT::Other, Custom);
277 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
280 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
281 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
282 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
283 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
284 if (Subtarget->is64Bit())
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
289 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
290 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
291 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
293 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
294 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
295 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
296 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
297 if (Subtarget->is64Bit()) {
298 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
299 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
300 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
303 if (Subtarget->hasSSE1())
304 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
306 if (!Subtarget->hasSSE2())
307 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
309 // Expand certain atomics
310 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
311 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
312 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
313 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
315 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
316 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
317 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
318 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
320 if (!Subtarget->is64Bit()) {
321 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
322 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
323 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
324 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
325 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
326 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
327 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
330 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
331 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
332 // FIXME - use subtarget debug flags
333 if (!Subtarget->isTargetDarwin() &&
334 !Subtarget->isTargetELF() &&
335 !Subtarget->isTargetCygMing()) {
336 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
337 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
340 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
341 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
342 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
343 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
344 if (Subtarget->is64Bit()) {
345 setExceptionPointerRegister(X86::RAX);
346 setExceptionSelectorRegister(X86::RDX);
348 setExceptionPointerRegister(X86::EAX);
349 setExceptionSelectorRegister(X86::EDX);
351 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
352 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
354 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
356 setOperationAction(ISD::TRAP, MVT::Other, Legal);
358 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
359 setOperationAction(ISD::VASTART , MVT::Other, Custom);
360 setOperationAction(ISD::VAEND , MVT::Other, Expand);
361 if (Subtarget->is64Bit()) {
362 setOperationAction(ISD::VAARG , MVT::Other, Custom);
363 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
365 setOperationAction(ISD::VAARG , MVT::Other, Expand);
366 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
369 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
370 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
371 if (Subtarget->is64Bit())
372 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
373 if (Subtarget->isTargetCygMing())
374 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
376 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
378 if (X86ScalarSSEf64) {
379 // f32 and f64 use SSE.
380 // Set up the FP register classes.
381 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
382 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
384 // Use ANDPD to simulate FABS.
385 setOperationAction(ISD::FABS , MVT::f64, Custom);
386 setOperationAction(ISD::FABS , MVT::f32, Custom);
388 // Use XORP to simulate FNEG.
389 setOperationAction(ISD::FNEG , MVT::f64, Custom);
390 setOperationAction(ISD::FNEG , MVT::f32, Custom);
392 // Use ANDPD and ORPD to simulate FCOPYSIGN.
393 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
394 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
396 // We don't support sin/cos/fmod
397 setOperationAction(ISD::FSIN , MVT::f64, Expand);
398 setOperationAction(ISD::FCOS , MVT::f64, Expand);
399 setOperationAction(ISD::FSIN , MVT::f32, Expand);
400 setOperationAction(ISD::FCOS , MVT::f32, Expand);
402 // Expand FP immediates into loads from the stack, except for the special
404 addLegalFPImmediate(APFloat(+0.0)); // xorpd
405 addLegalFPImmediate(APFloat(+0.0f)); // xorps
407 // Floating truncations from f80 and extensions to f80 go through memory.
408 // If optimizing, we lie about this though and handle it in
409 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
411 setConvertAction(MVT::f32, MVT::f80, Expand);
412 setConvertAction(MVT::f64, MVT::f80, Expand);
413 setConvertAction(MVT::f80, MVT::f32, Expand);
414 setConvertAction(MVT::f80, MVT::f64, Expand);
416 } else if (X86ScalarSSEf32) {
417 // Use SSE for f32, x87 for f64.
418 // Set up the FP register classes.
419 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
420 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
422 // Use ANDPS to simulate FABS.
423 setOperationAction(ISD::FABS , MVT::f32, Custom);
425 // Use XORP to simulate FNEG.
426 setOperationAction(ISD::FNEG , MVT::f32, Custom);
428 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
430 // Use ANDPS and ORPS to simulate FCOPYSIGN.
431 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
432 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
434 // We don't support sin/cos/fmod
435 setOperationAction(ISD::FSIN , MVT::f32, Expand);
436 setOperationAction(ISD::FCOS , MVT::f32, Expand);
438 // Special cases we handle for FP constants.
439 addLegalFPImmediate(APFloat(+0.0f)); // xorps
440 addLegalFPImmediate(APFloat(+0.0)); // FLD0
441 addLegalFPImmediate(APFloat(+1.0)); // FLD1
442 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
443 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
445 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
446 // this though and handle it in InstructionSelectPreprocess so that
447 // dagcombine2 can hack on these.
449 setConvertAction(MVT::f32, MVT::f64, Expand);
450 setConvertAction(MVT::f32, MVT::f80, Expand);
451 setConvertAction(MVT::f80, MVT::f32, Expand);
452 setConvertAction(MVT::f64, MVT::f32, Expand);
453 // And x87->x87 truncations also.
454 setConvertAction(MVT::f80, MVT::f64, Expand);
458 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
459 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
462 // f32 and f64 in x87.
463 // Set up the FP register classes.
464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
465 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
467 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
468 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
469 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
470 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
472 // Floating truncations go through memory. If optimizing, we lie about
473 // this though and handle it in InstructionSelectPreprocess so that
474 // dagcombine2 can hack on these.
476 setConvertAction(MVT::f80, MVT::f32, Expand);
477 setConvertAction(MVT::f64, MVT::f32, Expand);
478 setConvertAction(MVT::f80, MVT::f64, Expand);
482 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
483 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
485 addLegalFPImmediate(APFloat(+0.0)); // FLD0
486 addLegalFPImmediate(APFloat(+1.0)); // FLD1
487 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
488 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
489 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
490 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
491 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
492 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
495 // Long double always uses X87.
496 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
497 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
498 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
501 APFloat TmpFlt(+0.0);
502 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
504 addLegalFPImmediate(TmpFlt); // FLD0
506 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
507 APFloat TmpFlt2(+1.0);
508 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
510 addLegalFPImmediate(TmpFlt2); // FLD1
511 TmpFlt2.changeSign();
512 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
516 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
517 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
520 // Always use a library call for pow.
521 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
522 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
523 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
525 setOperationAction(ISD::FLOG, MVT::f80, Expand);
526 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
527 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
528 setOperationAction(ISD::FEXP, MVT::f80, Expand);
529 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
531 // First set operation action for all vector types to either promote
532 // (for widening) or expand (for scalarization). Then we will selectively
533 // turn on ones that can be effectively codegen'd.
534 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
535 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
536 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
551 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
581 if (!DisableMMX && Subtarget->hasMMX()) {
582 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
583 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
584 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
585 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
586 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
588 // FIXME: add MMX packed arithmetics
590 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
591 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
592 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
593 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
595 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
596 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
597 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
598 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
600 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
601 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
603 setOperationAction(ISD::AND, MVT::v8i8, Promote);
604 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
605 setOperationAction(ISD::AND, MVT::v4i16, Promote);
606 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
607 setOperationAction(ISD::AND, MVT::v2i32, Promote);
608 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
609 setOperationAction(ISD::AND, MVT::v1i64, Legal);
611 setOperationAction(ISD::OR, MVT::v8i8, Promote);
612 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
613 setOperationAction(ISD::OR, MVT::v4i16, Promote);
614 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
615 setOperationAction(ISD::OR, MVT::v2i32, Promote);
616 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
617 setOperationAction(ISD::OR, MVT::v1i64, Legal);
619 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
620 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
621 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
622 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
623 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
624 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
625 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
627 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
628 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
629 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
630 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
631 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
632 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
633 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
634 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
635 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
637 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
638 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
639 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
640 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
641 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
645 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
646 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
648 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
649 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
651 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
653 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
655 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
656 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
657 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
658 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
659 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
660 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
663 if (Subtarget->hasSSE1()) {
664 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
666 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
667 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
668 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
669 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
670 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
671 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
672 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
673 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
675 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
676 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
677 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
680 if (Subtarget->hasSSE2()) {
681 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
682 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
683 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
684 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
685 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
687 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
688 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
689 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
690 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
691 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
692 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
693 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
694 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
695 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
696 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
697 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
698 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
699 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
700 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
701 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
702 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
704 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
705 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
706 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
707 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
709 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
710 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
711 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
712 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
713 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
715 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
716 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
717 MVT VT = (MVT::SimpleValueType)i;
718 // Do not attempt to custom lower non-power-of-2 vectors
719 if (!isPowerOf2_32(VT.getVectorNumElements()))
721 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
722 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
723 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
725 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
726 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
727 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
728 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
729 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
730 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
731 if (Subtarget->is64Bit()) {
732 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
733 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
736 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
737 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
738 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
739 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
740 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
741 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
742 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
743 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
744 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
745 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
746 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
747 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
750 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
752 // Custom lower v2i64 and v2f64 selects.
753 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
754 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
755 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
756 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
760 if (Subtarget->hasSSE41()) {
761 // FIXME: Do we need to handle scalar-to-vector here?
762 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
764 // i8 and i16 vectors are custom , because the source register and source
765 // source memory operand types are not the same width. f32 vectors are
766 // custom since the immediate controlling the insert encodes additional
768 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
771 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
773 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
774 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
776 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
778 if (Subtarget->is64Bit()) {
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
780 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
784 if (Subtarget->hasSSE42()) {
785 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
788 // We want to custom lower some of our intrinsics.
789 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
791 // Add/Sub/Mul with overflow operations are custom lowered.
792 setOperationAction(ISD::SADDO, MVT::i32, Custom);
793 setOperationAction(ISD::SADDO, MVT::i64, Custom);
794 setOperationAction(ISD::UADDO, MVT::i32, Custom);
795 setOperationAction(ISD::UADDO, MVT::i64, Custom);
796 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
797 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
798 setOperationAction(ISD::USUBO, MVT::i32, Custom);
799 setOperationAction(ISD::USUBO, MVT::i64, Custom);
800 setOperationAction(ISD::SMULO, MVT::i32, Custom);
801 setOperationAction(ISD::SMULO, MVT::i64, Custom);
802 setOperationAction(ISD::UMULO, MVT::i32, Custom);
803 setOperationAction(ISD::UMULO, MVT::i64, Custom);
805 // We have target-specific dag combine patterns for the following nodes:
806 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
807 setTargetDAGCombine(ISD::BUILD_VECTOR);
808 setTargetDAGCombine(ISD::SELECT);
809 setTargetDAGCombine(ISD::SHL);
810 setTargetDAGCombine(ISD::SRA);
811 setTargetDAGCombine(ISD::SRL);
812 setTargetDAGCombine(ISD::STORE);
814 computeRegisterProperties();
816 // FIXME: These should be based on subtarget info. Plus, the values should
817 // be smaller when we are in optimizing for size mode.
818 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
819 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
820 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
821 allowUnalignedMemoryAccesses = true; // x86 supports it!
822 setPrefLoopAlignment(16);
826 MVT X86TargetLowering::getSetCCResultType(MVT VT) const {
831 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
832 /// the desired ByVal argument alignment.
833 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
836 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
837 if (VTy->getBitWidth() == 128)
839 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
840 unsigned EltAlign = 0;
841 getMaxByValAlign(ATy->getElementType(), EltAlign);
842 if (EltAlign > MaxAlign)
844 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
845 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
846 unsigned EltAlign = 0;
847 getMaxByValAlign(STy->getElementType(i), EltAlign);
848 if (EltAlign > MaxAlign)
857 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
858 /// function arguments in the caller parameter area. For X86, aggregates
859 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
860 /// are at 4-byte boundaries.
861 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
862 if (Subtarget->is64Bit()) {
863 // Max of 8 and alignment of type.
864 unsigned TyAlign = TD->getABITypeAlignment(Ty);
871 if (Subtarget->hasSSE1())
872 getMaxByValAlign(Ty, Align);
876 /// getOptimalMemOpType - Returns the target specific optimal type for load
877 /// and store operations as a result of memset, memcpy, and memmove
878 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
881 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
882 bool isSrcConst, bool isSrcStr) const {
883 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
884 // linux. This is because the stack realignment code can't handle certain
885 // cases like PR2962. This should be removed when PR2962 is fixed.
886 if (Subtarget->getStackAlignment() >= 16) {
887 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
889 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
892 if (Subtarget->is64Bit() && Size >= 8)
898 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
900 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
901 SelectionDAG &DAG) const {
902 if (usesGlobalOffsetTable())
903 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
904 if (!Subtarget->isPICStyleRIPRel())
905 // This doesn't have DebugLoc associated with it, but is not really the
906 // same as a Register.
907 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
912 //===----------------------------------------------------------------------===//
913 // Return Value Calling Convention Implementation
914 //===----------------------------------------------------------------------===//
916 #include "X86GenCallingConv.inc"
918 /// LowerRET - Lower an ISD::RET node.
919 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
920 DebugLoc dl = Op.getDebugLoc();
921 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
923 SmallVector<CCValAssign, 16> RVLocs;
924 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
925 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
926 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
927 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
929 // If this is the first return lowered for this function, add the regs to the
930 // liveout set for the function.
931 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
932 for (unsigned i = 0; i != RVLocs.size(); ++i)
933 if (RVLocs[i].isRegLoc())
934 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
936 SDValue Chain = Op.getOperand(0);
938 // Handle tail call return.
939 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
940 if (Chain.getOpcode() == X86ISD::TAILCALL) {
941 SDValue TailCall = Chain;
942 SDValue TargetAddress = TailCall.getOperand(1);
943 SDValue StackAdjustment = TailCall.getOperand(2);
944 assert(((TargetAddress.getOpcode() == ISD::Register &&
945 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
946 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
947 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
948 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
949 "Expecting an global address, external symbol, or register");
950 assert(StackAdjustment.getOpcode() == ISD::Constant &&
951 "Expecting a const value");
953 SmallVector<SDValue,8> Operands;
954 Operands.push_back(Chain.getOperand(0));
955 Operands.push_back(TargetAddress);
956 Operands.push_back(StackAdjustment);
957 // Copy registers used by the call. Last operand is a flag so it is not
959 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
960 Operands.push_back(Chain.getOperand(i));
962 return DAG.getNode(X86ISD::TC_RETURN, dl, MVT::Other, &Operands[0],
969 SmallVector<SDValue, 6> RetOps;
970 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
971 // Operand #1 = Bytes To Pop
972 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
974 // Copy the result values into the output registers.
975 for (unsigned i = 0; i != RVLocs.size(); ++i) {
976 CCValAssign &VA = RVLocs[i];
977 assert(VA.isRegLoc() && "Can only return in registers!");
978 SDValue ValToCopy = Op.getOperand(i*2+1);
980 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
981 // the RET instruction and handled by the FP Stackifier.
982 if (VA.getLocReg() == X86::ST0 ||
983 VA.getLocReg() == X86::ST1) {
984 // If this is a copy from an xmm register to ST(0), use an FPExtend to
985 // change the value to the FP stack register class.
986 if (isScalarFPTypeInSSEReg(VA.getValVT()))
987 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
988 RetOps.push_back(ValToCopy);
989 // Don't emit a copytoreg.
993 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
994 Flag = Chain.getValue(1);
997 // The x86-64 ABI for returning structs by value requires that we copy
998 // the sret argument into %rax for the return. We saved the argument into
999 // a virtual register in the entry block, so now we copy the value out
1001 if (Subtarget->is64Bit() &&
1002 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1003 MachineFunction &MF = DAG.getMachineFunction();
1004 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1005 unsigned Reg = FuncInfo->getSRetReturnReg();
1007 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1008 FuncInfo->setSRetReturnReg(Reg);
1010 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1012 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1013 Flag = Chain.getValue(1);
1016 RetOps[0] = Chain; // Update chain.
1018 // Add the flag if we have it.
1020 RetOps.push_back(Flag);
1022 return DAG.getNode(X86ISD::RET_FLAG, dl,
1023 MVT::Other, &RetOps[0], RetOps.size());
1027 /// LowerCallResult - Lower the result values of an ISD::CALL into the
1028 /// appropriate copies out of appropriate physical registers. This assumes that
1029 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
1030 /// being lowered. The returns a SDNode with the same number of values as the
1032 SDNode *X86TargetLowering::
1033 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
1034 unsigned CallingConv, SelectionDAG &DAG) {
1036 DebugLoc dl = TheCall->getDebugLoc();
1037 // Assign locations to each value returned by this call.
1038 SmallVector<CCValAssign, 16> RVLocs;
1039 bool isVarArg = TheCall->isVarArg();
1040 bool Is64Bit = Subtarget->is64Bit();
1041 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
1042 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
1044 SmallVector<SDValue, 8> ResultVals;
1046 // Copy all of the result registers out of their specified physreg.
1047 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1048 CCValAssign &VA = RVLocs[i];
1049 MVT CopyVT = VA.getValVT();
1051 // If this is x86-64, and we disabled SSE, we can't return FP values
1052 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1053 ((Is64Bit || TheCall->isInreg()) && !Subtarget->hasSSE1())) {
1054 cerr << "SSE register return with SSE disabled\n";
1058 // If this is a call to a function that returns an fp value on the floating
1059 // point stack, but where we prefer to use the value in xmm registers, copy
1060 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1061 if ((VA.getLocReg() == X86::ST0 ||
1062 VA.getLocReg() == X86::ST1) &&
1063 isScalarFPTypeInSSEReg(VA.getValVT())) {
1067 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1068 CopyVT, InFlag).getValue(1);
1069 SDValue Val = Chain.getValue(0);
1070 InFlag = Chain.getValue(2);
1072 if (CopyVT != VA.getValVT()) {
1073 // Round the F80 the right size, which also moves to the appropriate xmm
1075 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1076 // This truncation won't change the value.
1077 DAG.getIntPtrConstant(1));
1080 ResultVals.push_back(Val);
1083 // Merge everything together with a MERGE_VALUES node.
1084 ResultVals.push_back(Chain);
1085 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
1086 &ResultVals[0], ResultVals.size()).getNode();
1090 //===----------------------------------------------------------------------===//
1091 // C & StdCall & Fast Calling Convention implementation
1092 //===----------------------------------------------------------------------===//
1093 // StdCall calling convention seems to be standard for many Windows' API
1094 // routines and around. It differs from C calling convention just a little:
1095 // callee should clean up the stack, not caller. Symbols should be also
1096 // decorated in some fancy way :) It doesn't support any vector arguments.
1097 // For info on fast calling convention see Fast Calling Convention (tail call)
1098 // implementation LowerX86_32FastCCCallTo.
1100 /// AddLiveIn - This helper function adds the specified physical register to the
1101 /// MachineFunction as a live in value. It also creates a corresponding virtual
1102 /// register for it.
1103 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
1104 const TargetRegisterClass *RC) {
1105 assert(RC->contains(PReg) && "Not the correct regclass!");
1106 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1107 MF.getRegInfo().addLiveIn(PReg, VReg);
1111 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1113 static bool CallIsStructReturn(CallSDNode *TheCall) {
1114 unsigned NumOps = TheCall->getNumArgs();
1118 return TheCall->getArgFlags(0).isSRet();
1121 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1122 /// return semantics.
1123 static bool ArgsAreStructReturn(SDValue Op) {
1124 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1128 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1131 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1132 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1134 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1138 switch (CallingConv) {
1141 case CallingConv::X86_StdCall:
1142 return !Subtarget->is64Bit();
1143 case CallingConv::X86_FastCall:
1144 return !Subtarget->is64Bit();
1145 case CallingConv::Fast:
1146 return PerformTailCallOpt;
1150 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1151 /// given CallingConvention value.
1152 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1153 if (Subtarget->is64Bit()) {
1154 if (Subtarget->isTargetWin64())
1155 return CC_X86_Win64_C;
1156 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1157 return CC_X86_64_TailCall;
1162 if (CC == CallingConv::X86_FastCall)
1163 return CC_X86_32_FastCall;
1164 else if (CC == CallingConv::Fast)
1165 return CC_X86_32_FastCC;
1170 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1171 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1173 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1174 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1175 if (CC == CallingConv::X86_FastCall)
1177 else if (CC == CallingConv::X86_StdCall)
1183 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1184 /// in a register before calling.
1185 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1186 return !IsTailCall && !Is64Bit &&
1187 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1188 Subtarget->isPICStyleGOT();
1191 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1192 /// address to be loaded in a register.
1194 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1195 return !Is64Bit && IsTailCall &&
1196 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1197 Subtarget->isPICStyleGOT();
1200 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1201 /// by "Src" to address "Dst" with size and alignment information specified by
1202 /// the specific parameter attribute. The copy will be passed as a byval
1203 /// function parameter.
1205 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1206 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1208 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1209 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1210 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1213 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1214 const CCValAssign &VA,
1215 MachineFrameInfo *MFI,
1217 SDValue Root, unsigned i) {
1218 // Create the nodes corresponding to a load from this parameter slot.
1219 ISD::ArgFlagsTy Flags =
1220 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1221 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1222 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1224 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1225 // changed with more analysis.
1226 // In case of tail call optimization mark all arguments mutable. Since they
1227 // could be overwritten by lowering of arguments in case of a tail call.
1228 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1229 VA.getLocMemOffset(), isImmutable);
1230 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1231 if (Flags.isByVal())
1233 return DAG.getLoad(VA.getValVT(), Op.getDebugLoc(), Root, FIN,
1234 PseudoSourceValue::getFixedStack(FI), 0);
1238 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1239 MachineFunction &MF = DAG.getMachineFunction();
1240 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1241 DebugLoc dl = Op.getDebugLoc();
1243 const Function* Fn = MF.getFunction();
1244 if (Fn->hasExternalLinkage() &&
1245 Subtarget->isTargetCygMing() &&
1246 Fn->getName() == "main")
1247 FuncInfo->setForceFramePointer(true);
1249 // Decorate the function name.
1250 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1252 MachineFrameInfo *MFI = MF.getFrameInfo();
1253 SDValue Root = Op.getOperand(0);
1254 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1255 unsigned CC = MF.getFunction()->getCallingConv();
1256 bool Is64Bit = Subtarget->is64Bit();
1257 bool IsWin64 = Subtarget->isTargetWin64();
1259 assert(!(isVarArg && CC == CallingConv::Fast) &&
1260 "Var args not supported with calling convention fastcc");
1262 // Assign locations to all of the incoming arguments.
1263 SmallVector<CCValAssign, 16> ArgLocs;
1264 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1265 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
1267 SmallVector<SDValue, 8> ArgValues;
1268 unsigned LastVal = ~0U;
1269 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1270 CCValAssign &VA = ArgLocs[i];
1271 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1273 assert(VA.getValNo() != LastVal &&
1274 "Don't support value assigned to multiple locs yet");
1275 LastVal = VA.getValNo();
1277 if (VA.isRegLoc()) {
1278 MVT RegVT = VA.getLocVT();
1279 TargetRegisterClass *RC = NULL;
1280 if (RegVT == MVT::i32)
1281 RC = X86::GR32RegisterClass;
1282 else if (Is64Bit && RegVT == MVT::i64)
1283 RC = X86::GR64RegisterClass;
1284 else if (RegVT == MVT::f32)
1285 RC = X86::FR32RegisterClass;
1286 else if (RegVT == MVT::f64)
1287 RC = X86::FR64RegisterClass;
1288 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1289 RC = X86::VR128RegisterClass;
1290 else if (RegVT.isVector()) {
1291 assert(RegVT.getSizeInBits() == 64);
1293 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1295 // Darwin calling convention passes MMX values in either GPRs or
1296 // XMMs in x86-64. Other targets pass them in memory.
1297 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1298 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1301 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1306 assert(0 && "Unknown argument type!");
1309 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1310 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1312 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1313 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1315 if (VA.getLocInfo() == CCValAssign::SExt)
1316 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1317 DAG.getValueType(VA.getValVT()));
1318 else if (VA.getLocInfo() == CCValAssign::ZExt)
1319 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1320 DAG.getValueType(VA.getValVT()));
1322 if (VA.getLocInfo() != CCValAssign::Full)
1323 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1325 // Handle MMX values passed in GPRs.
1326 if (Is64Bit && RegVT != VA.getLocVT()) {
1327 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1328 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
1329 else if (RC == X86::VR128RegisterClass) {
1330 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1331 ArgValue, DAG.getConstant(0, MVT::i64));
1332 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), ArgValue);
1336 ArgValues.push_back(ArgValue);
1338 assert(VA.isMemLoc());
1339 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1343 // The x86-64 ABI for returning structs by value requires that we copy
1344 // the sret argument into %rax for the return. Save the argument into
1345 // a virtual register so that we can access it from the return points.
1346 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1347 MachineFunction &MF = DAG.getMachineFunction();
1348 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1349 unsigned Reg = FuncInfo->getSRetReturnReg();
1351 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1352 FuncInfo->setSRetReturnReg(Reg);
1354 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, ArgValues[0]);
1355 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Root);
1358 unsigned StackSize = CCInfo.getNextStackOffset();
1359 // align stack specially for tail calls
1360 if (PerformTailCallOpt && CC == CallingConv::Fast)
1361 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1363 // If the function takes variable number of arguments, make a frame index for
1364 // the start of the first vararg value... for expansion of llvm.va_start.
1366 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1367 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1370 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1372 // FIXME: We should really autogenerate these arrays
1373 static const unsigned GPR64ArgRegsWin64[] = {
1374 X86::RCX, X86::RDX, X86::R8, X86::R9
1376 static const unsigned XMMArgRegsWin64[] = {
1377 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1379 static const unsigned GPR64ArgRegs64Bit[] = {
1380 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1382 static const unsigned XMMArgRegs64Bit[] = {
1383 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1384 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1386 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1389 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1390 GPR64ArgRegs = GPR64ArgRegsWin64;
1391 XMMArgRegs = XMMArgRegsWin64;
1393 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1394 GPR64ArgRegs = GPR64ArgRegs64Bit;
1395 XMMArgRegs = XMMArgRegs64Bit;
1397 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1399 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1402 assert((Subtarget->hasSSE1() || !NumXMMRegs) &&
1403 "SSE register cannot be used when SSE is disabled!");
1404 if (!Subtarget->hasSSE1()) {
1405 // Kernel mode asks for SSE to be disabled, so don't push them
1407 TotalNumXMMRegs = 0;
1409 // For X86-64, if there are vararg parameters that are passed via
1410 // registers, then we must store them to their spots on the stack so they
1411 // may be loaded by deferencing the result of va_next.
1412 VarArgsGPOffset = NumIntRegs * 8;
1413 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1414 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1415 TotalNumXMMRegs * 16, 16);
1417 // Store the integer parameter registers.
1418 SmallVector<SDValue, 8> MemOps;
1419 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1420 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1421 DAG.getIntPtrConstant(VarArgsGPOffset));
1422 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1423 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1424 X86::GR64RegisterClass);
1425 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
1427 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1428 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1429 MemOps.push_back(Store);
1430 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1431 DAG.getIntPtrConstant(8));
1434 // Now store the XMM (fp + vector) parameter registers.
1435 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1436 DAG.getIntPtrConstant(VarArgsFPOffset));
1437 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1438 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1439 X86::VR128RegisterClass);
1440 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::v4f32);
1442 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1443 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1444 MemOps.push_back(Store);
1445 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1446 DAG.getIntPtrConstant(16));
1448 if (!MemOps.empty())
1449 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1450 &MemOps[0], MemOps.size());
1454 ArgValues.push_back(Root);
1456 // Some CCs need callee pop.
1457 if (IsCalleePop(isVarArg, CC)) {
1458 BytesToPopOnReturn = StackSize; // Callee pops everything.
1459 BytesCallerReserves = 0;
1461 BytesToPopOnReturn = 0; // Callee pops nothing.
1462 // If this is an sret function, the return should pop the hidden pointer.
1463 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
1464 BytesToPopOnReturn = 4;
1465 BytesCallerReserves = StackSize;
1469 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1470 if (CC == CallingConv::X86_FastCall)
1471 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1474 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1476 // Return the new list of results.
1477 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1478 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1482 X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
1483 const SDValue &StackPtr,
1484 const CCValAssign &VA,
1486 SDValue Arg, ISD::ArgFlagsTy Flags) {
1487 DebugLoc dl = TheCall->getDebugLoc();
1488 unsigned LocMemOffset = VA.getLocMemOffset();
1489 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1490 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1491 if (Flags.isByVal()) {
1492 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1494 return DAG.getStore(Chain, dl, Arg, PtrOff,
1495 PseudoSourceValue::getStack(), LocMemOffset);
1498 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1499 /// optimization is performed and it is required.
1501 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1502 SDValue &OutRetAddr,
1508 if (!IsTailCall || FPDiff==0) return Chain;
1510 // Adjust the Return address stack slot.
1511 MVT VT = getPointerTy();
1512 OutRetAddr = getReturnAddressFrameIndex(DAG);
1514 // Load the "old" Return address.
1515 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1516 return SDValue(OutRetAddr.getNode(), 1);
1519 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1520 /// optimization is performed and it is required (FPDiff!=0).
1522 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1523 SDValue Chain, SDValue RetAddrFrIdx,
1524 bool Is64Bit, int FPDiff, DebugLoc dl) {
1525 // Store the return address to the appropriate stack slot.
1526 if (!FPDiff) return Chain;
1527 // Calculate the new stack slot for the return address.
1528 int SlotSize = Is64Bit ? 8 : 4;
1529 int NewReturnAddrFI =
1530 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1531 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1532 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1533 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1534 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1538 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1539 MachineFunction &MF = DAG.getMachineFunction();
1540 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1541 SDValue Chain = TheCall->getChain();
1542 unsigned CC = TheCall->getCallingConv();
1543 bool isVarArg = TheCall->isVarArg();
1544 bool IsTailCall = TheCall->isTailCall() &&
1545 CC == CallingConv::Fast && PerformTailCallOpt;
1546 SDValue Callee = TheCall->getCallee();
1547 bool Is64Bit = Subtarget->is64Bit();
1548 bool IsStructRet = CallIsStructReturn(TheCall);
1549 DebugLoc dl = TheCall->getDebugLoc();
1551 assert(!(isVarArg && CC == CallingConv::Fast) &&
1552 "Var args not supported with calling convention fastcc");
1554 // Analyze operands of the call, assigning locations to each operand.
1555 SmallVector<CCValAssign, 16> ArgLocs;
1556 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1557 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
1559 // Get a count of how many bytes are to be pushed on the stack.
1560 unsigned NumBytes = CCInfo.getNextStackOffset();
1561 if (PerformTailCallOpt && CC == CallingConv::Fast)
1562 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1566 // Lower arguments at fp - stackoffset + fpdiff.
1567 unsigned NumBytesCallerPushed =
1568 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1569 FPDiff = NumBytesCallerPushed - NumBytes;
1571 // Set the delta of movement of the returnaddr stackslot.
1572 // But only set if delta is greater than previous delta.
1573 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1574 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1577 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1579 SDValue RetAddrFrIdx;
1580 // Load return adress for tail calls.
1581 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1584 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1585 SmallVector<SDValue, 8> MemOpChains;
1588 // Walk the register/memloc assignments, inserting copies/loads. In the case
1589 // of tail call optimization arguments are handle later.
1590 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1591 CCValAssign &VA = ArgLocs[i];
1592 SDValue Arg = TheCall->getArg(i);
1593 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1594 bool isByVal = Flags.isByVal();
1596 // Promote the value if needed.
1597 switch (VA.getLocInfo()) {
1598 default: assert(0 && "Unknown loc info!");
1599 case CCValAssign::Full: break;
1600 case CCValAssign::SExt:
1601 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1603 case CCValAssign::ZExt:
1604 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1606 case CCValAssign::AExt:
1607 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1611 if (VA.isRegLoc()) {
1613 MVT RegVT = VA.getLocVT();
1614 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1615 switch (VA.getLocReg()) {
1618 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1620 // Special case: passing MMX values in GPR registers.
1621 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1624 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1625 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1626 // Special case: passing MMX values in XMM registers.
1627 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1628 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1629 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64,
1630 DAG.getUNDEF(MVT::v2i64), Arg,
1631 getMOVLMask(2, DAG, dl));
1636 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1638 if (!IsTailCall || (IsTailCall && isByVal)) {
1639 assert(VA.isMemLoc());
1640 if (StackPtr.getNode() == 0)
1641 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1643 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1644 Chain, Arg, Flags));
1649 if (!MemOpChains.empty())
1650 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1651 &MemOpChains[0], MemOpChains.size());
1653 // Build a sequence of copy-to-reg nodes chained together with token chain
1654 // and flag operands which copy the outgoing args into registers.
1656 // Tail call byval lowering might overwrite argument registers so in case of
1657 // tail call optimization the copies to registers are lowered later.
1659 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1660 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1661 RegsToPass[i].second, InFlag);
1662 InFlag = Chain.getValue(1);
1665 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1667 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1668 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1669 DAG.getNode(X86ISD::GlobalBaseReg,
1670 DebugLoc::getUnknownLoc(),
1673 InFlag = Chain.getValue(1);
1675 // If we are tail calling and generating PIC/GOT style code load the address
1676 // of the callee into ecx. The value in ecx is used as target of the tail
1677 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1678 // calls on PIC/GOT architectures. Normally we would just put the address of
1679 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1680 // restored (since ebx is callee saved) before jumping to the target@PLT.
1681 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1682 // Note: The actual moving to ecx is done further down.
1683 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1684 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1685 !G->getGlobal()->hasProtectedVisibility())
1686 Callee = LowerGlobalAddress(Callee, DAG);
1687 else if (isa<ExternalSymbolSDNode>(Callee))
1688 Callee = LowerExternalSymbol(Callee,DAG);
1691 if (Is64Bit && isVarArg) {
1692 // From AMD64 ABI document:
1693 // For calls that may call functions that use varargs or stdargs
1694 // (prototype-less calls or calls to functions containing ellipsis (...) in
1695 // the declaration) %al is used as hidden argument to specify the number
1696 // of SSE registers used. The contents of %al do not need to match exactly
1697 // the number of registers, but must be an ubound on the number of SSE
1698 // registers used and is in the range 0 - 8 inclusive.
1700 // FIXME: Verify this on Win64
1701 // Count the number of XMM registers allocated.
1702 static const unsigned XMMArgRegs[] = {
1703 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1704 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1706 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1707 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1708 && "SSE registers cannot be used when SSE is disabled");
1710 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1711 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1712 InFlag = Chain.getValue(1);
1716 // For tail calls lower the arguments to the 'real' stack slot.
1718 SmallVector<SDValue, 8> MemOpChains2;
1721 // Do not flag preceeding copytoreg stuff together with the following stuff.
1723 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1724 CCValAssign &VA = ArgLocs[i];
1725 if (!VA.isRegLoc()) {
1726 assert(VA.isMemLoc());
1727 SDValue Arg = TheCall->getArg(i);
1728 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1729 // Create frame index.
1730 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1731 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1732 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1733 FIN = DAG.getFrameIndex(FI, getPointerTy());
1735 if (Flags.isByVal()) {
1736 // Copy relative to framepointer.
1737 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1738 if (StackPtr.getNode() == 0)
1739 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1741 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1743 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1746 // Store relative to framepointer.
1747 MemOpChains2.push_back(
1748 DAG.getStore(Chain, dl, Arg, FIN,
1749 PseudoSourceValue::getFixedStack(FI), 0));
1754 if (!MemOpChains2.empty())
1755 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1756 &MemOpChains2[0], MemOpChains2.size());
1758 // Copy arguments to their registers.
1759 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1760 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1761 RegsToPass[i].second, InFlag);
1762 InFlag = Chain.getValue(1);
1766 // Store the return address to the appropriate stack slot.
1767 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1771 // If the callee is a GlobalAddress node (quite common, every direct call is)
1772 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1773 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1774 // We should use extra load for direct calls to dllimported functions in
1776 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1777 getTargetMachine(), true))
1778 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(),
1780 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1781 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1782 } else if (IsTailCall) {
1783 unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
1785 Chain = DAG.getCopyToReg(Chain, dl,
1786 DAG.getRegister(Opc, getPointerTy()),
1788 Callee = DAG.getRegister(Opc, getPointerTy());
1789 // Add register as live out.
1790 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1793 // Returns a chain & a flag for retval copy to use.
1794 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1795 SmallVector<SDValue, 8> Ops;
1798 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1799 DAG.getIntPtrConstant(0, true), InFlag);
1800 InFlag = Chain.getValue(1);
1802 // Returns a chain & a flag for retval copy to use.
1803 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1807 Ops.push_back(Chain);
1808 Ops.push_back(Callee);
1811 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1813 // Add argument registers to the end of the list so that they are known live
1815 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1816 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1817 RegsToPass[i].second.getValueType()));
1819 // Add an implicit use GOT pointer in EBX.
1820 if (!IsTailCall && !Is64Bit &&
1821 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1822 Subtarget->isPICStyleGOT())
1823 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1825 // Add an implicit use of AL for x86 vararg functions.
1826 if (Is64Bit && isVarArg)
1827 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1829 if (InFlag.getNode())
1830 Ops.push_back(InFlag);
1833 assert(InFlag.getNode() &&
1834 "Flag must be set. Depend on flag being set in LowerRET");
1835 Chain = DAG.getNode(X86ISD::TAILCALL, dl,
1836 TheCall->getVTList(), &Ops[0], Ops.size());
1838 return SDValue(Chain.getNode(), Op.getResNo());
1841 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
1842 InFlag = Chain.getValue(1);
1844 // Create the CALLSEQ_END node.
1845 unsigned NumBytesForCalleeToPush;
1846 if (IsCalleePop(isVarArg, CC))
1847 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1848 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
1849 // If this is is a call to a struct-return function, the callee
1850 // pops the hidden struct pointer, so we have to push it back.
1851 // This is common for Darwin/X86, Linux & Mingw32 targets.
1852 NumBytesForCalleeToPush = 4;
1854 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1856 // Returns a flag for retval copy to use.
1857 Chain = DAG.getCALLSEQ_END(Chain,
1858 DAG.getIntPtrConstant(NumBytes, true),
1859 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
1862 InFlag = Chain.getValue(1);
1864 // Handle result values, copying them out of physregs into vregs that we
1866 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
1871 //===----------------------------------------------------------------------===//
1872 // Fast Calling Convention (tail call) implementation
1873 //===----------------------------------------------------------------------===//
1875 // Like std call, callee cleans arguments, convention except that ECX is
1876 // reserved for storing the tail called function address. Only 2 registers are
1877 // free for argument passing (inreg). Tail call optimization is performed
1879 // * tailcallopt is enabled
1880 // * caller/callee are fastcc
1881 // On X86_64 architecture with GOT-style position independent code only local
1882 // (within module) calls are supported at the moment.
1883 // To keep the stack aligned according to platform abi the function
1884 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1885 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1886 // If a tail called function callee has more arguments than the caller the
1887 // caller needs to make sure that there is room to move the RETADDR to. This is
1888 // achieved by reserving an area the size of the argument delta right after the
1889 // original REtADDR, but before the saved framepointer or the spilled registers
1890 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1902 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1903 /// for a 16 byte align requirement.
1904 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1905 SelectionDAG& DAG) {
1906 MachineFunction &MF = DAG.getMachineFunction();
1907 const TargetMachine &TM = MF.getTarget();
1908 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1909 unsigned StackAlignment = TFI.getStackAlignment();
1910 uint64_t AlignMask = StackAlignment - 1;
1911 int64_t Offset = StackSize;
1912 uint64_t SlotSize = TD->getPointerSize();
1913 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1914 // Number smaller than 12 so just add the difference.
1915 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1917 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1918 Offset = ((~AlignMask) & Offset) + StackAlignment +
1919 (StackAlignment-SlotSize);
1924 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1925 /// following the call is a return. A function is eligible if caller/callee
1926 /// calling conventions match, currently only fastcc supports tail calls, and
1927 /// the function CALL is immediatly followed by a RET.
1928 bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1930 SelectionDAG& DAG) const {
1931 if (!PerformTailCallOpt)
1934 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1935 MachineFunction &MF = DAG.getMachineFunction();
1936 unsigned CallerCC = MF.getFunction()->getCallingConv();
1937 unsigned CalleeCC= TheCall->getCallingConv();
1938 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1939 SDValue Callee = TheCall->getCallee();
1940 // On x86/32Bit PIC/GOT tail calls are supported.
1941 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1942 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1945 // Can only do local tail calls (in same module, hidden or protected) on
1946 // x86_64 PIC/GOT at the moment.
1947 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1948 return G->getGlobal()->hasHiddenVisibility()
1949 || G->getGlobal()->hasProtectedVisibility();
1957 X86TargetLowering::createFastISel(MachineFunction &mf,
1958 MachineModuleInfo *mmo,
1960 DenseMap<const Value *, unsigned> &vm,
1961 DenseMap<const BasicBlock *,
1962 MachineBasicBlock *> &bm,
1963 DenseMap<const AllocaInst *, int> &am
1965 , SmallSet<Instruction*, 8> &cil
1968 return X86::createFastISel(mf, mmo, dw, vm, bm, am
1976 //===----------------------------------------------------------------------===//
1977 // Other Lowering Hooks
1978 //===----------------------------------------------------------------------===//
1981 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1982 MachineFunction &MF = DAG.getMachineFunction();
1983 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1984 int ReturnAddrIndex = FuncInfo->getRAIndex();
1986 if (ReturnAddrIndex == 0) {
1987 // Set up a frame object for the return address.
1988 uint64_t SlotSize = TD->getPointerSize();
1989 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
1990 FuncInfo->setRAIndex(ReturnAddrIndex);
1993 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1997 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
1998 /// specific condition code, returning the condition code and the LHS/RHS of the
1999 /// comparison to make.
2000 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2001 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2003 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2004 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2005 // X > -1 -> X == 0, jump !sign.
2006 RHS = DAG.getConstant(0, RHS.getValueType());
2007 return X86::COND_NS;
2008 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2009 // X < 0 -> X == 0, jump on sign.
2011 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2013 RHS = DAG.getConstant(0, RHS.getValueType());
2014 return X86::COND_LE;
2018 switch (SetCCOpcode) {
2019 default: assert(0 && "Invalid integer condition!");
2020 case ISD::SETEQ: return X86::COND_E;
2021 case ISD::SETGT: return X86::COND_G;
2022 case ISD::SETGE: return X86::COND_GE;
2023 case ISD::SETLT: return X86::COND_L;
2024 case ISD::SETLE: return X86::COND_LE;
2025 case ISD::SETNE: return X86::COND_NE;
2026 case ISD::SETULT: return X86::COND_B;
2027 case ISD::SETUGT: return X86::COND_A;
2028 case ISD::SETULE: return X86::COND_BE;
2029 case ISD::SETUGE: return X86::COND_AE;
2033 // First determine if it is required or is profitable to flip the operands.
2035 // If LHS is a foldable load, but RHS is not, flip the condition.
2036 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2037 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2038 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2039 std::swap(LHS, RHS);
2042 switch (SetCCOpcode) {
2048 std::swap(LHS, RHS);
2052 // On a floating point condition, the flags are set as follows:
2054 // 0 | 0 | 0 | X > Y
2055 // 0 | 0 | 1 | X < Y
2056 // 1 | 0 | 0 | X == Y
2057 // 1 | 1 | 1 | unordered
2058 switch (SetCCOpcode) {
2059 default: assert(0 && "Condcode should be pre-legalized away");
2061 case ISD::SETEQ: return X86::COND_E;
2062 case ISD::SETOLT: // flipped
2064 case ISD::SETGT: return X86::COND_A;
2065 case ISD::SETOLE: // flipped
2067 case ISD::SETGE: return X86::COND_AE;
2068 case ISD::SETUGT: // flipped
2070 case ISD::SETLT: return X86::COND_B;
2071 case ISD::SETUGE: // flipped
2073 case ISD::SETLE: return X86::COND_BE;
2075 case ISD::SETNE: return X86::COND_NE;
2076 case ISD::SETUO: return X86::COND_P;
2077 case ISD::SETO: return X86::COND_NP;
2081 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2082 /// code. Current x86 isa includes the following FP cmov instructions:
2083 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2084 static bool hasFPCMov(unsigned X86CC) {
2100 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2101 /// true if Op is undef or if its value falls within the specified range (L, H].
2102 static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
2103 if (Op.getOpcode() == ISD::UNDEF)
2106 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue();
2107 return (Val >= Low && Val < Hi);
2110 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2111 /// true if Op is undef or if its value equal to the specified value.
2112 static bool isUndefOrEqual(SDValue Op, unsigned Val) {
2113 if (Op.getOpcode() == ISD::UNDEF)
2115 return cast<ConstantSDNode>(Op)->getZExtValue() == Val;
2118 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2119 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2120 bool X86::isPSHUFDMask(SDNode *N) {
2121 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2123 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2126 // Check if the value doesn't reference the second vector.
2127 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2128 SDValue Arg = N->getOperand(i);
2129 if (Arg.getOpcode() == ISD::UNDEF) continue;
2130 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2131 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e)
2138 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2139 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2140 bool X86::isPSHUFHWMask(SDNode *N) {
2141 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2143 if (N->getNumOperands() != 8)
2146 // Lower quadword copied in order.
2147 for (unsigned i = 0; i != 4; ++i) {
2148 SDValue Arg = N->getOperand(i);
2149 if (Arg.getOpcode() == ISD::UNDEF) continue;
2150 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2151 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i)
2155 // Upper quadword shuffled.
2156 for (unsigned i = 4; i != 8; ++i) {
2157 SDValue Arg = N->getOperand(i);
2158 if (Arg.getOpcode() == ISD::UNDEF) continue;
2159 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2160 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2161 if (Val < 4 || Val > 7)
2168 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2169 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2170 bool X86::isPSHUFLWMask(SDNode *N) {
2171 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2173 if (N->getNumOperands() != 8)
2176 // Upper quadword copied in order.
2177 for (unsigned i = 4; i != 8; ++i)
2178 if (!isUndefOrEqual(N->getOperand(i), i))
2181 // Lower quadword shuffled.
2182 for (unsigned i = 0; i != 4; ++i)
2183 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2189 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2190 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2191 template<class SDOperand>
2192 static bool isSHUFPMask(SDOperand *Elems, unsigned NumElems) {
2193 if (NumElems != 2 && NumElems != 4) return false;
2195 unsigned Half = NumElems / 2;
2196 for (unsigned i = 0; i < Half; ++i)
2197 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2199 for (unsigned i = Half; i < NumElems; ++i)
2200 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2206 bool X86::isSHUFPMask(SDNode *N) {
2207 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2208 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2211 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2212 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2213 /// half elements to come from vector 1 (which would equal the dest.) and
2214 /// the upper half to come from vector 2.
2215 template<class SDOperand>
2216 static bool isCommutedSHUFP(SDOperand *Ops, unsigned NumOps) {
2217 if (NumOps != 2 && NumOps != 4) return false;
2219 unsigned Half = NumOps / 2;
2220 for (unsigned i = 0; i < Half; ++i)
2221 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2223 for (unsigned i = Half; i < NumOps; ++i)
2224 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2229 static bool isCommutedSHUFP(SDNode *N) {
2230 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2231 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2234 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2235 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2236 bool X86::isMOVHLPSMask(SDNode *N) {
2237 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2239 if (N->getNumOperands() != 4)
2242 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2243 return isUndefOrEqual(N->getOperand(0), 6) &&
2244 isUndefOrEqual(N->getOperand(1), 7) &&
2245 isUndefOrEqual(N->getOperand(2), 2) &&
2246 isUndefOrEqual(N->getOperand(3), 3);
2249 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2250 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2252 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2253 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2255 if (N->getNumOperands() != 4)
2258 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2259 return isUndefOrEqual(N->getOperand(0), 2) &&
2260 isUndefOrEqual(N->getOperand(1), 3) &&
2261 isUndefOrEqual(N->getOperand(2), 2) &&
2262 isUndefOrEqual(N->getOperand(3), 3);
2265 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2266 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2267 bool X86::isMOVLPMask(SDNode *N) {
2268 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2270 unsigned NumElems = N->getNumOperands();
2271 if (NumElems != 2 && NumElems != 4)
2274 for (unsigned i = 0; i < NumElems/2; ++i)
2275 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2278 for (unsigned i = NumElems/2; i < NumElems; ++i)
2279 if (!isUndefOrEqual(N->getOperand(i), i))
2285 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2286 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2288 bool X86::isMOVHPMask(SDNode *N) {
2289 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2291 unsigned NumElems = N->getNumOperands();
2292 if (NumElems != 2 && NumElems != 4)
2295 for (unsigned i = 0; i < NumElems/2; ++i)
2296 if (!isUndefOrEqual(N->getOperand(i), i))
2299 for (unsigned i = 0; i < NumElems/2; ++i) {
2300 SDValue Arg = N->getOperand(i + NumElems/2);
2301 if (!isUndefOrEqual(Arg, i + NumElems))
2308 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2309 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2310 template<class SDOperand>
2311 bool static isUNPCKLMask(SDOperand *Elts, unsigned NumElts,
2312 bool V2IsSplat = false) {
2313 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2316 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2317 SDValue BitI = Elts[i];
2318 SDValue BitI1 = Elts[i+1];
2319 if (!isUndefOrEqual(BitI, j))
2322 if (!isUndefOrEqual(BitI1, NumElts))
2325 if (!isUndefOrEqual(BitI1, j + NumElts))
2333 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2334 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2335 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2338 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2339 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2340 template<class SDOperand>
2341 bool static isUNPCKHMask(SDOperand *Elts, unsigned NumElts,
2342 bool V2IsSplat = false) {
2343 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2346 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2347 SDValue BitI = Elts[i];
2348 SDValue BitI1 = Elts[i+1];
2349 if (!isUndefOrEqual(BitI, j + NumElts/2))
2352 if (isUndefOrEqual(BitI1, NumElts))
2355 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2363 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2364 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2365 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2368 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2369 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2371 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2372 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2374 unsigned NumElems = N->getNumOperands();
2375 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2378 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2379 SDValue BitI = N->getOperand(i);
2380 SDValue BitI1 = N->getOperand(i+1);
2382 if (!isUndefOrEqual(BitI, j))
2384 if (!isUndefOrEqual(BitI1, j))
2391 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2392 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2394 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2395 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2397 unsigned NumElems = N->getNumOperands();
2398 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2401 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2402 SDValue BitI = N->getOperand(i);
2403 SDValue BitI1 = N->getOperand(i + 1);
2405 if (!isUndefOrEqual(BitI, j))
2407 if (!isUndefOrEqual(BitI1, j))
2414 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2415 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2416 /// MOVSD, and MOVD, i.e. setting the lowest element.
2417 template<class SDOperand>
2418 static bool isMOVLMask(SDOperand *Elts, unsigned NumElts) {
2419 if (NumElts != 2 && NumElts != 4)
2422 if (!isUndefOrEqual(Elts[0], NumElts))
2425 for (unsigned i = 1; i < NumElts; ++i) {
2426 if (!isUndefOrEqual(Elts[i], i))
2433 bool X86::isMOVLMask(SDNode *N) {
2434 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2435 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2438 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2439 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2440 /// element of vector 2 and the other elements to come from vector 1 in order.
2441 template<class SDOperand>
2442 static bool isCommutedMOVL(SDOperand *Ops, unsigned NumOps,
2443 bool V2IsSplat = false,
2444 bool V2IsUndef = false) {
2445 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2448 if (!isUndefOrEqual(Ops[0], 0))
2451 for (unsigned i = 1; i < NumOps; ++i) {
2452 SDValue Arg = Ops[i];
2453 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2454 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2455 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2462 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2463 bool V2IsUndef = false) {
2464 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2465 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2466 V2IsSplat, V2IsUndef);
2469 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2470 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2471 bool X86::isMOVSHDUPMask(SDNode *N) {
2472 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2474 if (N->getNumOperands() != 4)
2477 // Expect 1, 1, 3, 3
2478 for (unsigned i = 0; i < 2; ++i) {
2479 SDValue Arg = N->getOperand(i);
2480 if (Arg.getOpcode() == ISD::UNDEF) continue;
2481 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2482 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2483 if (Val != 1) return false;
2487 for (unsigned i = 2; i < 4; ++i) {
2488 SDValue Arg = N->getOperand(i);
2489 if (Arg.getOpcode() == ISD::UNDEF) continue;
2490 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2491 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2492 if (Val != 3) return false;
2496 // Don't use movshdup if it can be done with a shufps.
2500 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2501 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2502 bool X86::isMOVSLDUPMask(SDNode *N) {
2503 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2505 if (N->getNumOperands() != 4)
2508 // Expect 0, 0, 2, 2
2509 for (unsigned i = 0; i < 2; ++i) {
2510 SDValue Arg = N->getOperand(i);
2511 if (Arg.getOpcode() == ISD::UNDEF) continue;
2512 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2513 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2514 if (Val != 0) return false;
2518 for (unsigned i = 2; i < 4; ++i) {
2519 SDValue Arg = N->getOperand(i);
2520 if (Arg.getOpcode() == ISD::UNDEF) continue;
2521 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2522 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2523 if (Val != 2) return false;
2527 // Don't use movshdup if it can be done with a shufps.
2531 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2532 /// specifies a identity operation on the LHS or RHS.
2533 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2534 unsigned NumElems = N->getNumOperands();
2535 for (unsigned i = 0; i < NumElems; ++i)
2536 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2541 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2542 /// a splat of a single element.
2543 static bool isSplatMask(SDNode *N) {
2544 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2546 // This is a splat operation if each element of the permute is the same, and
2547 // if the value doesn't reference the second vector.
2548 unsigned NumElems = N->getNumOperands();
2549 SDValue ElementBase;
2551 for (; i != NumElems; ++i) {
2552 SDValue Elt = N->getOperand(i);
2553 if (isa<ConstantSDNode>(Elt)) {
2559 if (!ElementBase.getNode())
2562 for (; i != NumElems; ++i) {
2563 SDValue Arg = N->getOperand(i);
2564 if (Arg.getOpcode() == ISD::UNDEF) continue;
2565 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2566 if (Arg != ElementBase) return false;
2569 // Make sure it is a splat of the first vector operand.
2570 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems;
2573 /// getSplatMaskEltNo - Given a splat mask, return the index to the element
2574 /// we want to splat.
2575 static SDValue getSplatMaskEltNo(SDNode *N) {
2576 assert(isSplatMask(N) && "Not a splat mask");
2577 unsigned NumElems = N->getNumOperands();
2578 SDValue ElementBase;
2580 for (; i != NumElems; ++i) {
2581 SDValue Elt = N->getOperand(i);
2582 if (isa<ConstantSDNode>(Elt))
2585 assert(0 && " No splat value found!");
2590 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2591 /// a splat of a single element and it's a 2 or 4 element mask.
2592 bool X86::isSplatMask(SDNode *N) {
2593 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2595 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2596 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2598 return ::isSplatMask(N);
2601 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2602 /// specifies a splat of zero element.
2603 bool X86::isSplatLoMask(SDNode *N) {
2604 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2606 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2607 if (!isUndefOrEqual(N->getOperand(i), 0))
2612 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2613 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2614 bool X86::isMOVDDUPMask(SDNode *N) {
2615 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2617 unsigned e = N->getNumOperands() / 2;
2618 for (unsigned i = 0; i < e; ++i)
2619 if (!isUndefOrEqual(N->getOperand(i), i))
2621 for (unsigned i = 0; i < e; ++i)
2622 if (!isUndefOrEqual(N->getOperand(e+i), i))
2627 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2628 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2630 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2631 unsigned NumOperands = N->getNumOperands();
2632 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2634 for (unsigned i = 0; i < NumOperands; ++i) {
2636 SDValue Arg = N->getOperand(NumOperands-i-1);
2637 if (Arg.getOpcode() != ISD::UNDEF)
2638 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2639 if (Val >= NumOperands) Val -= NumOperands;
2641 if (i != NumOperands - 1)
2648 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2649 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2651 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2653 // 8 nodes, but we only care about the last 4.
2654 for (unsigned i = 7; i >= 4; --i) {
2656 SDValue Arg = N->getOperand(i);
2657 if (Arg.getOpcode() != ISD::UNDEF) {
2658 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2668 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2669 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2671 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2673 // 8 nodes, but we only care about the first 4.
2674 for (int i = 3; i >= 0; --i) {
2676 SDValue Arg = N->getOperand(i);
2677 if (Arg.getOpcode() != ISD::UNDEF)
2678 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2687 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2688 /// specifies a 8 element shuffle that can be broken into a pair of
2689 /// PSHUFHW and PSHUFLW.
2690 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2691 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2693 if (N->getNumOperands() != 8)
2696 // Lower quadword shuffled.
2697 for (unsigned i = 0; i != 4; ++i) {
2698 SDValue Arg = N->getOperand(i);
2699 if (Arg.getOpcode() == ISD::UNDEF) continue;
2700 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2701 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2706 // Upper quadword shuffled.
2707 for (unsigned i = 4; i != 8; ++i) {
2708 SDValue Arg = N->getOperand(i);
2709 if (Arg.getOpcode() == ISD::UNDEF) continue;
2710 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2711 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2712 if (Val < 4 || Val > 7)
2719 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2720 /// values in ther permute mask.
2721 static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
2722 SDValue &V2, SDValue &Mask,
2723 SelectionDAG &DAG) {
2724 MVT VT = Op.getValueType();
2725 MVT MaskVT = Mask.getValueType();
2726 MVT EltVT = MaskVT.getVectorElementType();
2727 unsigned NumElems = Mask.getNumOperands();
2728 SmallVector<SDValue, 8> MaskVec;
2729 DebugLoc dl = Op.getDebugLoc();
2731 for (unsigned i = 0; i != NumElems; ++i) {
2732 SDValue Arg = Mask.getOperand(i);
2733 if (Arg.getOpcode() == ISD::UNDEF) {
2734 MaskVec.push_back(DAG.getUNDEF(EltVT));
2737 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2738 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2740 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2742 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2746 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems);
2747 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask);
2750 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2751 /// the two vector operands have swapped position.
2753 SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG, DebugLoc dl) {
2754 MVT MaskVT = Mask.getValueType();
2755 MVT EltVT = MaskVT.getVectorElementType();
2756 unsigned NumElems = Mask.getNumOperands();
2757 SmallVector<SDValue, 8> MaskVec;
2758 for (unsigned i = 0; i != NumElems; ++i) {
2759 SDValue Arg = Mask.getOperand(i);
2760 if (Arg.getOpcode() == ISD::UNDEF) {
2761 MaskVec.push_back(DAG.getUNDEF(EltVT));
2764 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2765 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2767 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2769 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2771 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems);
2775 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2776 /// match movhlps. The lower half elements should come from upper half of
2777 /// V1 (and in order), and the upper half elements should come from the upper
2778 /// half of V2 (and in order).
2779 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2780 unsigned NumElems = Mask->getNumOperands();
2783 for (unsigned i = 0, e = 2; i != e; ++i)
2784 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2786 for (unsigned i = 2; i != 4; ++i)
2787 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2792 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2793 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2795 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2796 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2798 N = N->getOperand(0).getNode();
2799 if (!ISD::isNON_EXTLoad(N))
2802 *LD = cast<LoadSDNode>(N);
2806 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2807 /// match movlp{s|d}. The lower half elements should come from lower half of
2808 /// V1 (and in order), and the upper half elements should come from the upper
2809 /// half of V2 (and in order). And since V1 will become the source of the
2810 /// MOVLP, it must be either a vector load or a scalar load to vector.
2811 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2812 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2814 // Is V2 is a vector load, don't do this transformation. We will try to use
2815 // load folding shufps op.
2816 if (ISD::isNON_EXTLoad(V2))
2819 unsigned NumElems = Mask->getNumOperands();
2820 if (NumElems != 2 && NumElems != 4)
2822 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2823 if (!isUndefOrEqual(Mask->getOperand(i), i))
2825 for (unsigned i = NumElems/2; i != NumElems; ++i)
2826 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2831 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2833 static bool isSplatVector(SDNode *N) {
2834 if (N->getOpcode() != ISD::BUILD_VECTOR)
2837 SDValue SplatValue = N->getOperand(0);
2838 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2839 if (N->getOperand(i) != SplatValue)
2844 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2846 static bool isUndefShuffle(SDNode *N) {
2847 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2850 SDValue V1 = N->getOperand(0);
2851 SDValue V2 = N->getOperand(1);
2852 SDValue Mask = N->getOperand(2);
2853 unsigned NumElems = Mask.getNumOperands();
2854 for (unsigned i = 0; i != NumElems; ++i) {
2855 SDValue Arg = Mask.getOperand(i);
2856 if (Arg.getOpcode() != ISD::UNDEF) {
2857 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2858 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2860 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2867 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2869 static inline bool isZeroNode(SDValue Elt) {
2870 return ((isa<ConstantSDNode>(Elt) &&
2871 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2872 (isa<ConstantFPSDNode>(Elt) &&
2873 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2876 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2877 /// to an zero vector.
2878 static bool isZeroShuffle(SDNode *N) {
2879 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2882 SDValue V1 = N->getOperand(0);
2883 SDValue V2 = N->getOperand(1);
2884 SDValue Mask = N->getOperand(2);
2885 unsigned NumElems = Mask.getNumOperands();
2886 for (unsigned i = 0; i != NumElems; ++i) {
2887 SDValue Arg = Mask.getOperand(i);
2888 if (Arg.getOpcode() == ISD::UNDEF)
2891 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2892 if (Idx < NumElems) {
2893 unsigned Opc = V1.getNode()->getOpcode();
2894 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2896 if (Opc != ISD::BUILD_VECTOR ||
2897 !isZeroNode(V1.getNode()->getOperand(Idx)))
2899 } else if (Idx >= NumElems) {
2900 unsigned Opc = V2.getNode()->getOpcode();
2901 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2903 if (Opc != ISD::BUILD_VECTOR ||
2904 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
2911 /// getZeroVector - Returns a vector of specified type with all zero elements.
2913 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG,
2915 assert(VT.isVector() && "Expected a vector type");
2917 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2918 // type. This ensures they get CSE'd.
2920 if (VT.getSizeInBits() == 64) { // MMX
2921 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2922 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2923 } else if (HasSSE2) { // SSE2
2924 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2925 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2927 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2928 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
2930 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2933 /// getOnesVector - Returns a vector of specified type with all bits set.
2935 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
2936 assert(VT.isVector() && "Expected a vector type");
2938 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2939 // type. This ensures they get CSE'd.
2940 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2942 if (VT.getSizeInBits() == 64) // MMX
2943 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2945 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2946 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2950 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2951 /// that point to V2 points to its first element.
2952 static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
2953 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2955 bool Changed = false;
2956 SmallVector<SDValue, 8> MaskVec;
2957 unsigned NumElems = Mask.getNumOperands();
2958 for (unsigned i = 0; i != NumElems; ++i) {
2959 SDValue Arg = Mask.getOperand(i);
2960 if (Arg.getOpcode() != ISD::UNDEF) {
2961 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2962 if (Val > NumElems) {
2963 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2967 MaskVec.push_back(Arg);
2971 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(),
2972 Mask.getValueType(),
2973 &MaskVec[0], MaskVec.size());
2977 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2978 /// operation of specified width.
2979 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl) {
2980 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2981 MVT BaseVT = MaskVT.getVectorElementType();
2983 SmallVector<SDValue, 8> MaskVec;
2984 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2985 for (unsigned i = 1; i != NumElems; ++i)
2986 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2987 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
2988 &MaskVec[0], MaskVec.size());
2991 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2992 /// of specified width.
2993 static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG,
2995 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2996 MVT BaseVT = MaskVT.getVectorElementType();
2997 SmallVector<SDValue, 8> MaskVec;
2998 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2999 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3000 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
3002 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3003 &MaskVec[0], MaskVec.size());
3006 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
3007 /// of specified width.
3008 static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG,
3010 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3011 MVT BaseVT = MaskVT.getVectorElementType();
3012 unsigned Half = NumElems/2;
3013 SmallVector<SDValue, 8> MaskVec;
3014 for (unsigned i = 0; i != Half; ++i) {
3015 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
3016 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
3018 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3019 &MaskVec[0], MaskVec.size());
3022 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
3023 /// element #0 of a vector with the specified index, leaving the rest of the
3024 /// elements in place.
3025 static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
3026 SelectionDAG &DAG, DebugLoc dl) {
3027 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3028 MVT BaseVT = MaskVT.getVectorElementType();
3029 SmallVector<SDValue, 8> MaskVec;
3030 // Element #0 of the result gets the elt we are replacing.
3031 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
3032 for (unsigned i = 1; i != NumElems; ++i)
3033 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
3034 return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3035 &MaskVec[0], MaskVec.size());
3038 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3039 static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
3040 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
3041 MVT VT = Op.getValueType();
3044 SDValue V1 = Op.getOperand(0);
3045 SDValue Mask = Op.getOperand(2);
3046 unsigned MaskNumElems = Mask.getNumOperands();
3047 unsigned NumElems = MaskNumElems;
3048 DebugLoc dl = Op.getDebugLoc();
3049 // Special handling of v4f32 -> v4i32.
3050 if (VT != MVT::v4f32) {
3051 // Find which element we want to splat.
3052 SDNode* EltNoNode = getSplatMaskEltNo(Mask.getNode()).getNode();
3053 unsigned EltNo = cast<ConstantSDNode>(EltNoNode)->getZExtValue();
3054 // unpack elements to the correct location
3055 while (NumElems > 4) {
3056 if (EltNo < NumElems/2) {
3057 Mask = getUnpacklMask(MaskNumElems, DAG, dl);
3059 Mask = getUnpackhMask(MaskNumElems, DAG, dl);
3060 EltNo -= NumElems/2;
3062 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1, Mask);
3065 SDValue Cst = DAG.getConstant(EltNo, MVT::i32);
3066 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3069 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3070 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1,
3071 DAG.getUNDEF(PVT), Mask);
3072 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle);
3075 /// isVectorLoad - Returns true if the node is a vector load, a scalar
3076 /// load that's promoted to vector, or a load bitcasted.
3077 static bool isVectorLoad(SDValue Op) {
3078 assert(Op.getValueType().isVector() && "Expected a vector type");
3079 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR ||
3080 Op.getOpcode() == ISD::BIT_CONVERT) {
3081 return isa<LoadSDNode>(Op.getOperand(0));
3083 return isa<LoadSDNode>(Op);
3087 /// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
3089 static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask,
3090 SelectionDAG &DAG, bool HasSSE3) {
3091 // If we have sse3 and shuffle has more than one use or input is a load, then
3092 // use movddup. Otherwise, use movlhps.
3093 bool UseMovddup = HasSSE3 && (!Op.hasOneUse() || isVectorLoad(V1));
3094 MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32;
3095 MVT VT = Op.getValueType();
3098 DebugLoc dl = Op.getDebugLoc();
3099 unsigned NumElems = PVT.getVectorNumElements();
3100 if (NumElems == 2) {
3101 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3102 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3104 assert(NumElems == 4);
3105 SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32);
3106 SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32);
3107 Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
3108 Cst0, Cst1, Cst0, Cst1);
3111 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3112 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, PVT, V1,
3113 DAG.getUNDEF(PVT), Mask);
3114 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuffle);
3117 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3118 /// vector of zero or undef vector. This produces a shuffle where the low
3119 /// element of V2 is swizzled into the zero/undef vector, landing at element
3120 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3121 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3122 bool isZero, bool HasSSE2,
3123 SelectionDAG &DAG) {
3124 DebugLoc dl = V2.getDebugLoc();
3125 MVT VT = V2.getValueType();
3127 ? getZeroVector(VT, HasSSE2, DAG, dl) : DAG.getUNDEF(VT);
3128 unsigned NumElems = V2.getValueType().getVectorNumElements();
3129 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3130 MVT EVT = MaskVT.getVectorElementType();
3131 SmallVector<SDValue, 16> MaskVec;
3132 for (unsigned i = 0; i != NumElems; ++i)
3133 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
3134 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
3136 MaskVec.push_back(DAG.getConstant(i, EVT));
3137 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3138 &MaskVec[0], MaskVec.size());
3139 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask);
3142 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3143 /// a shuffle that is zero.
3145 unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
3146 unsigned NumElems, bool Low,
3147 SelectionDAG &DAG) {
3148 unsigned NumZeros = 0;
3149 for (unsigned i = 0; i < NumElems; ++i) {
3150 unsigned Index = Low ? i : NumElems-i-1;
3151 SDValue Idx = Mask.getOperand(Index);
3152 if (Idx.getOpcode() == ISD::UNDEF) {
3156 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
3157 if (Elt.getNode() && isZeroNode(Elt))
3165 /// isVectorShift - Returns true if the shuffle can be implemented as a
3166 /// logical left or right shift of a vector.
3167 static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
3168 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3169 unsigned NumElems = Mask.getNumOperands();
3172 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
3175 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
3180 bool SeenV1 = false;
3181 bool SeenV2 = false;
3182 for (unsigned i = NumZeros; i < NumElems; ++i) {
3183 unsigned Val = isLeft ? (i - NumZeros) : i;
3184 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
3185 if (Idx.getOpcode() == ISD::UNDEF)
3187 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
3188 if (Index < NumElems)
3197 if (SeenV1 && SeenV2)
3200 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
3206 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3208 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3209 unsigned NumNonZero, unsigned NumZero,
3210 SelectionDAG &DAG, TargetLowering &TLI) {
3214 DebugLoc dl = Op.getDebugLoc();
3217 for (unsigned i = 0; i < 16; ++i) {
3218 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3219 if (ThisIsNonZero && First) {
3221 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3223 V = DAG.getUNDEF(MVT::v8i16);
3228 SDValue ThisElt(0, 0), LastElt(0, 0);
3229 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3230 if (LastIsNonZero) {
3231 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3232 MVT::i16, Op.getOperand(i-1));
3234 if (ThisIsNonZero) {
3235 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3236 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3237 ThisElt, DAG.getConstant(8, MVT::i8));
3239 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3243 if (ThisElt.getNode())
3244 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3245 DAG.getIntPtrConstant(i/2));
3249 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3252 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3254 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3255 unsigned NumNonZero, unsigned NumZero,
3256 SelectionDAG &DAG, TargetLowering &TLI) {
3260 DebugLoc dl = Op.getDebugLoc();
3263 for (unsigned i = 0; i < 8; ++i) {
3264 bool isNonZero = (NonZeros & (1 << i)) != 0;
3268 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3270 V = DAG.getUNDEF(MVT::v8i16);
3273 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3274 MVT::v8i16, V, Op.getOperand(i),
3275 DAG.getIntPtrConstant(i));
3282 /// getVShift - Return a vector logical shift node.
3284 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3285 unsigned NumBits, SelectionDAG &DAG,
3286 const TargetLowering &TLI, DebugLoc dl) {
3287 bool isMMX = VT.getSizeInBits() == 64;
3288 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3289 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3290 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3291 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3292 DAG.getNode(Opc, dl, ShVT, SrcOp,
3293 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3297 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3298 DebugLoc dl = Op.getDebugLoc();
3299 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3300 if (ISD::isBuildVectorAllZeros(Op.getNode())
3301 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3302 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3303 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3304 // eliminated on x86-32 hosts.
3305 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3308 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3309 return getOnesVector(Op.getValueType(), DAG, dl);
3310 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3313 MVT VT = Op.getValueType();
3314 MVT EVT = VT.getVectorElementType();
3315 unsigned EVTBits = EVT.getSizeInBits();
3317 unsigned NumElems = Op.getNumOperands();
3318 unsigned NumZero = 0;
3319 unsigned NumNonZero = 0;
3320 unsigned NonZeros = 0;
3321 bool IsAllConstants = true;
3322 SmallSet<SDValue, 8> Values;
3323 for (unsigned i = 0; i < NumElems; ++i) {
3324 SDValue Elt = Op.getOperand(i);
3325 if (Elt.getOpcode() == ISD::UNDEF)
3328 if (Elt.getOpcode() != ISD::Constant &&
3329 Elt.getOpcode() != ISD::ConstantFP)
3330 IsAllConstants = false;
3331 if (isZeroNode(Elt))
3334 NonZeros |= (1 << i);
3339 if (NumNonZero == 0) {
3340 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3341 return DAG.getUNDEF(VT);
3344 // Special case for single non-zero, non-undef, element.
3345 if (NumNonZero == 1 && NumElems <= 4) {
3346 unsigned Idx = CountTrailingZeros_32(NonZeros);
3347 SDValue Item = Op.getOperand(Idx);
3349 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3350 // the value are obviously zero, truncate the value to i32 and do the
3351 // insertion that way. Only do this if the value is non-constant or if the
3352 // value is a constant being inserted into element 0. It is cheaper to do
3353 // a constant pool load than it is to do a movd + shuffle.
3354 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3355 (!IsAllConstants || Idx == 0)) {
3356 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3357 // Handle MMX and SSE both.
3358 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3359 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3361 // Truncate the value (which may itself be a constant) to i32, and
3362 // convert it to a vector with movd (S2V+shuffle to zero extend).
3363 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3364 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3365 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3366 Subtarget->hasSSE2(), DAG);
3368 // Now we have our 32-bit value zero extended in the low element of
3369 // a vector. If Idx != 0, swizzle it into place.
3372 Item, DAG.getUNDEF(Item.getValueType()),
3373 getSwapEltZeroMask(VecElts, Idx, DAG, dl)
3375 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VecVT, Ops, 3);
3377 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3381 // If we have a constant or non-constant insertion into the low element of
3382 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3383 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3384 // depending on what the source datatype is. Because we can only get here
3385 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3387 // Don't do this for i64 values on x86-32.
3388 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3389 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3390 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3391 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3392 Subtarget->hasSSE2(), DAG);
3395 // Is it a vector logical left shift?
3396 if (NumElems == 2 && Idx == 1 &&
3397 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3398 unsigned NumBits = VT.getSizeInBits();
3399 return getVShift(true, VT,
3400 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3401 VT, Op.getOperand(1)),
3402 NumBits/2, DAG, *this, dl);
3405 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3408 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3409 // is a non-constant being inserted into an element other than the low one,
3410 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3411 // movd/movss) to move this into the low element, then shuffle it into
3413 if (EVTBits == 32) {
3414 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3416 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3417 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3418 Subtarget->hasSSE2(), DAG);
3419 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3420 MVT MaskEVT = MaskVT.getVectorElementType();
3421 SmallVector<SDValue, 8> MaskVec;
3422 for (unsigned i = 0; i < NumElems; i++)
3423 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3424 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3425 &MaskVec[0], MaskVec.size());
3426 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, Item,
3427 DAG.getUNDEF(VT), Mask);
3431 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3432 if (Values.size() == 1)
3435 // A vector full of immediates; various special cases are already
3436 // handled, so this is best done with a single constant-pool load.
3440 // Let legalizer expand 2-wide build_vectors.
3441 if (EVTBits == 64) {
3442 if (NumNonZero == 1) {
3443 // One half is zero or undef.
3444 unsigned Idx = CountTrailingZeros_32(NonZeros);
3445 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3446 Op.getOperand(Idx));
3447 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3448 Subtarget->hasSSE2(), DAG);
3453 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3454 if (EVTBits == 8 && NumElems == 16) {
3455 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3457 if (V.getNode()) return V;
3460 if (EVTBits == 16 && NumElems == 8) {
3461 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3463 if (V.getNode()) return V;
3466 // If element VT is == 32 bits, turn it into a number of shuffles.
3467 SmallVector<SDValue, 8> V;
3469 if (NumElems == 4 && NumZero > 0) {
3470 for (unsigned i = 0; i < 4; ++i) {
3471 bool isZero = !(NonZeros & (1 << i));
3473 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3475 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3478 for (unsigned i = 0; i < 2; ++i) {
3479 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3482 V[i] = V[i*2]; // Must be a zero vector.
3485 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2+1], V[i*2],
3486 getMOVLMask(NumElems, DAG, dl));
3489 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1],
3490 getMOVLMask(NumElems, DAG, dl));
3493 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i*2], V[i*2+1],
3494 getUnpacklMask(NumElems, DAG, dl));
3499 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3500 MVT EVT = MaskVT.getVectorElementType();
3501 SmallVector<SDValue, 8> MaskVec;
3502 bool Reverse = (NonZeros & 0x3) == 2;
3503 for (unsigned i = 0; i < 2; ++i)
3505 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3507 MaskVec.push_back(DAG.getConstant(i, EVT));
3508 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3509 for (unsigned i = 0; i < 2; ++i)
3511 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3513 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3514 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3515 &MaskVec[0], MaskVec.size());
3516 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[0], V[1], ShufMask);
3519 if (Values.size() > 2) {
3520 // Expand into a number of unpckl*.
3522 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3523 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3524 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3525 SDValue UnpckMask = getUnpacklMask(NumElems, DAG, dl);
3526 for (unsigned i = 0; i < NumElems; ++i)
3527 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3529 while (NumElems != 0) {
3530 for (unsigned i = 0; i < NumElems; ++i)
3531 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[i], V[i + NumElems],
3542 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
3543 SDValue PermMask, SelectionDAG &DAG,
3544 TargetLowering &TLI, DebugLoc dl) {
3546 MVT MaskVT = MVT::getIntVectorWithNumElements(8);
3547 MVT MaskEVT = MaskVT.getVectorElementType();
3548 MVT PtrVT = TLI.getPointerTy();
3549 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
3550 PermMask.getNode()->op_end());
3552 // First record which half of which vector the low elements come from.
3553 SmallVector<unsigned, 4> LowQuad(4);
3554 for (unsigned i = 0; i < 4; ++i) {
3555 SDValue Elt = MaskElts[i];
3556 if (Elt.getOpcode() == ISD::UNDEF)
3558 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3559 int QuadIdx = EltIdx / 4;
3563 int BestLowQuad = -1;
3564 unsigned MaxQuad = 1;
3565 for (unsigned i = 0; i < 4; ++i) {
3566 if (LowQuad[i] > MaxQuad) {
3568 MaxQuad = LowQuad[i];
3572 // Record which half of which vector the high elements come from.
3573 SmallVector<unsigned, 4> HighQuad(4);
3574 for (unsigned i = 4; i < 8; ++i) {
3575 SDValue Elt = MaskElts[i];
3576 if (Elt.getOpcode() == ISD::UNDEF)
3578 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3579 int QuadIdx = EltIdx / 4;
3580 ++HighQuad[QuadIdx];
3583 int BestHighQuad = -1;
3585 for (unsigned i = 0; i < 4; ++i) {
3586 if (HighQuad[i] > MaxQuad) {
3588 MaxQuad = HighQuad[i];
3592 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3593 if (BestLowQuad != -1 || BestHighQuad != -1) {
3594 // First sort the 4 chunks in order using shufpd.
3595 SmallVector<SDValue, 8> MaskVec;
3597 if (BestLowQuad != -1)
3598 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3600 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3602 if (BestHighQuad != -1)
3603 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3605 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3607 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, &MaskVec[0],2);
3608 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64,
3609 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3610 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), Mask);
3611 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3613 // Now sort high and low parts separately.
3614 BitVector InOrder(8);
3615 if (BestLowQuad != -1) {
3616 // Sort lower half in order using PSHUFLW.
3618 bool AnyOutOrder = false;
3620 for (unsigned i = 0; i != 4; ++i) {
3621 SDValue Elt = MaskElts[i];
3622 if (Elt.getOpcode() == ISD::UNDEF) {
3623 MaskVec.push_back(Elt);
3626 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3630 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3632 // If this element is in the right place after this shuffle, then
3634 if ((int)(EltIdx / 4) == BestLowQuad)
3639 for (unsigned i = 4; i != 8; ++i)
3640 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3641 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3643 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16,
3648 if (BestHighQuad != -1) {
3649 // Sort high half in order using PSHUFHW if possible.
3652 for (unsigned i = 0; i != 4; ++i)
3653 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3655 bool AnyOutOrder = false;
3656 for (unsigned i = 4; i != 8; ++i) {
3657 SDValue Elt = MaskElts[i];
3658 if (Elt.getOpcode() == ISD::UNDEF) {
3659 MaskVec.push_back(Elt);
3662 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3666 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3668 // If this element is in the right place after this shuffle, then
3670 if ((int)(EltIdx / 4) == BestHighQuad)
3676 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl,
3677 MaskVT, &MaskVec[0], 8);
3678 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16,
3683 // The other elements are put in the right place using pextrw and pinsrw.
3684 for (unsigned i = 0; i != 8; ++i) {
3687 SDValue Elt = MaskElts[i];
3688 if (Elt.getOpcode() == ISD::UNDEF)
3690 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3691 SDValue ExtOp = (EltIdx < 8)
3692 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3693 DAG.getConstant(EltIdx, PtrVT))
3694 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3695 DAG.getConstant(EltIdx - 8, PtrVT));
3696 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3697 DAG.getConstant(i, PtrVT));
3703 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use as
3704 // few as possible. First, let's find out how many elements are already in the
3706 unsigned V1InOrder = 0;
3707 unsigned V1FromV1 = 0;
3708 unsigned V2InOrder = 0;
3709 unsigned V2FromV2 = 0;
3710 SmallVector<SDValue, 8> V1Elts;
3711 SmallVector<SDValue, 8> V2Elts;
3712 for (unsigned i = 0; i < 8; ++i) {
3713 SDValue Elt = MaskElts[i];
3714 if (Elt.getOpcode() == ISD::UNDEF) {
3715 V1Elts.push_back(Elt);
3716 V2Elts.push_back(Elt);
3721 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3723 V1Elts.push_back(Elt);
3724 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3726 } else if (EltIdx == i+8) {
3727 V1Elts.push_back(Elt);
3728 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3730 } else if (EltIdx < 8) {
3731 V1Elts.push_back(Elt);
3732 V2Elts.push_back(DAG.getConstant(EltIdx+8, MaskEVT));
3735 V1Elts.push_back(Elt);
3736 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3741 if (V2InOrder > V1InOrder) {
3742 PermMask = CommuteVectorShuffleMask(PermMask, DAG, dl);
3744 std::swap(V1Elts, V2Elts);
3745 std::swap(V1FromV1, V2FromV2);
3748 if ((V1FromV1 + V1InOrder) != 8) {
3749 // Some elements are from V2.
3751 // If there are elements that are from V1 but out of place,
3752 // then first sort them in place
3753 SmallVector<SDValue, 8> MaskVec;
3754 for (unsigned i = 0; i < 8; ++i) {
3755 SDValue Elt = V1Elts[i];
3756 if (Elt.getOpcode() == ISD::UNDEF) {
3757 MaskVec.push_back(DAG.getUNDEF(MaskEVT));
3760 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3762 MaskVec.push_back(DAG.getUNDEF(MaskEVT));
3764 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3766 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], 8);
3767 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, V1, V1, Mask);
3771 for (unsigned i = 0; i < 8; ++i) {
3772 SDValue Elt = V1Elts[i];
3773 if (Elt.getOpcode() == ISD::UNDEF)
3775 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3778 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3779 DAG.getConstant(EltIdx - 8, PtrVT));
3780 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3781 DAG.getConstant(i, PtrVT));
3785 // All elements are from V1.
3787 for (unsigned i = 0; i < 8; ++i) {
3788 SDValue Elt = V1Elts[i];
3789 if (Elt.getOpcode() == ISD::UNDEF)
3791 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3792 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3793 DAG.getConstant(EltIdx, PtrVT));
3794 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3795 DAG.getConstant(i, PtrVT));
3801 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3802 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3803 /// done when every pair / quad of shuffle mask elements point to elements in
3804 /// the right sequence. e.g.
3805 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3807 SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
3809 SDValue PermMask, SelectionDAG &DAG,
3810 TargetLowering &TLI, DebugLoc dl) {
3811 unsigned NumElems = PermMask.getNumOperands();
3812 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3813 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3814 MVT MaskEltVT = MaskVT.getVectorElementType();
3816 switch (VT.getSimpleVT()) {
3817 default: assert(false && "Unexpected!");
3818 case MVT::v4f32: NewVT = MVT::v2f64; break;
3819 case MVT::v4i32: NewVT = MVT::v2i64; break;
3820 case MVT::v8i16: NewVT = MVT::v4i32; break;
3821 case MVT::v16i8: NewVT = MVT::v4i32; break;
3824 if (NewWidth == 2) {
3830 unsigned Scale = NumElems / NewWidth;
3831 SmallVector<SDValue, 8> MaskVec;
3832 for (unsigned i = 0; i < NumElems; i += Scale) {
3833 unsigned StartIdx = ~0U;
3834 for (unsigned j = 0; j < Scale; ++j) {
3835 SDValue Elt = PermMask.getOperand(i+j);
3836 if (Elt.getOpcode() == ISD::UNDEF)
3838 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3839 if (StartIdx == ~0U)
3840 StartIdx = EltIdx - (EltIdx % Scale);
3841 if (EltIdx != StartIdx + j)
3844 if (StartIdx == ~0U)
3845 MaskVec.push_back(DAG.getUNDEF(MaskEltVT));
3847 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
3850 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
3851 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
3852 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, V1, V2,
3853 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3854 &MaskVec[0], MaskVec.size()));
3857 /// getVZextMovL - Return a zero-extending vector move low node.
3859 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3860 SDValue SrcOp, SelectionDAG &DAG,
3861 const X86Subtarget *Subtarget, DebugLoc dl) {
3862 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3863 LoadSDNode *LD = NULL;
3864 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3865 LD = dyn_cast<LoadSDNode>(SrcOp);
3867 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3869 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3870 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3871 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3872 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3873 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3875 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3876 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3877 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3878 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3886 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3887 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3888 DAG.getNode(ISD::BIT_CONVERT, dl,
3892 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3895 LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
3896 SDValue PermMask, MVT VT, SelectionDAG &DAG,
3898 MVT MaskVT = PermMask.getValueType();
3899 MVT MaskEVT = MaskVT.getVectorElementType();
3900 SmallVector<std::pair<int, int>, 8> Locs;
3902 SmallVector<SDValue, 8> Mask1(4, DAG.getUNDEF(MaskEVT));
3905 for (unsigned i = 0; i != 4; ++i) {
3906 SDValue Elt = PermMask.getOperand(i);
3907 if (Elt.getOpcode() == ISD::UNDEF) {
3908 Locs[i] = std::make_pair(-1, -1);
3910 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3911 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
3913 Locs[i] = std::make_pair(0, NumLo);
3917 Locs[i] = std::make_pair(1, NumHi);
3919 Mask1[2+NumHi] = Elt;
3925 if (NumLo <= 2 && NumHi <= 2) {
3926 // If no more than two elements come from either vector. This can be
3927 // implemented with two shuffles. First shuffle gather the elements.
3928 // The second shuffle, which takes the first shuffle as both of its
3929 // vector operands, put the elements into the right order.
3930 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
3931 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3932 &Mask1[0], Mask1.size()));
3934 SmallVector<SDValue, 8> Mask2(4, DAG.getUNDEF(MaskEVT));
3935 for (unsigned i = 0; i != 4; ++i) {
3936 if (Locs[i].first == -1)
3939 unsigned Idx = (i < 2) ? 0 : 4;
3940 Idx += Locs[i].first * 2 + Locs[i].second;
3941 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3945 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1,
3946 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
3947 &Mask2[0], Mask2.size()));
3948 } else if (NumLo == 3 || NumHi == 3) {
3949 // Otherwise, we must have three elements from one vector, call it X, and
3950 // one element from the other, call it Y. First, use a shufps to build an
3951 // intermediate vector with the one element from Y and the element from X
3952 // that will be in the same half in the final destination (the indexes don't
3953 // matter). Then, use a shufps to build the final vector, taking the half
3954 // containing the element from Y from the intermediate, and the other half
3957 // Normalize it so the 3 elements come from V1.
3958 PermMask = CommuteVectorShuffleMask(PermMask, DAG, dl);
3962 // Find the element from V2.
3964 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3965 SDValue Elt = PermMask.getOperand(HiIndex);
3966 if (Elt.getOpcode() == ISD::UNDEF)
3968 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3973 Mask1[0] = PermMask.getOperand(HiIndex);
3974 Mask1[1] = DAG.getUNDEF(MaskEVT);
3975 Mask1[2] = PermMask.getOperand(HiIndex^1);
3976 Mask1[3] = DAG.getUNDEF(MaskEVT);
3977 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
3978 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &Mask1[0], 4));
3981 Mask1[0] = PermMask.getOperand(0);
3982 Mask1[1] = PermMask.getOperand(1);
3983 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
3984 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
3985 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
3986 DAG.getNode(ISD::BUILD_VECTOR, dl,
3987 MaskVT, &Mask1[0], 4));
3989 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
3990 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
3991 Mask1[2] = PermMask.getOperand(2);
3992 Mask1[3] = PermMask.getOperand(3);
3993 if (Mask1[2].getOpcode() != ISD::UNDEF)
3995 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4,
3997 if (Mask1[3].getOpcode() != ISD::UNDEF)
3999 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
4001 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V2, V1,
4002 DAG.getNode(ISD::BUILD_VECTOR, dl,
4003 MaskVT, &Mask1[0], 4));
4007 // Break it into (shuffle shuffle_hi, shuffle_lo).
4009 SmallVector<SDValue,8> LoMask(4, DAG.getUNDEF(MaskEVT));
4010 SmallVector<SDValue,8> HiMask(4, DAG.getUNDEF(MaskEVT));
4011 SmallVector<SDValue,8> *MaskPtr = &LoMask;
4012 unsigned MaskIdx = 0;
4015 for (unsigned i = 0; i != 4; ++i) {
4022 SDValue Elt = PermMask.getOperand(i);
4023 if (Elt.getOpcode() == ISD::UNDEF) {
4024 Locs[i] = std::make_pair(-1, -1);
4025 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) {
4026 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4027 (*MaskPtr)[LoIdx] = Elt;
4030 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4031 (*MaskPtr)[HiIdx] = Elt;
4036 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
4037 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4038 &LoMask[0], LoMask.size()));
4039 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
4040 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4041 &HiMask[0], HiMask.size()));
4042 SmallVector<SDValue, 8> MaskOps;
4043 for (unsigned i = 0; i != 4; ++i) {
4044 if (Locs[i].first == -1) {
4045 MaskOps.push_back(DAG.getUNDEF(MaskEVT));
4047 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4048 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
4051 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, LoShuffle, HiShuffle,
4052 DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4053 &MaskOps[0], MaskOps.size()));
4057 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4058 SDValue V1 = Op.getOperand(0);
4059 SDValue V2 = Op.getOperand(1);
4060 SDValue PermMask = Op.getOperand(2);
4061 MVT VT = Op.getValueType();
4062 DebugLoc dl = Op.getDebugLoc();
4063 unsigned NumElems = PermMask.getNumOperands();
4064 bool isMMX = VT.getSizeInBits() == 64;
4065 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4066 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4067 bool V1IsSplat = false;
4068 bool V2IsSplat = false;
4070 if (isUndefShuffle(Op.getNode()))
4071 return DAG.getUNDEF(VT);
4073 if (isZeroShuffle(Op.getNode()))
4074 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4076 if (isIdentityMask(PermMask.getNode()))
4078 else if (isIdentityMask(PermMask.getNode(), true))
4081 // Canonicalize movddup shuffles.
4082 if (V2IsUndef && Subtarget->hasSSE2() &&
4083 VT.getSizeInBits() == 128 &&
4084 X86::isMOVDDUPMask(PermMask.getNode()))
4085 return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3());
4087 if (isSplatMask(PermMask.getNode())) {
4088 if (isMMX || NumElems < 4) return Op;
4089 // Promote it to a v4{if}32 splat.
4090 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
4093 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4095 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4096 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG,
4098 if (NewOp.getNode())
4099 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4100 LowerVECTOR_SHUFFLE(NewOp, DAG));
4101 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4102 // FIXME: Figure out a cleaner way to do this.
4103 // Try to make use of movq to zero out the top part.
4104 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4105 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4107 if (NewOp.getNode()) {
4108 SDValue NewV1 = NewOp.getOperand(0);
4109 SDValue NewV2 = NewOp.getOperand(1);
4110 SDValue NewMask = NewOp.getOperand(2);
4111 if (isCommutedMOVL(NewMask.getNode(), true, false)) {
4112 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
4113 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget,
4117 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4118 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4120 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
4121 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4122 DAG, Subtarget, dl);
4126 // Check if this can be converted into a logical shift.
4127 bool isLeft = false;
4130 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
4131 if (isShift && ShVal.hasOneUse()) {
4132 // If the shifted value has multiple uses, it may be cheaper to use
4133 // v_set0 + movlhps or movhlps, etc.
4134 MVT EVT = VT.getVectorElementType();
4135 ShAmt *= EVT.getSizeInBits();
4136 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4139 if (X86::isMOVLMask(PermMask.getNode())) {
4142 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4143 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4148 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
4149 X86::isMOVSLDUPMask(PermMask.getNode()) ||
4150 X86::isMOVHLPSMask(PermMask.getNode()) ||
4151 X86::isMOVHPMask(PermMask.getNode()) ||
4152 X86::isMOVLPMask(PermMask.getNode())))
4155 if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
4156 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
4157 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4160 // No better options. Use a vshl / vsrl.
4161 MVT EVT = VT.getVectorElementType();
4162 ShAmt *= EVT.getSizeInBits();
4163 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4166 bool Commuted = false;
4167 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4168 // 1,1,1,1 -> v8i16 though.
4169 V1IsSplat = isSplatVector(V1.getNode());
4170 V2IsSplat = isSplatVector(V2.getNode());
4172 // Canonicalize the splat or undef, if present, to be on the RHS.
4173 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4174 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4175 std::swap(V1IsSplat, V2IsSplat);
4176 std::swap(V1IsUndef, V2IsUndef);
4180 // FIXME: Figure out a cleaner way to do this.
4181 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
4182 if (V2IsUndef) return V1;
4183 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4185 // V2 is a splat, so the mask may be malformed. That is, it may point
4186 // to any V2 element. The instruction selectior won't like this. Get
4187 // a corrected mask and commute to form a proper MOVS{S|D}.
4188 SDValue NewMask = getMOVLMask(NumElems, DAG, dl);
4189 if (NewMask.getNode() != PermMask.getNode())
4190 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
4195 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4196 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4197 X86::isUNPCKLMask(PermMask.getNode()) ||
4198 X86::isUNPCKHMask(PermMask.getNode()))
4202 // Normalize mask so all entries that point to V2 points to its first
4203 // element then try to match unpck{h|l} again. If match, return a
4204 // new vector_shuffle with the corrected mask.
4205 SDValue NewMask = NormalizeMask(PermMask, DAG);
4206 if (NewMask.getNode() != PermMask.getNode()) {
4207 if (X86::isUNPCKLMask(NewMask.getNode(), true)) {
4208 SDValue NewMask = getUnpacklMask(NumElems, DAG, dl);
4209 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
4210 } else if (X86::isUNPCKHMask(NewMask.getNode(), true)) {
4211 SDValue NewMask = getUnpackhMask(NumElems, DAG, dl);
4212 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, NewMask);
4217 // Normalize the node to match x86 shuffle ops if needed
4218 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
4219 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4222 // Commute is back and try unpck* again.
4223 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4224 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4225 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4226 X86::isUNPCKLMask(PermMask.getNode()) ||
4227 X86::isUNPCKHMask(PermMask.getNode()))
4231 // Try PSHUF* first, then SHUFP*.
4232 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
4233 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
4234 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
4235 if (V2.getOpcode() != ISD::UNDEF)
4236 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1,
4237 DAG.getUNDEF(VT), PermMask);
4242 if (Subtarget->hasSSE2() &&
4243 (X86::isPSHUFDMask(PermMask.getNode()) ||
4244 X86::isPSHUFHWMask(PermMask.getNode()) ||
4245 X86::isPSHUFLWMask(PermMask.getNode()))) {
4247 if (VT == MVT::v4f32) {
4249 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT,
4250 DAG.getNode(ISD::BIT_CONVERT, dl, RVT, V1),
4251 DAG.getUNDEF(RVT), PermMask);
4252 } else if (V2.getOpcode() != ISD::UNDEF)
4253 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, RVT, V1,
4254 DAG.getUNDEF(RVT), PermMask);
4256 Op = DAG.getNode(ISD::BIT_CONVERT, dl, VT, Op);
4260 // Binary or unary shufps.
4261 if (X86::isSHUFPMask(PermMask.getNode()) ||
4262 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
4266 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4267 if (VT == MVT::v8i16) {
4268 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this, dl);
4269 if (NewOp.getNode())
4273 // Handle all 4 wide cases with a number of shuffles except for MMX.
4274 if (NumElems == 4 && !isMMX)
4275 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG, dl);
4281 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4282 SelectionDAG &DAG) {
4283 MVT VT = Op.getValueType();
4284 DebugLoc dl = Op.getDebugLoc();
4285 if (VT.getSizeInBits() == 8) {
4286 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4287 Op.getOperand(0), Op.getOperand(1));
4288 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4289 DAG.getValueType(VT));
4290 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4291 } else if (VT.getSizeInBits() == 16) {
4292 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4293 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4295 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4296 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4297 DAG.getNode(ISD::BIT_CONVERT, dl,
4301 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4302 Op.getOperand(0), Op.getOperand(1));
4303 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4304 DAG.getValueType(VT));
4305 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4306 } else if (VT == MVT::f32) {
4307 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4308 // the result back to FR32 register. It's only worth matching if the
4309 // result has a single use which is a store or a bitcast to i32. And in
4310 // the case of a store, it's not worth it if the index is a constant 0,
4311 // because a MOVSSmr can be used instead, which is smaller and faster.
4312 if (!Op.hasOneUse())
4314 SDNode *User = *Op.getNode()->use_begin();
4315 if ((User->getOpcode() != ISD::STORE ||
4316 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4317 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4318 (User->getOpcode() != ISD::BIT_CONVERT ||
4319 User->getValueType(0) != MVT::i32))
4321 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4322 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4325 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4326 } else if (VT == MVT::i32) {
4327 // ExtractPS works with constant index.
4328 if (isa<ConstantSDNode>(Op.getOperand(1)))
4336 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4337 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4340 if (Subtarget->hasSSE41()) {
4341 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4346 MVT VT = Op.getValueType();
4347 DebugLoc dl = Op.getDebugLoc();
4348 // TODO: handle v16i8.
4349 if (VT.getSizeInBits() == 16) {
4350 SDValue Vec = Op.getOperand(0);
4351 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4353 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4354 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4355 DAG.getNode(ISD::BIT_CONVERT, dl,
4358 // Transform it so it match pextrw which produces a 32-bit result.
4359 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4360 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
4361 Op.getOperand(0), Op.getOperand(1));
4362 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
4363 DAG.getValueType(VT));
4364 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4365 } else if (VT.getSizeInBits() == 32) {
4366 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4369 // SHUFPS the element to the lowest double word, then movss.
4370 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4371 SmallVector<SDValue, 8> IdxVec;
4373 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4375 push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
4377 push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
4379 push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
4380 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4381 &IdxVec[0], IdxVec.size());
4382 SDValue Vec = Op.getOperand(0);
4383 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
4384 Vec, DAG.getUNDEF(Vec.getValueType()), Mask);
4385 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4386 DAG.getIntPtrConstant(0));
4387 } else if (VT.getSizeInBits() == 64) {
4388 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4389 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4390 // to match extract_elt for f64.
4391 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4395 // UNPCKHPD the element to the lowest double word, then movsd.
4396 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4397 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4398 MVT MaskVT = MVT::getIntVectorWithNumElements(2);
4399 SmallVector<SDValue, 8> IdxVec;
4400 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4402 push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
4403 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
4404 &IdxVec[0], IdxVec.size());
4405 SDValue Vec = Op.getOperand(0);
4406 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
4407 Vec, DAG.getUNDEF(Vec.getValueType()),
4409 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4410 DAG.getIntPtrConstant(0));
4417 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4418 MVT VT = Op.getValueType();
4419 MVT EVT = VT.getVectorElementType();
4420 DebugLoc dl = Op.getDebugLoc();
4422 SDValue N0 = Op.getOperand(0);
4423 SDValue N1 = Op.getOperand(1);
4424 SDValue N2 = Op.getOperand(2);
4426 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4427 isa<ConstantSDNode>(N2)) {
4428 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4430 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4432 if (N1.getValueType() != MVT::i32)
4433 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4434 if (N2.getValueType() != MVT::i32)
4435 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4436 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4437 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4438 // Bits [7:6] of the constant are the source select. This will always be
4439 // zero here. The DAG Combiner may combine an extract_elt index into these
4440 // bits. For example (insert (extract, 3), 2) could be matched by putting
4441 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4442 // Bits [5:4] of the constant are the destination select. This is the
4443 // value of the incoming immediate.
4444 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4445 // combine either bitwise AND or insert of float 0.0 to set these bits.
4446 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4447 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4448 } else if (EVT == MVT::i32) {
4449 // InsertPS works with constant index.
4450 if (isa<ConstantSDNode>(N2))
4457 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4458 MVT VT = Op.getValueType();
4459 MVT EVT = VT.getVectorElementType();
4461 if (Subtarget->hasSSE41())
4462 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4467 DebugLoc dl = Op.getDebugLoc();
4468 SDValue N0 = Op.getOperand(0);
4469 SDValue N1 = Op.getOperand(1);
4470 SDValue N2 = Op.getOperand(2);
4472 if (EVT.getSizeInBits() == 16) {
4473 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4474 // as its second argument.
4475 if (N1.getValueType() != MVT::i32)
4476 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4477 if (N2.getValueType() != MVT::i32)
4478 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4479 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4485 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4486 DebugLoc dl = Op.getDebugLoc();
4487 if (Op.getValueType() == MVT::v2f32)
4488 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4489 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4490 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4491 Op.getOperand(0))));
4493 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4494 MVT VT = MVT::v2i32;
4495 switch (Op.getValueType().getSimpleVT()) {
4502 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4503 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4506 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4507 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4508 // one of the above mentioned nodes. It has to be wrapped because otherwise
4509 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4510 // be used to form addressing mode. These wrapped nodes will be selected
4513 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4514 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4515 // FIXME there isn't really any debug info here, should come from the parent
4516 DebugLoc dl = CP->getDebugLoc();
4517 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
4519 CP->getAlignment());
4520 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4521 // With PIC, the address is actually $g + Offset.
4522 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4523 !Subtarget->isPICStyleRIPRel()) {
4524 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4525 DAG.getNode(X86ISD::GlobalBaseReg,
4526 DebugLoc::getUnknownLoc(),
4535 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4537 SelectionDAG &DAG) const {
4538 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
4539 bool ExtraLoadRequired =
4540 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false);
4542 // Create the TargetGlobalAddress node, folding in the constant
4543 // offset if it is legal.
4545 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) {
4546 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4549 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0);
4550 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4552 // With PIC, the address is actually $g + Offset.
4553 if (IsPic && !Subtarget->isPICStyleRIPRel()) {
4554 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4555 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4559 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4560 // load the value at address GV, not the value of GV itself. This means that
4561 // the GlobalAddress must be in the base or index register of the address, not
4562 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4563 // The same applies for external symbols during PIC codegen
4564 if (ExtraLoadRequired)
4565 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4566 PseudoSourceValue::getGOT(), 0);
4568 // If there was a non-zero offset that we didn't fold, create an explicit
4571 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4572 DAG.getConstant(Offset, getPointerTy()));
4578 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4579 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4580 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4581 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4584 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4586 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4589 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4590 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4591 DAG.getNode(X86ISD::GlobalBaseReg,
4592 DebugLoc::getUnknownLoc(),
4594 InFlag = Chain.getValue(1);
4596 // emit leal symbol@TLSGD(,%ebx,1), %eax
4597 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4598 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4599 GA->getValueType(0),
4601 SDValue Ops[] = { Chain, TGA, InFlag };
4602 SDValue Result = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4603 InFlag = Result.getValue(2);
4604 Chain = Result.getValue(1);
4606 // call ___tls_get_addr. This function receives its argument in
4607 // the register EAX.
4608 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Result, InFlag);
4609 InFlag = Chain.getValue(1);
4611 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4612 SDValue Ops1[] = { Chain,
4613 DAG.getTargetExternalSymbol("___tls_get_addr",
4615 DAG.getRegister(X86::EAX, PtrVT),
4616 DAG.getRegister(X86::EBX, PtrVT),
4618 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops1, 5);
4619 InFlag = Chain.getValue(1);
4621 return DAG.getCopyFromReg(Chain, dl, X86::EAX, PtrVT, InFlag);
4624 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4626 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4628 SDValue InFlag, Chain;
4629 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4631 // emit leaq symbol@TLSGD(%rip), %rdi
4632 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4633 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4634 GA->getValueType(0),
4636 SDValue Ops[] = { DAG.getEntryNode(), TGA};
4637 SDValue Result = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4638 Chain = Result.getValue(1);
4639 InFlag = Result.getValue(2);
4641 // call __tls_get_addr. This function receives its argument in
4642 // the register RDI.
4643 Chain = DAG.getCopyToReg(Chain, dl, X86::RDI, Result, InFlag);
4644 InFlag = Chain.getValue(1);
4646 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4647 SDValue Ops1[] = { Chain,
4648 DAG.getTargetExternalSymbol("__tls_get_addr",
4650 DAG.getRegister(X86::RDI, PtrVT),
4652 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops1, 4);
4653 InFlag = Chain.getValue(1);
4655 return DAG.getCopyFromReg(Chain, dl, X86::RAX, PtrVT, InFlag);
4658 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4659 // "local exec" model.
4660 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4662 DebugLoc dl = GA->getDebugLoc();
4663 // Get the Thread Pointer
4664 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER,
4665 DebugLoc::getUnknownLoc(), PtrVT);
4666 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4668 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4669 GA->getValueType(0),
4671 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
4673 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
4674 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4675 PseudoSourceValue::getGOT(), 0);
4677 // The address of the thread local variable is the add of the thread
4678 // pointer with the offset of the variable.
4679 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
4683 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4684 // TODO: implement the "local dynamic" model
4685 // TODO: implement the "initial exec"model for pic executables
4686 assert(Subtarget->isTargetELF() &&
4687 "TLS not implemented for non-ELF targets");
4688 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4689 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4690 // otherwise use the "Local Exec"TLS Model
4691 if (Subtarget->is64Bit()) {
4692 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4694 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4695 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4697 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4702 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4703 // FIXME there isn't really any debug info here
4704 DebugLoc dl = Op.getDebugLoc();
4705 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4706 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4707 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4708 // With PIC, the address is actually $g + Offset.
4709 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4710 !Subtarget->isPICStyleRIPRel()) {
4711 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4712 DAG.getNode(X86ISD::GlobalBaseReg,
4713 DebugLoc::getUnknownLoc(),
4721 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4722 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4723 // FIXME there isn't really any debug into here
4724 DebugLoc dl = JT->getDebugLoc();
4725 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4726 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4727 // With PIC, the address is actually $g + Offset.
4728 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4729 !Subtarget->isPICStyleRIPRel()) {
4730 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4731 DAG.getNode(X86ISD::GlobalBaseReg,
4732 DebugLoc::getUnknownLoc(),
4740 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4741 /// take a 2 x i32 value to shift plus a shift amount.
4742 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4743 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4744 MVT VT = Op.getValueType();
4745 unsigned VTBits = VT.getSizeInBits();
4746 DebugLoc dl = Op.getDebugLoc();
4747 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4748 SDValue ShOpLo = Op.getOperand(0);
4749 SDValue ShOpHi = Op.getOperand(1);
4750 SDValue ShAmt = Op.getOperand(2);
4751 SDValue Tmp1 = isSRA ?
4752 DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
4753 DAG.getConstant(VTBits - 1, MVT::i8)) :
4754 DAG.getConstant(0, VT);
4757 if (Op.getOpcode() == ISD::SHL_PARTS) {
4758 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
4759 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4761 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
4762 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
4765 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
4766 DAG.getConstant(VTBits, MVT::i8));
4767 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
4768 AndNode, DAG.getConstant(0, MVT::i8));
4771 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4772 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4773 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4775 if (Op.getOpcode() == ISD::SHL_PARTS) {
4776 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4777 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4779 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4780 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4783 SDValue Ops[2] = { Lo, Hi };
4784 return DAG.getMergeValues(Ops, 2, dl);
4787 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4788 MVT SrcVT = Op.getOperand(0).getValueType();
4789 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4790 "Unknown SINT_TO_FP to lower!");
4792 // These are really Legal; caller falls through into that case.
4793 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4795 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4796 Subtarget->is64Bit())
4799 DebugLoc dl = Op.getDebugLoc();
4800 unsigned Size = SrcVT.getSizeInBits()/8;
4801 MachineFunction &MF = DAG.getMachineFunction();
4802 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4803 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4804 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
4806 PseudoSourceValue::getFixedStack(SSFI), 0);
4810 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4812 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4814 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4815 SmallVector<SDValue, 8> Ops;
4816 Ops.push_back(Chain);
4817 Ops.push_back(StackSlot);
4818 Ops.push_back(DAG.getValueType(SrcVT));
4819 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
4820 Tys, &Ops[0], Ops.size());
4823 Chain = Result.getValue(1);
4824 SDValue InFlag = Result.getValue(2);
4826 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4827 // shouldn't be necessary except that RFP cannot be live across
4828 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4829 MachineFunction &MF = DAG.getMachineFunction();
4830 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4831 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4832 Tys = DAG.getVTList(MVT::Other);
4833 SmallVector<SDValue, 8> Ops;
4834 Ops.push_back(Chain);
4835 Ops.push_back(Result);
4836 Ops.push_back(StackSlot);
4837 Ops.push_back(DAG.getValueType(Op.getValueType()));
4838 Ops.push_back(InFlag);
4839 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
4840 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
4841 PseudoSourceValue::getFixedStack(SSFI), 0);
4847 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
4848 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
4849 // This algorithm is not obvious. Here it is in C code, more or less:
4851 double uint64_to_double( uint32_t hi, uint32_t lo ) {
4852 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4853 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
4855 // Copy ints to xmm registers.
4856 __m128i xh = _mm_cvtsi32_si128( hi );
4857 __m128i xl = _mm_cvtsi32_si128( lo );
4859 // Combine into low half of a single xmm register.
4860 __m128i x = _mm_unpacklo_epi32( xh, xl );
4864 // Merge in appropriate exponents to give the integer bits the right
4866 x = _mm_unpacklo_epi32( x, exp );
4868 // Subtract away the biases to deal with the IEEE-754 double precision
4870 d = _mm_sub_pd( (__m128d) x, bias );
4872 // All conversions up to here are exact. The correctly rounded result is
4873 // calculated using the current rounding mode using the following
4875 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4876 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
4877 // store doesn't really need to be here (except
4878 // maybe to zero the other double)
4883 DebugLoc dl = Op.getDebugLoc();
4885 // Build some magic constants.
4886 std::vector<Constant*> CV0;
4887 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000)));
4888 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000)));
4889 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4890 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4891 Constant *C0 = ConstantVector::get(CV0);
4892 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 4);
4894 std::vector<Constant*> CV1;
4895 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL))));
4896 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL))));
4897 Constant *C1 = ConstantVector::get(CV1);
4898 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 4);
4900 SmallVector<SDValue, 4> MaskVec;
4901 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
4902 MaskVec.push_back(DAG.getConstant(4, MVT::i32));
4903 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
4904 MaskVec.push_back(DAG.getConstant(5, MVT::i32));
4905 SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
4906 &MaskVec[0], MaskVec.size());
4907 SmallVector<SDValue, 4> MaskVec2;
4908 MaskVec2.push_back(DAG.getConstant(1, MVT::i32));
4909 MaskVec2.push_back(DAG.getConstant(0, MVT::i32));
4910 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32,
4911 &MaskVec2[0], MaskVec2.size());
4913 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4914 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4916 DAG.getIntPtrConstant(1)));
4917 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4918 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4920 DAG.getIntPtrConstant(0)));
4921 SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32,
4922 XR1, XR2, UnpcklMask);
4923 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
4924 PseudoSourceValue::getConstantPool(), 0,
4926 SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v4i32,
4927 Unpck1, CLod0, UnpcklMask);
4928 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
4929 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
4930 PseudoSourceValue::getConstantPool(), 0,
4932 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
4934 // Add the halves; easiest way is to swap them into another reg first.
4935 SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2f64,
4936 Sub, Sub, ShufMask);
4937 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
4938 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
4939 DAG.getIntPtrConstant(0));
4942 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
4943 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
4944 DebugLoc dl = Op.getDebugLoc();
4945 // FP constant to bias correct the final result.
4946 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
4949 // Load the 32-bit value into an XMM register.
4950 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4951 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4953 DAG.getIntPtrConstant(0)));
4955 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4956 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
4957 DAG.getIntPtrConstant(0));
4959 // Or the load with the bias.
4960 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
4961 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4962 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4964 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4965 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4966 MVT::v2f64, Bias)));
4967 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4968 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
4969 DAG.getIntPtrConstant(0));
4971 // Subtract the bias.
4972 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
4974 // Handle final rounding.
4975 MVT DestVT = Op.getValueType();
4977 if (DestVT.bitsLT(MVT::f64)) {
4978 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
4979 DAG.getIntPtrConstant(0));
4980 } else if (DestVT.bitsGT(MVT::f64)) {
4981 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
4984 // Handle final rounding.
4988 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4989 SDValue N0 = Op.getOperand(0);
4990 DebugLoc dl = Op.getDebugLoc();
4992 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
4993 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
4994 // the optimization here.
4995 if (DAG.SignBitIsZero(N0))
4996 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
4998 MVT SrcVT = N0.getValueType();
4999 if (SrcVT == MVT::i64) {
5000 // We only handle SSE2 f64 target here; caller can handle the rest.
5001 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5004 return LowerUINT_TO_FP_i64(Op, DAG);
5005 } else if (SrcVT == MVT::i32) {
5006 return LowerUINT_TO_FP_i32(Op, DAG);
5009 assert(0 && "Unknown UINT_TO_FP to lower!");
5013 std::pair<SDValue,SDValue> X86TargetLowering::
5014 FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
5015 DebugLoc dl = Op.getDebugLoc();
5016 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
5017 Op.getValueType().getSimpleVT() >= MVT::i16 &&
5018 "Unknown FP_TO_SINT to lower!");
5020 // These are really Legal.
5021 if (Op.getValueType() == MVT::i32 &&
5022 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5023 return std::make_pair(SDValue(), SDValue());
5024 if (Subtarget->is64Bit() &&
5025 Op.getValueType() == MVT::i64 &&
5026 Op.getOperand(0).getValueType() != MVT::f80)
5027 return std::make_pair(SDValue(), SDValue());
5029 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5031 MachineFunction &MF = DAG.getMachineFunction();
5032 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
5033 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5034 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5036 switch (Op.getValueType().getSimpleVT()) {
5037 default: assert(0 && "Invalid FP_TO_SINT to lower!");
5038 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5039 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5040 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5043 SDValue Chain = DAG.getEntryNode();
5044 SDValue Value = Op.getOperand(0);
5045 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5046 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5047 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5048 PseudoSourceValue::getFixedStack(SSFI), 0);
5049 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5051 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5053 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5054 Chain = Value.getValue(1);
5055 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5056 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5059 // Build the FP_TO_INT*_IN_MEM
5060 SDValue Ops[] = { Chain, Value, StackSlot };
5061 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5063 return std::make_pair(FIST, StackSlot);
5066 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5067 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
5068 SDValue FIST = Vals.first, StackSlot = Vals.second;
5069 if (FIST.getNode() == 0) return SDValue();
5072 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5073 FIST, StackSlot, NULL, 0);
5076 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5077 DebugLoc dl = Op.getDebugLoc();
5078 MVT VT = Op.getValueType();
5081 EltVT = VT.getVectorElementType();
5082 std::vector<Constant*> CV;
5083 if (EltVT == MVT::f64) {
5084 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
5088 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
5094 Constant *C = ConstantVector::get(CV);
5095 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5096 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5097 PseudoSourceValue::getConstantPool(), 0,
5099 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5102 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5103 DebugLoc dl = Op.getDebugLoc();
5104 MVT VT = Op.getValueType();
5106 unsigned EltNum = 1;
5107 if (VT.isVector()) {
5108 EltVT = VT.getVectorElementType();
5109 EltNum = VT.getVectorNumElements();
5111 std::vector<Constant*> CV;
5112 if (EltVT == MVT::f64) {
5113 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
5117 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
5123 Constant *C = ConstantVector::get(CV);
5124 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5125 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5126 PseudoSourceValue::getConstantPool(), 0,
5128 if (VT.isVector()) {
5129 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5130 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5131 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5133 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5135 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5139 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5140 SDValue Op0 = Op.getOperand(0);
5141 SDValue Op1 = Op.getOperand(1);
5142 DebugLoc dl = Op.getDebugLoc();
5143 MVT VT = Op.getValueType();
5144 MVT SrcVT = Op1.getValueType();
5146 // If second operand is smaller, extend it first.
5147 if (SrcVT.bitsLT(VT)) {
5148 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5151 // And if it is bigger, shrink it first.
5152 if (SrcVT.bitsGT(VT)) {
5153 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5157 // At this point the operands and the result should have the same
5158 // type, and that won't be f80 since that is not custom lowered.
5160 // First get the sign bit of second operand.
5161 std::vector<Constant*> CV;
5162 if (SrcVT == MVT::f64) {
5163 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
5164 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
5166 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
5167 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5168 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5169 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5171 Constant *C = ConstantVector::get(CV);
5172 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5173 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5174 PseudoSourceValue::getConstantPool(), 0,
5176 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5178 // Shift sign bit right or left if the two operands have different types.
5179 if (SrcVT.bitsGT(VT)) {
5180 // Op0 is MVT::f32, Op1 is MVT::f64.
5181 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5182 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5183 DAG.getConstant(32, MVT::i32));
5184 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5185 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5186 DAG.getIntPtrConstant(0));
5189 // Clear first operand sign bit.
5191 if (VT == MVT::f64) {
5192 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
5193 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
5195 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
5196 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5197 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5198 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5200 C = ConstantVector::get(CV);
5201 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5202 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5203 PseudoSourceValue::getConstantPool(), 0,
5205 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5207 // Or the value with the sign bit.
5208 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5211 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5212 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5213 SDValue Op0 = Op.getOperand(0);
5214 SDValue Op1 = Op.getOperand(1);
5215 DebugLoc dl = Op.getDebugLoc();
5216 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5218 // Lower (X & (1 << N)) == 0 to BT(X, N).
5219 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5220 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5221 if (Op0.getOpcode() == ISD::AND &&
5223 Op1.getOpcode() == ISD::Constant &&
5224 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5225 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5227 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5228 if (ConstantSDNode *Op010C =
5229 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5230 if (Op010C->getZExtValue() == 1) {
5231 LHS = Op0.getOperand(0);
5232 RHS = Op0.getOperand(1).getOperand(1);
5234 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5235 if (ConstantSDNode *Op000C =
5236 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5237 if (Op000C->getZExtValue() == 1) {
5238 LHS = Op0.getOperand(1);
5239 RHS = Op0.getOperand(0).getOperand(1);
5241 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5242 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5243 SDValue AndLHS = Op0.getOperand(0);
5244 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5245 LHS = AndLHS.getOperand(0);
5246 RHS = AndLHS.getOperand(1);
5250 if (LHS.getNode()) {
5251 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5252 // instruction. Since the shift amount is in-range-or-undefined, we know
5253 // that doing a bittest on the i16 value is ok. We extend to i32 because
5254 // the encoding for the i16 version is larger than the i32 version.
5255 if (LHS.getValueType() == MVT::i8)
5256 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5258 // If the operand types disagree, extend the shift amount to match. Since
5259 // BT ignores high bits (like shifts) we can use anyextend.
5260 if (LHS.getValueType() != RHS.getValueType())
5261 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5263 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5264 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5265 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5266 DAG.getConstant(Cond, MVT::i8), BT);
5270 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5271 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5273 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5274 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5275 DAG.getConstant(X86CC, MVT::i8), Cond);
5278 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5280 SDValue Op0 = Op.getOperand(0);
5281 SDValue Op1 = Op.getOperand(1);
5282 SDValue CC = Op.getOperand(2);
5283 MVT VT = Op.getValueType();
5284 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5285 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5286 DebugLoc dl = Op.getDebugLoc();
5290 MVT VT0 = Op0.getValueType();
5291 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5292 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5295 switch (SetCCOpcode) {
5298 case ISD::SETEQ: SSECC = 0; break;
5300 case ISD::SETGT: Swap = true; // Fallthrough
5302 case ISD::SETOLT: SSECC = 1; break;
5304 case ISD::SETGE: Swap = true; // Fallthrough
5306 case ISD::SETOLE: SSECC = 2; break;
5307 case ISD::SETUO: SSECC = 3; break;
5309 case ISD::SETNE: SSECC = 4; break;
5310 case ISD::SETULE: Swap = true;
5311 case ISD::SETUGE: SSECC = 5; break;
5312 case ISD::SETULT: Swap = true;
5313 case ISD::SETUGT: SSECC = 6; break;
5314 case ISD::SETO: SSECC = 7; break;
5317 std::swap(Op0, Op1);
5319 // In the two special cases we can't handle, emit two comparisons.
5321 if (SetCCOpcode == ISD::SETUEQ) {
5323 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5324 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5325 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5327 else if (SetCCOpcode == ISD::SETONE) {
5329 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5330 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5331 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5333 assert(0 && "Illegal FP comparison");
5335 // Handle all other FP comparisons here.
5336 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5339 // We are handling one of the integer comparisons here. Since SSE only has
5340 // GT and EQ comparisons for integer, swapping operands and multiple
5341 // operations may be required for some comparisons.
5342 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5343 bool Swap = false, Invert = false, FlipSigns = false;
5345 switch (VT.getSimpleVT()) {
5347 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5348 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5349 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5350 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5353 switch (SetCCOpcode) {
5355 case ISD::SETNE: Invert = true;
5356 case ISD::SETEQ: Opc = EQOpc; break;
5357 case ISD::SETLT: Swap = true;
5358 case ISD::SETGT: Opc = GTOpc; break;
5359 case ISD::SETGE: Swap = true;
5360 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5361 case ISD::SETULT: Swap = true;
5362 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5363 case ISD::SETUGE: Swap = true;
5364 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5367 std::swap(Op0, Op1);
5369 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5370 // bits of the inputs before performing those operations.
5372 MVT EltVT = VT.getVectorElementType();
5373 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5375 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5376 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5378 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5379 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5382 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5384 // If the logical-not of the result is required, perform that now.
5386 Result = DAG.getNOT(dl, Result, VT);
5391 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5392 static bool isX86LogicalCmp(unsigned Opc) {
5393 return Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI;
5396 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5397 bool addTest = true;
5398 SDValue Cond = Op.getOperand(0);
5399 DebugLoc dl = Op.getDebugLoc();
5402 if (Cond.getOpcode() == ISD::SETCC)
5403 Cond = LowerSETCC(Cond, DAG);
5405 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5406 // setting operand in place of the X86ISD::SETCC.
5407 if (Cond.getOpcode() == X86ISD::SETCC) {
5408 CC = Cond.getOperand(0);
5410 SDValue Cmp = Cond.getOperand(1);
5411 unsigned Opc = Cmp.getOpcode();
5412 MVT VT = Op.getValueType();
5414 bool IllegalFPCMov = false;
5415 if (VT.isFloatingPoint() && !VT.isVector() &&
5416 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5417 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5419 if ((isX86LogicalCmp(Opc) && !IllegalFPCMov) || Opc == X86ISD::BT) { // FIXME
5426 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5427 Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond,
5428 DAG.getConstant(0, MVT::i8));
5431 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
5433 SmallVector<SDValue, 4> Ops;
5434 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5435 // condition is true.
5436 Ops.push_back(Op.getOperand(2));
5437 Ops.push_back(Op.getOperand(1));
5439 Ops.push_back(Cond);
5440 return DAG.getNode(X86ISD::CMOV, dl, VTs, 2, &Ops[0], Ops.size());
5443 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5444 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5445 // from the AND / OR.
5446 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5447 Opc = Op.getOpcode();
5448 if (Opc != ISD::OR && Opc != ISD::AND)
5450 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5451 Op.getOperand(0).hasOneUse() &&
5452 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5453 Op.getOperand(1).hasOneUse());
5456 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5457 // 1 and that the SETCC node has a single use.
5458 static bool isXor1OfSetCC(SDValue Op) {
5459 if (Op.getOpcode() != ISD::XOR)
5461 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5462 if (N1C && N1C->getAPIntValue() == 1) {
5463 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5464 Op.getOperand(0).hasOneUse();
5469 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5470 bool addTest = true;
5471 SDValue Chain = Op.getOperand(0);
5472 SDValue Cond = Op.getOperand(1);
5473 SDValue Dest = Op.getOperand(2);
5474 DebugLoc dl = Op.getDebugLoc();
5477 if (Cond.getOpcode() == ISD::SETCC)
5478 Cond = LowerSETCC(Cond, DAG);
5480 // FIXME: LowerXALUO doesn't handle these!!
5481 else if (Cond.getOpcode() == X86ISD::ADD ||
5482 Cond.getOpcode() == X86ISD::SUB ||
5483 Cond.getOpcode() == X86ISD::SMUL ||
5484 Cond.getOpcode() == X86ISD::UMUL)
5485 Cond = LowerXALUO(Cond, DAG);
5488 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5489 // setting operand in place of the X86ISD::SETCC.
5490 if (Cond.getOpcode() == X86ISD::SETCC) {
5491 CC = Cond.getOperand(0);
5493 SDValue Cmp = Cond.getOperand(1);
5494 unsigned Opc = Cmp.getOpcode();
5495 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5496 if (isX86LogicalCmp(Opc) || Opc == X86ISD::BT) {
5500 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5504 // These can only come from an arithmetic instruction with overflow,
5505 // e.g. SADDO, UADDO.
5506 Cond = Cond.getNode()->getOperand(1);
5513 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5514 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5515 unsigned Opc = Cmp.getOpcode();
5516 if (CondOpc == ISD::OR) {
5517 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5518 // two branches instead of an explicit OR instruction with a
5520 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5521 isX86LogicalCmp(Opc)) {
5522 CC = Cond.getOperand(0).getOperand(0);
5523 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5524 Chain, Dest, CC, Cmp);
5525 CC = Cond.getOperand(1).getOperand(0);
5529 } else { // ISD::AND
5530 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5531 // two branches instead of an explicit AND instruction with a
5532 // separate test. However, we only do this if this block doesn't
5533 // have a fall-through edge, because this requires an explicit
5534 // jmp when the condition is false.
5535 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5536 isX86LogicalCmp(Opc) &&
5537 Op.getNode()->hasOneUse()) {
5538 X86::CondCode CCode =
5539 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5540 CCode = X86::GetOppositeBranchCondition(CCode);
5541 CC = DAG.getConstant(CCode, MVT::i8);
5542 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5543 // Look for an unconditional branch following this conditional branch.
5544 // We need this because we need to reverse the successors in order
5545 // to implement FCMP_OEQ.
5546 if (User.getOpcode() == ISD::BR) {
5547 SDValue FalseBB = User.getOperand(1);
5549 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5550 assert(NewBR == User);
5553 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5554 Chain, Dest, CC, Cmp);
5555 X86::CondCode CCode =
5556 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5557 CCode = X86::GetOppositeBranchCondition(CCode);
5558 CC = DAG.getConstant(CCode, MVT::i8);
5564 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5565 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5566 // It should be transformed during dag combiner except when the condition
5567 // is set by a arithmetics with overflow node.
5568 X86::CondCode CCode =
5569 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5570 CCode = X86::GetOppositeBranchCondition(CCode);
5571 CC = DAG.getConstant(CCode, MVT::i8);
5572 Cond = Cond.getOperand(0).getOperand(1);
5578 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5579 Cond= DAG.getNode(X86ISD::CMP, dl, MVT::i32, Cond,
5580 DAG.getConstant(0, MVT::i8));
5582 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5583 Chain, Dest, CC, Cond);
5587 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5588 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5589 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5590 // that the guard pages used by the OS virtual memory manager are allocated in
5591 // correct sequence.
5593 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5594 SelectionDAG &DAG) {
5595 assert(Subtarget->isTargetCygMing() &&
5596 "This should be used only on Cygwin/Mingw targets");
5597 DebugLoc dl = Op.getDebugLoc();
5600 SDValue Chain = Op.getOperand(0);
5601 SDValue Size = Op.getOperand(1);
5602 // FIXME: Ensure alignment here
5606 MVT IntPtr = getPointerTy();
5607 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5609 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5611 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
5612 Flag = Chain.getValue(1);
5614 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5615 SDValue Ops[] = { Chain,
5616 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5617 DAG.getRegister(X86::EAX, IntPtr),
5618 DAG.getRegister(X86StackPtr, SPTy),
5620 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
5621 Flag = Chain.getValue(1);
5623 Chain = DAG.getCALLSEQ_END(Chain,
5624 DAG.getIntPtrConstant(0, true),
5625 DAG.getIntPtrConstant(0, true),
5628 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
5630 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5631 return DAG.getMergeValues(Ops1, 2, dl);
5635 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
5637 SDValue Dst, SDValue Src,
5638 SDValue Size, unsigned Align,
5640 uint64_t DstSVOff) {
5641 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5643 // If not DWORD aligned or size is more than the threshold, call the library.
5644 // The libc version is likely to be faster for these cases. It can use the
5645 // address value and run time information about the CPU.
5646 if ((Align & 3) != 0 ||
5648 ConstantSize->getZExtValue() >
5649 getSubtarget()->getMaxInlineSizeThreshold()) {
5650 SDValue InFlag(0, 0);
5652 // Check to see if there is a specialized entry-point for memory zeroing.
5653 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5655 if (const char *bzeroEntry = V &&
5656 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5657 MVT IntPtr = getPointerTy();
5658 const Type *IntPtrTy = TD->getIntPtrType();
5659 TargetLowering::ArgListTy Args;
5660 TargetLowering::ArgListEntry Entry;
5662 Entry.Ty = IntPtrTy;
5663 Args.push_back(Entry);
5665 Args.push_back(Entry);
5666 std::pair<SDValue,SDValue> CallResult =
5667 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
5668 CallingConv::C, false,
5669 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
5670 return CallResult.second;
5673 // Otherwise have the target-independent code call memset.
5677 uint64_t SizeVal = ConstantSize->getZExtValue();
5678 SDValue InFlag(0, 0);
5681 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5682 unsigned BytesLeft = 0;
5683 bool TwoRepStos = false;
5686 uint64_t Val = ValC->getZExtValue() & 255;
5688 // If the value is a constant, then we can potentially use larger sets.
5689 switch (Align & 3) {
5690 case 2: // WORD aligned
5693 Val = (Val << 8) | Val;
5695 case 0: // DWORD aligned
5698 Val = (Val << 8) | Val;
5699 Val = (Val << 16) | Val;
5700 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5703 Val = (Val << 32) | Val;
5706 default: // Byte aligned
5709 Count = DAG.getIntPtrConstant(SizeVal);
5713 if (AVT.bitsGT(MVT::i8)) {
5714 unsigned UBytes = AVT.getSizeInBits() / 8;
5715 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5716 BytesLeft = SizeVal % UBytes;
5719 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
5721 InFlag = Chain.getValue(1);
5724 Count = DAG.getIntPtrConstant(SizeVal);
5725 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
5726 InFlag = Chain.getValue(1);
5729 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5732 InFlag = Chain.getValue(1);
5733 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5736 InFlag = Chain.getValue(1);
5738 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5739 SmallVector<SDValue, 8> Ops;
5740 Ops.push_back(Chain);
5741 Ops.push_back(DAG.getValueType(AVT));
5742 Ops.push_back(InFlag);
5743 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5746 InFlag = Chain.getValue(1);
5748 MVT CVT = Count.getValueType();
5749 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
5750 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5751 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
5754 InFlag = Chain.getValue(1);
5755 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5757 Ops.push_back(Chain);
5758 Ops.push_back(DAG.getValueType(MVT::i8));
5759 Ops.push_back(InFlag);
5760 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5761 } else if (BytesLeft) {
5762 // Handle the last 1 - 7 bytes.
5763 unsigned Offset = SizeVal - BytesLeft;
5764 MVT AddrVT = Dst.getValueType();
5765 MVT SizeVT = Size.getValueType();
5767 Chain = DAG.getMemset(Chain, dl,
5768 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
5769 DAG.getConstant(Offset, AddrVT)),
5771 DAG.getConstant(BytesLeft, SizeVT),
5772 Align, DstSV, DstSVOff + Offset);
5775 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5780 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
5781 SDValue Chain, SDValue Dst, SDValue Src,
5782 SDValue Size, unsigned Align,
5784 const Value *DstSV, uint64_t DstSVOff,
5785 const Value *SrcSV, uint64_t SrcSVOff) {
5786 // This requires the copy size to be a constant, preferrably
5787 // within a subtarget-specific limit.
5788 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5791 uint64_t SizeVal = ConstantSize->getZExtValue();
5792 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5795 /// If not DWORD aligned, call the library.
5796 if ((Align & 3) != 0)
5801 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5804 unsigned UBytes = AVT.getSizeInBits() / 8;
5805 unsigned CountVal = SizeVal / UBytes;
5806 SDValue Count = DAG.getIntPtrConstant(CountVal);
5807 unsigned BytesLeft = SizeVal % UBytes;
5809 SDValue InFlag(0, 0);
5810 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5813 InFlag = Chain.getValue(1);
5814 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5817 InFlag = Chain.getValue(1);
5818 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
5821 InFlag = Chain.getValue(1);
5823 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5824 SmallVector<SDValue, 8> Ops;
5825 Ops.push_back(Chain);
5826 Ops.push_back(DAG.getValueType(AVT));
5827 Ops.push_back(InFlag);
5828 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
5830 SmallVector<SDValue, 4> Results;
5831 Results.push_back(RepMovs);
5833 // Handle the last 1 - 7 bytes.
5834 unsigned Offset = SizeVal - BytesLeft;
5835 MVT DstVT = Dst.getValueType();
5836 MVT SrcVT = Src.getValueType();
5837 MVT SizeVT = Size.getValueType();
5838 Results.push_back(DAG.getMemcpy(Chain, dl,
5839 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
5840 DAG.getConstant(Offset, DstVT)),
5841 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
5842 DAG.getConstant(Offset, SrcVT)),
5843 DAG.getConstant(BytesLeft, SizeVT),
5844 Align, AlwaysInline,
5845 DstSV, DstSVOff + Offset,
5846 SrcSV, SrcSVOff + Offset));
5849 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5850 &Results[0], Results.size());
5853 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
5854 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
5855 DebugLoc dl = Op.getDebugLoc();
5857 if (!Subtarget->is64Bit()) {
5858 // vastart just stores the address of the VarArgsFrameIndex slot into the
5859 // memory location argument.
5860 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5861 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
5865 // gp_offset (0 - 6 * 8)
5866 // fp_offset (48 - 48 + 8 * 16)
5867 // overflow_arg_area (point to parameters coming in memory).
5869 SmallVector<SDValue, 8> MemOps;
5870 SDValue FIN = Op.getOperand(1);
5872 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
5873 DAG.getConstant(VarArgsGPOffset, MVT::i32),
5875 MemOps.push_back(Store);
5878 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5879 FIN, DAG.getIntPtrConstant(4));
5880 Store = DAG.getStore(Op.getOperand(0), dl,
5881 DAG.getConstant(VarArgsFPOffset, MVT::i32),
5883 MemOps.push_back(Store);
5885 // Store ptr to overflow_arg_area
5886 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5887 FIN, DAG.getIntPtrConstant(4));
5888 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5889 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
5890 MemOps.push_back(Store);
5892 // Store ptr to reg_save_area.
5893 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5894 FIN, DAG.getIntPtrConstant(8));
5895 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
5896 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
5897 MemOps.push_back(Store);
5898 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5899 &MemOps[0], MemOps.size());
5902 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
5903 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5904 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
5905 SDValue Chain = Op.getOperand(0);
5906 SDValue SrcPtr = Op.getOperand(1);
5907 SDValue SrcSV = Op.getOperand(2);
5909 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5914 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
5915 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5916 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
5917 SDValue Chain = Op.getOperand(0);
5918 SDValue DstPtr = Op.getOperand(1);
5919 SDValue SrcPtr = Op.getOperand(2);
5920 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5921 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5922 DebugLoc dl = Op.getDebugLoc();
5924 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
5925 DAG.getIntPtrConstant(24), 8, false,
5926 DstSV, 0, SrcSV, 0);
5930 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
5931 DebugLoc dl = Op.getDebugLoc();
5932 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5934 default: return SDValue(); // Don't custom lower most intrinsics.
5935 // Comparison intrinsics.
5936 case Intrinsic::x86_sse_comieq_ss:
5937 case Intrinsic::x86_sse_comilt_ss:
5938 case Intrinsic::x86_sse_comile_ss:
5939 case Intrinsic::x86_sse_comigt_ss:
5940 case Intrinsic::x86_sse_comige_ss:
5941 case Intrinsic::x86_sse_comineq_ss:
5942 case Intrinsic::x86_sse_ucomieq_ss:
5943 case Intrinsic::x86_sse_ucomilt_ss:
5944 case Intrinsic::x86_sse_ucomile_ss:
5945 case Intrinsic::x86_sse_ucomigt_ss:
5946 case Intrinsic::x86_sse_ucomige_ss:
5947 case Intrinsic::x86_sse_ucomineq_ss:
5948 case Intrinsic::x86_sse2_comieq_sd:
5949 case Intrinsic::x86_sse2_comilt_sd:
5950 case Intrinsic::x86_sse2_comile_sd:
5951 case Intrinsic::x86_sse2_comigt_sd:
5952 case Intrinsic::x86_sse2_comige_sd:
5953 case Intrinsic::x86_sse2_comineq_sd:
5954 case Intrinsic::x86_sse2_ucomieq_sd:
5955 case Intrinsic::x86_sse2_ucomilt_sd:
5956 case Intrinsic::x86_sse2_ucomile_sd:
5957 case Intrinsic::x86_sse2_ucomigt_sd:
5958 case Intrinsic::x86_sse2_ucomige_sd:
5959 case Intrinsic::x86_sse2_ucomineq_sd: {
5961 ISD::CondCode CC = ISD::SETCC_INVALID;
5964 case Intrinsic::x86_sse_comieq_ss:
5965 case Intrinsic::x86_sse2_comieq_sd:
5969 case Intrinsic::x86_sse_comilt_ss:
5970 case Intrinsic::x86_sse2_comilt_sd:
5974 case Intrinsic::x86_sse_comile_ss:
5975 case Intrinsic::x86_sse2_comile_sd:
5979 case Intrinsic::x86_sse_comigt_ss:
5980 case Intrinsic::x86_sse2_comigt_sd:
5984 case Intrinsic::x86_sse_comige_ss:
5985 case Intrinsic::x86_sse2_comige_sd:
5989 case Intrinsic::x86_sse_comineq_ss:
5990 case Intrinsic::x86_sse2_comineq_sd:
5994 case Intrinsic::x86_sse_ucomieq_ss:
5995 case Intrinsic::x86_sse2_ucomieq_sd:
5996 Opc = X86ISD::UCOMI;
5999 case Intrinsic::x86_sse_ucomilt_ss:
6000 case Intrinsic::x86_sse2_ucomilt_sd:
6001 Opc = X86ISD::UCOMI;
6004 case Intrinsic::x86_sse_ucomile_ss:
6005 case Intrinsic::x86_sse2_ucomile_sd:
6006 Opc = X86ISD::UCOMI;
6009 case Intrinsic::x86_sse_ucomigt_ss:
6010 case Intrinsic::x86_sse2_ucomigt_sd:
6011 Opc = X86ISD::UCOMI;
6014 case Intrinsic::x86_sse_ucomige_ss:
6015 case Intrinsic::x86_sse2_ucomige_sd:
6016 Opc = X86ISD::UCOMI;
6019 case Intrinsic::x86_sse_ucomineq_ss:
6020 case Intrinsic::x86_sse2_ucomineq_sd:
6021 Opc = X86ISD::UCOMI;
6026 SDValue LHS = Op.getOperand(1);
6027 SDValue RHS = Op.getOperand(2);
6028 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6029 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6030 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6031 DAG.getConstant(X86CC, MVT::i8), Cond);
6032 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6035 // Fix vector shift instructions where the last operand is a non-immediate
6037 case Intrinsic::x86_sse2_pslli_w:
6038 case Intrinsic::x86_sse2_pslli_d:
6039 case Intrinsic::x86_sse2_pslli_q:
6040 case Intrinsic::x86_sse2_psrli_w:
6041 case Intrinsic::x86_sse2_psrli_d:
6042 case Intrinsic::x86_sse2_psrli_q:
6043 case Intrinsic::x86_sse2_psrai_w:
6044 case Intrinsic::x86_sse2_psrai_d:
6045 case Intrinsic::x86_mmx_pslli_w:
6046 case Intrinsic::x86_mmx_pslli_d:
6047 case Intrinsic::x86_mmx_pslli_q:
6048 case Intrinsic::x86_mmx_psrli_w:
6049 case Intrinsic::x86_mmx_psrli_d:
6050 case Intrinsic::x86_mmx_psrli_q:
6051 case Intrinsic::x86_mmx_psrai_w:
6052 case Intrinsic::x86_mmx_psrai_d: {
6053 SDValue ShAmt = Op.getOperand(2);
6054 if (isa<ConstantSDNode>(ShAmt))
6057 unsigned NewIntNo = 0;
6058 MVT ShAmtVT = MVT::v4i32;
6060 case Intrinsic::x86_sse2_pslli_w:
6061 NewIntNo = Intrinsic::x86_sse2_psll_w;
6063 case Intrinsic::x86_sse2_pslli_d:
6064 NewIntNo = Intrinsic::x86_sse2_psll_d;
6066 case Intrinsic::x86_sse2_pslli_q:
6067 NewIntNo = Intrinsic::x86_sse2_psll_q;
6069 case Intrinsic::x86_sse2_psrli_w:
6070 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6072 case Intrinsic::x86_sse2_psrli_d:
6073 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6075 case Intrinsic::x86_sse2_psrli_q:
6076 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6078 case Intrinsic::x86_sse2_psrai_w:
6079 NewIntNo = Intrinsic::x86_sse2_psra_w;
6081 case Intrinsic::x86_sse2_psrai_d:
6082 NewIntNo = Intrinsic::x86_sse2_psra_d;
6085 ShAmtVT = MVT::v2i32;
6087 case Intrinsic::x86_mmx_pslli_w:
6088 NewIntNo = Intrinsic::x86_mmx_psll_w;
6090 case Intrinsic::x86_mmx_pslli_d:
6091 NewIntNo = Intrinsic::x86_mmx_psll_d;
6093 case Intrinsic::x86_mmx_pslli_q:
6094 NewIntNo = Intrinsic::x86_mmx_psll_q;
6096 case Intrinsic::x86_mmx_psrli_w:
6097 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6099 case Intrinsic::x86_mmx_psrli_d:
6100 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6102 case Intrinsic::x86_mmx_psrli_q:
6103 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6105 case Intrinsic::x86_mmx_psrai_w:
6106 NewIntNo = Intrinsic::x86_mmx_psra_w;
6108 case Intrinsic::x86_mmx_psrai_d:
6109 NewIntNo = Intrinsic::x86_mmx_psra_d;
6111 default: abort(); // Can't reach here.
6116 MVT VT = Op.getValueType();
6117 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6118 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
6119 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6120 DAG.getConstant(NewIntNo, MVT::i32),
6121 Op.getOperand(1), ShAmt);
6126 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6127 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6128 DebugLoc dl = Op.getDebugLoc();
6131 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6133 DAG.getConstant(TD->getPointerSize(),
6134 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6135 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6136 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6141 // Just load the return address.
6142 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6143 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6144 RetAddrFI, NULL, 0);
6147 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6148 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6149 MFI->setFrameAddressIsTaken(true);
6150 MVT VT = Op.getValueType();
6151 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6152 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6153 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6154 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6156 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6160 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6161 SelectionDAG &DAG) {
6162 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6165 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6167 MachineFunction &MF = DAG.getMachineFunction();
6168 SDValue Chain = Op.getOperand(0);
6169 SDValue Offset = Op.getOperand(1);
6170 SDValue Handler = Op.getOperand(2);
6171 DebugLoc dl = Op.getDebugLoc();
6173 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6175 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6177 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6178 DAG.getIntPtrConstant(-TD->getPointerSize()));
6179 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6180 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6181 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6182 MF.getRegInfo().addLiveOut(StoreAddrReg);
6184 return DAG.getNode(X86ISD::EH_RETURN, dl,
6186 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6189 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6190 SelectionDAG &DAG) {
6191 SDValue Root = Op.getOperand(0);
6192 SDValue Trmp = Op.getOperand(1); // trampoline
6193 SDValue FPtr = Op.getOperand(2); // nested function
6194 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6195 DebugLoc dl = Op.getDebugLoc();
6197 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6199 const X86InstrInfo *TII =
6200 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6202 if (Subtarget->is64Bit()) {
6203 SDValue OutChains[6];
6205 // Large code-model.
6207 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6208 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6210 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6211 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6213 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6215 // Load the pointer to the nested function into R11.
6216 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6217 SDValue Addr = Trmp;
6218 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6221 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6222 DAG.getConstant(2, MVT::i64));
6223 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6225 // Load the 'nest' parameter value into R10.
6226 // R10 is specified in X86CallingConv.td
6227 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6228 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6229 DAG.getConstant(10, MVT::i64));
6230 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6231 Addr, TrmpAddr, 10);
6233 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6234 DAG.getConstant(12, MVT::i64));
6235 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6237 // Jump to the nested function.
6238 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6239 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6240 DAG.getConstant(20, MVT::i64));
6241 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6242 Addr, TrmpAddr, 20);
6244 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6245 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6246 DAG.getConstant(22, MVT::i64));
6247 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6251 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6252 return DAG.getMergeValues(Ops, 2, dl);
6254 const Function *Func =
6255 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6256 unsigned CC = Func->getCallingConv();
6261 assert(0 && "Unsupported calling convention");
6262 case CallingConv::C:
6263 case CallingConv::X86_StdCall: {
6264 // Pass 'nest' parameter in ECX.
6265 // Must be kept in sync with X86CallingConv.td
6268 // Check that ECX wasn't needed by an 'inreg' parameter.
6269 const FunctionType *FTy = Func->getFunctionType();
6270 const AttrListPtr &Attrs = Func->getAttributes();
6272 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6273 unsigned InRegCount = 0;
6276 for (FunctionType::param_iterator I = FTy->param_begin(),
6277 E = FTy->param_end(); I != E; ++I, ++Idx)
6278 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6279 // FIXME: should only count parameters that are lowered to integers.
6280 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6282 if (InRegCount > 2) {
6283 cerr << "Nest register in use - reduce number of inreg parameters!\n";
6289 case CallingConv::X86_FastCall:
6290 case CallingConv::Fast:
6291 // Pass 'nest' parameter in EAX.
6292 // Must be kept in sync with X86CallingConv.td
6297 SDValue OutChains[4];
6300 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6301 DAG.getConstant(10, MVT::i32));
6302 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6304 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6305 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6306 OutChains[0] = DAG.getStore(Root, dl,
6307 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6310 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6311 DAG.getConstant(1, MVT::i32));
6312 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6314 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6315 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6316 DAG.getConstant(5, MVT::i32));
6317 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6318 TrmpAddr, 5, false, 1);
6320 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6321 DAG.getConstant(6, MVT::i32));
6322 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6325 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6326 return DAG.getMergeValues(Ops, 2, dl);
6330 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6332 The rounding mode is in bits 11:10 of FPSR, and has the following
6339 FLT_ROUNDS, on the other hand, expects the following:
6346 To perform the conversion, we do:
6347 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6350 MachineFunction &MF = DAG.getMachineFunction();
6351 const TargetMachine &TM = MF.getTarget();
6352 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6353 unsigned StackAlignment = TFI.getStackAlignment();
6354 MVT VT = Op.getValueType();
6355 DebugLoc dl = Op.getDebugLoc();
6357 // Save FP Control Word to stack slot
6358 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6359 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6361 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6362 DAG.getEntryNode(), StackSlot);
6364 // Load FP Control Word from stack slot
6365 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6367 // Transform as necessary
6369 DAG.getNode(ISD::SRL, dl, MVT::i16,
6370 DAG.getNode(ISD::AND, dl, MVT::i16,
6371 CWD, DAG.getConstant(0x800, MVT::i16)),
6372 DAG.getConstant(11, MVT::i8));
6374 DAG.getNode(ISD::SRL, dl, MVT::i16,
6375 DAG.getNode(ISD::AND, dl, MVT::i16,
6376 CWD, DAG.getConstant(0x400, MVT::i16)),
6377 DAG.getConstant(9, MVT::i8));
6380 DAG.getNode(ISD::AND, dl, MVT::i16,
6381 DAG.getNode(ISD::ADD, dl, MVT::i16,
6382 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6383 DAG.getConstant(1, MVT::i16)),
6384 DAG.getConstant(3, MVT::i16));
6387 return DAG.getNode((VT.getSizeInBits() < 16 ?
6388 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6391 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6392 MVT VT = Op.getValueType();
6394 unsigned NumBits = VT.getSizeInBits();
6395 DebugLoc dl = Op.getDebugLoc();
6397 Op = Op.getOperand(0);
6398 if (VT == MVT::i8) {
6399 // Zero extend to i32 since there is not an i8 bsr.
6401 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6404 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6405 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6406 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6408 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6409 SmallVector<SDValue, 4> Ops;
6411 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6412 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6413 Ops.push_back(Op.getValue(1));
6414 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6416 // Finally xor with NumBits-1.
6417 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6420 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6424 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6425 MVT VT = Op.getValueType();
6427 unsigned NumBits = VT.getSizeInBits();
6428 DebugLoc dl = Op.getDebugLoc();
6430 Op = Op.getOperand(0);
6431 if (VT == MVT::i8) {
6433 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6436 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6437 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6438 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
6440 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6441 SmallVector<SDValue, 4> Ops;
6443 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6444 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6445 Ops.push_back(Op.getValue(1));
6446 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6449 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6453 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6454 MVT VT = Op.getValueType();
6455 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6456 DebugLoc dl = Op.getDebugLoc();
6458 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6459 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6460 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6461 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6462 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6464 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6465 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6466 // return AloBlo + AloBhi + AhiBlo;
6468 SDValue A = Op.getOperand(0);
6469 SDValue B = Op.getOperand(1);
6471 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6472 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6473 A, DAG.getConstant(32, MVT::i32));
6474 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6475 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6476 B, DAG.getConstant(32, MVT::i32));
6477 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6478 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6480 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6481 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6483 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6484 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6486 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6487 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6488 AloBhi, DAG.getConstant(32, MVT::i32));
6489 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6490 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6491 AhiBlo, DAG.getConstant(32, MVT::i32));
6492 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
6493 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
6498 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6499 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6500 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6501 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6502 // has only one use.
6503 SDNode *N = Op.getNode();
6504 SDValue LHS = N->getOperand(0);
6505 SDValue RHS = N->getOperand(1);
6506 unsigned BaseOp = 0;
6508 DebugLoc dl = Op.getDebugLoc();
6510 switch (Op.getOpcode()) {
6511 default: assert(0 && "Unknown ovf instruction!");
6513 BaseOp = X86ISD::ADD;
6517 BaseOp = X86ISD::ADD;
6521 BaseOp = X86ISD::SUB;
6525 BaseOp = X86ISD::SUB;
6529 BaseOp = X86ISD::SMUL;
6533 BaseOp = X86ISD::UMUL;
6538 // Also sets EFLAGS.
6539 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6540 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
6543 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
6544 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6546 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6550 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6551 MVT T = Op.getValueType();
6552 DebugLoc dl = Op.getDebugLoc();
6555 switch(T.getSimpleVT()) {
6557 assert(false && "Invalid value type!");
6558 case MVT::i8: Reg = X86::AL; size = 1; break;
6559 case MVT::i16: Reg = X86::AX; size = 2; break;
6560 case MVT::i32: Reg = X86::EAX; size = 4; break;
6562 assert(Subtarget->is64Bit() && "Node not type legal!");
6563 Reg = X86::RAX; size = 8;
6566 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
6567 Op.getOperand(2), SDValue());
6568 SDValue Ops[] = { cpIn.getValue(0),
6571 DAG.getTargetConstant(size, MVT::i8),
6573 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6574 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
6576 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
6580 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6581 SelectionDAG &DAG) {
6582 assert(Subtarget->is64Bit() && "Result not type legalized?");
6583 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6584 SDValue TheChain = Op.getOperand(0);
6585 DebugLoc dl = Op.getDebugLoc();
6586 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6587 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
6588 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
6590 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
6591 DAG.getConstant(32, MVT::i8));
6593 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
6596 return DAG.getMergeValues(Ops, 2, dl);
6599 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6600 SDNode *Node = Op.getNode();
6601 DebugLoc dl = Node->getDebugLoc();
6602 MVT T = Node->getValueType(0);
6603 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
6604 DAG.getConstant(0, T), Node->getOperand(2));
6605 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
6606 cast<AtomicSDNode>(Node)->getMemoryVT(),
6607 Node->getOperand(0),
6608 Node->getOperand(1), negOp,
6609 cast<AtomicSDNode>(Node)->getSrcValue(),
6610 cast<AtomicSDNode>(Node)->getAlignment());
6613 /// LowerOperation - Provide custom lowering hooks for some operations.
6615 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6616 switch (Op.getOpcode()) {
6617 default: assert(0 && "Should not custom lower this!");
6618 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6619 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
6620 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6621 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6622 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6623 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6624 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6625 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6626 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6627 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6628 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6629 case ISD::SHL_PARTS:
6630 case ISD::SRA_PARTS:
6631 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6632 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6633 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6634 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6635 case ISD::FABS: return LowerFABS(Op, DAG);
6636 case ISD::FNEG: return LowerFNEG(Op, DAG);
6637 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6638 case ISD::SETCC: return LowerSETCC(Op, DAG);
6639 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6640 case ISD::SELECT: return LowerSELECT(Op, DAG);
6641 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6642 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6643 case ISD::CALL: return LowerCALL(Op, DAG);
6644 case ISD::RET: return LowerRET(Op, DAG);
6645 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
6646 case ISD::VASTART: return LowerVASTART(Op, DAG);
6647 case ISD::VAARG: return LowerVAARG(Op, DAG);
6648 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6649 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6650 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6651 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6652 case ISD::FRAME_TO_ARGS_OFFSET:
6653 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6654 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6655 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6656 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6657 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6658 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6659 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6660 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
6666 case ISD::UMULO: return LowerXALUO(Op, DAG);
6667 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6671 void X86TargetLowering::
6672 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6673 SelectionDAG &DAG, unsigned NewOp) {
6674 MVT T = Node->getValueType(0);
6675 DebugLoc dl = Node->getDebugLoc();
6676 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6678 SDValue Chain = Node->getOperand(0);
6679 SDValue In1 = Node->getOperand(1);
6680 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6681 Node->getOperand(2), DAG.getIntPtrConstant(0));
6682 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6683 Node->getOperand(2), DAG.getIntPtrConstant(1));
6684 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6685 // have a MemOperand. Pass the info through as a normal operand.
6686 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6687 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6688 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6689 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
6690 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6691 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6692 Results.push_back(Result.getValue(2));
6695 /// ReplaceNodeResults - Replace a node with an illegal result type
6696 /// with a new node built out of custom code.
6697 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
6698 SmallVectorImpl<SDValue>&Results,
6699 SelectionDAG &DAG) {
6700 DebugLoc dl = N->getDebugLoc();
6701 switch (N->getOpcode()) {
6703 assert(false && "Do not know how to custom type legalize this operation!");
6705 case ISD::FP_TO_SINT: {
6706 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
6707 SDValue FIST = Vals.first, StackSlot = Vals.second;
6708 if (FIST.getNode() != 0) {
6709 MVT VT = N->getValueType(0);
6710 // Return a load from the stack slot.
6711 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
6715 case ISD::READCYCLECOUNTER: {
6716 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6717 SDValue TheChain = N->getOperand(0);
6718 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6719 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
6721 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
6723 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
6724 SDValue Ops[] = { eax, edx };
6725 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
6726 Results.push_back(edx.getValue(1));
6729 case ISD::ATOMIC_CMP_SWAP: {
6730 MVT T = N->getValueType(0);
6731 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6732 SDValue cpInL, cpInH;
6733 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6734 DAG.getConstant(0, MVT::i32));
6735 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6736 DAG.getConstant(1, MVT::i32));
6737 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
6738 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
6740 SDValue swapInL, swapInH;
6741 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
6742 DAG.getConstant(0, MVT::i32));
6743 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
6744 DAG.getConstant(1, MVT::i32));
6745 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
6747 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
6748 swapInL.getValue(1));
6749 SDValue Ops[] = { swapInH.getValue(0),
6751 swapInH.getValue(1) };
6752 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6753 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
6754 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
6755 MVT::i32, Result.getValue(1));
6756 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
6757 MVT::i32, cpOutL.getValue(2));
6758 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
6759 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6760 Results.push_back(cpOutH.getValue(1));
6763 case ISD::ATOMIC_LOAD_ADD:
6764 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
6766 case ISD::ATOMIC_LOAD_AND:
6767 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
6769 case ISD::ATOMIC_LOAD_NAND:
6770 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
6772 case ISD::ATOMIC_LOAD_OR:
6773 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
6775 case ISD::ATOMIC_LOAD_SUB:
6776 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
6778 case ISD::ATOMIC_LOAD_XOR:
6779 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
6781 case ISD::ATOMIC_SWAP:
6782 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
6787 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
6789 default: return NULL;
6790 case X86ISD::BSF: return "X86ISD::BSF";
6791 case X86ISD::BSR: return "X86ISD::BSR";
6792 case X86ISD::SHLD: return "X86ISD::SHLD";
6793 case X86ISD::SHRD: return "X86ISD::SHRD";
6794 case X86ISD::FAND: return "X86ISD::FAND";
6795 case X86ISD::FOR: return "X86ISD::FOR";
6796 case X86ISD::FXOR: return "X86ISD::FXOR";
6797 case X86ISD::FSRL: return "X86ISD::FSRL";
6798 case X86ISD::FILD: return "X86ISD::FILD";
6799 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
6800 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
6801 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
6802 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
6803 case X86ISD::FLD: return "X86ISD::FLD";
6804 case X86ISD::FST: return "X86ISD::FST";
6805 case X86ISD::CALL: return "X86ISD::CALL";
6806 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
6807 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
6808 case X86ISD::BT: return "X86ISD::BT";
6809 case X86ISD::CMP: return "X86ISD::CMP";
6810 case X86ISD::COMI: return "X86ISD::COMI";
6811 case X86ISD::UCOMI: return "X86ISD::UCOMI";
6812 case X86ISD::SETCC: return "X86ISD::SETCC";
6813 case X86ISD::CMOV: return "X86ISD::CMOV";
6814 case X86ISD::BRCOND: return "X86ISD::BRCOND";
6815 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
6816 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
6817 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
6818 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
6819 case X86ISD::Wrapper: return "X86ISD::Wrapper";
6820 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
6821 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
6822 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6823 case X86ISD::PINSRB: return "X86ISD::PINSRB";
6824 case X86ISD::PINSRW: return "X86ISD::PINSRW";
6825 case X86ISD::FMAX: return "X86ISD::FMAX";
6826 case X86ISD::FMIN: return "X86ISD::FMIN";
6827 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
6828 case X86ISD::FRCP: return "X86ISD::FRCP";
6829 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
6830 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
6831 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
6832 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
6833 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
6834 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
6835 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
6836 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
6837 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
6838 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
6839 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
6840 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
6841 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
6842 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
6843 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
6844 case X86ISD::VSHL: return "X86ISD::VSHL";
6845 case X86ISD::VSRL: return "X86ISD::VSRL";
6846 case X86ISD::CMPPD: return "X86ISD::CMPPD";
6847 case X86ISD::CMPPS: return "X86ISD::CMPPS";
6848 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
6849 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
6850 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
6851 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
6852 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
6853 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
6854 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
6855 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
6856 case X86ISD::ADD: return "X86ISD::ADD";
6857 case X86ISD::SUB: return "X86ISD::SUB";
6858 case X86ISD::SMUL: return "X86ISD::SMUL";
6859 case X86ISD::UMUL: return "X86ISD::UMUL";
6863 // isLegalAddressingMode - Return true if the addressing mode represented
6864 // by AM is legal for this target, for a load/store of the specified type.
6865 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6866 const Type *Ty) const {
6867 // X86 supports extremely general addressing modes.
6869 // X86 allows a sign-extended 32-bit immediate field as a displacement.
6870 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
6874 // We can only fold this if we don't need an extra load.
6875 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
6877 // If BaseGV requires a register, we cannot also have a BaseReg.
6878 if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) &&
6882 // X86-64 only supports addr of globals in small code model.
6883 if (Subtarget->is64Bit()) {
6884 if (getTargetMachine().getCodeModel() != CodeModel::Small)
6886 // If lower 4G is not available, then we must use rip-relative addressing.
6887 if (AM.BaseOffs || AM.Scale > 1)
6898 // These scales always work.
6903 // These scales are formed with basereg+scalereg. Only accept if there is
6908 default: // Other stuff never works.
6916 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
6917 if (!Ty1->isInteger() || !Ty2->isInteger())
6919 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6920 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6921 if (NumBits1 <= NumBits2)
6923 return Subtarget->is64Bit() || NumBits1 < 64;
6926 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
6927 if (!VT1.isInteger() || !VT2.isInteger())
6929 unsigned NumBits1 = VT1.getSizeInBits();
6930 unsigned NumBits2 = VT2.getSizeInBits();
6931 if (NumBits1 <= NumBits2)
6933 return Subtarget->is64Bit() || NumBits1 < 64;
6936 /// isShuffleMaskLegal - Targets can use this to indicate that they only
6937 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
6938 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
6939 /// are assumed to be legal.
6941 X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
6942 // Only do shuffles on 128-bit vector types for now.
6943 if (VT.getSizeInBits() == 64) return false;
6944 return (Mask.getNode()->getNumOperands() <= 4 ||
6945 isIdentityMask(Mask.getNode()) ||
6946 isIdentityMask(Mask.getNode(), true) ||
6947 isSplatMask(Mask.getNode()) ||
6948 isPSHUFHW_PSHUFLWMask(Mask.getNode()) ||
6949 X86::isUNPCKLMask(Mask.getNode()) ||
6950 X86::isUNPCKHMask(Mask.getNode()) ||
6951 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
6952 X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
6956 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
6957 MVT EVT, SelectionDAG &DAG) const {
6958 unsigned NumElts = BVOps.size();
6959 // Only do shuffles on 128-bit vector types for now.
6960 if (EVT.getSizeInBits() * NumElts == 64) return false;
6961 if (NumElts == 2) return true;
6963 return (isMOVLMask(&BVOps[0], 4) ||
6964 isCommutedMOVL(&BVOps[0], 4, true) ||
6965 isSHUFPMask(&BVOps[0], 4) ||
6966 isCommutedSHUFP(&BVOps[0], 4));
6971 //===----------------------------------------------------------------------===//
6972 // X86 Scheduler Hooks
6973 //===----------------------------------------------------------------------===//
6975 // private utility function
6977 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
6978 MachineBasicBlock *MBB,
6986 TargetRegisterClass *RC,
6987 bool invSrc) const {
6988 // For the atomic bitwise operator, we generate
6991 // ld t1 = [bitinstr.addr]
6992 // op t2 = t1, [bitinstr.val]
6994 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6996 // fallthrough -->nextMBB
6997 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6998 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6999 MachineFunction::iterator MBBIter = MBB;
7002 /// First build the CFG
7003 MachineFunction *F = MBB->getParent();
7004 MachineBasicBlock *thisMBB = MBB;
7005 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7006 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7007 F->insert(MBBIter, newMBB);
7008 F->insert(MBBIter, nextMBB);
7010 // Move all successors to thisMBB to nextMBB
7011 nextMBB->transferSuccessors(thisMBB);
7013 // Update thisMBB to fall through to newMBB
7014 thisMBB->addSuccessor(newMBB);
7016 // newMBB jumps to itself and fall through to nextMBB
7017 newMBB->addSuccessor(nextMBB);
7018 newMBB->addSuccessor(newMBB);
7020 // Insert instructions into newMBB based on incoming instruction
7021 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
7022 DebugLoc dl = bInstr->getDebugLoc();
7023 MachineOperand& destOper = bInstr->getOperand(0);
7024 MachineOperand* argOpers[6];
7025 int numArgs = bInstr->getNumOperands() - 1;
7026 for (int i=0; i < numArgs; ++i)
7027 argOpers[i] = &bInstr->getOperand(i+1);
7029 // x86 address has 4 operands: base, index, scale, and displacement
7030 int lastAddrIndx = 3; // [0,3]
7033 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7034 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7035 for (int i=0; i <= lastAddrIndx; ++i)
7036 (*MIB).addOperand(*argOpers[i]);
7038 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7040 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7045 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7046 assert((argOpers[valArgIndx]->isReg() ||
7047 argOpers[valArgIndx]->isImm()) &&
7049 if (argOpers[valArgIndx]->isReg())
7050 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7052 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7054 (*MIB).addOperand(*argOpers[valArgIndx]);
7056 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7059 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7060 for (int i=0; i <= lastAddrIndx; ++i)
7061 (*MIB).addOperand(*argOpers[i]);
7063 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7064 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7066 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7070 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7072 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7076 // private utility function: 64 bit atomics on 32 bit host.
7078 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7079 MachineBasicBlock *MBB,
7084 bool invSrc) const {
7085 // For the atomic bitwise operator, we generate
7086 // thisMBB (instructions are in pairs, except cmpxchg8b)
7087 // ld t1,t2 = [bitinstr.addr]
7089 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7090 // op t5, t6 <- out1, out2, [bitinstr.val]
7091 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7092 // mov ECX, EBX <- t5, t6
7093 // mov EAX, EDX <- t1, t2
7094 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7095 // mov t3, t4 <- EAX, EDX
7097 // result in out1, out2
7098 // fallthrough -->nextMBB
7100 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7101 const unsigned LoadOpc = X86::MOV32rm;
7102 const unsigned copyOpc = X86::MOV32rr;
7103 const unsigned NotOpc = X86::NOT32r;
7104 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7105 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7106 MachineFunction::iterator MBBIter = MBB;
7109 /// First build the CFG
7110 MachineFunction *F = MBB->getParent();
7111 MachineBasicBlock *thisMBB = MBB;
7112 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7113 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7114 F->insert(MBBIter, newMBB);
7115 F->insert(MBBIter, nextMBB);
7117 // Move all successors to thisMBB to nextMBB
7118 nextMBB->transferSuccessors(thisMBB);
7120 // Update thisMBB to fall through to newMBB
7121 thisMBB->addSuccessor(newMBB);
7123 // newMBB jumps to itself and fall through to nextMBB
7124 newMBB->addSuccessor(nextMBB);
7125 newMBB->addSuccessor(newMBB);
7127 DebugLoc dl = bInstr->getDebugLoc();
7128 // Insert instructions into newMBB based on incoming instruction
7129 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7130 assert(bInstr->getNumOperands() < 18 && "unexpected number of operands");
7131 MachineOperand& dest1Oper = bInstr->getOperand(0);
7132 MachineOperand& dest2Oper = bInstr->getOperand(1);
7133 MachineOperand* argOpers[6];
7134 for (int i=0; i < 6; ++i)
7135 argOpers[i] = &bInstr->getOperand(i+2);
7137 // x86 address has 4 operands: base, index, scale, and displacement
7138 int lastAddrIndx = 3; // [0,3]
7140 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7141 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7142 for (int i=0; i <= lastAddrIndx; ++i)
7143 (*MIB).addOperand(*argOpers[i]);
7144 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7145 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7146 // add 4 to displacement.
7147 for (int i=0; i <= lastAddrIndx-1; ++i)
7148 (*MIB).addOperand(*argOpers[i]);
7149 MachineOperand newOp3 = *(argOpers[3]);
7151 newOp3.setImm(newOp3.getImm()+4);
7153 newOp3.setOffset(newOp3.getOffset()+4);
7154 (*MIB).addOperand(newOp3);
7156 // t3/4 are defined later, at the bottom of the loop
7157 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7158 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7159 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7160 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7161 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7162 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7164 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7165 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7167 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7168 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7174 assert((argOpers[4]->isReg() || argOpers[4]->isImm()) &&
7176 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7177 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7178 if (argOpers[4]->isReg())
7179 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7181 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7182 if (regOpcL != X86::MOV32rr)
7184 (*MIB).addOperand(*argOpers[4]);
7185 assert(argOpers[5]->isReg() == argOpers[4]->isReg());
7186 assert(argOpers[5]->isImm() == argOpers[4]->isImm());
7187 if (argOpers[5]->isReg())
7188 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7190 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7191 if (regOpcH != X86::MOV32rr)
7193 (*MIB).addOperand(*argOpers[5]);
7195 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7197 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7200 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7202 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7205 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7206 for (int i=0; i <= lastAddrIndx; ++i)
7207 (*MIB).addOperand(*argOpers[i]);
7209 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7210 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7212 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7213 MIB.addReg(X86::EAX);
7214 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7215 MIB.addReg(X86::EDX);
7218 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7220 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7224 // private utility function
7226 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7227 MachineBasicBlock *MBB,
7228 unsigned cmovOpc) const {
7229 // For the atomic min/max operator, we generate
7232 // ld t1 = [min/max.addr]
7233 // mov t2 = [min/max.val]
7235 // cmov[cond] t2 = t1
7237 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7239 // fallthrough -->nextMBB
7241 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7242 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7243 MachineFunction::iterator MBBIter = MBB;
7246 /// First build the CFG
7247 MachineFunction *F = MBB->getParent();
7248 MachineBasicBlock *thisMBB = MBB;
7249 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7250 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7251 F->insert(MBBIter, newMBB);
7252 F->insert(MBBIter, nextMBB);
7254 // Move all successors to thisMBB to nextMBB
7255 nextMBB->transferSuccessors(thisMBB);
7257 // Update thisMBB to fall through to newMBB
7258 thisMBB->addSuccessor(newMBB);
7260 // newMBB jumps to newMBB and fall through to nextMBB
7261 newMBB->addSuccessor(nextMBB);
7262 newMBB->addSuccessor(newMBB);
7264 DebugLoc dl = mInstr->getDebugLoc();
7265 // Insert instructions into newMBB based on incoming instruction
7266 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
7267 MachineOperand& destOper = mInstr->getOperand(0);
7268 MachineOperand* argOpers[6];
7269 int numArgs = mInstr->getNumOperands() - 1;
7270 for (int i=0; i < numArgs; ++i)
7271 argOpers[i] = &mInstr->getOperand(i+1);
7273 // x86 address has 4 operands: base, index, scale, and displacement
7274 int lastAddrIndx = 3; // [0,3]
7277 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7278 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7279 for (int i=0; i <= lastAddrIndx; ++i)
7280 (*MIB).addOperand(*argOpers[i]);
7282 // We only support register and immediate values
7283 assert((argOpers[valArgIndx]->isReg() ||
7284 argOpers[valArgIndx]->isImm()) &&
7287 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7288 if (argOpers[valArgIndx]->isReg())
7289 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7291 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7292 (*MIB).addOperand(*argOpers[valArgIndx]);
7294 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7297 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7302 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7303 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7307 // Cmp and exchange if none has modified the memory location
7308 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7309 for (int i=0; i <= lastAddrIndx; ++i)
7310 (*MIB).addOperand(*argOpers[i]);
7312 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7313 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
7315 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7316 MIB.addReg(X86::EAX);
7319 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7321 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7327 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7328 MachineBasicBlock *BB) const {
7329 DebugLoc dl = MI->getDebugLoc();
7330 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7331 switch (MI->getOpcode()) {
7332 default: assert(false && "Unexpected instr type to insert");
7333 case X86::CMOV_V1I64:
7334 case X86::CMOV_FR32:
7335 case X86::CMOV_FR64:
7336 case X86::CMOV_V4F32:
7337 case X86::CMOV_V2F64:
7338 case X86::CMOV_V2I64: {
7339 // To "insert" a SELECT_CC instruction, we actually have to insert the
7340 // diamond control-flow pattern. The incoming instruction knows the
7341 // destination vreg to set, the condition code register to branch on, the
7342 // true/false values to select between, and a branch opcode to use.
7343 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7344 MachineFunction::iterator It = BB;
7350 // cmpTY ccX, r1, r2
7352 // fallthrough --> copy0MBB
7353 MachineBasicBlock *thisMBB = BB;
7354 MachineFunction *F = BB->getParent();
7355 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7356 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7358 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7359 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
7360 F->insert(It, copy0MBB);
7361 F->insert(It, sinkMBB);
7362 // Update machine-CFG edges by transferring all successors of the current
7363 // block to the new block which will contain the Phi node for the select.
7364 sinkMBB->transferSuccessors(BB);
7366 // Add the true and fallthrough blocks as its successors.
7367 BB->addSuccessor(copy0MBB);
7368 BB->addSuccessor(sinkMBB);
7371 // %FalseValue = ...
7372 // # fallthrough to sinkMBB
7375 // Update machine-CFG edges
7376 BB->addSuccessor(sinkMBB);
7379 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7382 BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg())
7383 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7384 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7386 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7390 case X86::FP32_TO_INT16_IN_MEM:
7391 case X86::FP32_TO_INT32_IN_MEM:
7392 case X86::FP32_TO_INT64_IN_MEM:
7393 case X86::FP64_TO_INT16_IN_MEM:
7394 case X86::FP64_TO_INT32_IN_MEM:
7395 case X86::FP64_TO_INT64_IN_MEM:
7396 case X86::FP80_TO_INT16_IN_MEM:
7397 case X86::FP80_TO_INT32_IN_MEM:
7398 case X86::FP80_TO_INT64_IN_MEM: {
7399 // Change the floating point control register to use "round towards zero"
7400 // mode when truncating to an integer value.
7401 MachineFunction *F = BB->getParent();
7402 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7403 addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7405 // Load the old value of the high byte of the control word...
7407 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7408 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
7411 // Set the high part to be round to zero...
7412 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx)
7415 // Reload the modified control word now...
7416 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7418 // Restore the memory image of control word to original value
7419 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx)
7422 // Get the X86 opcode to use.
7424 switch (MI->getOpcode()) {
7425 default: assert(0 && "illegal opcode!");
7426 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7427 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7428 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7429 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7430 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7431 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7432 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7433 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7434 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7438 MachineOperand &Op = MI->getOperand(0);
7440 AM.BaseType = X86AddressMode::RegBase;
7441 AM.Base.Reg = Op.getReg();
7443 AM.BaseType = X86AddressMode::FrameIndexBase;
7444 AM.Base.FrameIndex = Op.getIndex();
7446 Op = MI->getOperand(1);
7448 AM.Scale = Op.getImm();
7449 Op = MI->getOperand(2);
7451 AM.IndexReg = Op.getImm();
7452 Op = MI->getOperand(3);
7453 if (Op.isGlobal()) {
7454 AM.GV = Op.getGlobal();
7456 AM.Disp = Op.getImm();
7458 addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
7459 .addReg(MI->getOperand(4).getReg());
7461 // Reload the original control word now.
7462 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7464 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7467 case X86::ATOMAND32:
7468 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7469 X86::AND32ri, X86::MOV32rm,
7470 X86::LCMPXCHG32, X86::MOV32rr,
7471 X86::NOT32r, X86::EAX,
7472 X86::GR32RegisterClass);
7474 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7475 X86::OR32ri, X86::MOV32rm,
7476 X86::LCMPXCHG32, X86::MOV32rr,
7477 X86::NOT32r, X86::EAX,
7478 X86::GR32RegisterClass);
7479 case X86::ATOMXOR32:
7480 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7481 X86::XOR32ri, X86::MOV32rm,
7482 X86::LCMPXCHG32, X86::MOV32rr,
7483 X86::NOT32r, X86::EAX,
7484 X86::GR32RegisterClass);
7485 case X86::ATOMNAND32:
7486 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7487 X86::AND32ri, X86::MOV32rm,
7488 X86::LCMPXCHG32, X86::MOV32rr,
7489 X86::NOT32r, X86::EAX,
7490 X86::GR32RegisterClass, true);
7491 case X86::ATOMMIN32:
7492 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7493 case X86::ATOMMAX32:
7494 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7495 case X86::ATOMUMIN32:
7496 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7497 case X86::ATOMUMAX32:
7498 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7500 case X86::ATOMAND16:
7501 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7502 X86::AND16ri, X86::MOV16rm,
7503 X86::LCMPXCHG16, X86::MOV16rr,
7504 X86::NOT16r, X86::AX,
7505 X86::GR16RegisterClass);
7507 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7508 X86::OR16ri, X86::MOV16rm,
7509 X86::LCMPXCHG16, X86::MOV16rr,
7510 X86::NOT16r, X86::AX,
7511 X86::GR16RegisterClass);
7512 case X86::ATOMXOR16:
7513 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7514 X86::XOR16ri, X86::MOV16rm,
7515 X86::LCMPXCHG16, X86::MOV16rr,
7516 X86::NOT16r, X86::AX,
7517 X86::GR16RegisterClass);
7518 case X86::ATOMNAND16:
7519 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7520 X86::AND16ri, X86::MOV16rm,
7521 X86::LCMPXCHG16, X86::MOV16rr,
7522 X86::NOT16r, X86::AX,
7523 X86::GR16RegisterClass, true);
7524 case X86::ATOMMIN16:
7525 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7526 case X86::ATOMMAX16:
7527 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7528 case X86::ATOMUMIN16:
7529 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7530 case X86::ATOMUMAX16:
7531 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7534 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7535 X86::AND8ri, X86::MOV8rm,
7536 X86::LCMPXCHG8, X86::MOV8rr,
7537 X86::NOT8r, X86::AL,
7538 X86::GR8RegisterClass);
7540 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7541 X86::OR8ri, X86::MOV8rm,
7542 X86::LCMPXCHG8, X86::MOV8rr,
7543 X86::NOT8r, X86::AL,
7544 X86::GR8RegisterClass);
7546 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7547 X86::XOR8ri, X86::MOV8rm,
7548 X86::LCMPXCHG8, X86::MOV8rr,
7549 X86::NOT8r, X86::AL,
7550 X86::GR8RegisterClass);
7551 case X86::ATOMNAND8:
7552 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7553 X86::AND8ri, X86::MOV8rm,
7554 X86::LCMPXCHG8, X86::MOV8rr,
7555 X86::NOT8r, X86::AL,
7556 X86::GR8RegisterClass, true);
7557 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7558 // This group is for 64-bit host.
7559 case X86::ATOMAND64:
7560 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7561 X86::AND64ri32, X86::MOV64rm,
7562 X86::LCMPXCHG64, X86::MOV64rr,
7563 X86::NOT64r, X86::RAX,
7564 X86::GR64RegisterClass);
7566 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7567 X86::OR64ri32, X86::MOV64rm,
7568 X86::LCMPXCHG64, X86::MOV64rr,
7569 X86::NOT64r, X86::RAX,
7570 X86::GR64RegisterClass);
7571 case X86::ATOMXOR64:
7572 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
7573 X86::XOR64ri32, X86::MOV64rm,
7574 X86::LCMPXCHG64, X86::MOV64rr,
7575 X86::NOT64r, X86::RAX,
7576 X86::GR64RegisterClass);
7577 case X86::ATOMNAND64:
7578 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7579 X86::AND64ri32, X86::MOV64rm,
7580 X86::LCMPXCHG64, X86::MOV64rr,
7581 X86::NOT64r, X86::RAX,
7582 X86::GR64RegisterClass, true);
7583 case X86::ATOMMIN64:
7584 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7585 case X86::ATOMMAX64:
7586 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7587 case X86::ATOMUMIN64:
7588 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7589 case X86::ATOMUMAX64:
7590 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
7592 // This group does 64-bit operations on a 32-bit host.
7593 case X86::ATOMAND6432:
7594 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7595 X86::AND32rr, X86::AND32rr,
7596 X86::AND32ri, X86::AND32ri,
7598 case X86::ATOMOR6432:
7599 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7600 X86::OR32rr, X86::OR32rr,
7601 X86::OR32ri, X86::OR32ri,
7603 case X86::ATOMXOR6432:
7604 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7605 X86::XOR32rr, X86::XOR32rr,
7606 X86::XOR32ri, X86::XOR32ri,
7608 case X86::ATOMNAND6432:
7609 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7610 X86::AND32rr, X86::AND32rr,
7611 X86::AND32ri, X86::AND32ri,
7613 case X86::ATOMADD6432:
7614 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7615 X86::ADD32rr, X86::ADC32rr,
7616 X86::ADD32ri, X86::ADC32ri,
7618 case X86::ATOMSUB6432:
7619 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7620 X86::SUB32rr, X86::SBB32rr,
7621 X86::SUB32ri, X86::SBB32ri,
7623 case X86::ATOMSWAP6432:
7624 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7625 X86::MOV32rr, X86::MOV32rr,
7626 X86::MOV32ri, X86::MOV32ri,
7631 //===----------------------------------------------------------------------===//
7632 // X86 Optimization Hooks
7633 //===----------------------------------------------------------------------===//
7635 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7639 const SelectionDAG &DAG,
7640 unsigned Depth) const {
7641 unsigned Opc = Op.getOpcode();
7642 assert((Opc >= ISD::BUILTIN_OP_END ||
7643 Opc == ISD::INTRINSIC_WO_CHAIN ||
7644 Opc == ISD::INTRINSIC_W_CHAIN ||
7645 Opc == ISD::INTRINSIC_VOID) &&
7646 "Should use MaskedValueIsZero if you don't know whether Op"
7647 " is a target node!");
7649 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7656 // These nodes' second result is a boolean.
7657 if (Op.getResNo() == 0)
7661 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7662 Mask.getBitWidth() - 1);
7667 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7668 /// node is a GlobalAddress + offset.
7669 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7670 GlobalValue* &GA, int64_t &Offset) const{
7671 if (N->getOpcode() == X86ISD::Wrapper) {
7672 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
7673 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
7674 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
7678 return TargetLowering::isGAPlusOffset(N, GA, Offset);
7681 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7682 const TargetLowering &TLI) {
7685 if (TLI.isGAPlusOffset(Base, GV, Offset))
7686 return (GV->getAlignment() >= N && (Offset % N) == 0);
7687 // DAG combine handles the stack object case.
7691 static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
7692 unsigned NumElems, MVT EVT,
7694 SelectionDAG &DAG, MachineFrameInfo *MFI,
7695 const TargetLowering &TLI) {
7697 for (unsigned i = 0; i < NumElems; ++i) {
7698 SDValue Idx = PermMask.getOperand(i);
7699 if (Idx.getOpcode() == ISD::UNDEF) {
7705 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7706 if (!Elt.getNode() ||
7707 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7710 Base = Elt.getNode();
7711 if (Base->getOpcode() == ISD::UNDEF)
7715 if (Elt.getOpcode() == ISD::UNDEF)
7718 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
7719 EVT.getSizeInBits()/8, i, MFI))
7725 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7726 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7727 /// if the load addresses are consecutive, non-overlapping, and in the right
7729 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7730 const TargetLowering &TLI) {
7731 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7732 DebugLoc dl = N->getDebugLoc();
7733 MVT VT = N->getValueType(0);
7734 MVT EVT = VT.getVectorElementType();
7735 SDValue PermMask = N->getOperand(2);
7736 unsigned NumElems = PermMask.getNumOperands();
7737 SDNode *Base = NULL;
7738 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
7742 LoadSDNode *LD = cast<LoadSDNode>(Base);
7743 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
7744 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
7745 LD->getSrcValue(), LD->getSrcValueOffset(),
7747 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
7748 LD->getSrcValue(), LD->getSrcValueOffset(),
7749 LD->isVolatile(), LD->getAlignment());
7752 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
7753 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
7754 TargetLowering::DAGCombinerInfo &DCI,
7755 const X86Subtarget *Subtarget,
7756 const TargetLowering &TLI) {
7757 unsigned NumOps = N->getNumOperands();
7758 DebugLoc dl = N->getDebugLoc();
7760 // Ignore single operand BUILD_VECTOR.
7764 MVT VT = N->getValueType(0);
7765 MVT EVT = VT.getVectorElementType();
7766 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
7767 // We are looking for load i64 and zero extend. We want to transform
7768 // it before legalizer has a chance to expand it. Also look for i64
7769 // BUILD_PAIR bit casted to f64.
7771 // This must be an insertion into a zero vector.
7772 SDValue HighElt = N->getOperand(1);
7773 if (!isZeroNode(HighElt))
7776 // Value must be a load.
7777 SDNode *Base = N->getOperand(0).getNode();
7778 if (!isa<LoadSDNode>(Base)) {
7779 if (Base->getOpcode() != ISD::BIT_CONVERT)
7781 Base = Base->getOperand(0).getNode();
7782 if (!isa<LoadSDNode>(Base))
7786 // Transform it into VZEXT_LOAD addr.
7787 LoadSDNode *LD = cast<LoadSDNode>(Base);
7789 // Load must not be an extload.
7790 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
7793 // Load type should legal type so we don't have to legalize it.
7794 if (!TLI.isTypeLegal(VT))
7797 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
7798 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
7799 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
7800 TargetLowering::TargetLoweringOpt TLO(DAG);
7801 TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1));
7802 DCI.CommitTargetLoweringOpt(TLO);
7806 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
7807 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
7808 const X86Subtarget *Subtarget) {
7809 DebugLoc dl = N->getDebugLoc();
7810 SDValue Cond = N->getOperand(0);
7812 // If we have SSE[12] support, try to form min/max nodes.
7813 if (Subtarget->hasSSE2() &&
7814 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
7815 if (Cond.getOpcode() == ISD::SETCC) {
7816 // Get the LHS/RHS of the select.
7817 SDValue LHS = N->getOperand(1);
7818 SDValue RHS = N->getOperand(2);
7819 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
7821 unsigned Opcode = 0;
7822 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
7825 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
7828 if (!UnsafeFPMath) break;
7830 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
7832 Opcode = X86ISD::FMIN;
7835 case ISD::SETOGT: // (X > Y) ? X : Y -> max
7838 if (!UnsafeFPMath) break;
7840 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
7842 Opcode = X86ISD::FMAX;
7845 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
7848 case ISD::SETOGT: // (X > Y) ? Y : X -> min
7851 if (!UnsafeFPMath) break;
7853 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
7855 Opcode = X86ISD::FMIN;
7858 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
7861 if (!UnsafeFPMath) break;
7863 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
7865 Opcode = X86ISD::FMAX;
7871 return DAG.getNode(Opcode, dl, N->getValueType(0), LHS, RHS);
7879 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
7881 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
7882 const X86Subtarget *Subtarget) {
7883 // On X86 with SSE2 support, we can transform this to a vector shift if
7884 // all elements are shifted by the same amount. We can't do this in legalize
7885 // because the a constant vector is typically transformed to a constant pool
7886 // so we have no knowledge of the shift amount.
7887 if (!Subtarget->hasSSE2())
7890 MVT VT = N->getValueType(0);
7891 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
7894 SDValue ShAmtOp = N->getOperand(1);
7895 MVT EltVT = VT.getVectorElementType();
7896 DebugLoc dl = N->getDebugLoc();
7898 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
7899 unsigned NumElts = VT.getVectorNumElements();
7901 for (; i != NumElts; ++i) {
7902 SDValue Arg = ShAmtOp.getOperand(i);
7903 if (Arg.getOpcode() == ISD::UNDEF) continue;
7907 for (; i != NumElts; ++i) {
7908 SDValue Arg = ShAmtOp.getOperand(i);
7909 if (Arg.getOpcode() == ISD::UNDEF) continue;
7910 if (Arg != BaseShAmt) {
7914 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
7915 isSplatMask(ShAmtOp.getOperand(2).getNode())) {
7916 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ShAmtOp,
7917 DAG.getIntPtrConstant(0));
7921 if (EltVT.bitsGT(MVT::i32))
7922 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
7923 else if (EltVT.bitsLT(MVT::i32))
7924 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BaseShAmt);
7926 // The shift amount is identical so we can do a vector shift.
7927 SDValue ValOp = N->getOperand(0);
7928 switch (N->getOpcode()) {
7930 assert(0 && "Unknown shift opcode!");
7933 if (VT == MVT::v2i64)
7934 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7935 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7937 if (VT == MVT::v4i32)
7938 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7939 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
7941 if (VT == MVT::v8i16)
7942 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7943 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
7947 if (VT == MVT::v4i32)
7948 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7949 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
7951 if (VT == MVT::v8i16)
7952 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7953 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
7957 if (VT == MVT::v2i64)
7958 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7959 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7961 if (VT == MVT::v4i32)
7962 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7963 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
7965 if (VT == MVT::v8i16)
7966 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7967 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
7974 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
7975 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
7976 const X86Subtarget *Subtarget) {
7977 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
7978 // the FP state in cases where an emms may be missing.
7979 // A preferable solution to the general problem is to figure out the right
7980 // places to insert EMMS. This qualifies as a quick hack.
7981 StoreSDNode *St = cast<StoreSDNode>(N);
7982 if (St->getValue().getValueType().isVector() &&
7983 St->getValue().getValueType().getSizeInBits() == 64 &&
7984 isa<LoadSDNode>(St->getValue()) &&
7985 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
7986 St->getChain().hasOneUse() && !St->isVolatile()) {
7987 SDNode* LdVal = St->getValue().getNode();
7989 int TokenFactorIndex = -1;
7990 SmallVector<SDValue, 8> Ops;
7991 SDNode* ChainVal = St->getChain().getNode();
7992 // Must be a store of a load. We currently handle two cases: the load
7993 // is a direct child, and it's under an intervening TokenFactor. It is
7994 // possible to dig deeper under nested TokenFactors.
7995 if (ChainVal == LdVal)
7996 Ld = cast<LoadSDNode>(St->getChain());
7997 else if (St->getValue().hasOneUse() &&
7998 ChainVal->getOpcode() == ISD::TokenFactor) {
7999 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
8000 if (ChainVal->getOperand(i).getNode() == LdVal) {
8001 TokenFactorIndex = i;
8002 Ld = cast<LoadSDNode>(St->getValue());
8004 Ops.push_back(ChainVal->getOperand(i));
8008 DebugLoc dl = N->getDebugLoc();
8009 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
8010 if (Subtarget->is64Bit()) {
8011 SDValue NewLd = DAG.getLoad(MVT::i64, dl, Ld->getChain(),
8012 Ld->getBasePtr(), Ld->getSrcValue(),
8013 Ld->getSrcValueOffset(), Ld->isVolatile(),
8014 Ld->getAlignment());
8015 SDValue NewChain = NewLd.getValue(1);
8016 if (TokenFactorIndex != -1) {
8017 Ops.push_back(NewChain);
8018 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0],
8021 return DAG.getStore(NewChain, dl, NewLd, St->getBasePtr(),
8022 St->getSrcValue(), St->getSrcValueOffset(),
8023 St->isVolatile(), St->getAlignment());
8026 // Otherwise, lower to two 32-bit copies.
8027 SDValue LoAddr = Ld->getBasePtr();
8028 SDValue HiAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, LoAddr,
8029 DAG.getConstant(4, MVT::i32));
8031 SDValue LoLd = DAG.getLoad(MVT::i32, dl, Ld->getChain(), LoAddr,
8032 Ld->getSrcValue(), Ld->getSrcValueOffset(),
8033 Ld->isVolatile(), Ld->getAlignment());
8034 SDValue HiLd = DAG.getLoad(MVT::i32, dl, Ld->getChain(), HiAddr,
8035 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
8037 MinAlign(Ld->getAlignment(), 4));
8039 SDValue NewChain = LoLd.getValue(1);
8040 if (TokenFactorIndex != -1) {
8041 Ops.push_back(LoLd);
8042 Ops.push_back(HiLd);
8043 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Ops[0],
8047 LoAddr = St->getBasePtr();
8048 HiAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, LoAddr,
8049 DAG.getConstant(4, MVT::i32));
8051 SDValue LoSt = DAG.getStore(NewChain, dl, LoLd, LoAddr,
8052 St->getSrcValue(), St->getSrcValueOffset(),
8053 St->isVolatile(), St->getAlignment());
8054 SDValue HiSt = DAG.getStore(NewChain, dl, HiLd, HiAddr,
8056 St->getSrcValueOffset() + 4,
8058 MinAlign(St->getAlignment(), 4));
8059 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoSt, HiSt);
8065 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
8066 /// X86ISD::FXOR nodes.
8067 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
8068 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
8069 // F[X]OR(0.0, x) -> x
8070 // F[X]OR(x, 0.0) -> x
8071 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8072 if (C->getValueAPF().isPosZero())
8073 return N->getOperand(1);
8074 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8075 if (C->getValueAPF().isPosZero())
8076 return N->getOperand(0);
8080 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
8081 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
8082 // FAND(0.0, x) -> 0.0
8083 // FAND(x, 0.0) -> 0.0
8084 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8085 if (C->getValueAPF().isPosZero())
8086 return N->getOperand(0);
8087 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8088 if (C->getValueAPF().isPosZero())
8089 return N->getOperand(1);
8093 static SDValue PerformBTCombine(SDNode *N,
8095 TargetLowering::DAGCombinerInfo &DCI) {
8096 // BT ignores high bits in the bit index operand.
8097 SDValue Op1 = N->getOperand(1);
8098 if (Op1.hasOneUse()) {
8099 unsigned BitWidth = Op1.getValueSizeInBits();
8100 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
8101 APInt KnownZero, KnownOne;
8102 TargetLowering::TargetLoweringOpt TLO(DAG);
8103 TargetLowering &TLI = DAG.getTargetLoweringInfo();
8104 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
8105 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
8106 DCI.CommitTargetLoweringOpt(TLO);
8111 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
8112 DAGCombinerInfo &DCI) const {
8113 SelectionDAG &DAG = DCI.DAG;
8114 switch (N->getOpcode()) {
8116 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
8117 case ISD::BUILD_VECTOR:
8118 return PerformBuildVectorCombine(N, DAG, DCI, Subtarget, *this);
8119 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
8122 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
8123 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
8125 case X86ISD::FOR: return PerformFORCombine(N, DAG);
8126 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
8127 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
8133 //===----------------------------------------------------------------------===//
8134 // X86 Inline Assembly Support
8135 //===----------------------------------------------------------------------===//
8137 /// getConstraintType - Given a constraint letter, return the type of
8138 /// constraint it is for this target.
8139 X86TargetLowering::ConstraintType
8140 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
8141 if (Constraint.size() == 1) {
8142 switch (Constraint[0]) {
8154 return C_RegisterClass;
8159 return TargetLowering::getConstraintType(Constraint);
8162 /// LowerXConstraint - try to replace an X constraint, which matches anything,
8163 /// with another that has more specific requirements based on the type of the
8164 /// corresponding operand.
8165 const char *X86TargetLowering::
8166 LowerXConstraint(MVT ConstraintVT) const {
8167 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
8168 // 'f' like normal targets.
8169 if (ConstraintVT.isFloatingPoint()) {
8170 if (Subtarget->hasSSE2())
8172 if (Subtarget->hasSSE1())
8176 return TargetLowering::LowerXConstraint(ConstraintVT);
8179 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8180 /// vector. If it is invalid, don't add anything to Ops.
8181 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8184 std::vector<SDValue>&Ops,
8185 SelectionDAG &DAG) const {
8186 SDValue Result(0, 0);
8188 switch (Constraint) {
8191 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8192 if (C->getZExtValue() <= 31) {
8193 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8199 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8200 if (C->getZExtValue() <= 63) {
8201 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8207 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8208 if (C->getZExtValue() <= 255) {
8209 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8215 // Literal immediates are always ok.
8216 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
8217 Result = DAG.getTargetConstant(CST->getZExtValue(), Op.getValueType());
8221 // If we are in non-pic codegen mode, we allow the address of a global (with
8222 // an optional displacement) to be used with 'i'.
8223 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
8226 // Match either (GA) or (GA+C)
8228 Offset = GA->getOffset();
8229 } else if (Op.getOpcode() == ISD::ADD) {
8230 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8231 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
8233 Offset = GA->getOffset()+C->getZExtValue();
8235 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8236 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
8238 Offset = GA->getOffset()+C->getZExtValue();
8246 Op = LowerGlobalAddress(GA->getGlobal(), Op.getDebugLoc(),
8249 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
8255 // Otherwise, not valid for this mode.
8260 if (Result.getNode()) {
8261 Ops.push_back(Result);
8264 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
8268 std::vector<unsigned> X86TargetLowering::
8269 getRegClassForInlineAsmConstraint(const std::string &Constraint,
8271 if (Constraint.size() == 1) {
8272 // FIXME: not handling fp-stack yet!
8273 switch (Constraint[0]) { // GCC X86 Constraint Letters
8274 default: break; // Unknown constraint letter
8275 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
8278 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
8279 else if (VT == MVT::i16)
8280 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
8281 else if (VT == MVT::i8)
8282 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
8283 else if (VT == MVT::i64)
8284 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
8289 return std::vector<unsigned>();
8292 std::pair<unsigned, const TargetRegisterClass*>
8293 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8295 // First, see if this is a constraint that directly corresponds to an LLVM
8297 if (Constraint.size() == 1) {
8298 // GCC Constraint Letters
8299 switch (Constraint[0]) {
8301 case 'r': // GENERAL_REGS
8302 case 'R': // LEGACY_REGS
8303 case 'l': // INDEX_REGS
8305 return std::make_pair(0U, X86::GR8RegisterClass);
8307 return std::make_pair(0U, X86::GR16RegisterClass);
8308 if (VT == MVT::i32 || !Subtarget->is64Bit())
8309 return std::make_pair(0U, X86::GR32RegisterClass);
8310 return std::make_pair(0U, X86::GR64RegisterClass);
8311 case 'f': // FP Stack registers.
8312 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
8313 // value to the correct fpstack register class.
8314 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
8315 return std::make_pair(0U, X86::RFP32RegisterClass);
8316 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
8317 return std::make_pair(0U, X86::RFP64RegisterClass);
8318 return std::make_pair(0U, X86::RFP80RegisterClass);
8319 case 'y': // MMX_REGS if MMX allowed.
8320 if (!Subtarget->hasMMX()) break;
8321 return std::make_pair(0U, X86::VR64RegisterClass);
8322 case 'Y': // SSE_REGS if SSE2 allowed
8323 if (!Subtarget->hasSSE2()) break;
8325 case 'x': // SSE_REGS if SSE1 allowed
8326 if (!Subtarget->hasSSE1()) break;
8328 switch (VT.getSimpleVT()) {
8330 // Scalar SSE types.
8333 return std::make_pair(0U, X86::FR32RegisterClass);
8336 return std::make_pair(0U, X86::FR64RegisterClass);
8344 return std::make_pair(0U, X86::VR128RegisterClass);
8350 // Use the default implementation in TargetLowering to convert the register
8351 // constraint into a member of a register class.
8352 std::pair<unsigned, const TargetRegisterClass*> Res;
8353 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8355 // Not found as a standard register?
8356 if (Res.second == 0) {
8357 // GCC calls "st(0)" just plain "st".
8358 if (StringsEqualNoCase("{st}", Constraint)) {
8359 Res.first = X86::ST0;
8360 Res.second = X86::RFP80RegisterClass;
8362 // 'A' means EAX + EDX.
8363 if (Constraint == "A") {
8364 Res.first = X86::EAX;
8365 Res.second = X86::GRADRegisterClass;
8370 // Otherwise, check to see if this is a register class of the wrong value
8371 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
8372 // turn into {ax},{dx}.
8373 if (Res.second->hasType(VT))
8374 return Res; // Correct type already, nothing to do.
8376 // All of the single-register GCC register classes map their values onto
8377 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
8378 // really want an 8-bit or 32-bit register, map to the appropriate register
8379 // class and return the appropriate register.
8380 if (Res.second == X86::GR16RegisterClass) {
8381 if (VT == MVT::i8) {
8382 unsigned DestReg = 0;
8383 switch (Res.first) {
8385 case X86::AX: DestReg = X86::AL; break;
8386 case X86::DX: DestReg = X86::DL; break;
8387 case X86::CX: DestReg = X86::CL; break;
8388 case X86::BX: DestReg = X86::BL; break;
8391 Res.first = DestReg;
8392 Res.second = Res.second = X86::GR8RegisterClass;
8394 } else if (VT == MVT::i32) {
8395 unsigned DestReg = 0;
8396 switch (Res.first) {
8398 case X86::AX: DestReg = X86::EAX; break;
8399 case X86::DX: DestReg = X86::EDX; break;
8400 case X86::CX: DestReg = X86::ECX; break;
8401 case X86::BX: DestReg = X86::EBX; break;
8402 case X86::SI: DestReg = X86::ESI; break;
8403 case X86::DI: DestReg = X86::EDI; break;
8404 case X86::BP: DestReg = X86::EBP; break;
8405 case X86::SP: DestReg = X86::ESP; break;
8408 Res.first = DestReg;
8409 Res.second = Res.second = X86::GR32RegisterClass;
8411 } else if (VT == MVT::i64) {
8412 unsigned DestReg = 0;
8413 switch (Res.first) {
8415 case X86::AX: DestReg = X86::RAX; break;
8416 case X86::DX: DestReg = X86::RDX; break;
8417 case X86::CX: DestReg = X86::RCX; break;
8418 case X86::BX: DestReg = X86::RBX; break;
8419 case X86::SI: DestReg = X86::RSI; break;
8420 case X86::DI: DestReg = X86::RDI; break;
8421 case X86::BP: DestReg = X86::RBP; break;
8422 case X86::SP: DestReg = X86::RSP; break;
8425 Res.first = DestReg;
8426 Res.second = Res.second = X86::GR64RegisterClass;
8429 } else if (Res.second == X86::FR32RegisterClass ||
8430 Res.second == X86::FR64RegisterClass ||
8431 Res.second == X86::VR128RegisterClass) {
8432 // Handle references to XMM physical registers that got mapped into the
8433 // wrong class. This can happen with constraints like {xmm0} where the
8434 // target independent register mapper will just pick the first match it can
8435 // find, ignoring the required type.
8437 Res.second = X86::FR32RegisterClass;
8438 else if (VT == MVT::f64)
8439 Res.second = X86::FR64RegisterClass;
8440 else if (X86::VR128RegisterClass->hasType(VT))
8441 Res.second = X86::VR128RegisterClass;
8447 //===----------------------------------------------------------------------===//
8448 // X86 Widen vector type
8449 //===----------------------------------------------------------------------===//
8451 /// getWidenVectorType: given a vector type, returns the type to widen
8452 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
8453 /// If there is no vector type that we want to widen to, returns MVT::Other
8454 /// When and where to widen is target dependent based on the cost of
8455 /// scalarizing vs using the wider vector type.
8457 MVT X86TargetLowering::getWidenVectorType(MVT VT) const {
8458 assert(VT.isVector());
8459 if (isTypeLegal(VT))
8462 // TODO: In computeRegisterProperty, we can compute the list of legal vector
8463 // type based on element type. This would speed up our search (though
8464 // it may not be worth it since the size of the list is relatively
8466 MVT EltVT = VT.getVectorElementType();
8467 unsigned NElts = VT.getVectorNumElements();
8469 // On X86, it make sense to widen any vector wider than 1
8473 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
8474 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
8475 MVT SVT = (MVT::SimpleValueType)nVT;
8477 if (isTypeLegal(SVT) &&
8478 SVT.getVectorElementType() == EltVT &&
8479 SVT.getVectorNumElements() > NElts)