1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86MCTargetExpr.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
53 STATISTIC(NumTailCalls, "Number of tail calls");
56 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
58 // Disable16Bit - 16-bit operations typically have a larger encoding than
59 // corresponding 32-bit instructions, and 16-bit code is slow on some
60 // processors. This is an experimental flag to disable 16-bit operations
61 // (which forces them to be Legalized to 32-bit operations).
63 Disable16Bit("disable-16bit", cl::Hidden,
64 cl::desc("Disable use of 16-bit instructions"));
66 // Forward declarations.
67 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
70 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
71 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
72 default: llvm_unreachable("unknown subtarget type");
73 case X86Subtarget::isDarwin:
74 if (TM.getSubtarget<X86Subtarget>().is64Bit())
75 return new X8664_MachoTargetObjectFile();
76 return new X8632_MachoTargetObjectFile();
77 case X86Subtarget::isELF:
78 return new TargetLoweringObjectFileELF();
79 case X86Subtarget::isMingw:
80 case X86Subtarget::isCygwin:
81 case X86Subtarget::isWindows:
82 return new TargetLoweringObjectFileCOFF();
87 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
88 : TargetLowering(TM, createTLOF(TM)) {
89 Subtarget = &TM.getSubtarget<X86Subtarget>();
90 X86ScalarSSEf64 = Subtarget->hasSSE2();
91 X86ScalarSSEf32 = Subtarget->hasSSE1();
92 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
94 RegInfo = TM.getRegisterInfo();
97 // Set up the TargetLowering object.
99 // X86 is weird, it always uses i8 for shift amounts and setcc results.
100 setShiftAmountType(MVT::i8);
101 setBooleanContents(ZeroOrOneBooleanContent);
102 setSchedulingPreference(SchedulingForRegPressure);
103 setStackPointerRegisterToSaveRestore(X86StackPtr);
105 if (Subtarget->isTargetDarwin()) {
106 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
107 setUseUnderscoreSetJmp(false);
108 setUseUnderscoreLongJmp(false);
109 } else if (Subtarget->isTargetMingw()) {
110 // MS runtime is weird: it exports _setjmp, but longjmp!
111 setUseUnderscoreSetJmp(true);
112 setUseUnderscoreLongJmp(false);
114 setUseUnderscoreSetJmp(true);
115 setUseUnderscoreLongJmp(true);
118 // Set up the register classes.
119 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
121 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
122 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
123 if (Subtarget->is64Bit())
124 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
126 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
128 // We don't accept any truncstore of integer registers.
129 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
131 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
132 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
134 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
135 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
136 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
138 // SETOEQ and SETUNE require checking two conditions.
139 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
140 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
141 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
142 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
143 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
144 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
146 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
148 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
149 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
150 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
152 if (Subtarget->is64Bit()) {
153 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
154 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
155 } else if (!UseSoftFloat) {
156 if (X86ScalarSSEf64) {
157 // We have an impenetrably clever algorithm for ui64->double only.
158 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
160 // We have an algorithm for SSE2, and we turn this into a 64-bit
161 // FILD for other targets.
162 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
165 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
167 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
168 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
171 // SSE has no i16 to fp conversion, only i32
172 if (X86ScalarSSEf32) {
173 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
174 // f32 and f64 cases are Legal, f80 case is not
175 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
177 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
178 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
181 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
182 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
185 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
186 // are Legal, f80 is custom lowered.
187 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
188 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
190 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
192 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
193 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
195 if (X86ScalarSSEf32) {
196 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
197 // f32 and f64 cases are Legal, f80 case is not
198 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
200 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
201 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
204 // Handle FP_TO_UINT by promoting the destination to a larger signed
206 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
207 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
208 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
210 if (Subtarget->is64Bit()) {
211 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
212 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
213 } else if (!UseSoftFloat) {
214 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
215 // Expand FP_TO_UINT into a select.
216 // FIXME: We would like to use a Custom expander here eventually to do
217 // the optimal thing for SSE vs. the default expansion in the legalizer.
218 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
220 // With SSE3 we can use fisttpll to convert to a signed i64; without
221 // SSE, we're stuck with a fistpll.
222 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
225 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
226 if (!X86ScalarSSEf64) {
227 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
228 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
231 // Scalar integer divide and remainder are lowered to use operations that
232 // produce two results, to match the available instructions. This exposes
233 // the two-result form to trivial CSE, which is able to combine x/y and x%y
234 // into a single instruction.
236 // Scalar integer multiply-high is also lowered to use two-result
237 // operations, to match the available instructions. However, plain multiply
238 // (low) operations are left as Legal, as there are single-result
239 // instructions for this in x86. Using the two-result multiply instructions
240 // when both high and low results are needed must be arranged by dagcombine.
241 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
242 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
243 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
244 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
245 setOperationAction(ISD::SREM , MVT::i8 , Expand);
246 setOperationAction(ISD::UREM , MVT::i8 , Expand);
247 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
248 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
249 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
250 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
251 setOperationAction(ISD::SREM , MVT::i16 , Expand);
252 setOperationAction(ISD::UREM , MVT::i16 , Expand);
253 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
254 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
255 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
256 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
257 setOperationAction(ISD::SREM , MVT::i32 , Expand);
258 setOperationAction(ISD::UREM , MVT::i32 , Expand);
259 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
260 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
261 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
262 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
263 setOperationAction(ISD::SREM , MVT::i64 , Expand);
264 setOperationAction(ISD::UREM , MVT::i64 , Expand);
266 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
267 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
268 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
269 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
270 if (Subtarget->is64Bit())
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
273 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
275 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
276 setOperationAction(ISD::FREM , MVT::f32 , Expand);
277 setOperationAction(ISD::FREM , MVT::f64 , Expand);
278 setOperationAction(ISD::FREM , MVT::f80 , Expand);
279 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
281 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
282 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
283 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
286 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
287 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
292 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
293 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
294 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
295 if (Subtarget->is64Bit()) {
296 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
297 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
298 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
301 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
302 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
304 // These should be promoted to a larger select which is supported.
305 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
306 // X86 wants to expand cmov itself.
307 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
309 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
311 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
312 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
313 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
314 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
315 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
316 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
318 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
320 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
321 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
322 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
323 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
324 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
325 if (Subtarget->is64Bit()) {
326 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
327 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
329 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
332 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
333 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
334 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
335 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
336 if (Subtarget->is64Bit())
337 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
338 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
339 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
340 if (Subtarget->is64Bit()) {
341 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
342 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
343 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
344 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
345 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
347 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
348 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
349 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
350 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
351 if (Subtarget->is64Bit()) {
352 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
353 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
354 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
357 if (Subtarget->hasSSE1())
358 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
360 if (!Subtarget->hasSSE2())
361 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
363 // Expand certain atomics
364 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
365 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
366 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
374 if (!Subtarget->is64Bit()) {
375 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
376 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
377 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
378 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
379 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
380 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
381 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
384 // FIXME - use subtarget debug flags
385 if (!Subtarget->isTargetDarwin() &&
386 !Subtarget->isTargetELF() &&
387 !Subtarget->isTargetCygMing()) {
388 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
391 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
392 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
393 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
394 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
395 if (Subtarget->is64Bit()) {
396 setExceptionPointerRegister(X86::RAX);
397 setExceptionSelectorRegister(X86::RDX);
399 setExceptionPointerRegister(X86::EAX);
400 setExceptionSelectorRegister(X86::EDX);
402 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
403 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
405 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
407 setOperationAction(ISD::TRAP, MVT::Other, Legal);
409 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
410 setOperationAction(ISD::VASTART , MVT::Other, Custom);
411 setOperationAction(ISD::VAEND , MVT::Other, Expand);
412 if (Subtarget->is64Bit()) {
413 setOperationAction(ISD::VAARG , MVT::Other, Custom);
414 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
416 setOperationAction(ISD::VAARG , MVT::Other, Expand);
417 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
420 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
421 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
422 if (Subtarget->is64Bit())
423 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
424 if (Subtarget->isTargetCygMing())
425 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
427 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
429 if (!UseSoftFloat && X86ScalarSSEf64) {
430 // f32 and f64 use SSE.
431 // Set up the FP register classes.
432 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
433 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
435 // Use ANDPD to simulate FABS.
436 setOperationAction(ISD::FABS , MVT::f64, Custom);
437 setOperationAction(ISD::FABS , MVT::f32, Custom);
439 // Use XORP to simulate FNEG.
440 setOperationAction(ISD::FNEG , MVT::f64, Custom);
441 setOperationAction(ISD::FNEG , MVT::f32, Custom);
443 // Use ANDPD and ORPD to simulate FCOPYSIGN.
444 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
445 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
447 // We don't support sin/cos/fmod
448 setOperationAction(ISD::FSIN , MVT::f64, Expand);
449 setOperationAction(ISD::FCOS , MVT::f64, Expand);
450 setOperationAction(ISD::FSIN , MVT::f32, Expand);
451 setOperationAction(ISD::FCOS , MVT::f32, Expand);
453 // Expand FP immediates into loads from the stack, except for the special
455 addLegalFPImmediate(APFloat(+0.0)); // xorpd
456 addLegalFPImmediate(APFloat(+0.0f)); // xorps
457 } else if (!UseSoftFloat && X86ScalarSSEf32) {
458 // Use SSE for f32, x87 for f64.
459 // Set up the FP register classes.
460 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
461 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
463 // Use ANDPS to simulate FABS.
464 setOperationAction(ISD::FABS , MVT::f32, Custom);
466 // Use XORP to simulate FNEG.
467 setOperationAction(ISD::FNEG , MVT::f32, Custom);
469 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
471 // Use ANDPS and ORPS to simulate FCOPYSIGN.
472 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
473 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
475 // We don't support sin/cos/fmod
476 setOperationAction(ISD::FSIN , MVT::f32, Expand);
477 setOperationAction(ISD::FCOS , MVT::f32, Expand);
479 // Special cases we handle for FP constants.
480 addLegalFPImmediate(APFloat(+0.0f)); // xorps
481 addLegalFPImmediate(APFloat(+0.0)); // FLD0
482 addLegalFPImmediate(APFloat(+1.0)); // FLD1
483 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
484 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
487 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
488 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
490 } else if (!UseSoftFloat) {
491 // f32 and f64 in x87.
492 // Set up the FP register classes.
493 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
494 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
496 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
497 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
498 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
499 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
502 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
503 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
505 addLegalFPImmediate(APFloat(+0.0)); // FLD0
506 addLegalFPImmediate(APFloat(+1.0)); // FLD1
507 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
508 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
509 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
510 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
511 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
512 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
515 // Long double always uses X87.
517 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
518 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
519 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
522 APFloat TmpFlt(+0.0);
523 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
525 addLegalFPImmediate(TmpFlt); // FLD0
527 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
528 APFloat TmpFlt2(+1.0);
529 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
531 addLegalFPImmediate(TmpFlt2); // FLD1
532 TmpFlt2.changeSign();
533 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
537 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
538 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
542 // Always use a library call for pow.
543 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
544 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
545 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
547 setOperationAction(ISD::FLOG, MVT::f80, Expand);
548 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
549 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
550 setOperationAction(ISD::FEXP, MVT::f80, Expand);
551 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
553 // First set operation action for all vector types to either promote
554 // (for widening) or expand (for scalarization). Then we will selectively
555 // turn on ones that can be effectively codegen'd.
556 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
557 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
558 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
573 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
574 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
605 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
606 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
607 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
608 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
609 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
610 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
611 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
612 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
613 setTruncStoreAction((MVT::SimpleValueType)VT,
614 (MVT::SimpleValueType)InnerVT, Expand);
615 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
616 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
617 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
620 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
621 // with -msoft-float, disable use of MMX as well.
622 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
623 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
624 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
625 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
626 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
627 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
629 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
630 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
631 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
632 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
634 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
635 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
636 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
637 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
639 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
640 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
642 setOperationAction(ISD::AND, MVT::v8i8, Promote);
643 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
644 setOperationAction(ISD::AND, MVT::v4i16, Promote);
645 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
646 setOperationAction(ISD::AND, MVT::v2i32, Promote);
647 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
648 setOperationAction(ISD::AND, MVT::v1i64, Legal);
650 setOperationAction(ISD::OR, MVT::v8i8, Promote);
651 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
652 setOperationAction(ISD::OR, MVT::v4i16, Promote);
653 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
654 setOperationAction(ISD::OR, MVT::v2i32, Promote);
655 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
656 setOperationAction(ISD::OR, MVT::v1i64, Legal);
658 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
659 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
660 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
661 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
662 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
663 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
664 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
666 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
667 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
668 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
669 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
670 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
671 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
672 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
673 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
674 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
676 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
677 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
678 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
679 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
680 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
682 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
683 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
684 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
685 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
687 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
688 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
689 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
690 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
692 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
694 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
695 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
696 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
697 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
698 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
699 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
700 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
703 if (!UseSoftFloat && Subtarget->hasSSE1()) {
704 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
706 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
707 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
708 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
709 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
710 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
711 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
712 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
713 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
714 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
715 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
716 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
717 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
720 if (!UseSoftFloat && Subtarget->hasSSE2()) {
721 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
723 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
724 // registers cannot be used even for integer operations.
725 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
726 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
727 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
728 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
730 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
731 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
732 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
733 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
734 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
735 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
736 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
737 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
738 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
739 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
740 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
741 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
742 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
743 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
744 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
745 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
747 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
748 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
749 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
750 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
753 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
754 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
755 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
756 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
758 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
759 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
760 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
764 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
765 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
766 EVT VT = (MVT::SimpleValueType)i;
767 // Do not attempt to custom lower non-power-of-2 vectors
768 if (!isPowerOf2_32(VT.getVectorNumElements()))
770 // Do not attempt to custom lower non-128-bit vectors
771 if (!VT.is128BitVector())
773 setOperationAction(ISD::BUILD_VECTOR,
774 VT.getSimpleVT().SimpleTy, Custom);
775 setOperationAction(ISD::VECTOR_SHUFFLE,
776 VT.getSimpleVT().SimpleTy, Custom);
777 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
778 VT.getSimpleVT().SimpleTy, Custom);
781 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
782 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
783 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
785 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
788 if (Subtarget->is64Bit()) {
789 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
790 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
793 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
794 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
795 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
798 // Do not attempt to promote non-128-bit vectors
799 if (!VT.is128BitVector()) {
802 setOperationAction(ISD::AND, SVT, Promote);
803 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
804 setOperationAction(ISD::OR, SVT, Promote);
805 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
806 setOperationAction(ISD::XOR, SVT, Promote);
807 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
808 setOperationAction(ISD::LOAD, SVT, Promote);
809 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
810 setOperationAction(ISD::SELECT, SVT, Promote);
811 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
814 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
816 // Custom lower v2i64 and v2f64 selects.
817 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
818 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
819 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
820 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
822 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
823 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
824 if (!DisableMMX && Subtarget->hasMMX()) {
825 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
826 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
830 if (Subtarget->hasSSE41()) {
831 // FIXME: Do we need to handle scalar-to-vector here?
832 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
834 // i8 and i16 vectors are custom , because the source register and source
835 // source memory operand types are not the same width. f32 vectors are
836 // custom since the immediate controlling the insert encodes additional
838 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
839 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
843 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
844 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
845 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
848 if (Subtarget->is64Bit()) {
849 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
854 if (Subtarget->hasSSE42()) {
855 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
858 if (!UseSoftFloat && Subtarget->hasAVX()) {
859 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
860 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
861 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
862 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
864 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
865 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
866 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
867 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
868 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
869 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
870 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
871 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
872 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
873 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
874 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
875 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
876 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
877 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
878 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
880 // Operations to consider commented out -v16i16 v32i8
881 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
882 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
883 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
884 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
885 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
886 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
887 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
888 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
889 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
890 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
891 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
892 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
893 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
894 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
896 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
897 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
898 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
899 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
901 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
902 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
903 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
905 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
907 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
908 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
909 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
910 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
912 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
915 // Not sure we want to do this since there are no 256-bit integer
918 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
919 // This includes 256-bit vectors
920 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
921 EVT VT = (MVT::SimpleValueType)i;
923 // Do not attempt to custom lower non-power-of-2 vectors
924 if (!isPowerOf2_32(VT.getVectorNumElements()))
927 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
928 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
929 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
932 if (Subtarget->is64Bit()) {
933 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
934 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
939 // Not sure we want to do this since there are no 256-bit integer
942 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
943 // Including 256-bit vectors
944 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
945 EVT VT = (MVT::SimpleValueType)i;
947 if (!VT.is256BitVector()) {
950 setOperationAction(ISD::AND, VT, Promote);
951 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
952 setOperationAction(ISD::OR, VT, Promote);
953 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
954 setOperationAction(ISD::XOR, VT, Promote);
955 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
956 setOperationAction(ISD::LOAD, VT, Promote);
957 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
958 setOperationAction(ISD::SELECT, VT, Promote);
959 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
962 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
966 // We want to custom lower some of our intrinsics.
967 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
969 // Add/Sub/Mul with overflow operations are custom lowered.
970 setOperationAction(ISD::SADDO, MVT::i32, Custom);
971 setOperationAction(ISD::SADDO, MVT::i64, Custom);
972 setOperationAction(ISD::UADDO, MVT::i32, Custom);
973 setOperationAction(ISD::UADDO, MVT::i64, Custom);
974 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
975 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
976 setOperationAction(ISD::USUBO, MVT::i32, Custom);
977 setOperationAction(ISD::USUBO, MVT::i64, Custom);
978 setOperationAction(ISD::SMULO, MVT::i32, Custom);
979 setOperationAction(ISD::SMULO, MVT::i64, Custom);
981 if (!Subtarget->is64Bit()) {
982 // These libcalls are not available in 32-bit.
983 setLibcallName(RTLIB::SHL_I128, 0);
984 setLibcallName(RTLIB::SRL_I128, 0);
985 setLibcallName(RTLIB::SRA_I128, 0);
988 // We have target-specific dag combine patterns for the following nodes:
989 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
990 setTargetDAGCombine(ISD::BUILD_VECTOR);
991 setTargetDAGCombine(ISD::SELECT);
992 setTargetDAGCombine(ISD::SHL);
993 setTargetDAGCombine(ISD::SRA);
994 setTargetDAGCombine(ISD::SRL);
995 setTargetDAGCombine(ISD::OR);
996 setTargetDAGCombine(ISD::STORE);
997 setTargetDAGCombine(ISD::MEMBARRIER);
998 setTargetDAGCombine(ISD::ZERO_EXTEND);
999 if (Subtarget->is64Bit())
1000 setTargetDAGCombine(ISD::MUL);
1002 computeRegisterProperties();
1004 // FIXME: These should be based on subtarget info. Plus, the values should
1005 // be smaller when we are in optimizing for size mode.
1006 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1007 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
1008 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1009 setPrefLoopAlignment(16);
1010 benefitFromCodePlacementOpt = true;
1014 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1019 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1020 /// the desired ByVal argument alignment.
1021 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1024 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1025 if (VTy->getBitWidth() == 128)
1027 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1028 unsigned EltAlign = 0;
1029 getMaxByValAlign(ATy->getElementType(), EltAlign);
1030 if (EltAlign > MaxAlign)
1031 MaxAlign = EltAlign;
1032 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1033 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1034 unsigned EltAlign = 0;
1035 getMaxByValAlign(STy->getElementType(i), EltAlign);
1036 if (EltAlign > MaxAlign)
1037 MaxAlign = EltAlign;
1045 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1046 /// function arguments in the caller parameter area. For X86, aggregates
1047 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1048 /// are at 4-byte boundaries.
1049 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1050 if (Subtarget->is64Bit()) {
1051 // Max of 8 and alignment of type.
1052 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1059 if (Subtarget->hasSSE1())
1060 getMaxByValAlign(Ty, Align);
1064 /// getOptimalMemOpType - Returns the target specific optimal type for load
1065 /// and store operations as a result of memset, memcpy, and memmove
1066 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1069 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1070 bool isSrcConst, bool isSrcStr,
1071 SelectionDAG &DAG) const {
1072 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1073 // linux. This is because the stack realignment code can't handle certain
1074 // cases like PR2962. This should be removed when PR2962 is fixed.
1075 const Function *F = DAG.getMachineFunction().getFunction();
1076 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1077 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1078 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1080 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1083 if (Subtarget->is64Bit() && Size >= 8)
1088 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1089 /// current function. The returned value is a member of the
1090 /// MachineJumpTableInfo::JTEntryKind enum.
1091 unsigned X86TargetLowering::getJumpTableEncoding() const {
1092 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1094 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1095 Subtarget->isPICStyleGOT())
1096 return MachineJumpTableInfo::EK_Custom32;
1098 // Otherwise, use the normal jump table encoding heuristics.
1099 return TargetLowering::getJumpTableEncoding();
1102 /// getPICBaseSymbol - Return the X86-32 PIC base.
1104 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1105 MCContext &Ctx) const {
1106 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1107 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1108 Twine(MF->getFunctionNumber())+"$pb");
1113 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1114 const MachineBasicBlock *MBB,
1115 unsigned uid,MCContext &Ctx) const{
1116 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1117 Subtarget->isPICStyleGOT());
1118 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1120 return X86MCTargetExpr::Create(MBB->getSymbol(Ctx),
1121 X86MCTargetExpr::GOTOFF, Ctx);
1124 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1126 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1127 SelectionDAG &DAG) const {
1128 if (!Subtarget->is64Bit())
1129 // This doesn't have DebugLoc associated with it, but is not really the
1130 // same as a Register.
1131 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1136 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1137 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1139 const MCExpr *X86TargetLowering::
1140 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1141 MCContext &Ctx) const {
1142 // X86-64 uses RIP relative addressing based on the jump table label.
1143 if (Subtarget->isPICStyleRIPRel())
1144 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1146 // Otherwise, the reference is relative to the PIC base.
1147 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1150 /// getFunctionAlignment - Return the Log2 alignment of this function.
1151 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1152 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1155 //===----------------------------------------------------------------------===//
1156 // Return Value Calling Convention Implementation
1157 //===----------------------------------------------------------------------===//
1159 #include "X86GenCallingConv.inc"
1162 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1163 const SmallVectorImpl<EVT> &OutTys,
1164 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1165 SelectionDAG &DAG) {
1166 SmallVector<CCValAssign, 16> RVLocs;
1167 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1168 RVLocs, *DAG.getContext());
1169 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1173 X86TargetLowering::LowerReturn(SDValue Chain,
1174 CallingConv::ID CallConv, bool isVarArg,
1175 const SmallVectorImpl<ISD::OutputArg> &Outs,
1176 DebugLoc dl, SelectionDAG &DAG) {
1178 SmallVector<CCValAssign, 16> RVLocs;
1179 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1180 RVLocs, *DAG.getContext());
1181 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1183 // Add the regs to the liveout set for the function.
1184 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1185 for (unsigned i = 0; i != RVLocs.size(); ++i)
1186 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1187 MRI.addLiveOut(RVLocs[i].getLocReg());
1191 SmallVector<SDValue, 6> RetOps;
1192 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1193 // Operand #1 = Bytes To Pop
1194 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1196 // Copy the result values into the output registers.
1197 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1198 CCValAssign &VA = RVLocs[i];
1199 assert(VA.isRegLoc() && "Can only return in registers!");
1200 SDValue ValToCopy = Outs[i].Val;
1202 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1203 // the RET instruction and handled by the FP Stackifier.
1204 if (VA.getLocReg() == X86::ST0 ||
1205 VA.getLocReg() == X86::ST1) {
1206 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1207 // change the value to the FP stack register class.
1208 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1209 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1210 RetOps.push_back(ValToCopy);
1211 // Don't emit a copytoreg.
1215 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1216 // which is returned in RAX / RDX.
1217 if (Subtarget->is64Bit()) {
1218 EVT ValVT = ValToCopy.getValueType();
1219 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1220 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1221 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1222 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1226 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1227 Flag = Chain.getValue(1);
1230 // The x86-64 ABI for returning structs by value requires that we copy
1231 // the sret argument into %rax for the return. We saved the argument into
1232 // a virtual register in the entry block, so now we copy the value out
1234 if (Subtarget->is64Bit() &&
1235 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1236 MachineFunction &MF = DAG.getMachineFunction();
1237 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1238 unsigned Reg = FuncInfo->getSRetReturnReg();
1240 Reg = MRI.createVirtualRegister(getRegClassFor(MVT::i64));
1241 FuncInfo->setSRetReturnReg(Reg);
1243 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1245 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1246 Flag = Chain.getValue(1);
1248 // RAX now acts like a return value.
1249 MRI.addLiveOut(X86::RAX);
1252 RetOps[0] = Chain; // Update chain.
1254 // Add the flag if we have it.
1256 RetOps.push_back(Flag);
1258 return DAG.getNode(X86ISD::RET_FLAG, dl,
1259 MVT::Other, &RetOps[0], RetOps.size());
1262 /// LowerCallResult - Lower the result values of a call into the
1263 /// appropriate copies out of appropriate physical registers.
1266 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1267 CallingConv::ID CallConv, bool isVarArg,
1268 const SmallVectorImpl<ISD::InputArg> &Ins,
1269 DebugLoc dl, SelectionDAG &DAG,
1270 SmallVectorImpl<SDValue> &InVals) {
1272 // Assign locations to each value returned by this call.
1273 SmallVector<CCValAssign, 16> RVLocs;
1274 bool Is64Bit = Subtarget->is64Bit();
1275 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1276 RVLocs, *DAG.getContext());
1277 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1279 // Copy all of the result registers out of their specified physreg.
1280 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1281 CCValAssign &VA = RVLocs[i];
1282 EVT CopyVT = VA.getValVT();
1284 // If this is x86-64, and we disabled SSE, we can't return FP values
1285 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1286 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1287 llvm_report_error("SSE register return with SSE disabled");
1290 // If this is a call to a function that returns an fp value on the floating
1291 // point stack, but where we prefer to use the value in xmm registers, copy
1292 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1293 if ((VA.getLocReg() == X86::ST0 ||
1294 VA.getLocReg() == X86::ST1) &&
1295 isScalarFPTypeInSSEReg(VA.getValVT())) {
1300 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1301 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1302 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1303 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1304 MVT::v2i64, InFlag).getValue(1);
1305 Val = Chain.getValue(0);
1306 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1307 Val, DAG.getConstant(0, MVT::i64));
1309 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1310 MVT::i64, InFlag).getValue(1);
1311 Val = Chain.getValue(0);
1313 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1315 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1316 CopyVT, InFlag).getValue(1);
1317 Val = Chain.getValue(0);
1319 InFlag = Chain.getValue(2);
1321 if (CopyVT != VA.getValVT()) {
1322 // Round the F80 the right size, which also moves to the appropriate xmm
1324 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1325 // This truncation won't change the value.
1326 DAG.getIntPtrConstant(1));
1329 InVals.push_back(Val);
1336 //===----------------------------------------------------------------------===//
1337 // C & StdCall & Fast Calling Convention implementation
1338 //===----------------------------------------------------------------------===//
1339 // StdCall calling convention seems to be standard for many Windows' API
1340 // routines and around. It differs from C calling convention just a little:
1341 // callee should clean up the stack, not caller. Symbols should be also
1342 // decorated in some fancy way :) It doesn't support any vector arguments.
1343 // For info on fast calling convention see Fast Calling Convention (tail call)
1344 // implementation LowerX86_32FastCCCallTo.
1346 /// CallIsStructReturn - Determines whether a call uses struct return
1348 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1352 return Outs[0].Flags.isSRet();
1355 /// ArgsAreStructReturn - Determines whether a function uses struct
1356 /// return semantics.
1358 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1362 return Ins[0].Flags.isSRet();
1365 /// IsCalleePop - Determines whether the callee is required to pop its
1366 /// own arguments. Callee pop is necessary to support tail calls.
1367 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1371 switch (CallingConv) {
1374 case CallingConv::X86_StdCall:
1375 return !Subtarget->is64Bit();
1376 case CallingConv::X86_FastCall:
1377 return !Subtarget->is64Bit();
1378 case CallingConv::Fast:
1379 return GuaranteedTailCallOpt;
1383 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1384 /// given CallingConvention value.
1385 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1386 if (Subtarget->is64Bit()) {
1387 if (Subtarget->isTargetWin64())
1388 return CC_X86_Win64_C;
1393 if (CC == CallingConv::X86_FastCall)
1394 return CC_X86_32_FastCall;
1395 else if (CC == CallingConv::Fast)
1396 return CC_X86_32_FastCC;
1401 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1402 /// by "Src" to address "Dst" with size and alignment information specified by
1403 /// the specific parameter attribute. The copy will be passed as a byval
1404 /// function parameter.
1406 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1407 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1409 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1410 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1411 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1414 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1415 /// a tailcall target by changing its ABI.
1416 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1417 return GuaranteedTailCallOpt && CC == CallingConv::Fast;
1421 X86TargetLowering::LowerMemArgument(SDValue Chain,
1422 CallingConv::ID CallConv,
1423 const SmallVectorImpl<ISD::InputArg> &Ins,
1424 DebugLoc dl, SelectionDAG &DAG,
1425 const CCValAssign &VA,
1426 MachineFrameInfo *MFI,
1428 // Create the nodes corresponding to a load from this parameter slot.
1429 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1430 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1431 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1434 // If value is passed by pointer we have address passed instead of the value
1436 if (VA.getLocInfo() == CCValAssign::Indirect)
1437 ValVT = VA.getLocVT();
1439 ValVT = VA.getValVT();
1441 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1442 // changed with more analysis.
1443 // In case of tail call optimization mark all arguments mutable. Since they
1444 // could be overwritten by lowering of arguments in case of a tail call.
1445 if (Flags.isByVal()) {
1446 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1447 VA.getLocMemOffset(), isImmutable, false);
1448 return DAG.getFrameIndex(FI, getPointerTy());
1450 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1451 VA.getLocMemOffset(), isImmutable, false);
1452 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1453 return DAG.getLoad(ValVT, dl, Chain, FIN,
1454 PseudoSourceValue::getFixedStack(FI), 0);
1459 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1460 CallingConv::ID CallConv,
1462 const SmallVectorImpl<ISD::InputArg> &Ins,
1465 SmallVectorImpl<SDValue> &InVals) {
1467 MachineFunction &MF = DAG.getMachineFunction();
1468 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1470 const Function* Fn = MF.getFunction();
1471 if (Fn->hasExternalLinkage() &&
1472 Subtarget->isTargetCygMing() &&
1473 Fn->getName() == "main")
1474 FuncInfo->setForceFramePointer(true);
1476 MachineFrameInfo *MFI = MF.getFrameInfo();
1477 bool Is64Bit = Subtarget->is64Bit();
1478 bool IsWin64 = Subtarget->isTargetWin64();
1480 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1481 "Var args not supported with calling convention fastcc");
1483 // Assign locations to all of the incoming arguments.
1484 SmallVector<CCValAssign, 16> ArgLocs;
1485 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1486 ArgLocs, *DAG.getContext());
1487 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1489 unsigned LastVal = ~0U;
1491 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1492 CCValAssign &VA = ArgLocs[i];
1493 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1495 assert(VA.getValNo() != LastVal &&
1496 "Don't support value assigned to multiple locs yet");
1497 LastVal = VA.getValNo();
1499 if (VA.isRegLoc()) {
1500 EVT RegVT = VA.getLocVT();
1501 TargetRegisterClass *RC = NULL;
1502 if (RegVT == MVT::i32)
1503 RC = X86::GR32RegisterClass;
1504 else if (Is64Bit && RegVT == MVT::i64)
1505 RC = X86::GR64RegisterClass;
1506 else if (RegVT == MVT::f32)
1507 RC = X86::FR32RegisterClass;
1508 else if (RegVT == MVT::f64)
1509 RC = X86::FR64RegisterClass;
1510 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1511 RC = X86::VR128RegisterClass;
1512 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1513 RC = X86::VR64RegisterClass;
1515 llvm_unreachable("Unknown argument type!");
1517 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1518 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1520 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1521 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1523 if (VA.getLocInfo() == CCValAssign::SExt)
1524 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1525 DAG.getValueType(VA.getValVT()));
1526 else if (VA.getLocInfo() == CCValAssign::ZExt)
1527 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1528 DAG.getValueType(VA.getValVT()));
1529 else if (VA.getLocInfo() == CCValAssign::BCvt)
1530 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1532 if (VA.isExtInLoc()) {
1533 // Handle MMX values passed in XMM regs.
1534 if (RegVT.isVector()) {
1535 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1536 ArgValue, DAG.getConstant(0, MVT::i64));
1537 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1539 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1542 assert(VA.isMemLoc());
1543 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1546 // If value is passed via pointer - do a load.
1547 if (VA.getLocInfo() == CCValAssign::Indirect)
1548 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1550 InVals.push_back(ArgValue);
1553 // The x86-64 ABI for returning structs by value requires that we copy
1554 // the sret argument into %rax for the return. Save the argument into
1555 // a virtual register so that we can access it from the return points.
1556 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1557 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1558 unsigned Reg = FuncInfo->getSRetReturnReg();
1560 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1561 FuncInfo->setSRetReturnReg(Reg);
1563 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1564 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1567 unsigned StackSize = CCInfo.getNextStackOffset();
1568 // Align stack specially for tail calls.
1569 if (FuncIsMadeTailCallSafe(CallConv))
1570 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1572 // If the function takes variable number of arguments, make a frame index for
1573 // the start of the first vararg value... for expansion of llvm.va_start.
1575 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1576 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false);
1579 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1581 // FIXME: We should really autogenerate these arrays
1582 static const unsigned GPR64ArgRegsWin64[] = {
1583 X86::RCX, X86::RDX, X86::R8, X86::R9
1585 static const unsigned XMMArgRegsWin64[] = {
1586 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1588 static const unsigned GPR64ArgRegs64Bit[] = {
1589 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1591 static const unsigned XMMArgRegs64Bit[] = {
1592 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1593 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1595 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1598 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1599 GPR64ArgRegs = GPR64ArgRegsWin64;
1600 XMMArgRegs = XMMArgRegsWin64;
1602 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1603 GPR64ArgRegs = GPR64ArgRegs64Bit;
1604 XMMArgRegs = XMMArgRegs64Bit;
1606 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1608 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1611 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1612 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1613 "SSE register cannot be used when SSE is disabled!");
1614 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1615 "SSE register cannot be used when SSE is disabled!");
1616 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1617 // Kernel mode asks for SSE to be disabled, so don't push them
1619 TotalNumXMMRegs = 0;
1621 // For X86-64, if there are vararg parameters that are passed via
1622 // registers, then we must store them to their spots on the stack so they
1623 // may be loaded by deferencing the result of va_next.
1624 VarArgsGPOffset = NumIntRegs * 8;
1625 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1626 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1627 TotalNumXMMRegs * 16, 16,
1630 // Store the integer parameter registers.
1631 SmallVector<SDValue, 8> MemOps;
1632 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1633 unsigned Offset = VarArgsGPOffset;
1634 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1635 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1636 DAG.getIntPtrConstant(Offset));
1637 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1638 X86::GR64RegisterClass);
1639 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1641 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1642 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1644 MemOps.push_back(Store);
1648 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1649 // Now store the XMM (fp + vector) parameter registers.
1650 SmallVector<SDValue, 11> SaveXMMOps;
1651 SaveXMMOps.push_back(Chain);
1653 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1654 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1655 SaveXMMOps.push_back(ALVal);
1657 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1658 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1660 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1661 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1662 X86::VR128RegisterClass);
1663 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1664 SaveXMMOps.push_back(Val);
1666 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1668 &SaveXMMOps[0], SaveXMMOps.size()));
1671 if (!MemOps.empty())
1672 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1673 &MemOps[0], MemOps.size());
1677 // Some CCs need callee pop.
1678 if (IsCalleePop(isVarArg, CallConv)) {
1679 BytesToPopOnReturn = StackSize; // Callee pops everything.
1681 BytesToPopOnReturn = 0; // Callee pops nothing.
1682 // If this is an sret function, the return should pop the hidden pointer.
1683 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1684 BytesToPopOnReturn = 4;
1688 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1689 if (CallConv == CallingConv::X86_FastCall)
1690 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1693 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1699 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1700 SDValue StackPtr, SDValue Arg,
1701 DebugLoc dl, SelectionDAG &DAG,
1702 const CCValAssign &VA,
1703 ISD::ArgFlagsTy Flags) {
1704 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1705 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1706 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1707 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1708 if (Flags.isByVal()) {
1709 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1711 return DAG.getStore(Chain, dl, Arg, PtrOff,
1712 PseudoSourceValue::getStack(), LocMemOffset);
1715 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1716 /// optimization is performed and it is required.
1718 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1719 SDValue &OutRetAddr, SDValue Chain,
1720 bool IsTailCall, bool Is64Bit,
1721 int FPDiff, DebugLoc dl) {
1722 // Adjust the Return address stack slot.
1723 EVT VT = getPointerTy();
1724 OutRetAddr = getReturnAddressFrameIndex(DAG);
1726 // Load the "old" Return address.
1727 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1728 return SDValue(OutRetAddr.getNode(), 1);
1731 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1732 /// optimization is performed and it is required (FPDiff!=0).
1734 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1735 SDValue Chain, SDValue RetAddrFrIdx,
1736 bool Is64Bit, int FPDiff, DebugLoc dl) {
1737 // Store the return address to the appropriate stack slot.
1738 if (!FPDiff) return Chain;
1739 // Calculate the new stack slot for the return address.
1740 int SlotSize = Is64Bit ? 8 : 4;
1741 int NewReturnAddrFI =
1742 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, true,false);
1743 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1744 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1745 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1746 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1751 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1752 CallingConv::ID CallConv, bool isVarArg,
1754 const SmallVectorImpl<ISD::OutputArg> &Outs,
1755 const SmallVectorImpl<ISD::InputArg> &Ins,
1756 DebugLoc dl, SelectionDAG &DAG,
1757 SmallVectorImpl<SDValue> &InVals) {
1758 MachineFunction &MF = DAG.getMachineFunction();
1759 bool Is64Bit = Subtarget->is64Bit();
1760 bool IsStructRet = CallIsStructReturn(Outs);
1761 bool IsSibcall = false;
1764 // Check if it's really possible to do a tail call.
1765 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
1768 // Sibcalls are automatically detected tailcalls which do not require
1770 if (!GuaranteedTailCallOpt && isTailCall)
1777 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1778 "Var args not supported with calling convention fastcc");
1780 // Analyze operands of the call, assigning locations to each operand.
1781 SmallVector<CCValAssign, 16> ArgLocs;
1782 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1783 ArgLocs, *DAG.getContext());
1784 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1786 // Get a count of how many bytes are to be pushed on the stack.
1787 unsigned NumBytes = CCInfo.getNextStackOffset();
1789 // This is a sibcall. The memory operands are available in caller's
1790 // own caller's stack.
1792 else if (GuaranteedTailCallOpt && CallConv == CallingConv::Fast)
1793 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1796 if (isTailCall && !IsSibcall) {
1797 // Lower arguments at fp - stackoffset + fpdiff.
1798 unsigned NumBytesCallerPushed =
1799 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1800 FPDiff = NumBytesCallerPushed - NumBytes;
1802 // Set the delta of movement of the returnaddr stackslot.
1803 // But only set if delta is greater than previous delta.
1804 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1805 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1809 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1811 SDValue RetAddrFrIdx;
1812 // Load return adress for tail calls.
1813 if (isTailCall && FPDiff)
1814 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1815 Is64Bit, FPDiff, dl);
1817 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1818 SmallVector<SDValue, 8> MemOpChains;
1821 // Walk the register/memloc assignments, inserting copies/loads. In the case
1822 // of tail call optimization arguments are handle later.
1823 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1824 CCValAssign &VA = ArgLocs[i];
1825 EVT RegVT = VA.getLocVT();
1826 SDValue Arg = Outs[i].Val;
1827 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1828 bool isByVal = Flags.isByVal();
1830 // Promote the value if needed.
1831 switch (VA.getLocInfo()) {
1832 default: llvm_unreachable("Unknown loc info!");
1833 case CCValAssign::Full: break;
1834 case CCValAssign::SExt:
1835 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1837 case CCValAssign::ZExt:
1838 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1840 case CCValAssign::AExt:
1841 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1842 // Special case: passing MMX values in XMM registers.
1843 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1844 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1845 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1847 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1849 case CCValAssign::BCvt:
1850 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1852 case CCValAssign::Indirect: {
1853 // Store the argument.
1854 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1855 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1856 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1857 PseudoSourceValue::getFixedStack(FI), 0);
1863 if (VA.isRegLoc()) {
1864 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1865 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1866 assert(VA.isMemLoc());
1867 if (StackPtr.getNode() == 0)
1868 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1869 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1870 dl, DAG, VA, Flags));
1874 if (!MemOpChains.empty())
1875 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1876 &MemOpChains[0], MemOpChains.size());
1878 // Build a sequence of copy-to-reg nodes chained together with token chain
1879 // and flag operands which copy the outgoing args into registers.
1881 // Tail call byval lowering might overwrite argument registers so in case of
1882 // tail call optimization the copies to registers are lowered later.
1884 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1885 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1886 RegsToPass[i].second, InFlag);
1887 InFlag = Chain.getValue(1);
1890 if (Subtarget->isPICStyleGOT()) {
1891 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1894 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1895 DAG.getNode(X86ISD::GlobalBaseReg,
1896 DebugLoc::getUnknownLoc(),
1899 InFlag = Chain.getValue(1);
1901 // If we are tail calling and generating PIC/GOT style code load the
1902 // address of the callee into ECX. The value in ecx is used as target of
1903 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1904 // for tail calls on PIC/GOT architectures. Normally we would just put the
1905 // address of GOT into ebx and then call target@PLT. But for tail calls
1906 // ebx would be restored (since ebx is callee saved) before jumping to the
1909 // Note: The actual moving to ECX is done further down.
1910 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1911 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1912 !G->getGlobal()->hasProtectedVisibility())
1913 Callee = LowerGlobalAddress(Callee, DAG);
1914 else if (isa<ExternalSymbolSDNode>(Callee))
1915 Callee = LowerExternalSymbol(Callee, DAG);
1919 if (Is64Bit && isVarArg) {
1920 // From AMD64 ABI document:
1921 // For calls that may call functions that use varargs or stdargs
1922 // (prototype-less calls or calls to functions containing ellipsis (...) in
1923 // the declaration) %al is used as hidden argument to specify the number
1924 // of SSE registers used. The contents of %al do not need to match exactly
1925 // the number of registers, but must be an ubound on the number of SSE
1926 // registers used and is in the range 0 - 8 inclusive.
1928 // FIXME: Verify this on Win64
1929 // Count the number of XMM registers allocated.
1930 static const unsigned XMMArgRegs[] = {
1931 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1932 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1934 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1935 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1936 && "SSE registers cannot be used when SSE is disabled");
1938 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1939 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1940 InFlag = Chain.getValue(1);
1944 // For tail calls lower the arguments to the 'real' stack slot.
1946 // Force all the incoming stack arguments to be loaded from the stack
1947 // before any new outgoing arguments are stored to the stack, because the
1948 // outgoing stack slots may alias the incoming argument stack slots, and
1949 // the alias isn't otherwise explicit. This is slightly more conservative
1950 // than necessary, because it means that each store effectively depends
1951 // on every argument instead of just those arguments it would clobber.
1952 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1954 SmallVector<SDValue, 8> MemOpChains2;
1957 // Do not flag preceeding copytoreg stuff together with the following stuff.
1959 if (GuaranteedTailCallOpt) {
1960 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1961 CCValAssign &VA = ArgLocs[i];
1964 assert(VA.isMemLoc());
1965 SDValue Arg = Outs[i].Val;
1966 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1967 // Create frame index.
1968 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1969 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1970 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
1971 FIN = DAG.getFrameIndex(FI, getPointerTy());
1973 if (Flags.isByVal()) {
1974 // Copy relative to framepointer.
1975 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1976 if (StackPtr.getNode() == 0)
1977 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1979 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1981 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
1985 // Store relative to framepointer.
1986 MemOpChains2.push_back(
1987 DAG.getStore(ArgChain, dl, Arg, FIN,
1988 PseudoSourceValue::getFixedStack(FI), 0));
1993 if (!MemOpChains2.empty())
1994 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1995 &MemOpChains2[0], MemOpChains2.size());
1997 // Copy arguments to their registers.
1998 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1999 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2000 RegsToPass[i].second, InFlag);
2001 InFlag = Chain.getValue(1);
2005 // Store the return address to the appropriate stack slot.
2006 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2010 bool WasGlobalOrExternal = false;
2011 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2012 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2013 // In the 64-bit large code model, we have to make all calls
2014 // through a register, since the call instruction's 32-bit
2015 // pc-relative offset may not be large enough to hold the whole
2017 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2018 WasGlobalOrExternal = true;
2019 // If the callee is a GlobalAddress node (quite common, every direct call
2020 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2023 // We should use extra load for direct calls to dllimported functions in
2025 GlobalValue *GV = G->getGlobal();
2026 if (!GV->hasDLLImportLinkage()) {
2027 unsigned char OpFlags = 0;
2029 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2030 // external symbols most go through the PLT in PIC mode. If the symbol
2031 // has hidden or protected visibility, or if it is static or local, then
2032 // we don't need to use the PLT - we can directly call it.
2033 if (Subtarget->isTargetELF() &&
2034 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2035 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2036 OpFlags = X86II::MO_PLT;
2037 } else if (Subtarget->isPICStyleStubAny() &&
2038 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2039 Subtarget->getDarwinVers() < 9) {
2040 // PC-relative references to external symbols should go through $stub,
2041 // unless we're building with the leopard linker or later, which
2042 // automatically synthesizes these stubs.
2043 OpFlags = X86II::MO_DARWIN_STUB;
2046 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
2047 G->getOffset(), OpFlags);
2049 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2050 WasGlobalOrExternal = true;
2051 unsigned char OpFlags = 0;
2053 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2054 // symbols should go through the PLT.
2055 if (Subtarget->isTargetELF() &&
2056 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2057 OpFlags = X86II::MO_PLT;
2058 } else if (Subtarget->isPICStyleStubAny() &&
2059 Subtarget->getDarwinVers() < 9) {
2060 // PC-relative references to external symbols should go through $stub,
2061 // unless we're building with the leopard linker or later, which
2062 // automatically synthesizes these stubs.
2063 OpFlags = X86II::MO_DARWIN_STUB;
2066 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2070 if (isTailCall && !WasGlobalOrExternal) {
2071 // Force the address into a (call preserved) caller-saved register since
2072 // tailcall must happen after callee-saved registers are poped.
2073 // FIXME: Give it a special register class that contains caller-saved
2074 // register instead?
2075 unsigned TCReg = Is64Bit ? X86::R11 : X86::EAX;
2076 Chain = DAG.getCopyToReg(Chain, dl,
2077 DAG.getRegister(TCReg, getPointerTy()),
2079 Callee = DAG.getRegister(TCReg, getPointerTy());
2082 // Returns a chain & a flag for retval copy to use.
2083 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2084 SmallVector<SDValue, 8> Ops;
2086 if (!IsSibcall && isTailCall) {
2087 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2088 DAG.getIntPtrConstant(0, true), InFlag);
2089 InFlag = Chain.getValue(1);
2092 Ops.push_back(Chain);
2093 Ops.push_back(Callee);
2096 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2098 // Add argument registers to the end of the list so that they are known live
2100 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2101 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2102 RegsToPass[i].second.getValueType()));
2104 // Add an implicit use GOT pointer in EBX.
2105 if (!isTailCall && Subtarget->isPICStyleGOT())
2106 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2108 // Add an implicit use of AL for x86 vararg functions.
2109 if (Is64Bit && isVarArg)
2110 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2112 if (InFlag.getNode())
2113 Ops.push_back(InFlag);
2116 // If this is the first return lowered for this function, add the regs
2117 // to the liveout set for the function.
2118 if (MF.getRegInfo().liveout_empty()) {
2119 SmallVector<CCValAssign, 16> RVLocs;
2120 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2122 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2123 for (unsigned i = 0; i != RVLocs.size(); ++i)
2124 if (RVLocs[i].isRegLoc())
2125 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2128 assert(((Callee.getOpcode() == ISD::Register &&
2129 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2130 cast<RegisterSDNode>(Callee)->getReg() == X86::R11)) ||
2131 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2132 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2133 "Expecting a global address, external symbol, or scratch register");
2135 return DAG.getNode(X86ISD::TC_RETURN, dl,
2136 NodeTys, &Ops[0], Ops.size());
2139 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2140 InFlag = Chain.getValue(1);
2142 // Create the CALLSEQ_END node.
2143 unsigned NumBytesForCalleeToPush;
2144 if (IsCalleePop(isVarArg, CallConv))
2145 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2146 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2147 // If this is a call to a struct-return function, the callee
2148 // pops the hidden struct pointer, so we have to push it back.
2149 // This is common for Darwin/X86, Linux & Mingw32 targets.
2150 NumBytesForCalleeToPush = 4;
2152 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2154 // Returns a flag for retval copy to use.
2156 Chain = DAG.getCALLSEQ_END(Chain,
2157 DAG.getIntPtrConstant(NumBytes, true),
2158 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2161 InFlag = Chain.getValue(1);
2164 // Handle result values, copying them out of physregs into vregs that we
2166 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2167 Ins, dl, DAG, InVals);
2171 //===----------------------------------------------------------------------===//
2172 // Fast Calling Convention (tail call) implementation
2173 //===----------------------------------------------------------------------===//
2175 // Like std call, callee cleans arguments, convention except that ECX is
2176 // reserved for storing the tail called function address. Only 2 registers are
2177 // free for argument passing (inreg). Tail call optimization is performed
2179 // * tailcallopt is enabled
2180 // * caller/callee are fastcc
2181 // On X86_64 architecture with GOT-style position independent code only local
2182 // (within module) calls are supported at the moment.
2183 // To keep the stack aligned according to platform abi the function
2184 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2185 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2186 // If a tail called function callee has more arguments than the caller the
2187 // caller needs to make sure that there is room to move the RETADDR to. This is
2188 // achieved by reserving an area the size of the argument delta right after the
2189 // original REtADDR, but before the saved framepointer or the spilled registers
2190 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2202 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2203 /// for a 16 byte align requirement.
2204 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2205 SelectionDAG& DAG) {
2206 MachineFunction &MF = DAG.getMachineFunction();
2207 const TargetMachine &TM = MF.getTarget();
2208 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2209 unsigned StackAlignment = TFI.getStackAlignment();
2210 uint64_t AlignMask = StackAlignment - 1;
2211 int64_t Offset = StackSize;
2212 uint64_t SlotSize = TD->getPointerSize();
2213 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2214 // Number smaller than 12 so just add the difference.
2215 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2217 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2218 Offset = ((~AlignMask) & Offset) + StackAlignment +
2219 (StackAlignment-SlotSize);
2224 /// MatchingStackOffset - Return true if the given stack call argument is
2225 /// already available in the same position (relatively) of the caller's
2226 /// incoming argument stack.
2228 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2229 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2230 const X86InstrInfo *TII) {
2232 if (Arg.getOpcode() == ISD::CopyFromReg) {
2233 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2234 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2236 MachineInstr *Def = MRI->getVRegDef(VR);
2239 if (!Flags.isByVal()) {
2240 if (!TII->isLoadFromStackSlot(Def, FI))
2243 unsigned Opcode = Def->getOpcode();
2244 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2245 Def->getOperand(1).isFI()) {
2246 FI = Def->getOperand(1).getIndex();
2247 if (MFI->getObjectSize(FI) != Flags.getByValSize())
2253 LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg);
2256 SDValue Ptr = Ld->getBasePtr();
2257 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2260 FI = FINode->getIndex();
2263 if (!MFI->isFixedObjectIndex(FI))
2265 return Offset == MFI->getObjectOffset(FI);
2268 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2269 /// for tail call optimization. Targets which want to do tail call
2270 /// optimization should implement this function.
2272 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2273 CallingConv::ID CalleeCC,
2275 const SmallVectorImpl<ISD::OutputArg> &Outs,
2276 const SmallVectorImpl<ISD::InputArg> &Ins,
2277 SelectionDAG& DAG) const {
2278 if (CalleeCC != CallingConv::Fast &&
2279 CalleeCC != CallingConv::C)
2282 // If -tailcallopt is specified, make fastcc functions tail-callable.
2283 const Function *CallerF = DAG.getMachineFunction().getFunction();
2284 if (GuaranteedTailCallOpt) {
2285 if (CalleeCC == CallingConv::Fast &&
2286 CallerF->getCallingConv() == CalleeCC)
2291 // Look for obvious safe cases to perform tail call optimization that does not
2292 // requite ABI changes. This is what gcc calls sibcall.
2294 // Do not tail call optimize vararg calls for now.
2298 // If the callee takes no arguments then go on to check the results of the
2300 if (!Outs.empty()) {
2301 // Check if stack adjustment is needed. For now, do not do this if any
2302 // argument is passed on the stack.
2303 SmallVector<CCValAssign, 16> ArgLocs;
2304 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2305 ArgLocs, *DAG.getContext());
2306 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2307 if (CCInfo.getNextStackOffset()) {
2308 MachineFunction &MF = DAG.getMachineFunction();
2309 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2311 if (Subtarget->isTargetWin64())
2312 // Win64 ABI has additional complications.
2315 // Check if the arguments are already laid out in the right way as
2316 // the caller's fixed stack objects.
2317 MachineFrameInfo *MFI = MF.getFrameInfo();
2318 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2319 const X86InstrInfo *TII =
2320 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2321 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2322 CCValAssign &VA = ArgLocs[i];
2323 EVT RegVT = VA.getLocVT();
2324 SDValue Arg = Outs[i].Val;
2325 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2326 if (VA.getLocInfo() == CCValAssign::Indirect)
2328 if (!VA.isRegLoc()) {
2329 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2341 X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo,
2343 DenseMap<const Value *, unsigned> &vm,
2344 DenseMap<const BasicBlock*, MachineBasicBlock*> &bm,
2345 DenseMap<const AllocaInst *, int> &am
2347 , SmallSet<Instruction*, 8> &cil
2350 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2358 //===----------------------------------------------------------------------===//
2359 // Other Lowering Hooks
2360 //===----------------------------------------------------------------------===//
2363 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2364 MachineFunction &MF = DAG.getMachineFunction();
2365 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2366 int ReturnAddrIndex = FuncInfo->getRAIndex();
2368 if (ReturnAddrIndex == 0) {
2369 // Set up a frame object for the return address.
2370 uint64_t SlotSize = TD->getPointerSize();
2371 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2373 FuncInfo->setRAIndex(ReturnAddrIndex);
2376 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2380 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2381 bool hasSymbolicDisplacement) {
2382 // Offset should fit into 32 bit immediate field.
2383 if (!isInt32(Offset))
2386 // If we don't have a symbolic displacement - we don't have any extra
2388 if (!hasSymbolicDisplacement)
2391 // FIXME: Some tweaks might be needed for medium code model.
2392 if (M != CodeModel::Small && M != CodeModel::Kernel)
2395 // For small code model we assume that latest object is 16MB before end of 31
2396 // bits boundary. We may also accept pretty large negative constants knowing
2397 // that all objects are in the positive half of address space.
2398 if (M == CodeModel::Small && Offset < 16*1024*1024)
2401 // For kernel code model we know that all object resist in the negative half
2402 // of 32bits address space. We may not accept negative offsets, since they may
2403 // be just off and we may accept pretty large positive ones.
2404 if (M == CodeModel::Kernel && Offset > 0)
2410 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2411 /// specific condition code, returning the condition code and the LHS/RHS of the
2412 /// comparison to make.
2413 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2414 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2416 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2417 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2418 // X > -1 -> X == 0, jump !sign.
2419 RHS = DAG.getConstant(0, RHS.getValueType());
2420 return X86::COND_NS;
2421 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2422 // X < 0 -> X == 0, jump on sign.
2424 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2426 RHS = DAG.getConstant(0, RHS.getValueType());
2427 return X86::COND_LE;
2431 switch (SetCCOpcode) {
2432 default: llvm_unreachable("Invalid integer condition!");
2433 case ISD::SETEQ: return X86::COND_E;
2434 case ISD::SETGT: return X86::COND_G;
2435 case ISD::SETGE: return X86::COND_GE;
2436 case ISD::SETLT: return X86::COND_L;
2437 case ISD::SETLE: return X86::COND_LE;
2438 case ISD::SETNE: return X86::COND_NE;
2439 case ISD::SETULT: return X86::COND_B;
2440 case ISD::SETUGT: return X86::COND_A;
2441 case ISD::SETULE: return X86::COND_BE;
2442 case ISD::SETUGE: return X86::COND_AE;
2446 // First determine if it is required or is profitable to flip the operands.
2448 // If LHS is a foldable load, but RHS is not, flip the condition.
2449 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2450 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2451 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2452 std::swap(LHS, RHS);
2455 switch (SetCCOpcode) {
2461 std::swap(LHS, RHS);
2465 // On a floating point condition, the flags are set as follows:
2467 // 0 | 0 | 0 | X > Y
2468 // 0 | 0 | 1 | X < Y
2469 // 1 | 0 | 0 | X == Y
2470 // 1 | 1 | 1 | unordered
2471 switch (SetCCOpcode) {
2472 default: llvm_unreachable("Condcode should be pre-legalized away");
2474 case ISD::SETEQ: return X86::COND_E;
2475 case ISD::SETOLT: // flipped
2477 case ISD::SETGT: return X86::COND_A;
2478 case ISD::SETOLE: // flipped
2480 case ISD::SETGE: return X86::COND_AE;
2481 case ISD::SETUGT: // flipped
2483 case ISD::SETLT: return X86::COND_B;
2484 case ISD::SETUGE: // flipped
2486 case ISD::SETLE: return X86::COND_BE;
2488 case ISD::SETNE: return X86::COND_NE;
2489 case ISD::SETUO: return X86::COND_P;
2490 case ISD::SETO: return X86::COND_NP;
2492 case ISD::SETUNE: return X86::COND_INVALID;
2496 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2497 /// code. Current x86 isa includes the following FP cmov instructions:
2498 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2499 static bool hasFPCMov(unsigned X86CC) {
2515 /// isFPImmLegal - Returns true if the target can instruction select the
2516 /// specified FP immediate natively. If false, the legalizer will
2517 /// materialize the FP immediate as a load from a constant pool.
2518 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2519 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2520 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2526 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2527 /// the specified range (L, H].
2528 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2529 return (Val < 0) || (Val >= Low && Val < Hi);
2532 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2533 /// specified value.
2534 static bool isUndefOrEqual(int Val, int CmpVal) {
2535 if (Val < 0 || Val == CmpVal)
2540 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2541 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2542 /// the second operand.
2543 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2544 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2545 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2546 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2547 return (Mask[0] < 2 && Mask[1] < 2);
2551 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2552 SmallVector<int, 8> M;
2554 return ::isPSHUFDMask(M, N->getValueType(0));
2557 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2558 /// is suitable for input to PSHUFHW.
2559 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2560 if (VT != MVT::v8i16)
2563 // Lower quadword copied in order or undef.
2564 for (int i = 0; i != 4; ++i)
2565 if (Mask[i] >= 0 && Mask[i] != i)
2568 // Upper quadword shuffled.
2569 for (int i = 4; i != 8; ++i)
2570 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2576 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2577 SmallVector<int, 8> M;
2579 return ::isPSHUFHWMask(M, N->getValueType(0));
2582 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2583 /// is suitable for input to PSHUFLW.
2584 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2585 if (VT != MVT::v8i16)
2588 // Upper quadword copied in order.
2589 for (int i = 4; i != 8; ++i)
2590 if (Mask[i] >= 0 && Mask[i] != i)
2593 // Lower quadword shuffled.
2594 for (int i = 0; i != 4; ++i)
2601 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2602 SmallVector<int, 8> M;
2604 return ::isPSHUFLWMask(M, N->getValueType(0));
2607 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2608 /// is suitable for input to PALIGNR.
2609 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2611 int i, e = VT.getVectorNumElements();
2613 // Do not handle v2i64 / v2f64 shuffles with palignr.
2614 if (e < 4 || !hasSSSE3)
2617 for (i = 0; i != e; ++i)
2621 // All undef, not a palignr.
2625 // Determine if it's ok to perform a palignr with only the LHS, since we
2626 // don't have access to the actual shuffle elements to see if RHS is undef.
2627 bool Unary = Mask[i] < (int)e;
2628 bool NeedsUnary = false;
2630 int s = Mask[i] - i;
2632 // Check the rest of the elements to see if they are consecutive.
2633 for (++i; i != e; ++i) {
2638 Unary = Unary && (m < (int)e);
2639 NeedsUnary = NeedsUnary || (m < s);
2641 if (NeedsUnary && !Unary)
2643 if (Unary && m != ((s+i) & (e-1)))
2645 if (!Unary && m != (s+i))
2651 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2652 SmallVector<int, 8> M;
2654 return ::isPALIGNRMask(M, N->getValueType(0), true);
2657 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2658 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2659 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2660 int NumElems = VT.getVectorNumElements();
2661 if (NumElems != 2 && NumElems != 4)
2664 int Half = NumElems / 2;
2665 for (int i = 0; i < Half; ++i)
2666 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2668 for (int i = Half; i < NumElems; ++i)
2669 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2675 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2676 SmallVector<int, 8> M;
2678 return ::isSHUFPMask(M, N->getValueType(0));
2681 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2682 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2683 /// half elements to come from vector 1 (which would equal the dest.) and
2684 /// the upper half to come from vector 2.
2685 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2686 int NumElems = VT.getVectorNumElements();
2688 if (NumElems != 2 && NumElems != 4)
2691 int Half = NumElems / 2;
2692 for (int i = 0; i < Half; ++i)
2693 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2695 for (int i = Half; i < NumElems; ++i)
2696 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2701 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2702 SmallVector<int, 8> M;
2704 return isCommutedSHUFPMask(M, N->getValueType(0));
2707 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2708 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2709 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2710 if (N->getValueType(0).getVectorNumElements() != 4)
2713 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2714 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2715 isUndefOrEqual(N->getMaskElt(1), 7) &&
2716 isUndefOrEqual(N->getMaskElt(2), 2) &&
2717 isUndefOrEqual(N->getMaskElt(3), 3);
2720 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2721 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2723 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2724 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2729 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2730 isUndefOrEqual(N->getMaskElt(1), 3) &&
2731 isUndefOrEqual(N->getMaskElt(2), 2) &&
2732 isUndefOrEqual(N->getMaskElt(3), 3);
2735 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2736 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2737 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2738 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2740 if (NumElems != 2 && NumElems != 4)
2743 for (unsigned i = 0; i < NumElems/2; ++i)
2744 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2747 for (unsigned i = NumElems/2; i < NumElems; ++i)
2748 if (!isUndefOrEqual(N->getMaskElt(i), i))
2754 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2755 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2756 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2757 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2759 if (NumElems != 2 && NumElems != 4)
2762 for (unsigned i = 0; i < NumElems/2; ++i)
2763 if (!isUndefOrEqual(N->getMaskElt(i), i))
2766 for (unsigned i = 0; i < NumElems/2; ++i)
2767 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2773 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2774 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2775 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2776 bool V2IsSplat = false) {
2777 int NumElts = VT.getVectorNumElements();
2778 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2781 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2783 int BitI1 = Mask[i+1];
2784 if (!isUndefOrEqual(BitI, j))
2787 if (!isUndefOrEqual(BitI1, NumElts))
2790 if (!isUndefOrEqual(BitI1, j + NumElts))
2797 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2798 SmallVector<int, 8> M;
2800 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2803 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2804 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2805 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2806 bool V2IsSplat = false) {
2807 int NumElts = VT.getVectorNumElements();
2808 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2811 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2813 int BitI1 = Mask[i+1];
2814 if (!isUndefOrEqual(BitI, j + NumElts/2))
2817 if (isUndefOrEqual(BitI1, NumElts))
2820 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2827 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2828 SmallVector<int, 8> M;
2830 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2833 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2834 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2836 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2837 int NumElems = VT.getVectorNumElements();
2838 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2841 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2843 int BitI1 = Mask[i+1];
2844 if (!isUndefOrEqual(BitI, j))
2846 if (!isUndefOrEqual(BitI1, j))
2852 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2853 SmallVector<int, 8> M;
2855 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2858 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2859 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2861 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2862 int NumElems = VT.getVectorNumElements();
2863 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2866 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2868 int BitI1 = Mask[i+1];
2869 if (!isUndefOrEqual(BitI, j))
2871 if (!isUndefOrEqual(BitI1, j))
2877 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2878 SmallVector<int, 8> M;
2880 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2883 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2884 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2885 /// MOVSD, and MOVD, i.e. setting the lowest element.
2886 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2887 if (VT.getVectorElementType().getSizeInBits() < 32)
2890 int NumElts = VT.getVectorNumElements();
2892 if (!isUndefOrEqual(Mask[0], NumElts))
2895 for (int i = 1; i < NumElts; ++i)
2896 if (!isUndefOrEqual(Mask[i], i))
2902 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2903 SmallVector<int, 8> M;
2905 return ::isMOVLMask(M, N->getValueType(0));
2908 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2909 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2910 /// element of vector 2 and the other elements to come from vector 1 in order.
2911 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2912 bool V2IsSplat = false, bool V2IsUndef = false) {
2913 int NumOps = VT.getVectorNumElements();
2914 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2917 if (!isUndefOrEqual(Mask[0], 0))
2920 for (int i = 1; i < NumOps; ++i)
2921 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2922 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2923 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2929 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2930 bool V2IsUndef = false) {
2931 SmallVector<int, 8> M;
2933 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2936 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2937 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2938 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2939 if (N->getValueType(0).getVectorNumElements() != 4)
2942 // Expect 1, 1, 3, 3
2943 for (unsigned i = 0; i < 2; ++i) {
2944 int Elt = N->getMaskElt(i);
2945 if (Elt >= 0 && Elt != 1)
2950 for (unsigned i = 2; i < 4; ++i) {
2951 int Elt = N->getMaskElt(i);
2952 if (Elt >= 0 && Elt != 3)
2957 // Don't use movshdup if it can be done with a shufps.
2958 // FIXME: verify that matching u, u, 3, 3 is what we want.
2962 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2963 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2964 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2965 if (N->getValueType(0).getVectorNumElements() != 4)
2968 // Expect 0, 0, 2, 2
2969 for (unsigned i = 0; i < 2; ++i)
2970 if (N->getMaskElt(i) > 0)
2974 for (unsigned i = 2; i < 4; ++i) {
2975 int Elt = N->getMaskElt(i);
2976 if (Elt >= 0 && Elt != 2)
2981 // Don't use movsldup if it can be done with a shufps.
2985 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2986 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2987 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2988 int e = N->getValueType(0).getVectorNumElements() / 2;
2990 for (int i = 0; i < e; ++i)
2991 if (!isUndefOrEqual(N->getMaskElt(i), i))
2993 for (int i = 0; i < e; ++i)
2994 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2999 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3000 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3001 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3002 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3003 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3005 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3007 for (int i = 0; i < NumOperands; ++i) {
3008 int Val = SVOp->getMaskElt(NumOperands-i-1);
3009 if (Val < 0) Val = 0;
3010 if (Val >= NumOperands) Val -= NumOperands;
3012 if (i != NumOperands - 1)
3018 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3019 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3020 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3021 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3023 // 8 nodes, but we only care about the last 4.
3024 for (unsigned i = 7; i >= 4; --i) {
3025 int Val = SVOp->getMaskElt(i);
3034 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3035 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3036 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3037 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3039 // 8 nodes, but we only care about the first 4.
3040 for (int i = 3; i >= 0; --i) {
3041 int Val = SVOp->getMaskElt(i);
3050 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3051 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3052 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3053 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3054 EVT VVT = N->getValueType(0);
3055 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3059 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3060 Val = SVOp->getMaskElt(i);
3064 return (Val - i) * EltSize;
3067 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3069 bool X86::isZeroNode(SDValue Elt) {
3070 return ((isa<ConstantSDNode>(Elt) &&
3071 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
3072 (isa<ConstantFPSDNode>(Elt) &&
3073 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3076 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3077 /// their permute mask.
3078 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3079 SelectionDAG &DAG) {
3080 EVT VT = SVOp->getValueType(0);
3081 unsigned NumElems = VT.getVectorNumElements();
3082 SmallVector<int, 8> MaskVec;
3084 for (unsigned i = 0; i != NumElems; ++i) {
3085 int idx = SVOp->getMaskElt(i);
3087 MaskVec.push_back(idx);
3088 else if (idx < (int)NumElems)
3089 MaskVec.push_back(idx + NumElems);
3091 MaskVec.push_back(idx - NumElems);
3093 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3094 SVOp->getOperand(0), &MaskVec[0]);
3097 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3098 /// the two vector operands have swapped position.
3099 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3100 unsigned NumElems = VT.getVectorNumElements();
3101 for (unsigned i = 0; i != NumElems; ++i) {
3105 else if (idx < (int)NumElems)
3106 Mask[i] = idx + NumElems;
3108 Mask[i] = idx - NumElems;
3112 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3113 /// match movhlps. The lower half elements should come from upper half of
3114 /// V1 (and in order), and the upper half elements should come from the upper
3115 /// half of V2 (and in order).
3116 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3117 if (Op->getValueType(0).getVectorNumElements() != 4)
3119 for (unsigned i = 0, e = 2; i != e; ++i)
3120 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3122 for (unsigned i = 2; i != 4; ++i)
3123 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3128 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3129 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3131 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3132 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3134 N = N->getOperand(0).getNode();
3135 if (!ISD::isNON_EXTLoad(N))
3138 *LD = cast<LoadSDNode>(N);
3142 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3143 /// match movlp{s|d}. The lower half elements should come from lower half of
3144 /// V1 (and in order), and the upper half elements should come from the upper
3145 /// half of V2 (and in order). And since V1 will become the source of the
3146 /// MOVLP, it must be either a vector load or a scalar load to vector.
3147 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3148 ShuffleVectorSDNode *Op) {
3149 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3151 // Is V2 is a vector load, don't do this transformation. We will try to use
3152 // load folding shufps op.
3153 if (ISD::isNON_EXTLoad(V2))
3156 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3158 if (NumElems != 2 && NumElems != 4)
3160 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3161 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3163 for (unsigned i = NumElems/2; i != NumElems; ++i)
3164 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3169 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3171 static bool isSplatVector(SDNode *N) {
3172 if (N->getOpcode() != ISD::BUILD_VECTOR)
3175 SDValue SplatValue = N->getOperand(0);
3176 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3177 if (N->getOperand(i) != SplatValue)
3182 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3183 /// to an zero vector.
3184 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3185 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3186 SDValue V1 = N->getOperand(0);
3187 SDValue V2 = N->getOperand(1);
3188 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3189 for (unsigned i = 0; i != NumElems; ++i) {
3190 int Idx = N->getMaskElt(i);
3191 if (Idx >= (int)NumElems) {
3192 unsigned Opc = V2.getOpcode();
3193 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3195 if (Opc != ISD::BUILD_VECTOR ||
3196 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3198 } else if (Idx >= 0) {
3199 unsigned Opc = V1.getOpcode();
3200 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3202 if (Opc != ISD::BUILD_VECTOR ||
3203 !X86::isZeroNode(V1.getOperand(Idx)))
3210 /// getZeroVector - Returns a vector of specified type with all zero elements.
3212 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3214 assert(VT.isVector() && "Expected a vector type");
3216 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3217 // type. This ensures they get CSE'd.
3219 if (VT.getSizeInBits() == 64) { // MMX
3220 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3221 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3222 } else if (HasSSE2) { // SSE2
3223 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3224 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3226 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3227 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3229 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3232 /// getOnesVector - Returns a vector of specified type with all bits set.
3234 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3235 assert(VT.isVector() && "Expected a vector type");
3237 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3238 // type. This ensures they get CSE'd.
3239 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3241 if (VT.getSizeInBits() == 64) // MMX
3242 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3244 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3245 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3249 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3250 /// that point to V2 points to its first element.
3251 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3252 EVT VT = SVOp->getValueType(0);
3253 unsigned NumElems = VT.getVectorNumElements();
3255 bool Changed = false;
3256 SmallVector<int, 8> MaskVec;
3257 SVOp->getMask(MaskVec);
3259 for (unsigned i = 0; i != NumElems; ++i) {
3260 if (MaskVec[i] > (int)NumElems) {
3261 MaskVec[i] = NumElems;
3266 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3267 SVOp->getOperand(1), &MaskVec[0]);
3268 return SDValue(SVOp, 0);
3271 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3272 /// operation of specified width.
3273 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3275 unsigned NumElems = VT.getVectorNumElements();
3276 SmallVector<int, 8> Mask;
3277 Mask.push_back(NumElems);
3278 for (unsigned i = 1; i != NumElems; ++i)
3280 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3283 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3284 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3286 unsigned NumElems = VT.getVectorNumElements();
3287 SmallVector<int, 8> Mask;
3288 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3290 Mask.push_back(i + NumElems);
3292 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3295 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3296 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3298 unsigned NumElems = VT.getVectorNumElements();
3299 unsigned Half = NumElems/2;
3300 SmallVector<int, 8> Mask;
3301 for (unsigned i = 0; i != Half; ++i) {
3302 Mask.push_back(i + Half);
3303 Mask.push_back(i + NumElems + Half);
3305 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3308 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3309 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3311 if (SV->getValueType(0).getVectorNumElements() <= 4)
3312 return SDValue(SV, 0);
3314 EVT PVT = MVT::v4f32;
3315 EVT VT = SV->getValueType(0);
3316 DebugLoc dl = SV->getDebugLoc();
3317 SDValue V1 = SV->getOperand(0);
3318 int NumElems = VT.getVectorNumElements();
3319 int EltNo = SV->getSplatIndex();
3321 // unpack elements to the correct location
3322 while (NumElems > 4) {
3323 if (EltNo < NumElems/2) {
3324 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3326 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3327 EltNo -= NumElems/2;
3332 // Perform the splat.
3333 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3334 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3335 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3336 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3339 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3340 /// vector of zero or undef vector. This produces a shuffle where the low
3341 /// element of V2 is swizzled into the zero/undef vector, landing at element
3342 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3343 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3344 bool isZero, bool HasSSE2,
3345 SelectionDAG &DAG) {
3346 EVT VT = V2.getValueType();
3348 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3349 unsigned NumElems = VT.getVectorNumElements();
3350 SmallVector<int, 16> MaskVec;
3351 for (unsigned i = 0; i != NumElems; ++i)
3352 // If this is the insertion idx, put the low elt of V2 here.
3353 MaskVec.push_back(i == Idx ? NumElems : i);
3354 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3357 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3358 /// a shuffle that is zero.
3360 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3361 bool Low, SelectionDAG &DAG) {
3362 unsigned NumZeros = 0;
3363 for (int i = 0; i < NumElems; ++i) {
3364 unsigned Index = Low ? i : NumElems-i-1;
3365 int Idx = SVOp->getMaskElt(Index);
3370 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3371 if (Elt.getNode() && X86::isZeroNode(Elt))
3379 /// isVectorShift - Returns true if the shuffle can be implemented as a
3380 /// logical left or right shift of a vector.
3381 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3382 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3383 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3384 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3387 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3390 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3394 bool SeenV1 = false;
3395 bool SeenV2 = false;
3396 for (int i = NumZeros; i < NumElems; ++i) {
3397 int Val = isLeft ? (i - NumZeros) : i;
3398 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3410 if (SeenV1 && SeenV2)
3413 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3419 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3421 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3422 unsigned NumNonZero, unsigned NumZero,
3423 SelectionDAG &DAG, TargetLowering &TLI) {
3427 DebugLoc dl = Op.getDebugLoc();
3430 for (unsigned i = 0; i < 16; ++i) {
3431 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3432 if (ThisIsNonZero && First) {
3434 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3436 V = DAG.getUNDEF(MVT::v8i16);
3441 SDValue ThisElt(0, 0), LastElt(0, 0);
3442 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3443 if (LastIsNonZero) {
3444 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3445 MVT::i16, Op.getOperand(i-1));
3447 if (ThisIsNonZero) {
3448 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3449 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3450 ThisElt, DAG.getConstant(8, MVT::i8));
3452 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3456 if (ThisElt.getNode())
3457 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3458 DAG.getIntPtrConstant(i/2));
3462 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3465 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3467 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3468 unsigned NumNonZero, unsigned NumZero,
3469 SelectionDAG &DAG, TargetLowering &TLI) {
3473 DebugLoc dl = Op.getDebugLoc();
3476 for (unsigned i = 0; i < 8; ++i) {
3477 bool isNonZero = (NonZeros & (1 << i)) != 0;
3481 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3483 V = DAG.getUNDEF(MVT::v8i16);
3486 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3487 MVT::v8i16, V, Op.getOperand(i),
3488 DAG.getIntPtrConstant(i));
3495 /// getVShift - Return a vector logical shift node.
3497 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3498 unsigned NumBits, SelectionDAG &DAG,
3499 const TargetLowering &TLI, DebugLoc dl) {
3500 bool isMMX = VT.getSizeInBits() == 64;
3501 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3502 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3503 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3504 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3505 DAG.getNode(Opc, dl, ShVT, SrcOp,
3506 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3510 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3511 SelectionDAG &DAG) {
3513 // Check if the scalar load can be widened into a vector load. And if
3514 // the address is "base + cst" see if the cst can be "absorbed" into
3515 // the shuffle mask.
3516 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3517 SDValue Ptr = LD->getBasePtr();
3518 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3520 EVT PVT = LD->getValueType(0);
3521 if (PVT != MVT::i32 && PVT != MVT::f32)
3526 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
3527 FI = FINode->getIndex();
3529 } else if (Ptr.getOpcode() == ISD::ADD &&
3530 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
3531 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
3532 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
3533 Offset = Ptr.getConstantOperandVal(1);
3534 Ptr = Ptr.getOperand(0);
3539 SDValue Chain = LD->getChain();
3540 // Make sure the stack object alignment is at least 16.
3541 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3542 if (DAG.InferPtrAlignment(Ptr) < 16) {
3543 if (MFI->isFixedObjectIndex(FI)) {
3544 // Can't change the alignment. FIXME: It's possible to compute
3545 // the exact stack offset and reference FI + adjust offset instead.
3546 // If someone *really* cares about this. That's the way to implement it.
3549 MFI->setObjectAlignment(FI, 16);
3553 // (Offset % 16) must be multiple of 4. Then address is then
3554 // Ptr + (Offset & ~15).
3557 if ((Offset % 16) & 3)
3559 int64_t StartOffset = Offset & ~15;
3561 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
3562 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
3564 int EltNo = (Offset - StartOffset) >> 2;
3565 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
3566 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
3567 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0);
3568 // Canonicalize it to a v4i32 shuffle.
3569 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
3570 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3571 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
3572 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
3579 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3580 DebugLoc dl = Op.getDebugLoc();
3581 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3582 if (ISD::isBuildVectorAllZeros(Op.getNode())
3583 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3584 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3585 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3586 // eliminated on x86-32 hosts.
3587 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3590 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3591 return getOnesVector(Op.getValueType(), DAG, dl);
3592 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3595 EVT VT = Op.getValueType();
3596 EVT ExtVT = VT.getVectorElementType();
3597 unsigned EVTBits = ExtVT.getSizeInBits();
3599 unsigned NumElems = Op.getNumOperands();
3600 unsigned NumZero = 0;
3601 unsigned NumNonZero = 0;
3602 unsigned NonZeros = 0;
3603 bool IsAllConstants = true;
3604 SmallSet<SDValue, 8> Values;
3605 for (unsigned i = 0; i < NumElems; ++i) {
3606 SDValue Elt = Op.getOperand(i);
3607 if (Elt.getOpcode() == ISD::UNDEF)
3610 if (Elt.getOpcode() != ISD::Constant &&
3611 Elt.getOpcode() != ISD::ConstantFP)
3612 IsAllConstants = false;
3613 if (X86::isZeroNode(Elt))
3616 NonZeros |= (1 << i);
3621 if (NumNonZero == 0) {
3622 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3623 return DAG.getUNDEF(VT);
3626 // Special case for single non-zero, non-undef, element.
3627 if (NumNonZero == 1) {
3628 unsigned Idx = CountTrailingZeros_32(NonZeros);
3629 SDValue Item = Op.getOperand(Idx);
3631 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3632 // the value are obviously zero, truncate the value to i32 and do the
3633 // insertion that way. Only do this if the value is non-constant or if the
3634 // value is a constant being inserted into element 0. It is cheaper to do
3635 // a constant pool load than it is to do a movd + shuffle.
3636 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3637 (!IsAllConstants || Idx == 0)) {
3638 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3639 // Handle MMX and SSE both.
3640 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3641 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3643 // Truncate the value (which may itself be a constant) to i32, and
3644 // convert it to a vector with movd (S2V+shuffle to zero extend).
3645 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3646 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3647 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3648 Subtarget->hasSSE2(), DAG);
3650 // Now we have our 32-bit value zero extended in the low element of
3651 // a vector. If Idx != 0, swizzle it into place.
3653 SmallVector<int, 4> Mask;
3654 Mask.push_back(Idx);
3655 for (unsigned i = 1; i != VecElts; ++i)
3657 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3658 DAG.getUNDEF(Item.getValueType()),
3661 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3665 // If we have a constant or non-constant insertion into the low element of
3666 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3667 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3668 // depending on what the source datatype is.
3671 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3672 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3673 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3674 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3675 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3676 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3678 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3679 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3680 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3681 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3682 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3683 Subtarget->hasSSE2(), DAG);
3684 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3688 // Is it a vector logical left shift?
3689 if (NumElems == 2 && Idx == 1 &&
3690 X86::isZeroNode(Op.getOperand(0)) &&
3691 !X86::isZeroNode(Op.getOperand(1))) {
3692 unsigned NumBits = VT.getSizeInBits();
3693 return getVShift(true, VT,
3694 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3695 VT, Op.getOperand(1)),
3696 NumBits/2, DAG, *this, dl);
3699 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3702 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3703 // is a non-constant being inserted into an element other than the low one,
3704 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3705 // movd/movss) to move this into the low element, then shuffle it into
3707 if (EVTBits == 32) {
3708 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3710 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3711 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3712 Subtarget->hasSSE2(), DAG);
3713 SmallVector<int, 8> MaskVec;
3714 for (unsigned i = 0; i < NumElems; i++)
3715 MaskVec.push_back(i == Idx ? 0 : 1);
3716 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3720 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3721 if (Values.size() == 1) {
3722 if (EVTBits == 32) {
3723 // Instead of a shuffle like this:
3724 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
3725 // Check if it's possible to issue this instead.
3726 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
3727 unsigned Idx = CountTrailingZeros_32(NonZeros);
3728 SDValue Item = Op.getOperand(Idx);
3729 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
3730 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
3735 // A vector full of immediates; various special cases are already
3736 // handled, so this is best done with a single constant-pool load.
3740 // Let legalizer expand 2-wide build_vectors.
3741 if (EVTBits == 64) {
3742 if (NumNonZero == 1) {
3743 // One half is zero or undef.
3744 unsigned Idx = CountTrailingZeros_32(NonZeros);
3745 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3746 Op.getOperand(Idx));
3747 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3748 Subtarget->hasSSE2(), DAG);
3753 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3754 if (EVTBits == 8 && NumElems == 16) {
3755 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3757 if (V.getNode()) return V;
3760 if (EVTBits == 16 && NumElems == 8) {
3761 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3763 if (V.getNode()) return V;
3766 // If element VT is == 32 bits, turn it into a number of shuffles.
3767 SmallVector<SDValue, 8> V;
3769 if (NumElems == 4 && NumZero > 0) {
3770 for (unsigned i = 0; i < 4; ++i) {
3771 bool isZero = !(NonZeros & (1 << i));
3773 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3775 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3778 for (unsigned i = 0; i < 2; ++i) {
3779 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3782 V[i] = V[i*2]; // Must be a zero vector.
3785 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3788 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3791 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3796 SmallVector<int, 8> MaskVec;
3797 bool Reverse = (NonZeros & 0x3) == 2;
3798 for (unsigned i = 0; i < 2; ++i)
3799 MaskVec.push_back(Reverse ? 1-i : i);
3800 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3801 for (unsigned i = 0; i < 2; ++i)
3802 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3803 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3806 if (Values.size() > 2) {
3807 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3808 // values to be inserted is equal to the number of elements, in which case
3809 // use the unpack code below in the hopes of matching the consecutive elts
3810 // load merge pattern for shuffles.
3811 // FIXME: We could probably just check that here directly.
3812 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3813 getSubtarget()->hasSSE41()) {
3814 V[0] = DAG.getUNDEF(VT);
3815 for (unsigned i = 0; i < NumElems; ++i)
3816 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3817 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3818 Op.getOperand(i), DAG.getIntPtrConstant(i));
3821 // Expand into a number of unpckl*.
3823 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3824 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3825 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3826 for (unsigned i = 0; i < NumElems; ++i)
3827 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3829 while (NumElems != 0) {
3830 for (unsigned i = 0; i < NumElems; ++i)
3831 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3841 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3842 // We support concatenate two MMX registers and place them in a MMX
3843 // register. This is better than doing a stack convert.
3844 DebugLoc dl = Op.getDebugLoc();
3845 EVT ResVT = Op.getValueType();
3846 assert(Op.getNumOperands() == 2);
3847 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
3848 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
3850 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
3851 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3852 InVec = Op.getOperand(1);
3853 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3854 unsigned NumElts = ResVT.getVectorNumElements();
3855 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3856 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
3857 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
3859 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
3860 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
3861 Mask[0] = 0; Mask[1] = 2;
3862 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
3864 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
3867 // v8i16 shuffles - Prefer shuffles in the following order:
3868 // 1. [all] pshuflw, pshufhw, optional move
3869 // 2. [ssse3] 1 x pshufb
3870 // 3. [ssse3] 2 x pshufb + 1 x por
3871 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3873 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3874 SelectionDAG &DAG, X86TargetLowering &TLI) {
3875 SDValue V1 = SVOp->getOperand(0);
3876 SDValue V2 = SVOp->getOperand(1);
3877 DebugLoc dl = SVOp->getDebugLoc();
3878 SmallVector<int, 8> MaskVals;
3880 // Determine if more than 1 of the words in each of the low and high quadwords
3881 // of the result come from the same quadword of one of the two inputs. Undef
3882 // mask values count as coming from any quadword, for better codegen.
3883 SmallVector<unsigned, 4> LoQuad(4);
3884 SmallVector<unsigned, 4> HiQuad(4);
3885 BitVector InputQuads(4);
3886 for (unsigned i = 0; i < 8; ++i) {
3887 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3888 int EltIdx = SVOp->getMaskElt(i);
3889 MaskVals.push_back(EltIdx);
3898 InputQuads.set(EltIdx / 4);
3901 int BestLoQuad = -1;
3902 unsigned MaxQuad = 1;
3903 for (unsigned i = 0; i < 4; ++i) {
3904 if (LoQuad[i] > MaxQuad) {
3906 MaxQuad = LoQuad[i];
3910 int BestHiQuad = -1;
3912 for (unsigned i = 0; i < 4; ++i) {
3913 if (HiQuad[i] > MaxQuad) {
3915 MaxQuad = HiQuad[i];
3919 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3920 // of the two input vectors, shuffle them into one input vector so only a
3921 // single pshufb instruction is necessary. If There are more than 2 input
3922 // quads, disable the next transformation since it does not help SSSE3.
3923 bool V1Used = InputQuads[0] || InputQuads[1];
3924 bool V2Used = InputQuads[2] || InputQuads[3];
3925 if (TLI.getSubtarget()->hasSSSE3()) {
3926 if (InputQuads.count() == 2 && V1Used && V2Used) {
3927 BestLoQuad = InputQuads.find_first();
3928 BestHiQuad = InputQuads.find_next(BestLoQuad);
3930 if (InputQuads.count() > 2) {
3936 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3937 // the shuffle mask. If a quad is scored as -1, that means that it contains
3938 // words from all 4 input quadwords.
3940 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3941 SmallVector<int, 8> MaskV;
3942 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3943 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3944 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3945 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3946 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3947 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3949 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3950 // source words for the shuffle, to aid later transformations.
3951 bool AllWordsInNewV = true;
3952 bool InOrder[2] = { true, true };
3953 for (unsigned i = 0; i != 8; ++i) {
3954 int idx = MaskVals[i];
3956 InOrder[i/4] = false;
3957 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3959 AllWordsInNewV = false;
3963 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3964 if (AllWordsInNewV) {
3965 for (int i = 0; i != 8; ++i) {
3966 int idx = MaskVals[i];
3969 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3970 if ((idx != i) && idx < 4)
3972 if ((idx != i) && idx > 3)
3981 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3982 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3983 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3984 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3985 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3989 // If we have SSSE3, and all words of the result are from 1 input vector,
3990 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3991 // is present, fall back to case 4.
3992 if (TLI.getSubtarget()->hasSSSE3()) {
3993 SmallVector<SDValue,16> pshufbMask;
3995 // If we have elements from both input vectors, set the high bit of the
3996 // shuffle mask element to zero out elements that come from V2 in the V1
3997 // mask, and elements that come from V1 in the V2 mask, so that the two
3998 // results can be OR'd together.
3999 bool TwoInputs = V1Used && V2Used;
4000 for (unsigned i = 0; i != 8; ++i) {
4001 int EltIdx = MaskVals[i] * 2;
4002 if (TwoInputs && (EltIdx >= 16)) {
4003 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4004 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4007 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4008 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4010 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4011 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4012 DAG.getNode(ISD::BUILD_VECTOR, dl,
4013 MVT::v16i8, &pshufbMask[0], 16));
4015 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4017 // Calculate the shuffle mask for the second input, shuffle it, and
4018 // OR it with the first shuffled input.
4020 for (unsigned i = 0; i != 8; ++i) {
4021 int EltIdx = MaskVals[i] * 2;
4023 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4024 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4027 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4028 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4030 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4031 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4032 DAG.getNode(ISD::BUILD_VECTOR, dl,
4033 MVT::v16i8, &pshufbMask[0], 16));
4034 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4035 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4038 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4039 // and update MaskVals with new element order.
4040 BitVector InOrder(8);
4041 if (BestLoQuad >= 0) {
4042 SmallVector<int, 8> MaskV;
4043 for (int i = 0; i != 4; ++i) {
4044 int idx = MaskVals[i];
4046 MaskV.push_back(-1);
4048 } else if ((idx / 4) == BestLoQuad) {
4049 MaskV.push_back(idx & 3);
4052 MaskV.push_back(-1);
4055 for (unsigned i = 4; i != 8; ++i)
4057 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4061 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4062 // and update MaskVals with the new element order.
4063 if (BestHiQuad >= 0) {
4064 SmallVector<int, 8> MaskV;
4065 for (unsigned i = 0; i != 4; ++i)
4067 for (unsigned i = 4; i != 8; ++i) {
4068 int idx = MaskVals[i];
4070 MaskV.push_back(-1);
4072 } else if ((idx / 4) == BestHiQuad) {
4073 MaskV.push_back((idx & 3) + 4);
4076 MaskV.push_back(-1);
4079 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4083 // In case BestHi & BestLo were both -1, which means each quadword has a word
4084 // from each of the four input quadwords, calculate the InOrder bitvector now
4085 // before falling through to the insert/extract cleanup.
4086 if (BestLoQuad == -1 && BestHiQuad == -1) {
4088 for (int i = 0; i != 8; ++i)
4089 if (MaskVals[i] < 0 || MaskVals[i] == i)
4093 // The other elements are put in the right place using pextrw and pinsrw.
4094 for (unsigned i = 0; i != 8; ++i) {
4097 int EltIdx = MaskVals[i];
4100 SDValue ExtOp = (EltIdx < 8)
4101 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4102 DAG.getIntPtrConstant(EltIdx))
4103 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4104 DAG.getIntPtrConstant(EltIdx - 8));
4105 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4106 DAG.getIntPtrConstant(i));
4111 // v16i8 shuffles - Prefer shuffles in the following order:
4112 // 1. [ssse3] 1 x pshufb
4113 // 2. [ssse3] 2 x pshufb + 1 x por
4114 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4116 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4117 SelectionDAG &DAG, X86TargetLowering &TLI) {
4118 SDValue V1 = SVOp->getOperand(0);
4119 SDValue V2 = SVOp->getOperand(1);
4120 DebugLoc dl = SVOp->getDebugLoc();
4121 SmallVector<int, 16> MaskVals;
4122 SVOp->getMask(MaskVals);
4124 // If we have SSSE3, case 1 is generated when all result bytes come from
4125 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4126 // present, fall back to case 3.
4127 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4130 for (unsigned i = 0; i < 16; ++i) {
4131 int EltIdx = MaskVals[i];
4140 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4141 if (TLI.getSubtarget()->hasSSSE3()) {
4142 SmallVector<SDValue,16> pshufbMask;
4144 // If all result elements are from one input vector, then only translate
4145 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4147 // Otherwise, we have elements from both input vectors, and must zero out
4148 // elements that come from V2 in the first mask, and V1 in the second mask
4149 // so that we can OR them together.
4150 bool TwoInputs = !(V1Only || V2Only);
4151 for (unsigned i = 0; i != 16; ++i) {
4152 int EltIdx = MaskVals[i];
4153 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4154 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4157 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4159 // If all the elements are from V2, assign it to V1 and return after
4160 // building the first pshufb.
4163 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4164 DAG.getNode(ISD::BUILD_VECTOR, dl,
4165 MVT::v16i8, &pshufbMask[0], 16));
4169 // Calculate the shuffle mask for the second input, shuffle it, and
4170 // OR it with the first shuffled input.
4172 for (unsigned i = 0; i != 16; ++i) {
4173 int EltIdx = MaskVals[i];
4175 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4178 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4180 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4181 DAG.getNode(ISD::BUILD_VECTOR, dl,
4182 MVT::v16i8, &pshufbMask[0], 16));
4183 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4186 // No SSSE3 - Calculate in place words and then fix all out of place words
4187 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4188 // the 16 different words that comprise the two doublequadword input vectors.
4189 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4190 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4191 SDValue NewV = V2Only ? V2 : V1;
4192 for (int i = 0; i != 8; ++i) {
4193 int Elt0 = MaskVals[i*2];
4194 int Elt1 = MaskVals[i*2+1];
4196 // This word of the result is all undef, skip it.
4197 if (Elt0 < 0 && Elt1 < 0)
4200 // This word of the result is already in the correct place, skip it.
4201 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4203 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4206 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4207 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4210 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4211 // using a single extract together, load it and store it.
4212 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4213 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4214 DAG.getIntPtrConstant(Elt1 / 2));
4215 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4216 DAG.getIntPtrConstant(i));
4220 // If Elt1 is defined, extract it from the appropriate source. If the
4221 // source byte is not also odd, shift the extracted word left 8 bits
4222 // otherwise clear the bottom 8 bits if we need to do an or.
4224 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4225 DAG.getIntPtrConstant(Elt1 / 2));
4226 if ((Elt1 & 1) == 0)
4227 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4228 DAG.getConstant(8, TLI.getShiftAmountTy()));
4230 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4231 DAG.getConstant(0xFF00, MVT::i16));
4233 // If Elt0 is defined, extract it from the appropriate source. If the
4234 // source byte is not also even, shift the extracted word right 8 bits. If
4235 // Elt1 was also defined, OR the extracted values together before
4236 // inserting them in the result.
4238 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4239 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4240 if ((Elt0 & 1) != 0)
4241 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4242 DAG.getConstant(8, TLI.getShiftAmountTy()));
4244 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4245 DAG.getConstant(0x00FF, MVT::i16));
4246 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4249 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4250 DAG.getIntPtrConstant(i));
4252 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4255 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4256 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
4257 /// done when every pair / quad of shuffle mask elements point to elements in
4258 /// the right sequence. e.g.
4259 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4261 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4263 TargetLowering &TLI, DebugLoc dl) {
4264 EVT VT = SVOp->getValueType(0);
4265 SDValue V1 = SVOp->getOperand(0);
4266 SDValue V2 = SVOp->getOperand(1);
4267 unsigned NumElems = VT.getVectorNumElements();
4268 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4269 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
4270 EVT MaskEltVT = MaskVT.getVectorElementType();
4272 switch (VT.getSimpleVT().SimpleTy) {
4273 default: assert(false && "Unexpected!");
4274 case MVT::v4f32: NewVT = MVT::v2f64; break;
4275 case MVT::v4i32: NewVT = MVT::v2i64; break;
4276 case MVT::v8i16: NewVT = MVT::v4i32; break;
4277 case MVT::v16i8: NewVT = MVT::v4i32; break;
4280 if (NewWidth == 2) {
4286 int Scale = NumElems / NewWidth;
4287 SmallVector<int, 8> MaskVec;
4288 for (unsigned i = 0; i < NumElems; i += Scale) {
4290 for (int j = 0; j < Scale; ++j) {
4291 int EltIdx = SVOp->getMaskElt(i+j);
4295 StartIdx = EltIdx - (EltIdx % Scale);
4296 if (EltIdx != StartIdx + j)
4300 MaskVec.push_back(-1);
4302 MaskVec.push_back(StartIdx / Scale);
4305 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4306 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4307 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4310 /// getVZextMovL - Return a zero-extending vector move low node.
4312 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4313 SDValue SrcOp, SelectionDAG &DAG,
4314 const X86Subtarget *Subtarget, DebugLoc dl) {
4315 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4316 LoadSDNode *LD = NULL;
4317 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4318 LD = dyn_cast<LoadSDNode>(SrcOp);
4320 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4322 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4323 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4324 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4325 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4326 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4328 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4329 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4330 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4331 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4339 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4340 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4341 DAG.getNode(ISD::BIT_CONVERT, dl,
4345 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4348 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4349 SDValue V1 = SVOp->getOperand(0);
4350 SDValue V2 = SVOp->getOperand(1);
4351 DebugLoc dl = SVOp->getDebugLoc();
4352 EVT VT = SVOp->getValueType(0);
4354 SmallVector<std::pair<int, int>, 8> Locs;
4356 SmallVector<int, 8> Mask1(4U, -1);
4357 SmallVector<int, 8> PermMask;
4358 SVOp->getMask(PermMask);
4362 for (unsigned i = 0; i != 4; ++i) {
4363 int Idx = PermMask[i];
4365 Locs[i] = std::make_pair(-1, -1);
4367 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4369 Locs[i] = std::make_pair(0, NumLo);
4373 Locs[i] = std::make_pair(1, NumHi);
4375 Mask1[2+NumHi] = Idx;
4381 if (NumLo <= 2 && NumHi <= 2) {
4382 // If no more than two elements come from either vector. This can be
4383 // implemented with two shuffles. First shuffle gather the elements.
4384 // The second shuffle, which takes the first shuffle as both of its
4385 // vector operands, put the elements into the right order.
4386 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4388 SmallVector<int, 8> Mask2(4U, -1);
4390 for (unsigned i = 0; i != 4; ++i) {
4391 if (Locs[i].first == -1)
4394 unsigned Idx = (i < 2) ? 0 : 4;
4395 Idx += Locs[i].first * 2 + Locs[i].second;
4400 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4401 } else if (NumLo == 3 || NumHi == 3) {
4402 // Otherwise, we must have three elements from one vector, call it X, and
4403 // one element from the other, call it Y. First, use a shufps to build an
4404 // intermediate vector with the one element from Y and the element from X
4405 // that will be in the same half in the final destination (the indexes don't
4406 // matter). Then, use a shufps to build the final vector, taking the half
4407 // containing the element from Y from the intermediate, and the other half
4410 // Normalize it so the 3 elements come from V1.
4411 CommuteVectorShuffleMask(PermMask, VT);
4415 // Find the element from V2.
4417 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4418 int Val = PermMask[HiIndex];
4425 Mask1[0] = PermMask[HiIndex];
4427 Mask1[2] = PermMask[HiIndex^1];
4429 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4432 Mask1[0] = PermMask[0];
4433 Mask1[1] = PermMask[1];
4434 Mask1[2] = HiIndex & 1 ? 6 : 4;
4435 Mask1[3] = HiIndex & 1 ? 4 : 6;
4436 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4438 Mask1[0] = HiIndex & 1 ? 2 : 0;
4439 Mask1[1] = HiIndex & 1 ? 0 : 2;
4440 Mask1[2] = PermMask[2];
4441 Mask1[3] = PermMask[3];
4446 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4450 // Break it into (shuffle shuffle_hi, shuffle_lo).
4452 SmallVector<int,8> LoMask(4U, -1);
4453 SmallVector<int,8> HiMask(4U, -1);
4455 SmallVector<int,8> *MaskPtr = &LoMask;
4456 unsigned MaskIdx = 0;
4459 for (unsigned i = 0; i != 4; ++i) {
4466 int Idx = PermMask[i];
4468 Locs[i] = std::make_pair(-1, -1);
4469 } else if (Idx < 4) {
4470 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4471 (*MaskPtr)[LoIdx] = Idx;
4474 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4475 (*MaskPtr)[HiIdx] = Idx;
4480 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4481 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4482 SmallVector<int, 8> MaskOps;
4483 for (unsigned i = 0; i != 4; ++i) {
4484 if (Locs[i].first == -1) {
4485 MaskOps.push_back(-1);
4487 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4488 MaskOps.push_back(Idx);
4491 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4495 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4496 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4497 SDValue V1 = Op.getOperand(0);
4498 SDValue V2 = Op.getOperand(1);
4499 EVT VT = Op.getValueType();
4500 DebugLoc dl = Op.getDebugLoc();
4501 unsigned NumElems = VT.getVectorNumElements();
4502 bool isMMX = VT.getSizeInBits() == 64;
4503 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4504 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4505 bool V1IsSplat = false;
4506 bool V2IsSplat = false;
4508 if (isZeroShuffle(SVOp))
4509 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4511 // Promote splats to v4f32.
4512 if (SVOp->isSplat()) {
4513 if (isMMX || NumElems < 4)
4515 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4518 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4520 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4521 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4522 if (NewOp.getNode())
4523 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4524 LowerVECTOR_SHUFFLE(NewOp, DAG));
4525 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4526 // FIXME: Figure out a cleaner way to do this.
4527 // Try to make use of movq to zero out the top part.
4528 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4529 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4530 if (NewOp.getNode()) {
4531 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4532 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4533 DAG, Subtarget, dl);
4535 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4536 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4537 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4538 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4539 DAG, Subtarget, dl);
4543 if (X86::isPSHUFDMask(SVOp))
4546 // Check if this can be converted into a logical shift.
4547 bool isLeft = false;
4550 bool isShift = getSubtarget()->hasSSE2() &&
4551 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4552 if (isShift && ShVal.hasOneUse()) {
4553 // If the shifted value has multiple uses, it may be cheaper to use
4554 // v_set0 + movlhps or movhlps, etc.
4555 EVT EltVT = VT.getVectorElementType();
4556 ShAmt *= EltVT.getSizeInBits();
4557 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4560 if (X86::isMOVLMask(SVOp)) {
4563 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4564 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4569 // FIXME: fold these into legal mask.
4570 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4571 X86::isMOVSLDUPMask(SVOp) ||
4572 X86::isMOVHLPSMask(SVOp) ||
4573 X86::isMOVLHPSMask(SVOp) ||
4574 X86::isMOVLPMask(SVOp)))
4577 if (ShouldXformToMOVHLPS(SVOp) ||
4578 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4579 return CommuteVectorShuffle(SVOp, DAG);
4582 // No better options. Use a vshl / vsrl.
4583 EVT EltVT = VT.getVectorElementType();
4584 ShAmt *= EltVT.getSizeInBits();
4585 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4588 bool Commuted = false;
4589 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4590 // 1,1,1,1 -> v8i16 though.
4591 V1IsSplat = isSplatVector(V1.getNode());
4592 V2IsSplat = isSplatVector(V2.getNode());
4594 // Canonicalize the splat or undef, if present, to be on the RHS.
4595 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4596 Op = CommuteVectorShuffle(SVOp, DAG);
4597 SVOp = cast<ShuffleVectorSDNode>(Op);
4598 V1 = SVOp->getOperand(0);
4599 V2 = SVOp->getOperand(1);
4600 std::swap(V1IsSplat, V2IsSplat);
4601 std::swap(V1IsUndef, V2IsUndef);
4605 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4606 // Shuffling low element of v1 into undef, just return v1.
4609 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4610 // the instruction selector will not match, so get a canonical MOVL with
4611 // swapped operands to undo the commute.
4612 return getMOVL(DAG, dl, VT, V2, V1);
4615 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4616 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4617 X86::isUNPCKLMask(SVOp) ||
4618 X86::isUNPCKHMask(SVOp))
4622 // Normalize mask so all entries that point to V2 points to its first
4623 // element then try to match unpck{h|l} again. If match, return a
4624 // new vector_shuffle with the corrected mask.
4625 SDValue NewMask = NormalizeMask(SVOp, DAG);
4626 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4627 if (NSVOp != SVOp) {
4628 if (X86::isUNPCKLMask(NSVOp, true)) {
4630 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4637 // Commute is back and try unpck* again.
4638 // FIXME: this seems wrong.
4639 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4640 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4641 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4642 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4643 X86::isUNPCKLMask(NewSVOp) ||
4644 X86::isUNPCKHMask(NewSVOp))
4648 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4650 // Normalize the node to match x86 shuffle ops if needed
4651 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4652 return CommuteVectorShuffle(SVOp, DAG);
4654 // Check for legal shuffle and return?
4655 SmallVector<int, 16> PermMask;
4656 SVOp->getMask(PermMask);
4657 if (isShuffleMaskLegal(PermMask, VT))
4660 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4661 if (VT == MVT::v8i16) {
4662 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4663 if (NewOp.getNode())
4667 if (VT == MVT::v16i8) {
4668 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4669 if (NewOp.getNode())
4673 // Handle all 4 wide cases with a number of shuffles except for MMX.
4674 if (NumElems == 4 && !isMMX)
4675 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4681 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4682 SelectionDAG &DAG) {
4683 EVT VT = Op.getValueType();
4684 DebugLoc dl = Op.getDebugLoc();
4685 if (VT.getSizeInBits() == 8) {
4686 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4687 Op.getOperand(0), Op.getOperand(1));
4688 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4689 DAG.getValueType(VT));
4690 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4691 } else if (VT.getSizeInBits() == 16) {
4692 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4693 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4695 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4696 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4697 DAG.getNode(ISD::BIT_CONVERT, dl,
4701 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4702 Op.getOperand(0), Op.getOperand(1));
4703 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4704 DAG.getValueType(VT));
4705 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4706 } else if (VT == MVT::f32) {
4707 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4708 // the result back to FR32 register. It's only worth matching if the
4709 // result has a single use which is a store or a bitcast to i32. And in
4710 // the case of a store, it's not worth it if the index is a constant 0,
4711 // because a MOVSSmr can be used instead, which is smaller and faster.
4712 if (!Op.hasOneUse())
4714 SDNode *User = *Op.getNode()->use_begin();
4715 if ((User->getOpcode() != ISD::STORE ||
4716 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4717 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4718 (User->getOpcode() != ISD::BIT_CONVERT ||
4719 User->getValueType(0) != MVT::i32))
4721 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4722 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4725 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4726 } else if (VT == MVT::i32) {
4727 // ExtractPS works with constant index.
4728 if (isa<ConstantSDNode>(Op.getOperand(1)))
4736 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4737 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4740 if (Subtarget->hasSSE41()) {
4741 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4746 EVT VT = Op.getValueType();
4747 DebugLoc dl = Op.getDebugLoc();
4748 // TODO: handle v16i8.
4749 if (VT.getSizeInBits() == 16) {
4750 SDValue Vec = Op.getOperand(0);
4751 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4753 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4754 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4755 DAG.getNode(ISD::BIT_CONVERT, dl,
4758 // Transform it so it match pextrw which produces a 32-bit result.
4759 EVT EltVT = MVT::i32;
4760 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4761 Op.getOperand(0), Op.getOperand(1));
4762 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4763 DAG.getValueType(VT));
4764 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4765 } else if (VT.getSizeInBits() == 32) {
4766 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4770 // SHUFPS the element to the lowest double word, then movss.
4771 int Mask[4] = { Idx, -1, -1, -1 };
4772 EVT VVT = Op.getOperand(0).getValueType();
4773 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4774 DAG.getUNDEF(VVT), Mask);
4775 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4776 DAG.getIntPtrConstant(0));
4777 } else if (VT.getSizeInBits() == 64) {
4778 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4779 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4780 // to match extract_elt for f64.
4781 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4785 // UNPCKHPD the element to the lowest double word, then movsd.
4786 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4787 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4788 int Mask[2] = { 1, -1 };
4789 EVT VVT = Op.getOperand(0).getValueType();
4790 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4791 DAG.getUNDEF(VVT), Mask);
4792 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4793 DAG.getIntPtrConstant(0));
4800 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4801 EVT VT = Op.getValueType();
4802 EVT EltVT = VT.getVectorElementType();
4803 DebugLoc dl = Op.getDebugLoc();
4805 SDValue N0 = Op.getOperand(0);
4806 SDValue N1 = Op.getOperand(1);
4807 SDValue N2 = Op.getOperand(2);
4809 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4810 isa<ConstantSDNode>(N2)) {
4811 unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4813 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4815 if (N1.getValueType() != MVT::i32)
4816 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4817 if (N2.getValueType() != MVT::i32)
4818 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4819 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4820 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4821 // Bits [7:6] of the constant are the source select. This will always be
4822 // zero here. The DAG Combiner may combine an extract_elt index into these
4823 // bits. For example (insert (extract, 3), 2) could be matched by putting
4824 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4825 // Bits [5:4] of the constant are the destination select. This is the
4826 // value of the incoming immediate.
4827 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4828 // combine either bitwise AND or insert of float 0.0 to set these bits.
4829 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4830 // Create this as a scalar to vector..
4831 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4832 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4833 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4834 // PINSR* works with constant index.
4841 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4842 EVT VT = Op.getValueType();
4843 EVT EltVT = VT.getVectorElementType();
4845 if (Subtarget->hasSSE41())
4846 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4848 if (EltVT == MVT::i8)
4851 DebugLoc dl = Op.getDebugLoc();
4852 SDValue N0 = Op.getOperand(0);
4853 SDValue N1 = Op.getOperand(1);
4854 SDValue N2 = Op.getOperand(2);
4856 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4857 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4858 // as its second argument.
4859 if (N1.getValueType() != MVT::i32)
4860 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4861 if (N2.getValueType() != MVT::i32)
4862 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4863 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4869 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4870 DebugLoc dl = Op.getDebugLoc();
4871 if (Op.getValueType() == MVT::v2f32)
4872 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4873 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4874 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4875 Op.getOperand(0))));
4877 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4878 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4880 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4881 EVT VT = MVT::v2i32;
4882 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4889 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4890 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4893 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4894 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4895 // one of the above mentioned nodes. It has to be wrapped because otherwise
4896 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4897 // be used to form addressing mode. These wrapped nodes will be selected
4900 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4901 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4903 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4905 unsigned char OpFlag = 0;
4906 unsigned WrapperKind = X86ISD::Wrapper;
4907 CodeModel::Model M = getTargetMachine().getCodeModel();
4909 if (Subtarget->isPICStyleRIPRel() &&
4910 (M == CodeModel::Small || M == CodeModel::Kernel))
4911 WrapperKind = X86ISD::WrapperRIP;
4912 else if (Subtarget->isPICStyleGOT())
4913 OpFlag = X86II::MO_GOTOFF;
4914 else if (Subtarget->isPICStyleStubPIC())
4915 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4917 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4919 CP->getOffset(), OpFlag);
4920 DebugLoc DL = CP->getDebugLoc();
4921 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4922 // With PIC, the address is actually $g + Offset.
4924 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4925 DAG.getNode(X86ISD::GlobalBaseReg,
4926 DebugLoc::getUnknownLoc(), getPointerTy()),
4933 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4934 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4936 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4938 unsigned char OpFlag = 0;
4939 unsigned WrapperKind = X86ISD::Wrapper;
4940 CodeModel::Model M = getTargetMachine().getCodeModel();
4942 if (Subtarget->isPICStyleRIPRel() &&
4943 (M == CodeModel::Small || M == CodeModel::Kernel))
4944 WrapperKind = X86ISD::WrapperRIP;
4945 else if (Subtarget->isPICStyleGOT())
4946 OpFlag = X86II::MO_GOTOFF;
4947 else if (Subtarget->isPICStyleStubPIC())
4948 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4950 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4952 DebugLoc DL = JT->getDebugLoc();
4953 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4955 // With PIC, the address is actually $g + Offset.
4957 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4958 DAG.getNode(X86ISD::GlobalBaseReg,
4959 DebugLoc::getUnknownLoc(), getPointerTy()),
4967 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4968 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4970 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4972 unsigned char OpFlag = 0;
4973 unsigned WrapperKind = X86ISD::Wrapper;
4974 CodeModel::Model M = getTargetMachine().getCodeModel();
4976 if (Subtarget->isPICStyleRIPRel() &&
4977 (M == CodeModel::Small || M == CodeModel::Kernel))
4978 WrapperKind = X86ISD::WrapperRIP;
4979 else if (Subtarget->isPICStyleGOT())
4980 OpFlag = X86II::MO_GOTOFF;
4981 else if (Subtarget->isPICStyleStubPIC())
4982 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4984 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4986 DebugLoc DL = Op.getDebugLoc();
4987 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4990 // With PIC, the address is actually $g + Offset.
4991 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4992 !Subtarget->is64Bit()) {
4993 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4994 DAG.getNode(X86ISD::GlobalBaseReg,
4995 DebugLoc::getUnknownLoc(),
5004 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
5005 // Create the TargetBlockAddressAddress node.
5006 unsigned char OpFlags =
5007 Subtarget->ClassifyBlockAddressReference();
5008 CodeModel::Model M = getTargetMachine().getCodeModel();
5009 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5010 DebugLoc dl = Op.getDebugLoc();
5011 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5012 /*isTarget=*/true, OpFlags);
5014 if (Subtarget->isPICStyleRIPRel() &&
5015 (M == CodeModel::Small || M == CodeModel::Kernel))
5016 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5018 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5020 // With PIC, the address is actually $g + Offset.
5021 if (isGlobalRelativeToPICBase(OpFlags)) {
5022 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5023 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5031 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5033 SelectionDAG &DAG) const {
5034 // Create the TargetGlobalAddress node, folding in the constant
5035 // offset if it is legal.
5036 unsigned char OpFlags =
5037 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5038 CodeModel::Model M = getTargetMachine().getCodeModel();
5040 if (OpFlags == X86II::MO_NO_FLAG &&
5041 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5042 // A direct static reference to a global.
5043 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
5046 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
5049 if (Subtarget->isPICStyleRIPRel() &&
5050 (M == CodeModel::Small || M == CodeModel::Kernel))
5051 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5053 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5055 // With PIC, the address is actually $g + Offset.
5056 if (isGlobalRelativeToPICBase(OpFlags)) {
5057 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5058 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5062 // For globals that require a load from a stub to get the address, emit the
5064 if (isGlobalStubReference(OpFlags))
5065 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5066 PseudoSourceValue::getGOT(), 0);
5068 // If there was a non-zero offset that we didn't fold, create an explicit
5071 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5072 DAG.getConstant(Offset, getPointerTy()));
5078 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
5079 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5080 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5081 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5085 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5086 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5087 unsigned char OperandFlags) {
5088 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5089 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5090 DebugLoc dl = GA->getDebugLoc();
5091 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
5092 GA->getValueType(0),
5096 SDValue Ops[] = { Chain, TGA, *InFlag };
5097 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5099 SDValue Ops[] = { Chain, TGA };
5100 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5103 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5104 MFI->setHasCalls(true);
5106 SDValue Flag = Chain.getValue(1);
5107 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5110 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5112 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5115 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5116 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5117 DAG.getNode(X86ISD::GlobalBaseReg,
5118 DebugLoc::getUnknownLoc(),
5120 InFlag = Chain.getValue(1);
5122 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5125 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5127 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5129 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5130 X86::RAX, X86II::MO_TLSGD);
5133 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
5134 // "local exec" model.
5135 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5136 const EVT PtrVT, TLSModel::Model model,
5138 DebugLoc dl = GA->getDebugLoc();
5139 // Get the Thread Pointer
5140 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
5141 DebugLoc::getUnknownLoc(), PtrVT,
5142 DAG.getRegister(is64Bit? X86::FS : X86::GS,
5145 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
5148 unsigned char OperandFlags = 0;
5149 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
5151 unsigned WrapperKind = X86ISD::Wrapper;
5152 if (model == TLSModel::LocalExec) {
5153 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
5154 } else if (is64Bit) {
5155 assert(model == TLSModel::InitialExec);
5156 OperandFlags = X86II::MO_GOTTPOFF;
5157 WrapperKind = X86ISD::WrapperRIP;
5159 assert(model == TLSModel::InitialExec);
5160 OperandFlags = X86II::MO_INDNTPOFF;
5163 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
5165 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5166 GA->getOffset(), OperandFlags);
5167 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
5169 if (model == TLSModel::InitialExec)
5170 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
5171 PseudoSourceValue::getGOT(), 0);
5173 // The address of the thread local variable is the add of the thread
5174 // pointer with the offset of the variable.
5175 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
5179 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
5180 // TODO: implement the "local dynamic" model
5181 // TODO: implement the "initial exec"model for pic executables
5182 assert(Subtarget->isTargetELF() &&
5183 "TLS not implemented for non-ELF targets");
5184 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
5185 const GlobalValue *GV = GA->getGlobal();
5187 // If GV is an alias then use the aliasee for determining
5188 // thread-localness.
5189 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
5190 GV = GA->resolveAliasedGlobal(false);
5192 TLSModel::Model model = getTLSModel(GV,
5193 getTargetMachine().getRelocationModel());
5196 case TLSModel::GeneralDynamic:
5197 case TLSModel::LocalDynamic: // not implemented
5198 if (Subtarget->is64Bit())
5199 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
5200 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
5202 case TLSModel::InitialExec:
5203 case TLSModel::LocalExec:
5204 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
5205 Subtarget->is64Bit());
5208 llvm_unreachable("Unreachable");
5213 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
5214 /// take a 2 x i32 value to shift plus a shift amount.
5215 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
5216 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
5217 EVT VT = Op.getValueType();
5218 unsigned VTBits = VT.getSizeInBits();
5219 DebugLoc dl = Op.getDebugLoc();
5220 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
5221 SDValue ShOpLo = Op.getOperand(0);
5222 SDValue ShOpHi = Op.getOperand(1);
5223 SDValue ShAmt = Op.getOperand(2);
5224 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
5225 DAG.getConstant(VTBits - 1, MVT::i8))
5226 : DAG.getConstant(0, VT);
5229 if (Op.getOpcode() == ISD::SHL_PARTS) {
5230 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
5231 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5233 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
5234 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
5237 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
5238 DAG.getConstant(VTBits, MVT::i8));
5239 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
5240 AndNode, DAG.getConstant(0, MVT::i8));
5243 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5244 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
5245 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
5247 if (Op.getOpcode() == ISD::SHL_PARTS) {
5248 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5249 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5251 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
5252 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
5255 SDValue Ops[2] = { Lo, Hi };
5256 return DAG.getMergeValues(Ops, 2, dl);
5259 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5260 EVT SrcVT = Op.getOperand(0).getValueType();
5262 if (SrcVT.isVector()) {
5263 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
5269 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
5270 "Unknown SINT_TO_FP to lower!");
5272 // These are really Legal; return the operand so the caller accepts it as
5274 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
5276 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
5277 Subtarget->is64Bit()) {
5281 DebugLoc dl = Op.getDebugLoc();
5282 unsigned Size = SrcVT.getSizeInBits()/8;
5283 MachineFunction &MF = DAG.getMachineFunction();
5284 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5285 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5286 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5288 PseudoSourceValue::getFixedStack(SSFI), 0);
5289 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5292 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5294 SelectionDAG &DAG) {
5296 DebugLoc dl = Op.getDebugLoc();
5298 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5300 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5302 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5303 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
5304 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5305 Tys, Ops, array_lengthof(Ops));
5308 Chain = Result.getValue(1);
5309 SDValue InFlag = Result.getValue(2);
5311 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5312 // shouldn't be necessary except that RFP cannot be live across
5313 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5314 MachineFunction &MF = DAG.getMachineFunction();
5315 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5316 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5317 Tys = DAG.getVTList(MVT::Other);
5319 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
5321 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
5322 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5323 PseudoSourceValue::getFixedStack(SSFI), 0);
5329 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5330 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5331 // This algorithm is not obvious. Here it is in C code, more or less:
5333 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5334 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5335 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5337 // Copy ints to xmm registers.
5338 __m128i xh = _mm_cvtsi32_si128( hi );
5339 __m128i xl = _mm_cvtsi32_si128( lo );
5341 // Combine into low half of a single xmm register.
5342 __m128i x = _mm_unpacklo_epi32( xh, xl );
5346 // Merge in appropriate exponents to give the integer bits the right
5348 x = _mm_unpacklo_epi32( x, exp );
5350 // Subtract away the biases to deal with the IEEE-754 double precision
5352 d = _mm_sub_pd( (__m128d) x, bias );
5354 // All conversions up to here are exact. The correctly rounded result is
5355 // calculated using the current rounding mode using the following
5357 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5358 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5359 // store doesn't really need to be here (except
5360 // maybe to zero the other double)
5365 DebugLoc dl = Op.getDebugLoc();
5366 LLVMContext *Context = DAG.getContext();
5368 // Build some magic constants.
5369 std::vector<Constant*> CV0;
5370 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5371 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5372 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5373 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5374 Constant *C0 = ConstantVector::get(CV0);
5375 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5377 std::vector<Constant*> CV1;
5379 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5381 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5382 Constant *C1 = ConstantVector::get(CV1);
5383 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5385 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5386 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5388 DAG.getIntPtrConstant(1)));
5389 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5390 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5392 DAG.getIntPtrConstant(0)));
5393 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5394 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5395 PseudoSourceValue::getConstantPool(), 0,
5397 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5398 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5399 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5400 PseudoSourceValue::getConstantPool(), 0,
5402 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5404 // Add the halves; easiest way is to swap them into another reg first.
5405 int ShufMask[2] = { 1, -1 };
5406 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5407 DAG.getUNDEF(MVT::v2f64), ShufMask);
5408 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5409 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5410 DAG.getIntPtrConstant(0));
5413 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5414 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5415 DebugLoc dl = Op.getDebugLoc();
5416 // FP constant to bias correct the final result.
5417 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5420 // Load the 32-bit value into an XMM register.
5421 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5422 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5424 DAG.getIntPtrConstant(0)));
5426 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5427 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5428 DAG.getIntPtrConstant(0));
5430 // Or the load with the bias.
5431 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5432 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5433 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5435 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5436 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5437 MVT::v2f64, Bias)));
5438 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5439 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5440 DAG.getIntPtrConstant(0));
5442 // Subtract the bias.
5443 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5445 // Handle final rounding.
5446 EVT DestVT = Op.getValueType();
5448 if (DestVT.bitsLT(MVT::f64)) {
5449 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5450 DAG.getIntPtrConstant(0));
5451 } else if (DestVT.bitsGT(MVT::f64)) {
5452 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5455 // Handle final rounding.
5459 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5460 SDValue N0 = Op.getOperand(0);
5461 DebugLoc dl = Op.getDebugLoc();
5463 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5464 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5465 // the optimization here.
5466 if (DAG.SignBitIsZero(N0))
5467 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5469 EVT SrcVT = N0.getValueType();
5470 if (SrcVT == MVT::i64) {
5471 // We only handle SSE2 f64 target here; caller can expand the rest.
5472 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5475 return LowerUINT_TO_FP_i64(Op, DAG);
5476 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5477 return LowerUINT_TO_FP_i32(Op, DAG);
5480 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5482 // Make a 64-bit buffer, and use it to build an FILD.
5483 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5484 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5485 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5486 getPointerTy(), StackSlot, WordOff);
5487 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5488 StackSlot, NULL, 0);
5489 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5490 OffsetSlot, NULL, 0);
5491 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5494 std::pair<SDValue,SDValue> X86TargetLowering::
5495 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5496 DebugLoc dl = Op.getDebugLoc();
5498 EVT DstTy = Op.getValueType();
5501 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5505 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5506 DstTy.getSimpleVT() >= MVT::i16 &&
5507 "Unknown FP_TO_SINT to lower!");
5509 // These are really Legal.
5510 if (DstTy == MVT::i32 &&
5511 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5512 return std::make_pair(SDValue(), SDValue());
5513 if (Subtarget->is64Bit() &&
5514 DstTy == MVT::i64 &&
5515 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5516 return std::make_pair(SDValue(), SDValue());
5518 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5520 MachineFunction &MF = DAG.getMachineFunction();
5521 unsigned MemSize = DstTy.getSizeInBits()/8;
5522 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5523 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5526 switch (DstTy.getSimpleVT().SimpleTy) {
5527 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5528 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5529 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5530 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5533 SDValue Chain = DAG.getEntryNode();
5534 SDValue Value = Op.getOperand(0);
5535 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5536 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5537 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5538 PseudoSourceValue::getFixedStack(SSFI), 0);
5539 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5541 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5543 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5544 Chain = Value.getValue(1);
5545 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5546 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5549 // Build the FP_TO_INT*_IN_MEM
5550 SDValue Ops[] = { Chain, Value, StackSlot };
5551 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5553 return std::make_pair(FIST, StackSlot);
5556 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5557 if (Op.getValueType().isVector()) {
5558 if (Op.getValueType() == MVT::v2i32 &&
5559 Op.getOperand(0).getValueType() == MVT::v2f64) {
5565 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5566 SDValue FIST = Vals.first, StackSlot = Vals.second;
5567 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5568 if (FIST.getNode() == 0) return Op;
5571 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5572 FIST, StackSlot, NULL, 0);
5575 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5576 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5577 SDValue FIST = Vals.first, StackSlot = Vals.second;
5578 assert(FIST.getNode() && "Unexpected failure");
5581 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5582 FIST, StackSlot, NULL, 0);
5585 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5586 LLVMContext *Context = DAG.getContext();
5587 DebugLoc dl = Op.getDebugLoc();
5588 EVT VT = Op.getValueType();
5591 EltVT = VT.getVectorElementType();
5592 std::vector<Constant*> CV;
5593 if (EltVT == MVT::f64) {
5594 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5598 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5604 Constant *C = ConstantVector::get(CV);
5605 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5606 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5607 PseudoSourceValue::getConstantPool(), 0,
5609 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5612 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5613 LLVMContext *Context = DAG.getContext();
5614 DebugLoc dl = Op.getDebugLoc();
5615 EVT VT = Op.getValueType();
5618 EltVT = VT.getVectorElementType();
5619 std::vector<Constant*> CV;
5620 if (EltVT == MVT::f64) {
5621 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5625 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5631 Constant *C = ConstantVector::get(CV);
5632 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5633 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5634 PseudoSourceValue::getConstantPool(), 0,
5636 if (VT.isVector()) {
5637 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5638 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5639 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5641 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5643 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5647 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5648 LLVMContext *Context = DAG.getContext();
5649 SDValue Op0 = Op.getOperand(0);
5650 SDValue Op1 = Op.getOperand(1);
5651 DebugLoc dl = Op.getDebugLoc();
5652 EVT VT = Op.getValueType();
5653 EVT SrcVT = Op1.getValueType();
5655 // If second operand is smaller, extend it first.
5656 if (SrcVT.bitsLT(VT)) {
5657 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5660 // And if it is bigger, shrink it first.
5661 if (SrcVT.bitsGT(VT)) {
5662 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5666 // At this point the operands and the result should have the same
5667 // type, and that won't be f80 since that is not custom lowered.
5669 // First get the sign bit of second operand.
5670 std::vector<Constant*> CV;
5671 if (SrcVT == MVT::f64) {
5672 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5673 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5675 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5676 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5677 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5678 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5680 Constant *C = ConstantVector::get(CV);
5681 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5682 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5683 PseudoSourceValue::getConstantPool(), 0,
5685 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5687 // Shift sign bit right or left if the two operands have different types.
5688 if (SrcVT.bitsGT(VT)) {
5689 // Op0 is MVT::f32, Op1 is MVT::f64.
5690 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5691 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5692 DAG.getConstant(32, MVT::i32));
5693 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5694 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5695 DAG.getIntPtrConstant(0));
5698 // Clear first operand sign bit.
5700 if (VT == MVT::f64) {
5701 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5702 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5704 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5705 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5706 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5707 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5709 C = ConstantVector::get(CV);
5710 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5711 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5712 PseudoSourceValue::getConstantPool(), 0,
5714 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5716 // Or the value with the sign bit.
5717 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5720 /// Emit nodes that will be selected as "test Op0,Op0", or something
5722 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5723 SelectionDAG &DAG) {
5724 DebugLoc dl = Op.getDebugLoc();
5726 // CF and OF aren't always set the way we want. Determine which
5727 // of these we need.
5728 bool NeedCF = false;
5729 bool NeedOF = false;
5731 case X86::COND_A: case X86::COND_AE:
5732 case X86::COND_B: case X86::COND_BE:
5735 case X86::COND_G: case X86::COND_GE:
5736 case X86::COND_L: case X86::COND_LE:
5737 case X86::COND_O: case X86::COND_NO:
5743 // See if we can use the EFLAGS value from the operand instead of
5744 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5745 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5746 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5747 unsigned Opcode = 0;
5748 unsigned NumOperands = 0;
5749 switch (Op.getNode()->getOpcode()) {
5751 // Due to an isel shortcoming, be conservative if this add is likely to
5752 // be selected as part of a load-modify-store instruction. When the root
5753 // node in a match is a store, isel doesn't know how to remap non-chain
5754 // non-flag uses of other nodes in the match, such as the ADD in this
5755 // case. This leads to the ADD being left around and reselected, with
5756 // the result being two adds in the output.
5757 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5758 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5759 if (UI->getOpcode() == ISD::STORE)
5761 if (ConstantSDNode *C =
5762 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5763 // An add of one will be selected as an INC.
5764 if (C->getAPIntValue() == 1) {
5765 Opcode = X86ISD::INC;
5769 // An add of negative one (subtract of one) will be selected as a DEC.
5770 if (C->getAPIntValue().isAllOnesValue()) {
5771 Opcode = X86ISD::DEC;
5776 // Otherwise use a regular EFLAGS-setting add.
5777 Opcode = X86ISD::ADD;
5781 // If the primary and result isn't used, don't bother using X86ISD::AND,
5782 // because a TEST instruction will be better.
5783 bool NonFlagUse = false;
5784 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5785 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
5787 unsigned UOpNo = UI.getOperandNo();
5788 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
5789 // Look pass truncate.
5790 UOpNo = User->use_begin().getOperandNo();
5791 User = *User->use_begin();
5793 if (User->getOpcode() != ISD::BRCOND &&
5794 User->getOpcode() != ISD::SETCC &&
5795 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
5807 // Due to the ISEL shortcoming noted above, be conservative if this op is
5808 // likely to be selected as part of a load-modify-store instruction.
5809 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5810 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5811 if (UI->getOpcode() == ISD::STORE)
5813 // Otherwise use a regular EFLAGS-setting instruction.
5814 switch (Op.getNode()->getOpcode()) {
5815 case ISD::SUB: Opcode = X86ISD::SUB; break;
5816 case ISD::OR: Opcode = X86ISD::OR; break;
5817 case ISD::XOR: Opcode = X86ISD::XOR; break;
5818 case ISD::AND: Opcode = X86ISD::AND; break;
5819 default: llvm_unreachable("unexpected operator!");
5830 return SDValue(Op.getNode(), 1);
5836 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5837 SmallVector<SDValue, 4> Ops;
5838 for (unsigned i = 0; i != NumOperands; ++i)
5839 Ops.push_back(Op.getOperand(i));
5840 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5841 DAG.ReplaceAllUsesWith(Op, New);
5842 return SDValue(New.getNode(), 1);
5846 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5847 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5848 DAG.getConstant(0, Op.getValueType()));
5851 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5853 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5854 SelectionDAG &DAG) {
5855 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5856 if (C->getAPIntValue() == 0)
5857 return EmitTest(Op0, X86CC, DAG);
5859 DebugLoc dl = Op0.getDebugLoc();
5860 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5863 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
5864 /// if it's possible.
5865 static SDValue LowerToBT(SDValue Op0, ISD::CondCode CC,
5866 DebugLoc dl, SelectionDAG &DAG) {
5868 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5869 if (ConstantSDNode *Op010C =
5870 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5871 if (Op010C->getZExtValue() == 1) {
5872 LHS = Op0.getOperand(0);
5873 RHS = Op0.getOperand(1).getOperand(1);
5875 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5876 if (ConstantSDNode *Op000C =
5877 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5878 if (Op000C->getZExtValue() == 1) {
5879 LHS = Op0.getOperand(1);
5880 RHS = Op0.getOperand(0).getOperand(1);
5882 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5883 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5884 SDValue AndLHS = Op0.getOperand(0);
5885 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5886 LHS = AndLHS.getOperand(0);
5887 RHS = AndLHS.getOperand(1);
5891 if (LHS.getNode()) {
5892 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5893 // instruction. Since the shift amount is in-range-or-undefined, we know
5894 // that doing a bittest on the i16 value is ok. We extend to i32 because
5895 // the encoding for the i16 version is larger than the i32 version.
5896 if (LHS.getValueType() == MVT::i8)
5897 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5899 // If the operand types disagree, extend the shift amount to match. Since
5900 // BT ignores high bits (like shifts) we can use anyextend.
5901 if (LHS.getValueType() != RHS.getValueType())
5902 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5904 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5905 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5906 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5907 DAG.getConstant(Cond, MVT::i8), BT);
5913 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5914 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5915 SDValue Op0 = Op.getOperand(0);
5916 SDValue Op1 = Op.getOperand(1);
5917 DebugLoc dl = Op.getDebugLoc();
5918 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5920 // Optimize to BT if possible.
5921 // Lower (X & (1 << N)) == 0 to BT(X, N).
5922 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5923 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5924 if (Op0.getOpcode() == ISD::AND &&
5926 Op1.getOpcode() == ISD::Constant &&
5927 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5928 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5929 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
5930 if (NewSetCC.getNode())
5934 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5935 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5936 if (X86CC == X86::COND_INVALID)
5939 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5941 // Use sbb x, x to materialize carry bit into a GPR.
5942 if (X86CC == X86::COND_B)
5943 return DAG.getNode(ISD::AND, dl, MVT::i8,
5944 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
5945 DAG.getConstant(X86CC, MVT::i8), Cond),
5946 DAG.getConstant(1, MVT::i8));
5948 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5949 DAG.getConstant(X86CC, MVT::i8), Cond);
5952 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5954 SDValue Op0 = Op.getOperand(0);
5955 SDValue Op1 = Op.getOperand(1);
5956 SDValue CC = Op.getOperand(2);
5957 EVT VT = Op.getValueType();
5958 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5959 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5960 DebugLoc dl = Op.getDebugLoc();
5964 EVT VT0 = Op0.getValueType();
5965 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5966 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5969 switch (SetCCOpcode) {
5972 case ISD::SETEQ: SSECC = 0; break;
5974 case ISD::SETGT: Swap = true; // Fallthrough
5976 case ISD::SETOLT: SSECC = 1; break;
5978 case ISD::SETGE: Swap = true; // Fallthrough
5980 case ISD::SETOLE: SSECC = 2; break;
5981 case ISD::SETUO: SSECC = 3; break;
5983 case ISD::SETNE: SSECC = 4; break;
5984 case ISD::SETULE: Swap = true;
5985 case ISD::SETUGE: SSECC = 5; break;
5986 case ISD::SETULT: Swap = true;
5987 case ISD::SETUGT: SSECC = 6; break;
5988 case ISD::SETO: SSECC = 7; break;
5991 std::swap(Op0, Op1);
5993 // In the two special cases we can't handle, emit two comparisons.
5995 if (SetCCOpcode == ISD::SETUEQ) {
5997 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5998 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5999 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
6001 else if (SetCCOpcode == ISD::SETONE) {
6003 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
6004 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
6005 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
6007 llvm_unreachable("Illegal FP comparison");
6009 // Handle all other FP comparisons here.
6010 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
6013 // We are handling one of the integer comparisons here. Since SSE only has
6014 // GT and EQ comparisons for integer, swapping operands and multiple
6015 // operations may be required for some comparisons.
6016 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
6017 bool Swap = false, Invert = false, FlipSigns = false;
6019 switch (VT.getSimpleVT().SimpleTy) {
6022 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
6024 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
6026 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
6027 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
6030 switch (SetCCOpcode) {
6032 case ISD::SETNE: Invert = true;
6033 case ISD::SETEQ: Opc = EQOpc; break;
6034 case ISD::SETLT: Swap = true;
6035 case ISD::SETGT: Opc = GTOpc; break;
6036 case ISD::SETGE: Swap = true;
6037 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
6038 case ISD::SETULT: Swap = true;
6039 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
6040 case ISD::SETUGE: Swap = true;
6041 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
6044 std::swap(Op0, Op1);
6046 // Since SSE has no unsigned integer comparisons, we need to flip the sign
6047 // bits of the inputs before performing those operations.
6049 EVT EltVT = VT.getVectorElementType();
6050 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
6052 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
6053 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
6055 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
6056 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
6059 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
6061 // If the logical-not of the result is required, perform that now.
6063 Result = DAG.getNOT(dl, Result, VT);
6068 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
6069 static bool isX86LogicalCmp(SDValue Op) {
6070 unsigned Opc = Op.getNode()->getOpcode();
6071 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
6073 if (Op.getResNo() == 1 &&
6074 (Opc == X86ISD::ADD ||
6075 Opc == X86ISD::SUB ||
6076 Opc == X86ISD::SMUL ||
6077 Opc == X86ISD::UMUL ||
6078 Opc == X86ISD::INC ||
6079 Opc == X86ISD::DEC ||
6080 Opc == X86ISD::OR ||
6081 Opc == X86ISD::XOR ||
6082 Opc == X86ISD::AND))
6088 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
6089 bool addTest = true;
6090 SDValue Cond = Op.getOperand(0);
6091 DebugLoc dl = Op.getDebugLoc();
6094 if (Cond.getOpcode() == ISD::SETCC) {
6095 SDValue NewCond = LowerSETCC(Cond, DAG);
6096 if (NewCond.getNode())
6100 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
6101 SDValue Op1 = Op.getOperand(1);
6102 SDValue Op2 = Op.getOperand(2);
6103 if (Cond.getOpcode() == X86ISD::SETCC &&
6104 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
6105 SDValue Cmp = Cond.getOperand(1);
6106 if (Cmp.getOpcode() == X86ISD::CMP) {
6107 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
6108 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
6109 ConstantSDNode *RHSC =
6110 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
6111 if (N1C && N1C->isAllOnesValue() &&
6112 N2C && N2C->isNullValue() &&
6113 RHSC && RHSC->isNullValue()) {
6114 SDValue CmpOp0 = Cmp.getOperand(0);
6115 Cmp = DAG.getNode(X86ISD::CMP, dl, CmpOp0.getValueType(),
6116 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
6117 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
6118 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
6123 // Look pass (and (setcc_carry (cmp ...)), 1).
6124 if (Cond.getOpcode() == ISD::AND &&
6125 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6126 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6127 if (C && C->getAPIntValue() == 1)
6128 Cond = Cond.getOperand(0);
6131 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6132 // setting operand in place of the X86ISD::SETCC.
6133 if (Cond.getOpcode() == X86ISD::SETCC ||
6134 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6135 CC = Cond.getOperand(0);
6137 SDValue Cmp = Cond.getOperand(1);
6138 unsigned Opc = Cmp.getOpcode();
6139 EVT VT = Op.getValueType();
6141 bool IllegalFPCMov = false;
6142 if (VT.isFloatingPoint() && !VT.isVector() &&
6143 !isScalarFPTypeInSSEReg(VT)) // FPStack?
6144 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
6146 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
6147 Opc == X86ISD::BT) { // FIXME
6154 // Look pass the truncate.
6155 if (Cond.getOpcode() == ISD::TRUNCATE)
6156 Cond = Cond.getOperand(0);
6158 // We know the result of AND is compared against zero. Try to match
6160 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6161 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6162 if (NewSetCC.getNode()) {
6163 CC = NewSetCC.getOperand(0);
6164 Cond = NewSetCC.getOperand(1);
6171 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6172 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6175 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
6176 // condition is true.
6177 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
6178 SDValue Ops[] = { Op2, Op1, CC, Cond };
6179 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
6182 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
6183 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
6184 // from the AND / OR.
6185 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
6186 Opc = Op.getOpcode();
6187 if (Opc != ISD::OR && Opc != ISD::AND)
6189 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6190 Op.getOperand(0).hasOneUse() &&
6191 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
6192 Op.getOperand(1).hasOneUse());
6195 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
6196 // 1 and that the SETCC node has a single use.
6197 static bool isXor1OfSetCC(SDValue Op) {
6198 if (Op.getOpcode() != ISD::XOR)
6200 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6201 if (N1C && N1C->getAPIntValue() == 1) {
6202 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
6203 Op.getOperand(0).hasOneUse();
6208 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
6209 bool addTest = true;
6210 SDValue Chain = Op.getOperand(0);
6211 SDValue Cond = Op.getOperand(1);
6212 SDValue Dest = Op.getOperand(2);
6213 DebugLoc dl = Op.getDebugLoc();
6216 if (Cond.getOpcode() == ISD::SETCC) {
6217 SDValue NewCond = LowerSETCC(Cond, DAG);
6218 if (NewCond.getNode())
6222 // FIXME: LowerXALUO doesn't handle these!!
6223 else if (Cond.getOpcode() == X86ISD::ADD ||
6224 Cond.getOpcode() == X86ISD::SUB ||
6225 Cond.getOpcode() == X86ISD::SMUL ||
6226 Cond.getOpcode() == X86ISD::UMUL)
6227 Cond = LowerXALUO(Cond, DAG);
6230 // Look pass (and (setcc_carry (cmp ...)), 1).
6231 if (Cond.getOpcode() == ISD::AND &&
6232 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
6233 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
6234 if (C && C->getAPIntValue() == 1)
6235 Cond = Cond.getOperand(0);
6238 // If condition flag is set by a X86ISD::CMP, then use it as the condition
6239 // setting operand in place of the X86ISD::SETCC.
6240 if (Cond.getOpcode() == X86ISD::SETCC ||
6241 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
6242 CC = Cond.getOperand(0);
6244 SDValue Cmp = Cond.getOperand(1);
6245 unsigned Opc = Cmp.getOpcode();
6246 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
6247 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
6251 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
6255 // These can only come from an arithmetic instruction with overflow,
6256 // e.g. SADDO, UADDO.
6257 Cond = Cond.getNode()->getOperand(1);
6264 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
6265 SDValue Cmp = Cond.getOperand(0).getOperand(1);
6266 if (CondOpc == ISD::OR) {
6267 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
6268 // two branches instead of an explicit OR instruction with a
6270 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6271 isX86LogicalCmp(Cmp)) {
6272 CC = Cond.getOperand(0).getOperand(0);
6273 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6274 Chain, Dest, CC, Cmp);
6275 CC = Cond.getOperand(1).getOperand(0);
6279 } else { // ISD::AND
6280 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
6281 // two branches instead of an explicit AND instruction with a
6282 // separate test. However, we only do this if this block doesn't
6283 // have a fall-through edge, because this requires an explicit
6284 // jmp when the condition is false.
6285 if (Cmp == Cond.getOperand(1).getOperand(1) &&
6286 isX86LogicalCmp(Cmp) &&
6287 Op.getNode()->hasOneUse()) {
6288 X86::CondCode CCode =
6289 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6290 CCode = X86::GetOppositeBranchCondition(CCode);
6291 CC = DAG.getConstant(CCode, MVT::i8);
6292 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
6293 // Look for an unconditional branch following this conditional branch.
6294 // We need this because we need to reverse the successors in order
6295 // to implement FCMP_OEQ.
6296 if (User.getOpcode() == ISD::BR) {
6297 SDValue FalseBB = User.getOperand(1);
6299 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
6300 assert(NewBR == User);
6303 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6304 Chain, Dest, CC, Cmp);
6305 X86::CondCode CCode =
6306 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
6307 CCode = X86::GetOppositeBranchCondition(CCode);
6308 CC = DAG.getConstant(CCode, MVT::i8);
6314 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
6315 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
6316 // It should be transformed during dag combiner except when the condition
6317 // is set by a arithmetics with overflow node.
6318 X86::CondCode CCode =
6319 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
6320 CCode = X86::GetOppositeBranchCondition(CCode);
6321 CC = DAG.getConstant(CCode, MVT::i8);
6322 Cond = Cond.getOperand(0).getOperand(1);
6328 // Look pass the truncate.
6329 if (Cond.getOpcode() == ISD::TRUNCATE)
6330 Cond = Cond.getOperand(0);
6332 // We know the result of AND is compared against zero. Try to match
6334 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
6335 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
6336 if (NewSetCC.getNode()) {
6337 CC = NewSetCC.getOperand(0);
6338 Cond = NewSetCC.getOperand(1);
6345 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6346 Cond = EmitTest(Cond, X86::COND_NE, DAG);
6348 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
6349 Chain, Dest, CC, Cond);
6353 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
6354 // Calls to _alloca is needed to probe the stack when allocating more than 4k
6355 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
6356 // that the guard pages used by the OS virtual memory manager are allocated in
6357 // correct sequence.
6359 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
6360 SelectionDAG &DAG) {
6361 assert(Subtarget->isTargetCygMing() &&
6362 "This should be used only on Cygwin/Mingw targets");
6363 DebugLoc dl = Op.getDebugLoc();
6366 SDValue Chain = Op.getOperand(0);
6367 SDValue Size = Op.getOperand(1);
6368 // FIXME: Ensure alignment here
6372 EVT IntPtr = getPointerTy();
6373 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
6375 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
6377 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6378 Flag = Chain.getValue(1);
6380 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6381 SDValue Ops[] = { Chain,
6382 DAG.getTargetExternalSymbol("_alloca", IntPtr),
6383 DAG.getRegister(X86::EAX, IntPtr),
6384 DAG.getRegister(X86StackPtr, SPTy),
6386 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
6387 Flag = Chain.getValue(1);
6389 Chain = DAG.getCALLSEQ_END(Chain,
6390 DAG.getIntPtrConstant(0, true),
6391 DAG.getIntPtrConstant(0, true),
6394 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6396 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6397 return DAG.getMergeValues(Ops1, 2, dl);
6401 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
6403 SDValue Dst, SDValue Src,
6404 SDValue Size, unsigned Align,
6406 uint64_t DstSVOff) {
6407 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6409 // If not DWORD aligned or size is more than the threshold, call the library.
6410 // The libc version is likely to be faster for these cases. It can use the
6411 // address value and run time information about the CPU.
6412 if ((Align & 3) != 0 ||
6414 ConstantSize->getZExtValue() >
6415 getSubtarget()->getMaxInlineSizeThreshold()) {
6416 SDValue InFlag(0, 0);
6418 // Check to see if there is a specialized entry-point for memory zeroing.
6419 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6421 if (const char *bzeroEntry = V &&
6422 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6423 EVT IntPtr = getPointerTy();
6424 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6425 TargetLowering::ArgListTy Args;
6426 TargetLowering::ArgListEntry Entry;
6428 Entry.Ty = IntPtrTy;
6429 Args.push_back(Entry);
6431 Args.push_back(Entry);
6432 std::pair<SDValue,SDValue> CallResult =
6433 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6434 false, false, false, false,
6435 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6436 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl,
6437 DAG.GetOrdering(Chain.getNode()));
6438 return CallResult.second;
6441 // Otherwise have the target-independent code call memset.
6445 uint64_t SizeVal = ConstantSize->getZExtValue();
6446 SDValue InFlag(0, 0);
6449 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6450 unsigned BytesLeft = 0;
6451 bool TwoRepStos = false;
6454 uint64_t Val = ValC->getZExtValue() & 255;
6456 // If the value is a constant, then we can potentially use larger sets.
6457 switch (Align & 3) {
6458 case 2: // WORD aligned
6461 Val = (Val << 8) | Val;
6463 case 0: // DWORD aligned
6466 Val = (Val << 8) | Val;
6467 Val = (Val << 16) | Val;
6468 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
6471 Val = (Val << 32) | Val;
6474 default: // Byte aligned
6477 Count = DAG.getIntPtrConstant(SizeVal);
6481 if (AVT.bitsGT(MVT::i8)) {
6482 unsigned UBytes = AVT.getSizeInBits() / 8;
6483 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6484 BytesLeft = SizeVal % UBytes;
6487 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6489 InFlag = Chain.getValue(1);
6492 Count = DAG.getIntPtrConstant(SizeVal);
6493 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6494 InFlag = Chain.getValue(1);
6497 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6500 InFlag = Chain.getValue(1);
6501 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6504 InFlag = Chain.getValue(1);
6506 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6507 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6508 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6511 InFlag = Chain.getValue(1);
6513 EVT CVT = Count.getValueType();
6514 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6515 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6516 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6519 InFlag = Chain.getValue(1);
6520 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6521 SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
6522 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops, array_lengthof(Ops));
6523 } else if (BytesLeft) {
6524 // Handle the last 1 - 7 bytes.
6525 unsigned Offset = SizeVal - BytesLeft;
6526 EVT AddrVT = Dst.getValueType();
6527 EVT SizeVT = Size.getValueType();
6529 Chain = DAG.getMemset(Chain, dl,
6530 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6531 DAG.getConstant(Offset, AddrVT)),
6533 DAG.getConstant(BytesLeft, SizeVT),
6534 Align, DstSV, DstSVOff + Offset);
6537 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6542 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6543 SDValue Chain, SDValue Dst, SDValue Src,
6544 SDValue Size, unsigned Align,
6546 const Value *DstSV, uint64_t DstSVOff,
6547 const Value *SrcSV, uint64_t SrcSVOff) {
6548 // This requires the copy size to be a constant, preferrably
6549 // within a subtarget-specific limit.
6550 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6553 uint64_t SizeVal = ConstantSize->getZExtValue();
6554 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6557 /// If not DWORD aligned, call the library.
6558 if ((Align & 3) != 0)
6563 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6566 unsigned UBytes = AVT.getSizeInBits() / 8;
6567 unsigned CountVal = SizeVal / UBytes;
6568 SDValue Count = DAG.getIntPtrConstant(CountVal);
6569 unsigned BytesLeft = SizeVal % UBytes;
6571 SDValue InFlag(0, 0);
6572 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6575 InFlag = Chain.getValue(1);
6576 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6579 InFlag = Chain.getValue(1);
6580 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6583 InFlag = Chain.getValue(1);
6585 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6586 SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
6587 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops,
6588 array_lengthof(Ops));
6590 SmallVector<SDValue, 4> Results;
6591 Results.push_back(RepMovs);
6593 // Handle the last 1 - 7 bytes.
6594 unsigned Offset = SizeVal - BytesLeft;
6595 EVT DstVT = Dst.getValueType();
6596 EVT SrcVT = Src.getValueType();
6597 EVT SizeVT = Size.getValueType();
6598 Results.push_back(DAG.getMemcpy(Chain, dl,
6599 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6600 DAG.getConstant(Offset, DstVT)),
6601 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6602 DAG.getConstant(Offset, SrcVT)),
6603 DAG.getConstant(BytesLeft, SizeVT),
6604 Align, AlwaysInline,
6605 DstSV, DstSVOff + Offset,
6606 SrcSV, SrcSVOff + Offset));
6609 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6610 &Results[0], Results.size());
6613 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6614 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6615 DebugLoc dl = Op.getDebugLoc();
6617 if (!Subtarget->is64Bit()) {
6618 // vastart just stores the address of the VarArgsFrameIndex slot into the
6619 // memory location argument.
6620 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6621 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6625 // gp_offset (0 - 6 * 8)
6626 // fp_offset (48 - 48 + 8 * 16)
6627 // overflow_arg_area (point to parameters coming in memory).
6629 SmallVector<SDValue, 8> MemOps;
6630 SDValue FIN = Op.getOperand(1);
6632 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6633 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6635 MemOps.push_back(Store);
6638 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6639 FIN, DAG.getIntPtrConstant(4));
6640 Store = DAG.getStore(Op.getOperand(0), dl,
6641 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6643 MemOps.push_back(Store);
6645 // Store ptr to overflow_arg_area
6646 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6647 FIN, DAG.getIntPtrConstant(4));
6648 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6649 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6650 MemOps.push_back(Store);
6652 // Store ptr to reg_save_area.
6653 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6654 FIN, DAG.getIntPtrConstant(8));
6655 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6656 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6657 MemOps.push_back(Store);
6658 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6659 &MemOps[0], MemOps.size());
6662 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6663 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6664 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6665 SDValue Chain = Op.getOperand(0);
6666 SDValue SrcPtr = Op.getOperand(1);
6667 SDValue SrcSV = Op.getOperand(2);
6669 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6673 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6674 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6675 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6676 SDValue Chain = Op.getOperand(0);
6677 SDValue DstPtr = Op.getOperand(1);
6678 SDValue SrcPtr = Op.getOperand(2);
6679 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6680 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6681 DebugLoc dl = Op.getDebugLoc();
6683 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6684 DAG.getIntPtrConstant(24), 8, false,
6685 DstSV, 0, SrcSV, 0);
6689 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6690 DebugLoc dl = Op.getDebugLoc();
6691 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6693 default: return SDValue(); // Don't custom lower most intrinsics.
6694 // Comparison intrinsics.
6695 case Intrinsic::x86_sse_comieq_ss:
6696 case Intrinsic::x86_sse_comilt_ss:
6697 case Intrinsic::x86_sse_comile_ss:
6698 case Intrinsic::x86_sse_comigt_ss:
6699 case Intrinsic::x86_sse_comige_ss:
6700 case Intrinsic::x86_sse_comineq_ss:
6701 case Intrinsic::x86_sse_ucomieq_ss:
6702 case Intrinsic::x86_sse_ucomilt_ss:
6703 case Intrinsic::x86_sse_ucomile_ss:
6704 case Intrinsic::x86_sse_ucomigt_ss:
6705 case Intrinsic::x86_sse_ucomige_ss:
6706 case Intrinsic::x86_sse_ucomineq_ss:
6707 case Intrinsic::x86_sse2_comieq_sd:
6708 case Intrinsic::x86_sse2_comilt_sd:
6709 case Intrinsic::x86_sse2_comile_sd:
6710 case Intrinsic::x86_sse2_comigt_sd:
6711 case Intrinsic::x86_sse2_comige_sd:
6712 case Intrinsic::x86_sse2_comineq_sd:
6713 case Intrinsic::x86_sse2_ucomieq_sd:
6714 case Intrinsic::x86_sse2_ucomilt_sd:
6715 case Intrinsic::x86_sse2_ucomile_sd:
6716 case Intrinsic::x86_sse2_ucomigt_sd:
6717 case Intrinsic::x86_sse2_ucomige_sd:
6718 case Intrinsic::x86_sse2_ucomineq_sd: {
6720 ISD::CondCode CC = ISD::SETCC_INVALID;
6723 case Intrinsic::x86_sse_comieq_ss:
6724 case Intrinsic::x86_sse2_comieq_sd:
6728 case Intrinsic::x86_sse_comilt_ss:
6729 case Intrinsic::x86_sse2_comilt_sd:
6733 case Intrinsic::x86_sse_comile_ss:
6734 case Intrinsic::x86_sse2_comile_sd:
6738 case Intrinsic::x86_sse_comigt_ss:
6739 case Intrinsic::x86_sse2_comigt_sd:
6743 case Intrinsic::x86_sse_comige_ss:
6744 case Intrinsic::x86_sse2_comige_sd:
6748 case Intrinsic::x86_sse_comineq_ss:
6749 case Intrinsic::x86_sse2_comineq_sd:
6753 case Intrinsic::x86_sse_ucomieq_ss:
6754 case Intrinsic::x86_sse2_ucomieq_sd:
6755 Opc = X86ISD::UCOMI;
6758 case Intrinsic::x86_sse_ucomilt_ss:
6759 case Intrinsic::x86_sse2_ucomilt_sd:
6760 Opc = X86ISD::UCOMI;
6763 case Intrinsic::x86_sse_ucomile_ss:
6764 case Intrinsic::x86_sse2_ucomile_sd:
6765 Opc = X86ISD::UCOMI;
6768 case Intrinsic::x86_sse_ucomigt_ss:
6769 case Intrinsic::x86_sse2_ucomigt_sd:
6770 Opc = X86ISD::UCOMI;
6773 case Intrinsic::x86_sse_ucomige_ss:
6774 case Intrinsic::x86_sse2_ucomige_sd:
6775 Opc = X86ISD::UCOMI;
6778 case Intrinsic::x86_sse_ucomineq_ss:
6779 case Intrinsic::x86_sse2_ucomineq_sd:
6780 Opc = X86ISD::UCOMI;
6785 SDValue LHS = Op.getOperand(1);
6786 SDValue RHS = Op.getOperand(2);
6787 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6788 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6789 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6790 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6791 DAG.getConstant(X86CC, MVT::i8), Cond);
6792 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6794 // ptest intrinsics. The intrinsic these come from are designed to return
6795 // an integer value, not just an instruction so lower it to the ptest
6796 // pattern and a setcc for the result.
6797 case Intrinsic::x86_sse41_ptestz:
6798 case Intrinsic::x86_sse41_ptestc:
6799 case Intrinsic::x86_sse41_ptestnzc:{
6802 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6803 case Intrinsic::x86_sse41_ptestz:
6805 X86CC = X86::COND_E;
6807 case Intrinsic::x86_sse41_ptestc:
6809 X86CC = X86::COND_B;
6811 case Intrinsic::x86_sse41_ptestnzc:
6813 X86CC = X86::COND_A;
6817 SDValue LHS = Op.getOperand(1);
6818 SDValue RHS = Op.getOperand(2);
6819 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6820 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6821 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6822 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6825 // Fix vector shift instructions where the last operand is a non-immediate
6827 case Intrinsic::x86_sse2_pslli_w:
6828 case Intrinsic::x86_sse2_pslli_d:
6829 case Intrinsic::x86_sse2_pslli_q:
6830 case Intrinsic::x86_sse2_psrli_w:
6831 case Intrinsic::x86_sse2_psrli_d:
6832 case Intrinsic::x86_sse2_psrli_q:
6833 case Intrinsic::x86_sse2_psrai_w:
6834 case Intrinsic::x86_sse2_psrai_d:
6835 case Intrinsic::x86_mmx_pslli_w:
6836 case Intrinsic::x86_mmx_pslli_d:
6837 case Intrinsic::x86_mmx_pslli_q:
6838 case Intrinsic::x86_mmx_psrli_w:
6839 case Intrinsic::x86_mmx_psrli_d:
6840 case Intrinsic::x86_mmx_psrli_q:
6841 case Intrinsic::x86_mmx_psrai_w:
6842 case Intrinsic::x86_mmx_psrai_d: {
6843 SDValue ShAmt = Op.getOperand(2);
6844 if (isa<ConstantSDNode>(ShAmt))
6847 unsigned NewIntNo = 0;
6848 EVT ShAmtVT = MVT::v4i32;
6850 case Intrinsic::x86_sse2_pslli_w:
6851 NewIntNo = Intrinsic::x86_sse2_psll_w;
6853 case Intrinsic::x86_sse2_pslli_d:
6854 NewIntNo = Intrinsic::x86_sse2_psll_d;
6856 case Intrinsic::x86_sse2_pslli_q:
6857 NewIntNo = Intrinsic::x86_sse2_psll_q;
6859 case Intrinsic::x86_sse2_psrli_w:
6860 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6862 case Intrinsic::x86_sse2_psrli_d:
6863 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6865 case Intrinsic::x86_sse2_psrli_q:
6866 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6868 case Intrinsic::x86_sse2_psrai_w:
6869 NewIntNo = Intrinsic::x86_sse2_psra_w;
6871 case Intrinsic::x86_sse2_psrai_d:
6872 NewIntNo = Intrinsic::x86_sse2_psra_d;
6875 ShAmtVT = MVT::v2i32;
6877 case Intrinsic::x86_mmx_pslli_w:
6878 NewIntNo = Intrinsic::x86_mmx_psll_w;
6880 case Intrinsic::x86_mmx_pslli_d:
6881 NewIntNo = Intrinsic::x86_mmx_psll_d;
6883 case Intrinsic::x86_mmx_pslli_q:
6884 NewIntNo = Intrinsic::x86_mmx_psll_q;
6886 case Intrinsic::x86_mmx_psrli_w:
6887 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6889 case Intrinsic::x86_mmx_psrli_d:
6890 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6892 case Intrinsic::x86_mmx_psrli_q:
6893 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6895 case Intrinsic::x86_mmx_psrai_w:
6896 NewIntNo = Intrinsic::x86_mmx_psra_w;
6898 case Intrinsic::x86_mmx_psrai_d:
6899 NewIntNo = Intrinsic::x86_mmx_psra_d;
6901 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6907 // The vector shift intrinsics with scalars uses 32b shift amounts but
6908 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6912 ShOps[1] = DAG.getConstant(0, MVT::i32);
6913 if (ShAmtVT == MVT::v4i32) {
6914 ShOps[2] = DAG.getUNDEF(MVT::i32);
6915 ShOps[3] = DAG.getUNDEF(MVT::i32);
6916 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6918 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6921 EVT VT = Op.getValueType();
6922 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6923 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6924 DAG.getConstant(NewIntNo, MVT::i32),
6925 Op.getOperand(1), ShAmt);
6930 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6931 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6932 DebugLoc dl = Op.getDebugLoc();
6935 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6937 DAG.getConstant(TD->getPointerSize(),
6938 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6939 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6940 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6945 // Just load the return address.
6946 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6947 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6948 RetAddrFI, NULL, 0);
6951 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6952 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6953 MFI->setFrameAddressIsTaken(true);
6954 EVT VT = Op.getValueType();
6955 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6956 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6957 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6958 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6960 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6964 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6965 SelectionDAG &DAG) {
6966 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6969 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6971 MachineFunction &MF = DAG.getMachineFunction();
6972 SDValue Chain = Op.getOperand(0);
6973 SDValue Offset = Op.getOperand(1);
6974 SDValue Handler = Op.getOperand(2);
6975 DebugLoc dl = Op.getDebugLoc();
6977 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6979 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6981 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6982 DAG.getIntPtrConstant(-TD->getPointerSize()));
6983 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6984 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6985 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6986 MF.getRegInfo().addLiveOut(StoreAddrReg);
6988 return DAG.getNode(X86ISD::EH_RETURN, dl,
6990 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6993 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6994 SelectionDAG &DAG) {
6995 SDValue Root = Op.getOperand(0);
6996 SDValue Trmp = Op.getOperand(1); // trampoline
6997 SDValue FPtr = Op.getOperand(2); // nested function
6998 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6999 DebugLoc dl = Op.getDebugLoc();
7001 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7003 if (Subtarget->is64Bit()) {
7004 SDValue OutChains[6];
7006 // Large code-model.
7007 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7008 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7010 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7011 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7013 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7015 // Load the pointer to the nested function into R11.
7016 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7017 SDValue Addr = Trmp;
7018 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7021 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7022 DAG.getConstant(2, MVT::i64));
7023 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
7025 // Load the 'nest' parameter value into R10.
7026 // R10 is specified in X86CallingConv.td
7027 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7028 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7029 DAG.getConstant(10, MVT::i64));
7030 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7031 Addr, TrmpAddr, 10);
7033 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7034 DAG.getConstant(12, MVT::i64));
7035 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
7037 // Jump to the nested function.
7038 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7039 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7040 DAG.getConstant(20, MVT::i64));
7041 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7042 Addr, TrmpAddr, 20);
7044 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7045 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7046 DAG.getConstant(22, MVT::i64));
7047 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7051 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7052 return DAG.getMergeValues(Ops, 2, dl);
7054 const Function *Func =
7055 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7056 CallingConv::ID CC = Func->getCallingConv();
7061 llvm_unreachable("Unsupported calling convention");
7062 case CallingConv::C:
7063 case CallingConv::X86_StdCall: {
7064 // Pass 'nest' parameter in ECX.
7065 // Must be kept in sync with X86CallingConv.td
7068 // Check that ECX wasn't needed by an 'inreg' parameter.
7069 const FunctionType *FTy = Func->getFunctionType();
7070 const AttrListPtr &Attrs = Func->getAttributes();
7072 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7073 unsigned InRegCount = 0;
7076 for (FunctionType::param_iterator I = FTy->param_begin(),
7077 E = FTy->param_end(); I != E; ++I, ++Idx)
7078 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7079 // FIXME: should only count parameters that are lowered to integers.
7080 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7082 if (InRegCount > 2) {
7083 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
7088 case CallingConv::X86_FastCall:
7089 case CallingConv::Fast:
7090 // Pass 'nest' parameter in EAX.
7091 // Must be kept in sync with X86CallingConv.td
7096 SDValue OutChains[4];
7099 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7100 DAG.getConstant(10, MVT::i32));
7101 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7103 // This is storing the opcode for MOV32ri.
7104 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7105 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7106 OutChains[0] = DAG.getStore(Root, dl,
7107 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7110 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7111 DAG.getConstant(1, MVT::i32));
7112 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
7114 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7115 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7116 DAG.getConstant(5, MVT::i32));
7117 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7118 TrmpAddr, 5, false, 1);
7120 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7121 DAG.getConstant(6, MVT::i32));
7122 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
7125 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7126 return DAG.getMergeValues(Ops, 2, dl);
7130 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
7132 The rounding mode is in bits 11:10 of FPSR, and has the following
7139 FLT_ROUNDS, on the other hand, expects the following:
7146 To perform the conversion, we do:
7147 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7150 MachineFunction &MF = DAG.getMachineFunction();
7151 const TargetMachine &TM = MF.getTarget();
7152 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7153 unsigned StackAlignment = TFI.getStackAlignment();
7154 EVT VT = Op.getValueType();
7155 DebugLoc dl = Op.getDebugLoc();
7157 // Save FP Control Word to stack slot
7158 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7159 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7161 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7162 DAG.getEntryNode(), StackSlot);
7164 // Load FP Control Word from stack slot
7165 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
7167 // Transform as necessary
7169 DAG.getNode(ISD::SRL, dl, MVT::i16,
7170 DAG.getNode(ISD::AND, dl, MVT::i16,
7171 CWD, DAG.getConstant(0x800, MVT::i16)),
7172 DAG.getConstant(11, MVT::i8));
7174 DAG.getNode(ISD::SRL, dl, MVT::i16,
7175 DAG.getNode(ISD::AND, dl, MVT::i16,
7176 CWD, DAG.getConstant(0x400, MVT::i16)),
7177 DAG.getConstant(9, MVT::i8));
7180 DAG.getNode(ISD::AND, dl, MVT::i16,
7181 DAG.getNode(ISD::ADD, dl, MVT::i16,
7182 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
7183 DAG.getConstant(1, MVT::i16)),
7184 DAG.getConstant(3, MVT::i16));
7187 return DAG.getNode((VT.getSizeInBits() < 16 ?
7188 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
7191 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
7192 EVT VT = Op.getValueType();
7194 unsigned NumBits = VT.getSizeInBits();
7195 DebugLoc dl = Op.getDebugLoc();
7197 Op = Op.getOperand(0);
7198 if (VT == MVT::i8) {
7199 // Zero extend to i32 since there is not an i8 bsr.
7201 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7204 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
7205 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7206 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
7208 // If src is zero (i.e. bsr sets ZF), returns NumBits.
7211 DAG.getConstant(NumBits+NumBits-1, OpVT),
7212 DAG.getConstant(X86::COND_E, MVT::i8),
7215 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7217 // Finally xor with NumBits-1.
7218 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
7221 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7225 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
7226 EVT VT = Op.getValueType();
7228 unsigned NumBits = VT.getSizeInBits();
7229 DebugLoc dl = Op.getDebugLoc();
7231 Op = Op.getOperand(0);
7232 if (VT == MVT::i8) {
7234 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
7237 // Issue a bsf (scan bits forward) which also sets EFLAGS.
7238 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
7239 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
7241 // If src is zero (i.e. bsf sets ZF), returns NumBits.
7244 DAG.getConstant(NumBits, OpVT),
7245 DAG.getConstant(X86::COND_E, MVT::i8),
7248 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
7251 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
7255 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
7256 EVT VT = Op.getValueType();
7257 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
7258 DebugLoc dl = Op.getDebugLoc();
7260 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
7261 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
7262 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
7263 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
7264 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
7266 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
7267 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
7268 // return AloBlo + AloBhi + AhiBlo;
7270 SDValue A = Op.getOperand(0);
7271 SDValue B = Op.getOperand(1);
7273 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7274 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7275 A, DAG.getConstant(32, MVT::i32));
7276 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7277 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7278 B, DAG.getConstant(32, MVT::i32));
7279 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7280 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7282 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7283 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7285 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7286 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
7288 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7289 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7290 AloBhi, DAG.getConstant(32, MVT::i32));
7291 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7292 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7293 AhiBlo, DAG.getConstant(32, MVT::i32));
7294 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
7295 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
7300 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
7301 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
7302 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
7303 // looks for this combo and may remove the "setcc" instruction if the "setcc"
7304 // has only one use.
7305 SDNode *N = Op.getNode();
7306 SDValue LHS = N->getOperand(0);
7307 SDValue RHS = N->getOperand(1);
7308 unsigned BaseOp = 0;
7310 DebugLoc dl = Op.getDebugLoc();
7312 switch (Op.getOpcode()) {
7313 default: llvm_unreachable("Unknown ovf instruction!");
7315 // A subtract of one will be selected as a INC. Note that INC doesn't
7316 // set CF, so we can't do this for UADDO.
7317 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7318 if (C->getAPIntValue() == 1) {
7319 BaseOp = X86ISD::INC;
7323 BaseOp = X86ISD::ADD;
7327 BaseOp = X86ISD::ADD;
7331 // A subtract of one will be selected as a DEC. Note that DEC doesn't
7332 // set CF, so we can't do this for USUBO.
7333 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
7334 if (C->getAPIntValue() == 1) {
7335 BaseOp = X86ISD::DEC;
7339 BaseOp = X86ISD::SUB;
7343 BaseOp = X86ISD::SUB;
7347 BaseOp = X86ISD::SMUL;
7351 BaseOp = X86ISD::UMUL;
7356 // Also sets EFLAGS.
7357 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
7358 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
7361 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
7362 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
7364 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
7368 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
7369 EVT T = Op.getValueType();
7370 DebugLoc dl = Op.getDebugLoc();
7373 switch(T.getSimpleVT().SimpleTy) {
7375 assert(false && "Invalid value type!");
7376 case MVT::i8: Reg = X86::AL; size = 1; break;
7377 case MVT::i16: Reg = X86::AX; size = 2; break;
7378 case MVT::i32: Reg = X86::EAX; size = 4; break;
7380 assert(Subtarget->is64Bit() && "Node not type legal!");
7381 Reg = X86::RAX; size = 8;
7384 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7385 Op.getOperand(2), SDValue());
7386 SDValue Ops[] = { cpIn.getValue(0),
7389 DAG.getTargetConstant(size, MVT::i8),
7391 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7392 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7394 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7398 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7399 SelectionDAG &DAG) {
7400 assert(Subtarget->is64Bit() && "Result not type legalized?");
7401 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7402 SDValue TheChain = Op.getOperand(0);
7403 DebugLoc dl = Op.getDebugLoc();
7404 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7405 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7406 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7408 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7409 DAG.getConstant(32, MVT::i8));
7411 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7414 return DAG.getMergeValues(Ops, 2, dl);
7417 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7418 SDNode *Node = Op.getNode();
7419 DebugLoc dl = Node->getDebugLoc();
7420 EVT T = Node->getValueType(0);
7421 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7422 DAG.getConstant(0, T), Node->getOperand(2));
7423 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7424 cast<AtomicSDNode>(Node)->getMemoryVT(),
7425 Node->getOperand(0),
7426 Node->getOperand(1), negOp,
7427 cast<AtomicSDNode>(Node)->getSrcValue(),
7428 cast<AtomicSDNode>(Node)->getAlignment());
7431 /// LowerOperation - Provide custom lowering hooks for some operations.
7433 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7434 switch (Op.getOpcode()) {
7435 default: llvm_unreachable("Should not custom lower this!");
7436 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7437 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7438 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7439 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7440 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7441 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7442 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7443 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7444 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7445 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7446 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7447 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7448 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7449 case ISD::SHL_PARTS:
7450 case ISD::SRA_PARTS:
7451 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7452 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7453 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7454 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7455 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7456 case ISD::FABS: return LowerFABS(Op, DAG);
7457 case ISD::FNEG: return LowerFNEG(Op, DAG);
7458 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7459 case ISD::SETCC: return LowerSETCC(Op, DAG);
7460 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7461 case ISD::SELECT: return LowerSELECT(Op, DAG);
7462 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7463 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7464 case ISD::VASTART: return LowerVASTART(Op, DAG);
7465 case ISD::VAARG: return LowerVAARG(Op, DAG);
7466 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7467 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7468 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7469 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7470 case ISD::FRAME_TO_ARGS_OFFSET:
7471 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7472 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7473 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7474 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7475 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7476 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7477 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7478 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7484 case ISD::UMULO: return LowerXALUO(Op, DAG);
7485 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7489 void X86TargetLowering::
7490 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7491 SelectionDAG &DAG, unsigned NewOp) {
7492 EVT T = Node->getValueType(0);
7493 DebugLoc dl = Node->getDebugLoc();
7494 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7496 SDValue Chain = Node->getOperand(0);
7497 SDValue In1 = Node->getOperand(1);
7498 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7499 Node->getOperand(2), DAG.getIntPtrConstant(0));
7500 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7501 Node->getOperand(2), DAG.getIntPtrConstant(1));
7502 SDValue Ops[] = { Chain, In1, In2L, In2H };
7503 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7505 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7506 cast<MemSDNode>(Node)->getMemOperand());
7507 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7508 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7509 Results.push_back(Result.getValue(2));
7512 /// ReplaceNodeResults - Replace a node with an illegal result type
7513 /// with a new node built out of custom code.
7514 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7515 SmallVectorImpl<SDValue>&Results,
7516 SelectionDAG &DAG) {
7517 DebugLoc dl = N->getDebugLoc();
7518 switch (N->getOpcode()) {
7520 assert(false && "Do not know how to custom type legalize this operation!");
7522 case ISD::FP_TO_SINT: {
7523 std::pair<SDValue,SDValue> Vals =
7524 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7525 SDValue FIST = Vals.first, StackSlot = Vals.second;
7526 if (FIST.getNode() != 0) {
7527 EVT VT = N->getValueType(0);
7528 // Return a load from the stack slot.
7529 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
7533 case ISD::READCYCLECOUNTER: {
7534 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7535 SDValue TheChain = N->getOperand(0);
7536 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7537 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7539 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7541 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7542 SDValue Ops[] = { eax, edx };
7543 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7544 Results.push_back(edx.getValue(1));
7547 case ISD::ATOMIC_CMP_SWAP: {
7548 EVT T = N->getValueType(0);
7549 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7550 SDValue cpInL, cpInH;
7551 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7552 DAG.getConstant(0, MVT::i32));
7553 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7554 DAG.getConstant(1, MVT::i32));
7555 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7556 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7558 SDValue swapInL, swapInH;
7559 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7560 DAG.getConstant(0, MVT::i32));
7561 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7562 DAG.getConstant(1, MVT::i32));
7563 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7565 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7566 swapInL.getValue(1));
7567 SDValue Ops[] = { swapInH.getValue(0),
7569 swapInH.getValue(1) };
7570 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7571 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7572 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7573 MVT::i32, Result.getValue(1));
7574 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7575 MVT::i32, cpOutL.getValue(2));
7576 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7577 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7578 Results.push_back(cpOutH.getValue(1));
7581 case ISD::ATOMIC_LOAD_ADD:
7582 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7584 case ISD::ATOMIC_LOAD_AND:
7585 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7587 case ISD::ATOMIC_LOAD_NAND:
7588 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7590 case ISD::ATOMIC_LOAD_OR:
7591 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7593 case ISD::ATOMIC_LOAD_SUB:
7594 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7596 case ISD::ATOMIC_LOAD_XOR:
7597 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7599 case ISD::ATOMIC_SWAP:
7600 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7605 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7607 default: return NULL;
7608 case X86ISD::BSF: return "X86ISD::BSF";
7609 case X86ISD::BSR: return "X86ISD::BSR";
7610 case X86ISD::SHLD: return "X86ISD::SHLD";
7611 case X86ISD::SHRD: return "X86ISD::SHRD";
7612 case X86ISD::FAND: return "X86ISD::FAND";
7613 case X86ISD::FOR: return "X86ISD::FOR";
7614 case X86ISD::FXOR: return "X86ISD::FXOR";
7615 case X86ISD::FSRL: return "X86ISD::FSRL";
7616 case X86ISD::FILD: return "X86ISD::FILD";
7617 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7618 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7619 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7620 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7621 case X86ISD::FLD: return "X86ISD::FLD";
7622 case X86ISD::FST: return "X86ISD::FST";
7623 case X86ISD::CALL: return "X86ISD::CALL";
7624 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7625 case X86ISD::BT: return "X86ISD::BT";
7626 case X86ISD::CMP: return "X86ISD::CMP";
7627 case X86ISD::COMI: return "X86ISD::COMI";
7628 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7629 case X86ISD::SETCC: return "X86ISD::SETCC";
7630 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
7631 case X86ISD::CMOV: return "X86ISD::CMOV";
7632 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7633 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7634 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7635 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7636 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7637 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7638 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7639 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7640 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7641 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7642 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7643 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7644 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7645 case X86ISD::FMAX: return "X86ISD::FMAX";
7646 case X86ISD::FMIN: return "X86ISD::FMIN";
7647 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7648 case X86ISD::FRCP: return "X86ISD::FRCP";
7649 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7650 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7651 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7652 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7653 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7654 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7655 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7656 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7657 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7658 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7659 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7660 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7661 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7662 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7663 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7664 case X86ISD::VSHL: return "X86ISD::VSHL";
7665 case X86ISD::VSRL: return "X86ISD::VSRL";
7666 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7667 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7668 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7669 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7670 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7671 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7672 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7673 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7674 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7675 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7676 case X86ISD::ADD: return "X86ISD::ADD";
7677 case X86ISD::SUB: return "X86ISD::SUB";
7678 case X86ISD::SMUL: return "X86ISD::SMUL";
7679 case X86ISD::UMUL: return "X86ISD::UMUL";
7680 case X86ISD::INC: return "X86ISD::INC";
7681 case X86ISD::DEC: return "X86ISD::DEC";
7682 case X86ISD::OR: return "X86ISD::OR";
7683 case X86ISD::XOR: return "X86ISD::XOR";
7684 case X86ISD::AND: return "X86ISD::AND";
7685 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7686 case X86ISD::PTEST: return "X86ISD::PTEST";
7687 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7691 // isLegalAddressingMode - Return true if the addressing mode represented
7692 // by AM is legal for this target, for a load/store of the specified type.
7693 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7694 const Type *Ty) const {
7695 // X86 supports extremely general addressing modes.
7696 CodeModel::Model M = getTargetMachine().getCodeModel();
7698 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7699 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7704 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7706 // If a reference to this global requires an extra load, we can't fold it.
7707 if (isGlobalStubReference(GVFlags))
7710 // If BaseGV requires a register for the PIC base, we cannot also have a
7711 // BaseReg specified.
7712 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7715 // If lower 4G is not available, then we must use rip-relative addressing.
7716 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7726 // These scales always work.
7731 // These scales are formed with basereg+scalereg. Only accept if there is
7736 default: // Other stuff never works.
7744 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7745 if (!Ty1->isInteger() || !Ty2->isInteger())
7747 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7748 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7749 if (NumBits1 <= NumBits2)
7751 return Subtarget->is64Bit() || NumBits1 < 64;
7754 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7755 if (!VT1.isInteger() || !VT2.isInteger())
7757 unsigned NumBits1 = VT1.getSizeInBits();
7758 unsigned NumBits2 = VT2.getSizeInBits();
7759 if (NumBits1 <= NumBits2)
7761 return Subtarget->is64Bit() || NumBits1 < 64;
7764 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7765 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7766 return Ty1->isInteger(32) && Ty2->isInteger(64) && Subtarget->is64Bit();
7769 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7770 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7771 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7774 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7775 // i16 instructions are longer (0x66 prefix) and potentially slower.
7776 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7779 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7780 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7781 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7782 /// are assumed to be legal.
7784 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7786 // Only do shuffles on 128-bit vector types for now.
7787 if (VT.getSizeInBits() == 64)
7790 // FIXME: pshufb, blends, shifts.
7791 return (VT.getVectorNumElements() == 2 ||
7792 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7793 isMOVLMask(M, VT) ||
7794 isSHUFPMask(M, VT) ||
7795 isPSHUFDMask(M, VT) ||
7796 isPSHUFHWMask(M, VT) ||
7797 isPSHUFLWMask(M, VT) ||
7798 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7799 isUNPCKLMask(M, VT) ||
7800 isUNPCKHMask(M, VT) ||
7801 isUNPCKL_v_undef_Mask(M, VT) ||
7802 isUNPCKH_v_undef_Mask(M, VT));
7806 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7808 unsigned NumElts = VT.getVectorNumElements();
7809 // FIXME: This collection of masks seems suspect.
7812 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7813 return (isMOVLMask(Mask, VT) ||
7814 isCommutedMOVLMask(Mask, VT, true) ||
7815 isSHUFPMask(Mask, VT) ||
7816 isCommutedSHUFPMask(Mask, VT));
7821 //===----------------------------------------------------------------------===//
7822 // X86 Scheduler Hooks
7823 //===----------------------------------------------------------------------===//
7825 // private utility function
7827 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7828 MachineBasicBlock *MBB,
7836 TargetRegisterClass *RC,
7837 bool invSrc) const {
7838 // For the atomic bitwise operator, we generate
7841 // ld t1 = [bitinstr.addr]
7842 // op t2 = t1, [bitinstr.val]
7844 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7846 // fallthrough -->nextMBB
7847 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7848 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7849 MachineFunction::iterator MBBIter = MBB;
7852 /// First build the CFG
7853 MachineFunction *F = MBB->getParent();
7854 MachineBasicBlock *thisMBB = MBB;
7855 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7856 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7857 F->insert(MBBIter, newMBB);
7858 F->insert(MBBIter, nextMBB);
7860 // Move all successors to thisMBB to nextMBB
7861 nextMBB->transferSuccessors(thisMBB);
7863 // Update thisMBB to fall through to newMBB
7864 thisMBB->addSuccessor(newMBB);
7866 // newMBB jumps to itself and fall through to nextMBB
7867 newMBB->addSuccessor(nextMBB);
7868 newMBB->addSuccessor(newMBB);
7870 // Insert instructions into newMBB based on incoming instruction
7871 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7872 "unexpected number of operands");
7873 DebugLoc dl = bInstr->getDebugLoc();
7874 MachineOperand& destOper = bInstr->getOperand(0);
7875 MachineOperand* argOpers[2 + X86AddrNumOperands];
7876 int numArgs = bInstr->getNumOperands() - 1;
7877 for (int i=0; i < numArgs; ++i)
7878 argOpers[i] = &bInstr->getOperand(i+1);
7880 // x86 address has 4 operands: base, index, scale, and displacement
7881 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7882 int valArgIndx = lastAddrIndx + 1;
7884 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7885 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7886 for (int i=0; i <= lastAddrIndx; ++i)
7887 (*MIB).addOperand(*argOpers[i]);
7889 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7891 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7896 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7897 assert((argOpers[valArgIndx]->isReg() ||
7898 argOpers[valArgIndx]->isImm()) &&
7900 if (argOpers[valArgIndx]->isReg())
7901 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7903 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7905 (*MIB).addOperand(*argOpers[valArgIndx]);
7907 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7910 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7911 for (int i=0; i <= lastAddrIndx; ++i)
7912 (*MIB).addOperand(*argOpers[i]);
7914 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7915 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7916 bInstr->memoperands_end());
7918 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7922 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
7924 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7928 // private utility function: 64 bit atomics on 32 bit host.
7930 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7931 MachineBasicBlock *MBB,
7936 bool invSrc) const {
7937 // For the atomic bitwise operator, we generate
7938 // thisMBB (instructions are in pairs, except cmpxchg8b)
7939 // ld t1,t2 = [bitinstr.addr]
7941 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7942 // op t5, t6 <- out1, out2, [bitinstr.val]
7943 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7944 // mov ECX, EBX <- t5, t6
7945 // mov EAX, EDX <- t1, t2
7946 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7947 // mov t3, t4 <- EAX, EDX
7949 // result in out1, out2
7950 // fallthrough -->nextMBB
7952 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7953 const unsigned LoadOpc = X86::MOV32rm;
7954 const unsigned copyOpc = X86::MOV32rr;
7955 const unsigned NotOpc = X86::NOT32r;
7956 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7957 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7958 MachineFunction::iterator MBBIter = MBB;
7961 /// First build the CFG
7962 MachineFunction *F = MBB->getParent();
7963 MachineBasicBlock *thisMBB = MBB;
7964 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7965 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7966 F->insert(MBBIter, newMBB);
7967 F->insert(MBBIter, nextMBB);
7969 // Move all successors to thisMBB to nextMBB
7970 nextMBB->transferSuccessors(thisMBB);
7972 // Update thisMBB to fall through to newMBB
7973 thisMBB->addSuccessor(newMBB);
7975 // newMBB jumps to itself and fall through to nextMBB
7976 newMBB->addSuccessor(nextMBB);
7977 newMBB->addSuccessor(newMBB);
7979 DebugLoc dl = bInstr->getDebugLoc();
7980 // Insert instructions into newMBB based on incoming instruction
7981 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7982 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7983 "unexpected number of operands");
7984 MachineOperand& dest1Oper = bInstr->getOperand(0);
7985 MachineOperand& dest2Oper = bInstr->getOperand(1);
7986 MachineOperand* argOpers[2 + X86AddrNumOperands];
7987 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7988 argOpers[i] = &bInstr->getOperand(i+2);
7990 // x86 address has 5 operands: base, index, scale, displacement, and segment.
7991 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7993 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7994 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7995 for (int i=0; i <= lastAddrIndx; ++i)
7996 (*MIB).addOperand(*argOpers[i]);
7997 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7998 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7999 // add 4 to displacement.
8000 for (int i=0; i <= lastAddrIndx-2; ++i)
8001 (*MIB).addOperand(*argOpers[i]);
8002 MachineOperand newOp3 = *(argOpers[3]);
8004 newOp3.setImm(newOp3.getImm()+4);
8006 newOp3.setOffset(newOp3.getOffset()+4);
8007 (*MIB).addOperand(newOp3);
8008 (*MIB).addOperand(*argOpers[lastAddrIndx]);
8010 // t3/4 are defined later, at the bottom of the loop
8011 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
8012 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
8013 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
8014 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
8015 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
8016 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
8018 // The subsequent operations should be using the destination registers of
8019 //the PHI instructions.
8021 t1 = F->getRegInfo().createVirtualRegister(RC);
8022 t2 = F->getRegInfo().createVirtualRegister(RC);
8023 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
8024 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
8026 t1 = dest1Oper.getReg();
8027 t2 = dest2Oper.getReg();
8030 int valArgIndx = lastAddrIndx + 1;
8031 assert((argOpers[valArgIndx]->isReg() ||
8032 argOpers[valArgIndx]->isImm()) &&
8034 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
8035 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
8036 if (argOpers[valArgIndx]->isReg())
8037 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
8039 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
8040 if (regOpcL != X86::MOV32rr)
8042 (*MIB).addOperand(*argOpers[valArgIndx]);
8043 assert(argOpers[valArgIndx + 1]->isReg() ==
8044 argOpers[valArgIndx]->isReg());
8045 assert(argOpers[valArgIndx + 1]->isImm() ==
8046 argOpers[valArgIndx]->isImm());
8047 if (argOpers[valArgIndx + 1]->isReg())
8048 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
8050 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
8051 if (regOpcH != X86::MOV32rr)
8053 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
8055 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
8057 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
8060 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
8062 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
8065 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
8066 for (int i=0; i <= lastAddrIndx; ++i)
8067 (*MIB).addOperand(*argOpers[i]);
8069 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8070 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8071 bInstr->memoperands_end());
8073 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
8074 MIB.addReg(X86::EAX);
8075 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
8076 MIB.addReg(X86::EDX);
8079 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8081 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
8085 // private utility function
8087 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
8088 MachineBasicBlock *MBB,
8089 unsigned cmovOpc) const {
8090 // For the atomic min/max operator, we generate
8093 // ld t1 = [min/max.addr]
8094 // mov t2 = [min/max.val]
8096 // cmov[cond] t2 = t1
8098 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8100 // fallthrough -->nextMBB
8102 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8103 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8104 MachineFunction::iterator MBBIter = MBB;
8107 /// First build the CFG
8108 MachineFunction *F = MBB->getParent();
8109 MachineBasicBlock *thisMBB = MBB;
8110 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8111 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8112 F->insert(MBBIter, newMBB);
8113 F->insert(MBBIter, nextMBB);
8115 // Move all successors of thisMBB to nextMBB
8116 nextMBB->transferSuccessors(thisMBB);
8118 // Update thisMBB to fall through to newMBB
8119 thisMBB->addSuccessor(newMBB);
8121 // newMBB jumps to newMBB and fall through to nextMBB
8122 newMBB->addSuccessor(nextMBB);
8123 newMBB->addSuccessor(newMBB);
8125 DebugLoc dl = mInstr->getDebugLoc();
8126 // Insert instructions into newMBB based on incoming instruction
8127 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
8128 "unexpected number of operands");
8129 MachineOperand& destOper = mInstr->getOperand(0);
8130 MachineOperand* argOpers[2 + X86AddrNumOperands];
8131 int numArgs = mInstr->getNumOperands() - 1;
8132 for (int i=0; i < numArgs; ++i)
8133 argOpers[i] = &mInstr->getOperand(i+1);
8135 // x86 address has 4 operands: base, index, scale, and displacement
8136 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
8137 int valArgIndx = lastAddrIndx + 1;
8139 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8140 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
8141 for (int i=0; i <= lastAddrIndx; ++i)
8142 (*MIB).addOperand(*argOpers[i]);
8144 // We only support register and immediate values
8145 assert((argOpers[valArgIndx]->isReg() ||
8146 argOpers[valArgIndx]->isImm()) &&
8149 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8150 if (argOpers[valArgIndx]->isReg())
8151 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8153 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
8154 (*MIB).addOperand(*argOpers[valArgIndx]);
8156 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
8159 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
8164 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
8165 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
8169 // Cmp and exchange if none has modified the memory location
8170 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
8171 for (int i=0; i <= lastAddrIndx; ++i)
8172 (*MIB).addOperand(*argOpers[i]);
8174 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8175 (*MIB).setMemRefs(mInstr->memoperands_begin(),
8176 mInstr->memoperands_end());
8178 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
8179 MIB.addReg(X86::EAX);
8182 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8184 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
8188 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
8189 // all of this code can be replaced with that in the .td file.
8191 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
8192 unsigned numArgs, bool memArg) const {
8194 MachineFunction *F = BB->getParent();
8195 DebugLoc dl = MI->getDebugLoc();
8196 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8200 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
8202 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
8204 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
8206 for (unsigned i = 0; i < numArgs; ++i) {
8207 MachineOperand &Op = MI->getOperand(i+1);
8209 if (!(Op.isReg() && Op.isImplicit()))
8213 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
8216 F->DeleteMachineInstr(MI);
8222 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
8224 MachineBasicBlock *MBB) const {
8225 // Emit code to save XMM registers to the stack. The ABI says that the
8226 // number of registers to save is given in %al, so it's theoretically
8227 // possible to do an indirect jump trick to avoid saving all of them,
8228 // however this code takes a simpler approach and just executes all
8229 // of the stores if %al is non-zero. It's less code, and it's probably
8230 // easier on the hardware branch predictor, and stores aren't all that
8231 // expensive anyway.
8233 // Create the new basic blocks. One block contains all the XMM stores,
8234 // and one block is the final destination regardless of whether any
8235 // stores were performed.
8236 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8237 MachineFunction *F = MBB->getParent();
8238 MachineFunction::iterator MBBIter = MBB;
8240 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
8241 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
8242 F->insert(MBBIter, XMMSaveMBB);
8243 F->insert(MBBIter, EndMBB);
8246 // Move any original successors of MBB to the end block.
8247 EndMBB->transferSuccessors(MBB);
8248 // The original block will now fall through to the XMM save block.
8249 MBB->addSuccessor(XMMSaveMBB);
8250 // The XMMSaveMBB will fall through to the end block.
8251 XMMSaveMBB->addSuccessor(EndMBB);
8253 // Now add the instructions.
8254 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8255 DebugLoc DL = MI->getDebugLoc();
8257 unsigned CountReg = MI->getOperand(0).getReg();
8258 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
8259 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
8261 if (!Subtarget->isTargetWin64()) {
8262 // If %al is 0, branch around the XMM save block.
8263 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
8264 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
8265 MBB->addSuccessor(EndMBB);
8268 // In the XMM save block, save all the XMM argument registers.
8269 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
8270 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
8271 MachineMemOperand *MMO =
8272 F->getMachineMemOperand(
8273 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
8274 MachineMemOperand::MOStore, Offset,
8275 /*Size=*/16, /*Align=*/16);
8276 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
8277 .addFrameIndex(RegSaveFrameIndex)
8278 .addImm(/*Scale=*/1)
8279 .addReg(/*IndexReg=*/0)
8280 .addImm(/*Disp=*/Offset)
8281 .addReg(/*Segment=*/0)
8282 .addReg(MI->getOperand(i).getReg())
8283 .addMemOperand(MMO);
8286 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8292 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
8293 MachineBasicBlock *BB,
8294 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8295 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8296 DebugLoc DL = MI->getDebugLoc();
8298 // To "insert" a SELECT_CC instruction, we actually have to insert the
8299 // diamond control-flow pattern. The incoming instruction knows the
8300 // destination vreg to set, the condition code register to branch on, the
8301 // true/false values to select between, and a branch opcode to use.
8302 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8303 MachineFunction::iterator It = BB;
8309 // cmpTY ccX, r1, r2
8311 // fallthrough --> copy0MBB
8312 MachineBasicBlock *thisMBB = BB;
8313 MachineFunction *F = BB->getParent();
8314 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8315 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8317 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
8318 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
8319 F->insert(It, copy0MBB);
8320 F->insert(It, sinkMBB);
8321 // Update machine-CFG edges by first adding all successors of the current
8322 // block to the new block which will contain the Phi node for the select.
8323 // Also inform sdisel of the edge changes.
8324 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
8325 E = BB->succ_end(); I != E; ++I) {
8326 EM->insert(std::make_pair(*I, sinkMBB));
8327 sinkMBB->addSuccessor(*I);
8329 // Next, remove all successors of the current block, and add the true
8330 // and fallthrough blocks as its successors.
8331 while (!BB->succ_empty())
8332 BB->removeSuccessor(BB->succ_begin());
8333 // Add the true and fallthrough blocks as its successors.
8334 BB->addSuccessor(copy0MBB);
8335 BB->addSuccessor(sinkMBB);
8338 // %FalseValue = ...
8339 // # fallthrough to sinkMBB
8342 // Update machine-CFG edges
8343 BB->addSuccessor(sinkMBB);
8346 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8349 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
8350 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8351 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8353 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8359 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8360 MachineBasicBlock *BB,
8361 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
8362 switch (MI->getOpcode()) {
8363 default: assert(false && "Unexpected instr type to insert");
8365 case X86::CMOV_V1I64:
8366 case X86::CMOV_FR32:
8367 case X86::CMOV_FR64:
8368 case X86::CMOV_V4F32:
8369 case X86::CMOV_V2F64:
8370 case X86::CMOV_V2I64:
8371 return EmitLoweredSelect(MI, BB, EM);
8373 case X86::FP32_TO_INT16_IN_MEM:
8374 case X86::FP32_TO_INT32_IN_MEM:
8375 case X86::FP32_TO_INT64_IN_MEM:
8376 case X86::FP64_TO_INT16_IN_MEM:
8377 case X86::FP64_TO_INT32_IN_MEM:
8378 case X86::FP64_TO_INT64_IN_MEM:
8379 case X86::FP80_TO_INT16_IN_MEM:
8380 case X86::FP80_TO_INT32_IN_MEM:
8381 case X86::FP80_TO_INT64_IN_MEM: {
8382 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8383 DebugLoc DL = MI->getDebugLoc();
8385 // Change the floating point control register to use "round towards zero"
8386 // mode when truncating to an integer value.
8387 MachineFunction *F = BB->getParent();
8388 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8389 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8391 // Load the old value of the high byte of the control word...
8393 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8394 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8397 // Set the high part to be round to zero...
8398 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8401 // Reload the modified control word now...
8402 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8404 // Restore the memory image of control word to original value
8405 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8408 // Get the X86 opcode to use.
8410 switch (MI->getOpcode()) {
8411 default: llvm_unreachable("illegal opcode!");
8412 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8413 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8414 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8415 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8416 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8417 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8418 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8419 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8420 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8424 MachineOperand &Op = MI->getOperand(0);
8426 AM.BaseType = X86AddressMode::RegBase;
8427 AM.Base.Reg = Op.getReg();
8429 AM.BaseType = X86AddressMode::FrameIndexBase;
8430 AM.Base.FrameIndex = Op.getIndex();
8432 Op = MI->getOperand(1);
8434 AM.Scale = Op.getImm();
8435 Op = MI->getOperand(2);
8437 AM.IndexReg = Op.getImm();
8438 Op = MI->getOperand(3);
8439 if (Op.isGlobal()) {
8440 AM.GV = Op.getGlobal();
8442 AM.Disp = Op.getImm();
8444 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8445 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8447 // Reload the original control word now.
8448 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8450 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8453 // String/text processing lowering.
8454 case X86::PCMPISTRM128REG:
8455 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8456 case X86::PCMPISTRM128MEM:
8457 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8458 case X86::PCMPESTRM128REG:
8459 return EmitPCMP(MI, BB, 5, false /* in mem */);
8460 case X86::PCMPESTRM128MEM:
8461 return EmitPCMP(MI, BB, 5, true /* in mem */);
8464 case X86::ATOMAND32:
8465 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8466 X86::AND32ri, X86::MOV32rm,
8467 X86::LCMPXCHG32, X86::MOV32rr,
8468 X86::NOT32r, X86::EAX,
8469 X86::GR32RegisterClass);
8471 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8472 X86::OR32ri, X86::MOV32rm,
8473 X86::LCMPXCHG32, X86::MOV32rr,
8474 X86::NOT32r, X86::EAX,
8475 X86::GR32RegisterClass);
8476 case X86::ATOMXOR32:
8477 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8478 X86::XOR32ri, X86::MOV32rm,
8479 X86::LCMPXCHG32, X86::MOV32rr,
8480 X86::NOT32r, X86::EAX,
8481 X86::GR32RegisterClass);
8482 case X86::ATOMNAND32:
8483 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8484 X86::AND32ri, X86::MOV32rm,
8485 X86::LCMPXCHG32, X86::MOV32rr,
8486 X86::NOT32r, X86::EAX,
8487 X86::GR32RegisterClass, true);
8488 case X86::ATOMMIN32:
8489 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8490 case X86::ATOMMAX32:
8491 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8492 case X86::ATOMUMIN32:
8493 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8494 case X86::ATOMUMAX32:
8495 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8497 case X86::ATOMAND16:
8498 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8499 X86::AND16ri, X86::MOV16rm,
8500 X86::LCMPXCHG16, X86::MOV16rr,
8501 X86::NOT16r, X86::AX,
8502 X86::GR16RegisterClass);
8504 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8505 X86::OR16ri, X86::MOV16rm,
8506 X86::LCMPXCHG16, X86::MOV16rr,
8507 X86::NOT16r, X86::AX,
8508 X86::GR16RegisterClass);
8509 case X86::ATOMXOR16:
8510 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8511 X86::XOR16ri, X86::MOV16rm,
8512 X86::LCMPXCHG16, X86::MOV16rr,
8513 X86::NOT16r, X86::AX,
8514 X86::GR16RegisterClass);
8515 case X86::ATOMNAND16:
8516 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8517 X86::AND16ri, X86::MOV16rm,
8518 X86::LCMPXCHG16, X86::MOV16rr,
8519 X86::NOT16r, X86::AX,
8520 X86::GR16RegisterClass, true);
8521 case X86::ATOMMIN16:
8522 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8523 case X86::ATOMMAX16:
8524 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8525 case X86::ATOMUMIN16:
8526 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8527 case X86::ATOMUMAX16:
8528 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8531 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8532 X86::AND8ri, X86::MOV8rm,
8533 X86::LCMPXCHG8, X86::MOV8rr,
8534 X86::NOT8r, X86::AL,
8535 X86::GR8RegisterClass);
8537 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8538 X86::OR8ri, X86::MOV8rm,
8539 X86::LCMPXCHG8, X86::MOV8rr,
8540 X86::NOT8r, X86::AL,
8541 X86::GR8RegisterClass);
8543 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8544 X86::XOR8ri, X86::MOV8rm,
8545 X86::LCMPXCHG8, X86::MOV8rr,
8546 X86::NOT8r, X86::AL,
8547 X86::GR8RegisterClass);
8548 case X86::ATOMNAND8:
8549 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8550 X86::AND8ri, X86::MOV8rm,
8551 X86::LCMPXCHG8, X86::MOV8rr,
8552 X86::NOT8r, X86::AL,
8553 X86::GR8RegisterClass, true);
8554 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8555 // This group is for 64-bit host.
8556 case X86::ATOMAND64:
8557 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8558 X86::AND64ri32, X86::MOV64rm,
8559 X86::LCMPXCHG64, X86::MOV64rr,
8560 X86::NOT64r, X86::RAX,
8561 X86::GR64RegisterClass);
8563 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8564 X86::OR64ri32, X86::MOV64rm,
8565 X86::LCMPXCHG64, X86::MOV64rr,
8566 X86::NOT64r, X86::RAX,
8567 X86::GR64RegisterClass);
8568 case X86::ATOMXOR64:
8569 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8570 X86::XOR64ri32, X86::MOV64rm,
8571 X86::LCMPXCHG64, X86::MOV64rr,
8572 X86::NOT64r, X86::RAX,
8573 X86::GR64RegisterClass);
8574 case X86::ATOMNAND64:
8575 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8576 X86::AND64ri32, X86::MOV64rm,
8577 X86::LCMPXCHG64, X86::MOV64rr,
8578 X86::NOT64r, X86::RAX,
8579 X86::GR64RegisterClass, true);
8580 case X86::ATOMMIN64:
8581 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8582 case X86::ATOMMAX64:
8583 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8584 case X86::ATOMUMIN64:
8585 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8586 case X86::ATOMUMAX64:
8587 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8589 // This group does 64-bit operations on a 32-bit host.
8590 case X86::ATOMAND6432:
8591 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8592 X86::AND32rr, X86::AND32rr,
8593 X86::AND32ri, X86::AND32ri,
8595 case X86::ATOMOR6432:
8596 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8597 X86::OR32rr, X86::OR32rr,
8598 X86::OR32ri, X86::OR32ri,
8600 case X86::ATOMXOR6432:
8601 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8602 X86::XOR32rr, X86::XOR32rr,
8603 X86::XOR32ri, X86::XOR32ri,
8605 case X86::ATOMNAND6432:
8606 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8607 X86::AND32rr, X86::AND32rr,
8608 X86::AND32ri, X86::AND32ri,
8610 case X86::ATOMADD6432:
8611 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8612 X86::ADD32rr, X86::ADC32rr,
8613 X86::ADD32ri, X86::ADC32ri,
8615 case X86::ATOMSUB6432:
8616 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8617 X86::SUB32rr, X86::SBB32rr,
8618 X86::SUB32ri, X86::SBB32ri,
8620 case X86::ATOMSWAP6432:
8621 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8622 X86::MOV32rr, X86::MOV32rr,
8623 X86::MOV32ri, X86::MOV32ri,
8625 case X86::VASTART_SAVE_XMM_REGS:
8626 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8630 //===----------------------------------------------------------------------===//
8631 // X86 Optimization Hooks
8632 //===----------------------------------------------------------------------===//
8634 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8638 const SelectionDAG &DAG,
8639 unsigned Depth) const {
8640 unsigned Opc = Op.getOpcode();
8641 assert((Opc >= ISD::BUILTIN_OP_END ||
8642 Opc == ISD::INTRINSIC_WO_CHAIN ||
8643 Opc == ISD::INTRINSIC_W_CHAIN ||
8644 Opc == ISD::INTRINSIC_VOID) &&
8645 "Should use MaskedValueIsZero if you don't know whether Op"
8646 " is a target node!");
8648 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8660 // These nodes' second result is a boolean.
8661 if (Op.getResNo() == 0)
8665 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8666 Mask.getBitWidth() - 1);
8671 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8672 /// node is a GlobalAddress + offset.
8673 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8674 GlobalValue* &GA, int64_t &Offset) const{
8675 if (N->getOpcode() == X86ISD::Wrapper) {
8676 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8677 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8678 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8682 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8685 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8686 EVT EltVT, LoadSDNode *&LDBase,
8687 unsigned &LastLoadedElt,
8688 SelectionDAG &DAG, MachineFrameInfo *MFI,
8689 const TargetLowering &TLI) {
8691 LastLoadedElt = -1U;
8692 for (unsigned i = 0; i < NumElems; ++i) {
8693 if (N->getMaskElt(i) < 0) {
8699 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8700 if (!Elt.getNode() ||
8701 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8704 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8706 LDBase = cast<LoadSDNode>(Elt.getNode());
8710 if (Elt.getOpcode() == ISD::UNDEF)
8713 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8714 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
8721 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8722 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8723 /// if the load addresses are consecutive, non-overlapping, and in the right
8724 /// order. In the case of v2i64, it will see if it can rewrite the
8725 /// shuffle to be an appropriate build vector so it can take advantage of
8726 // performBuildVectorCombine.
8727 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8728 const TargetLowering &TLI) {
8729 DebugLoc dl = N->getDebugLoc();
8730 EVT VT = N->getValueType(0);
8731 EVT EltVT = VT.getVectorElementType();
8732 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8733 unsigned NumElems = VT.getVectorNumElements();
8735 if (VT.getSizeInBits() != 128)
8738 // Try to combine a vector_shuffle into a 128-bit load.
8739 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8740 LoadSDNode *LD = NULL;
8741 unsigned LastLoadedElt;
8742 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8746 if (LastLoadedElt == NumElems - 1) {
8747 if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
8748 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8749 LD->getSrcValue(), LD->getSrcValueOffset(),
8751 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8752 LD->getSrcValue(), LD->getSrcValueOffset(),
8753 LD->isVolatile(), LD->getAlignment());
8754 } else if (NumElems == 4 && LastLoadedElt == 1) {
8755 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8756 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8757 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8758 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8763 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8764 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8765 const X86Subtarget *Subtarget) {
8766 DebugLoc DL = N->getDebugLoc();
8767 SDValue Cond = N->getOperand(0);
8768 // Get the LHS/RHS of the select.
8769 SDValue LHS = N->getOperand(1);
8770 SDValue RHS = N->getOperand(2);
8772 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8773 // instructions have the peculiarity that if either operand is a NaN,
8774 // they chose what we call the RHS operand (and as such are not symmetric).
8775 // It happens that this matches the semantics of the common C idiom
8776 // x<y?x:y and related forms, so we can recognize these cases.
8777 if (Subtarget->hasSSE2() &&
8778 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8779 Cond.getOpcode() == ISD::SETCC) {
8780 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8782 unsigned Opcode = 0;
8783 // Check for x CC y ? x : y.
8784 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8788 // This can be a min if we can prove that at least one of the operands
8790 if (!FiniteOnlyFPMath()) {
8791 if (DAG.isKnownNeverNaN(RHS)) {
8792 // Put the potential NaN in the RHS so that SSE will preserve it.
8793 std::swap(LHS, RHS);
8794 } else if (!DAG.isKnownNeverNaN(LHS))
8797 Opcode = X86ISD::FMIN;
8800 // This can be a min if we can prove that at least one of the operands
8802 if (!FiniteOnlyFPMath()) {
8803 if (DAG.isKnownNeverNaN(LHS)) {
8804 // Put the potential NaN in the RHS so that SSE will preserve it.
8805 std::swap(LHS, RHS);
8806 } else if (!DAG.isKnownNeverNaN(RHS))
8809 Opcode = X86ISD::FMIN;
8812 // This can be a min, but if either operand is a NaN we need it to
8813 // preserve the original LHS.
8814 std::swap(LHS, RHS);
8818 Opcode = X86ISD::FMIN;
8822 // This can be a max if we can prove that at least one of the operands
8824 if (!FiniteOnlyFPMath()) {
8825 if (DAG.isKnownNeverNaN(LHS)) {
8826 // Put the potential NaN in the RHS so that SSE will preserve it.
8827 std::swap(LHS, RHS);
8828 } else if (!DAG.isKnownNeverNaN(RHS))
8831 Opcode = X86ISD::FMAX;
8834 // This can be a max if we can prove that at least one of the operands
8836 if (!FiniteOnlyFPMath()) {
8837 if (DAG.isKnownNeverNaN(RHS)) {
8838 // Put the potential NaN in the RHS so that SSE will preserve it.
8839 std::swap(LHS, RHS);
8840 } else if (!DAG.isKnownNeverNaN(LHS))
8843 Opcode = X86ISD::FMAX;
8846 // This can be a max, but if either operand is a NaN we need it to
8847 // preserve the original LHS.
8848 std::swap(LHS, RHS);
8852 Opcode = X86ISD::FMAX;
8855 // Check for x CC y ? y : x -- a min/max with reversed arms.
8856 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8860 // This can be a min if we can prove that at least one of the operands
8862 if (!FiniteOnlyFPMath()) {
8863 if (DAG.isKnownNeverNaN(RHS)) {
8864 // Put the potential NaN in the RHS so that SSE will preserve it.
8865 std::swap(LHS, RHS);
8866 } else if (!DAG.isKnownNeverNaN(LHS))
8869 Opcode = X86ISD::FMIN;
8872 // This can be a min if we can prove that at least one of the operands
8874 if (!FiniteOnlyFPMath()) {
8875 if (DAG.isKnownNeverNaN(LHS)) {
8876 // Put the potential NaN in the RHS so that SSE will preserve it.
8877 std::swap(LHS, RHS);
8878 } else if (!DAG.isKnownNeverNaN(RHS))
8881 Opcode = X86ISD::FMIN;
8884 // This can be a min, but if either operand is a NaN we need it to
8885 // preserve the original LHS.
8886 std::swap(LHS, RHS);
8890 Opcode = X86ISD::FMIN;
8894 // This can be a max if we can prove that at least one of the operands
8896 if (!FiniteOnlyFPMath()) {
8897 if (DAG.isKnownNeverNaN(LHS)) {
8898 // Put the potential NaN in the RHS so that SSE will preserve it.
8899 std::swap(LHS, RHS);
8900 } else if (!DAG.isKnownNeverNaN(RHS))
8903 Opcode = X86ISD::FMAX;
8906 // This can be a max if we can prove that at least one of the operands
8908 if (!FiniteOnlyFPMath()) {
8909 if (DAG.isKnownNeverNaN(RHS)) {
8910 // Put the potential NaN in the RHS so that SSE will preserve it.
8911 std::swap(LHS, RHS);
8912 } else if (!DAG.isKnownNeverNaN(LHS))
8915 Opcode = X86ISD::FMAX;
8918 // This can be a max, but if either operand is a NaN we need it to
8919 // preserve the original LHS.
8920 std::swap(LHS, RHS);
8924 Opcode = X86ISD::FMAX;
8930 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8933 // If this is a select between two integer constants, try to do some
8935 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8936 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8937 // Don't do this for crazy integer types.
8938 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8939 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8940 // so that TrueC (the true value) is larger than FalseC.
8941 bool NeedsCondInvert = false;
8943 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8944 // Efficiently invertible.
8945 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8946 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8947 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8948 NeedsCondInvert = true;
8949 std::swap(TrueC, FalseC);
8952 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8953 if (FalseC->getAPIntValue() == 0 &&
8954 TrueC->getAPIntValue().isPowerOf2()) {
8955 if (NeedsCondInvert) // Invert the condition if needed.
8956 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8957 DAG.getConstant(1, Cond.getValueType()));
8959 // Zero extend the condition if needed.
8960 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8962 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8963 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8964 DAG.getConstant(ShAmt, MVT::i8));
8967 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8968 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8969 if (NeedsCondInvert) // Invert the condition if needed.
8970 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8971 DAG.getConstant(1, Cond.getValueType()));
8973 // Zero extend the condition if needed.
8974 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8975 FalseC->getValueType(0), Cond);
8976 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8977 SDValue(FalseC, 0));
8980 // Optimize cases that will turn into an LEA instruction. This requires
8981 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8982 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8983 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8984 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8986 bool isFastMultiplier = false;
8988 switch ((unsigned char)Diff) {
8990 case 1: // result = add base, cond
8991 case 2: // result = lea base( , cond*2)
8992 case 3: // result = lea base(cond, cond*2)
8993 case 4: // result = lea base( , cond*4)
8994 case 5: // result = lea base(cond, cond*4)
8995 case 8: // result = lea base( , cond*8)
8996 case 9: // result = lea base(cond, cond*8)
8997 isFastMultiplier = true;
9002 if (isFastMultiplier) {
9003 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9004 if (NeedsCondInvert) // Invert the condition if needed.
9005 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
9006 DAG.getConstant(1, Cond.getValueType()));
9008 // Zero extend the condition if needed.
9009 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9011 // Scale the condition by the difference.
9013 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9014 DAG.getConstant(Diff, Cond.getValueType()));
9016 // Add the base if non-zero.
9017 if (FalseC->getAPIntValue() != 0)
9018 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9019 SDValue(FalseC, 0));
9029 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
9030 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
9031 TargetLowering::DAGCombinerInfo &DCI) {
9032 DebugLoc DL = N->getDebugLoc();
9034 // If the flag operand isn't dead, don't touch this CMOV.
9035 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
9038 // If this is a select between two integer constants, try to do some
9039 // optimizations. Note that the operands are ordered the opposite of SELECT
9041 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
9042 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9043 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
9044 // larger than FalseC (the false value).
9045 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
9047 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
9048 CC = X86::GetOppositeBranchCondition(CC);
9049 std::swap(TrueC, FalseC);
9052 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
9053 // This is efficient for any integer data type (including i8/i16) and
9055 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
9056 SDValue Cond = N->getOperand(3);
9057 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9058 DAG.getConstant(CC, MVT::i8), Cond);
9060 // Zero extend the condition if needed.
9061 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
9063 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
9064 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
9065 DAG.getConstant(ShAmt, MVT::i8));
9066 if (N->getNumValues() == 2) // Dead flag value?
9067 return DCI.CombineTo(N, Cond, SDValue());
9071 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
9072 // for any integer data type, including i8/i16.
9073 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
9074 SDValue Cond = N->getOperand(3);
9075 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9076 DAG.getConstant(CC, MVT::i8), Cond);
9078 // Zero extend the condition if needed.
9079 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
9080 FalseC->getValueType(0), Cond);
9081 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9082 SDValue(FalseC, 0));
9084 if (N->getNumValues() == 2) // Dead flag value?
9085 return DCI.CombineTo(N, Cond, SDValue());
9089 // Optimize cases that will turn into an LEA instruction. This requires
9090 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
9091 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
9092 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
9093 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
9095 bool isFastMultiplier = false;
9097 switch ((unsigned char)Diff) {
9099 case 1: // result = add base, cond
9100 case 2: // result = lea base( , cond*2)
9101 case 3: // result = lea base(cond, cond*2)
9102 case 4: // result = lea base( , cond*4)
9103 case 5: // result = lea base(cond, cond*4)
9104 case 8: // result = lea base( , cond*8)
9105 case 9: // result = lea base(cond, cond*8)
9106 isFastMultiplier = true;
9111 if (isFastMultiplier) {
9112 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
9113 SDValue Cond = N->getOperand(3);
9114 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9115 DAG.getConstant(CC, MVT::i8), Cond);
9116 // Zero extend the condition if needed.
9117 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
9119 // Scale the condition by the difference.
9121 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
9122 DAG.getConstant(Diff, Cond.getValueType()));
9124 // Add the base if non-zero.
9125 if (FalseC->getAPIntValue() != 0)
9126 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
9127 SDValue(FalseC, 0));
9128 if (N->getNumValues() == 2) // Dead flag value?
9129 return DCI.CombineTo(N, Cond, SDValue());
9139 /// PerformMulCombine - Optimize a single multiply with constant into two
9140 /// in order to implement it with two cheaper instructions, e.g.
9141 /// LEA + SHL, LEA + LEA.
9142 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
9143 TargetLowering::DAGCombinerInfo &DCI) {
9144 if (DAG.getMachineFunction().
9145 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
9148 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9151 EVT VT = N->getValueType(0);
9155 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
9158 uint64_t MulAmt = C->getZExtValue();
9159 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
9162 uint64_t MulAmt1 = 0;
9163 uint64_t MulAmt2 = 0;
9164 if ((MulAmt % 9) == 0) {
9166 MulAmt2 = MulAmt / 9;
9167 } else if ((MulAmt % 5) == 0) {
9169 MulAmt2 = MulAmt / 5;
9170 } else if ((MulAmt % 3) == 0) {
9172 MulAmt2 = MulAmt / 3;
9175 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
9176 DebugLoc DL = N->getDebugLoc();
9178 if (isPowerOf2_64(MulAmt2) &&
9179 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
9180 // If second multiplifer is pow2, issue it first. We want the multiply by
9181 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
9183 std::swap(MulAmt1, MulAmt2);
9186 if (isPowerOf2_64(MulAmt1))
9187 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
9188 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
9190 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
9191 DAG.getConstant(MulAmt1, VT));
9193 if (isPowerOf2_64(MulAmt2))
9194 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
9195 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
9197 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
9198 DAG.getConstant(MulAmt2, VT));
9200 // Do not add new nodes to DAG combiner worklist.
9201 DCI.CombineTo(N, NewMul, false);
9206 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
9207 SDValue N0 = N->getOperand(0);
9208 SDValue N1 = N->getOperand(1);
9209 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9210 EVT VT = N0.getValueType();
9212 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
9213 // since the result of setcc_c is all zero's or all ones.
9214 if (N1C && N0.getOpcode() == ISD::AND &&
9215 N0.getOperand(1).getOpcode() == ISD::Constant) {
9216 SDValue N00 = N0.getOperand(0);
9217 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
9218 ((N00.getOpcode() == ISD::ANY_EXTEND ||
9219 N00.getOpcode() == ISD::ZERO_EXTEND) &&
9220 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
9221 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
9222 APInt ShAmt = N1C->getAPIntValue();
9223 Mask = Mask.shl(ShAmt);
9225 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
9226 N00, DAG.getConstant(Mask, VT));
9233 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
9235 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
9236 const X86Subtarget *Subtarget) {
9237 EVT VT = N->getValueType(0);
9238 if (!VT.isVector() && VT.isInteger() &&
9239 N->getOpcode() == ISD::SHL)
9240 return PerformSHLCombine(N, DAG);
9242 // On X86 with SSE2 support, we can transform this to a vector shift if
9243 // all elements are shifted by the same amount. We can't do this in legalize
9244 // because the a constant vector is typically transformed to a constant pool
9245 // so we have no knowledge of the shift amount.
9246 if (!Subtarget->hasSSE2())
9249 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
9252 SDValue ShAmtOp = N->getOperand(1);
9253 EVT EltVT = VT.getVectorElementType();
9254 DebugLoc DL = N->getDebugLoc();
9255 SDValue BaseShAmt = SDValue();
9256 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
9257 unsigned NumElts = VT.getVectorNumElements();
9259 for (; i != NumElts; ++i) {
9260 SDValue Arg = ShAmtOp.getOperand(i);
9261 if (Arg.getOpcode() == ISD::UNDEF) continue;
9265 for (; i != NumElts; ++i) {
9266 SDValue Arg = ShAmtOp.getOperand(i);
9267 if (Arg.getOpcode() == ISD::UNDEF) continue;
9268 if (Arg != BaseShAmt) {
9272 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
9273 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
9274 SDValue InVec = ShAmtOp.getOperand(0);
9275 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
9276 unsigned NumElts = InVec.getValueType().getVectorNumElements();
9278 for (; i != NumElts; ++i) {
9279 SDValue Arg = InVec.getOperand(i);
9280 if (Arg.getOpcode() == ISD::UNDEF) continue;
9284 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
9285 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
9286 unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
9287 if (C->getZExtValue() == SplatIdx)
9288 BaseShAmt = InVec.getOperand(1);
9291 if (BaseShAmt.getNode() == 0)
9292 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
9293 DAG.getIntPtrConstant(0));
9297 // The shift amount is an i32.
9298 if (EltVT.bitsGT(MVT::i32))
9299 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
9300 else if (EltVT.bitsLT(MVT::i32))
9301 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
9303 // The shift amount is identical so we can do a vector shift.
9304 SDValue ValOp = N->getOperand(0);
9305 switch (N->getOpcode()) {
9307 llvm_unreachable("Unknown shift opcode!");
9310 if (VT == MVT::v2i64)
9311 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9312 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9314 if (VT == MVT::v4i32)
9315 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9316 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9318 if (VT == MVT::v8i16)
9319 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9320 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9324 if (VT == MVT::v4i32)
9325 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9326 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9328 if (VT == MVT::v8i16)
9329 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9330 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9334 if (VT == MVT::v2i64)
9335 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9336 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9338 if (VT == MVT::v4i32)
9339 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9340 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9342 if (VT == MVT::v8i16)
9343 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
9344 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9351 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
9352 const X86Subtarget *Subtarget) {
9353 EVT VT = N->getValueType(0);
9354 if (VT != MVT::i64 || !Subtarget->is64Bit())
9357 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
9358 SDValue N0 = N->getOperand(0);
9359 SDValue N1 = N->getOperand(1);
9360 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
9362 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
9365 SDValue ShAmt0 = N0.getOperand(1);
9366 if (ShAmt0.getValueType() != MVT::i8)
9368 SDValue ShAmt1 = N1.getOperand(1);
9369 if (ShAmt1.getValueType() != MVT::i8)
9371 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
9372 ShAmt0 = ShAmt0.getOperand(0);
9373 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
9374 ShAmt1 = ShAmt1.getOperand(0);
9376 DebugLoc DL = N->getDebugLoc();
9377 unsigned Opc = X86ISD::SHLD;
9378 SDValue Op0 = N0.getOperand(0);
9379 SDValue Op1 = N1.getOperand(0);
9380 if (ShAmt0.getOpcode() == ISD::SUB) {
9382 std::swap(Op0, Op1);
9383 std::swap(ShAmt0, ShAmt1);
9386 if (ShAmt1.getOpcode() == ISD::SUB) {
9387 SDValue Sum = ShAmt1.getOperand(0);
9388 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
9389 if (SumC->getSExtValue() == 64 &&
9390 ShAmt1.getOperand(1) == ShAmt0)
9391 return DAG.getNode(Opc, DL, VT,
9393 DAG.getNode(ISD::TRUNCATE, DL,
9396 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
9397 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
9399 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64)
9400 return DAG.getNode(Opc, DL, VT,
9401 N0.getOperand(0), N1.getOperand(0),
9402 DAG.getNode(ISD::TRUNCATE, DL,
9409 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
9410 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
9411 const X86Subtarget *Subtarget) {
9412 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
9413 // the FP state in cases where an emms may be missing.
9414 // A preferable solution to the general problem is to figure out the right
9415 // places to insert EMMS. This qualifies as a quick hack.
9417 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
9418 StoreSDNode *St = cast<StoreSDNode>(N);
9419 EVT VT = St->getValue().getValueType();
9420 if (VT.getSizeInBits() != 64)
9423 const Function *F = DAG.getMachineFunction().getFunction();
9424 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
9425 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
9426 && Subtarget->hasSSE2();
9427 if ((VT.isVector() ||
9428 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
9429 isa<LoadSDNode>(St->getValue()) &&
9430 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
9431 St->getChain().hasOneUse() && !St->isVolatile()) {
9432 SDNode* LdVal = St->getValue().getNode();
9434 int TokenFactorIndex = -1;
9435 SmallVector<SDValue, 8> Ops;
9436 SDNode* ChainVal = St->getChain().getNode();
9437 // Must be a store of a load. We currently handle two cases: the load
9438 // is a direct child, and it's under an intervening TokenFactor. It is
9439 // possible to dig deeper under nested TokenFactors.
9440 if (ChainVal == LdVal)
9441 Ld = cast<LoadSDNode>(St->getChain());
9442 else if (St->getValue().hasOneUse() &&
9443 ChainVal->getOpcode() == ISD::TokenFactor) {
9444 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
9445 if (ChainVal->getOperand(i).getNode() == LdVal) {
9446 TokenFactorIndex = i;
9447 Ld = cast<LoadSDNode>(St->getValue());
9449 Ops.push_back(ChainVal->getOperand(i));
9453 if (!Ld || !ISD::isNormalLoad(Ld))
9456 // If this is not the MMX case, i.e. we are just turning i64 load/store
9457 // into f64 load/store, avoid the transformation if there are multiple
9458 // uses of the loaded value.
9459 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9462 DebugLoc LdDL = Ld->getDebugLoc();
9463 DebugLoc StDL = N->getDebugLoc();
9464 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9465 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9467 if (Subtarget->is64Bit() || F64IsLegal) {
9468 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9469 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9470 Ld->getBasePtr(), Ld->getSrcValue(),
9471 Ld->getSrcValueOffset(), Ld->isVolatile(),
9472 Ld->getAlignment());
9473 SDValue NewChain = NewLd.getValue(1);
9474 if (TokenFactorIndex != -1) {
9475 Ops.push_back(NewChain);
9476 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9479 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9480 St->getSrcValue(), St->getSrcValueOffset(),
9481 St->isVolatile(), St->getAlignment());
9484 // Otherwise, lower to two pairs of 32-bit loads / stores.
9485 SDValue LoAddr = Ld->getBasePtr();
9486 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9487 DAG.getConstant(4, MVT::i32));
9489 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9490 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9491 Ld->isVolatile(), Ld->getAlignment());
9492 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9493 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9495 MinAlign(Ld->getAlignment(), 4));
9497 SDValue NewChain = LoLd.getValue(1);
9498 if (TokenFactorIndex != -1) {
9499 Ops.push_back(LoLd);
9500 Ops.push_back(HiLd);
9501 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9505 LoAddr = St->getBasePtr();
9506 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9507 DAG.getConstant(4, MVT::i32));
9509 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9510 St->getSrcValue(), St->getSrcValueOffset(),
9511 St->isVolatile(), St->getAlignment());
9512 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9514 St->getSrcValueOffset() + 4,
9516 MinAlign(St->getAlignment(), 4));
9517 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9522 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9523 /// X86ISD::FXOR nodes.
9524 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9525 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9526 // F[X]OR(0.0, x) -> x
9527 // F[X]OR(x, 0.0) -> x
9528 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9529 if (C->getValueAPF().isPosZero())
9530 return N->getOperand(1);
9531 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9532 if (C->getValueAPF().isPosZero())
9533 return N->getOperand(0);
9537 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9538 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9539 // FAND(0.0, x) -> 0.0
9540 // FAND(x, 0.0) -> 0.0
9541 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9542 if (C->getValueAPF().isPosZero())
9543 return N->getOperand(0);
9544 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9545 if (C->getValueAPF().isPosZero())
9546 return N->getOperand(1);
9550 static SDValue PerformBTCombine(SDNode *N,
9552 TargetLowering::DAGCombinerInfo &DCI) {
9553 // BT ignores high bits in the bit index operand.
9554 SDValue Op1 = N->getOperand(1);
9555 if (Op1.hasOneUse()) {
9556 unsigned BitWidth = Op1.getValueSizeInBits();
9557 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9558 APInt KnownZero, KnownOne;
9559 TargetLowering::TargetLoweringOpt TLO(DAG);
9560 TargetLowering &TLI = DAG.getTargetLoweringInfo();
9561 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9562 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9563 DCI.CommitTargetLoweringOpt(TLO);
9568 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9569 SDValue Op = N->getOperand(0);
9570 if (Op.getOpcode() == ISD::BIT_CONVERT)
9571 Op = Op.getOperand(0);
9572 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9573 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9574 VT.getVectorElementType().getSizeInBits() ==
9575 OpVT.getVectorElementType().getSizeInBits()) {
9576 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9581 // On X86 and X86-64, atomic operations are lowered to locked instructions.
9582 // Locked instructions, in turn, have implicit fence semantics (all memory
9583 // operations are flushed before issuing the locked instruction, and the
9584 // are not buffered), so we can fold away the common pattern of
9585 // fence-atomic-fence.
9586 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9587 SDValue atomic = N->getOperand(0);
9588 switch (atomic.getOpcode()) {
9589 case ISD::ATOMIC_CMP_SWAP:
9590 case ISD::ATOMIC_SWAP:
9591 case ISD::ATOMIC_LOAD_ADD:
9592 case ISD::ATOMIC_LOAD_SUB:
9593 case ISD::ATOMIC_LOAD_AND:
9594 case ISD::ATOMIC_LOAD_OR:
9595 case ISD::ATOMIC_LOAD_XOR:
9596 case ISD::ATOMIC_LOAD_NAND:
9597 case ISD::ATOMIC_LOAD_MIN:
9598 case ISD::ATOMIC_LOAD_MAX:
9599 case ISD::ATOMIC_LOAD_UMIN:
9600 case ISD::ATOMIC_LOAD_UMAX:
9606 SDValue fence = atomic.getOperand(0);
9607 if (fence.getOpcode() != ISD::MEMBARRIER)
9610 switch (atomic.getOpcode()) {
9611 case ISD::ATOMIC_CMP_SWAP:
9612 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9613 atomic.getOperand(1), atomic.getOperand(2),
9614 atomic.getOperand(3));
9615 case ISD::ATOMIC_SWAP:
9616 case ISD::ATOMIC_LOAD_ADD:
9617 case ISD::ATOMIC_LOAD_SUB:
9618 case ISD::ATOMIC_LOAD_AND:
9619 case ISD::ATOMIC_LOAD_OR:
9620 case ISD::ATOMIC_LOAD_XOR:
9621 case ISD::ATOMIC_LOAD_NAND:
9622 case ISD::ATOMIC_LOAD_MIN:
9623 case ISD::ATOMIC_LOAD_MAX:
9624 case ISD::ATOMIC_LOAD_UMIN:
9625 case ISD::ATOMIC_LOAD_UMAX:
9626 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9627 atomic.getOperand(1), atomic.getOperand(2));
9633 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
9634 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
9635 // (and (i32 x86isd::setcc_carry), 1)
9636 // This eliminates the zext. This transformation is necessary because
9637 // ISD::SETCC is always legalized to i8.
9638 DebugLoc dl = N->getDebugLoc();
9639 SDValue N0 = N->getOperand(0);
9640 EVT VT = N->getValueType(0);
9641 if (N0.getOpcode() == ISD::AND &&
9643 N0.getOperand(0).hasOneUse()) {
9644 SDValue N00 = N0.getOperand(0);
9645 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
9647 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
9648 if (!C || C->getZExtValue() != 1)
9650 return DAG.getNode(ISD::AND, dl, VT,
9651 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
9652 N00.getOperand(0), N00.getOperand(1)),
9653 DAG.getConstant(1, VT));
9659 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9660 DAGCombinerInfo &DCI) const {
9661 SelectionDAG &DAG = DCI.DAG;
9662 switch (N->getOpcode()) {
9664 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9665 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9666 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9667 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9670 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9671 case ISD::OR: return PerformOrCombine(N, DAG, Subtarget);
9672 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9674 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9675 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9676 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9677 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9678 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9679 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
9685 //===----------------------------------------------------------------------===//
9686 // X86 Inline Assembly Support
9687 //===----------------------------------------------------------------------===//
9689 static bool LowerToBSwap(CallInst *CI) {
9690 // FIXME: this should verify that we are targetting a 486 or better. If not,
9691 // we will turn this bswap into something that will be lowered to logical ops
9692 // instead of emitting the bswap asm. For now, we don't support 486 or lower
9693 // so don't worry about this.
9695 // Verify this is a simple bswap.
9696 if (CI->getNumOperands() != 2 ||
9697 CI->getType() != CI->getOperand(1)->getType() ||
9698 !CI->getType()->isInteger())
9701 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9702 if (!Ty || Ty->getBitWidth() % 16 != 0)
9705 // Okay, we can do this xform, do so now.
9706 const Type *Tys[] = { Ty };
9707 Module *M = CI->getParent()->getParent()->getParent();
9708 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9710 Value *Op = CI->getOperand(1);
9711 Op = CallInst::Create(Int, Op, CI->getName(), CI);
9713 CI->replaceAllUsesWith(Op);
9714 CI->eraseFromParent();
9718 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9719 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9720 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9722 std::string AsmStr = IA->getAsmString();
9724 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9725 SmallVector<StringRef, 4> AsmPieces;
9726 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9728 switch (AsmPieces.size()) {
9729 default: return false;
9731 AsmStr = AsmPieces[0];
9733 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9736 if (AsmPieces.size() == 2 &&
9737 (AsmPieces[0] == "bswap" ||
9738 AsmPieces[0] == "bswapq" ||
9739 AsmPieces[0] == "bswapl") &&
9740 (AsmPieces[1] == "$0" ||
9741 AsmPieces[1] == "${0:q}")) {
9742 // No need to check constraints, nothing other than the equivalent of
9743 // "=r,0" would be valid here.
9744 return LowerToBSwap(CI);
9746 // rorw $$8, ${0:w} --> llvm.bswap.i16
9747 if (CI->getType()->isInteger(16) &&
9748 AsmPieces.size() == 3 &&
9749 AsmPieces[0] == "rorw" &&
9750 AsmPieces[1] == "$$8," &&
9751 AsmPieces[2] == "${0:w}" &&
9752 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
9753 return LowerToBSwap(CI);
9757 if (CI->getType()->isInteger(64) &&
9758 Constraints.size() >= 2 &&
9759 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9760 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9761 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9762 SmallVector<StringRef, 4> Words;
9763 SplitString(AsmPieces[0], Words, " \t");
9764 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9766 SplitString(AsmPieces[1], Words, " \t");
9767 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9769 SplitString(AsmPieces[2], Words, " \t,");
9770 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9771 Words[2] == "%edx") {
9772 return LowerToBSwap(CI);
9784 /// getConstraintType - Given a constraint letter, return the type of
9785 /// constraint it is for this target.
9786 X86TargetLowering::ConstraintType
9787 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9788 if (Constraint.size() == 1) {
9789 switch (Constraint[0]) {
9801 return C_RegisterClass;
9809 return TargetLowering::getConstraintType(Constraint);
9812 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9813 /// with another that has more specific requirements based on the type of the
9814 /// corresponding operand.
9815 const char *X86TargetLowering::
9816 LowerXConstraint(EVT ConstraintVT) const {
9817 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9818 // 'f' like normal targets.
9819 if (ConstraintVT.isFloatingPoint()) {
9820 if (Subtarget->hasSSE2())
9822 if (Subtarget->hasSSE1())
9826 return TargetLowering::LowerXConstraint(ConstraintVT);
9829 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9830 /// vector. If it is invalid, don't add anything to Ops.
9831 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9834 std::vector<SDValue>&Ops,
9835 SelectionDAG &DAG) const {
9836 SDValue Result(0, 0);
9838 switch (Constraint) {
9841 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9842 if (C->getZExtValue() <= 31) {
9843 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9849 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9850 if (C->getZExtValue() <= 63) {
9851 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9857 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9858 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9859 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9865 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9866 if (C->getZExtValue() <= 255) {
9867 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9873 // 32-bit signed value
9874 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9875 const ConstantInt *CI = C->getConstantIntValue();
9876 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9877 C->getSExtValue())) {
9878 // Widen to 64 bits here to get it sign extended.
9879 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9882 // FIXME gcc accepts some relocatable values here too, but only in certain
9883 // memory models; it's complicated.
9888 // 32-bit unsigned value
9889 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9890 const ConstantInt *CI = C->getConstantIntValue();
9891 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9892 C->getZExtValue())) {
9893 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9897 // FIXME gcc accepts some relocatable values here too, but only in certain
9898 // memory models; it's complicated.
9902 // Literal immediates are always ok.
9903 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9904 // Widen to 64 bits here to get it sign extended.
9905 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
9909 // If we are in non-pic codegen mode, we allow the address of a global (with
9910 // an optional displacement) to be used with 'i'.
9911 GlobalAddressSDNode *GA = 0;
9914 // Match either (GA), (GA+C), (GA+C1+C2), etc.
9916 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
9917 Offset += GA->getOffset();
9919 } else if (Op.getOpcode() == ISD::ADD) {
9920 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9921 Offset += C->getZExtValue();
9922 Op = Op.getOperand(0);
9925 } else if (Op.getOpcode() == ISD::SUB) {
9926 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9927 Offset += -C->getZExtValue();
9928 Op = Op.getOperand(0);
9933 // Otherwise, this isn't something we can handle, reject it.
9937 GlobalValue *GV = GA->getGlobal();
9938 // If we require an extra load to get this address, as in PIC mode, we
9940 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
9941 getTargetMachine())))
9945 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
9947 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
9953 if (Result.getNode()) {
9954 Ops.push_back(Result);
9957 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
9961 std::vector<unsigned> X86TargetLowering::
9962 getRegClassForInlineAsmConstraint(const std::string &Constraint,
9964 if (Constraint.size() == 1) {
9965 // FIXME: not handling fp-stack yet!
9966 switch (Constraint[0]) { // GCC X86 Constraint Letters
9967 default: break; // Unknown constraint letter
9968 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
9969 if (Subtarget->is64Bit()) {
9971 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
9972 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
9973 X86::R10D,X86::R11D,X86::R12D,
9974 X86::R13D,X86::R14D,X86::R15D,
9975 X86::EBP, X86::ESP, 0);
9976 else if (VT == MVT::i16)
9977 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
9978 X86::SI, X86::DI, X86::R8W,X86::R9W,
9979 X86::R10W,X86::R11W,X86::R12W,
9980 X86::R13W,X86::R14W,X86::R15W,
9981 X86::BP, X86::SP, 0);
9982 else if (VT == MVT::i8)
9983 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
9984 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9985 X86::R10B,X86::R11B,X86::R12B,
9986 X86::R13B,X86::R14B,X86::R15B,
9987 X86::BPL, X86::SPL, 0);
9989 else if (VT == MVT::i64)
9990 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
9991 X86::RSI, X86::RDI, X86::R8, X86::R9,
9992 X86::R10, X86::R11, X86::R12,
9993 X86::R13, X86::R14, X86::R15,
9994 X86::RBP, X86::RSP, 0);
9998 // 32-bit fallthrough
10000 if (VT == MVT::i32)
10001 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
10002 else if (VT == MVT::i16)
10003 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
10004 else if (VT == MVT::i8)
10005 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
10006 else if (VT == MVT::i64)
10007 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
10012 return std::vector<unsigned>();
10015 std::pair<unsigned, const TargetRegisterClass*>
10016 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10018 // First, see if this is a constraint that directly corresponds to an LLVM
10020 if (Constraint.size() == 1) {
10021 // GCC Constraint Letters
10022 switch (Constraint[0]) {
10024 case 'r': // GENERAL_REGS
10025 case 'l': // INDEX_REGS
10027 return std::make_pair(0U, X86::GR8RegisterClass);
10028 if (VT == MVT::i16)
10029 return std::make_pair(0U, X86::GR16RegisterClass);
10030 if (VT == MVT::i32 || !Subtarget->is64Bit())
10031 return std::make_pair(0U, X86::GR32RegisterClass);
10032 return std::make_pair(0U, X86::GR64RegisterClass);
10033 case 'R': // LEGACY_REGS
10035 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
10036 if (VT == MVT::i16)
10037 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
10038 if (VT == MVT::i32 || !Subtarget->is64Bit())
10039 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
10040 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
10041 case 'f': // FP Stack registers.
10042 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
10043 // value to the correct fpstack register class.
10044 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
10045 return std::make_pair(0U, X86::RFP32RegisterClass);
10046 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
10047 return std::make_pair(0U, X86::RFP64RegisterClass);
10048 return std::make_pair(0U, X86::RFP80RegisterClass);
10049 case 'y': // MMX_REGS if MMX allowed.
10050 if (!Subtarget->hasMMX()) break;
10051 return std::make_pair(0U, X86::VR64RegisterClass);
10052 case 'Y': // SSE_REGS if SSE2 allowed
10053 if (!Subtarget->hasSSE2()) break;
10055 case 'x': // SSE_REGS if SSE1 allowed
10056 if (!Subtarget->hasSSE1()) break;
10058 switch (VT.getSimpleVT().SimpleTy) {
10060 // Scalar SSE types.
10063 return std::make_pair(0U, X86::FR32RegisterClass);
10066 return std::make_pair(0U, X86::FR64RegisterClass);
10074 return std::make_pair(0U, X86::VR128RegisterClass);
10080 // Use the default implementation in TargetLowering to convert the register
10081 // constraint into a member of a register class.
10082 std::pair<unsigned, const TargetRegisterClass*> Res;
10083 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10085 // Not found as a standard register?
10086 if (Res.second == 0) {
10087 // Map st(0) -> st(7) -> ST0
10088 if (Constraint.size() == 7 && Constraint[0] == '{' &&
10089 tolower(Constraint[1]) == 's' &&
10090 tolower(Constraint[2]) == 't' &&
10091 Constraint[3] == '(' &&
10092 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
10093 Constraint[5] == ')' &&
10094 Constraint[6] == '}') {
10096 Res.first = X86::ST0+Constraint[4]-'0';
10097 Res.second = X86::RFP80RegisterClass;
10101 // GCC allows "st(0)" to be called just plain "st".
10102 if (StringRef("{st}").equals_lower(Constraint)) {
10103 Res.first = X86::ST0;
10104 Res.second = X86::RFP80RegisterClass;
10109 if (StringRef("{flags}").equals_lower(Constraint)) {
10110 Res.first = X86::EFLAGS;
10111 Res.second = X86::CCRRegisterClass;
10115 // 'A' means EAX + EDX.
10116 if (Constraint == "A") {
10117 Res.first = X86::EAX;
10118 Res.second = X86::GR32_ADRegisterClass;
10124 // Otherwise, check to see if this is a register class of the wrong value
10125 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
10126 // turn into {ax},{dx}.
10127 if (Res.second->hasType(VT))
10128 return Res; // Correct type already, nothing to do.
10130 // All of the single-register GCC register classes map their values onto
10131 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
10132 // really want an 8-bit or 32-bit register, map to the appropriate register
10133 // class and return the appropriate register.
10134 if (Res.second == X86::GR16RegisterClass) {
10135 if (VT == MVT::i8) {
10136 unsigned DestReg = 0;
10137 switch (Res.first) {
10139 case X86::AX: DestReg = X86::AL; break;
10140 case X86::DX: DestReg = X86::DL; break;
10141 case X86::CX: DestReg = X86::CL; break;
10142 case X86::BX: DestReg = X86::BL; break;
10145 Res.first = DestReg;
10146 Res.second = X86::GR8RegisterClass;
10148 } else if (VT == MVT::i32) {
10149 unsigned DestReg = 0;
10150 switch (Res.first) {
10152 case X86::AX: DestReg = X86::EAX; break;
10153 case X86::DX: DestReg = X86::EDX; break;
10154 case X86::CX: DestReg = X86::ECX; break;
10155 case X86::BX: DestReg = X86::EBX; break;
10156 case X86::SI: DestReg = X86::ESI; break;
10157 case X86::DI: DestReg = X86::EDI; break;
10158 case X86::BP: DestReg = X86::EBP; break;
10159 case X86::SP: DestReg = X86::ESP; break;
10162 Res.first = DestReg;
10163 Res.second = X86::GR32RegisterClass;
10165 } else if (VT == MVT::i64) {
10166 unsigned DestReg = 0;
10167 switch (Res.first) {
10169 case X86::AX: DestReg = X86::RAX; break;
10170 case X86::DX: DestReg = X86::RDX; break;
10171 case X86::CX: DestReg = X86::RCX; break;
10172 case X86::BX: DestReg = X86::RBX; break;
10173 case X86::SI: DestReg = X86::RSI; break;
10174 case X86::DI: DestReg = X86::RDI; break;
10175 case X86::BP: DestReg = X86::RBP; break;
10176 case X86::SP: DestReg = X86::RSP; break;
10179 Res.first = DestReg;
10180 Res.second = X86::GR64RegisterClass;
10183 } else if (Res.second == X86::FR32RegisterClass ||
10184 Res.second == X86::FR64RegisterClass ||
10185 Res.second == X86::VR128RegisterClass) {
10186 // Handle references to XMM physical registers that got mapped into the
10187 // wrong class. This can happen with constraints like {xmm0} where the
10188 // target independent register mapper will just pick the first match it can
10189 // find, ignoring the required type.
10190 if (VT == MVT::f32)
10191 Res.second = X86::FR32RegisterClass;
10192 else if (VT == MVT::f64)
10193 Res.second = X86::FR64RegisterClass;
10194 else if (X86::VR128RegisterClass->hasType(VT))
10195 Res.second = X86::VR128RegisterClass;
10201 //===----------------------------------------------------------------------===//
10202 // X86 Widen vector type
10203 //===----------------------------------------------------------------------===//
10205 /// getWidenVectorType: given a vector type, returns the type to widen
10206 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
10207 /// If there is no vector type that we want to widen to, returns MVT::Other
10208 /// When and where to widen is target dependent based on the cost of
10209 /// scalarizing vs using the wider vector type.
10211 EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
10212 assert(VT.isVector());
10213 if (isTypeLegal(VT))
10216 // TODO: In computeRegisterProperty, we can compute the list of legal vector
10217 // type based on element type. This would speed up our search (though
10218 // it may not be worth it since the size of the list is relatively
10220 EVT EltVT = VT.getVectorElementType();
10221 unsigned NElts = VT.getVectorNumElements();
10223 // On X86, it make sense to widen any vector wider than 1
10227 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
10228 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
10229 EVT SVT = (MVT::SimpleValueType)nVT;
10231 if (isTypeLegal(SVT) &&
10232 SVT.getVectorElementType() == EltVT &&
10233 SVT.getVectorNumElements() > NElts)