1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static SDValue Insert128BitVector(SDValue Result,
69 static SDValue Extract128BitVector(SDValue Vec,
74 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
75 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
76 /// simple subregister reference. Idx is an index in the 128 bits we
77 /// want. It need not be aligned to a 128-bit bounday. That makes
78 /// lowering EXTRACT_VECTOR_ELT operations easier.
79 static SDValue Extract128BitVector(SDValue Vec,
83 EVT VT = Vec.getValueType();
84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
85 EVT ElVT = VT.getVectorElementType();
86 int Factor = VT.getSizeInBits()/128;
87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
88 VT.getVectorNumElements()/Factor);
90 // Extract from UNDEF is UNDEF.
91 if (Vec.getOpcode() == ISD::UNDEF)
92 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
94 if (isa<ConstantSDNode>(Idx)) {
95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
98 // we can match to VEXTRACTF128.
99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
101 // This is the index of the first element of the 128-bit chunk
103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
116 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
117 /// sets things up to match to an AVX VINSERTF128 instruction or a
118 /// simple superregister reference. Idx is an index in the 128 bits
119 /// we want. It need not be aligned to a 128-bit bounday. That makes
120 /// lowering INSERT_VECTOR_ELT operations easier.
121 static SDValue Insert128BitVector(SDValue Result,
126 if (isa<ConstantSDNode>(Idx)) {
127 EVT VT = Vec.getValueType();
128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
130 EVT ElVT = VT.getVectorElementType();
131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
132 EVT ResultVT = Result.getValueType();
134 // Insert the relevant 128 bits.
135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
137 // This is the index of the first element of the 128-bit chunk
139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
151 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
153 bool is64Bit = Subtarget->is64Bit();
155 if (Subtarget->isTargetEnvMacho()) {
157 return new X8664_MachoTargetObjectFile();
158 return new TargetLoweringObjectFileMachO();
161 if (Subtarget->isTargetELF())
162 return new TargetLoweringObjectFileELF();
163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
164 return new TargetLoweringObjectFileCOFF();
165 llvm_unreachable("unknown subtarget type");
168 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
169 : TargetLowering(TM, createTLOF(TM)) {
170 Subtarget = &TM.getSubtarget<X86Subtarget>();
171 X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX();
172 X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX();
173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
175 RegInfo = TM.getRegisterInfo();
176 TD = getTargetData();
178 // Set up the TargetLowering object.
179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
181 // X86 is weird, it always uses i8 for shift amounts and setcc results.
182 setBooleanContents(ZeroOrOneBooleanContent);
184 // For 64-bit since we have so many registers use the ILP scheduler, for
185 // 32-bit code use the register pressure specific scheduling.
186 if (Subtarget->is64Bit())
187 setSchedulingPreference(Sched::ILP);
189 setSchedulingPreference(Sched::RegPressure);
190 setStackPointerRegisterToSaveRestore(X86StackPtr);
192 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
193 // Setup Windows compiler runtime calls.
194 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
195 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
196 setLibcallName(RTLIB::SREM_I64, "_allrem");
197 setLibcallName(RTLIB::UREM_I64, "_aullrem");
198 setLibcallName(RTLIB::MUL_I64, "_allmul");
199 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
200 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
201 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
202 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
203 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
207 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
210 if (Subtarget->isTargetDarwin()) {
211 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
212 setUseUnderscoreSetJmp(false);
213 setUseUnderscoreLongJmp(false);
214 } else if (Subtarget->isTargetMingw()) {
215 // MS runtime is weird: it exports _setjmp, but longjmp!
216 setUseUnderscoreSetJmp(true);
217 setUseUnderscoreLongJmp(false);
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(true);
223 // Set up the register classes.
224 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
225 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
226 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
227 if (Subtarget->is64Bit())
228 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
232 // We don't accept any truncstore of integer registers.
233 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
235 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
236 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
237 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
238 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
240 // SETOEQ and SETUNE require checking two conditions.
241 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
243 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
248 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
254 if (Subtarget->is64Bit()) {
255 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
257 } else if (!UseSoftFloat) {
258 // We have an algorithm for SSE2->double, and we turn this into a
259 // 64-bit FILD followed by conditional FADD for other targets.
260 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
261 // We have an algorithm for SSE2, and we turn this into a 64-bit
262 // FILD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
272 // SSE has no i16 to fp conversion, only i32
273 if (X86ScalarSSEf32) {
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
275 // f32 and f64 cases are Legal, f80 case is not
276 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
286 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
287 // are Legal, f80 is custom lowered.
288 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
289 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
291 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
293 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
294 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
296 if (X86ScalarSSEf32) {
297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
298 // f32 and f64 cases are Legal, f80 case is not
299 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
305 // Handle FP_TO_UINT by promoting the destination to a larger signed
307 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
311 if (Subtarget->is64Bit()) {
312 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
313 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
314 } else if (!UseSoftFloat) {
315 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
327 if (!X86ScalarSSEf64) {
328 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
329 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
330 if (Subtarget->is64Bit()) {
331 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
332 // Without SSE, i64->f64 goes through memory.
333 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
337 // Scalar integer divide and remainder are lowered to use operations that
338 // produce two results, to match the available instructions. This exposes
339 // the two-result form to trivial CSE, which is able to combine x/y and x%y
340 // into a single instruction.
342 // Scalar integer multiply-high is also lowered to use two-result
343 // operations, to match the available instructions. However, plain multiply
344 // (low) operations are left as Legal, as there are single-result
345 // instructions for this in x86. Using the two-result multiply instructions
346 // when both high and low results are needed must be arranged by dagcombine.
347 for (unsigned i = 0, e = 4; i != e; ++i) {
349 setOperationAction(ISD::MULHS, VT, Expand);
350 setOperationAction(ISD::MULHU, VT, Expand);
351 setOperationAction(ISD::SDIV, VT, Expand);
352 setOperationAction(ISD::UDIV, VT, Expand);
353 setOperationAction(ISD::SREM, VT, Expand);
354 setOperationAction(ISD::UREM, VT, Expand);
356 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
357 setOperationAction(ISD::ADDC, VT, Custom);
358 setOperationAction(ISD::ADDE, VT, Custom);
359 setOperationAction(ISD::SUBC, VT, Custom);
360 setOperationAction(ISD::SUBE, VT, Custom);
363 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
364 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
365 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
366 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
367 if (Subtarget->is64Bit())
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
372 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
373 setOperationAction(ISD::FREM , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f64 , Expand);
375 setOperationAction(ISD::FREM , MVT::f80 , Expand);
376 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
378 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
379 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
380 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
381 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
382 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
383 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
384 if (Subtarget->is64Bit()) {
385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
386 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
400 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
402 // These should be promoted to a larger select which is supported.
403 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
404 // X86 wants to expand cmov itself.
405 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
406 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
407 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
409 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
412 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
415 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
421 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
425 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
426 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
427 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
430 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
431 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
432 if (Subtarget->is64Bit()) {
433 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
434 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
435 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
436 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
437 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
439 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
440 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
441 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
442 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
443 if (Subtarget->is64Bit()) {
444 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
449 if (Subtarget->hasXMM())
450 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
452 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
453 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
455 // On X86 and X86-64, atomic operations are lowered to locked instructions.
456 // Locked instructions, in turn, have implicit fence semantics (all memory
457 // operations are flushed before issuing the locked instruction, and they
458 // are not buffered), so we can fold away the common pattern of
459 // fence-atomic-fence.
460 setShouldFoldAtomicFences(true);
462 // Expand certain atomics
463 for (unsigned i = 0, e = 4; i != e; ++i) {
465 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
466 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
467 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
470 if (!Subtarget->is64Bit()) {
471 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
472 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
473 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
474 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
477 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
478 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
481 if (Subtarget->hasCmpxchg16b()) {
482 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
485 // FIXME - use subtarget debug flags
486 if (!Subtarget->isTargetDarwin() &&
487 !Subtarget->isTargetELF() &&
488 !Subtarget->isTargetCygMing()) {
489 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
492 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
493 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
494 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
495 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
496 if (Subtarget->is64Bit()) {
497 setExceptionPointerRegister(X86::RAX);
498 setExceptionSelectorRegister(X86::RDX);
500 setExceptionPointerRegister(X86::EAX);
501 setExceptionSelectorRegister(X86::EDX);
503 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
504 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
506 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
508 setOperationAction(ISD::TRAP, MVT::Other, Legal);
510 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
511 setOperationAction(ISD::VASTART , MVT::Other, Custom);
512 setOperationAction(ISD::VAEND , MVT::Other, Expand);
513 if (Subtarget->is64Bit()) {
514 setOperationAction(ISD::VAARG , MVT::Other, Custom);
515 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
517 setOperationAction(ISD::VAARG , MVT::Other, Expand);
518 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
521 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
522 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
523 setOperationAction(ISD::DYNAMIC_STACKALLOC,
524 (Subtarget->is64Bit() ? MVT::i64 : MVT::i32),
525 (Subtarget->isTargetCOFF()
526 && !Subtarget->isTargetEnvMacho()
529 if (!UseSoftFloat && X86ScalarSSEf64) {
530 // f32 and f64 use SSE.
531 // Set up the FP register classes.
532 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
533 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
535 // Use ANDPD to simulate FABS.
536 setOperationAction(ISD::FABS , MVT::f64, Custom);
537 setOperationAction(ISD::FABS , MVT::f32, Custom);
539 // Use XORP to simulate FNEG.
540 setOperationAction(ISD::FNEG , MVT::f64, Custom);
541 setOperationAction(ISD::FNEG , MVT::f32, Custom);
543 // Use ANDPD and ORPD to simulate FCOPYSIGN.
544 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
545 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
547 // Lower this to FGETSIGNx86 plus an AND.
548 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
549 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
551 // We don't support sin/cos/fmod
552 setOperationAction(ISD::FSIN , MVT::f64, Expand);
553 setOperationAction(ISD::FCOS , MVT::f64, Expand);
554 setOperationAction(ISD::FSIN , MVT::f32, Expand);
555 setOperationAction(ISD::FCOS , MVT::f32, Expand);
557 // Expand FP immediates into loads from the stack, except for the special
559 addLegalFPImmediate(APFloat(+0.0)); // xorpd
560 addLegalFPImmediate(APFloat(+0.0f)); // xorps
561 } else if (!UseSoftFloat && X86ScalarSSEf32) {
562 // Use SSE for f32, x87 for f64.
563 // Set up the FP register classes.
564 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
565 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
567 // Use ANDPS to simulate FABS.
568 setOperationAction(ISD::FABS , MVT::f32, Custom);
570 // Use XORP to simulate FNEG.
571 setOperationAction(ISD::FNEG , MVT::f32, Custom);
573 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
575 // Use ANDPS and ORPS to simulate FCOPYSIGN.
576 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
577 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
579 // We don't support sin/cos/fmod
580 setOperationAction(ISD::FSIN , MVT::f32, Expand);
581 setOperationAction(ISD::FCOS , MVT::f32, Expand);
583 // Special cases we handle for FP constants.
584 addLegalFPImmediate(APFloat(+0.0f)); // xorps
585 addLegalFPImmediate(APFloat(+0.0)); // FLD0
586 addLegalFPImmediate(APFloat(+1.0)); // FLD1
587 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
588 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
591 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
592 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
594 } else if (!UseSoftFloat) {
595 // f32 and f64 in x87.
596 // Set up the FP register classes.
597 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
598 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
600 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
601 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
602 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
603 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
606 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
607 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
609 addLegalFPImmediate(APFloat(+0.0)); // FLD0
610 addLegalFPImmediate(APFloat(+1.0)); // FLD1
611 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
612 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
613 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
614 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
615 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
616 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
619 // We don't support FMA.
620 setOperationAction(ISD::FMA, MVT::f64, Expand);
621 setOperationAction(ISD::FMA, MVT::f32, Expand);
623 // Long double always uses X87.
625 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
626 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
627 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
629 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
630 addLegalFPImmediate(TmpFlt); // FLD0
632 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
635 APFloat TmpFlt2(+1.0);
636 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
638 addLegalFPImmediate(TmpFlt2); // FLD1
639 TmpFlt2.changeSign();
640 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
644 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
645 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
648 setOperationAction(ISD::FMA, MVT::f80, Expand);
651 // Always use a library call for pow.
652 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
653 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
656 setOperationAction(ISD::FLOG, MVT::f80, Expand);
657 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
659 setOperationAction(ISD::FEXP, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
662 // First set operation action for all vector types to either promote
663 // (for widening) or expand (for scalarization). Then we will selectively
664 // turn on ones that can be effectively codegen'd.
665 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
666 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
667 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
668 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
669 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
670 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
671 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
672 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
673 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
674 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
675 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
676 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
677 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
678 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
679 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
680 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
681 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
682 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
683 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
684 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
685 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
686 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
687 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
688 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
690 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
691 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
692 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
693 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
694 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
717 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
721 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
722 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
723 setTruncStoreAction((MVT::SimpleValueType)VT,
724 (MVT::SimpleValueType)InnerVT, Expand);
725 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
726 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
727 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
730 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
731 // with -msoft-float, disable use of MMX as well.
732 if (!UseSoftFloat && Subtarget->hasMMX()) {
733 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
734 // No operations on x86mmx supported, everything uses intrinsics.
737 // MMX-sized vectors (other than x86mmx) are expected to be expanded
738 // into smaller operations.
739 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
740 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
741 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
742 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
743 setOperationAction(ISD::AND, MVT::v8i8, Expand);
744 setOperationAction(ISD::AND, MVT::v4i16, Expand);
745 setOperationAction(ISD::AND, MVT::v2i32, Expand);
746 setOperationAction(ISD::AND, MVT::v1i64, Expand);
747 setOperationAction(ISD::OR, MVT::v8i8, Expand);
748 setOperationAction(ISD::OR, MVT::v4i16, Expand);
749 setOperationAction(ISD::OR, MVT::v2i32, Expand);
750 setOperationAction(ISD::OR, MVT::v1i64, Expand);
751 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
752 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
753 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
754 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
755 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
756 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
757 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
758 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
759 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
760 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
761 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
762 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
763 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
764 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
765 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
766 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
767 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
769 if (!UseSoftFloat && Subtarget->hasXMM()) {
770 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
772 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
773 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
774 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
775 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
776 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
777 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
778 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
779 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
780 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
781 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
782 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
783 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
786 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
787 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
789 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
790 // registers cannot be used even for integer operations.
791 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
792 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
793 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
794 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
796 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
797 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
798 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
799 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
800 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
801 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
802 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
803 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
804 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
805 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
806 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
807 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
808 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
809 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
810 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
811 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
813 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
814 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
815 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
816 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
818 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
819 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
820 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
821 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
824 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
825 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
826 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
827 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
828 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
830 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
831 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
832 EVT VT = (MVT::SimpleValueType)i;
833 // Do not attempt to custom lower non-power-of-2 vectors
834 if (!isPowerOf2_32(VT.getVectorNumElements()))
836 // Do not attempt to custom lower non-128-bit vectors
837 if (!VT.is128BitVector())
839 setOperationAction(ISD::BUILD_VECTOR,
840 VT.getSimpleVT().SimpleTy, Custom);
841 setOperationAction(ISD::VECTOR_SHUFFLE,
842 VT.getSimpleVT().SimpleTy, Custom);
843 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
844 VT.getSimpleVT().SimpleTy, Custom);
847 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
848 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
849 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
850 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
851 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
852 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
854 if (Subtarget->is64Bit()) {
855 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
856 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
859 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
860 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
861 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
864 // Do not attempt to promote non-128-bit vectors
865 if (!VT.is128BitVector())
868 setOperationAction(ISD::AND, SVT, Promote);
869 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
870 setOperationAction(ISD::OR, SVT, Promote);
871 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
872 setOperationAction(ISD::XOR, SVT, Promote);
873 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
874 setOperationAction(ISD::LOAD, SVT, Promote);
875 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
876 setOperationAction(ISD::SELECT, SVT, Promote);
877 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
880 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
882 // Custom lower v2i64 and v2f64 selects.
883 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
884 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
885 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
886 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
888 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
889 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
892 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
893 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
894 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
895 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
896 setOperationAction(ISD::FRINT, MVT::f32, Legal);
897 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
898 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
899 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
900 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
901 setOperationAction(ISD::FRINT, MVT::f64, Legal);
902 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
904 // FIXME: Do we need to handle scalar-to-vector here?
905 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
907 // Can turn SHL into an integer multiply.
908 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
909 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
911 // i8 and i16 vectors are custom , because the source register and source
912 // source memory operand types are not the same width. f32 vectors are
913 // custom since the immediate controlling the insert encodes additional
915 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
916 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
917 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
920 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
921 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
922 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
925 if (Subtarget->is64Bit()) {
926 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
927 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
931 if (Subtarget->hasSSE2() || Subtarget->hasAVX()) {
932 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
933 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
934 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
935 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
937 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
938 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
939 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
941 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
942 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
945 if (Subtarget->hasSSE42() || Subtarget->hasAVX())
946 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
948 if (!UseSoftFloat && Subtarget->hasAVX()) {
949 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
950 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
951 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
952 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
953 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
954 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
956 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
957 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
958 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
960 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
961 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
962 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
963 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
964 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
965 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
967 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
968 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
969 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
970 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
971 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
972 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
974 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
975 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
976 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
978 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
979 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
980 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
981 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
982 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
983 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
985 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
986 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
987 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
988 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
990 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
991 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
992 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
993 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
995 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
996 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
998 setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
999 setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
1000 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
1001 setOperationAction(ISD::VSETCC, MVT::v4i64, Custom);
1003 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1004 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1005 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1007 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1008 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1009 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1010 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1012 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1013 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1014 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1015 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1017 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1018 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1019 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1020 // Don't lower v32i8 because there is no 128-bit byte mul
1022 // Custom lower several nodes for 256-bit types.
1023 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1024 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1025 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1028 // Extract subvector is special because the value type
1029 // (result) is 128-bit but the source is 256-bit wide.
1030 if (VT.is128BitVector())
1031 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1033 // Do not attempt to custom lower other non-256-bit vectors
1034 if (!VT.is256BitVector())
1037 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1038 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1041 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1042 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1045 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1046 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1047 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1050 // Do not attempt to promote non-256-bit vectors
1051 if (!VT.is256BitVector())
1054 setOperationAction(ISD::AND, SVT, Promote);
1055 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1056 setOperationAction(ISD::OR, SVT, Promote);
1057 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1058 setOperationAction(ISD::XOR, SVT, Promote);
1059 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1060 setOperationAction(ISD::LOAD, SVT, Promote);
1061 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1062 setOperationAction(ISD::SELECT, SVT, Promote);
1063 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1067 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1068 // of this type with custom code.
1069 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1070 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1071 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1074 // We want to custom lower some of our intrinsics.
1075 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1078 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1079 // handle type legalization for these operations here.
1081 // FIXME: We really should do custom legalization for addition and
1082 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1083 // than generic legalization for 64-bit multiplication-with-overflow, though.
1084 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1085 // Add/Sub/Mul with overflow operations are custom lowered.
1087 setOperationAction(ISD::SADDO, VT, Custom);
1088 setOperationAction(ISD::UADDO, VT, Custom);
1089 setOperationAction(ISD::SSUBO, VT, Custom);
1090 setOperationAction(ISD::USUBO, VT, Custom);
1091 setOperationAction(ISD::SMULO, VT, Custom);
1092 setOperationAction(ISD::UMULO, VT, Custom);
1095 // There are no 8-bit 3-address imul/mul instructions
1096 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1097 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1099 if (!Subtarget->is64Bit()) {
1100 // These libcalls are not available in 32-bit.
1101 setLibcallName(RTLIB::SHL_I128, 0);
1102 setLibcallName(RTLIB::SRL_I128, 0);
1103 setLibcallName(RTLIB::SRA_I128, 0);
1106 // We have target-specific dag combine patterns for the following nodes:
1107 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1108 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1109 setTargetDAGCombine(ISD::BUILD_VECTOR);
1110 setTargetDAGCombine(ISD::SELECT);
1111 setTargetDAGCombine(ISD::SHL);
1112 setTargetDAGCombine(ISD::SRA);
1113 setTargetDAGCombine(ISD::SRL);
1114 setTargetDAGCombine(ISD::OR);
1115 setTargetDAGCombine(ISD::AND);
1116 setTargetDAGCombine(ISD::ADD);
1117 setTargetDAGCombine(ISD::SUB);
1118 setTargetDAGCombine(ISD::STORE);
1119 setTargetDAGCombine(ISD::ZERO_EXTEND);
1120 setTargetDAGCombine(ISD::SINT_TO_FP);
1121 if (Subtarget->is64Bit())
1122 setTargetDAGCombine(ISD::MUL);
1124 computeRegisterProperties();
1126 // On Darwin, -Os means optimize for size without hurting performance,
1127 // do not reduce the limit.
1128 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1129 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1130 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1131 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1132 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1133 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1134 setPrefLoopAlignment(16);
1135 benefitFromCodePlacementOpt = true;
1137 setPrefFunctionAlignment(4);
1141 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1146 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1147 /// the desired ByVal argument alignment.
1148 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1151 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1152 if (VTy->getBitWidth() == 128)
1154 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1155 unsigned EltAlign = 0;
1156 getMaxByValAlign(ATy->getElementType(), EltAlign);
1157 if (EltAlign > MaxAlign)
1158 MaxAlign = EltAlign;
1159 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1160 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1161 unsigned EltAlign = 0;
1162 getMaxByValAlign(STy->getElementType(i), EltAlign);
1163 if (EltAlign > MaxAlign)
1164 MaxAlign = EltAlign;
1172 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1173 /// function arguments in the caller parameter area. For X86, aggregates
1174 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1175 /// are at 4-byte boundaries.
1176 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1177 if (Subtarget->is64Bit()) {
1178 // Max of 8 and alignment of type.
1179 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1186 if (Subtarget->hasXMM())
1187 getMaxByValAlign(Ty, Align);
1191 /// getOptimalMemOpType - Returns the target specific optimal type for load
1192 /// and store operations as a result of memset, memcpy, and memmove
1193 /// lowering. If DstAlign is zero that means it's safe to destination
1194 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1195 /// means there isn't a need to check it against alignment requirement,
1196 /// probably because the source does not need to be loaded. If
1197 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1198 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1199 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1200 /// constant so it does not need to be loaded.
1201 /// It returns EVT::Other if the type should be determined using generic
1202 /// target-independent logic.
1204 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1205 unsigned DstAlign, unsigned SrcAlign,
1206 bool NonScalarIntSafe,
1208 MachineFunction &MF) const {
1209 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1210 // linux. This is because the stack realignment code can't handle certain
1211 // cases like PR2962. This should be removed when PR2962 is fixed.
1212 const Function *F = MF.getFunction();
1213 if (NonScalarIntSafe &&
1214 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1216 (Subtarget->isUnalignedMemAccessFast() ||
1217 ((DstAlign == 0 || DstAlign >= 16) &&
1218 (SrcAlign == 0 || SrcAlign >= 16))) &&
1219 Subtarget->getStackAlignment() >= 16) {
1220 if (Subtarget->hasSSE2())
1222 if (Subtarget->hasSSE1())
1224 } else if (!MemcpyStrSrc && Size >= 8 &&
1225 !Subtarget->is64Bit() &&
1226 Subtarget->getStackAlignment() >= 8 &&
1227 Subtarget->hasXMMInt()) {
1228 // Do not use f64 to lower memcpy if source is string constant. It's
1229 // better to use i32 to avoid the loads.
1233 if (Subtarget->is64Bit() && Size >= 8)
1238 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1239 /// current function. The returned value is a member of the
1240 /// MachineJumpTableInfo::JTEntryKind enum.
1241 unsigned X86TargetLowering::getJumpTableEncoding() const {
1242 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1244 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1245 Subtarget->isPICStyleGOT())
1246 return MachineJumpTableInfo::EK_Custom32;
1248 // Otherwise, use the normal jump table encoding heuristics.
1249 return TargetLowering::getJumpTableEncoding();
1253 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1254 const MachineBasicBlock *MBB,
1255 unsigned uid,MCContext &Ctx) const{
1256 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1257 Subtarget->isPICStyleGOT());
1258 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1260 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1261 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1264 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1266 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1267 SelectionDAG &DAG) const {
1268 if (!Subtarget->is64Bit())
1269 // This doesn't have DebugLoc associated with it, but is not really the
1270 // same as a Register.
1271 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1275 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1276 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1278 const MCExpr *X86TargetLowering::
1279 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1280 MCContext &Ctx) const {
1281 // X86-64 uses RIP relative addressing based on the jump table label.
1282 if (Subtarget->isPICStyleRIPRel())
1283 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1285 // Otherwise, the reference is relative to the PIC base.
1286 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1289 // FIXME: Why this routine is here? Move to RegInfo!
1290 std::pair<const TargetRegisterClass*, uint8_t>
1291 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1292 const TargetRegisterClass *RRC = 0;
1294 switch (VT.getSimpleVT().SimpleTy) {
1296 return TargetLowering::findRepresentativeClass(VT);
1297 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1298 RRC = (Subtarget->is64Bit()
1299 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1302 RRC = X86::VR64RegisterClass;
1304 case MVT::f32: case MVT::f64:
1305 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1306 case MVT::v4f32: case MVT::v2f64:
1307 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1309 RRC = X86::VR128RegisterClass;
1312 return std::make_pair(RRC, Cost);
1315 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1316 unsigned &Offset) const {
1317 if (!Subtarget->isTargetLinux())
1320 if (Subtarget->is64Bit()) {
1321 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1323 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1336 //===----------------------------------------------------------------------===//
1337 // Return Value Calling Convention Implementation
1338 //===----------------------------------------------------------------------===//
1340 #include "X86GenCallingConv.inc"
1343 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1344 MachineFunction &MF, bool isVarArg,
1345 const SmallVectorImpl<ISD::OutputArg> &Outs,
1346 LLVMContext &Context) const {
1347 SmallVector<CCValAssign, 16> RVLocs;
1348 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1350 return CCInfo.CheckReturn(Outs, RetCC_X86);
1354 X86TargetLowering::LowerReturn(SDValue Chain,
1355 CallingConv::ID CallConv, bool isVarArg,
1356 const SmallVectorImpl<ISD::OutputArg> &Outs,
1357 const SmallVectorImpl<SDValue> &OutVals,
1358 DebugLoc dl, SelectionDAG &DAG) const {
1359 MachineFunction &MF = DAG.getMachineFunction();
1360 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1362 SmallVector<CCValAssign, 16> RVLocs;
1363 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1364 RVLocs, *DAG.getContext());
1365 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1367 // Add the regs to the liveout set for the function.
1368 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1369 for (unsigned i = 0; i != RVLocs.size(); ++i)
1370 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1371 MRI.addLiveOut(RVLocs[i].getLocReg());
1375 SmallVector<SDValue, 6> RetOps;
1376 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1377 // Operand #1 = Bytes To Pop
1378 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1381 // Copy the result values into the output registers.
1382 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1383 CCValAssign &VA = RVLocs[i];
1384 assert(VA.isRegLoc() && "Can only return in registers!");
1385 SDValue ValToCopy = OutVals[i];
1386 EVT ValVT = ValToCopy.getValueType();
1388 // If this is x86-64, and we disabled SSE, we can't return FP values,
1389 // or SSE or MMX vectors.
1390 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1391 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1392 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1393 report_fatal_error("SSE register return with SSE disabled");
1395 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1396 // llvm-gcc has never done it right and no one has noticed, so this
1397 // should be OK for now.
1398 if (ValVT == MVT::f64 &&
1399 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1400 report_fatal_error("SSE2 register return with SSE2 disabled");
1402 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1403 // the RET instruction and handled by the FP Stackifier.
1404 if (VA.getLocReg() == X86::ST0 ||
1405 VA.getLocReg() == X86::ST1) {
1406 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1407 // change the value to the FP stack register class.
1408 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1409 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1410 RetOps.push_back(ValToCopy);
1411 // Don't emit a copytoreg.
1415 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1416 // which is returned in RAX / RDX.
1417 if (Subtarget->is64Bit()) {
1418 if (ValVT == MVT::x86mmx) {
1419 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1420 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1421 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1423 // If we don't have SSE2 available, convert to v4f32 so the generated
1424 // register is legal.
1425 if (!Subtarget->hasSSE2())
1426 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1431 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1432 Flag = Chain.getValue(1);
1435 // The x86-64 ABI for returning structs by value requires that we copy
1436 // the sret argument into %rax for the return. We saved the argument into
1437 // a virtual register in the entry block, so now we copy the value out
1439 if (Subtarget->is64Bit() &&
1440 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1441 MachineFunction &MF = DAG.getMachineFunction();
1442 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1443 unsigned Reg = FuncInfo->getSRetReturnReg();
1445 "SRetReturnReg should have been set in LowerFormalArguments().");
1446 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1448 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1449 Flag = Chain.getValue(1);
1451 // RAX now acts like a return value.
1452 MRI.addLiveOut(X86::RAX);
1455 RetOps[0] = Chain; // Update chain.
1457 // Add the flag if we have it.
1459 RetOps.push_back(Flag);
1461 return DAG.getNode(X86ISD::RET_FLAG, dl,
1462 MVT::Other, &RetOps[0], RetOps.size());
1465 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1466 if (N->getNumValues() != 1)
1468 if (!N->hasNUsesOfValue(1, 0))
1471 SDNode *Copy = *N->use_begin();
1472 if (Copy->getOpcode() != ISD::CopyToReg &&
1473 Copy->getOpcode() != ISD::FP_EXTEND)
1476 bool HasRet = false;
1477 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1479 if (UI->getOpcode() != X86ISD::RET_FLAG)
1488 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1489 ISD::NodeType ExtendKind) const {
1491 // TODO: Is this also valid on 32-bit?
1492 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1493 ReturnMVT = MVT::i8;
1495 ReturnMVT = MVT::i32;
1497 EVT MinVT = getRegisterType(Context, ReturnMVT);
1498 return VT.bitsLT(MinVT) ? MinVT : VT;
1501 /// LowerCallResult - Lower the result values of a call into the
1502 /// appropriate copies out of appropriate physical registers.
1505 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1506 CallingConv::ID CallConv, bool isVarArg,
1507 const SmallVectorImpl<ISD::InputArg> &Ins,
1508 DebugLoc dl, SelectionDAG &DAG,
1509 SmallVectorImpl<SDValue> &InVals) const {
1511 // Assign locations to each value returned by this call.
1512 SmallVector<CCValAssign, 16> RVLocs;
1513 bool Is64Bit = Subtarget->is64Bit();
1514 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1515 getTargetMachine(), RVLocs, *DAG.getContext());
1516 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1518 // Copy all of the result registers out of their specified physreg.
1519 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1520 CCValAssign &VA = RVLocs[i];
1521 EVT CopyVT = VA.getValVT();
1523 // If this is x86-64, and we disabled SSE, we can't return FP values
1524 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1525 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1526 report_fatal_error("SSE register return with SSE disabled");
1531 // If this is a call to a function that returns an fp value on the floating
1532 // point stack, we must guarantee the the value is popped from the stack, so
1533 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1534 // if the return value is not used. We use the FpPOP_RETVAL instruction
1536 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1537 // If we prefer to use the value in xmm registers, copy it out as f80 and
1538 // use a truncate to move it from fp stack reg to xmm reg.
1539 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1540 SDValue Ops[] = { Chain, InFlag };
1541 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1542 MVT::Other, MVT::Glue, Ops, 2), 1);
1543 Val = Chain.getValue(0);
1545 // Round the f80 to the right size, which also moves it to the appropriate
1547 if (CopyVT != VA.getValVT())
1548 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1549 // This truncation won't change the value.
1550 DAG.getIntPtrConstant(1));
1552 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1553 CopyVT, InFlag).getValue(1);
1554 Val = Chain.getValue(0);
1556 InFlag = Chain.getValue(2);
1557 InVals.push_back(Val);
1564 //===----------------------------------------------------------------------===//
1565 // C & StdCall & Fast Calling Convention implementation
1566 //===----------------------------------------------------------------------===//
1567 // StdCall calling convention seems to be standard for many Windows' API
1568 // routines and around. It differs from C calling convention just a little:
1569 // callee should clean up the stack, not caller. Symbols should be also
1570 // decorated in some fancy way :) It doesn't support any vector arguments.
1571 // For info on fast calling convention see Fast Calling Convention (tail call)
1572 // implementation LowerX86_32FastCCCallTo.
1574 /// CallIsStructReturn - Determines whether a call uses struct return
1576 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1580 return Outs[0].Flags.isSRet();
1583 /// ArgsAreStructReturn - Determines whether a function uses struct
1584 /// return semantics.
1586 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1590 return Ins[0].Flags.isSRet();
1593 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1594 /// by "Src" to address "Dst" with size and alignment information specified by
1595 /// the specific parameter attribute. The copy will be passed as a byval
1596 /// function parameter.
1598 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1599 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1601 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1603 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1604 /*isVolatile*/false, /*AlwaysInline=*/true,
1605 MachinePointerInfo(), MachinePointerInfo());
1608 /// IsTailCallConvention - Return true if the calling convention is one that
1609 /// supports tail call optimization.
1610 static bool IsTailCallConvention(CallingConv::ID CC) {
1611 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1614 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1615 if (!CI->isTailCall())
1619 CallingConv::ID CalleeCC = CS.getCallingConv();
1620 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1626 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1627 /// a tailcall target by changing its ABI.
1628 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1629 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1633 X86TargetLowering::LowerMemArgument(SDValue Chain,
1634 CallingConv::ID CallConv,
1635 const SmallVectorImpl<ISD::InputArg> &Ins,
1636 DebugLoc dl, SelectionDAG &DAG,
1637 const CCValAssign &VA,
1638 MachineFrameInfo *MFI,
1640 // Create the nodes corresponding to a load from this parameter slot.
1641 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1642 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1643 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1646 // If value is passed by pointer we have address passed instead of the value
1648 if (VA.getLocInfo() == CCValAssign::Indirect)
1649 ValVT = VA.getLocVT();
1651 ValVT = VA.getValVT();
1653 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1654 // changed with more analysis.
1655 // In case of tail call optimization mark all arguments mutable. Since they
1656 // could be overwritten by lowering of arguments in case of a tail call.
1657 if (Flags.isByVal()) {
1658 unsigned Bytes = Flags.getByValSize();
1659 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1660 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1661 return DAG.getFrameIndex(FI, getPointerTy());
1663 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1664 VA.getLocMemOffset(), isImmutable);
1665 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1666 return DAG.getLoad(ValVT, dl, Chain, FIN,
1667 MachinePointerInfo::getFixedStack(FI),
1673 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1674 CallingConv::ID CallConv,
1676 const SmallVectorImpl<ISD::InputArg> &Ins,
1679 SmallVectorImpl<SDValue> &InVals)
1681 MachineFunction &MF = DAG.getMachineFunction();
1682 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1684 const Function* Fn = MF.getFunction();
1685 if (Fn->hasExternalLinkage() &&
1686 Subtarget->isTargetCygMing() &&
1687 Fn->getName() == "main")
1688 FuncInfo->setForceFramePointer(true);
1690 MachineFrameInfo *MFI = MF.getFrameInfo();
1691 bool Is64Bit = Subtarget->is64Bit();
1692 bool IsWin64 = Subtarget->isTargetWin64();
1694 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1695 "Var args not supported with calling convention fastcc or ghc");
1697 // Assign locations to all of the incoming arguments.
1698 SmallVector<CCValAssign, 16> ArgLocs;
1699 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1700 ArgLocs, *DAG.getContext());
1702 // Allocate shadow area for Win64
1704 CCInfo.AllocateStack(32, 8);
1707 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1709 unsigned LastVal = ~0U;
1711 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1712 CCValAssign &VA = ArgLocs[i];
1713 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1715 assert(VA.getValNo() != LastVal &&
1716 "Don't support value assigned to multiple locs yet");
1717 LastVal = VA.getValNo();
1719 if (VA.isRegLoc()) {
1720 EVT RegVT = VA.getLocVT();
1721 TargetRegisterClass *RC = NULL;
1722 if (RegVT == MVT::i32)
1723 RC = X86::GR32RegisterClass;
1724 else if (Is64Bit && RegVT == MVT::i64)
1725 RC = X86::GR64RegisterClass;
1726 else if (RegVT == MVT::f32)
1727 RC = X86::FR32RegisterClass;
1728 else if (RegVT == MVT::f64)
1729 RC = X86::FR64RegisterClass;
1730 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1731 RC = X86::VR256RegisterClass;
1732 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1733 RC = X86::VR128RegisterClass;
1734 else if (RegVT == MVT::x86mmx)
1735 RC = X86::VR64RegisterClass;
1737 llvm_unreachable("Unknown argument type!");
1739 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1740 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1742 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1743 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1745 if (VA.getLocInfo() == CCValAssign::SExt)
1746 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1747 DAG.getValueType(VA.getValVT()));
1748 else if (VA.getLocInfo() == CCValAssign::ZExt)
1749 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1750 DAG.getValueType(VA.getValVT()));
1751 else if (VA.getLocInfo() == CCValAssign::BCvt)
1752 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1754 if (VA.isExtInLoc()) {
1755 // Handle MMX values passed in XMM regs.
1756 if (RegVT.isVector()) {
1757 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1760 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1763 assert(VA.isMemLoc());
1764 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1767 // If value is passed via pointer - do a load.
1768 if (VA.getLocInfo() == CCValAssign::Indirect)
1769 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1770 MachinePointerInfo(), false, false, 0);
1772 InVals.push_back(ArgValue);
1775 // The x86-64 ABI for returning structs by value requires that we copy
1776 // the sret argument into %rax for the return. Save the argument into
1777 // a virtual register so that we can access it from the return points.
1778 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1779 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1780 unsigned Reg = FuncInfo->getSRetReturnReg();
1782 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1783 FuncInfo->setSRetReturnReg(Reg);
1785 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1786 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1789 unsigned StackSize = CCInfo.getNextStackOffset();
1790 // Align stack specially for tail calls.
1791 if (FuncIsMadeTailCallSafe(CallConv))
1792 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1794 // If the function takes variable number of arguments, make a frame index for
1795 // the start of the first vararg value... for expansion of llvm.va_start.
1797 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1798 CallConv != CallingConv::X86_ThisCall)) {
1799 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1802 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1804 // FIXME: We should really autogenerate these arrays
1805 static const unsigned GPR64ArgRegsWin64[] = {
1806 X86::RCX, X86::RDX, X86::R8, X86::R9
1808 static const unsigned GPR64ArgRegs64Bit[] = {
1809 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1811 static const unsigned XMMArgRegs64Bit[] = {
1812 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1813 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1815 const unsigned *GPR64ArgRegs;
1816 unsigned NumXMMRegs = 0;
1819 // The XMM registers which might contain var arg parameters are shadowed
1820 // in their paired GPR. So we only need to save the GPR to their home
1822 TotalNumIntRegs = 4;
1823 GPR64ArgRegs = GPR64ArgRegsWin64;
1825 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1826 GPR64ArgRegs = GPR64ArgRegs64Bit;
1828 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1830 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1833 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1834 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1835 "SSE register cannot be used when SSE is disabled!");
1836 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1837 "SSE register cannot be used when SSE is disabled!");
1838 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1839 // Kernel mode asks for SSE to be disabled, so don't push them
1841 TotalNumXMMRegs = 0;
1844 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1845 // Get to the caller-allocated home save location. Add 8 to account
1846 // for the return address.
1847 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1848 FuncInfo->setRegSaveFrameIndex(
1849 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1850 // Fixup to set vararg frame on shadow area (4 x i64).
1852 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1854 // For X86-64, if there are vararg parameters that are passed via
1855 // registers, then we must store them to their spots on the stack so they
1856 // may be loaded by deferencing the result of va_next.
1857 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1858 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1859 FuncInfo->setRegSaveFrameIndex(
1860 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1864 // Store the integer parameter registers.
1865 SmallVector<SDValue, 8> MemOps;
1866 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1868 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1869 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1870 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1871 DAG.getIntPtrConstant(Offset));
1872 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1873 X86::GR64RegisterClass);
1874 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1876 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1877 MachinePointerInfo::getFixedStack(
1878 FuncInfo->getRegSaveFrameIndex(), Offset),
1880 MemOps.push_back(Store);
1884 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1885 // Now store the XMM (fp + vector) parameter registers.
1886 SmallVector<SDValue, 11> SaveXMMOps;
1887 SaveXMMOps.push_back(Chain);
1889 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1890 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1891 SaveXMMOps.push_back(ALVal);
1893 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1894 FuncInfo->getRegSaveFrameIndex()));
1895 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1896 FuncInfo->getVarArgsFPOffset()));
1898 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1899 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1900 X86::VR128RegisterClass);
1901 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1902 SaveXMMOps.push_back(Val);
1904 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1906 &SaveXMMOps[0], SaveXMMOps.size()));
1909 if (!MemOps.empty())
1910 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1911 &MemOps[0], MemOps.size());
1915 // Some CCs need callee pop.
1916 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
1917 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1919 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1920 // If this is an sret function, the return should pop the hidden pointer.
1921 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1922 FuncInfo->setBytesToPopOnReturn(4);
1926 // RegSaveFrameIndex is X86-64 only.
1927 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1928 if (CallConv == CallingConv::X86_FastCall ||
1929 CallConv == CallingConv::X86_ThisCall)
1930 // fastcc functions can't have varargs.
1931 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1934 FuncInfo->setArgumentStackSize(StackSize);
1940 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1941 SDValue StackPtr, SDValue Arg,
1942 DebugLoc dl, SelectionDAG &DAG,
1943 const CCValAssign &VA,
1944 ISD::ArgFlagsTy Flags) const {
1945 unsigned LocMemOffset = VA.getLocMemOffset();
1946 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1947 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1948 if (Flags.isByVal())
1949 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1951 return DAG.getStore(Chain, dl, Arg, PtrOff,
1952 MachinePointerInfo::getStack(LocMemOffset),
1956 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1957 /// optimization is performed and it is required.
1959 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1960 SDValue &OutRetAddr, SDValue Chain,
1961 bool IsTailCall, bool Is64Bit,
1962 int FPDiff, DebugLoc dl) const {
1963 // Adjust the Return address stack slot.
1964 EVT VT = getPointerTy();
1965 OutRetAddr = getReturnAddressFrameIndex(DAG);
1967 // Load the "old" Return address.
1968 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1970 return SDValue(OutRetAddr.getNode(), 1);
1973 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
1974 /// optimization is performed and it is required (FPDiff!=0).
1976 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1977 SDValue Chain, SDValue RetAddrFrIdx,
1978 bool Is64Bit, int FPDiff, DebugLoc dl) {
1979 // Store the return address to the appropriate stack slot.
1980 if (!FPDiff) return Chain;
1981 // Calculate the new stack slot for the return address.
1982 int SlotSize = Is64Bit ? 8 : 4;
1983 int NewReturnAddrFI =
1984 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1985 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1986 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1987 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1988 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1994 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1995 CallingConv::ID CallConv, bool isVarArg,
1997 const SmallVectorImpl<ISD::OutputArg> &Outs,
1998 const SmallVectorImpl<SDValue> &OutVals,
1999 const SmallVectorImpl<ISD::InputArg> &Ins,
2000 DebugLoc dl, SelectionDAG &DAG,
2001 SmallVectorImpl<SDValue> &InVals) const {
2002 MachineFunction &MF = DAG.getMachineFunction();
2003 bool Is64Bit = Subtarget->is64Bit();
2004 bool IsWin64 = Subtarget->isTargetWin64();
2005 bool IsStructRet = CallIsStructReturn(Outs);
2006 bool IsSibcall = false;
2009 // Check if it's really possible to do a tail call.
2010 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2011 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2012 Outs, OutVals, Ins, DAG);
2014 // Sibcalls are automatically detected tailcalls which do not require
2016 if (!GuaranteedTailCallOpt && isTailCall)
2023 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2024 "Var args not supported with calling convention fastcc or ghc");
2026 // Analyze operands of the call, assigning locations to each operand.
2027 SmallVector<CCValAssign, 16> ArgLocs;
2028 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2029 ArgLocs, *DAG.getContext());
2031 // Allocate shadow area for Win64
2033 CCInfo.AllocateStack(32, 8);
2036 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2038 // Get a count of how many bytes are to be pushed on the stack.
2039 unsigned NumBytes = CCInfo.getNextStackOffset();
2041 // This is a sibcall. The memory operands are available in caller's
2042 // own caller's stack.
2044 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2045 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2048 if (isTailCall && !IsSibcall) {
2049 // Lower arguments at fp - stackoffset + fpdiff.
2050 unsigned NumBytesCallerPushed =
2051 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2052 FPDiff = NumBytesCallerPushed - NumBytes;
2054 // Set the delta of movement of the returnaddr stackslot.
2055 // But only set if delta is greater than previous delta.
2056 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2057 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2061 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2063 SDValue RetAddrFrIdx;
2064 // Load return address for tail calls.
2065 if (isTailCall && FPDiff)
2066 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2067 Is64Bit, FPDiff, dl);
2069 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2070 SmallVector<SDValue, 8> MemOpChains;
2073 // Walk the register/memloc assignments, inserting copies/loads. In the case
2074 // of tail call optimization arguments are handle later.
2075 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2076 CCValAssign &VA = ArgLocs[i];
2077 EVT RegVT = VA.getLocVT();
2078 SDValue Arg = OutVals[i];
2079 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2080 bool isByVal = Flags.isByVal();
2082 // Promote the value if needed.
2083 switch (VA.getLocInfo()) {
2084 default: llvm_unreachable("Unknown loc info!");
2085 case CCValAssign::Full: break;
2086 case CCValAssign::SExt:
2087 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2089 case CCValAssign::ZExt:
2090 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2092 case CCValAssign::AExt:
2093 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2094 // Special case: passing MMX values in XMM registers.
2095 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2096 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2097 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2099 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2101 case CCValAssign::BCvt:
2102 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2104 case CCValAssign::Indirect: {
2105 // Store the argument.
2106 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2107 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2108 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2109 MachinePointerInfo::getFixedStack(FI),
2116 if (VA.isRegLoc()) {
2117 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2118 if (isVarArg && IsWin64) {
2119 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2120 // shadow reg if callee is a varargs function.
2121 unsigned ShadowReg = 0;
2122 switch (VA.getLocReg()) {
2123 case X86::XMM0: ShadowReg = X86::RCX; break;
2124 case X86::XMM1: ShadowReg = X86::RDX; break;
2125 case X86::XMM2: ShadowReg = X86::R8; break;
2126 case X86::XMM3: ShadowReg = X86::R9; break;
2129 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2131 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2132 assert(VA.isMemLoc());
2133 if (StackPtr.getNode() == 0)
2134 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2135 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2136 dl, DAG, VA, Flags));
2140 if (!MemOpChains.empty())
2141 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2142 &MemOpChains[0], MemOpChains.size());
2144 // Build a sequence of copy-to-reg nodes chained together with token chain
2145 // and flag operands which copy the outgoing args into registers.
2147 // Tail call byval lowering might overwrite argument registers so in case of
2148 // tail call optimization the copies to registers are lowered later.
2150 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2151 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2152 RegsToPass[i].second, InFlag);
2153 InFlag = Chain.getValue(1);
2156 if (Subtarget->isPICStyleGOT()) {
2157 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2160 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2161 DAG.getNode(X86ISD::GlobalBaseReg,
2162 DebugLoc(), getPointerTy()),
2164 InFlag = Chain.getValue(1);
2166 // If we are tail calling and generating PIC/GOT style code load the
2167 // address of the callee into ECX. The value in ecx is used as target of
2168 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2169 // for tail calls on PIC/GOT architectures. Normally we would just put the
2170 // address of GOT into ebx and then call target@PLT. But for tail calls
2171 // ebx would be restored (since ebx is callee saved) before jumping to the
2174 // Note: The actual moving to ECX is done further down.
2175 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2176 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2177 !G->getGlobal()->hasProtectedVisibility())
2178 Callee = LowerGlobalAddress(Callee, DAG);
2179 else if (isa<ExternalSymbolSDNode>(Callee))
2180 Callee = LowerExternalSymbol(Callee, DAG);
2184 if (Is64Bit && isVarArg && !IsWin64) {
2185 // From AMD64 ABI document:
2186 // For calls that may call functions that use varargs or stdargs
2187 // (prototype-less calls or calls to functions containing ellipsis (...) in
2188 // the declaration) %al is used as hidden argument to specify the number
2189 // of SSE registers used. The contents of %al do not need to match exactly
2190 // the number of registers, but must be an ubound on the number of SSE
2191 // registers used and is in the range 0 - 8 inclusive.
2193 // Count the number of XMM registers allocated.
2194 static const unsigned XMMArgRegs[] = {
2195 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2196 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2198 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2199 assert((Subtarget->hasXMM() || !NumXMMRegs)
2200 && "SSE registers cannot be used when SSE is disabled");
2202 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2203 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2204 InFlag = Chain.getValue(1);
2208 // For tail calls lower the arguments to the 'real' stack slot.
2210 // Force all the incoming stack arguments to be loaded from the stack
2211 // before any new outgoing arguments are stored to the stack, because the
2212 // outgoing stack slots may alias the incoming argument stack slots, and
2213 // the alias isn't otherwise explicit. This is slightly more conservative
2214 // than necessary, because it means that each store effectively depends
2215 // on every argument instead of just those arguments it would clobber.
2216 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2218 SmallVector<SDValue, 8> MemOpChains2;
2221 // Do not flag preceding copytoreg stuff together with the following stuff.
2223 if (GuaranteedTailCallOpt) {
2224 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2225 CCValAssign &VA = ArgLocs[i];
2228 assert(VA.isMemLoc());
2229 SDValue Arg = OutVals[i];
2230 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2231 // Create frame index.
2232 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2233 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2234 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2235 FIN = DAG.getFrameIndex(FI, getPointerTy());
2237 if (Flags.isByVal()) {
2238 // Copy relative to framepointer.
2239 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2240 if (StackPtr.getNode() == 0)
2241 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2243 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2245 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2249 // Store relative to framepointer.
2250 MemOpChains2.push_back(
2251 DAG.getStore(ArgChain, dl, Arg, FIN,
2252 MachinePointerInfo::getFixedStack(FI),
2258 if (!MemOpChains2.empty())
2259 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2260 &MemOpChains2[0], MemOpChains2.size());
2262 // Copy arguments to their registers.
2263 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2264 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2265 RegsToPass[i].second, InFlag);
2266 InFlag = Chain.getValue(1);
2270 // Store the return address to the appropriate stack slot.
2271 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2275 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2276 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2277 // In the 64-bit large code model, we have to make all calls
2278 // through a register, since the call instruction's 32-bit
2279 // pc-relative offset may not be large enough to hold the whole
2281 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2282 // If the callee is a GlobalAddress node (quite common, every direct call
2283 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2286 // We should use extra load for direct calls to dllimported functions in
2288 const GlobalValue *GV = G->getGlobal();
2289 if (!GV->hasDLLImportLinkage()) {
2290 unsigned char OpFlags = 0;
2291 bool ExtraLoad = false;
2292 unsigned WrapperKind = ISD::DELETED_NODE;
2294 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2295 // external symbols most go through the PLT in PIC mode. If the symbol
2296 // has hidden or protected visibility, or if it is static or local, then
2297 // we don't need to use the PLT - we can directly call it.
2298 if (Subtarget->isTargetELF() &&
2299 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2300 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2301 OpFlags = X86II::MO_PLT;
2302 } else if (Subtarget->isPICStyleStubAny() &&
2303 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2304 (!Subtarget->getTargetTriple().isMacOSX() ||
2305 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2306 // PC-relative references to external symbols should go through $stub,
2307 // unless we're building with the leopard linker or later, which
2308 // automatically synthesizes these stubs.
2309 OpFlags = X86II::MO_DARWIN_STUB;
2310 } else if (Subtarget->isPICStyleRIPRel() &&
2311 isa<Function>(GV) &&
2312 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2313 // If the function is marked as non-lazy, generate an indirect call
2314 // which loads from the GOT directly. This avoids runtime overhead
2315 // at the cost of eager binding (and one extra byte of encoding).
2316 OpFlags = X86II::MO_GOTPCREL;
2317 WrapperKind = X86ISD::WrapperRIP;
2321 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2322 G->getOffset(), OpFlags);
2324 // Add a wrapper if needed.
2325 if (WrapperKind != ISD::DELETED_NODE)
2326 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2327 // Add extra indirection if needed.
2329 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2330 MachinePointerInfo::getGOT(),
2333 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2334 unsigned char OpFlags = 0;
2336 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2337 // external symbols should go through the PLT.
2338 if (Subtarget->isTargetELF() &&
2339 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2340 OpFlags = X86II::MO_PLT;
2341 } else if (Subtarget->isPICStyleStubAny() &&
2342 (!Subtarget->getTargetTriple().isMacOSX() ||
2343 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2344 // PC-relative references to external symbols should go through $stub,
2345 // unless we're building with the leopard linker or later, which
2346 // automatically synthesizes these stubs.
2347 OpFlags = X86II::MO_DARWIN_STUB;
2350 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2354 // Returns a chain & a flag for retval copy to use.
2355 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2356 SmallVector<SDValue, 8> Ops;
2358 if (!IsSibcall && isTailCall) {
2359 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2360 DAG.getIntPtrConstant(0, true), InFlag);
2361 InFlag = Chain.getValue(1);
2364 Ops.push_back(Chain);
2365 Ops.push_back(Callee);
2368 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2370 // Add argument registers to the end of the list so that they are known live
2372 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2373 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2374 RegsToPass[i].second.getValueType()));
2376 // Add an implicit use GOT pointer in EBX.
2377 if (!isTailCall && Subtarget->isPICStyleGOT())
2378 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2380 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2381 if (Is64Bit && isVarArg && !IsWin64)
2382 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2384 if (InFlag.getNode())
2385 Ops.push_back(InFlag);
2389 //// If this is the first return lowered for this function, add the regs
2390 //// to the liveout set for the function.
2391 // This isn't right, although it's probably harmless on x86; liveouts
2392 // should be computed from returns not tail calls. Consider a void
2393 // function making a tail call to a function returning int.
2394 return DAG.getNode(X86ISD::TC_RETURN, dl,
2395 NodeTys, &Ops[0], Ops.size());
2398 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2399 InFlag = Chain.getValue(1);
2401 // Create the CALLSEQ_END node.
2402 unsigned NumBytesForCalleeToPush;
2403 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2404 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2405 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2406 // If this is a call to a struct-return function, the callee
2407 // pops the hidden struct pointer, so we have to push it back.
2408 // This is common for Darwin/X86, Linux & Mingw32 targets.
2409 NumBytesForCalleeToPush = 4;
2411 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2413 // Returns a flag for retval copy to use.
2415 Chain = DAG.getCALLSEQ_END(Chain,
2416 DAG.getIntPtrConstant(NumBytes, true),
2417 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2420 InFlag = Chain.getValue(1);
2423 // Handle result values, copying them out of physregs into vregs that we
2425 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2426 Ins, dl, DAG, InVals);
2430 //===----------------------------------------------------------------------===//
2431 // Fast Calling Convention (tail call) implementation
2432 //===----------------------------------------------------------------------===//
2434 // Like std call, callee cleans arguments, convention except that ECX is
2435 // reserved for storing the tail called function address. Only 2 registers are
2436 // free for argument passing (inreg). Tail call optimization is performed
2438 // * tailcallopt is enabled
2439 // * caller/callee are fastcc
2440 // On X86_64 architecture with GOT-style position independent code only local
2441 // (within module) calls are supported at the moment.
2442 // To keep the stack aligned according to platform abi the function
2443 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2444 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2445 // If a tail called function callee has more arguments than the caller the
2446 // caller needs to make sure that there is room to move the RETADDR to. This is
2447 // achieved by reserving an area the size of the argument delta right after the
2448 // original REtADDR, but before the saved framepointer or the spilled registers
2449 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2461 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2462 /// for a 16 byte align requirement.
2464 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2465 SelectionDAG& DAG) const {
2466 MachineFunction &MF = DAG.getMachineFunction();
2467 const TargetMachine &TM = MF.getTarget();
2468 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2469 unsigned StackAlignment = TFI.getStackAlignment();
2470 uint64_t AlignMask = StackAlignment - 1;
2471 int64_t Offset = StackSize;
2472 uint64_t SlotSize = TD->getPointerSize();
2473 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2474 // Number smaller than 12 so just add the difference.
2475 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2477 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2478 Offset = ((~AlignMask) & Offset) + StackAlignment +
2479 (StackAlignment-SlotSize);
2484 /// MatchingStackOffset - Return true if the given stack call argument is
2485 /// already available in the same position (relatively) of the caller's
2486 /// incoming argument stack.
2488 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2489 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2490 const X86InstrInfo *TII) {
2491 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2493 if (Arg.getOpcode() == ISD::CopyFromReg) {
2494 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2495 if (!TargetRegisterInfo::isVirtualRegister(VR))
2497 MachineInstr *Def = MRI->getVRegDef(VR);
2500 if (!Flags.isByVal()) {
2501 if (!TII->isLoadFromStackSlot(Def, FI))
2504 unsigned Opcode = Def->getOpcode();
2505 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2506 Def->getOperand(1).isFI()) {
2507 FI = Def->getOperand(1).getIndex();
2508 Bytes = Flags.getByValSize();
2512 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2513 if (Flags.isByVal())
2514 // ByVal argument is passed in as a pointer but it's now being
2515 // dereferenced. e.g.
2516 // define @foo(%struct.X* %A) {
2517 // tail call @bar(%struct.X* byval %A)
2520 SDValue Ptr = Ld->getBasePtr();
2521 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2524 FI = FINode->getIndex();
2525 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2526 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2527 FI = FINode->getIndex();
2528 Bytes = Flags.getByValSize();
2532 assert(FI != INT_MAX);
2533 if (!MFI->isFixedObjectIndex(FI))
2535 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2538 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2539 /// for tail call optimization. Targets which want to do tail call
2540 /// optimization should implement this function.
2542 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2543 CallingConv::ID CalleeCC,
2545 bool isCalleeStructRet,
2546 bool isCallerStructRet,
2547 const SmallVectorImpl<ISD::OutputArg> &Outs,
2548 const SmallVectorImpl<SDValue> &OutVals,
2549 const SmallVectorImpl<ISD::InputArg> &Ins,
2550 SelectionDAG& DAG) const {
2551 if (!IsTailCallConvention(CalleeCC) &&
2552 CalleeCC != CallingConv::C)
2555 // If -tailcallopt is specified, make fastcc functions tail-callable.
2556 const MachineFunction &MF = DAG.getMachineFunction();
2557 const Function *CallerF = DAG.getMachineFunction().getFunction();
2558 CallingConv::ID CallerCC = CallerF->getCallingConv();
2559 bool CCMatch = CallerCC == CalleeCC;
2561 if (GuaranteedTailCallOpt) {
2562 if (IsTailCallConvention(CalleeCC) && CCMatch)
2567 // Look for obvious safe cases to perform tail call optimization that do not
2568 // require ABI changes. This is what gcc calls sibcall.
2570 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2571 // emit a special epilogue.
2572 if (RegInfo->needsStackRealignment(MF))
2575 // Also avoid sibcall optimization if either caller or callee uses struct
2576 // return semantics.
2577 if (isCalleeStructRet || isCallerStructRet)
2580 // An stdcall caller is expected to clean up its arguments; the callee
2581 // isn't going to do that.
2582 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2585 // Do not sibcall optimize vararg calls unless all arguments are passed via
2587 if (isVarArg && !Outs.empty()) {
2589 // Optimizing for varargs on Win64 is unlikely to be safe without
2590 // additional testing.
2591 if (Subtarget->isTargetWin64())
2594 SmallVector<CCValAssign, 16> ArgLocs;
2595 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2596 getTargetMachine(), ArgLocs, *DAG.getContext());
2598 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2599 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2600 if (!ArgLocs[i].isRegLoc())
2604 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2605 // Therefore if it's not used by the call it is not safe to optimize this into
2607 bool Unused = false;
2608 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2615 SmallVector<CCValAssign, 16> RVLocs;
2616 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2617 getTargetMachine(), RVLocs, *DAG.getContext());
2618 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2619 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2620 CCValAssign &VA = RVLocs[i];
2621 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2626 // If the calling conventions do not match, then we'd better make sure the
2627 // results are returned in the same way as what the caller expects.
2629 SmallVector<CCValAssign, 16> RVLocs1;
2630 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2631 getTargetMachine(), RVLocs1, *DAG.getContext());
2632 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2634 SmallVector<CCValAssign, 16> RVLocs2;
2635 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2636 getTargetMachine(), RVLocs2, *DAG.getContext());
2637 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2639 if (RVLocs1.size() != RVLocs2.size())
2641 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2642 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2644 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2646 if (RVLocs1[i].isRegLoc()) {
2647 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2650 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2656 // If the callee takes no arguments then go on to check the results of the
2658 if (!Outs.empty()) {
2659 // Check if stack adjustment is needed. For now, do not do this if any
2660 // argument is passed on the stack.
2661 SmallVector<CCValAssign, 16> ArgLocs;
2662 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2663 getTargetMachine(), ArgLocs, *DAG.getContext());
2665 // Allocate shadow area for Win64
2666 if (Subtarget->isTargetWin64()) {
2667 CCInfo.AllocateStack(32, 8);
2670 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2671 if (CCInfo.getNextStackOffset()) {
2672 MachineFunction &MF = DAG.getMachineFunction();
2673 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2676 // Check if the arguments are already laid out in the right way as
2677 // the caller's fixed stack objects.
2678 MachineFrameInfo *MFI = MF.getFrameInfo();
2679 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2680 const X86InstrInfo *TII =
2681 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2682 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2683 CCValAssign &VA = ArgLocs[i];
2684 SDValue Arg = OutVals[i];
2685 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2686 if (VA.getLocInfo() == CCValAssign::Indirect)
2688 if (!VA.isRegLoc()) {
2689 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2696 // If the tailcall address may be in a register, then make sure it's
2697 // possible to register allocate for it. In 32-bit, the call address can
2698 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2699 // callee-saved registers are restored. These happen to be the same
2700 // registers used to pass 'inreg' arguments so watch out for those.
2701 if (!Subtarget->is64Bit() &&
2702 !isa<GlobalAddressSDNode>(Callee) &&
2703 !isa<ExternalSymbolSDNode>(Callee)) {
2704 unsigned NumInRegs = 0;
2705 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2706 CCValAssign &VA = ArgLocs[i];
2709 unsigned Reg = VA.getLocReg();
2712 case X86::EAX: case X86::EDX: case X86::ECX:
2713 if (++NumInRegs == 3)
2725 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2726 return X86::createFastISel(funcInfo);
2730 //===----------------------------------------------------------------------===//
2731 // Other Lowering Hooks
2732 //===----------------------------------------------------------------------===//
2734 static bool MayFoldLoad(SDValue Op) {
2735 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2738 static bool MayFoldIntoStore(SDValue Op) {
2739 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2742 static bool isTargetShuffle(unsigned Opcode) {
2744 default: return false;
2745 case X86ISD::PSHUFD:
2746 case X86ISD::PSHUFHW:
2747 case X86ISD::PSHUFLW:
2748 case X86ISD::SHUFPD:
2749 case X86ISD::PALIGN:
2750 case X86ISD::SHUFPS:
2751 case X86ISD::MOVLHPS:
2752 case X86ISD::MOVLHPD:
2753 case X86ISD::MOVHLPS:
2754 case X86ISD::MOVLPS:
2755 case X86ISD::MOVLPD:
2756 case X86ISD::MOVSHDUP:
2757 case X86ISD::MOVSLDUP:
2758 case X86ISD::MOVDDUP:
2761 case X86ISD::UNPCKLPS:
2762 case X86ISD::UNPCKLPD:
2763 case X86ISD::VUNPCKLPSY:
2764 case X86ISD::VUNPCKLPDY:
2765 case X86ISD::PUNPCKLWD:
2766 case X86ISD::PUNPCKLBW:
2767 case X86ISD::PUNPCKLDQ:
2768 case X86ISD::PUNPCKLQDQ:
2769 case X86ISD::UNPCKHPS:
2770 case X86ISD::UNPCKHPD:
2771 case X86ISD::VUNPCKHPSY:
2772 case X86ISD::VUNPCKHPDY:
2773 case X86ISD::PUNPCKHWD:
2774 case X86ISD::PUNPCKHBW:
2775 case X86ISD::PUNPCKHDQ:
2776 case X86ISD::PUNPCKHQDQ:
2777 case X86ISD::VPERMILPS:
2778 case X86ISD::VPERMILPSY:
2779 case X86ISD::VPERMILPD:
2780 case X86ISD::VPERMILPDY:
2781 case X86ISD::VPERM2F128:
2787 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2788 SDValue V1, SelectionDAG &DAG) {
2790 default: llvm_unreachable("Unknown x86 shuffle node");
2791 case X86ISD::MOVSHDUP:
2792 case X86ISD::MOVSLDUP:
2793 case X86ISD::MOVDDUP:
2794 return DAG.getNode(Opc, dl, VT, V1);
2800 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2801 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2803 default: llvm_unreachable("Unknown x86 shuffle node");
2804 case X86ISD::PSHUFD:
2805 case X86ISD::PSHUFHW:
2806 case X86ISD::PSHUFLW:
2807 case X86ISD::VPERMILPS:
2808 case X86ISD::VPERMILPSY:
2809 case X86ISD::VPERMILPD:
2810 case X86ISD::VPERMILPDY:
2811 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2817 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2818 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2820 default: llvm_unreachable("Unknown x86 shuffle node");
2821 case X86ISD::PALIGN:
2822 case X86ISD::SHUFPD:
2823 case X86ISD::SHUFPS:
2824 case X86ISD::VPERM2F128:
2825 return DAG.getNode(Opc, dl, VT, V1, V2,
2826 DAG.getConstant(TargetMask, MVT::i8));
2831 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2832 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2834 default: llvm_unreachable("Unknown x86 shuffle node");
2835 case X86ISD::MOVLHPS:
2836 case X86ISD::MOVLHPD:
2837 case X86ISD::MOVHLPS:
2838 case X86ISD::MOVLPS:
2839 case X86ISD::MOVLPD:
2842 case X86ISD::UNPCKLPS:
2843 case X86ISD::UNPCKLPD:
2844 case X86ISD::VUNPCKLPSY:
2845 case X86ISD::VUNPCKLPDY:
2846 case X86ISD::PUNPCKLWD:
2847 case X86ISD::PUNPCKLBW:
2848 case X86ISD::PUNPCKLDQ:
2849 case X86ISD::PUNPCKLQDQ:
2850 case X86ISD::UNPCKHPS:
2851 case X86ISD::UNPCKHPD:
2852 case X86ISD::VUNPCKHPSY:
2853 case X86ISD::VUNPCKHPDY:
2854 case X86ISD::PUNPCKHWD:
2855 case X86ISD::PUNPCKHBW:
2856 case X86ISD::PUNPCKHDQ:
2857 case X86ISD::PUNPCKHQDQ:
2858 return DAG.getNode(Opc, dl, VT, V1, V2);
2863 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2864 MachineFunction &MF = DAG.getMachineFunction();
2865 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2866 int ReturnAddrIndex = FuncInfo->getRAIndex();
2868 if (ReturnAddrIndex == 0) {
2869 // Set up a frame object for the return address.
2870 uint64_t SlotSize = TD->getPointerSize();
2871 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2873 FuncInfo->setRAIndex(ReturnAddrIndex);
2876 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2880 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2881 bool hasSymbolicDisplacement) {
2882 // Offset should fit into 32 bit immediate field.
2883 if (!isInt<32>(Offset))
2886 // If we don't have a symbolic displacement - we don't have any extra
2888 if (!hasSymbolicDisplacement)
2891 // FIXME: Some tweaks might be needed for medium code model.
2892 if (M != CodeModel::Small && M != CodeModel::Kernel)
2895 // For small code model we assume that latest object is 16MB before end of 31
2896 // bits boundary. We may also accept pretty large negative constants knowing
2897 // that all objects are in the positive half of address space.
2898 if (M == CodeModel::Small && Offset < 16*1024*1024)
2901 // For kernel code model we know that all object resist in the negative half
2902 // of 32bits address space. We may not accept negative offsets, since they may
2903 // be just off and we may accept pretty large positive ones.
2904 if (M == CodeModel::Kernel && Offset > 0)
2910 /// isCalleePop - Determines whether the callee is required to pop its
2911 /// own arguments. Callee pop is necessary to support tail calls.
2912 bool X86::isCalleePop(CallingConv::ID CallingConv,
2913 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2917 switch (CallingConv) {
2920 case CallingConv::X86_StdCall:
2922 case CallingConv::X86_FastCall:
2924 case CallingConv::X86_ThisCall:
2926 case CallingConv::Fast:
2928 case CallingConv::GHC:
2933 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2934 /// specific condition code, returning the condition code and the LHS/RHS of the
2935 /// comparison to make.
2936 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2937 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2939 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2940 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2941 // X > -1 -> X == 0, jump !sign.
2942 RHS = DAG.getConstant(0, RHS.getValueType());
2943 return X86::COND_NS;
2944 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2945 // X < 0 -> X == 0, jump on sign.
2947 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2949 RHS = DAG.getConstant(0, RHS.getValueType());
2950 return X86::COND_LE;
2954 switch (SetCCOpcode) {
2955 default: llvm_unreachable("Invalid integer condition!");
2956 case ISD::SETEQ: return X86::COND_E;
2957 case ISD::SETGT: return X86::COND_G;
2958 case ISD::SETGE: return X86::COND_GE;
2959 case ISD::SETLT: return X86::COND_L;
2960 case ISD::SETLE: return X86::COND_LE;
2961 case ISD::SETNE: return X86::COND_NE;
2962 case ISD::SETULT: return X86::COND_B;
2963 case ISD::SETUGT: return X86::COND_A;
2964 case ISD::SETULE: return X86::COND_BE;
2965 case ISD::SETUGE: return X86::COND_AE;
2969 // First determine if it is required or is profitable to flip the operands.
2971 // If LHS is a foldable load, but RHS is not, flip the condition.
2972 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
2973 !ISD::isNON_EXTLoad(RHS.getNode())) {
2974 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2975 std::swap(LHS, RHS);
2978 switch (SetCCOpcode) {
2984 std::swap(LHS, RHS);
2988 // On a floating point condition, the flags are set as follows:
2990 // 0 | 0 | 0 | X > Y
2991 // 0 | 0 | 1 | X < Y
2992 // 1 | 0 | 0 | X == Y
2993 // 1 | 1 | 1 | unordered
2994 switch (SetCCOpcode) {
2995 default: llvm_unreachable("Condcode should be pre-legalized away");
2997 case ISD::SETEQ: return X86::COND_E;
2998 case ISD::SETOLT: // flipped
3000 case ISD::SETGT: return X86::COND_A;
3001 case ISD::SETOLE: // flipped
3003 case ISD::SETGE: return X86::COND_AE;
3004 case ISD::SETUGT: // flipped
3006 case ISD::SETLT: return X86::COND_B;
3007 case ISD::SETUGE: // flipped
3009 case ISD::SETLE: return X86::COND_BE;
3011 case ISD::SETNE: return X86::COND_NE;
3012 case ISD::SETUO: return X86::COND_P;
3013 case ISD::SETO: return X86::COND_NP;
3015 case ISD::SETUNE: return X86::COND_INVALID;
3019 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3020 /// code. Current x86 isa includes the following FP cmov instructions:
3021 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3022 static bool hasFPCMov(unsigned X86CC) {
3038 /// isFPImmLegal - Returns true if the target can instruction select the
3039 /// specified FP immediate natively. If false, the legalizer will
3040 /// materialize the FP immediate as a load from a constant pool.
3041 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3042 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3043 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3049 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3050 /// the specified range (L, H].
3051 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3052 return (Val < 0) || (Val >= Low && Val < Hi);
3055 /// isUndefOrInRange - Return true if every element in Mask, begining
3056 /// from position Pos and ending in Pos+Size, falls within the specified
3057 /// range (L, L+Pos]. or is undef.
3058 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3059 int Pos, int Size, int Low, int Hi) {
3060 for (int i = Pos, e = Pos+Size; i != e; ++i)
3061 if (!isUndefOrInRange(Mask[i], Low, Hi))
3066 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3067 /// specified value.
3068 static bool isUndefOrEqual(int Val, int CmpVal) {
3069 if (Val < 0 || Val == CmpVal)
3074 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3075 /// from position Pos and ending in Pos+Size, falls within the specified
3076 /// sequential range (L, L+Pos]. or is undef.
3077 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3078 int Pos, int Size, int Low) {
3079 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3080 if (!isUndefOrEqual(Mask[i], Low))
3085 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3086 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3087 /// the second operand.
3088 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3089 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3090 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3091 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3092 return (Mask[0] < 2 && Mask[1] < 2);
3096 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3097 SmallVector<int, 8> M;
3099 return ::isPSHUFDMask(M, N->getValueType(0));
3102 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3103 /// is suitable for input to PSHUFHW.
3104 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3105 if (VT != MVT::v8i16)
3108 // Lower quadword copied in order or undef.
3109 for (int i = 0; i != 4; ++i)
3110 if (Mask[i] >= 0 && Mask[i] != i)
3113 // Upper quadword shuffled.
3114 for (int i = 4; i != 8; ++i)
3115 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3121 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3122 SmallVector<int, 8> M;
3124 return ::isPSHUFHWMask(M, N->getValueType(0));
3127 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3128 /// is suitable for input to PSHUFLW.
3129 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3130 if (VT != MVT::v8i16)
3133 // Upper quadword copied in order.
3134 for (int i = 4; i != 8; ++i)
3135 if (Mask[i] >= 0 && Mask[i] != i)
3138 // Lower quadword shuffled.
3139 for (int i = 0; i != 4; ++i)
3146 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3147 SmallVector<int, 8> M;
3149 return ::isPSHUFLWMask(M, N->getValueType(0));
3152 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3153 /// is suitable for input to PALIGNR.
3154 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3156 int i, e = VT.getVectorNumElements();
3157 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64)
3160 // Do not handle v2i64 / v2f64 shuffles with palignr.
3161 if (e < 4 || !hasSSSE3)
3164 for (i = 0; i != e; ++i)
3168 // All undef, not a palignr.
3172 // Make sure we're shifting in the right direction.
3176 int s = Mask[i] - i;
3178 // Check the rest of the elements to see if they are consecutive.
3179 for (++i; i != e; ++i) {
3181 if (m >= 0 && m != s+i)
3187 /// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand
3188 /// specifies a shuffle of elements that is suitable for input to 256-bit
3190 static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3191 const X86Subtarget *Subtarget) {
3192 int NumElems = VT.getVectorNumElements();
3194 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3200 // VSHUFPSY divides the resulting vector into 4 chunks.
3201 // The sources are also splitted into 4 chunks, and each destination
3202 // chunk must come from a different source chunk.
3204 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3205 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3207 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3208 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3210 int QuarterSize = NumElems/4;
3211 int HalfSize = QuarterSize*2;
3212 for (int i = 0; i < QuarterSize; ++i)
3213 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3215 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3216 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3219 // The mask of the second half must be the same as the first but with
3220 // the appropriate offsets. This works in the same way as VPERMILPS
3221 // works with masks.
3222 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) {
3223 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3225 int FstHalfIdx = i-HalfSize;
3226 if (Mask[FstHalfIdx] < 0)
3228 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3231 for (int i = QuarterSize*3; i < NumElems; ++i) {
3232 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3234 int FstHalfIdx = i-HalfSize;
3235 if (Mask[FstHalfIdx] < 0)
3237 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3245 /// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle
3246 /// the specified VECTOR_MASK mask with VSHUFPSY instruction.
3247 static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) {
3248 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3249 EVT VT = SVOp->getValueType(0);
3250 int NumElems = VT.getVectorNumElements();
3252 assert(NumElems == 8 && VT.getSizeInBits() == 256 &&
3253 "Only supports v8i32 and v8f32 types");
3255 int HalfSize = NumElems/2;
3257 for (int i = 0; i != NumElems ; ++i) {
3258 if (SVOp->getMaskElt(i) < 0)
3260 // The mask of the first half must be equal to the second one.
3261 unsigned Shamt = (i%HalfSize)*2;
3262 unsigned Elt = SVOp->getMaskElt(i) % HalfSize;
3263 Mask |= Elt << Shamt;
3269 /// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand
3270 /// specifies a shuffle of elements that is suitable for input to 256-bit
3271 /// VSHUFPDY. This shuffle doesn't have the same restriction as the PS
3272 /// version and the mask of the second half isn't binded with the first
3274 static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3275 const X86Subtarget *Subtarget) {
3276 int NumElems = VT.getVectorNumElements();
3278 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3284 // VSHUFPSY divides the resulting vector into 4 chunks.
3285 // The sources are also splitted into 4 chunks, and each destination
3286 // chunk must come from a different source chunk.
3288 // SRC1 => X3 X2 X1 X0
3289 // SRC2 => Y3 Y2 Y1 Y0
3291 // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0
3293 int QuarterSize = NumElems/4;
3294 int HalfSize = QuarterSize*2;
3295 for (int i = 0; i < QuarterSize; ++i)
3296 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3298 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3299 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3301 for (int i = QuarterSize*2; i < QuarterSize*3; ++i)
3302 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3304 for (int i = QuarterSize*3; i < NumElems; ++i)
3305 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3311 /// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle
3312 /// the specified VECTOR_MASK mask with VSHUFPDY instruction.
3313 static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) {
3314 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3315 EVT VT = SVOp->getValueType(0);
3316 int NumElems = VT.getVectorNumElements();
3318 assert(NumElems == 4 && VT.getSizeInBits() == 256 &&
3319 "Only supports v4i64 and v4f64 types");
3321 int HalfSize = NumElems/2;
3323 for (int i = 0; i != NumElems ; ++i) {
3324 if (SVOp->getMaskElt(i) < 0)
3326 int Elt = SVOp->getMaskElt(i) % HalfSize;
3333 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3334 /// specifies a shuffle of elements that is suitable for input to 128-bit
3335 /// SHUFPS and SHUFPD.
3336 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3337 int NumElems = VT.getVectorNumElements();
3339 if (VT.getSizeInBits() != 128)
3342 if (NumElems != 2 && NumElems != 4)
3345 int Half = NumElems / 2;
3346 for (int i = 0; i < Half; ++i)
3347 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3349 for (int i = Half; i < NumElems; ++i)
3350 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3356 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3357 SmallVector<int, 8> M;
3359 return ::isSHUFPMask(M, N->getValueType(0));
3362 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3363 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3364 /// half elements to come from vector 1 (which would equal the dest.) and
3365 /// the upper half to come from vector 2.
3366 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3367 int NumElems = VT.getVectorNumElements();
3369 if (NumElems != 2 && NumElems != 4)
3372 int Half = NumElems / 2;
3373 for (int i = 0; i < Half; ++i)
3374 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3376 for (int i = Half; i < NumElems; ++i)
3377 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3382 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3383 SmallVector<int, 8> M;
3385 return isCommutedSHUFPMask(M, N->getValueType(0));
3388 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3389 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3390 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3391 EVT VT = N->getValueType(0);
3392 unsigned NumElems = VT.getVectorNumElements();
3394 if (VT.getSizeInBits() != 128)
3400 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3401 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3402 isUndefOrEqual(N->getMaskElt(1), 7) &&
3403 isUndefOrEqual(N->getMaskElt(2), 2) &&
3404 isUndefOrEqual(N->getMaskElt(3), 3);
3407 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3408 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3410 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3411 EVT VT = N->getValueType(0);
3412 unsigned NumElems = VT.getVectorNumElements();
3414 if (VT.getSizeInBits() != 128)
3420 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3421 isUndefOrEqual(N->getMaskElt(1), 3) &&
3422 isUndefOrEqual(N->getMaskElt(2), 2) &&
3423 isUndefOrEqual(N->getMaskElt(3), 3);
3426 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3427 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3428 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3429 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3431 if (NumElems != 2 && NumElems != 4)
3434 for (unsigned i = 0; i < NumElems/2; ++i)
3435 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3438 for (unsigned i = NumElems/2; i < NumElems; ++i)
3439 if (!isUndefOrEqual(N->getMaskElt(i), i))
3445 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3446 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3447 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3448 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3450 if ((NumElems != 2 && NumElems != 4)
3451 || N->getValueType(0).getSizeInBits() > 128)
3454 for (unsigned i = 0; i < NumElems/2; ++i)
3455 if (!isUndefOrEqual(N->getMaskElt(i), i))
3458 for (unsigned i = 0; i < NumElems/2; ++i)
3459 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3465 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3466 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3467 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3468 bool V2IsSplat = false) {
3469 int NumElts = VT.getVectorNumElements();
3471 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3472 "Unsupported vector type for unpckh");
3474 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3477 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3478 // independently on 128-bit lanes.
3479 unsigned NumLanes = VT.getSizeInBits()/128;
3480 unsigned NumLaneElts = NumElts/NumLanes;
3483 unsigned End = NumLaneElts;
3484 for (unsigned s = 0; s < NumLanes; ++s) {
3485 for (unsigned i = Start, j = s * NumLaneElts;
3489 int BitI1 = Mask[i+1];
3490 if (!isUndefOrEqual(BitI, j))
3493 if (!isUndefOrEqual(BitI1, NumElts))
3496 if (!isUndefOrEqual(BitI1, j + NumElts))
3500 // Process the next 128 bits.
3501 Start += NumLaneElts;
3508 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3509 SmallVector<int, 8> M;
3511 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3514 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3515 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3516 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3517 bool V2IsSplat = false) {
3518 int NumElts = VT.getVectorNumElements();
3520 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3521 "Unsupported vector type for unpckh");
3523 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3526 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3527 // independently on 128-bit lanes.
3528 unsigned NumLanes = VT.getSizeInBits()/128;
3529 unsigned NumLaneElts = NumElts/NumLanes;
3532 unsigned End = NumLaneElts;
3533 for (unsigned l = 0; l != NumLanes; ++l) {
3534 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3535 i != End; i += 2, ++j) {
3537 int BitI1 = Mask[i+1];
3538 if (!isUndefOrEqual(BitI, j))
3541 if (isUndefOrEqual(BitI1, NumElts))
3544 if (!isUndefOrEqual(BitI1, j+NumElts))
3548 // Process the next 128 bits.
3549 Start += NumLaneElts;
3555 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3556 SmallVector<int, 8> M;
3558 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3561 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3562 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3564 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3565 int NumElems = VT.getVectorNumElements();
3566 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3569 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3570 // FIXME: Need a better way to get rid of this, there's no latency difference
3571 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3572 // the former later. We should also remove the "_undef" special mask.
3573 if (NumElems == 4 && VT.getSizeInBits() == 256)
3576 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3577 // independently on 128-bit lanes.
3578 unsigned NumLanes = VT.getSizeInBits() / 128;
3579 unsigned NumLaneElts = NumElems / NumLanes;
3581 for (unsigned s = 0; s < NumLanes; ++s) {
3582 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3583 i != NumLaneElts * (s + 1);
3586 int BitI1 = Mask[i+1];
3588 if (!isUndefOrEqual(BitI, j))
3590 if (!isUndefOrEqual(BitI1, j))
3598 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3599 SmallVector<int, 8> M;
3601 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3604 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3605 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3607 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3608 int NumElems = VT.getVectorNumElements();
3609 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3612 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3614 int BitI1 = Mask[i+1];
3615 if (!isUndefOrEqual(BitI, j))
3617 if (!isUndefOrEqual(BitI1, j))
3623 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3624 SmallVector<int, 8> M;
3626 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3629 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3630 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3631 /// MOVSD, and MOVD, i.e. setting the lowest element.
3632 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3633 if (VT.getVectorElementType().getSizeInBits() < 32)
3636 int NumElts = VT.getVectorNumElements();
3638 if (!isUndefOrEqual(Mask[0], NumElts))
3641 for (int i = 1; i < NumElts; ++i)
3642 if (!isUndefOrEqual(Mask[i], i))
3648 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3649 SmallVector<int, 8> M;
3651 return ::isMOVLMask(M, N->getValueType(0));
3654 /// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered
3655 /// as permutations between 128-bit chunks or halves. As an example: this
3657 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3658 /// The first half comes from the second half of V1 and the second half from the
3659 /// the second half of V2.
3660 static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3661 const X86Subtarget *Subtarget) {
3662 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3665 // The shuffle result is divided into half A and half B. In total the two
3666 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3667 // B must come from C, D, E or F.
3668 int HalfSize = VT.getVectorNumElements()/2;
3669 bool MatchA = false, MatchB = false;
3671 // Check if A comes from one of C, D, E, F.
3672 for (int Half = 0; Half < 4; ++Half) {
3673 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3679 // Check if B comes from one of C, D, E, F.
3680 for (int Half = 0; Half < 4; ++Half) {
3681 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3687 return MatchA && MatchB;
3690 /// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle
3691 /// the specified VECTOR_MASK mask with VPERM2F128 instructions.
3692 static unsigned getShuffleVPERM2F128Immediate(SDNode *N) {
3693 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3694 EVT VT = SVOp->getValueType(0);
3696 int HalfSize = VT.getVectorNumElements()/2;
3698 int FstHalf = 0, SndHalf = 0;
3699 for (int i = 0; i < HalfSize; ++i) {
3700 if (SVOp->getMaskElt(i) > 0) {
3701 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3705 for (int i = HalfSize; i < HalfSize*2; ++i) {
3706 if (SVOp->getMaskElt(i) > 0) {
3707 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3712 return (FstHalf | (SndHalf << 4));
3715 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3716 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3717 /// Note that VPERMIL mask matching is different depending whether theunderlying
3718 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3719 /// to the same elements of the low, but to the higher half of the source.
3720 /// In VPERMILPD the two lanes could be shuffled independently of each other
3721 /// with the same restriction that lanes can't be crossed.
3722 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
3723 const X86Subtarget *Subtarget) {
3724 int NumElts = VT.getVectorNumElements();
3725 int NumLanes = VT.getSizeInBits()/128;
3727 if (!Subtarget->hasAVX())
3730 // Match any permutation of 128-bit vector with 64-bit types
3731 if (NumLanes == 1 && NumElts != 2)
3734 // Only match 256-bit with 32 types
3735 if (VT.getSizeInBits() == 256 && NumElts != 4)
3738 // The mask on the high lane is independent of the low. Both can match
3739 // any element in inside its own lane, but can't cross.
3740 int LaneSize = NumElts/NumLanes;
3741 for (int l = 0; l < NumLanes; ++l)
3742 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3743 int LaneStart = l*LaneSize;
3744 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize))
3751 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3752 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*.
3753 /// Note that VPERMIL mask matching is different depending whether theunderlying
3754 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3755 /// to the same elements of the low, but to the higher half of the source.
3756 /// In VPERMILPD the two lanes could be shuffled independently of each other
3757 /// with the same restriction that lanes can't be crossed.
3758 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
3759 const X86Subtarget *Subtarget) {
3760 unsigned NumElts = VT.getVectorNumElements();
3761 unsigned NumLanes = VT.getSizeInBits()/128;
3763 if (!Subtarget->hasAVX())
3766 // Match any permutation of 128-bit vector with 32-bit types
3767 if (NumLanes == 1 && NumElts != 4)
3770 // Only match 256-bit with 32 types
3771 if (VT.getSizeInBits() == 256 && NumElts != 8)
3774 // The mask on the high lane should be the same as the low. Actually,
3775 // they can differ if any of the corresponding index in a lane is undef
3776 // and the other stays in range.
3777 int LaneSize = NumElts/NumLanes;
3778 for (int i = 0; i < LaneSize; ++i) {
3779 int HighElt = i+LaneSize;
3780 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts);
3781 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize);
3783 if (!HighValid || !LowValid)
3785 if (Mask[i] < 0 || Mask[HighElt] < 0)
3787 if (Mask[HighElt]-Mask[i] != LaneSize)
3794 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle
3795 /// the specified VECTOR_MASK mask with VPERMILPS* instructions.
3796 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) {
3797 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3798 EVT VT = SVOp->getValueType(0);
3800 int NumElts = VT.getVectorNumElements();
3801 int NumLanes = VT.getSizeInBits()/128;
3802 int LaneSize = NumElts/NumLanes;
3804 // Although the mask is equal for both lanes do it twice to get the cases
3805 // where a mask will match because the same mask element is undef on the
3806 // first half but valid on the second. This would get pathological cases
3807 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3809 for (int l = 0; l < NumLanes; ++l) {
3810 for (int i = 0; i < LaneSize; ++i) {
3811 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize));
3814 if (MaskElt >= LaneSize)
3815 MaskElt -= LaneSize;
3816 Mask |= MaskElt << (i*2);
3823 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle
3824 /// the specified VECTOR_MASK mask with VPERMILPD* instructions.
3825 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) {
3826 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3827 EVT VT = SVOp->getValueType(0);
3829 int NumElts = VT.getVectorNumElements();
3830 int NumLanes = VT.getSizeInBits()/128;
3833 int LaneSize = NumElts/NumLanes;
3834 for (int l = 0; l < NumLanes; ++l)
3835 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3836 int MaskElt = SVOp->getMaskElt(i);
3839 Mask |= (MaskElt-l*LaneSize) << i;
3845 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3846 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3847 /// element of vector 2 and the other elements to come from vector 1 in order.
3848 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3849 bool V2IsSplat = false, bool V2IsUndef = false) {
3850 int NumOps = VT.getVectorNumElements();
3851 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3854 if (!isUndefOrEqual(Mask[0], 0))
3857 for (int i = 1; i < NumOps; ++i)
3858 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3859 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3860 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3866 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3867 bool V2IsUndef = false) {
3868 SmallVector<int, 8> M;
3870 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3873 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3874 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3875 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3876 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3877 const X86Subtarget *Subtarget) {
3878 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3881 // The second vector must be undef
3882 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3885 EVT VT = N->getValueType(0);
3886 unsigned NumElems = VT.getVectorNumElements();
3888 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3889 (VT.getSizeInBits() == 256 && NumElems != 8))
3892 // "i+1" is the value the indexed mask element must have
3893 for (unsigned i = 0; i < NumElems; i += 2)
3894 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3895 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3901 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3902 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3903 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3904 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3905 const X86Subtarget *Subtarget) {
3906 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3909 // The second vector must be undef
3910 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3913 EVT VT = N->getValueType(0);
3914 unsigned NumElems = VT.getVectorNumElements();
3916 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3917 (VT.getSizeInBits() == 256 && NumElems != 8))
3920 // "i" is the value the indexed mask element must have
3921 for (unsigned i = 0; i < NumElems; i += 2)
3922 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3923 !isUndefOrEqual(N->getMaskElt(i+1), i))
3929 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3930 /// specifies a shuffle of elements that is suitable for input to 256-bit
3931 /// version of MOVDDUP.
3932 static bool isMOVDDUPYMask(ShuffleVectorSDNode *N,
3933 const X86Subtarget *Subtarget) {
3934 EVT VT = N->getValueType(0);
3935 int NumElts = VT.getVectorNumElements();
3936 bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF;
3938 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 ||
3939 !V2IsUndef || NumElts != 4)
3942 for (int i = 0; i != NumElts/2; ++i)
3943 if (!isUndefOrEqual(N->getMaskElt(i), 0))
3945 for (int i = NumElts/2; i != NumElts; ++i)
3946 if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2))
3951 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3952 /// specifies a shuffle of elements that is suitable for input to 128-bit
3953 /// version of MOVDDUP.
3954 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3955 EVT VT = N->getValueType(0);
3957 if (VT.getSizeInBits() != 128)
3960 int e = VT.getVectorNumElements() / 2;
3961 for (int i = 0; i < e; ++i)
3962 if (!isUndefOrEqual(N->getMaskElt(i), i))
3964 for (int i = 0; i < e; ++i)
3965 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3970 /// isVEXTRACTF128Index - Return true if the specified
3971 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3972 /// suitable for input to VEXTRACTF128.
3973 bool X86::isVEXTRACTF128Index(SDNode *N) {
3974 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3977 // The index should be aligned on a 128-bit boundary.
3979 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3981 unsigned VL = N->getValueType(0).getVectorNumElements();
3982 unsigned VBits = N->getValueType(0).getSizeInBits();
3983 unsigned ElSize = VBits / VL;
3984 bool Result = (Index * ElSize) % 128 == 0;
3989 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3990 /// operand specifies a subvector insert that is suitable for input to
3992 bool X86::isVINSERTF128Index(SDNode *N) {
3993 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3996 // The index should be aligned on a 128-bit boundary.
3998 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4000 unsigned VL = N->getValueType(0).getVectorNumElements();
4001 unsigned VBits = N->getValueType(0).getSizeInBits();
4002 unsigned ElSize = VBits / VL;
4003 bool Result = (Index * ElSize) % 128 == 0;
4008 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4009 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4010 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
4011 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4012 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
4014 unsigned Shift = (NumOperands == 4) ? 2 : 1;
4016 for (int i = 0; i < NumOperands; ++i) {
4017 int Val = SVOp->getMaskElt(NumOperands-i-1);
4018 if (Val < 0) Val = 0;
4019 if (Val >= NumOperands) Val -= NumOperands;
4021 if (i != NumOperands - 1)
4027 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4028 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4029 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
4030 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4032 // 8 nodes, but we only care about the last 4.
4033 for (unsigned i = 7; i >= 4; --i) {
4034 int Val = SVOp->getMaskElt(i);
4043 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4044 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4045 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
4046 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4048 // 8 nodes, but we only care about the first 4.
4049 for (int i = 3; i >= 0; --i) {
4050 int Val = SVOp->getMaskElt(i);
4059 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4060 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4061 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
4062 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4063 EVT VVT = N->getValueType(0);
4064 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
4068 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
4069 Val = SVOp->getMaskElt(i);
4073 assert(Val - i > 0 && "PALIGNR imm should be positive");
4074 return (Val - i) * EltSize;
4077 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4078 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4080 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4081 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4082 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4085 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4087 EVT VecVT = N->getOperand(0).getValueType();
4088 EVT ElVT = VecVT.getVectorElementType();
4090 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4091 return Index / NumElemsPerChunk;
4094 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4095 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4097 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4098 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4099 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4102 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4104 EVT VecVT = N->getValueType(0);
4105 EVT ElVT = VecVT.getVectorElementType();
4107 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4108 return Index / NumElemsPerChunk;
4111 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4113 bool X86::isZeroNode(SDValue Elt) {
4114 return ((isa<ConstantSDNode>(Elt) &&
4115 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4116 (isa<ConstantFPSDNode>(Elt) &&
4117 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4120 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4121 /// their permute mask.
4122 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4123 SelectionDAG &DAG) {
4124 EVT VT = SVOp->getValueType(0);
4125 unsigned NumElems = VT.getVectorNumElements();
4126 SmallVector<int, 8> MaskVec;
4128 for (unsigned i = 0; i != NumElems; ++i) {
4129 int idx = SVOp->getMaskElt(i);
4131 MaskVec.push_back(idx);
4132 else if (idx < (int)NumElems)
4133 MaskVec.push_back(idx + NumElems);
4135 MaskVec.push_back(idx - NumElems);
4137 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4138 SVOp->getOperand(0), &MaskVec[0]);
4141 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4142 /// the two vector operands have swapped position.
4143 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
4144 unsigned NumElems = VT.getVectorNumElements();
4145 for (unsigned i = 0; i != NumElems; ++i) {
4149 else if (idx < (int)NumElems)
4150 Mask[i] = idx + NumElems;
4152 Mask[i] = idx - NumElems;
4156 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4157 /// match movhlps. The lower half elements should come from upper half of
4158 /// V1 (and in order), and the upper half elements should come from the upper
4159 /// half of V2 (and in order).
4160 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4161 EVT VT = Op->getValueType(0);
4162 if (VT.getSizeInBits() != 128)
4164 if (VT.getVectorNumElements() != 4)
4166 for (unsigned i = 0, e = 2; i != e; ++i)
4167 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4169 for (unsigned i = 2; i != 4; ++i)
4170 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4175 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4176 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4178 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4179 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4181 N = N->getOperand(0).getNode();
4182 if (!ISD::isNON_EXTLoad(N))
4185 *LD = cast<LoadSDNode>(N);
4189 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4190 /// match movlp{s|d}. The lower half elements should come from lower half of
4191 /// V1 (and in order), and the upper half elements should come from the upper
4192 /// half of V2 (and in order). And since V1 will become the source of the
4193 /// MOVLP, it must be either a vector load or a scalar load to vector.
4194 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4195 ShuffleVectorSDNode *Op) {
4196 EVT VT = Op->getValueType(0);
4197 if (VT.getSizeInBits() != 128)
4200 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4202 // Is V2 is a vector load, don't do this transformation. We will try to use
4203 // load folding shufps op.
4204 if (ISD::isNON_EXTLoad(V2))
4207 unsigned NumElems = VT.getVectorNumElements();
4209 if (NumElems != 2 && NumElems != 4)
4211 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4212 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4214 for (unsigned i = NumElems/2; i != NumElems; ++i)
4215 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4220 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4222 static bool isSplatVector(SDNode *N) {
4223 if (N->getOpcode() != ISD::BUILD_VECTOR)
4226 SDValue SplatValue = N->getOperand(0);
4227 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4228 if (N->getOperand(i) != SplatValue)
4233 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4234 /// to an zero vector.
4235 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4236 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4237 SDValue V1 = N->getOperand(0);
4238 SDValue V2 = N->getOperand(1);
4239 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4240 for (unsigned i = 0; i != NumElems; ++i) {
4241 int Idx = N->getMaskElt(i);
4242 if (Idx >= (int)NumElems) {
4243 unsigned Opc = V2.getOpcode();
4244 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4246 if (Opc != ISD::BUILD_VECTOR ||
4247 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4249 } else if (Idx >= 0) {
4250 unsigned Opc = V1.getOpcode();
4251 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4253 if (Opc != ISD::BUILD_VECTOR ||
4254 !X86::isZeroNode(V1.getOperand(Idx)))
4261 /// getZeroVector - Returns a vector of specified type with all zero elements.
4263 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
4265 assert(VT.isVector() && "Expected a vector type");
4267 // Always build SSE zero vectors as <4 x i32> bitcasted
4268 // to their dest type. This ensures they get CSE'd.
4270 if (VT.getSizeInBits() == 128) { // SSE
4271 if (HasSSE2) { // SSE2
4272 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4273 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4275 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4276 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4278 } else if (VT.getSizeInBits() == 256) { // AVX
4279 // 256-bit logic and arithmetic instructions in AVX are
4280 // all floating-point, no support for integer ops. Default
4281 // to emitting fp zeroed vectors then.
4282 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4283 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4284 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4286 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4289 /// getOnesVector - Returns a vector of specified type with all bits set.
4290 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two
4291 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
4292 /// original type, ensuring they get CSE'd.
4293 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4294 assert(VT.isVector() && "Expected a vector type");
4295 assert((VT.is128BitVector() || VT.is256BitVector())
4296 && "Expected a 128-bit or 256-bit vector type");
4298 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4299 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
4300 Cst, Cst, Cst, Cst);
4302 if (VT.is256BitVector()) {
4303 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4304 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4305 Vec = Insert128BitVector(InsV, Vec,
4306 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4309 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4312 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4313 /// that point to V2 points to its first element.
4314 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4315 EVT VT = SVOp->getValueType(0);
4316 unsigned NumElems = VT.getVectorNumElements();
4318 bool Changed = false;
4319 SmallVector<int, 8> MaskVec;
4320 SVOp->getMask(MaskVec);
4322 for (unsigned i = 0; i != NumElems; ++i) {
4323 if (MaskVec[i] > (int)NumElems) {
4324 MaskVec[i] = NumElems;
4329 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4330 SVOp->getOperand(1), &MaskVec[0]);
4331 return SDValue(SVOp, 0);
4334 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4335 /// operation of specified width.
4336 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4338 unsigned NumElems = VT.getVectorNumElements();
4339 SmallVector<int, 8> Mask;
4340 Mask.push_back(NumElems);
4341 for (unsigned i = 1; i != NumElems; ++i)
4343 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4346 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4347 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4349 unsigned NumElems = VT.getVectorNumElements();
4350 SmallVector<int, 8> Mask;
4351 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4353 Mask.push_back(i + NumElems);
4355 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4358 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4359 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4361 unsigned NumElems = VT.getVectorNumElements();
4362 unsigned Half = NumElems/2;
4363 SmallVector<int, 8> Mask;
4364 for (unsigned i = 0; i != Half; ++i) {
4365 Mask.push_back(i + Half);
4366 Mask.push_back(i + NumElems + Half);
4368 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4371 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4372 // a generic shuffle instruction because the target has no such instructions.
4373 // Generate shuffles which repeat i16 and i8 several times until they can be
4374 // represented by v4f32 and then be manipulated by target suported shuffles.
4375 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4376 EVT VT = V.getValueType();
4377 int NumElems = VT.getVectorNumElements();
4378 DebugLoc dl = V.getDebugLoc();
4380 while (NumElems > 4) {
4381 if (EltNo < NumElems/2) {
4382 V = getUnpackl(DAG, dl, VT, V, V);
4384 V = getUnpackh(DAG, dl, VT, V, V);
4385 EltNo -= NumElems/2;
4392 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4393 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4394 EVT VT = V.getValueType();
4395 DebugLoc dl = V.getDebugLoc();
4396 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4397 && "Vector size not supported");
4399 if (VT.getSizeInBits() == 128) {
4400 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4401 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4402 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4405 // To use VPERMILPS to splat scalars, the second half of indicies must
4406 // refer to the higher part, which is a duplication of the lower one,
4407 // because VPERMILPS can only handle in-lane permutations.
4408 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4409 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4411 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4412 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4416 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4419 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4420 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4421 EVT SrcVT = SV->getValueType(0);
4422 SDValue V1 = SV->getOperand(0);
4423 DebugLoc dl = SV->getDebugLoc();
4425 int EltNo = SV->getSplatIndex();
4426 int NumElems = SrcVT.getVectorNumElements();
4427 unsigned Size = SrcVT.getSizeInBits();
4429 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4430 "Unknown how to promote splat for type");
4432 // Extract the 128-bit part containing the splat element and update
4433 // the splat element index when it refers to the higher register.
4435 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4436 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4438 EltNo -= NumElems/2;
4441 // All i16 and i8 vector types can't be used directly by a generic shuffle
4442 // instruction because the target has no such instruction. Generate shuffles
4443 // which repeat i16 and i8 several times until they fit in i32, and then can
4444 // be manipulated by target suported shuffles.
4445 EVT EltVT = SrcVT.getVectorElementType();
4446 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4447 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4449 // Recreate the 256-bit vector and place the same 128-bit vector
4450 // into the low and high part. This is necessary because we want
4451 // to use VPERM* to shuffle the vectors
4453 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4454 DAG.getConstant(0, MVT::i32), DAG, dl);
4455 V1 = Insert128BitVector(InsV, V1,
4456 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4459 return getLegalSplat(DAG, V1, EltNo);
4462 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4463 /// vector of zero or undef vector. This produces a shuffle where the low
4464 /// element of V2 is swizzled into the zero/undef vector, landing at element
4465 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4466 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4467 bool isZero, bool HasSSE2,
4468 SelectionDAG &DAG) {
4469 EVT VT = V2.getValueType();
4471 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4472 unsigned NumElems = VT.getVectorNumElements();
4473 SmallVector<int, 16> MaskVec;
4474 for (unsigned i = 0; i != NumElems; ++i)
4475 // If this is the insertion idx, put the low elt of V2 here.
4476 MaskVec.push_back(i == Idx ? NumElems : i);
4477 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4480 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4481 /// element of the result of the vector shuffle.
4482 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4485 return SDValue(); // Limit search depth.
4487 SDValue V = SDValue(N, 0);
4488 EVT VT = V.getValueType();
4489 unsigned Opcode = V.getOpcode();
4491 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4492 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4493 Index = SV->getMaskElt(Index);
4496 return DAG.getUNDEF(VT.getVectorElementType());
4498 int NumElems = VT.getVectorNumElements();
4499 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4500 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4503 // Recurse into target specific vector shuffles to find scalars.
4504 if (isTargetShuffle(Opcode)) {
4505 int NumElems = VT.getVectorNumElements();
4506 SmallVector<unsigned, 16> ShuffleMask;
4510 case X86ISD::SHUFPS:
4511 case X86ISD::SHUFPD:
4512 ImmN = N->getOperand(N->getNumOperands()-1);
4513 DecodeSHUFPSMask(NumElems,
4514 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4517 case X86ISD::PUNPCKHBW:
4518 case X86ISD::PUNPCKHWD:
4519 case X86ISD::PUNPCKHDQ:
4520 case X86ISD::PUNPCKHQDQ:
4521 DecodePUNPCKHMask(NumElems, ShuffleMask);
4523 case X86ISD::UNPCKHPS:
4524 case X86ISD::UNPCKHPD:
4525 case X86ISD::VUNPCKHPSY:
4526 case X86ISD::VUNPCKHPDY:
4527 DecodeUNPCKHPMask(NumElems, ShuffleMask);
4529 case X86ISD::PUNPCKLBW:
4530 case X86ISD::PUNPCKLWD:
4531 case X86ISD::PUNPCKLDQ:
4532 case X86ISD::PUNPCKLQDQ:
4533 DecodePUNPCKLMask(VT, ShuffleMask);
4535 case X86ISD::UNPCKLPS:
4536 case X86ISD::UNPCKLPD:
4537 case X86ISD::VUNPCKLPSY:
4538 case X86ISD::VUNPCKLPDY:
4539 DecodeUNPCKLPMask(VT, ShuffleMask);
4541 case X86ISD::MOVHLPS:
4542 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4544 case X86ISD::MOVLHPS:
4545 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4547 case X86ISD::PSHUFD:
4548 ImmN = N->getOperand(N->getNumOperands()-1);
4549 DecodePSHUFMask(NumElems,
4550 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4553 case X86ISD::PSHUFHW:
4554 ImmN = N->getOperand(N->getNumOperands()-1);
4555 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4558 case X86ISD::PSHUFLW:
4559 ImmN = N->getOperand(N->getNumOperands()-1);
4560 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4564 case X86ISD::MOVSD: {
4565 // The index 0 always comes from the first element of the second source,
4566 // this is why MOVSS and MOVSD are used in the first place. The other
4567 // elements come from the other positions of the first source vector.
4568 unsigned OpNum = (Index == 0) ? 1 : 0;
4569 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4572 case X86ISD::VPERMILPS:
4573 ImmN = N->getOperand(N->getNumOperands()-1);
4574 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4577 case X86ISD::VPERMILPSY:
4578 ImmN = N->getOperand(N->getNumOperands()-1);
4579 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4582 case X86ISD::VPERMILPD:
4583 ImmN = N->getOperand(N->getNumOperands()-1);
4584 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4587 case X86ISD::VPERMILPDY:
4588 ImmN = N->getOperand(N->getNumOperands()-1);
4589 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4592 case X86ISD::VPERM2F128:
4593 ImmN = N->getOperand(N->getNumOperands()-1);
4594 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4598 assert("not implemented for target shuffle node");
4602 Index = ShuffleMask[Index];
4604 return DAG.getUNDEF(VT.getVectorElementType());
4606 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4607 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4611 // Actual nodes that may contain scalar elements
4612 if (Opcode == ISD::BITCAST) {
4613 V = V.getOperand(0);
4614 EVT SrcVT = V.getValueType();
4615 unsigned NumElems = VT.getVectorNumElements();
4617 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4621 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4622 return (Index == 0) ? V.getOperand(0)
4623 : DAG.getUNDEF(VT.getVectorElementType());
4625 if (V.getOpcode() == ISD::BUILD_VECTOR)
4626 return V.getOperand(Index);
4631 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4632 /// shuffle operation which come from a consecutively from a zero. The
4633 /// search can start in two different directions, from left or right.
4635 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4636 bool ZerosFromLeft, SelectionDAG &DAG) {
4639 while (i < NumElems) {
4640 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4641 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4642 if (!(Elt.getNode() &&
4643 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4651 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4652 /// MaskE correspond consecutively to elements from one of the vector operands,
4653 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4655 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4656 int OpIdx, int NumElems, unsigned &OpNum) {
4657 bool SeenV1 = false;
4658 bool SeenV2 = false;
4660 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4661 int Idx = SVOp->getMaskElt(i);
4662 // Ignore undef indicies
4671 // Only accept consecutive elements from the same vector
4672 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4676 OpNum = SeenV1 ? 0 : 1;
4680 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4681 /// logical left shift of a vector.
4682 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4683 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4684 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4685 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4686 false /* check zeros from right */, DAG);
4692 // Considering the elements in the mask that are not consecutive zeros,
4693 // check if they consecutively come from only one of the source vectors.
4695 // V1 = {X, A, B, C} 0
4697 // vector_shuffle V1, V2 <1, 2, 3, X>
4699 if (!isShuffleMaskConsecutive(SVOp,
4700 0, // Mask Start Index
4701 NumElems-NumZeros-1, // Mask End Index
4702 NumZeros, // Where to start looking in the src vector
4703 NumElems, // Number of elements in vector
4704 OpSrc)) // Which source operand ?
4709 ShVal = SVOp->getOperand(OpSrc);
4713 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4714 /// logical left shift of a vector.
4715 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4716 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4717 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4718 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4719 true /* check zeros from left */, DAG);
4725 // Considering the elements in the mask that are not consecutive zeros,
4726 // check if they consecutively come from only one of the source vectors.
4728 // 0 { A, B, X, X } = V2
4730 // vector_shuffle V1, V2 <X, X, 4, 5>
4732 if (!isShuffleMaskConsecutive(SVOp,
4733 NumZeros, // Mask Start Index
4734 NumElems-1, // Mask End Index
4735 0, // Where to start looking in the src vector
4736 NumElems, // Number of elements in vector
4737 OpSrc)) // Which source operand ?
4742 ShVal = SVOp->getOperand(OpSrc);
4746 /// isVectorShift - Returns true if the shuffle can be implemented as a
4747 /// logical left or right shift of a vector.
4748 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4749 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4750 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4751 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4757 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4759 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4760 unsigned NumNonZero, unsigned NumZero,
4762 const TargetLowering &TLI) {
4766 DebugLoc dl = Op.getDebugLoc();
4769 for (unsigned i = 0; i < 16; ++i) {
4770 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4771 if (ThisIsNonZero && First) {
4773 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4775 V = DAG.getUNDEF(MVT::v8i16);
4780 SDValue ThisElt(0, 0), LastElt(0, 0);
4781 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4782 if (LastIsNonZero) {
4783 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4784 MVT::i16, Op.getOperand(i-1));
4786 if (ThisIsNonZero) {
4787 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4788 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4789 ThisElt, DAG.getConstant(8, MVT::i8));
4791 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4795 if (ThisElt.getNode())
4796 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4797 DAG.getIntPtrConstant(i/2));
4801 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4804 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4806 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4807 unsigned NumNonZero, unsigned NumZero,
4809 const TargetLowering &TLI) {
4813 DebugLoc dl = Op.getDebugLoc();
4816 for (unsigned i = 0; i < 8; ++i) {
4817 bool isNonZero = (NonZeros & (1 << i)) != 0;
4821 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4823 V = DAG.getUNDEF(MVT::v8i16);
4826 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4827 MVT::v8i16, V, Op.getOperand(i),
4828 DAG.getIntPtrConstant(i));
4835 /// getVShift - Return a vector logical shift node.
4837 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4838 unsigned NumBits, SelectionDAG &DAG,
4839 const TargetLowering &TLI, DebugLoc dl) {
4840 EVT ShVT = MVT::v2i64;
4841 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4842 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4843 return DAG.getNode(ISD::BITCAST, dl, VT,
4844 DAG.getNode(Opc, dl, ShVT, SrcOp,
4845 DAG.getConstant(NumBits,
4846 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4850 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4851 SelectionDAG &DAG) const {
4853 // Check if the scalar load can be widened into a vector load. And if
4854 // the address is "base + cst" see if the cst can be "absorbed" into
4855 // the shuffle mask.
4856 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4857 SDValue Ptr = LD->getBasePtr();
4858 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4860 EVT PVT = LD->getValueType(0);
4861 if (PVT != MVT::i32 && PVT != MVT::f32)
4866 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4867 FI = FINode->getIndex();
4869 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4870 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4871 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4872 Offset = Ptr.getConstantOperandVal(1);
4873 Ptr = Ptr.getOperand(0);
4878 // FIXME: 256-bit vector instructions don't require a strict alignment,
4879 // improve this code to support it better.
4880 unsigned RequiredAlign = VT.getSizeInBits()/8;
4881 SDValue Chain = LD->getChain();
4882 // Make sure the stack object alignment is at least 16 or 32.
4883 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4884 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4885 if (MFI->isFixedObjectIndex(FI)) {
4886 // Can't change the alignment. FIXME: It's possible to compute
4887 // the exact stack offset and reference FI + adjust offset instead.
4888 // If someone *really* cares about this. That's the way to implement it.
4891 MFI->setObjectAlignment(FI, RequiredAlign);
4895 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4896 // Ptr + (Offset & ~15).
4899 if ((Offset % RequiredAlign) & 3)
4901 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4903 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4904 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4906 int EltNo = (Offset - StartOffset) >> 2;
4907 int NumElems = VT.getVectorNumElements();
4909 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4910 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4911 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4912 LD->getPointerInfo().getWithOffset(StartOffset),
4915 // Canonicalize it to a v4i32 or v8i32 shuffle.
4916 SmallVector<int, 8> Mask;
4917 for (int i = 0; i < NumElems; ++i)
4918 Mask.push_back(EltNo);
4920 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4921 return DAG.getNode(ISD::BITCAST, dl, NVT,
4922 DAG.getVectorShuffle(CanonVT, dl, V1,
4923 DAG.getUNDEF(CanonVT),&Mask[0]));
4929 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4930 /// vector of type 'VT', see if the elements can be replaced by a single large
4931 /// load which has the same value as a build_vector whose operands are 'elts'.
4933 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4935 /// FIXME: we'd also like to handle the case where the last elements are zero
4936 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4937 /// There's even a handy isZeroNode for that purpose.
4938 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4939 DebugLoc &DL, SelectionDAG &DAG) {
4940 EVT EltVT = VT.getVectorElementType();
4941 unsigned NumElems = Elts.size();
4943 LoadSDNode *LDBase = NULL;
4944 unsigned LastLoadedElt = -1U;
4946 // For each element in the initializer, see if we've found a load or an undef.
4947 // If we don't find an initial load element, or later load elements are
4948 // non-consecutive, bail out.
4949 for (unsigned i = 0; i < NumElems; ++i) {
4950 SDValue Elt = Elts[i];
4952 if (!Elt.getNode() ||
4953 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4956 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4958 LDBase = cast<LoadSDNode>(Elt.getNode());
4962 if (Elt.getOpcode() == ISD::UNDEF)
4965 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4966 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4971 // If we have found an entire vector of loads and undefs, then return a large
4972 // load of the entire vector width starting at the base pointer. If we found
4973 // consecutive loads for the low half, generate a vzext_load node.
4974 if (LastLoadedElt == NumElems - 1) {
4975 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4976 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4977 LDBase->getPointerInfo(),
4978 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4979 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4980 LDBase->getPointerInfo(),
4981 LDBase->isVolatile(), LDBase->isNonTemporal(),
4982 LDBase->getAlignment());
4983 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4984 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4985 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4986 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4987 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4989 LDBase->getMemOperand());
4990 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4996 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4997 DebugLoc dl = Op.getDebugLoc();
4999 EVT VT = Op.getValueType();
5000 EVT ExtVT = VT.getVectorElementType();
5001 unsigned NumElems = Op.getNumOperands();
5003 // Vectors containing all zeros can be matched by pxor and xorps later
5004 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5005 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5006 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5007 if (Op.getValueType() == MVT::v4i32 ||
5008 Op.getValueType() == MVT::v8i32)
5011 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
5014 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5015 // vectors or broken into v4i32 operations on 256-bit vectors.
5016 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5017 if (Op.getValueType() == MVT::v4i32)
5020 return getOnesVector(Op.getValueType(), DAG, dl);
5023 unsigned EVTBits = ExtVT.getSizeInBits();
5025 unsigned NumZero = 0;
5026 unsigned NumNonZero = 0;
5027 unsigned NonZeros = 0;
5028 bool IsAllConstants = true;
5029 SmallSet<SDValue, 8> Values;
5030 for (unsigned i = 0; i < NumElems; ++i) {
5031 SDValue Elt = Op.getOperand(i);
5032 if (Elt.getOpcode() == ISD::UNDEF)
5035 if (Elt.getOpcode() != ISD::Constant &&
5036 Elt.getOpcode() != ISD::ConstantFP)
5037 IsAllConstants = false;
5038 if (X86::isZeroNode(Elt))
5041 NonZeros |= (1 << i);
5046 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5047 if (NumNonZero == 0)
5048 return DAG.getUNDEF(VT);
5050 // Special case for single non-zero, non-undef, element.
5051 if (NumNonZero == 1) {
5052 unsigned Idx = CountTrailingZeros_32(NonZeros);
5053 SDValue Item = Op.getOperand(Idx);
5055 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5056 // the value are obviously zero, truncate the value to i32 and do the
5057 // insertion that way. Only do this if the value is non-constant or if the
5058 // value is a constant being inserted into element 0. It is cheaper to do
5059 // a constant pool load than it is to do a movd + shuffle.
5060 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5061 (!IsAllConstants || Idx == 0)) {
5062 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5064 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5065 EVT VecVT = MVT::v4i32;
5066 unsigned VecElts = 4;
5068 // Truncate the value (which may itself be a constant) to i32, and
5069 // convert it to a vector with movd (S2V+shuffle to zero extend).
5070 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5071 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5072 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5073 Subtarget->hasSSE2(), DAG);
5075 // Now we have our 32-bit value zero extended in the low element of
5076 // a vector. If Idx != 0, swizzle it into place.
5078 SmallVector<int, 4> Mask;
5079 Mask.push_back(Idx);
5080 for (unsigned i = 1; i != VecElts; ++i)
5082 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5083 DAG.getUNDEF(Item.getValueType()),
5086 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5090 // If we have a constant or non-constant insertion into the low element of
5091 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5092 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5093 // depending on what the source datatype is.
5096 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5097 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5098 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5099 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5100 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5101 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
5103 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5104 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5105 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5106 EVT MiddleVT = MVT::v4i32;
5107 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
5108 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5109 Subtarget->hasSSE2(), DAG);
5110 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5114 // Is it a vector logical left shift?
5115 if (NumElems == 2 && Idx == 1 &&
5116 X86::isZeroNode(Op.getOperand(0)) &&
5117 !X86::isZeroNode(Op.getOperand(1))) {
5118 unsigned NumBits = VT.getSizeInBits();
5119 return getVShift(true, VT,
5120 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5121 VT, Op.getOperand(1)),
5122 NumBits/2, DAG, *this, dl);
5125 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5128 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5129 // is a non-constant being inserted into an element other than the low one,
5130 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5131 // movd/movss) to move this into the low element, then shuffle it into
5133 if (EVTBits == 32) {
5134 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5136 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5137 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
5138 Subtarget->hasSSE2(), DAG);
5139 SmallVector<int, 8> MaskVec;
5140 for (unsigned i = 0; i < NumElems; i++)
5141 MaskVec.push_back(i == Idx ? 0 : 1);
5142 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5146 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5147 if (Values.size() == 1) {
5148 if (EVTBits == 32) {
5149 // Instead of a shuffle like this:
5150 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5151 // Check if it's possible to issue this instead.
5152 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5153 unsigned Idx = CountTrailingZeros_32(NonZeros);
5154 SDValue Item = Op.getOperand(Idx);
5155 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5156 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5161 // A vector full of immediates; various special cases are already
5162 // handled, so this is best done with a single constant-pool load.
5166 // For AVX-length vectors, build the individual 128-bit pieces and use
5167 // shuffles to put them in place.
5168 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5169 SmallVector<SDValue, 32> V;
5170 for (unsigned i = 0; i < NumElems; ++i)
5171 V.push_back(Op.getOperand(i));
5173 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5175 // Build both the lower and upper subvector.
5176 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5177 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5180 // Recreate the wider vector with the lower and upper part.
5181 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5182 DAG.getConstant(0, MVT::i32), DAG, dl);
5183 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5187 // Let legalizer expand 2-wide build_vectors.
5188 if (EVTBits == 64) {
5189 if (NumNonZero == 1) {
5190 // One half is zero or undef.
5191 unsigned Idx = CountTrailingZeros_32(NonZeros);
5192 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5193 Op.getOperand(Idx));
5194 return getShuffleVectorZeroOrUndef(V2, Idx, true,
5195 Subtarget->hasSSE2(), DAG);
5200 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5201 if (EVTBits == 8 && NumElems == 16) {
5202 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5204 if (V.getNode()) return V;
5207 if (EVTBits == 16 && NumElems == 8) {
5208 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5210 if (V.getNode()) return V;
5213 // If element VT is == 32 bits, turn it into a number of shuffles.
5214 SmallVector<SDValue, 8> V;
5216 if (NumElems == 4 && NumZero > 0) {
5217 for (unsigned i = 0; i < 4; ++i) {
5218 bool isZero = !(NonZeros & (1 << i));
5220 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5222 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5225 for (unsigned i = 0; i < 2; ++i) {
5226 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5229 V[i] = V[i*2]; // Must be a zero vector.
5232 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5235 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5238 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5243 SmallVector<int, 8> MaskVec;
5244 bool Reverse = (NonZeros & 0x3) == 2;
5245 for (unsigned i = 0; i < 2; ++i)
5246 MaskVec.push_back(Reverse ? 1-i : i);
5247 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5248 for (unsigned i = 0; i < 2; ++i)
5249 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5250 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5253 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5254 // Check for a build vector of consecutive loads.
5255 for (unsigned i = 0; i < NumElems; ++i)
5256 V[i] = Op.getOperand(i);
5258 // Check for elements which are consecutive loads.
5259 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5263 // For SSE 4.1, use insertps to put the high elements into the low element.
5264 if (getSubtarget()->hasSSE41()) {
5266 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5267 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5269 Result = DAG.getUNDEF(VT);
5271 for (unsigned i = 1; i < NumElems; ++i) {
5272 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5273 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5274 Op.getOperand(i), DAG.getIntPtrConstant(i));
5279 // Otherwise, expand into a number of unpckl*, start by extending each of
5280 // our (non-undef) elements to the full vector width with the element in the
5281 // bottom slot of the vector (which generates no code for SSE).
5282 for (unsigned i = 0; i < NumElems; ++i) {
5283 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5284 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5286 V[i] = DAG.getUNDEF(VT);
5289 // Next, we iteratively mix elements, e.g. for v4f32:
5290 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5291 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5292 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5293 unsigned EltStride = NumElems >> 1;
5294 while (EltStride != 0) {
5295 for (unsigned i = 0; i < EltStride; ++i) {
5296 // If V[i+EltStride] is undef and this is the first round of mixing,
5297 // then it is safe to just drop this shuffle: V[i] is already in the
5298 // right place, the one element (since it's the first round) being
5299 // inserted as undef can be dropped. This isn't safe for successive
5300 // rounds because they will permute elements within both vectors.
5301 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5302 EltStride == NumElems/2)
5305 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5314 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5315 // them in a MMX register. This is better than doing a stack convert.
5316 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5317 DebugLoc dl = Op.getDebugLoc();
5318 EVT ResVT = Op.getValueType();
5320 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5321 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5323 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5324 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5325 InVec = Op.getOperand(1);
5326 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5327 unsigned NumElts = ResVT.getVectorNumElements();
5328 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5329 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5330 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5332 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5333 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5334 Mask[0] = 0; Mask[1] = 2;
5335 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5337 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5340 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5341 // to create 256-bit vectors from two other 128-bit ones.
5342 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5343 DebugLoc dl = Op.getDebugLoc();
5344 EVT ResVT = Op.getValueType();
5346 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5348 SDValue V1 = Op.getOperand(0);
5349 SDValue V2 = Op.getOperand(1);
5350 unsigned NumElems = ResVT.getVectorNumElements();
5352 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5353 DAG.getConstant(0, MVT::i32), DAG, dl);
5354 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5359 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5360 EVT ResVT = Op.getValueType();
5362 assert(Op.getNumOperands() == 2);
5363 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5364 "Unsupported CONCAT_VECTORS for value type");
5366 // We support concatenate two MMX registers and place them in a MMX register.
5367 // This is better than doing a stack convert.
5368 if (ResVT.is128BitVector())
5369 return LowerMMXCONCAT_VECTORS(Op, DAG);
5371 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5372 // from two other 128-bit ones.
5373 return LowerAVXCONCAT_VECTORS(Op, DAG);
5376 // v8i16 shuffles - Prefer shuffles in the following order:
5377 // 1. [all] pshuflw, pshufhw, optional move
5378 // 2. [ssse3] 1 x pshufb
5379 // 3. [ssse3] 2 x pshufb + 1 x por
5380 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5382 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5383 SelectionDAG &DAG) const {
5384 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5385 SDValue V1 = SVOp->getOperand(0);
5386 SDValue V2 = SVOp->getOperand(1);
5387 DebugLoc dl = SVOp->getDebugLoc();
5388 SmallVector<int, 8> MaskVals;
5390 // Determine if more than 1 of the words in each of the low and high quadwords
5391 // of the result come from the same quadword of one of the two inputs. Undef
5392 // mask values count as coming from any quadword, for better codegen.
5393 SmallVector<unsigned, 4> LoQuad(4);
5394 SmallVector<unsigned, 4> HiQuad(4);
5395 BitVector InputQuads(4);
5396 for (unsigned i = 0; i < 8; ++i) {
5397 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
5398 int EltIdx = SVOp->getMaskElt(i);
5399 MaskVals.push_back(EltIdx);
5408 InputQuads.set(EltIdx / 4);
5411 int BestLoQuad = -1;
5412 unsigned MaxQuad = 1;
5413 for (unsigned i = 0; i < 4; ++i) {
5414 if (LoQuad[i] > MaxQuad) {
5416 MaxQuad = LoQuad[i];
5420 int BestHiQuad = -1;
5422 for (unsigned i = 0; i < 4; ++i) {
5423 if (HiQuad[i] > MaxQuad) {
5425 MaxQuad = HiQuad[i];
5429 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5430 // of the two input vectors, shuffle them into one input vector so only a
5431 // single pshufb instruction is necessary. If There are more than 2 input
5432 // quads, disable the next transformation since it does not help SSSE3.
5433 bool V1Used = InputQuads[0] || InputQuads[1];
5434 bool V2Used = InputQuads[2] || InputQuads[3];
5435 if (Subtarget->hasSSSE3()) {
5436 if (InputQuads.count() == 2 && V1Used && V2Used) {
5437 BestLoQuad = InputQuads.find_first();
5438 BestHiQuad = InputQuads.find_next(BestLoQuad);
5440 if (InputQuads.count() > 2) {
5446 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5447 // the shuffle mask. If a quad is scored as -1, that means that it contains
5448 // words from all 4 input quadwords.
5450 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5451 SmallVector<int, 8> MaskV;
5452 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5453 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5454 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5455 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5456 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5457 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5459 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5460 // source words for the shuffle, to aid later transformations.
5461 bool AllWordsInNewV = true;
5462 bool InOrder[2] = { true, true };
5463 for (unsigned i = 0; i != 8; ++i) {
5464 int idx = MaskVals[i];
5466 InOrder[i/4] = false;
5467 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5469 AllWordsInNewV = false;
5473 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5474 if (AllWordsInNewV) {
5475 for (int i = 0; i != 8; ++i) {
5476 int idx = MaskVals[i];
5479 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5480 if ((idx != i) && idx < 4)
5482 if ((idx != i) && idx > 3)
5491 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5492 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5493 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5494 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5495 unsigned TargetMask = 0;
5496 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5497 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5498 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5499 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5500 V1 = NewV.getOperand(0);
5501 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5505 // If we have SSSE3, and all words of the result are from 1 input vector,
5506 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5507 // is present, fall back to case 4.
5508 if (Subtarget->hasSSSE3()) {
5509 SmallVector<SDValue,16> pshufbMask;
5511 // If we have elements from both input vectors, set the high bit of the
5512 // shuffle mask element to zero out elements that come from V2 in the V1
5513 // mask, and elements that come from V1 in the V2 mask, so that the two
5514 // results can be OR'd together.
5515 bool TwoInputs = V1Used && V2Used;
5516 for (unsigned i = 0; i != 8; ++i) {
5517 int EltIdx = MaskVals[i] * 2;
5518 if (TwoInputs && (EltIdx >= 16)) {
5519 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5520 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5523 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5524 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5526 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5527 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5528 DAG.getNode(ISD::BUILD_VECTOR, dl,
5529 MVT::v16i8, &pshufbMask[0], 16));
5531 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5533 // Calculate the shuffle mask for the second input, shuffle it, and
5534 // OR it with the first shuffled input.
5536 for (unsigned i = 0; i != 8; ++i) {
5537 int EltIdx = MaskVals[i] * 2;
5539 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5540 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5543 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5544 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5546 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5547 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5548 DAG.getNode(ISD::BUILD_VECTOR, dl,
5549 MVT::v16i8, &pshufbMask[0], 16));
5550 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5551 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5554 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5555 // and update MaskVals with new element order.
5556 BitVector InOrder(8);
5557 if (BestLoQuad >= 0) {
5558 SmallVector<int, 8> MaskV;
5559 for (int i = 0; i != 4; ++i) {
5560 int idx = MaskVals[i];
5562 MaskV.push_back(-1);
5564 } else if ((idx / 4) == BestLoQuad) {
5565 MaskV.push_back(idx & 3);
5568 MaskV.push_back(-1);
5571 for (unsigned i = 4; i != 8; ++i)
5573 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5576 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5577 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5579 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5583 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5584 // and update MaskVals with the new element order.
5585 if (BestHiQuad >= 0) {
5586 SmallVector<int, 8> MaskV;
5587 for (unsigned i = 0; i != 4; ++i)
5589 for (unsigned i = 4; i != 8; ++i) {
5590 int idx = MaskVals[i];
5592 MaskV.push_back(-1);
5594 } else if ((idx / 4) == BestHiQuad) {
5595 MaskV.push_back((idx & 3) + 4);
5598 MaskV.push_back(-1);
5601 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5604 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5605 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5607 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5611 // In case BestHi & BestLo were both -1, which means each quadword has a word
5612 // from each of the four input quadwords, calculate the InOrder bitvector now
5613 // before falling through to the insert/extract cleanup.
5614 if (BestLoQuad == -1 && BestHiQuad == -1) {
5616 for (int i = 0; i != 8; ++i)
5617 if (MaskVals[i] < 0 || MaskVals[i] == i)
5621 // The other elements are put in the right place using pextrw and pinsrw.
5622 for (unsigned i = 0; i != 8; ++i) {
5625 int EltIdx = MaskVals[i];
5628 SDValue ExtOp = (EltIdx < 8)
5629 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5630 DAG.getIntPtrConstant(EltIdx))
5631 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5632 DAG.getIntPtrConstant(EltIdx - 8));
5633 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5634 DAG.getIntPtrConstant(i));
5639 // v16i8 shuffles - Prefer shuffles in the following order:
5640 // 1. [ssse3] 1 x pshufb
5641 // 2. [ssse3] 2 x pshufb + 1 x por
5642 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5644 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5646 const X86TargetLowering &TLI) {
5647 SDValue V1 = SVOp->getOperand(0);
5648 SDValue V2 = SVOp->getOperand(1);
5649 DebugLoc dl = SVOp->getDebugLoc();
5650 SmallVector<int, 16> MaskVals;
5651 SVOp->getMask(MaskVals);
5653 // If we have SSSE3, case 1 is generated when all result bytes come from
5654 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5655 // present, fall back to case 3.
5656 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5659 for (unsigned i = 0; i < 16; ++i) {
5660 int EltIdx = MaskVals[i];
5669 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5670 if (TLI.getSubtarget()->hasSSSE3()) {
5671 SmallVector<SDValue,16> pshufbMask;
5673 // If all result elements are from one input vector, then only translate
5674 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5676 // Otherwise, we have elements from both input vectors, and must zero out
5677 // elements that come from V2 in the first mask, and V1 in the second mask
5678 // so that we can OR them together.
5679 bool TwoInputs = !(V1Only || V2Only);
5680 for (unsigned i = 0; i != 16; ++i) {
5681 int EltIdx = MaskVals[i];
5682 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5683 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5686 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5688 // If all the elements are from V2, assign it to V1 and return after
5689 // building the first pshufb.
5692 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5693 DAG.getNode(ISD::BUILD_VECTOR, dl,
5694 MVT::v16i8, &pshufbMask[0], 16));
5698 // Calculate the shuffle mask for the second input, shuffle it, and
5699 // OR it with the first shuffled input.
5701 for (unsigned i = 0; i != 16; ++i) {
5702 int EltIdx = MaskVals[i];
5704 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5707 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5709 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5710 DAG.getNode(ISD::BUILD_VECTOR, dl,
5711 MVT::v16i8, &pshufbMask[0], 16));
5712 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5715 // No SSSE3 - Calculate in place words and then fix all out of place words
5716 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5717 // the 16 different words that comprise the two doublequadword input vectors.
5718 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5719 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5720 SDValue NewV = V2Only ? V2 : V1;
5721 for (int i = 0; i != 8; ++i) {
5722 int Elt0 = MaskVals[i*2];
5723 int Elt1 = MaskVals[i*2+1];
5725 // This word of the result is all undef, skip it.
5726 if (Elt0 < 0 && Elt1 < 0)
5729 // This word of the result is already in the correct place, skip it.
5730 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5732 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5735 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5736 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5739 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5740 // using a single extract together, load it and store it.
5741 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5742 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5743 DAG.getIntPtrConstant(Elt1 / 2));
5744 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5745 DAG.getIntPtrConstant(i));
5749 // If Elt1 is defined, extract it from the appropriate source. If the
5750 // source byte is not also odd, shift the extracted word left 8 bits
5751 // otherwise clear the bottom 8 bits if we need to do an or.
5753 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5754 DAG.getIntPtrConstant(Elt1 / 2));
5755 if ((Elt1 & 1) == 0)
5756 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5758 TLI.getShiftAmountTy(InsElt.getValueType())));
5760 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5761 DAG.getConstant(0xFF00, MVT::i16));
5763 // If Elt0 is defined, extract it from the appropriate source. If the
5764 // source byte is not also even, shift the extracted word right 8 bits. If
5765 // Elt1 was also defined, OR the extracted values together before
5766 // inserting them in the result.
5768 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5769 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5770 if ((Elt0 & 1) != 0)
5771 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5773 TLI.getShiftAmountTy(InsElt0.getValueType())));
5775 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5776 DAG.getConstant(0x00FF, MVT::i16));
5777 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5780 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5781 DAG.getIntPtrConstant(i));
5783 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5786 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5787 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5788 /// done when every pair / quad of shuffle mask elements point to elements in
5789 /// the right sequence. e.g.
5790 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5792 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5793 SelectionDAG &DAG, DebugLoc dl) {
5794 EVT VT = SVOp->getValueType(0);
5795 SDValue V1 = SVOp->getOperand(0);
5796 SDValue V2 = SVOp->getOperand(1);
5797 unsigned NumElems = VT.getVectorNumElements();
5798 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5800 switch (VT.getSimpleVT().SimpleTy) {
5801 default: assert(false && "Unexpected!");
5802 case MVT::v4f32: NewVT = MVT::v2f64; break;
5803 case MVT::v4i32: NewVT = MVT::v2i64; break;
5804 case MVT::v8i16: NewVT = MVT::v4i32; break;
5805 case MVT::v16i8: NewVT = MVT::v4i32; break;
5808 int Scale = NumElems / NewWidth;
5809 SmallVector<int, 8> MaskVec;
5810 for (unsigned i = 0; i < NumElems; i += Scale) {
5812 for (int j = 0; j < Scale; ++j) {
5813 int EltIdx = SVOp->getMaskElt(i+j);
5817 StartIdx = EltIdx - (EltIdx % Scale);
5818 if (EltIdx != StartIdx + j)
5822 MaskVec.push_back(-1);
5824 MaskVec.push_back(StartIdx / Scale);
5827 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5828 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5829 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5832 /// getVZextMovL - Return a zero-extending vector move low node.
5834 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5835 SDValue SrcOp, SelectionDAG &DAG,
5836 const X86Subtarget *Subtarget, DebugLoc dl) {
5837 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5838 LoadSDNode *LD = NULL;
5839 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5840 LD = dyn_cast<LoadSDNode>(SrcOp);
5842 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5844 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5845 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5846 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5847 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5848 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5850 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5851 return DAG.getNode(ISD::BITCAST, dl, VT,
5852 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5853 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5861 return DAG.getNode(ISD::BITCAST, dl, VT,
5862 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5863 DAG.getNode(ISD::BITCAST, dl,
5867 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5868 /// shuffle node referes to only one lane in the sources.
5869 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5870 EVT VT = SVOp->getValueType(0);
5871 int NumElems = VT.getVectorNumElements();
5872 int HalfSize = NumElems/2;
5873 SmallVector<int, 16> M;
5875 bool MatchA = false, MatchB = false;
5877 for (int l = 0; l < NumElems*2; l += HalfSize) {
5878 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5884 for (int l = 0; l < NumElems*2; l += HalfSize) {
5885 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5891 return MatchA && MatchB;
5894 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5895 /// which could not be matched by any known target speficic shuffle
5897 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5898 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5899 // If each half of a vector shuffle node referes to only one lane in the
5900 // source vectors, extract each used 128-bit lane and shuffle them using
5901 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5902 // the work to the legalizer.
5903 DebugLoc dl = SVOp->getDebugLoc();
5904 EVT VT = SVOp->getValueType(0);
5905 int NumElems = VT.getVectorNumElements();
5906 int HalfSize = NumElems/2;
5908 // Extract the reference for each half
5909 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5910 int FstVecOpNum = 0, SndVecOpNum = 0;
5911 for (int i = 0; i < HalfSize; ++i) {
5912 int Elt = SVOp->getMaskElt(i);
5913 if (SVOp->getMaskElt(i) < 0)
5915 FstVecOpNum = Elt/NumElems;
5916 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5919 for (int i = HalfSize; i < NumElems; ++i) {
5920 int Elt = SVOp->getMaskElt(i);
5921 if (SVOp->getMaskElt(i) < 0)
5923 SndVecOpNum = Elt/NumElems;
5924 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5928 // Extract the subvectors
5929 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5930 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5931 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5932 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5934 // Generate 128-bit shuffles
5935 SmallVector<int, 16> MaskV1, MaskV2;
5936 for (int i = 0; i < HalfSize; ++i) {
5937 int Elt = SVOp->getMaskElt(i);
5938 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5940 for (int i = HalfSize; i < NumElems; ++i) {
5941 int Elt = SVOp->getMaskElt(i);
5942 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5945 EVT NVT = V1.getValueType();
5946 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5947 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5949 // Concatenate the result back
5950 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5951 DAG.getConstant(0, MVT::i32), DAG, dl);
5952 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5959 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5960 /// 4 elements, and match them with several different shuffle types.
5962 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5963 SDValue V1 = SVOp->getOperand(0);
5964 SDValue V2 = SVOp->getOperand(1);
5965 DebugLoc dl = SVOp->getDebugLoc();
5966 EVT VT = SVOp->getValueType(0);
5968 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5970 SmallVector<std::pair<int, int>, 8> Locs;
5972 SmallVector<int, 8> Mask1(4U, -1);
5973 SmallVector<int, 8> PermMask;
5974 SVOp->getMask(PermMask);
5978 for (unsigned i = 0; i != 4; ++i) {
5979 int Idx = PermMask[i];
5981 Locs[i] = std::make_pair(-1, -1);
5983 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5985 Locs[i] = std::make_pair(0, NumLo);
5989 Locs[i] = std::make_pair(1, NumHi);
5991 Mask1[2+NumHi] = Idx;
5997 if (NumLo <= 2 && NumHi <= 2) {
5998 // If no more than two elements come from either vector. This can be
5999 // implemented with two shuffles. First shuffle gather the elements.
6000 // The second shuffle, which takes the first shuffle as both of its
6001 // vector operands, put the elements into the right order.
6002 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6004 SmallVector<int, 8> Mask2(4U, -1);
6006 for (unsigned i = 0; i != 4; ++i) {
6007 if (Locs[i].first == -1)
6010 unsigned Idx = (i < 2) ? 0 : 4;
6011 Idx += Locs[i].first * 2 + Locs[i].second;
6016 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6017 } else if (NumLo == 3 || NumHi == 3) {
6018 // Otherwise, we must have three elements from one vector, call it X, and
6019 // one element from the other, call it Y. First, use a shufps to build an
6020 // intermediate vector with the one element from Y and the element from X
6021 // that will be in the same half in the final destination (the indexes don't
6022 // matter). Then, use a shufps to build the final vector, taking the half
6023 // containing the element from Y from the intermediate, and the other half
6026 // Normalize it so the 3 elements come from V1.
6027 CommuteVectorShuffleMask(PermMask, VT);
6031 // Find the element from V2.
6033 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6034 int Val = PermMask[HiIndex];
6041 Mask1[0] = PermMask[HiIndex];
6043 Mask1[2] = PermMask[HiIndex^1];
6045 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6048 Mask1[0] = PermMask[0];
6049 Mask1[1] = PermMask[1];
6050 Mask1[2] = HiIndex & 1 ? 6 : 4;
6051 Mask1[3] = HiIndex & 1 ? 4 : 6;
6052 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6054 Mask1[0] = HiIndex & 1 ? 2 : 0;
6055 Mask1[1] = HiIndex & 1 ? 0 : 2;
6056 Mask1[2] = PermMask[2];
6057 Mask1[3] = PermMask[3];
6062 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6066 // Break it into (shuffle shuffle_hi, shuffle_lo).
6069 SmallVector<int,8> LoMask(4U, -1);
6070 SmallVector<int,8> HiMask(4U, -1);
6072 SmallVector<int,8> *MaskPtr = &LoMask;
6073 unsigned MaskIdx = 0;
6076 for (unsigned i = 0; i != 4; ++i) {
6083 int Idx = PermMask[i];
6085 Locs[i] = std::make_pair(-1, -1);
6086 } else if (Idx < 4) {
6087 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6088 (*MaskPtr)[LoIdx] = Idx;
6091 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6092 (*MaskPtr)[HiIdx] = Idx;
6097 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6098 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6099 SmallVector<int, 8> MaskOps;
6100 for (unsigned i = 0; i != 4; ++i) {
6101 if (Locs[i].first == -1) {
6102 MaskOps.push_back(-1);
6104 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6105 MaskOps.push_back(Idx);
6108 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6111 static bool MayFoldVectorLoad(SDValue V) {
6112 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6113 V = V.getOperand(0);
6114 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6115 V = V.getOperand(0);
6121 // FIXME: the version above should always be used. Since there's
6122 // a bug where several vector shuffles can't be folded because the
6123 // DAG is not updated during lowering and a node claims to have two
6124 // uses while it only has one, use this version, and let isel match
6125 // another instruction if the load really happens to have more than
6126 // one use. Remove this version after this bug get fixed.
6127 // rdar://8434668, PR8156
6128 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6129 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6130 V = V.getOperand(0);
6131 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6132 V = V.getOperand(0);
6133 if (ISD::isNormalLoad(V.getNode()))
6138 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6139 /// a vector extract, and if both can be later optimized into a single load.
6140 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6141 /// here because otherwise a target specific shuffle node is going to be
6142 /// emitted for this shuffle, and the optimization not done.
6143 /// FIXME: This is probably not the best approach, but fix the problem
6144 /// until the right path is decided.
6146 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6147 const TargetLowering &TLI) {
6148 EVT VT = V.getValueType();
6149 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6151 // Be sure that the vector shuffle is present in a pattern like this:
6152 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6156 SDNode *N = *V.getNode()->use_begin();
6157 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6160 SDValue EltNo = N->getOperand(1);
6161 if (!isa<ConstantSDNode>(EltNo))
6164 // If the bit convert changed the number of elements, it is unsafe
6165 // to examine the mask.
6166 bool HasShuffleIntoBitcast = false;
6167 if (V.getOpcode() == ISD::BITCAST) {
6168 EVT SrcVT = V.getOperand(0).getValueType();
6169 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6171 V = V.getOperand(0);
6172 HasShuffleIntoBitcast = true;
6175 // Select the input vector, guarding against out of range extract vector.
6176 unsigned NumElems = VT.getVectorNumElements();
6177 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6178 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6179 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6181 // Skip one more bit_convert if necessary
6182 if (V.getOpcode() == ISD::BITCAST)
6183 V = V.getOperand(0);
6185 if (ISD::isNormalLoad(V.getNode())) {
6186 // Is the original load suitable?
6187 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6189 // FIXME: avoid the multi-use bug that is preventing lots of
6190 // of foldings to be detected, this is still wrong of course, but
6191 // give the temporary desired behavior, and if it happens that
6192 // the load has real more uses, during isel it will not fold, and
6193 // will generate poor code.
6194 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
6197 if (!HasShuffleIntoBitcast)
6200 // If there's a bitcast before the shuffle, check if the load type and
6201 // alignment is valid.
6202 unsigned Align = LN0->getAlignment();
6204 TLI.getTargetData()->getABITypeAlignment(
6205 VT.getTypeForEVT(*DAG.getContext()));
6207 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6215 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6216 EVT VT = Op.getValueType();
6218 // Canonizalize to v2f64.
6219 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6220 return DAG.getNode(ISD::BITCAST, dl, VT,
6221 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6226 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6228 SDValue V1 = Op.getOperand(0);
6229 SDValue V2 = Op.getOperand(1);
6230 EVT VT = Op.getValueType();
6232 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6234 if (HasSSE2 && VT == MVT::v2f64)
6235 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6238 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
6242 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6243 SDValue V1 = Op.getOperand(0);
6244 SDValue V2 = Op.getOperand(1);
6245 EVT VT = Op.getValueType();
6247 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6248 "unsupported shuffle type");
6250 if (V2.getOpcode() == ISD::UNDEF)
6254 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6257 static inline unsigned getSHUFPOpcode(EVT VT) {
6258 switch(VT.getSimpleVT().SimpleTy) {
6259 case MVT::v8i32: // Use fp unit for int unpack.
6261 case MVT::v4i32: // Use fp unit for int unpack.
6262 case MVT::v4f32: return X86ISD::SHUFPS;
6263 case MVT::v4i64: // Use fp unit for int unpack.
6265 case MVT::v2i64: // Use fp unit for int unpack.
6266 case MVT::v2f64: return X86ISD::SHUFPD;
6268 llvm_unreachable("Unknown type for shufp*");
6274 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6275 SDValue V1 = Op.getOperand(0);
6276 SDValue V2 = Op.getOperand(1);
6277 EVT VT = Op.getValueType();
6278 unsigned NumElems = VT.getVectorNumElements();
6280 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6281 // operand of these instructions is only memory, so check if there's a
6282 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6284 bool CanFoldLoad = false;
6286 // Trivial case, when V2 comes from a load.
6287 if (MayFoldVectorLoad(V2))
6290 // When V1 is a load, it can be folded later into a store in isel, example:
6291 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6293 // (MOVLPSmr addr:$src1, VR128:$src2)
6294 // So, recognize this potential and also use MOVLPS or MOVLPD
6295 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6298 // Both of them can't be memory operations though.
6299 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
6300 CanFoldLoad = false;
6303 if (HasSSE2 && NumElems == 2)
6304 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6307 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6310 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6311 // movl and movlp will both match v2i64, but v2i64 is never matched by
6312 // movl earlier because we make it strict to avoid messing with the movlp load
6313 // folding logic (see the code above getMOVLP call). Match it here then,
6314 // this is horrible, but will stay like this until we move all shuffle
6315 // matching to x86 specific nodes. Note that for the 1st condition all
6316 // types are matched with movsd.
6317 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
6318 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6320 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6323 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6325 // Invert the operand order and use SHUFPS to match it.
6326 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1,
6327 X86::getShuffleSHUFImmediate(SVOp), DAG);
6330 static inline unsigned getUNPCKLOpcode(EVT VT) {
6331 switch(VT.getSimpleVT().SimpleTy) {
6332 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
6333 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
6334 case MVT::v4f32: return X86ISD::UNPCKLPS;
6335 case MVT::v2f64: return X86ISD::UNPCKLPD;
6336 case MVT::v8i32: // Use fp unit for int unpack.
6337 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
6338 case MVT::v4i64: // Use fp unit for int unpack.
6339 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
6340 case MVT::v16i8: return X86ISD::PUNPCKLBW;
6341 case MVT::v8i16: return X86ISD::PUNPCKLWD;
6343 llvm_unreachable("Unknown type for unpckl");
6348 static inline unsigned getUNPCKHOpcode(EVT VT) {
6349 switch(VT.getSimpleVT().SimpleTy) {
6350 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
6351 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
6352 case MVT::v4f32: return X86ISD::UNPCKHPS;
6353 case MVT::v2f64: return X86ISD::UNPCKHPD;
6354 case MVT::v8i32: // Use fp unit for int unpack.
6355 case MVT::v8f32: return X86ISD::VUNPCKHPSY;
6356 case MVT::v4i64: // Use fp unit for int unpack.
6357 case MVT::v4f64: return X86ISD::VUNPCKHPDY;
6358 case MVT::v16i8: return X86ISD::PUNPCKHBW;
6359 case MVT::v8i16: return X86ISD::PUNPCKHWD;
6361 llvm_unreachable("Unknown type for unpckh");
6366 static inline unsigned getVPERMILOpcode(EVT VT) {
6367 switch(VT.getSimpleVT().SimpleTy) {
6369 case MVT::v4f32: return X86ISD::VPERMILPS;
6371 case MVT::v2f64: return X86ISD::VPERMILPD;
6373 case MVT::v8f32: return X86ISD::VPERMILPSY;
6375 case MVT::v4f64: return X86ISD::VPERMILPDY;
6377 llvm_unreachable("Unknown type for vpermil");
6382 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
6383 /// a vbroadcast node. The nodes are suitable whenever we can fold a load coming
6384 /// from a 32 or 64 bit scalar. Update Op to the desired load to be folded.
6385 static bool isVectorBroadcast(SDValue &Op) {
6386 EVT VT = Op.getValueType();
6387 bool Is256 = VT.getSizeInBits() == 256;
6389 assert((VT.getSizeInBits() == 128 || Is256) &&
6390 "Unsupported type for vbroadcast node");
6393 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6394 V = V.getOperand(0);
6396 if (Is256 && !(V.hasOneUse() &&
6397 V.getOpcode() == ISD::INSERT_SUBVECTOR &&
6398 V.getOperand(0).getOpcode() == ISD::UNDEF))
6402 V = V.getOperand(1);
6403 if (V.hasOneUse() && V.getOpcode() != ISD::SCALAR_TO_VECTOR)
6406 // Check the source scalar_to_vector type. 256-bit broadcasts are
6407 // supported for 32/64-bit sizes, while 128-bit ones are only supported
6408 // for 32-bit scalars.
6409 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits();
6410 if (ScalarSize != 32 && ScalarSize != 64)
6412 if (!Is256 && ScalarSize == 64)
6415 V = V.getOperand(0);
6416 if (!MayFoldLoad(V))
6419 // Return the load node
6425 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6426 const TargetLowering &TLI,
6427 const X86Subtarget *Subtarget) {
6428 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6429 EVT VT = Op.getValueType();
6430 DebugLoc dl = Op.getDebugLoc();
6431 SDValue V1 = Op.getOperand(0);
6432 SDValue V2 = Op.getOperand(1);
6434 if (isZeroShuffle(SVOp))
6435 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
6437 // Handle splat operations
6438 if (SVOp->isSplat()) {
6439 unsigned NumElem = VT.getVectorNumElements();
6440 int Size = VT.getSizeInBits();
6441 // Special case, this is the only place now where it's allowed to return
6442 // a vector_shuffle operation without using a target specific node, because
6443 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6444 // this be moved to DAGCombine instead?
6445 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6448 // Use vbroadcast whenever the splat comes from a foldable load
6449 if (Subtarget->hasAVX() && isVectorBroadcast(V1))
6450 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1);
6452 // Handle splats by matching through known shuffle masks
6453 if ((Size == 128 && NumElem <= 4) ||
6454 (Size == 256 && NumElem < 8))
6457 // All remaning splats are promoted to target supported vector shuffles.
6458 return PromoteSplat(SVOp, DAG);
6461 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6463 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6464 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6465 if (NewOp.getNode())
6466 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6467 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6468 // FIXME: Figure out a cleaner way to do this.
6469 // Try to make use of movq to zero out the top part.
6470 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6471 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6472 if (NewOp.getNode()) {
6473 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6474 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6475 DAG, Subtarget, dl);
6477 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6478 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6479 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6480 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6481 DAG, Subtarget, dl);
6488 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6489 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6490 SDValue V1 = Op.getOperand(0);
6491 SDValue V2 = Op.getOperand(1);
6492 EVT VT = Op.getValueType();
6493 DebugLoc dl = Op.getDebugLoc();
6494 unsigned NumElems = VT.getVectorNumElements();
6495 bool isMMX = VT.getSizeInBits() == 64;
6496 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6497 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6498 bool V1IsSplat = false;
6499 bool V2IsSplat = false;
6500 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
6501 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
6502 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
6503 MachineFunction &MF = DAG.getMachineFunction();
6504 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6506 // Shuffle operations on MMX not supported.
6510 // Vector shuffle lowering takes 3 steps:
6512 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6513 // narrowing and commutation of operands should be handled.
6514 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6516 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6517 // so the shuffle can be broken into other shuffles and the legalizer can
6518 // try the lowering again.
6520 // The general ideia is that no vector_shuffle operation should be left to
6521 // be matched during isel, all of them must be converted to a target specific
6524 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6525 // narrowing and commutation of operands should be handled. The actual code
6526 // doesn't include all of those, work in progress...
6527 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6528 if (NewOp.getNode())
6531 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6532 // unpckh_undef). Only use pshufd if speed is more important than size.
6533 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
6534 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6535 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
6536 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6538 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
6539 RelaxedMayFoldVectorLoad(V1))
6540 return getMOVDDup(Op, dl, V1, DAG);
6542 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6543 return getMOVHighToLow(Op, dl, DAG);
6545 // Use to match splats
6546 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
6547 (VT == MVT::v2f64 || VT == MVT::v2i64))
6548 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6550 if (X86::isPSHUFDMask(SVOp)) {
6551 // The actual implementation will match the mask in the if above and then
6552 // during isel it can match several different instructions, not only pshufd
6553 // as its name says, sad but true, emulate the behavior for now...
6554 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6555 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6557 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6559 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6560 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6562 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1,
6566 // Check if this can be converted into a logical shift.
6567 bool isLeft = false;
6570 bool isShift = getSubtarget()->hasSSE2() &&
6571 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6572 if (isShift && ShVal.hasOneUse()) {
6573 // If the shifted value has multiple uses, it may be cheaper to use
6574 // v_set0 + movlhps or movhlps, etc.
6575 EVT EltVT = VT.getVectorElementType();
6576 ShAmt *= EltVT.getSizeInBits();
6577 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6580 if (X86::isMOVLMask(SVOp)) {
6583 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6584 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6585 if (!X86::isMOVLPMask(SVOp)) {
6586 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6587 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6589 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6590 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6594 // FIXME: fold these into legal mask.
6595 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
6596 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6598 if (X86::isMOVHLPSMask(SVOp))
6599 return getMOVHighToLow(Op, dl, DAG);
6601 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6602 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6604 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6605 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6607 if (X86::isMOVLPMask(SVOp))
6608 return getMOVLP(Op, dl, DAG, HasSSE2);
6610 if (ShouldXformToMOVHLPS(SVOp) ||
6611 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6612 return CommuteVectorShuffle(SVOp, DAG);
6615 // No better options. Use a vshl / vsrl.
6616 EVT EltVT = VT.getVectorElementType();
6617 ShAmt *= EltVT.getSizeInBits();
6618 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6621 bool Commuted = false;
6622 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6623 // 1,1,1,1 -> v8i16 though.
6624 V1IsSplat = isSplatVector(V1.getNode());
6625 V2IsSplat = isSplatVector(V2.getNode());
6627 // Canonicalize the splat or undef, if present, to be on the RHS.
6628 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
6629 Op = CommuteVectorShuffle(SVOp, DAG);
6630 SVOp = cast<ShuffleVectorSDNode>(Op);
6631 V1 = SVOp->getOperand(0);
6632 V2 = SVOp->getOperand(1);
6633 std::swap(V1IsSplat, V2IsSplat);
6634 std::swap(V1IsUndef, V2IsUndef);
6638 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
6639 // Shuffling low element of v1 into undef, just return v1.
6642 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6643 // the instruction selector will not match, so get a canonical MOVL with
6644 // swapped operands to undo the commute.
6645 return getMOVL(DAG, dl, VT, V2, V1);
6648 if (X86::isUNPCKLMask(SVOp))
6649 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
6651 if (X86::isUNPCKHMask(SVOp))
6652 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
6655 // Normalize mask so all entries that point to V2 points to its first
6656 // element then try to match unpck{h|l} again. If match, return a
6657 // new vector_shuffle with the corrected mask.
6658 SDValue NewMask = NormalizeMask(SVOp, DAG);
6659 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6660 if (NSVOp != SVOp) {
6661 if (X86::isUNPCKLMask(NSVOp, true)) {
6663 } else if (X86::isUNPCKHMask(NSVOp, true)) {
6670 // Commute is back and try unpck* again.
6671 // FIXME: this seems wrong.
6672 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6673 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6675 if (X86::isUNPCKLMask(NewSVOp))
6676 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
6678 if (X86::isUNPCKHMask(NewSVOp))
6679 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
6682 // Normalize the node to match x86 shuffle ops if needed
6683 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
6684 return CommuteVectorShuffle(SVOp, DAG);
6686 // The checks below are all present in isShuffleMaskLegal, but they are
6687 // inlined here right now to enable us to directly emit target specific
6688 // nodes, and remove one by one until they don't return Op anymore.
6689 SmallVector<int, 16> M;
6692 if (isPALIGNRMask(M, VT, HasSSSE3))
6693 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6694 X86::getShufflePALIGNRImmediate(SVOp),
6697 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6698 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6699 if (VT == MVT::v2f64)
6700 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
6701 if (VT == MVT::v2i64)
6702 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
6705 if (isPSHUFHWMask(M, VT))
6706 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6707 X86::getShufflePSHUFHWImmediate(SVOp),
6710 if (isPSHUFLWMask(M, VT))
6711 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6712 X86::getShufflePSHUFLWImmediate(SVOp),
6715 if (isSHUFPMask(M, VT))
6716 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6717 X86::getShuffleSHUFImmediate(SVOp), DAG);
6719 if (X86::isUNPCKL_v_undef_Mask(SVOp))
6720 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6721 if (X86::isUNPCKH_v_undef_Mask(SVOp))
6722 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6724 //===--------------------------------------------------------------------===//
6725 // Generate target specific nodes for 128 or 256-bit shuffles only
6726 // supported in the AVX instruction set.
6729 // Handle VMOVDDUPY permutations
6730 if (isMOVDDUPYMask(SVOp, Subtarget))
6731 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6733 // Handle VPERMILPS* permutations
6734 if (isVPERMILPSMask(M, VT, Subtarget))
6735 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6736 getShuffleVPERMILPSImmediate(SVOp), DAG);
6738 // Handle VPERMILPD* permutations
6739 if (isVPERMILPDMask(M, VT, Subtarget))
6740 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6741 getShuffleVPERMILPDImmediate(SVOp), DAG);
6743 // Handle VPERM2F128 permutations
6744 if (isVPERM2F128Mask(M, VT, Subtarget))
6745 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2,
6746 getShuffleVPERM2F128Immediate(SVOp), DAG);
6748 // Handle VSHUFPSY permutations
6749 if (isVSHUFPSYMask(M, VT, Subtarget))
6750 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6751 getShuffleVSHUFPSYImmediate(SVOp), DAG);
6753 // Handle VSHUFPDY permutations
6754 if (isVSHUFPDYMask(M, VT, Subtarget))
6755 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6756 getShuffleVSHUFPDYImmediate(SVOp), DAG);
6758 //===--------------------------------------------------------------------===//
6759 // Since no target specific shuffle was selected for this generic one,
6760 // lower it into other known shuffles. FIXME: this isn't true yet, but
6761 // this is the plan.
6764 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6765 if (VT == MVT::v8i16) {
6766 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6767 if (NewOp.getNode())
6771 if (VT == MVT::v16i8) {
6772 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6773 if (NewOp.getNode())
6777 // Handle all 128-bit wide vectors with 4 elements, and match them with
6778 // several different shuffle types.
6779 if (NumElems == 4 && VT.getSizeInBits() == 128)
6780 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6782 // Handle general 256-bit shuffles
6783 if (VT.is256BitVector())
6784 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6790 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6791 SelectionDAG &DAG) const {
6792 EVT VT = Op.getValueType();
6793 DebugLoc dl = Op.getDebugLoc();
6795 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6798 if (VT.getSizeInBits() == 8) {
6799 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6800 Op.getOperand(0), Op.getOperand(1));
6801 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6802 DAG.getValueType(VT));
6803 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6804 } else if (VT.getSizeInBits() == 16) {
6805 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6806 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6808 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6809 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6810 DAG.getNode(ISD::BITCAST, dl,
6814 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6815 Op.getOperand(0), Op.getOperand(1));
6816 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6817 DAG.getValueType(VT));
6818 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6819 } else if (VT == MVT::f32) {
6820 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6821 // the result back to FR32 register. It's only worth matching if the
6822 // result has a single use which is a store or a bitcast to i32. And in
6823 // the case of a store, it's not worth it if the index is a constant 0,
6824 // because a MOVSSmr can be used instead, which is smaller and faster.
6825 if (!Op.hasOneUse())
6827 SDNode *User = *Op.getNode()->use_begin();
6828 if ((User->getOpcode() != ISD::STORE ||
6829 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6830 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6831 (User->getOpcode() != ISD::BITCAST ||
6832 User->getValueType(0) != MVT::i32))
6834 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6835 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6838 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6839 } else if (VT == MVT::i32) {
6840 // ExtractPS works with constant index.
6841 if (isa<ConstantSDNode>(Op.getOperand(1)))
6849 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6850 SelectionDAG &DAG) const {
6851 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6854 SDValue Vec = Op.getOperand(0);
6855 EVT VecVT = Vec.getValueType();
6857 // If this is a 256-bit vector result, first extract the 128-bit vector and
6858 // then extract the element from the 128-bit vector.
6859 if (VecVT.getSizeInBits() == 256) {
6860 DebugLoc dl = Op.getNode()->getDebugLoc();
6861 unsigned NumElems = VecVT.getVectorNumElements();
6862 SDValue Idx = Op.getOperand(1);
6863 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6865 // Get the 128-bit vector.
6866 bool Upper = IdxVal >= NumElems/2;
6867 Vec = Extract128BitVector(Vec,
6868 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6870 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6871 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6874 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6876 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
6877 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6882 EVT VT = Op.getValueType();
6883 DebugLoc dl = Op.getDebugLoc();
6884 // TODO: handle v16i8.
6885 if (VT.getSizeInBits() == 16) {
6886 SDValue Vec = Op.getOperand(0);
6887 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6889 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6890 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6891 DAG.getNode(ISD::BITCAST, dl,
6894 // Transform it so it match pextrw which produces a 32-bit result.
6895 EVT EltVT = MVT::i32;
6896 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6897 Op.getOperand(0), Op.getOperand(1));
6898 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6899 DAG.getValueType(VT));
6900 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6901 } else if (VT.getSizeInBits() == 32) {
6902 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6906 // SHUFPS the element to the lowest double word, then movss.
6907 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6908 EVT VVT = Op.getOperand(0).getValueType();
6909 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6910 DAG.getUNDEF(VVT), Mask);
6911 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6912 DAG.getIntPtrConstant(0));
6913 } else if (VT.getSizeInBits() == 64) {
6914 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6915 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6916 // to match extract_elt for f64.
6917 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6921 // UNPCKHPD the element to the lowest double word, then movsd.
6922 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6923 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6924 int Mask[2] = { 1, -1 };
6925 EVT VVT = Op.getOperand(0).getValueType();
6926 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6927 DAG.getUNDEF(VVT), Mask);
6928 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6929 DAG.getIntPtrConstant(0));
6936 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6937 SelectionDAG &DAG) const {
6938 EVT VT = Op.getValueType();
6939 EVT EltVT = VT.getVectorElementType();
6940 DebugLoc dl = Op.getDebugLoc();
6942 SDValue N0 = Op.getOperand(0);
6943 SDValue N1 = Op.getOperand(1);
6944 SDValue N2 = Op.getOperand(2);
6946 if (VT.getSizeInBits() == 256)
6949 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6950 isa<ConstantSDNode>(N2)) {
6952 if (VT == MVT::v8i16)
6953 Opc = X86ISD::PINSRW;
6954 else if (VT == MVT::v16i8)
6955 Opc = X86ISD::PINSRB;
6957 Opc = X86ISD::PINSRB;
6959 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6961 if (N1.getValueType() != MVT::i32)
6962 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6963 if (N2.getValueType() != MVT::i32)
6964 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6965 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6966 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6967 // Bits [7:6] of the constant are the source select. This will always be
6968 // zero here. The DAG Combiner may combine an extract_elt index into these
6969 // bits. For example (insert (extract, 3), 2) could be matched by putting
6970 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6971 // Bits [5:4] of the constant are the destination select. This is the
6972 // value of the incoming immediate.
6973 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6974 // combine either bitwise AND or insert of float 0.0 to set these bits.
6975 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6976 // Create this as a scalar to vector..
6977 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6978 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6979 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
6980 // PINSR* works with constant index.
6987 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6988 EVT VT = Op.getValueType();
6989 EVT EltVT = VT.getVectorElementType();
6991 DebugLoc dl = Op.getDebugLoc();
6992 SDValue N0 = Op.getOperand(0);
6993 SDValue N1 = Op.getOperand(1);
6994 SDValue N2 = Op.getOperand(2);
6996 // If this is a 256-bit vector result, first extract the 128-bit vector,
6997 // insert the element into the extracted half and then place it back.
6998 if (VT.getSizeInBits() == 256) {
6999 if (!isa<ConstantSDNode>(N2))
7002 // Get the desired 128-bit vector half.
7003 unsigned NumElems = VT.getVectorNumElements();
7004 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7005 bool Upper = IdxVal >= NumElems/2;
7006 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
7007 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
7009 // Insert the element into the desired half.
7010 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
7011 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
7013 // Insert the changed part back to the 256-bit vector
7014 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
7017 if (Subtarget->hasSSE41() || Subtarget->hasAVX())
7018 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7020 if (EltVT == MVT::i8)
7023 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7024 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7025 // as its second argument.
7026 if (N1.getValueType() != MVT::i32)
7027 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7028 if (N2.getValueType() != MVT::i32)
7029 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7030 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7036 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7037 LLVMContext *Context = DAG.getContext();
7038 DebugLoc dl = Op.getDebugLoc();
7039 EVT OpVT = Op.getValueType();
7041 // If this is a 256-bit vector result, first insert into a 128-bit
7042 // vector and then insert into the 256-bit vector.
7043 if (OpVT.getSizeInBits() > 128) {
7044 // Insert into a 128-bit vector.
7045 EVT VT128 = EVT::getVectorVT(*Context,
7046 OpVT.getVectorElementType(),
7047 OpVT.getVectorNumElements() / 2);
7049 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7051 // Insert the 128-bit vector.
7052 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
7053 DAG.getConstant(0, MVT::i32),
7057 if (Op.getValueType() == MVT::v1i64 &&
7058 Op.getOperand(0).getValueType() == MVT::i64)
7059 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7061 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7062 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7063 "Expected an SSE type!");
7064 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7065 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7068 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7069 // a simple subregister reference or explicit instructions to grab
7070 // upper bits of a vector.
7072 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7073 if (Subtarget->hasAVX()) {
7074 DebugLoc dl = Op.getNode()->getDebugLoc();
7075 SDValue Vec = Op.getNode()->getOperand(0);
7076 SDValue Idx = Op.getNode()->getOperand(1);
7078 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7079 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7080 return Extract128BitVector(Vec, Idx, DAG, dl);
7086 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7087 // simple superregister reference or explicit instructions to insert
7088 // the upper bits of a vector.
7090 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7091 if (Subtarget->hasAVX()) {
7092 DebugLoc dl = Op.getNode()->getDebugLoc();
7093 SDValue Vec = Op.getNode()->getOperand(0);
7094 SDValue SubVec = Op.getNode()->getOperand(1);
7095 SDValue Idx = Op.getNode()->getOperand(2);
7097 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7098 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7099 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7105 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7106 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7107 // one of the above mentioned nodes. It has to be wrapped because otherwise
7108 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7109 // be used to form addressing mode. These wrapped nodes will be selected
7112 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7113 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7115 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7117 unsigned char OpFlag = 0;
7118 unsigned WrapperKind = X86ISD::Wrapper;
7119 CodeModel::Model M = getTargetMachine().getCodeModel();
7121 if (Subtarget->isPICStyleRIPRel() &&
7122 (M == CodeModel::Small || M == CodeModel::Kernel))
7123 WrapperKind = X86ISD::WrapperRIP;
7124 else if (Subtarget->isPICStyleGOT())
7125 OpFlag = X86II::MO_GOTOFF;
7126 else if (Subtarget->isPICStyleStubPIC())
7127 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7129 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7131 CP->getOffset(), OpFlag);
7132 DebugLoc DL = CP->getDebugLoc();
7133 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7134 // With PIC, the address is actually $g + Offset.
7136 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7137 DAG.getNode(X86ISD::GlobalBaseReg,
7138 DebugLoc(), getPointerTy()),
7145 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7146 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7148 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7150 unsigned char OpFlag = 0;
7151 unsigned WrapperKind = X86ISD::Wrapper;
7152 CodeModel::Model M = getTargetMachine().getCodeModel();
7154 if (Subtarget->isPICStyleRIPRel() &&
7155 (M == CodeModel::Small || M == CodeModel::Kernel))
7156 WrapperKind = X86ISD::WrapperRIP;
7157 else if (Subtarget->isPICStyleGOT())
7158 OpFlag = X86II::MO_GOTOFF;
7159 else if (Subtarget->isPICStyleStubPIC())
7160 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7162 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7164 DebugLoc DL = JT->getDebugLoc();
7165 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7167 // With PIC, the address is actually $g + Offset.
7169 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7170 DAG.getNode(X86ISD::GlobalBaseReg,
7171 DebugLoc(), getPointerTy()),
7178 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7179 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7181 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7183 unsigned char OpFlag = 0;
7184 unsigned WrapperKind = X86ISD::Wrapper;
7185 CodeModel::Model M = getTargetMachine().getCodeModel();
7187 if (Subtarget->isPICStyleRIPRel() &&
7188 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7189 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7190 OpFlag = X86II::MO_GOTPCREL;
7191 WrapperKind = X86ISD::WrapperRIP;
7192 } else if (Subtarget->isPICStyleGOT()) {
7193 OpFlag = X86II::MO_GOT;
7194 } else if (Subtarget->isPICStyleStubPIC()) {
7195 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7196 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7197 OpFlag = X86II::MO_DARWIN_NONLAZY;
7200 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7202 DebugLoc DL = Op.getDebugLoc();
7203 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7206 // With PIC, the address is actually $g + Offset.
7207 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7208 !Subtarget->is64Bit()) {
7209 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7210 DAG.getNode(X86ISD::GlobalBaseReg,
7211 DebugLoc(), getPointerTy()),
7215 // For symbols that require a load from a stub to get the address, emit the
7217 if (isGlobalStubReference(OpFlag))
7218 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7219 MachinePointerInfo::getGOT(), false, false, 0);
7225 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7226 // Create the TargetBlockAddressAddress node.
7227 unsigned char OpFlags =
7228 Subtarget->ClassifyBlockAddressReference();
7229 CodeModel::Model M = getTargetMachine().getCodeModel();
7230 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7231 DebugLoc dl = Op.getDebugLoc();
7232 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7233 /*isTarget=*/true, OpFlags);
7235 if (Subtarget->isPICStyleRIPRel() &&
7236 (M == CodeModel::Small || M == CodeModel::Kernel))
7237 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7239 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7241 // With PIC, the address is actually $g + Offset.
7242 if (isGlobalRelativeToPICBase(OpFlags)) {
7243 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7244 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7252 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7254 SelectionDAG &DAG) const {
7255 // Create the TargetGlobalAddress node, folding in the constant
7256 // offset if it is legal.
7257 unsigned char OpFlags =
7258 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7259 CodeModel::Model M = getTargetMachine().getCodeModel();
7261 if (OpFlags == X86II::MO_NO_FLAG &&
7262 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7263 // A direct static reference to a global.
7264 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7267 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7270 if (Subtarget->isPICStyleRIPRel() &&
7271 (M == CodeModel::Small || M == CodeModel::Kernel))
7272 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7274 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7276 // With PIC, the address is actually $g + Offset.
7277 if (isGlobalRelativeToPICBase(OpFlags)) {
7278 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7279 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7283 // For globals that require a load from a stub to get the address, emit the
7285 if (isGlobalStubReference(OpFlags))
7286 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7287 MachinePointerInfo::getGOT(), false, false, 0);
7289 // If there was a non-zero offset that we didn't fold, create an explicit
7292 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7293 DAG.getConstant(Offset, getPointerTy()));
7299 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7300 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7301 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7302 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7306 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7307 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7308 unsigned char OperandFlags) {
7309 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7310 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7311 DebugLoc dl = GA->getDebugLoc();
7312 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7313 GA->getValueType(0),
7317 SDValue Ops[] = { Chain, TGA, *InFlag };
7318 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7320 SDValue Ops[] = { Chain, TGA };
7321 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7324 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7325 MFI->setAdjustsStack(true);
7327 SDValue Flag = Chain.getValue(1);
7328 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7331 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7333 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7336 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7337 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7338 DAG.getNode(X86ISD::GlobalBaseReg,
7339 DebugLoc(), PtrVT), InFlag);
7340 InFlag = Chain.getValue(1);
7342 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7345 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7347 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7349 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7350 X86::RAX, X86II::MO_TLSGD);
7353 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7354 // "local exec" model.
7355 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7356 const EVT PtrVT, TLSModel::Model model,
7358 DebugLoc dl = GA->getDebugLoc();
7360 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7361 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7362 is64Bit ? 257 : 256));
7364 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7365 DAG.getIntPtrConstant(0),
7366 MachinePointerInfo(Ptr), false, false, 0);
7368 unsigned char OperandFlags = 0;
7369 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7371 unsigned WrapperKind = X86ISD::Wrapper;
7372 if (model == TLSModel::LocalExec) {
7373 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7374 } else if (is64Bit) {
7375 assert(model == TLSModel::InitialExec);
7376 OperandFlags = X86II::MO_GOTTPOFF;
7377 WrapperKind = X86ISD::WrapperRIP;
7379 assert(model == TLSModel::InitialExec);
7380 OperandFlags = X86II::MO_INDNTPOFF;
7383 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7385 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7386 GA->getValueType(0),
7387 GA->getOffset(), OperandFlags);
7388 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7390 if (model == TLSModel::InitialExec)
7391 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7392 MachinePointerInfo::getGOT(), false, false, 0);
7394 // The address of the thread local variable is the add of the thread
7395 // pointer with the offset of the variable.
7396 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7400 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7402 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7403 const GlobalValue *GV = GA->getGlobal();
7405 if (Subtarget->isTargetELF()) {
7406 // TODO: implement the "local dynamic" model
7407 // TODO: implement the "initial exec"model for pic executables
7409 // If GV is an alias then use the aliasee for determining
7410 // thread-localness.
7411 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7412 GV = GA->resolveAliasedGlobal(false);
7414 TLSModel::Model model
7415 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7418 case TLSModel::GeneralDynamic:
7419 case TLSModel::LocalDynamic: // not implemented
7420 if (Subtarget->is64Bit())
7421 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7422 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7424 case TLSModel::InitialExec:
7425 case TLSModel::LocalExec:
7426 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7427 Subtarget->is64Bit());
7429 } else if (Subtarget->isTargetDarwin()) {
7430 // Darwin only has one model of TLS. Lower to that.
7431 unsigned char OpFlag = 0;
7432 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7433 X86ISD::WrapperRIP : X86ISD::Wrapper;
7435 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7437 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7438 !Subtarget->is64Bit();
7440 OpFlag = X86II::MO_TLVP_PIC_BASE;
7442 OpFlag = X86II::MO_TLVP;
7443 DebugLoc DL = Op.getDebugLoc();
7444 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7445 GA->getValueType(0),
7446 GA->getOffset(), OpFlag);
7447 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7449 // With PIC32, the address is actually $g + Offset.
7451 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7452 DAG.getNode(X86ISD::GlobalBaseReg,
7453 DebugLoc(), getPointerTy()),
7456 // Lowering the machine isd will make sure everything is in the right
7458 SDValue Chain = DAG.getEntryNode();
7459 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7460 SDValue Args[] = { Chain, Offset };
7461 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7463 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7464 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7465 MFI->setAdjustsStack(true);
7467 // And our return value (tls address) is in the standard call return value
7469 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7470 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
7474 "TLS not implemented for this target.");
7476 llvm_unreachable("Unreachable");
7481 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7482 /// take a 2 x i32 value to shift plus a shift amount.
7483 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7484 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7485 EVT VT = Op.getValueType();
7486 unsigned VTBits = VT.getSizeInBits();
7487 DebugLoc dl = Op.getDebugLoc();
7488 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7489 SDValue ShOpLo = Op.getOperand(0);
7490 SDValue ShOpHi = Op.getOperand(1);
7491 SDValue ShAmt = Op.getOperand(2);
7492 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7493 DAG.getConstant(VTBits - 1, MVT::i8))
7494 : DAG.getConstant(0, VT);
7497 if (Op.getOpcode() == ISD::SHL_PARTS) {
7498 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7499 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7501 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7502 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7505 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7506 DAG.getConstant(VTBits, MVT::i8));
7507 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7508 AndNode, DAG.getConstant(0, MVT::i8));
7511 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7512 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7513 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7515 if (Op.getOpcode() == ISD::SHL_PARTS) {
7516 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7517 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7519 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7520 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7523 SDValue Ops[2] = { Lo, Hi };
7524 return DAG.getMergeValues(Ops, 2, dl);
7527 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7528 SelectionDAG &DAG) const {
7529 EVT SrcVT = Op.getOperand(0).getValueType();
7531 if (SrcVT.isVector())
7534 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7535 "Unknown SINT_TO_FP to lower!");
7537 // These are really Legal; return the operand so the caller accepts it as
7539 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7541 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7542 Subtarget->is64Bit()) {
7546 DebugLoc dl = Op.getDebugLoc();
7547 unsigned Size = SrcVT.getSizeInBits()/8;
7548 MachineFunction &MF = DAG.getMachineFunction();
7549 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7550 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7551 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7553 MachinePointerInfo::getFixedStack(SSFI),
7555 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7558 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7560 SelectionDAG &DAG) const {
7562 DebugLoc DL = Op.getDebugLoc();
7564 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7566 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7568 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7570 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7572 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7573 MachineMemOperand *MMO;
7575 int SSFI = FI->getIndex();
7577 DAG.getMachineFunction()
7578 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7579 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7581 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7582 StackSlot = StackSlot.getOperand(1);
7584 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7585 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7587 Tys, Ops, array_lengthof(Ops),
7591 Chain = Result.getValue(1);
7592 SDValue InFlag = Result.getValue(2);
7594 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7595 // shouldn't be necessary except that RFP cannot be live across
7596 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7597 MachineFunction &MF = DAG.getMachineFunction();
7598 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7599 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7600 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7601 Tys = DAG.getVTList(MVT::Other);
7603 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7605 MachineMemOperand *MMO =
7606 DAG.getMachineFunction()
7607 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7608 MachineMemOperand::MOStore, SSFISize, SSFISize);
7610 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7611 Ops, array_lengthof(Ops),
7612 Op.getValueType(), MMO);
7613 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7614 MachinePointerInfo::getFixedStack(SSFI),
7621 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7622 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7623 SelectionDAG &DAG) const {
7624 // This algorithm is not obvious. Here it is in C code, more or less:
7626 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7627 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7628 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7630 // Copy ints to xmm registers.
7631 __m128i xh = _mm_cvtsi32_si128( hi );
7632 __m128i xl = _mm_cvtsi32_si128( lo );
7634 // Combine into low half of a single xmm register.
7635 __m128i x = _mm_unpacklo_epi32( xh, xl );
7639 // Merge in appropriate exponents to give the integer bits the right
7641 x = _mm_unpacklo_epi32( x, exp );
7643 // Subtract away the biases to deal with the IEEE-754 double precision
7645 d = _mm_sub_pd( (__m128d) x, bias );
7647 // All conversions up to here are exact. The correctly rounded result is
7648 // calculated using the current rounding mode using the following
7650 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7651 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7652 // store doesn't really need to be here (except
7653 // maybe to zero the other double)
7658 DebugLoc dl = Op.getDebugLoc();
7659 LLVMContext *Context = DAG.getContext();
7661 // Build some magic constants.
7662 std::vector<Constant*> CV0;
7663 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7664 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7665 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7666 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7667 Constant *C0 = ConstantVector::get(CV0);
7668 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7670 std::vector<Constant*> CV1;
7672 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7674 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7675 Constant *C1 = ConstantVector::get(CV1);
7676 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7678 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7679 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7681 DAG.getIntPtrConstant(1)));
7682 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7683 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7685 DAG.getIntPtrConstant(0)));
7686 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7687 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7688 MachinePointerInfo::getConstantPool(),
7690 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7691 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7692 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7693 MachinePointerInfo::getConstantPool(),
7695 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7697 // Add the halves; easiest way is to swap them into another reg first.
7698 int ShufMask[2] = { 1, -1 };
7699 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7700 DAG.getUNDEF(MVT::v2f64), ShufMask);
7701 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7702 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7703 DAG.getIntPtrConstant(0));
7706 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7707 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7708 SelectionDAG &DAG) const {
7709 DebugLoc dl = Op.getDebugLoc();
7710 // FP constant to bias correct the final result.
7711 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7714 // Load the 32-bit value into an XMM register.
7715 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7718 // Zero out the upper parts of the register.
7719 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasSSE2(), DAG);
7721 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7722 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7723 DAG.getIntPtrConstant(0));
7725 // Or the load with the bias.
7726 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7727 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7728 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7730 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7731 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7732 MVT::v2f64, Bias)));
7733 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7734 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7735 DAG.getIntPtrConstant(0));
7737 // Subtract the bias.
7738 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7740 // Handle final rounding.
7741 EVT DestVT = Op.getValueType();
7743 if (DestVT.bitsLT(MVT::f64)) {
7744 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7745 DAG.getIntPtrConstant(0));
7746 } else if (DestVT.bitsGT(MVT::f64)) {
7747 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7750 // Handle final rounding.
7754 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7755 SelectionDAG &DAG) const {
7756 SDValue N0 = Op.getOperand(0);
7757 DebugLoc dl = Op.getDebugLoc();
7759 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7760 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7761 // the optimization here.
7762 if (DAG.SignBitIsZero(N0))
7763 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7765 EVT SrcVT = N0.getValueType();
7766 EVT DstVT = Op.getValueType();
7767 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7768 return LowerUINT_TO_FP_i64(Op, DAG);
7769 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7770 return LowerUINT_TO_FP_i32(Op, DAG);
7772 // Make a 64-bit buffer, and use it to build an FILD.
7773 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7774 if (SrcVT == MVT::i32) {
7775 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7776 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7777 getPointerTy(), StackSlot, WordOff);
7778 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7779 StackSlot, MachinePointerInfo(),
7781 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7782 OffsetSlot, MachinePointerInfo(),
7784 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7788 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7789 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7790 StackSlot, MachinePointerInfo(),
7792 // For i64 source, we need to add the appropriate power of 2 if the input
7793 // was negative. This is the same as the optimization in
7794 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7795 // we must be careful to do the computation in x87 extended precision, not
7796 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7797 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7798 MachineMemOperand *MMO =
7799 DAG.getMachineFunction()
7800 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7801 MachineMemOperand::MOLoad, 8, 8);
7803 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7804 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7805 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7808 APInt FF(32, 0x5F800000ULL);
7810 // Check whether the sign bit is set.
7811 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7812 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7815 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7816 SDValue FudgePtr = DAG.getConstantPool(
7817 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7820 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7821 SDValue Zero = DAG.getIntPtrConstant(0);
7822 SDValue Four = DAG.getIntPtrConstant(4);
7823 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7825 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7827 // Load the value out, extending it from f32 to f80.
7828 // FIXME: Avoid the extend by constructing the right constant pool?
7829 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7830 FudgePtr, MachinePointerInfo::getConstantPool(),
7831 MVT::f32, false, false, 4);
7832 // Extend everything to 80 bits to force it to be done on x87.
7833 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7834 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7837 std::pair<SDValue,SDValue> X86TargetLowering::
7838 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7839 DebugLoc DL = Op.getDebugLoc();
7841 EVT DstTy = Op.getValueType();
7844 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7848 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7849 DstTy.getSimpleVT() >= MVT::i16 &&
7850 "Unknown FP_TO_SINT to lower!");
7852 // These are really Legal.
7853 if (DstTy == MVT::i32 &&
7854 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7855 return std::make_pair(SDValue(), SDValue());
7856 if (Subtarget->is64Bit() &&
7857 DstTy == MVT::i64 &&
7858 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7859 return std::make_pair(SDValue(), SDValue());
7861 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7863 MachineFunction &MF = DAG.getMachineFunction();
7864 unsigned MemSize = DstTy.getSizeInBits()/8;
7865 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7866 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7871 switch (DstTy.getSimpleVT().SimpleTy) {
7872 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7873 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7874 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7875 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7878 SDValue Chain = DAG.getEntryNode();
7879 SDValue Value = Op.getOperand(0);
7880 EVT TheVT = Op.getOperand(0).getValueType();
7881 if (isScalarFPTypeInSSEReg(TheVT)) {
7882 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7883 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7884 MachinePointerInfo::getFixedStack(SSFI),
7886 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7888 Chain, StackSlot, DAG.getValueType(TheVT)
7891 MachineMemOperand *MMO =
7892 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7893 MachineMemOperand::MOLoad, MemSize, MemSize);
7894 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7896 Chain = Value.getValue(1);
7897 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7898 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7901 MachineMemOperand *MMO =
7902 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7903 MachineMemOperand::MOStore, MemSize, MemSize);
7905 // Build the FP_TO_INT*_IN_MEM
7906 SDValue Ops[] = { Chain, Value, StackSlot };
7907 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7908 Ops, 3, DstTy, MMO);
7910 return std::make_pair(FIST, StackSlot);
7913 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7914 SelectionDAG &DAG) const {
7915 if (Op.getValueType().isVector())
7918 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7919 SDValue FIST = Vals.first, StackSlot = Vals.second;
7920 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7921 if (FIST.getNode() == 0) return Op;
7924 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7925 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7928 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7929 SelectionDAG &DAG) const {
7930 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7931 SDValue FIST = Vals.first, StackSlot = Vals.second;
7932 assert(FIST.getNode() && "Unexpected failure");
7935 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7936 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7939 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7940 SelectionDAG &DAG) const {
7941 LLVMContext *Context = DAG.getContext();
7942 DebugLoc dl = Op.getDebugLoc();
7943 EVT VT = Op.getValueType();
7946 EltVT = VT.getVectorElementType();
7947 std::vector<Constant*> CV;
7948 if (EltVT == MVT::f64) {
7949 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7953 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7959 Constant *C = ConstantVector::get(CV);
7960 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7961 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7962 MachinePointerInfo::getConstantPool(),
7964 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7967 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7968 LLVMContext *Context = DAG.getContext();
7969 DebugLoc dl = Op.getDebugLoc();
7970 EVT VT = Op.getValueType();
7973 EltVT = VT.getVectorElementType();
7974 std::vector<Constant*> CV;
7975 if (EltVT == MVT::f64) {
7976 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7980 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7986 Constant *C = ConstantVector::get(CV);
7987 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7988 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7989 MachinePointerInfo::getConstantPool(),
7991 if (VT.isVector()) {
7992 return DAG.getNode(ISD::BITCAST, dl, VT,
7993 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
7994 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7996 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
7998 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8002 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8003 LLVMContext *Context = DAG.getContext();
8004 SDValue Op0 = Op.getOperand(0);
8005 SDValue Op1 = Op.getOperand(1);
8006 DebugLoc dl = Op.getDebugLoc();
8007 EVT VT = Op.getValueType();
8008 EVT SrcVT = Op1.getValueType();
8010 // If second operand is smaller, extend it first.
8011 if (SrcVT.bitsLT(VT)) {
8012 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8015 // And if it is bigger, shrink it first.
8016 if (SrcVT.bitsGT(VT)) {
8017 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8021 // At this point the operands and the result should have the same
8022 // type, and that won't be f80 since that is not custom lowered.
8024 // First get the sign bit of second operand.
8025 std::vector<Constant*> CV;
8026 if (SrcVT == MVT::f64) {
8027 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8028 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8030 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8031 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8032 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8033 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8035 Constant *C = ConstantVector::get(CV);
8036 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8037 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8038 MachinePointerInfo::getConstantPool(),
8040 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8042 // Shift sign bit right or left if the two operands have different types.
8043 if (SrcVT.bitsGT(VT)) {
8044 // Op0 is MVT::f32, Op1 is MVT::f64.
8045 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8046 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8047 DAG.getConstant(32, MVT::i32));
8048 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8049 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8050 DAG.getIntPtrConstant(0));
8053 // Clear first operand sign bit.
8055 if (VT == MVT::f64) {
8056 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8057 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8059 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8060 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8061 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8062 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8064 C = ConstantVector::get(CV);
8065 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8066 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8067 MachinePointerInfo::getConstantPool(),
8069 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8071 // Or the value with the sign bit.
8072 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8075 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8076 SDValue N0 = Op.getOperand(0);
8077 DebugLoc dl = Op.getDebugLoc();
8078 EVT VT = Op.getValueType();
8080 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8081 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8082 DAG.getConstant(1, VT));
8083 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8086 /// Emit nodes that will be selected as "test Op0,Op0", or something
8088 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8089 SelectionDAG &DAG) const {
8090 DebugLoc dl = Op.getDebugLoc();
8092 // CF and OF aren't always set the way we want. Determine which
8093 // of these we need.
8094 bool NeedCF = false;
8095 bool NeedOF = false;
8098 case X86::COND_A: case X86::COND_AE:
8099 case X86::COND_B: case X86::COND_BE:
8102 case X86::COND_G: case X86::COND_GE:
8103 case X86::COND_L: case X86::COND_LE:
8104 case X86::COND_O: case X86::COND_NO:
8109 // See if we can use the EFLAGS value from the operand instead of
8110 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8111 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8112 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8113 // Emit a CMP with 0, which is the TEST pattern.
8114 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8115 DAG.getConstant(0, Op.getValueType()));
8117 unsigned Opcode = 0;
8118 unsigned NumOperands = 0;
8119 switch (Op.getNode()->getOpcode()) {
8121 // Due to an isel shortcoming, be conservative if this add is likely to be
8122 // selected as part of a load-modify-store instruction. When the root node
8123 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8124 // uses of other nodes in the match, such as the ADD in this case. This
8125 // leads to the ADD being left around and reselected, with the result being
8126 // two adds in the output. Alas, even if none our users are stores, that
8127 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8128 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8129 // climbing the DAG back to the root, and it doesn't seem to be worth the
8131 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8132 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8133 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
8136 if (ConstantSDNode *C =
8137 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8138 // An add of one will be selected as an INC.
8139 if (C->getAPIntValue() == 1) {
8140 Opcode = X86ISD::INC;
8145 // An add of negative one (subtract of one) will be selected as a DEC.
8146 if (C->getAPIntValue().isAllOnesValue()) {
8147 Opcode = X86ISD::DEC;
8153 // Otherwise use a regular EFLAGS-setting add.
8154 Opcode = X86ISD::ADD;
8158 // If the primary and result isn't used, don't bother using X86ISD::AND,
8159 // because a TEST instruction will be better.
8160 bool NonFlagUse = false;
8161 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8162 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8164 unsigned UOpNo = UI.getOperandNo();
8165 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8166 // Look pass truncate.
8167 UOpNo = User->use_begin().getOperandNo();
8168 User = *User->use_begin();
8171 if (User->getOpcode() != ISD::BRCOND &&
8172 User->getOpcode() != ISD::SETCC &&
8173 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8186 // Due to the ISEL shortcoming noted above, be conservative if this op is
8187 // likely to be selected as part of a load-modify-store instruction.
8188 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8189 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8190 if (UI->getOpcode() == ISD::STORE)
8193 // Otherwise use a regular EFLAGS-setting instruction.
8194 switch (Op.getNode()->getOpcode()) {
8195 default: llvm_unreachable("unexpected operator!");
8196 case ISD::SUB: Opcode = X86ISD::SUB; break;
8197 case ISD::OR: Opcode = X86ISD::OR; break;
8198 case ISD::XOR: Opcode = X86ISD::XOR; break;
8199 case ISD::AND: Opcode = X86ISD::AND; break;
8211 return SDValue(Op.getNode(), 1);
8218 // Emit a CMP with 0, which is the TEST pattern.
8219 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8220 DAG.getConstant(0, Op.getValueType()));
8222 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8223 SmallVector<SDValue, 4> Ops;
8224 for (unsigned i = 0; i != NumOperands; ++i)
8225 Ops.push_back(Op.getOperand(i));
8227 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8228 DAG.ReplaceAllUsesWith(Op, New);
8229 return SDValue(New.getNode(), 1);
8232 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8234 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8235 SelectionDAG &DAG) const {
8236 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8237 if (C->getAPIntValue() == 0)
8238 return EmitTest(Op0, X86CC, DAG);
8240 DebugLoc dl = Op0.getDebugLoc();
8241 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8244 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8245 /// if it's possible.
8246 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8247 DebugLoc dl, SelectionDAG &DAG) const {
8248 SDValue Op0 = And.getOperand(0);
8249 SDValue Op1 = And.getOperand(1);
8250 if (Op0.getOpcode() == ISD::TRUNCATE)
8251 Op0 = Op0.getOperand(0);
8252 if (Op1.getOpcode() == ISD::TRUNCATE)
8253 Op1 = Op1.getOperand(0);
8256 if (Op1.getOpcode() == ISD::SHL)
8257 std::swap(Op0, Op1);
8258 if (Op0.getOpcode() == ISD::SHL) {
8259 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8260 if (And00C->getZExtValue() == 1) {
8261 // If we looked past a truncate, check that it's only truncating away
8263 unsigned BitWidth = Op0.getValueSizeInBits();
8264 unsigned AndBitWidth = And.getValueSizeInBits();
8265 if (BitWidth > AndBitWidth) {
8266 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8267 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8268 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8272 RHS = Op0.getOperand(1);
8274 } else if (Op1.getOpcode() == ISD::Constant) {
8275 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8276 SDValue AndLHS = Op0;
8277 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
8278 LHS = AndLHS.getOperand(0);
8279 RHS = AndLHS.getOperand(1);
8283 if (LHS.getNode()) {
8284 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8285 // instruction. Since the shift amount is in-range-or-undefined, we know
8286 // that doing a bittest on the i32 value is ok. We extend to i32 because
8287 // the encoding for the i16 version is larger than the i32 version.
8288 // Also promote i16 to i32 for performance / code size reason.
8289 if (LHS.getValueType() == MVT::i8 ||
8290 LHS.getValueType() == MVT::i16)
8291 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8293 // If the operand types disagree, extend the shift amount to match. Since
8294 // BT ignores high bits (like shifts) we can use anyextend.
8295 if (LHS.getValueType() != RHS.getValueType())
8296 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8298 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8299 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8300 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8301 DAG.getConstant(Cond, MVT::i8), BT);
8307 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8308 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8309 SDValue Op0 = Op.getOperand(0);
8310 SDValue Op1 = Op.getOperand(1);
8311 DebugLoc dl = Op.getDebugLoc();
8312 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8314 // Optimize to BT if possible.
8315 // Lower (X & (1 << N)) == 0 to BT(X, N).
8316 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8317 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8318 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8319 Op1.getOpcode() == ISD::Constant &&
8320 cast<ConstantSDNode>(Op1)->isNullValue() &&
8321 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8322 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8323 if (NewSetCC.getNode())
8327 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8329 if (Op1.getOpcode() == ISD::Constant &&
8330 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8331 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8332 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8334 // If the input is a setcc, then reuse the input setcc or use a new one with
8335 // the inverted condition.
8336 if (Op0.getOpcode() == X86ISD::SETCC) {
8337 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8338 bool Invert = (CC == ISD::SETNE) ^
8339 cast<ConstantSDNode>(Op1)->isNullValue();
8340 if (!Invert) return Op0;
8342 CCode = X86::GetOppositeBranchCondition(CCode);
8343 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8344 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8348 bool isFP = Op1.getValueType().isFloatingPoint();
8349 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8350 if (X86CC == X86::COND_INVALID)
8353 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8354 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8355 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8358 // Lower256IntVETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8359 // ones, and then concatenate the result back.
8360 static SDValue Lower256IntVETCC(SDValue Op, SelectionDAG &DAG) {
8361 EVT VT = Op.getValueType();
8363 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::VSETCC &&
8364 "Unsupported value type for operation");
8366 int NumElems = VT.getVectorNumElements();
8367 DebugLoc dl = Op.getDebugLoc();
8368 SDValue CC = Op.getOperand(2);
8369 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8370 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8372 // Extract the LHS vectors
8373 SDValue LHS = Op.getOperand(0);
8374 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8375 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8377 // Extract the RHS vectors
8378 SDValue RHS = Op.getOperand(1);
8379 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8380 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8382 // Issue the operation on the smaller types and concatenate the result back
8383 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8384 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8385 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8386 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8387 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8391 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8393 SDValue Op0 = Op.getOperand(0);
8394 SDValue Op1 = Op.getOperand(1);
8395 SDValue CC = Op.getOperand(2);
8396 EVT VT = Op.getValueType();
8397 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8398 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8399 DebugLoc dl = Op.getDebugLoc();
8403 EVT EltVT = Op0.getValueType().getVectorElementType();
8404 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8406 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8409 switch (SetCCOpcode) {
8412 case ISD::SETEQ: SSECC = 0; break;
8414 case ISD::SETGT: Swap = true; // Fallthrough
8416 case ISD::SETOLT: SSECC = 1; break;
8418 case ISD::SETGE: Swap = true; // Fallthrough
8420 case ISD::SETOLE: SSECC = 2; break;
8421 case ISD::SETUO: SSECC = 3; break;
8423 case ISD::SETNE: SSECC = 4; break;
8424 case ISD::SETULE: Swap = true;
8425 case ISD::SETUGE: SSECC = 5; break;
8426 case ISD::SETULT: Swap = true;
8427 case ISD::SETUGT: SSECC = 6; break;
8428 case ISD::SETO: SSECC = 7; break;
8431 std::swap(Op0, Op1);
8433 // In the two special cases we can't handle, emit two comparisons.
8435 if (SetCCOpcode == ISD::SETUEQ) {
8437 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8438 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8439 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8441 else if (SetCCOpcode == ISD::SETONE) {
8443 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8444 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8445 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8447 llvm_unreachable("Illegal FP comparison");
8449 // Handle all other FP comparisons here.
8450 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8453 // Break 256-bit integer vector compare into smaller ones.
8454 if (!isFP && VT.getSizeInBits() == 256)
8455 return Lower256IntVETCC(Op, DAG);
8457 // We are handling one of the integer comparisons here. Since SSE only has
8458 // GT and EQ comparisons for integer, swapping operands and multiple
8459 // operations may be required for some comparisons.
8460 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8461 bool Swap = false, Invert = false, FlipSigns = false;
8463 switch (VT.getSimpleVT().SimpleTy) {
8465 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8466 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8467 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8468 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8471 switch (SetCCOpcode) {
8473 case ISD::SETNE: Invert = true;
8474 case ISD::SETEQ: Opc = EQOpc; break;
8475 case ISD::SETLT: Swap = true;
8476 case ISD::SETGT: Opc = GTOpc; break;
8477 case ISD::SETGE: Swap = true;
8478 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8479 case ISD::SETULT: Swap = true;
8480 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8481 case ISD::SETUGE: Swap = true;
8482 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8485 std::swap(Op0, Op1);
8487 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8488 // bits of the inputs before performing those operations.
8490 EVT EltVT = VT.getVectorElementType();
8491 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8493 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8494 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8496 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8497 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8500 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8502 // If the logical-not of the result is required, perform that now.
8504 Result = DAG.getNOT(dl, Result, VT);
8509 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8510 static bool isX86LogicalCmp(SDValue Op) {
8511 unsigned Opc = Op.getNode()->getOpcode();
8512 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8514 if (Op.getResNo() == 1 &&
8515 (Opc == X86ISD::ADD ||
8516 Opc == X86ISD::SUB ||
8517 Opc == X86ISD::ADC ||
8518 Opc == X86ISD::SBB ||
8519 Opc == X86ISD::SMUL ||
8520 Opc == X86ISD::UMUL ||
8521 Opc == X86ISD::INC ||
8522 Opc == X86ISD::DEC ||
8523 Opc == X86ISD::OR ||
8524 Opc == X86ISD::XOR ||
8525 Opc == X86ISD::AND))
8528 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8534 static bool isZero(SDValue V) {
8535 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8536 return C && C->isNullValue();
8539 static bool isAllOnes(SDValue V) {
8540 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8541 return C && C->isAllOnesValue();
8544 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8545 bool addTest = true;
8546 SDValue Cond = Op.getOperand(0);
8547 SDValue Op1 = Op.getOperand(1);
8548 SDValue Op2 = Op.getOperand(2);
8549 DebugLoc DL = Op.getDebugLoc();
8552 if (Cond.getOpcode() == ISD::SETCC) {
8553 SDValue NewCond = LowerSETCC(Cond, DAG);
8554 if (NewCond.getNode())
8558 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8559 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8560 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8561 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8562 if (Cond.getOpcode() == X86ISD::SETCC &&
8563 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8564 isZero(Cond.getOperand(1).getOperand(1))) {
8565 SDValue Cmp = Cond.getOperand(1);
8567 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8569 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8570 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8571 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8573 SDValue CmpOp0 = Cmp.getOperand(0);
8574 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8575 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8577 SDValue Res = // Res = 0 or -1.
8578 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8579 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8581 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8582 Res = DAG.getNOT(DL, Res, Res.getValueType());
8584 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8585 if (N2C == 0 || !N2C->isNullValue())
8586 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8591 // Look past (and (setcc_carry (cmp ...)), 1).
8592 if (Cond.getOpcode() == ISD::AND &&
8593 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8594 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8595 if (C && C->getAPIntValue() == 1)
8596 Cond = Cond.getOperand(0);
8599 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8600 // setting operand in place of the X86ISD::SETCC.
8601 if (Cond.getOpcode() == X86ISD::SETCC ||
8602 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8603 CC = Cond.getOperand(0);
8605 SDValue Cmp = Cond.getOperand(1);
8606 unsigned Opc = Cmp.getOpcode();
8607 EVT VT = Op.getValueType();
8609 bool IllegalFPCMov = false;
8610 if (VT.isFloatingPoint() && !VT.isVector() &&
8611 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8612 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8614 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8615 Opc == X86ISD::BT) { // FIXME
8622 // Look pass the truncate.
8623 if (Cond.getOpcode() == ISD::TRUNCATE)
8624 Cond = Cond.getOperand(0);
8626 // We know the result of AND is compared against zero. Try to match
8628 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8629 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8630 if (NewSetCC.getNode()) {
8631 CC = NewSetCC.getOperand(0);
8632 Cond = NewSetCC.getOperand(1);
8639 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8640 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8643 // a < b ? -1 : 0 -> RES = ~setcc_carry
8644 // a < b ? 0 : -1 -> RES = setcc_carry
8645 // a >= b ? -1 : 0 -> RES = setcc_carry
8646 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8647 if (Cond.getOpcode() == X86ISD::CMP) {
8648 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8650 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8651 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8652 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8653 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8654 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8655 return DAG.getNOT(DL, Res, Res.getValueType());
8660 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8661 // condition is true.
8662 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8663 SDValue Ops[] = { Op2, Op1, CC, Cond };
8664 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8667 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8668 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8669 // from the AND / OR.
8670 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8671 Opc = Op.getOpcode();
8672 if (Opc != ISD::OR && Opc != ISD::AND)
8674 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8675 Op.getOperand(0).hasOneUse() &&
8676 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8677 Op.getOperand(1).hasOneUse());
8680 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8681 // 1 and that the SETCC node has a single use.
8682 static bool isXor1OfSetCC(SDValue Op) {
8683 if (Op.getOpcode() != ISD::XOR)
8685 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8686 if (N1C && N1C->getAPIntValue() == 1) {
8687 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8688 Op.getOperand(0).hasOneUse();
8693 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8694 bool addTest = true;
8695 SDValue Chain = Op.getOperand(0);
8696 SDValue Cond = Op.getOperand(1);
8697 SDValue Dest = Op.getOperand(2);
8698 DebugLoc dl = Op.getDebugLoc();
8701 if (Cond.getOpcode() == ISD::SETCC) {
8702 SDValue NewCond = LowerSETCC(Cond, DAG);
8703 if (NewCond.getNode())
8707 // FIXME: LowerXALUO doesn't handle these!!
8708 else if (Cond.getOpcode() == X86ISD::ADD ||
8709 Cond.getOpcode() == X86ISD::SUB ||
8710 Cond.getOpcode() == X86ISD::SMUL ||
8711 Cond.getOpcode() == X86ISD::UMUL)
8712 Cond = LowerXALUO(Cond, DAG);
8715 // Look pass (and (setcc_carry (cmp ...)), 1).
8716 if (Cond.getOpcode() == ISD::AND &&
8717 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8718 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8719 if (C && C->getAPIntValue() == 1)
8720 Cond = Cond.getOperand(0);
8723 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8724 // setting operand in place of the X86ISD::SETCC.
8725 if (Cond.getOpcode() == X86ISD::SETCC ||
8726 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8727 CC = Cond.getOperand(0);
8729 SDValue Cmp = Cond.getOperand(1);
8730 unsigned Opc = Cmp.getOpcode();
8731 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8732 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8736 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8740 // These can only come from an arithmetic instruction with overflow,
8741 // e.g. SADDO, UADDO.
8742 Cond = Cond.getNode()->getOperand(1);
8749 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8750 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8751 if (CondOpc == ISD::OR) {
8752 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8753 // two branches instead of an explicit OR instruction with a
8755 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8756 isX86LogicalCmp(Cmp)) {
8757 CC = Cond.getOperand(0).getOperand(0);
8758 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8759 Chain, Dest, CC, Cmp);
8760 CC = Cond.getOperand(1).getOperand(0);
8764 } else { // ISD::AND
8765 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8766 // two branches instead of an explicit AND instruction with a
8767 // separate test. However, we only do this if this block doesn't
8768 // have a fall-through edge, because this requires an explicit
8769 // jmp when the condition is false.
8770 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8771 isX86LogicalCmp(Cmp) &&
8772 Op.getNode()->hasOneUse()) {
8773 X86::CondCode CCode =
8774 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8775 CCode = X86::GetOppositeBranchCondition(CCode);
8776 CC = DAG.getConstant(CCode, MVT::i8);
8777 SDNode *User = *Op.getNode()->use_begin();
8778 // Look for an unconditional branch following this conditional branch.
8779 // We need this because we need to reverse the successors in order
8780 // to implement FCMP_OEQ.
8781 if (User->getOpcode() == ISD::BR) {
8782 SDValue FalseBB = User->getOperand(1);
8784 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8785 assert(NewBR == User);
8789 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8790 Chain, Dest, CC, Cmp);
8791 X86::CondCode CCode =
8792 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8793 CCode = X86::GetOppositeBranchCondition(CCode);
8794 CC = DAG.getConstant(CCode, MVT::i8);
8800 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8801 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8802 // It should be transformed during dag combiner except when the condition
8803 // is set by a arithmetics with overflow node.
8804 X86::CondCode CCode =
8805 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8806 CCode = X86::GetOppositeBranchCondition(CCode);
8807 CC = DAG.getConstant(CCode, MVT::i8);
8808 Cond = Cond.getOperand(0).getOperand(1);
8814 // Look pass the truncate.
8815 if (Cond.getOpcode() == ISD::TRUNCATE)
8816 Cond = Cond.getOperand(0);
8818 // We know the result of AND is compared against zero. Try to match
8820 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8821 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8822 if (NewSetCC.getNode()) {
8823 CC = NewSetCC.getOperand(0);
8824 Cond = NewSetCC.getOperand(1);
8831 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8832 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8834 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8835 Chain, Dest, CC, Cond);
8839 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8840 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8841 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8842 // that the guard pages used by the OS virtual memory manager are allocated in
8843 // correct sequence.
8845 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8846 SelectionDAG &DAG) const {
8847 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
8848 "This should be used only on Windows targets");
8849 assert(!Subtarget->isTargetEnvMacho());
8850 DebugLoc dl = Op.getDebugLoc();
8853 SDValue Chain = Op.getOperand(0);
8854 SDValue Size = Op.getOperand(1);
8855 // FIXME: Ensure alignment here
8859 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
8860 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8862 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8863 Flag = Chain.getValue(1);
8865 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8867 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8868 Flag = Chain.getValue(1);
8870 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8872 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8873 return DAG.getMergeValues(Ops1, 2, dl);
8876 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8877 MachineFunction &MF = DAG.getMachineFunction();
8878 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8880 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8881 DebugLoc DL = Op.getDebugLoc();
8883 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8884 // vastart just stores the address of the VarArgsFrameIndex slot into the
8885 // memory location argument.
8886 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8888 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8889 MachinePointerInfo(SV), false, false, 0);
8893 // gp_offset (0 - 6 * 8)
8894 // fp_offset (48 - 48 + 8 * 16)
8895 // overflow_arg_area (point to parameters coming in memory).
8897 SmallVector<SDValue, 8> MemOps;
8898 SDValue FIN = Op.getOperand(1);
8900 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8901 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
8903 FIN, MachinePointerInfo(SV), false, false, 0);
8904 MemOps.push_back(Store);
8907 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8908 FIN, DAG.getIntPtrConstant(4));
8909 Store = DAG.getStore(Op.getOperand(0), DL,
8910 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8912 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8913 MemOps.push_back(Store);
8915 // Store ptr to overflow_arg_area
8916 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8917 FIN, DAG.getIntPtrConstant(4));
8918 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8920 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
8921 MachinePointerInfo(SV, 8),
8923 MemOps.push_back(Store);
8925 // Store ptr to reg_save_area.
8926 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8927 FIN, DAG.getIntPtrConstant(8));
8928 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
8930 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
8931 MachinePointerInfo(SV, 16), false, false, 0);
8932 MemOps.push_back(Store);
8933 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
8934 &MemOps[0], MemOps.size());
8937 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
8938 assert(Subtarget->is64Bit() &&
8939 "LowerVAARG only handles 64-bit va_arg!");
8940 assert((Subtarget->isTargetLinux() ||
8941 Subtarget->isTargetDarwin()) &&
8942 "Unhandled target in LowerVAARG");
8943 assert(Op.getNode()->getNumOperands() == 4);
8944 SDValue Chain = Op.getOperand(0);
8945 SDValue SrcPtr = Op.getOperand(1);
8946 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8947 unsigned Align = Op.getConstantOperandVal(3);
8948 DebugLoc dl = Op.getDebugLoc();
8950 EVT ArgVT = Op.getNode()->getValueType(0);
8951 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
8952 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
8955 // Decide which area this value should be read from.
8956 // TODO: Implement the AMD64 ABI in its entirety. This simple
8957 // selection mechanism works only for the basic types.
8958 if (ArgVT == MVT::f80) {
8959 llvm_unreachable("va_arg for f80 not yet implemented");
8960 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
8961 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
8962 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
8963 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
8965 llvm_unreachable("Unhandled argument type in LowerVAARG");
8969 // Sanity Check: Make sure using fp_offset makes sense.
8970 assert(!UseSoftFloat &&
8971 !(DAG.getMachineFunction()
8972 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
8973 Subtarget->hasXMM());
8976 // Insert VAARG_64 node into the DAG
8977 // VAARG_64 returns two values: Variable Argument Address, Chain
8978 SmallVector<SDValue, 11> InstOps;
8979 InstOps.push_back(Chain);
8980 InstOps.push_back(SrcPtr);
8981 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
8982 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
8983 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
8984 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
8985 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
8986 VTs, &InstOps[0], InstOps.size(),
8988 MachinePointerInfo(SV),
8993 Chain = VAARG.getValue(1);
8995 // Load the next argument and return it
8996 return DAG.getLoad(ArgVT, dl,
8999 MachinePointerInfo(),
9003 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9004 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9005 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9006 SDValue Chain = Op.getOperand(0);
9007 SDValue DstPtr = Op.getOperand(1);
9008 SDValue SrcPtr = Op.getOperand(2);
9009 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9010 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9011 DebugLoc DL = Op.getDebugLoc();
9013 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9014 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9016 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9020 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9021 DebugLoc dl = Op.getDebugLoc();
9022 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9024 default: return SDValue(); // Don't custom lower most intrinsics.
9025 // Comparison intrinsics.
9026 case Intrinsic::x86_sse_comieq_ss:
9027 case Intrinsic::x86_sse_comilt_ss:
9028 case Intrinsic::x86_sse_comile_ss:
9029 case Intrinsic::x86_sse_comigt_ss:
9030 case Intrinsic::x86_sse_comige_ss:
9031 case Intrinsic::x86_sse_comineq_ss:
9032 case Intrinsic::x86_sse_ucomieq_ss:
9033 case Intrinsic::x86_sse_ucomilt_ss:
9034 case Intrinsic::x86_sse_ucomile_ss:
9035 case Intrinsic::x86_sse_ucomigt_ss:
9036 case Intrinsic::x86_sse_ucomige_ss:
9037 case Intrinsic::x86_sse_ucomineq_ss:
9038 case Intrinsic::x86_sse2_comieq_sd:
9039 case Intrinsic::x86_sse2_comilt_sd:
9040 case Intrinsic::x86_sse2_comile_sd:
9041 case Intrinsic::x86_sse2_comigt_sd:
9042 case Intrinsic::x86_sse2_comige_sd:
9043 case Intrinsic::x86_sse2_comineq_sd:
9044 case Intrinsic::x86_sse2_ucomieq_sd:
9045 case Intrinsic::x86_sse2_ucomilt_sd:
9046 case Intrinsic::x86_sse2_ucomile_sd:
9047 case Intrinsic::x86_sse2_ucomigt_sd:
9048 case Intrinsic::x86_sse2_ucomige_sd:
9049 case Intrinsic::x86_sse2_ucomineq_sd: {
9051 ISD::CondCode CC = ISD::SETCC_INVALID;
9054 case Intrinsic::x86_sse_comieq_ss:
9055 case Intrinsic::x86_sse2_comieq_sd:
9059 case Intrinsic::x86_sse_comilt_ss:
9060 case Intrinsic::x86_sse2_comilt_sd:
9064 case Intrinsic::x86_sse_comile_ss:
9065 case Intrinsic::x86_sse2_comile_sd:
9069 case Intrinsic::x86_sse_comigt_ss:
9070 case Intrinsic::x86_sse2_comigt_sd:
9074 case Intrinsic::x86_sse_comige_ss:
9075 case Intrinsic::x86_sse2_comige_sd:
9079 case Intrinsic::x86_sse_comineq_ss:
9080 case Intrinsic::x86_sse2_comineq_sd:
9084 case Intrinsic::x86_sse_ucomieq_ss:
9085 case Intrinsic::x86_sse2_ucomieq_sd:
9086 Opc = X86ISD::UCOMI;
9089 case Intrinsic::x86_sse_ucomilt_ss:
9090 case Intrinsic::x86_sse2_ucomilt_sd:
9091 Opc = X86ISD::UCOMI;
9094 case Intrinsic::x86_sse_ucomile_ss:
9095 case Intrinsic::x86_sse2_ucomile_sd:
9096 Opc = X86ISD::UCOMI;
9099 case Intrinsic::x86_sse_ucomigt_ss:
9100 case Intrinsic::x86_sse2_ucomigt_sd:
9101 Opc = X86ISD::UCOMI;
9104 case Intrinsic::x86_sse_ucomige_ss:
9105 case Intrinsic::x86_sse2_ucomige_sd:
9106 Opc = X86ISD::UCOMI;
9109 case Intrinsic::x86_sse_ucomineq_ss:
9110 case Intrinsic::x86_sse2_ucomineq_sd:
9111 Opc = X86ISD::UCOMI;
9116 SDValue LHS = Op.getOperand(1);
9117 SDValue RHS = Op.getOperand(2);
9118 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9119 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9120 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9121 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9122 DAG.getConstant(X86CC, MVT::i8), Cond);
9123 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9125 // ptest and testp intrinsics. The intrinsic these come from are designed to
9126 // return an integer value, not just an instruction so lower it to the ptest
9127 // or testp pattern and a setcc for the result.
9128 case Intrinsic::x86_sse41_ptestz:
9129 case Intrinsic::x86_sse41_ptestc:
9130 case Intrinsic::x86_sse41_ptestnzc:
9131 case Intrinsic::x86_avx_ptestz_256:
9132 case Intrinsic::x86_avx_ptestc_256:
9133 case Intrinsic::x86_avx_ptestnzc_256:
9134 case Intrinsic::x86_avx_vtestz_ps:
9135 case Intrinsic::x86_avx_vtestc_ps:
9136 case Intrinsic::x86_avx_vtestnzc_ps:
9137 case Intrinsic::x86_avx_vtestz_pd:
9138 case Intrinsic::x86_avx_vtestc_pd:
9139 case Intrinsic::x86_avx_vtestnzc_pd:
9140 case Intrinsic::x86_avx_vtestz_ps_256:
9141 case Intrinsic::x86_avx_vtestc_ps_256:
9142 case Intrinsic::x86_avx_vtestnzc_ps_256:
9143 case Intrinsic::x86_avx_vtestz_pd_256:
9144 case Intrinsic::x86_avx_vtestc_pd_256:
9145 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9146 bool IsTestPacked = false;
9149 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9150 case Intrinsic::x86_avx_vtestz_ps:
9151 case Intrinsic::x86_avx_vtestz_pd:
9152 case Intrinsic::x86_avx_vtestz_ps_256:
9153 case Intrinsic::x86_avx_vtestz_pd_256:
9154 IsTestPacked = true; // Fallthrough
9155 case Intrinsic::x86_sse41_ptestz:
9156 case Intrinsic::x86_avx_ptestz_256:
9158 X86CC = X86::COND_E;
9160 case Intrinsic::x86_avx_vtestc_ps:
9161 case Intrinsic::x86_avx_vtestc_pd:
9162 case Intrinsic::x86_avx_vtestc_ps_256:
9163 case Intrinsic::x86_avx_vtestc_pd_256:
9164 IsTestPacked = true; // Fallthrough
9165 case Intrinsic::x86_sse41_ptestc:
9166 case Intrinsic::x86_avx_ptestc_256:
9168 X86CC = X86::COND_B;
9170 case Intrinsic::x86_avx_vtestnzc_ps:
9171 case Intrinsic::x86_avx_vtestnzc_pd:
9172 case Intrinsic::x86_avx_vtestnzc_ps_256:
9173 case Intrinsic::x86_avx_vtestnzc_pd_256:
9174 IsTestPacked = true; // Fallthrough
9175 case Intrinsic::x86_sse41_ptestnzc:
9176 case Intrinsic::x86_avx_ptestnzc_256:
9178 X86CC = X86::COND_A;
9182 SDValue LHS = Op.getOperand(1);
9183 SDValue RHS = Op.getOperand(2);
9184 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9185 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9186 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9187 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9188 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9191 // Fix vector shift instructions where the last operand is a non-immediate
9193 case Intrinsic::x86_sse2_pslli_w:
9194 case Intrinsic::x86_sse2_pslli_d:
9195 case Intrinsic::x86_sse2_pslli_q:
9196 case Intrinsic::x86_sse2_psrli_w:
9197 case Intrinsic::x86_sse2_psrli_d:
9198 case Intrinsic::x86_sse2_psrli_q:
9199 case Intrinsic::x86_sse2_psrai_w:
9200 case Intrinsic::x86_sse2_psrai_d:
9201 case Intrinsic::x86_mmx_pslli_w:
9202 case Intrinsic::x86_mmx_pslli_d:
9203 case Intrinsic::x86_mmx_pslli_q:
9204 case Intrinsic::x86_mmx_psrli_w:
9205 case Intrinsic::x86_mmx_psrli_d:
9206 case Intrinsic::x86_mmx_psrli_q:
9207 case Intrinsic::x86_mmx_psrai_w:
9208 case Intrinsic::x86_mmx_psrai_d: {
9209 SDValue ShAmt = Op.getOperand(2);
9210 if (isa<ConstantSDNode>(ShAmt))
9213 unsigned NewIntNo = 0;
9214 EVT ShAmtVT = MVT::v4i32;
9216 case Intrinsic::x86_sse2_pslli_w:
9217 NewIntNo = Intrinsic::x86_sse2_psll_w;
9219 case Intrinsic::x86_sse2_pslli_d:
9220 NewIntNo = Intrinsic::x86_sse2_psll_d;
9222 case Intrinsic::x86_sse2_pslli_q:
9223 NewIntNo = Intrinsic::x86_sse2_psll_q;
9225 case Intrinsic::x86_sse2_psrli_w:
9226 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9228 case Intrinsic::x86_sse2_psrli_d:
9229 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9231 case Intrinsic::x86_sse2_psrli_q:
9232 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9234 case Intrinsic::x86_sse2_psrai_w:
9235 NewIntNo = Intrinsic::x86_sse2_psra_w;
9237 case Intrinsic::x86_sse2_psrai_d:
9238 NewIntNo = Intrinsic::x86_sse2_psra_d;
9241 ShAmtVT = MVT::v2i32;
9243 case Intrinsic::x86_mmx_pslli_w:
9244 NewIntNo = Intrinsic::x86_mmx_psll_w;
9246 case Intrinsic::x86_mmx_pslli_d:
9247 NewIntNo = Intrinsic::x86_mmx_psll_d;
9249 case Intrinsic::x86_mmx_pslli_q:
9250 NewIntNo = Intrinsic::x86_mmx_psll_q;
9252 case Intrinsic::x86_mmx_psrli_w:
9253 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9255 case Intrinsic::x86_mmx_psrli_d:
9256 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9258 case Intrinsic::x86_mmx_psrli_q:
9259 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9261 case Intrinsic::x86_mmx_psrai_w:
9262 NewIntNo = Intrinsic::x86_mmx_psra_w;
9264 case Intrinsic::x86_mmx_psrai_d:
9265 NewIntNo = Intrinsic::x86_mmx_psra_d;
9267 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9273 // The vector shift intrinsics with scalars uses 32b shift amounts but
9274 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9278 ShOps[1] = DAG.getConstant(0, MVT::i32);
9279 if (ShAmtVT == MVT::v4i32) {
9280 ShOps[2] = DAG.getUNDEF(MVT::i32);
9281 ShOps[3] = DAG.getUNDEF(MVT::i32);
9282 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9284 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9285 // FIXME this must be lowered to get rid of the invalid type.
9288 EVT VT = Op.getValueType();
9289 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9290 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9291 DAG.getConstant(NewIntNo, MVT::i32),
9292 Op.getOperand(1), ShAmt);
9297 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9298 SelectionDAG &DAG) const {
9299 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9300 MFI->setReturnAddressIsTaken(true);
9302 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9303 DebugLoc dl = Op.getDebugLoc();
9306 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9308 DAG.getConstant(TD->getPointerSize(),
9309 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9310 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9311 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9313 MachinePointerInfo(), false, false, 0);
9316 // Just load the return address.
9317 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9318 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9319 RetAddrFI, MachinePointerInfo(), false, false, 0);
9322 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9323 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9324 MFI->setFrameAddressIsTaken(true);
9326 EVT VT = Op.getValueType();
9327 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9328 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9329 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9330 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9332 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9333 MachinePointerInfo(),
9338 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9339 SelectionDAG &DAG) const {
9340 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9343 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9344 MachineFunction &MF = DAG.getMachineFunction();
9345 SDValue Chain = Op.getOperand(0);
9346 SDValue Offset = Op.getOperand(1);
9347 SDValue Handler = Op.getOperand(2);
9348 DebugLoc dl = Op.getDebugLoc();
9350 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9351 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9353 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9355 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9356 DAG.getIntPtrConstant(TD->getPointerSize()));
9357 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9358 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9360 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9361 MF.getRegInfo().addLiveOut(StoreAddrReg);
9363 return DAG.getNode(X86ISD::EH_RETURN, dl,
9365 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9368 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
9369 SelectionDAG &DAG) const {
9370 SDValue Root = Op.getOperand(0);
9371 SDValue Trmp = Op.getOperand(1); // trampoline
9372 SDValue FPtr = Op.getOperand(2); // nested function
9373 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9374 DebugLoc dl = Op.getDebugLoc();
9376 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9378 if (Subtarget->is64Bit()) {
9379 SDValue OutChains[6];
9381 // Large code-model.
9382 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9383 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9385 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9386 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9388 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9390 // Load the pointer to the nested function into R11.
9391 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9392 SDValue Addr = Trmp;
9393 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9394 Addr, MachinePointerInfo(TrmpAddr),
9397 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9398 DAG.getConstant(2, MVT::i64));
9399 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9400 MachinePointerInfo(TrmpAddr, 2),
9403 // Load the 'nest' parameter value into R10.
9404 // R10 is specified in X86CallingConv.td
9405 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9406 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9407 DAG.getConstant(10, MVT::i64));
9408 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9409 Addr, MachinePointerInfo(TrmpAddr, 10),
9412 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9413 DAG.getConstant(12, MVT::i64));
9414 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9415 MachinePointerInfo(TrmpAddr, 12),
9418 // Jump to the nested function.
9419 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9420 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9421 DAG.getConstant(20, MVT::i64));
9422 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9423 Addr, MachinePointerInfo(TrmpAddr, 20),
9426 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9427 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9428 DAG.getConstant(22, MVT::i64));
9429 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9430 MachinePointerInfo(TrmpAddr, 22),
9434 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
9435 return DAG.getMergeValues(Ops, 2, dl);
9437 const Function *Func =
9438 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9439 CallingConv::ID CC = Func->getCallingConv();
9444 llvm_unreachable("Unsupported calling convention");
9445 case CallingConv::C:
9446 case CallingConv::X86_StdCall: {
9447 // Pass 'nest' parameter in ECX.
9448 // Must be kept in sync with X86CallingConv.td
9451 // Check that ECX wasn't needed by an 'inreg' parameter.
9452 FunctionType *FTy = Func->getFunctionType();
9453 const AttrListPtr &Attrs = Func->getAttributes();
9455 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9456 unsigned InRegCount = 0;
9459 for (FunctionType::param_iterator I = FTy->param_begin(),
9460 E = FTy->param_end(); I != E; ++I, ++Idx)
9461 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9462 // FIXME: should only count parameters that are lowered to integers.
9463 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9465 if (InRegCount > 2) {
9466 report_fatal_error("Nest register in use - reduce number of inreg"
9472 case CallingConv::X86_FastCall:
9473 case CallingConv::X86_ThisCall:
9474 case CallingConv::Fast:
9475 // Pass 'nest' parameter in EAX.
9476 // Must be kept in sync with X86CallingConv.td
9481 SDValue OutChains[4];
9484 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9485 DAG.getConstant(10, MVT::i32));
9486 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9488 // This is storing the opcode for MOV32ri.
9489 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9490 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9491 OutChains[0] = DAG.getStore(Root, dl,
9492 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9493 Trmp, MachinePointerInfo(TrmpAddr),
9496 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9497 DAG.getConstant(1, MVT::i32));
9498 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9499 MachinePointerInfo(TrmpAddr, 1),
9502 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9503 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9504 DAG.getConstant(5, MVT::i32));
9505 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9506 MachinePointerInfo(TrmpAddr, 5),
9509 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9510 DAG.getConstant(6, MVT::i32));
9511 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9512 MachinePointerInfo(TrmpAddr, 6),
9516 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
9517 return DAG.getMergeValues(Ops, 2, dl);
9521 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9522 SelectionDAG &DAG) const {
9524 The rounding mode is in bits 11:10 of FPSR, and has the following
9531 FLT_ROUNDS, on the other hand, expects the following:
9538 To perform the conversion, we do:
9539 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9542 MachineFunction &MF = DAG.getMachineFunction();
9543 const TargetMachine &TM = MF.getTarget();
9544 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9545 unsigned StackAlignment = TFI.getStackAlignment();
9546 EVT VT = Op.getValueType();
9547 DebugLoc DL = Op.getDebugLoc();
9549 // Save FP Control Word to stack slot
9550 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9551 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9554 MachineMemOperand *MMO =
9555 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9556 MachineMemOperand::MOStore, 2, 2);
9558 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9559 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9560 DAG.getVTList(MVT::Other),
9561 Ops, 2, MVT::i16, MMO);
9563 // Load FP Control Word from stack slot
9564 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9565 MachinePointerInfo(), false, false, 0);
9567 // Transform as necessary
9569 DAG.getNode(ISD::SRL, DL, MVT::i16,
9570 DAG.getNode(ISD::AND, DL, MVT::i16,
9571 CWD, DAG.getConstant(0x800, MVT::i16)),
9572 DAG.getConstant(11, MVT::i8));
9574 DAG.getNode(ISD::SRL, DL, MVT::i16,
9575 DAG.getNode(ISD::AND, DL, MVT::i16,
9576 CWD, DAG.getConstant(0x400, MVT::i16)),
9577 DAG.getConstant(9, MVT::i8));
9580 DAG.getNode(ISD::AND, DL, MVT::i16,
9581 DAG.getNode(ISD::ADD, DL, MVT::i16,
9582 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9583 DAG.getConstant(1, MVT::i16)),
9584 DAG.getConstant(3, MVT::i16));
9587 return DAG.getNode((VT.getSizeInBits() < 16 ?
9588 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9591 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9592 EVT VT = Op.getValueType();
9594 unsigned NumBits = VT.getSizeInBits();
9595 DebugLoc dl = Op.getDebugLoc();
9597 Op = Op.getOperand(0);
9598 if (VT == MVT::i8) {
9599 // Zero extend to i32 since there is not an i8 bsr.
9601 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9604 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9605 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9606 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9608 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9611 DAG.getConstant(NumBits+NumBits-1, OpVT),
9612 DAG.getConstant(X86::COND_E, MVT::i8),
9615 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9617 // Finally xor with NumBits-1.
9618 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9621 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9625 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9626 EVT VT = Op.getValueType();
9628 unsigned NumBits = VT.getSizeInBits();
9629 DebugLoc dl = Op.getDebugLoc();
9631 Op = Op.getOperand(0);
9632 if (VT == MVT::i8) {
9634 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9637 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9638 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9639 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9641 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9644 DAG.getConstant(NumBits, OpVT),
9645 DAG.getConstant(X86::COND_E, MVT::i8),
9648 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9651 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9655 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9656 // ones, and then concatenate the result back.
9657 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9658 EVT VT = Op.getValueType();
9660 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9661 "Unsupported value type for operation");
9663 int NumElems = VT.getVectorNumElements();
9664 DebugLoc dl = Op.getDebugLoc();
9665 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9666 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9668 // Extract the LHS vectors
9669 SDValue LHS = Op.getOperand(0);
9670 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9671 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9673 // Extract the RHS vectors
9674 SDValue RHS = Op.getOperand(1);
9675 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9676 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9678 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9679 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9681 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9682 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9683 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9686 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9687 assert(Op.getValueType().getSizeInBits() == 256 &&
9688 Op.getValueType().isInteger() &&
9689 "Only handle AVX 256-bit vector integer operation");
9690 return Lower256IntArith(Op, DAG);
9693 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9694 assert(Op.getValueType().getSizeInBits() == 256 &&
9695 Op.getValueType().isInteger() &&
9696 "Only handle AVX 256-bit vector integer operation");
9697 return Lower256IntArith(Op, DAG);
9700 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9701 EVT VT = Op.getValueType();
9703 // Decompose 256-bit ops into smaller 128-bit ops.
9704 if (VT.getSizeInBits() == 256)
9705 return Lower256IntArith(Op, DAG);
9707 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9708 DebugLoc dl = Op.getDebugLoc();
9710 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9711 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9712 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9713 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9714 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9716 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9717 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9718 // return AloBlo + AloBhi + AhiBlo;
9720 SDValue A = Op.getOperand(0);
9721 SDValue B = Op.getOperand(1);
9723 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9724 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9725 A, DAG.getConstant(32, MVT::i32));
9726 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9727 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9728 B, DAG.getConstant(32, MVT::i32));
9729 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9730 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9732 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9733 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9735 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9736 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9738 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9739 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9740 AloBhi, DAG.getConstant(32, MVT::i32));
9741 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9742 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9743 AhiBlo, DAG.getConstant(32, MVT::i32));
9744 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9745 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9749 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9751 EVT VT = Op.getValueType();
9752 DebugLoc dl = Op.getDebugLoc();
9753 SDValue R = Op.getOperand(0);
9754 SDValue Amt = Op.getOperand(1);
9755 LLVMContext *Context = DAG.getContext();
9757 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
9760 // Decompose 256-bit shifts into smaller 128-bit shifts.
9761 if (VT.getSizeInBits() == 256) {
9762 int NumElems = VT.getVectorNumElements();
9763 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9764 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9766 // Extract the two vectors
9767 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
9768 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
9771 // Recreate the shift amount vectors
9773 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
9774 // Constant shift amount
9775 SmallVector<SDValue, 4> Amt1Csts;
9776 SmallVector<SDValue, 4> Amt2Csts;
9777 for (int i = 0; i < NumElems/2; ++i)
9778 Amt1Csts.push_back(Amt->getOperand(i));
9779 for (int i = NumElems/2; i < NumElems; ++i)
9780 Amt2Csts.push_back(Amt->getOperand(i));
9782 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9783 &Amt1Csts[0], NumElems/2);
9784 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9785 &Amt2Csts[0], NumElems/2);
9787 // Variable shift amount
9788 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
9789 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
9793 // Issue new vector shifts for the smaller types
9794 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
9795 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
9797 // Concatenate the result back
9798 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
9801 // Optimize shl/srl/sra with constant shift amount.
9802 if (isSplatVector(Amt.getNode())) {
9803 SDValue SclrAmt = Amt->getOperand(0);
9804 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9805 uint64_t ShiftAmt = C->getZExtValue();
9807 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
9808 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9809 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9810 R, DAG.getConstant(ShiftAmt, MVT::i32));
9812 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
9813 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9814 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9815 R, DAG.getConstant(ShiftAmt, MVT::i32));
9817 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
9818 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9819 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9820 R, DAG.getConstant(ShiftAmt, MVT::i32));
9822 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
9823 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9824 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9825 R, DAG.getConstant(ShiftAmt, MVT::i32));
9827 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
9828 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9829 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9830 R, DAG.getConstant(ShiftAmt, MVT::i32));
9832 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
9833 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9834 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9835 R, DAG.getConstant(ShiftAmt, MVT::i32));
9837 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
9838 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9839 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9840 R, DAG.getConstant(ShiftAmt, MVT::i32));
9842 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9843 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9844 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9845 R, DAG.getConstant(ShiftAmt, MVT::i32));
9849 // Lower SHL with variable shift amount.
9850 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
9851 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9852 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9853 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
9855 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
9857 std::vector<Constant*> CV(4, CI);
9858 Constant *C = ConstantVector::get(CV);
9859 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9860 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9861 MachinePointerInfo::getConstantPool(),
9864 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
9865 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
9866 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
9867 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
9869 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
9871 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9872 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9873 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
9875 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
9876 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
9878 std::vector<Constant*> CVM1(16, CM1);
9879 std::vector<Constant*> CVM2(16, CM2);
9880 Constant *C = ConstantVector::get(CVM1);
9881 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9882 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9883 MachinePointerInfo::getConstantPool(),
9886 // r = pblendv(r, psllw(r & (char16)15, 4), a);
9887 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9888 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9889 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9890 DAG.getConstant(4, MVT::i32));
9891 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9893 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9895 C = ConstantVector::get(CVM2);
9896 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9897 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9898 MachinePointerInfo::getConstantPool(),
9901 // r = pblendv(r, psllw(r & (char16)63, 2), a);
9902 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9903 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9904 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9905 DAG.getConstant(2, MVT::i32));
9906 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9908 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9910 // return pblendv(r, r+r, a);
9911 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
9912 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
9918 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
9919 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
9920 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
9921 // looks for this combo and may remove the "setcc" instruction if the "setcc"
9922 // has only one use.
9923 SDNode *N = Op.getNode();
9924 SDValue LHS = N->getOperand(0);
9925 SDValue RHS = N->getOperand(1);
9926 unsigned BaseOp = 0;
9928 DebugLoc DL = Op.getDebugLoc();
9929 switch (Op.getOpcode()) {
9930 default: llvm_unreachable("Unknown ovf instruction!");
9932 // A subtract of one will be selected as a INC. Note that INC doesn't
9933 // set CF, so we can't do this for UADDO.
9934 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9936 BaseOp = X86ISD::INC;
9940 BaseOp = X86ISD::ADD;
9944 BaseOp = X86ISD::ADD;
9948 // A subtract of one will be selected as a DEC. Note that DEC doesn't
9949 // set CF, so we can't do this for USUBO.
9950 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9952 BaseOp = X86ISD::DEC;
9956 BaseOp = X86ISD::SUB;
9960 BaseOp = X86ISD::SUB;
9964 BaseOp = X86ISD::SMUL;
9967 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
9968 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
9970 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
9973 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9974 DAG.getConstant(X86::COND_O, MVT::i32),
9975 SDValue(Sum.getNode(), 2));
9977 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9981 // Also sets EFLAGS.
9982 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
9983 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
9986 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
9987 DAG.getConstant(Cond, MVT::i32),
9988 SDValue(Sum.getNode(), 1));
9990 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9993 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
9994 DebugLoc dl = Op.getDebugLoc();
9995 SDNode* Node = Op.getNode();
9996 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
9997 EVT VT = Node->getValueType(0);
9999 if (Subtarget->hasSSE2() && VT.isVector()) {
10000 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10001 ExtraVT.getScalarType().getSizeInBits();
10002 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10004 unsigned SHLIntrinsicsID = 0;
10005 unsigned SRAIntrinsicsID = 0;
10006 switch (VT.getSimpleVT().SimpleTy) {
10010 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q;
10011 SRAIntrinsicsID = 0;
10015 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10016 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10020 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10021 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10026 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10027 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10028 Node->getOperand(0), ShAmt);
10030 // In case of 1 bit sext, no need to shr
10031 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
10033 if (SRAIntrinsicsID) {
10034 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10035 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10045 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10046 DebugLoc dl = Op.getDebugLoc();
10048 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10049 // There isn't any reason to disable it if the target processor supports it.
10050 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10051 SDValue Chain = Op.getOperand(0);
10052 SDValue Zero = DAG.getConstant(0, MVT::i32);
10054 DAG.getRegister(X86::ESP, MVT::i32), // Base
10055 DAG.getTargetConstant(1, MVT::i8), // Scale
10056 DAG.getRegister(0, MVT::i32), // Index
10057 DAG.getTargetConstant(0, MVT::i32), // Disp
10058 DAG.getRegister(0, MVT::i32), // Segment.
10063 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10064 array_lengthof(Ops));
10065 return SDValue(Res, 0);
10068 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10070 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10072 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10073 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10074 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10075 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10077 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10078 if (!Op1 && !Op2 && !Op3 && Op4)
10079 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10081 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10082 if (Op1 && !Op2 && !Op3 && !Op4)
10083 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10085 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10087 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10090 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10091 SelectionDAG &DAG) const {
10092 DebugLoc dl = Op.getDebugLoc();
10093 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10094 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10095 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10096 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10098 // The only fence that needs an instruction is a sequentially-consistent
10099 // cross-thread fence.
10100 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10101 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10102 // no-sse2). There isn't any reason to disable it if the target processor
10104 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10105 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10107 SDValue Chain = Op.getOperand(0);
10108 SDValue Zero = DAG.getConstant(0, MVT::i32);
10110 DAG.getRegister(X86::ESP, MVT::i32), // Base
10111 DAG.getTargetConstant(1, MVT::i8), // Scale
10112 DAG.getRegister(0, MVT::i32), // Index
10113 DAG.getTargetConstant(0, MVT::i32), // Disp
10114 DAG.getRegister(0, MVT::i32), // Segment.
10119 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10120 array_lengthof(Ops));
10121 return SDValue(Res, 0);
10124 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10125 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10129 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10130 EVT T = Op.getValueType();
10131 DebugLoc DL = Op.getDebugLoc();
10134 switch(T.getSimpleVT().SimpleTy) {
10136 assert(false && "Invalid value type!");
10137 case MVT::i8: Reg = X86::AL; size = 1; break;
10138 case MVT::i16: Reg = X86::AX; size = 2; break;
10139 case MVT::i32: Reg = X86::EAX; size = 4; break;
10141 assert(Subtarget->is64Bit() && "Node not type legal!");
10142 Reg = X86::RAX; size = 8;
10145 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10146 Op.getOperand(2), SDValue());
10147 SDValue Ops[] = { cpIn.getValue(0),
10150 DAG.getTargetConstant(size, MVT::i8),
10151 cpIn.getValue(1) };
10152 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10153 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10154 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10157 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10161 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10162 SelectionDAG &DAG) const {
10163 assert(Subtarget->is64Bit() && "Result not type legalized?");
10164 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10165 SDValue TheChain = Op.getOperand(0);
10166 DebugLoc dl = Op.getDebugLoc();
10167 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10168 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10169 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10171 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10172 DAG.getConstant(32, MVT::i8));
10174 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10177 return DAG.getMergeValues(Ops, 2, dl);
10180 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10181 SelectionDAG &DAG) const {
10182 EVT SrcVT = Op.getOperand(0).getValueType();
10183 EVT DstVT = Op.getValueType();
10184 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10185 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10186 assert((DstVT == MVT::i64 ||
10187 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10188 "Unexpected custom BITCAST");
10189 // i64 <=> MMX conversions are Legal.
10190 if (SrcVT==MVT::i64 && DstVT.isVector())
10192 if (DstVT==MVT::i64 && SrcVT.isVector())
10194 // MMX <=> MMX conversions are Legal.
10195 if (SrcVT.isVector() && DstVT.isVector())
10197 // All other conversions need to be expanded.
10201 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10202 SDNode *Node = Op.getNode();
10203 DebugLoc dl = Node->getDebugLoc();
10204 EVT T = Node->getValueType(0);
10205 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10206 DAG.getConstant(0, T), Node->getOperand(2));
10207 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10208 cast<AtomicSDNode>(Node)->getMemoryVT(),
10209 Node->getOperand(0),
10210 Node->getOperand(1), negOp,
10211 cast<AtomicSDNode>(Node)->getSrcValue(),
10212 cast<AtomicSDNode>(Node)->getAlignment(),
10213 cast<AtomicSDNode>(Node)->getOrdering(),
10214 cast<AtomicSDNode>(Node)->getSynchScope());
10217 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10218 SDNode *Node = Op.getNode();
10219 DebugLoc dl = Node->getDebugLoc();
10220 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10222 // Convert seq_cst store -> xchg
10223 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10224 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10225 // (The only way to get a 16-byte store is cmpxchg16b)
10226 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10227 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10228 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10229 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10230 cast<AtomicSDNode>(Node)->getMemoryVT(),
10231 Node->getOperand(0),
10232 Node->getOperand(1), Node->getOperand(2),
10233 cast<AtomicSDNode>(Node)->getMemOperand(),
10234 cast<AtomicSDNode>(Node)->getOrdering(),
10235 cast<AtomicSDNode>(Node)->getSynchScope());
10236 return Swap.getValue(1);
10238 // Other atomic stores have a simple pattern.
10242 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10243 EVT VT = Op.getNode()->getValueType(0);
10245 // Let legalize expand this if it isn't a legal type yet.
10246 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10249 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10252 bool ExtraOp = false;
10253 switch (Op.getOpcode()) {
10254 default: assert(0 && "Invalid code");
10255 case ISD::ADDC: Opc = X86ISD::ADD; break;
10256 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10257 case ISD::SUBC: Opc = X86ISD::SUB; break;
10258 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10262 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10264 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10265 Op.getOperand(1), Op.getOperand(2));
10268 /// LowerOperation - Provide custom lowering hooks for some operations.
10270 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10271 switch (Op.getOpcode()) {
10272 default: llvm_unreachable("Should not custom lower this!");
10273 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10274 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10275 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10276 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10277 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10278 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10279 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10280 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10281 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10282 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10283 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10284 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10285 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10286 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10287 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10288 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10289 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10290 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10291 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10292 case ISD::SHL_PARTS:
10293 case ISD::SRA_PARTS:
10294 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10295 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10296 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10297 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10298 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10299 case ISD::FABS: return LowerFABS(Op, DAG);
10300 case ISD::FNEG: return LowerFNEG(Op, DAG);
10301 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10302 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10303 case ISD::SETCC: return LowerSETCC(Op, DAG);
10304 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
10305 case ISD::SELECT: return LowerSELECT(Op, DAG);
10306 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10307 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10308 case ISD::VASTART: return LowerVASTART(Op, DAG);
10309 case ISD::VAARG: return LowerVAARG(Op, DAG);
10310 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10311 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10312 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10313 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10314 case ISD::FRAME_TO_ARGS_OFFSET:
10315 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10316 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10317 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10318 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
10319 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10320 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10321 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10322 case ISD::MUL: return LowerMUL(Op, DAG);
10325 case ISD::SHL: return LowerShift(Op, DAG);
10331 case ISD::UMULO: return LowerXALUO(Op, DAG);
10332 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10333 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10337 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10338 case ISD::ADD: return LowerADD(Op, DAG);
10339 case ISD::SUB: return LowerSUB(Op, DAG);
10343 static void ReplaceATOMIC_LOAD(SDNode *Node,
10344 SmallVectorImpl<SDValue> &Results,
10345 SelectionDAG &DAG) {
10346 DebugLoc dl = Node->getDebugLoc();
10347 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10349 // Convert wide load -> cmpxchg8b/cmpxchg16b
10350 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10351 // (The only way to get a 16-byte load is cmpxchg16b)
10352 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10353 SDValue Zero = DAG.getConstant(0, VT);
10354 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10355 Node->getOperand(0),
10356 Node->getOperand(1), Zero, Zero,
10357 cast<AtomicSDNode>(Node)->getMemOperand(),
10358 cast<AtomicSDNode>(Node)->getOrdering(),
10359 cast<AtomicSDNode>(Node)->getSynchScope());
10360 Results.push_back(Swap.getValue(0));
10361 Results.push_back(Swap.getValue(1));
10364 void X86TargetLowering::
10365 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10366 SelectionDAG &DAG, unsigned NewOp) const {
10367 EVT T = Node->getValueType(0);
10368 DebugLoc dl = Node->getDebugLoc();
10369 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
10371 SDValue Chain = Node->getOperand(0);
10372 SDValue In1 = Node->getOperand(1);
10373 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10374 Node->getOperand(2), DAG.getIntPtrConstant(0));
10375 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10376 Node->getOperand(2), DAG.getIntPtrConstant(1));
10377 SDValue Ops[] = { Chain, In1, In2L, In2H };
10378 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10380 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10381 cast<MemSDNode>(Node)->getMemOperand());
10382 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10383 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10384 Results.push_back(Result.getValue(2));
10387 /// ReplaceNodeResults - Replace a node with an illegal result type
10388 /// with a new node built out of custom code.
10389 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10390 SmallVectorImpl<SDValue>&Results,
10391 SelectionDAG &DAG) const {
10392 DebugLoc dl = N->getDebugLoc();
10393 switch (N->getOpcode()) {
10395 assert(false && "Do not know how to custom type legalize this operation!");
10397 case ISD::SIGN_EXTEND_INREG:
10402 // We don't want to expand or promote these.
10404 case ISD::FP_TO_SINT: {
10405 std::pair<SDValue,SDValue> Vals =
10406 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10407 SDValue FIST = Vals.first, StackSlot = Vals.second;
10408 if (FIST.getNode() != 0) {
10409 EVT VT = N->getValueType(0);
10410 // Return a load from the stack slot.
10411 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10412 MachinePointerInfo(), false, false, 0));
10416 case ISD::READCYCLECOUNTER: {
10417 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10418 SDValue TheChain = N->getOperand(0);
10419 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10420 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10422 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10424 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10425 SDValue Ops[] = { eax, edx };
10426 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10427 Results.push_back(edx.getValue(1));
10430 case ISD::ATOMIC_CMP_SWAP: {
10431 EVT T = N->getValueType(0);
10432 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10433 bool Regs64bit = T == MVT::i128;
10434 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10435 SDValue cpInL, cpInH;
10436 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10437 DAG.getConstant(0, HalfT));
10438 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10439 DAG.getConstant(1, HalfT));
10440 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10441 Regs64bit ? X86::RAX : X86::EAX,
10443 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10444 Regs64bit ? X86::RDX : X86::EDX,
10445 cpInH, cpInL.getValue(1));
10446 SDValue swapInL, swapInH;
10447 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10448 DAG.getConstant(0, HalfT));
10449 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10450 DAG.getConstant(1, HalfT));
10451 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10452 Regs64bit ? X86::RBX : X86::EBX,
10453 swapInL, cpInH.getValue(1));
10454 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10455 Regs64bit ? X86::RCX : X86::ECX,
10456 swapInH, swapInL.getValue(1));
10457 SDValue Ops[] = { swapInH.getValue(0),
10459 swapInH.getValue(1) };
10460 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10461 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10462 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10463 X86ISD::LCMPXCHG8_DAG;
10464 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10466 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10467 Regs64bit ? X86::RAX : X86::EAX,
10468 HalfT, Result.getValue(1));
10469 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10470 Regs64bit ? X86::RDX : X86::EDX,
10471 HalfT, cpOutL.getValue(2));
10472 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10473 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10474 Results.push_back(cpOutH.getValue(1));
10477 case ISD::ATOMIC_LOAD_ADD:
10478 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10480 case ISD::ATOMIC_LOAD_AND:
10481 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10483 case ISD::ATOMIC_LOAD_NAND:
10484 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10486 case ISD::ATOMIC_LOAD_OR:
10487 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10489 case ISD::ATOMIC_LOAD_SUB:
10490 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10492 case ISD::ATOMIC_LOAD_XOR:
10493 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10495 case ISD::ATOMIC_SWAP:
10496 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10498 case ISD::ATOMIC_LOAD:
10499 ReplaceATOMIC_LOAD(N, Results, DAG);
10503 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10505 default: return NULL;
10506 case X86ISD::BSF: return "X86ISD::BSF";
10507 case X86ISD::BSR: return "X86ISD::BSR";
10508 case X86ISD::SHLD: return "X86ISD::SHLD";
10509 case X86ISD::SHRD: return "X86ISD::SHRD";
10510 case X86ISD::FAND: return "X86ISD::FAND";
10511 case X86ISD::FOR: return "X86ISD::FOR";
10512 case X86ISD::FXOR: return "X86ISD::FXOR";
10513 case X86ISD::FSRL: return "X86ISD::FSRL";
10514 case X86ISD::FILD: return "X86ISD::FILD";
10515 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10516 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10517 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10518 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10519 case X86ISD::FLD: return "X86ISD::FLD";
10520 case X86ISD::FST: return "X86ISD::FST";
10521 case X86ISD::CALL: return "X86ISD::CALL";
10522 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10523 case X86ISD::BT: return "X86ISD::BT";
10524 case X86ISD::CMP: return "X86ISD::CMP";
10525 case X86ISD::COMI: return "X86ISD::COMI";
10526 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10527 case X86ISD::SETCC: return "X86ISD::SETCC";
10528 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10529 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10530 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10531 case X86ISD::CMOV: return "X86ISD::CMOV";
10532 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10533 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10534 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10535 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10536 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10537 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10538 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10539 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10540 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10541 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10542 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10543 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10544 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10545 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10546 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
10547 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
10548 case X86ISD::PSIGND: return "X86ISD::PSIGND";
10549 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
10550 case X86ISD::FMAX: return "X86ISD::FMAX";
10551 case X86ISD::FMIN: return "X86ISD::FMIN";
10552 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10553 case X86ISD::FRCP: return "X86ISD::FRCP";
10554 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10555 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10556 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10557 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10558 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10559 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10560 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10561 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10562 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10563 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10564 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10565 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10566 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10567 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10568 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10569 case X86ISD::VSHL: return "X86ISD::VSHL";
10570 case X86ISD::VSRL: return "X86ISD::VSRL";
10571 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10572 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10573 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10574 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10575 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10576 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10577 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10578 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10579 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10580 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10581 case X86ISD::ADD: return "X86ISD::ADD";
10582 case X86ISD::SUB: return "X86ISD::SUB";
10583 case X86ISD::ADC: return "X86ISD::ADC";
10584 case X86ISD::SBB: return "X86ISD::SBB";
10585 case X86ISD::SMUL: return "X86ISD::SMUL";
10586 case X86ISD::UMUL: return "X86ISD::UMUL";
10587 case X86ISD::INC: return "X86ISD::INC";
10588 case X86ISD::DEC: return "X86ISD::DEC";
10589 case X86ISD::OR: return "X86ISD::OR";
10590 case X86ISD::XOR: return "X86ISD::XOR";
10591 case X86ISD::AND: return "X86ISD::AND";
10592 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10593 case X86ISD::PTEST: return "X86ISD::PTEST";
10594 case X86ISD::TESTP: return "X86ISD::TESTP";
10595 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10596 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10597 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10598 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10599 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10600 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10601 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10602 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10603 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10604 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10605 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10606 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
10607 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10608 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10609 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10610 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10611 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10612 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10613 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10614 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10615 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10616 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
10617 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
10618 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
10619 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
10620 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
10621 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
10622 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
10623 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
10624 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
10625 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
10626 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
10627 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
10628 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
10629 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10630 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
10631 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
10632 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
10633 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
10634 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
10635 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10636 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10637 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10638 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10639 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
10643 // isLegalAddressingMode - Return true if the addressing mode represented
10644 // by AM is legal for this target, for a load/store of the specified type.
10645 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10647 // X86 supports extremely general addressing modes.
10648 CodeModel::Model M = getTargetMachine().getCodeModel();
10649 Reloc::Model R = getTargetMachine().getRelocationModel();
10651 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10652 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10657 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10659 // If a reference to this global requires an extra load, we can't fold it.
10660 if (isGlobalStubReference(GVFlags))
10663 // If BaseGV requires a register for the PIC base, we cannot also have a
10664 // BaseReg specified.
10665 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
10668 // If lower 4G is not available, then we must use rip-relative addressing.
10669 if ((M != CodeModel::Small || R != Reloc::Static) &&
10670 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
10674 switch (AM.Scale) {
10680 // These scales always work.
10685 // These scales are formed with basereg+scalereg. Only accept if there is
10690 default: // Other stuff never works.
10698 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
10699 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10701 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
10702 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
10703 if (NumBits1 <= NumBits2)
10708 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
10709 if (!VT1.isInteger() || !VT2.isInteger())
10711 unsigned NumBits1 = VT1.getSizeInBits();
10712 unsigned NumBits2 = VT2.getSizeInBits();
10713 if (NumBits1 <= NumBits2)
10718 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
10719 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10720 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
10723 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
10724 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10725 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
10728 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
10729 // i16 instructions are longer (0x66 prefix) and potentially slower.
10730 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
10733 /// isShuffleMaskLegal - Targets can use this to indicate that they only
10734 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
10735 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
10736 /// are assumed to be legal.
10738 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
10740 // Very little shuffling can be done for 64-bit vectors right now.
10741 if (VT.getSizeInBits() == 64)
10742 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
10744 // FIXME: pshufb, blends, shifts.
10745 return (VT.getVectorNumElements() == 2 ||
10746 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
10747 isMOVLMask(M, VT) ||
10748 isSHUFPMask(M, VT) ||
10749 isPSHUFDMask(M, VT) ||
10750 isPSHUFHWMask(M, VT) ||
10751 isPSHUFLWMask(M, VT) ||
10752 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
10753 isUNPCKLMask(M, VT) ||
10754 isUNPCKHMask(M, VT) ||
10755 isUNPCKL_v_undef_Mask(M, VT) ||
10756 isUNPCKH_v_undef_Mask(M, VT));
10760 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
10762 unsigned NumElts = VT.getVectorNumElements();
10763 // FIXME: This collection of masks seems suspect.
10766 if (NumElts == 4 && VT.getSizeInBits() == 128) {
10767 return (isMOVLMask(Mask, VT) ||
10768 isCommutedMOVLMask(Mask, VT, true) ||
10769 isSHUFPMask(Mask, VT) ||
10770 isCommutedSHUFPMask(Mask, VT));
10775 //===----------------------------------------------------------------------===//
10776 // X86 Scheduler Hooks
10777 //===----------------------------------------------------------------------===//
10779 // private utility function
10780 MachineBasicBlock *
10781 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
10782 MachineBasicBlock *MBB,
10789 TargetRegisterClass *RC,
10790 bool invSrc) const {
10791 // For the atomic bitwise operator, we generate
10794 // ld t1 = [bitinstr.addr]
10795 // op t2 = t1, [bitinstr.val]
10797 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10799 // fallthrough -->nextMBB
10800 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10801 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10802 MachineFunction::iterator MBBIter = MBB;
10805 /// First build the CFG
10806 MachineFunction *F = MBB->getParent();
10807 MachineBasicBlock *thisMBB = MBB;
10808 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10809 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10810 F->insert(MBBIter, newMBB);
10811 F->insert(MBBIter, nextMBB);
10813 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10814 nextMBB->splice(nextMBB->begin(), thisMBB,
10815 llvm::next(MachineBasicBlock::iterator(bInstr)),
10817 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10819 // Update thisMBB to fall through to newMBB
10820 thisMBB->addSuccessor(newMBB);
10822 // newMBB jumps to itself and fall through to nextMBB
10823 newMBB->addSuccessor(nextMBB);
10824 newMBB->addSuccessor(newMBB);
10826 // Insert instructions into newMBB based on incoming instruction
10827 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10828 "unexpected number of operands");
10829 DebugLoc dl = bInstr->getDebugLoc();
10830 MachineOperand& destOper = bInstr->getOperand(0);
10831 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10832 int numArgs = bInstr->getNumOperands() - 1;
10833 for (int i=0; i < numArgs; ++i)
10834 argOpers[i] = &bInstr->getOperand(i+1);
10836 // x86 address has 4 operands: base, index, scale, and displacement
10837 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10838 int valArgIndx = lastAddrIndx + 1;
10840 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10841 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
10842 for (int i=0; i <= lastAddrIndx; ++i)
10843 (*MIB).addOperand(*argOpers[i]);
10845 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
10847 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
10852 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10853 assert((argOpers[valArgIndx]->isReg() ||
10854 argOpers[valArgIndx]->isImm()) &&
10855 "invalid operand");
10856 if (argOpers[valArgIndx]->isReg())
10857 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
10859 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
10861 (*MIB).addOperand(*argOpers[valArgIndx]);
10863 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
10866 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
10867 for (int i=0; i <= lastAddrIndx; ++i)
10868 (*MIB).addOperand(*argOpers[i]);
10870 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10871 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10872 bInstr->memoperands_end());
10874 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10875 MIB.addReg(EAXreg);
10878 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10880 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10884 // private utility function: 64 bit atomics on 32 bit host.
10885 MachineBasicBlock *
10886 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
10887 MachineBasicBlock *MBB,
10892 bool invSrc) const {
10893 // For the atomic bitwise operator, we generate
10894 // thisMBB (instructions are in pairs, except cmpxchg8b)
10895 // ld t1,t2 = [bitinstr.addr]
10897 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
10898 // op t5, t6 <- out1, out2, [bitinstr.val]
10899 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
10900 // mov ECX, EBX <- t5, t6
10901 // mov EAX, EDX <- t1, t2
10902 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
10903 // mov t3, t4 <- EAX, EDX
10905 // result in out1, out2
10906 // fallthrough -->nextMBB
10908 const TargetRegisterClass *RC = X86::GR32RegisterClass;
10909 const unsigned LoadOpc = X86::MOV32rm;
10910 const unsigned NotOpc = X86::NOT32r;
10911 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10912 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10913 MachineFunction::iterator MBBIter = MBB;
10916 /// First build the CFG
10917 MachineFunction *F = MBB->getParent();
10918 MachineBasicBlock *thisMBB = MBB;
10919 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10920 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10921 F->insert(MBBIter, newMBB);
10922 F->insert(MBBIter, nextMBB);
10924 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10925 nextMBB->splice(nextMBB->begin(), thisMBB,
10926 llvm::next(MachineBasicBlock::iterator(bInstr)),
10928 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10930 // Update thisMBB to fall through to newMBB
10931 thisMBB->addSuccessor(newMBB);
10933 // newMBB jumps to itself and fall through to nextMBB
10934 newMBB->addSuccessor(nextMBB);
10935 newMBB->addSuccessor(newMBB);
10937 DebugLoc dl = bInstr->getDebugLoc();
10938 // Insert instructions into newMBB based on incoming instruction
10939 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
10940 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
10941 "unexpected number of operands");
10942 MachineOperand& dest1Oper = bInstr->getOperand(0);
10943 MachineOperand& dest2Oper = bInstr->getOperand(1);
10944 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10945 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
10946 argOpers[i] = &bInstr->getOperand(i+2);
10948 // We use some of the operands multiple times, so conservatively just
10949 // clear any kill flags that might be present.
10950 if (argOpers[i]->isReg() && argOpers[i]->isUse())
10951 argOpers[i]->setIsKill(false);
10954 // x86 address has 5 operands: base, index, scale, displacement, and segment.
10955 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10957 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10958 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
10959 for (int i=0; i <= lastAddrIndx; ++i)
10960 (*MIB).addOperand(*argOpers[i]);
10961 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10962 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
10963 // add 4 to displacement.
10964 for (int i=0; i <= lastAddrIndx-2; ++i)
10965 (*MIB).addOperand(*argOpers[i]);
10966 MachineOperand newOp3 = *(argOpers[3]);
10967 if (newOp3.isImm())
10968 newOp3.setImm(newOp3.getImm()+4);
10970 newOp3.setOffset(newOp3.getOffset()+4);
10971 (*MIB).addOperand(newOp3);
10972 (*MIB).addOperand(*argOpers[lastAddrIndx]);
10974 // t3/4 are defined later, at the bottom of the loop
10975 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
10976 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
10977 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
10978 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
10979 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
10980 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
10982 // The subsequent operations should be using the destination registers of
10983 //the PHI instructions.
10985 t1 = F->getRegInfo().createVirtualRegister(RC);
10986 t2 = F->getRegInfo().createVirtualRegister(RC);
10987 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
10988 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
10990 t1 = dest1Oper.getReg();
10991 t2 = dest2Oper.getReg();
10994 int valArgIndx = lastAddrIndx + 1;
10995 assert((argOpers[valArgIndx]->isReg() ||
10996 argOpers[valArgIndx]->isImm()) &&
10997 "invalid operand");
10998 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
10999 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11000 if (argOpers[valArgIndx]->isReg())
11001 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11003 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11004 if (regOpcL != X86::MOV32rr)
11006 (*MIB).addOperand(*argOpers[valArgIndx]);
11007 assert(argOpers[valArgIndx + 1]->isReg() ==
11008 argOpers[valArgIndx]->isReg());
11009 assert(argOpers[valArgIndx + 1]->isImm() ==
11010 argOpers[valArgIndx]->isImm());
11011 if (argOpers[valArgIndx + 1]->isReg())
11012 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11014 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11015 if (regOpcH != X86::MOV32rr)
11017 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11019 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11021 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11024 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11026 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11029 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11030 for (int i=0; i <= lastAddrIndx; ++i)
11031 (*MIB).addOperand(*argOpers[i]);
11033 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11034 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11035 bInstr->memoperands_end());
11037 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11038 MIB.addReg(X86::EAX);
11039 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11040 MIB.addReg(X86::EDX);
11043 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11045 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11049 // private utility function
11050 MachineBasicBlock *
11051 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11052 MachineBasicBlock *MBB,
11053 unsigned cmovOpc) const {
11054 // For the atomic min/max operator, we generate
11057 // ld t1 = [min/max.addr]
11058 // mov t2 = [min/max.val]
11060 // cmov[cond] t2 = t1
11062 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11064 // fallthrough -->nextMBB
11066 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11067 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11068 MachineFunction::iterator MBBIter = MBB;
11071 /// First build the CFG
11072 MachineFunction *F = MBB->getParent();
11073 MachineBasicBlock *thisMBB = MBB;
11074 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11075 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11076 F->insert(MBBIter, newMBB);
11077 F->insert(MBBIter, nextMBB);
11079 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11080 nextMBB->splice(nextMBB->begin(), thisMBB,
11081 llvm::next(MachineBasicBlock::iterator(mInstr)),
11083 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11085 // Update thisMBB to fall through to newMBB
11086 thisMBB->addSuccessor(newMBB);
11088 // newMBB jumps to newMBB and fall through to nextMBB
11089 newMBB->addSuccessor(nextMBB);
11090 newMBB->addSuccessor(newMBB);
11092 DebugLoc dl = mInstr->getDebugLoc();
11093 // Insert instructions into newMBB based on incoming instruction
11094 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11095 "unexpected number of operands");
11096 MachineOperand& destOper = mInstr->getOperand(0);
11097 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11098 int numArgs = mInstr->getNumOperands() - 1;
11099 for (int i=0; i < numArgs; ++i)
11100 argOpers[i] = &mInstr->getOperand(i+1);
11102 // x86 address has 4 operands: base, index, scale, and displacement
11103 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11104 int valArgIndx = lastAddrIndx + 1;
11106 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11107 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11108 for (int i=0; i <= lastAddrIndx; ++i)
11109 (*MIB).addOperand(*argOpers[i]);
11111 // We only support register and immediate values
11112 assert((argOpers[valArgIndx]->isReg() ||
11113 argOpers[valArgIndx]->isImm()) &&
11114 "invalid operand");
11116 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11117 if (argOpers[valArgIndx]->isReg())
11118 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11120 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11121 (*MIB).addOperand(*argOpers[valArgIndx]);
11123 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11126 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11131 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11132 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11136 // Cmp and exchange if none has modified the memory location
11137 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11138 for (int i=0; i <= lastAddrIndx; ++i)
11139 (*MIB).addOperand(*argOpers[i]);
11141 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11142 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11143 mInstr->memoperands_end());
11145 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11146 MIB.addReg(X86::EAX);
11149 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11151 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11155 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11156 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11157 // in the .td file.
11158 MachineBasicBlock *
11159 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11160 unsigned numArgs, bool memArg) const {
11161 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
11162 "Target must have SSE4.2 or AVX features enabled");
11164 DebugLoc dl = MI->getDebugLoc();
11165 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11167 if (!Subtarget->hasAVX()) {
11169 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11171 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11174 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11176 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11179 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11180 for (unsigned i = 0; i < numArgs; ++i) {
11181 MachineOperand &Op = MI->getOperand(i+1);
11182 if (!(Op.isReg() && Op.isImplicit()))
11183 MIB.addOperand(Op);
11185 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
11186 .addReg(X86::XMM0);
11188 MI->eraseFromParent();
11192 MachineBasicBlock *
11193 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11194 DebugLoc dl = MI->getDebugLoc();
11195 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11197 // Address into RAX/EAX, other two args into ECX, EDX.
11198 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11199 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11200 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11201 for (int i = 0; i < X86::AddrNumOperands; ++i)
11202 MIB.addOperand(MI->getOperand(i));
11204 unsigned ValOps = X86::AddrNumOperands;
11205 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11206 .addReg(MI->getOperand(ValOps).getReg());
11207 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11208 .addReg(MI->getOperand(ValOps+1).getReg());
11210 // The instruction doesn't actually take any operands though.
11211 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11213 MI->eraseFromParent(); // The pseudo is gone now.
11217 MachineBasicBlock *
11218 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11219 DebugLoc dl = MI->getDebugLoc();
11220 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11222 // First arg in ECX, the second in EAX.
11223 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11224 .addReg(MI->getOperand(0).getReg());
11225 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11226 .addReg(MI->getOperand(1).getReg());
11228 // The instruction doesn't actually take any operands though.
11229 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11231 MI->eraseFromParent(); // The pseudo is gone now.
11235 MachineBasicBlock *
11236 X86TargetLowering::EmitVAARG64WithCustomInserter(
11238 MachineBasicBlock *MBB) const {
11239 // Emit va_arg instruction on X86-64.
11241 // Operands to this pseudo-instruction:
11242 // 0 ) Output : destination address (reg)
11243 // 1-5) Input : va_list address (addr, i64mem)
11244 // 6 ) ArgSize : Size (in bytes) of vararg type
11245 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11246 // 8 ) Align : Alignment of type
11247 // 9 ) EFLAGS (implicit-def)
11249 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11250 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11252 unsigned DestReg = MI->getOperand(0).getReg();
11253 MachineOperand &Base = MI->getOperand(1);
11254 MachineOperand &Scale = MI->getOperand(2);
11255 MachineOperand &Index = MI->getOperand(3);
11256 MachineOperand &Disp = MI->getOperand(4);
11257 MachineOperand &Segment = MI->getOperand(5);
11258 unsigned ArgSize = MI->getOperand(6).getImm();
11259 unsigned ArgMode = MI->getOperand(7).getImm();
11260 unsigned Align = MI->getOperand(8).getImm();
11262 // Memory Reference
11263 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11264 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11265 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11267 // Machine Information
11268 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11269 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11270 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11271 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11272 DebugLoc DL = MI->getDebugLoc();
11274 // struct va_list {
11277 // i64 overflow_area (address)
11278 // i64 reg_save_area (address)
11280 // sizeof(va_list) = 24
11281 // alignment(va_list) = 8
11283 unsigned TotalNumIntRegs = 6;
11284 unsigned TotalNumXMMRegs = 8;
11285 bool UseGPOffset = (ArgMode == 1);
11286 bool UseFPOffset = (ArgMode == 2);
11287 unsigned MaxOffset = TotalNumIntRegs * 8 +
11288 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11290 /* Align ArgSize to a multiple of 8 */
11291 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11292 bool NeedsAlign = (Align > 8);
11294 MachineBasicBlock *thisMBB = MBB;
11295 MachineBasicBlock *overflowMBB;
11296 MachineBasicBlock *offsetMBB;
11297 MachineBasicBlock *endMBB;
11299 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11300 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11301 unsigned OffsetReg = 0;
11303 if (!UseGPOffset && !UseFPOffset) {
11304 // If we only pull from the overflow region, we don't create a branch.
11305 // We don't need to alter control flow.
11306 OffsetDestReg = 0; // unused
11307 OverflowDestReg = DestReg;
11310 overflowMBB = thisMBB;
11313 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11314 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11315 // If not, pull from overflow_area. (branch to overflowMBB)
11320 // offsetMBB overflowMBB
11325 // Registers for the PHI in endMBB
11326 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11327 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11329 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11330 MachineFunction *MF = MBB->getParent();
11331 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11332 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11333 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11335 MachineFunction::iterator MBBIter = MBB;
11338 // Insert the new basic blocks
11339 MF->insert(MBBIter, offsetMBB);
11340 MF->insert(MBBIter, overflowMBB);
11341 MF->insert(MBBIter, endMBB);
11343 // Transfer the remainder of MBB and its successor edges to endMBB.
11344 endMBB->splice(endMBB->begin(), thisMBB,
11345 llvm::next(MachineBasicBlock::iterator(MI)),
11347 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11349 // Make offsetMBB and overflowMBB successors of thisMBB
11350 thisMBB->addSuccessor(offsetMBB);
11351 thisMBB->addSuccessor(overflowMBB);
11353 // endMBB is a successor of both offsetMBB and overflowMBB
11354 offsetMBB->addSuccessor(endMBB);
11355 overflowMBB->addSuccessor(endMBB);
11357 // Load the offset value into a register
11358 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11359 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11363 .addDisp(Disp, UseFPOffset ? 4 : 0)
11364 .addOperand(Segment)
11365 .setMemRefs(MMOBegin, MMOEnd);
11367 // Check if there is enough room left to pull this argument.
11368 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11370 .addImm(MaxOffset + 8 - ArgSizeA8);
11372 // Branch to "overflowMBB" if offset >= max
11373 // Fall through to "offsetMBB" otherwise
11374 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11375 .addMBB(overflowMBB);
11378 // In offsetMBB, emit code to use the reg_save_area.
11380 assert(OffsetReg != 0);
11382 // Read the reg_save_area address.
11383 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11384 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11389 .addOperand(Segment)
11390 .setMemRefs(MMOBegin, MMOEnd);
11392 // Zero-extend the offset
11393 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11394 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11397 .addImm(X86::sub_32bit);
11399 // Add the offset to the reg_save_area to get the final address.
11400 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11401 .addReg(OffsetReg64)
11402 .addReg(RegSaveReg);
11404 // Compute the offset for the next argument
11405 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11406 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11408 .addImm(UseFPOffset ? 16 : 8);
11410 // Store it back into the va_list.
11411 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11415 .addDisp(Disp, UseFPOffset ? 4 : 0)
11416 .addOperand(Segment)
11417 .addReg(NextOffsetReg)
11418 .setMemRefs(MMOBegin, MMOEnd);
11421 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11426 // Emit code to use overflow area
11429 // Load the overflow_area address into a register.
11430 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11431 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11436 .addOperand(Segment)
11437 .setMemRefs(MMOBegin, MMOEnd);
11439 // If we need to align it, do so. Otherwise, just copy the address
11440 // to OverflowDestReg.
11442 // Align the overflow address
11443 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11444 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11446 // aligned_addr = (addr + (align-1)) & ~(align-1)
11447 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11448 .addReg(OverflowAddrReg)
11451 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11453 .addImm(~(uint64_t)(Align-1));
11455 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11456 .addReg(OverflowAddrReg);
11459 // Compute the next overflow address after this argument.
11460 // (the overflow address should be kept 8-byte aligned)
11461 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11462 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11463 .addReg(OverflowDestReg)
11464 .addImm(ArgSizeA8);
11466 // Store the new overflow address.
11467 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11472 .addOperand(Segment)
11473 .addReg(NextAddrReg)
11474 .setMemRefs(MMOBegin, MMOEnd);
11476 // If we branched, emit the PHI to the front of endMBB.
11478 BuildMI(*endMBB, endMBB->begin(), DL,
11479 TII->get(X86::PHI), DestReg)
11480 .addReg(OffsetDestReg).addMBB(offsetMBB)
11481 .addReg(OverflowDestReg).addMBB(overflowMBB);
11484 // Erase the pseudo instruction
11485 MI->eraseFromParent();
11490 MachineBasicBlock *
11491 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11493 MachineBasicBlock *MBB) const {
11494 // Emit code to save XMM registers to the stack. The ABI says that the
11495 // number of registers to save is given in %al, so it's theoretically
11496 // possible to do an indirect jump trick to avoid saving all of them,
11497 // however this code takes a simpler approach and just executes all
11498 // of the stores if %al is non-zero. It's less code, and it's probably
11499 // easier on the hardware branch predictor, and stores aren't all that
11500 // expensive anyway.
11502 // Create the new basic blocks. One block contains all the XMM stores,
11503 // and one block is the final destination regardless of whether any
11504 // stores were performed.
11505 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11506 MachineFunction *F = MBB->getParent();
11507 MachineFunction::iterator MBBIter = MBB;
11509 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11510 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11511 F->insert(MBBIter, XMMSaveMBB);
11512 F->insert(MBBIter, EndMBB);
11514 // Transfer the remainder of MBB and its successor edges to EndMBB.
11515 EndMBB->splice(EndMBB->begin(), MBB,
11516 llvm::next(MachineBasicBlock::iterator(MI)),
11518 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11520 // The original block will now fall through to the XMM save block.
11521 MBB->addSuccessor(XMMSaveMBB);
11522 // The XMMSaveMBB will fall through to the end block.
11523 XMMSaveMBB->addSuccessor(EndMBB);
11525 // Now add the instructions.
11526 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11527 DebugLoc DL = MI->getDebugLoc();
11529 unsigned CountReg = MI->getOperand(0).getReg();
11530 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11531 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11533 if (!Subtarget->isTargetWin64()) {
11534 // If %al is 0, branch around the XMM save block.
11535 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11536 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11537 MBB->addSuccessor(EndMBB);
11540 // In the XMM save block, save all the XMM argument registers.
11541 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11542 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11543 MachineMemOperand *MMO =
11544 F->getMachineMemOperand(
11545 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11546 MachineMemOperand::MOStore,
11547 /*Size=*/16, /*Align=*/16);
11548 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
11549 .addFrameIndex(RegSaveFrameIndex)
11550 .addImm(/*Scale=*/1)
11551 .addReg(/*IndexReg=*/0)
11552 .addImm(/*Disp=*/Offset)
11553 .addReg(/*Segment=*/0)
11554 .addReg(MI->getOperand(i).getReg())
11555 .addMemOperand(MMO);
11558 MI->eraseFromParent(); // The pseudo instruction is gone now.
11563 MachineBasicBlock *
11564 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11565 MachineBasicBlock *BB) const {
11566 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11567 DebugLoc DL = MI->getDebugLoc();
11569 // To "insert" a SELECT_CC instruction, we actually have to insert the
11570 // diamond control-flow pattern. The incoming instruction knows the
11571 // destination vreg to set, the condition code register to branch on, the
11572 // true/false values to select between, and a branch opcode to use.
11573 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11574 MachineFunction::iterator It = BB;
11580 // cmpTY ccX, r1, r2
11582 // fallthrough --> copy0MBB
11583 MachineBasicBlock *thisMBB = BB;
11584 MachineFunction *F = BB->getParent();
11585 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11586 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11587 F->insert(It, copy0MBB);
11588 F->insert(It, sinkMBB);
11590 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11591 // live into the sink and copy blocks.
11592 const MachineFunction *MF = BB->getParent();
11593 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
11594 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
11596 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
11597 const MachineOperand &MO = MI->getOperand(I);
11598 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
11599 unsigned Reg = MO.getReg();
11600 if (Reg != X86::EFLAGS) continue;
11601 copy0MBB->addLiveIn(Reg);
11602 sinkMBB->addLiveIn(Reg);
11605 // Transfer the remainder of BB and its successor edges to sinkMBB.
11606 sinkMBB->splice(sinkMBB->begin(), BB,
11607 llvm::next(MachineBasicBlock::iterator(MI)),
11609 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11611 // Add the true and fallthrough blocks as its successors.
11612 BB->addSuccessor(copy0MBB);
11613 BB->addSuccessor(sinkMBB);
11615 // Create the conditional branch instruction.
11617 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11618 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11621 // %FalseValue = ...
11622 // # fallthrough to sinkMBB
11623 copy0MBB->addSuccessor(sinkMBB);
11626 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11628 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11629 TII->get(X86::PHI), MI->getOperand(0).getReg())
11630 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11631 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11633 MI->eraseFromParent(); // The pseudo instruction is gone now.
11637 MachineBasicBlock *
11638 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
11639 MachineBasicBlock *BB) const {
11640 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11641 DebugLoc DL = MI->getDebugLoc();
11643 assert(!Subtarget->isTargetEnvMacho());
11645 // The lowering is pretty easy: we're just emitting the call to _alloca. The
11646 // non-trivial part is impdef of ESP.
11648 if (Subtarget->isTargetWin64()) {
11649 if (Subtarget->isTargetCygMing()) {
11650 // ___chkstk(Mingw64):
11651 // Clobbers R10, R11, RAX and EFLAGS.
11653 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11654 .addExternalSymbol("___chkstk")
11655 .addReg(X86::RAX, RegState::Implicit)
11656 .addReg(X86::RSP, RegState::Implicit)
11657 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
11658 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
11659 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11661 // __chkstk(MSVCRT): does not update stack pointer.
11662 // Clobbers R10, R11 and EFLAGS.
11663 // FIXME: RAX(allocated size) might be reused and not killed.
11664 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11665 .addExternalSymbol("__chkstk")
11666 .addReg(X86::RAX, RegState::Implicit)
11667 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11668 // RAX has the offset to subtracted from RSP.
11669 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
11674 const char *StackProbeSymbol =
11675 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
11677 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
11678 .addExternalSymbol(StackProbeSymbol)
11679 .addReg(X86::EAX, RegState::Implicit)
11680 .addReg(X86::ESP, RegState::Implicit)
11681 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
11682 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
11683 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11686 MI->eraseFromParent(); // The pseudo instruction is gone now.
11690 MachineBasicBlock *
11691 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
11692 MachineBasicBlock *BB) const {
11693 // This is pretty easy. We're taking the value that we received from
11694 // our load from the relocation, sticking it in either RDI (x86-64)
11695 // or EAX and doing an indirect call. The return value will then
11696 // be in the normal return register.
11697 const X86InstrInfo *TII
11698 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
11699 DebugLoc DL = MI->getDebugLoc();
11700 MachineFunction *F = BB->getParent();
11702 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
11703 assert(MI->getOperand(3).isGlobal() && "This should be a global");
11705 if (Subtarget->is64Bit()) {
11706 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11707 TII->get(X86::MOV64rm), X86::RDI)
11709 .addImm(0).addReg(0)
11710 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11711 MI->getOperand(3).getTargetFlags())
11713 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
11714 addDirectMem(MIB, X86::RDI);
11715 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
11716 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11717 TII->get(X86::MOV32rm), X86::EAX)
11719 .addImm(0).addReg(0)
11720 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11721 MI->getOperand(3).getTargetFlags())
11723 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11724 addDirectMem(MIB, X86::EAX);
11726 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11727 TII->get(X86::MOV32rm), X86::EAX)
11728 .addReg(TII->getGlobalBaseReg(F))
11729 .addImm(0).addReg(0)
11730 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11731 MI->getOperand(3).getTargetFlags())
11733 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11734 addDirectMem(MIB, X86::EAX);
11737 MI->eraseFromParent(); // The pseudo instruction is gone now.
11741 MachineBasicBlock *
11742 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
11743 MachineBasicBlock *BB) const {
11744 switch (MI->getOpcode()) {
11745 default: assert(false && "Unexpected instr type to insert");
11746 case X86::TAILJMPd64:
11747 case X86::TAILJMPr64:
11748 case X86::TAILJMPm64:
11749 assert(!"TAILJMP64 would not be touched here.");
11750 case X86::TCRETURNdi64:
11751 case X86::TCRETURNri64:
11752 case X86::TCRETURNmi64:
11753 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
11754 // On AMD64, additional defs should be added before register allocation.
11755 if (!Subtarget->isTargetWin64()) {
11756 MI->addRegisterDefined(X86::RSI);
11757 MI->addRegisterDefined(X86::RDI);
11758 MI->addRegisterDefined(X86::XMM6);
11759 MI->addRegisterDefined(X86::XMM7);
11760 MI->addRegisterDefined(X86::XMM8);
11761 MI->addRegisterDefined(X86::XMM9);
11762 MI->addRegisterDefined(X86::XMM10);
11763 MI->addRegisterDefined(X86::XMM11);
11764 MI->addRegisterDefined(X86::XMM12);
11765 MI->addRegisterDefined(X86::XMM13);
11766 MI->addRegisterDefined(X86::XMM14);
11767 MI->addRegisterDefined(X86::XMM15);
11770 case X86::WIN_ALLOCA:
11771 return EmitLoweredWinAlloca(MI, BB);
11772 case X86::TLSCall_32:
11773 case X86::TLSCall_64:
11774 return EmitLoweredTLSCall(MI, BB);
11775 case X86::CMOV_GR8:
11776 case X86::CMOV_FR32:
11777 case X86::CMOV_FR64:
11778 case X86::CMOV_V4F32:
11779 case X86::CMOV_V2F64:
11780 case X86::CMOV_V2I64:
11781 case X86::CMOV_V8F32:
11782 case X86::CMOV_V4F64:
11783 case X86::CMOV_V4I64:
11784 case X86::CMOV_GR16:
11785 case X86::CMOV_GR32:
11786 case X86::CMOV_RFP32:
11787 case X86::CMOV_RFP64:
11788 case X86::CMOV_RFP80:
11789 return EmitLoweredSelect(MI, BB);
11791 case X86::FP32_TO_INT16_IN_MEM:
11792 case X86::FP32_TO_INT32_IN_MEM:
11793 case X86::FP32_TO_INT64_IN_MEM:
11794 case X86::FP64_TO_INT16_IN_MEM:
11795 case X86::FP64_TO_INT32_IN_MEM:
11796 case X86::FP64_TO_INT64_IN_MEM:
11797 case X86::FP80_TO_INT16_IN_MEM:
11798 case X86::FP80_TO_INT32_IN_MEM:
11799 case X86::FP80_TO_INT64_IN_MEM: {
11800 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11801 DebugLoc DL = MI->getDebugLoc();
11803 // Change the floating point control register to use "round towards zero"
11804 // mode when truncating to an integer value.
11805 MachineFunction *F = BB->getParent();
11806 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
11807 addFrameReference(BuildMI(*BB, MI, DL,
11808 TII->get(X86::FNSTCW16m)), CWFrameIdx);
11810 // Load the old value of the high byte of the control word...
11812 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
11813 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
11816 // Set the high part to be round to zero...
11817 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
11820 // Reload the modified control word now...
11821 addFrameReference(BuildMI(*BB, MI, DL,
11822 TII->get(X86::FLDCW16m)), CWFrameIdx);
11824 // Restore the memory image of control word to original value
11825 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
11828 // Get the X86 opcode to use.
11830 switch (MI->getOpcode()) {
11831 default: llvm_unreachable("illegal opcode!");
11832 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
11833 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
11834 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
11835 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
11836 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
11837 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
11838 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
11839 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
11840 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
11844 MachineOperand &Op = MI->getOperand(0);
11846 AM.BaseType = X86AddressMode::RegBase;
11847 AM.Base.Reg = Op.getReg();
11849 AM.BaseType = X86AddressMode::FrameIndexBase;
11850 AM.Base.FrameIndex = Op.getIndex();
11852 Op = MI->getOperand(1);
11854 AM.Scale = Op.getImm();
11855 Op = MI->getOperand(2);
11857 AM.IndexReg = Op.getImm();
11858 Op = MI->getOperand(3);
11859 if (Op.isGlobal()) {
11860 AM.GV = Op.getGlobal();
11862 AM.Disp = Op.getImm();
11864 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
11865 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
11867 // Reload the original control word now.
11868 addFrameReference(BuildMI(*BB, MI, DL,
11869 TII->get(X86::FLDCW16m)), CWFrameIdx);
11871 MI->eraseFromParent(); // The pseudo instruction is gone now.
11874 // String/text processing lowering.
11875 case X86::PCMPISTRM128REG:
11876 case X86::VPCMPISTRM128REG:
11877 return EmitPCMP(MI, BB, 3, false /* in-mem */);
11878 case X86::PCMPISTRM128MEM:
11879 case X86::VPCMPISTRM128MEM:
11880 return EmitPCMP(MI, BB, 3, true /* in-mem */);
11881 case X86::PCMPESTRM128REG:
11882 case X86::VPCMPESTRM128REG:
11883 return EmitPCMP(MI, BB, 5, false /* in mem */);
11884 case X86::PCMPESTRM128MEM:
11885 case X86::VPCMPESTRM128MEM:
11886 return EmitPCMP(MI, BB, 5, true /* in mem */);
11888 // Thread synchronization.
11890 return EmitMonitor(MI, BB);
11892 return EmitMwait(MI, BB);
11894 // Atomic Lowering.
11895 case X86::ATOMAND32:
11896 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11897 X86::AND32ri, X86::MOV32rm,
11899 X86::NOT32r, X86::EAX,
11900 X86::GR32RegisterClass);
11901 case X86::ATOMOR32:
11902 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
11903 X86::OR32ri, X86::MOV32rm,
11905 X86::NOT32r, X86::EAX,
11906 X86::GR32RegisterClass);
11907 case X86::ATOMXOR32:
11908 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
11909 X86::XOR32ri, X86::MOV32rm,
11911 X86::NOT32r, X86::EAX,
11912 X86::GR32RegisterClass);
11913 case X86::ATOMNAND32:
11914 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11915 X86::AND32ri, X86::MOV32rm,
11917 X86::NOT32r, X86::EAX,
11918 X86::GR32RegisterClass, true);
11919 case X86::ATOMMIN32:
11920 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
11921 case X86::ATOMMAX32:
11922 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
11923 case X86::ATOMUMIN32:
11924 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
11925 case X86::ATOMUMAX32:
11926 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
11928 case X86::ATOMAND16:
11929 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11930 X86::AND16ri, X86::MOV16rm,
11932 X86::NOT16r, X86::AX,
11933 X86::GR16RegisterClass);
11934 case X86::ATOMOR16:
11935 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
11936 X86::OR16ri, X86::MOV16rm,
11938 X86::NOT16r, X86::AX,
11939 X86::GR16RegisterClass);
11940 case X86::ATOMXOR16:
11941 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
11942 X86::XOR16ri, X86::MOV16rm,
11944 X86::NOT16r, X86::AX,
11945 X86::GR16RegisterClass);
11946 case X86::ATOMNAND16:
11947 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11948 X86::AND16ri, X86::MOV16rm,
11950 X86::NOT16r, X86::AX,
11951 X86::GR16RegisterClass, true);
11952 case X86::ATOMMIN16:
11953 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
11954 case X86::ATOMMAX16:
11955 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
11956 case X86::ATOMUMIN16:
11957 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
11958 case X86::ATOMUMAX16:
11959 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
11961 case X86::ATOMAND8:
11962 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11963 X86::AND8ri, X86::MOV8rm,
11965 X86::NOT8r, X86::AL,
11966 X86::GR8RegisterClass);
11968 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
11969 X86::OR8ri, X86::MOV8rm,
11971 X86::NOT8r, X86::AL,
11972 X86::GR8RegisterClass);
11973 case X86::ATOMXOR8:
11974 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
11975 X86::XOR8ri, X86::MOV8rm,
11977 X86::NOT8r, X86::AL,
11978 X86::GR8RegisterClass);
11979 case X86::ATOMNAND8:
11980 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11981 X86::AND8ri, X86::MOV8rm,
11983 X86::NOT8r, X86::AL,
11984 X86::GR8RegisterClass, true);
11985 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
11986 // This group is for 64-bit host.
11987 case X86::ATOMAND64:
11988 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11989 X86::AND64ri32, X86::MOV64rm,
11991 X86::NOT64r, X86::RAX,
11992 X86::GR64RegisterClass);
11993 case X86::ATOMOR64:
11994 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
11995 X86::OR64ri32, X86::MOV64rm,
11997 X86::NOT64r, X86::RAX,
11998 X86::GR64RegisterClass);
11999 case X86::ATOMXOR64:
12000 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12001 X86::XOR64ri32, X86::MOV64rm,
12003 X86::NOT64r, X86::RAX,
12004 X86::GR64RegisterClass);
12005 case X86::ATOMNAND64:
12006 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12007 X86::AND64ri32, X86::MOV64rm,
12009 X86::NOT64r, X86::RAX,
12010 X86::GR64RegisterClass, true);
12011 case X86::ATOMMIN64:
12012 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12013 case X86::ATOMMAX64:
12014 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12015 case X86::ATOMUMIN64:
12016 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12017 case X86::ATOMUMAX64:
12018 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12020 // This group does 64-bit operations on a 32-bit host.
12021 case X86::ATOMAND6432:
12022 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12023 X86::AND32rr, X86::AND32rr,
12024 X86::AND32ri, X86::AND32ri,
12026 case X86::ATOMOR6432:
12027 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12028 X86::OR32rr, X86::OR32rr,
12029 X86::OR32ri, X86::OR32ri,
12031 case X86::ATOMXOR6432:
12032 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12033 X86::XOR32rr, X86::XOR32rr,
12034 X86::XOR32ri, X86::XOR32ri,
12036 case X86::ATOMNAND6432:
12037 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12038 X86::AND32rr, X86::AND32rr,
12039 X86::AND32ri, X86::AND32ri,
12041 case X86::ATOMADD6432:
12042 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12043 X86::ADD32rr, X86::ADC32rr,
12044 X86::ADD32ri, X86::ADC32ri,
12046 case X86::ATOMSUB6432:
12047 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12048 X86::SUB32rr, X86::SBB32rr,
12049 X86::SUB32ri, X86::SBB32ri,
12051 case X86::ATOMSWAP6432:
12052 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12053 X86::MOV32rr, X86::MOV32rr,
12054 X86::MOV32ri, X86::MOV32ri,
12056 case X86::VASTART_SAVE_XMM_REGS:
12057 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12059 case X86::VAARG_64:
12060 return EmitVAARG64WithCustomInserter(MI, BB);
12064 //===----------------------------------------------------------------------===//
12065 // X86 Optimization Hooks
12066 //===----------------------------------------------------------------------===//
12068 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12072 const SelectionDAG &DAG,
12073 unsigned Depth) const {
12074 unsigned Opc = Op.getOpcode();
12075 assert((Opc >= ISD::BUILTIN_OP_END ||
12076 Opc == ISD::INTRINSIC_WO_CHAIN ||
12077 Opc == ISD::INTRINSIC_W_CHAIN ||
12078 Opc == ISD::INTRINSIC_VOID) &&
12079 "Should use MaskedValueIsZero if you don't know whether Op"
12080 " is a target node!");
12082 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12096 // These nodes' second result is a boolean.
12097 if (Op.getResNo() == 0)
12100 case X86ISD::SETCC:
12101 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12102 Mask.getBitWidth() - 1);
12107 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12108 unsigned Depth) const {
12109 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12110 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12111 return Op.getValueType().getScalarType().getSizeInBits();
12117 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12118 /// node is a GlobalAddress + offset.
12119 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12120 const GlobalValue* &GA,
12121 int64_t &Offset) const {
12122 if (N->getOpcode() == X86ISD::Wrapper) {
12123 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12124 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12125 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12129 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12132 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12133 /// same as extracting the high 128-bit part of 256-bit vector and then
12134 /// inserting the result into the low part of a new 256-bit vector
12135 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12136 EVT VT = SVOp->getValueType(0);
12137 int NumElems = VT.getVectorNumElements();
12139 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12140 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12141 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12142 SVOp->getMaskElt(j) >= 0)
12148 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12149 /// same as extracting the low 128-bit part of 256-bit vector and then
12150 /// inserting the result into the high part of a new 256-bit vector
12151 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12152 EVT VT = SVOp->getValueType(0);
12153 int NumElems = VT.getVectorNumElements();
12155 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12156 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12157 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12158 SVOp->getMaskElt(j) >= 0)
12164 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12165 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12166 TargetLowering::DAGCombinerInfo &DCI) {
12167 DebugLoc dl = N->getDebugLoc();
12168 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12169 SDValue V1 = SVOp->getOperand(0);
12170 SDValue V2 = SVOp->getOperand(1);
12171 EVT VT = SVOp->getValueType(0);
12172 int NumElems = VT.getVectorNumElements();
12174 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12175 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12179 // V UNDEF BUILD_VECTOR UNDEF
12181 // CONCAT_VECTOR CONCAT_VECTOR
12184 // RESULT: V + zero extended
12186 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12187 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12188 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12191 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12194 // To match the shuffle mask, the first half of the mask should
12195 // be exactly the first vector, and all the rest a splat with the
12196 // first element of the second one.
12197 for (int i = 0; i < NumElems/2; ++i)
12198 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12199 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12202 // Emit a zeroed vector and insert the desired subvector on its
12204 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl);
12205 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12206 DAG.getConstant(0, MVT::i32), DAG, dl);
12207 return DCI.CombineTo(N, InsV);
12210 //===--------------------------------------------------------------------===//
12211 // Combine some shuffles into subvector extracts and inserts:
12214 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12215 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12216 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12218 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12219 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12220 return DCI.CombineTo(N, InsV);
12223 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12224 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12225 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12226 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12227 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12228 return DCI.CombineTo(N, InsV);
12234 /// PerformShuffleCombine - Performs several different shuffle combines.
12235 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12236 TargetLowering::DAGCombinerInfo &DCI,
12237 const X86Subtarget *Subtarget) {
12238 DebugLoc dl = N->getDebugLoc();
12239 EVT VT = N->getValueType(0);
12241 // Don't create instructions with illegal types after legalize types has run.
12242 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12243 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12246 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12247 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12248 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12249 return PerformShuffleCombine256(N, DAG, DCI);
12251 // Only handle 128 wide vector from here on.
12252 if (VT.getSizeInBits() != 128)
12255 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12256 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12257 // consecutive, non-overlapping, and in the right order.
12258 SmallVector<SDValue, 16> Elts;
12259 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12260 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12262 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12265 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12266 /// generation and convert it from being a bunch of shuffles and extracts
12267 /// to a simple store and scalar loads to extract the elements.
12268 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12269 const TargetLowering &TLI) {
12270 SDValue InputVector = N->getOperand(0);
12272 // Only operate on vectors of 4 elements, where the alternative shuffling
12273 // gets to be more expensive.
12274 if (InputVector.getValueType() != MVT::v4i32)
12277 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12278 // single use which is a sign-extend or zero-extend, and all elements are
12280 SmallVector<SDNode *, 4> Uses;
12281 unsigned ExtractedElements = 0;
12282 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12283 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12284 if (UI.getUse().getResNo() != InputVector.getResNo())
12287 SDNode *Extract = *UI;
12288 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12291 if (Extract->getValueType(0) != MVT::i32)
12293 if (!Extract->hasOneUse())
12295 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12296 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12298 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12301 // Record which element was extracted.
12302 ExtractedElements |=
12303 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12305 Uses.push_back(Extract);
12308 // If not all the elements were used, this may not be worthwhile.
12309 if (ExtractedElements != 15)
12312 // Ok, we've now decided to do the transformation.
12313 DebugLoc dl = InputVector.getDebugLoc();
12315 // Store the value to a temporary stack slot.
12316 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12317 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12318 MachinePointerInfo(), false, false, 0);
12320 // Replace each use (extract) with a load of the appropriate element.
12321 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12322 UE = Uses.end(); UI != UE; ++UI) {
12323 SDNode *Extract = *UI;
12325 // cOMpute the element's address.
12326 SDValue Idx = Extract->getOperand(1);
12328 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12329 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12330 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12332 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12333 StackPtr, OffsetVal);
12335 // Load the scalar.
12336 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12337 ScalarAddr, MachinePointerInfo(),
12340 // Replace the exact with the load.
12341 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12344 // The replacement was made in place; don't return anything.
12348 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
12349 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12350 const X86Subtarget *Subtarget) {
12351 DebugLoc DL = N->getDebugLoc();
12352 SDValue Cond = N->getOperand(0);
12353 // Get the LHS/RHS of the select.
12354 SDValue LHS = N->getOperand(1);
12355 SDValue RHS = N->getOperand(2);
12357 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12358 // instructions match the semantics of the common C idiom x<y?x:y but not
12359 // x<=y?x:y, because of how they handle negative zero (which can be
12360 // ignored in unsafe-math mode).
12361 if (Subtarget->hasSSE2() &&
12362 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
12363 Cond.getOpcode() == ISD::SETCC) {
12364 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12366 unsigned Opcode = 0;
12367 // Check for x CC y ? x : y.
12368 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12369 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12373 // Converting this to a min would handle NaNs incorrectly, and swapping
12374 // the operands would cause it to handle comparisons between positive
12375 // and negative zero incorrectly.
12376 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12377 if (!UnsafeFPMath &&
12378 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12380 std::swap(LHS, RHS);
12382 Opcode = X86ISD::FMIN;
12385 // Converting this to a min would handle comparisons between positive
12386 // and negative zero incorrectly.
12387 if (!UnsafeFPMath &&
12388 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12390 Opcode = X86ISD::FMIN;
12393 // Converting this to a min would handle both negative zeros and NaNs
12394 // incorrectly, but we can swap the operands to fix both.
12395 std::swap(LHS, RHS);
12399 Opcode = X86ISD::FMIN;
12403 // Converting this to a max would handle comparisons between positive
12404 // and negative zero incorrectly.
12405 if (!UnsafeFPMath &&
12406 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12408 Opcode = X86ISD::FMAX;
12411 // Converting this to a max would handle NaNs incorrectly, and swapping
12412 // the operands would cause it to handle comparisons between positive
12413 // and negative zero incorrectly.
12414 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12415 if (!UnsafeFPMath &&
12416 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12418 std::swap(LHS, RHS);
12420 Opcode = X86ISD::FMAX;
12423 // Converting this to a max would handle both negative zeros and NaNs
12424 // incorrectly, but we can swap the operands to fix both.
12425 std::swap(LHS, RHS);
12429 Opcode = X86ISD::FMAX;
12432 // Check for x CC y ? y : x -- a min/max with reversed arms.
12433 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12434 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12438 // Converting this to a min would handle comparisons between positive
12439 // and negative zero incorrectly, and swapping the operands would
12440 // cause it to handle NaNs incorrectly.
12441 if (!UnsafeFPMath &&
12442 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12443 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12445 std::swap(LHS, RHS);
12447 Opcode = X86ISD::FMIN;
12450 // Converting this to a min would handle NaNs incorrectly.
12451 if (!UnsafeFPMath &&
12452 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12454 Opcode = X86ISD::FMIN;
12457 // Converting this to a min would handle both negative zeros and NaNs
12458 // incorrectly, but we can swap the operands to fix both.
12459 std::swap(LHS, RHS);
12463 Opcode = X86ISD::FMIN;
12467 // Converting this to a max would handle NaNs incorrectly.
12468 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12470 Opcode = X86ISD::FMAX;
12473 // Converting this to a max would handle comparisons between positive
12474 // and negative zero incorrectly, and swapping the operands would
12475 // cause it to handle NaNs incorrectly.
12476 if (!UnsafeFPMath &&
12477 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12478 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12480 std::swap(LHS, RHS);
12482 Opcode = X86ISD::FMAX;
12485 // Converting this to a max would handle both negative zeros and NaNs
12486 // incorrectly, but we can swap the operands to fix both.
12487 std::swap(LHS, RHS);
12491 Opcode = X86ISD::FMAX;
12497 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
12500 // If this is a select between two integer constants, try to do some
12502 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
12503 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
12504 // Don't do this for crazy integer types.
12505 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
12506 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
12507 // so that TrueC (the true value) is larger than FalseC.
12508 bool NeedsCondInvert = false;
12510 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
12511 // Efficiently invertible.
12512 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
12513 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
12514 isa<ConstantSDNode>(Cond.getOperand(1))))) {
12515 NeedsCondInvert = true;
12516 std::swap(TrueC, FalseC);
12519 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
12520 if (FalseC->getAPIntValue() == 0 &&
12521 TrueC->getAPIntValue().isPowerOf2()) {
12522 if (NeedsCondInvert) // Invert the condition if needed.
12523 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12524 DAG.getConstant(1, Cond.getValueType()));
12526 // Zero extend the condition if needed.
12527 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
12529 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12530 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
12531 DAG.getConstant(ShAmt, MVT::i8));
12534 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
12535 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12536 if (NeedsCondInvert) // Invert the condition if needed.
12537 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12538 DAG.getConstant(1, Cond.getValueType()));
12540 // Zero extend the condition if needed.
12541 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12542 FalseC->getValueType(0), Cond);
12543 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12544 SDValue(FalseC, 0));
12547 // Optimize cases that will turn into an LEA instruction. This requires
12548 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12549 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12550 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12551 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12553 bool isFastMultiplier = false;
12555 switch ((unsigned char)Diff) {
12557 case 1: // result = add base, cond
12558 case 2: // result = lea base( , cond*2)
12559 case 3: // result = lea base(cond, cond*2)
12560 case 4: // result = lea base( , cond*4)
12561 case 5: // result = lea base(cond, cond*4)
12562 case 8: // result = lea base( , cond*8)
12563 case 9: // result = lea base(cond, cond*8)
12564 isFastMultiplier = true;
12569 if (isFastMultiplier) {
12570 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12571 if (NeedsCondInvert) // Invert the condition if needed.
12572 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12573 DAG.getConstant(1, Cond.getValueType()));
12575 // Zero extend the condition if needed.
12576 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12578 // Scale the condition by the difference.
12580 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12581 DAG.getConstant(Diff, Cond.getValueType()));
12583 // Add the base if non-zero.
12584 if (FalseC->getAPIntValue() != 0)
12585 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12586 SDValue(FalseC, 0));
12596 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
12597 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
12598 TargetLowering::DAGCombinerInfo &DCI) {
12599 DebugLoc DL = N->getDebugLoc();
12601 // If the flag operand isn't dead, don't touch this CMOV.
12602 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
12605 SDValue FalseOp = N->getOperand(0);
12606 SDValue TrueOp = N->getOperand(1);
12607 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
12608 SDValue Cond = N->getOperand(3);
12609 if (CC == X86::COND_E || CC == X86::COND_NE) {
12610 switch (Cond.getOpcode()) {
12614 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
12615 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
12616 return (CC == X86::COND_E) ? FalseOp : TrueOp;
12620 // If this is a select between two integer constants, try to do some
12621 // optimizations. Note that the operands are ordered the opposite of SELECT
12623 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
12624 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
12625 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
12626 // larger than FalseC (the false value).
12627 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
12628 CC = X86::GetOppositeBranchCondition(CC);
12629 std::swap(TrueC, FalseC);
12632 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
12633 // This is efficient for any integer data type (including i8/i16) and
12635 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
12636 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12637 DAG.getConstant(CC, MVT::i8), Cond);
12639 // Zero extend the condition if needed.
12640 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
12642 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12643 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
12644 DAG.getConstant(ShAmt, MVT::i8));
12645 if (N->getNumValues() == 2) // Dead flag value?
12646 return DCI.CombineTo(N, Cond, SDValue());
12650 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
12651 // for any integer data type, including i8/i16.
12652 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12653 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12654 DAG.getConstant(CC, MVT::i8), Cond);
12656 // Zero extend the condition if needed.
12657 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12658 FalseC->getValueType(0), Cond);
12659 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12660 SDValue(FalseC, 0));
12662 if (N->getNumValues() == 2) // Dead flag value?
12663 return DCI.CombineTo(N, Cond, SDValue());
12667 // Optimize cases that will turn into an LEA instruction. This requires
12668 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12669 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12670 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12671 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12673 bool isFastMultiplier = false;
12675 switch ((unsigned char)Diff) {
12677 case 1: // result = add base, cond
12678 case 2: // result = lea base( , cond*2)
12679 case 3: // result = lea base(cond, cond*2)
12680 case 4: // result = lea base( , cond*4)
12681 case 5: // result = lea base(cond, cond*4)
12682 case 8: // result = lea base( , cond*8)
12683 case 9: // result = lea base(cond, cond*8)
12684 isFastMultiplier = true;
12689 if (isFastMultiplier) {
12690 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12691 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12692 DAG.getConstant(CC, MVT::i8), Cond);
12693 // Zero extend the condition if needed.
12694 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12696 // Scale the condition by the difference.
12698 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12699 DAG.getConstant(Diff, Cond.getValueType()));
12701 // Add the base if non-zero.
12702 if (FalseC->getAPIntValue() != 0)
12703 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12704 SDValue(FalseC, 0));
12705 if (N->getNumValues() == 2) // Dead flag value?
12706 return DCI.CombineTo(N, Cond, SDValue());
12716 /// PerformMulCombine - Optimize a single multiply with constant into two
12717 /// in order to implement it with two cheaper instructions, e.g.
12718 /// LEA + SHL, LEA + LEA.
12719 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
12720 TargetLowering::DAGCombinerInfo &DCI) {
12721 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
12724 EVT VT = N->getValueType(0);
12725 if (VT != MVT::i64)
12728 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
12731 uint64_t MulAmt = C->getZExtValue();
12732 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
12735 uint64_t MulAmt1 = 0;
12736 uint64_t MulAmt2 = 0;
12737 if ((MulAmt % 9) == 0) {
12739 MulAmt2 = MulAmt / 9;
12740 } else if ((MulAmt % 5) == 0) {
12742 MulAmt2 = MulAmt / 5;
12743 } else if ((MulAmt % 3) == 0) {
12745 MulAmt2 = MulAmt / 3;
12748 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
12749 DebugLoc DL = N->getDebugLoc();
12751 if (isPowerOf2_64(MulAmt2) &&
12752 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
12753 // If second multiplifer is pow2, issue it first. We want the multiply by
12754 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
12756 std::swap(MulAmt1, MulAmt2);
12759 if (isPowerOf2_64(MulAmt1))
12760 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
12761 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
12763 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
12764 DAG.getConstant(MulAmt1, VT));
12766 if (isPowerOf2_64(MulAmt2))
12767 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
12768 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
12770 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
12771 DAG.getConstant(MulAmt2, VT));
12773 // Do not add new nodes to DAG combiner worklist.
12774 DCI.CombineTo(N, NewMul, false);
12779 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
12780 SDValue N0 = N->getOperand(0);
12781 SDValue N1 = N->getOperand(1);
12782 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
12783 EVT VT = N0.getValueType();
12785 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
12786 // since the result of setcc_c is all zero's or all ones.
12787 if (N1C && N0.getOpcode() == ISD::AND &&
12788 N0.getOperand(1).getOpcode() == ISD::Constant) {
12789 SDValue N00 = N0.getOperand(0);
12790 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
12791 ((N00.getOpcode() == ISD::ANY_EXTEND ||
12792 N00.getOpcode() == ISD::ZERO_EXTEND) &&
12793 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
12794 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
12795 APInt ShAmt = N1C->getAPIntValue();
12796 Mask = Mask.shl(ShAmt);
12798 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
12799 N00, DAG.getConstant(Mask, VT));
12806 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
12808 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
12809 const X86Subtarget *Subtarget) {
12810 EVT VT = N->getValueType(0);
12811 if (!VT.isVector() && VT.isInteger() &&
12812 N->getOpcode() == ISD::SHL)
12813 return PerformSHLCombine(N, DAG);
12815 // On X86 with SSE2 support, we can transform this to a vector shift if
12816 // all elements are shifted by the same amount. We can't do this in legalize
12817 // because the a constant vector is typically transformed to a constant pool
12818 // so we have no knowledge of the shift amount.
12819 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
12822 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
12825 SDValue ShAmtOp = N->getOperand(1);
12826 EVT EltVT = VT.getVectorElementType();
12827 DebugLoc DL = N->getDebugLoc();
12828 SDValue BaseShAmt = SDValue();
12829 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
12830 unsigned NumElts = VT.getVectorNumElements();
12832 for (; i != NumElts; ++i) {
12833 SDValue Arg = ShAmtOp.getOperand(i);
12834 if (Arg.getOpcode() == ISD::UNDEF) continue;
12838 for (; i != NumElts; ++i) {
12839 SDValue Arg = ShAmtOp.getOperand(i);
12840 if (Arg.getOpcode() == ISD::UNDEF) continue;
12841 if (Arg != BaseShAmt) {
12845 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
12846 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
12847 SDValue InVec = ShAmtOp.getOperand(0);
12848 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12849 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12851 for (; i != NumElts; ++i) {
12852 SDValue Arg = InVec.getOperand(i);
12853 if (Arg.getOpcode() == ISD::UNDEF) continue;
12857 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12858 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12859 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
12860 if (C->getZExtValue() == SplatIdx)
12861 BaseShAmt = InVec.getOperand(1);
12864 if (BaseShAmt.getNode() == 0)
12865 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
12866 DAG.getIntPtrConstant(0));
12870 // The shift amount is an i32.
12871 if (EltVT.bitsGT(MVT::i32))
12872 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
12873 else if (EltVT.bitsLT(MVT::i32))
12874 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
12876 // The shift amount is identical so we can do a vector shift.
12877 SDValue ValOp = N->getOperand(0);
12878 switch (N->getOpcode()) {
12880 llvm_unreachable("Unknown shift opcode!");
12883 if (VT == MVT::v2i64)
12884 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12885 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
12887 if (VT == MVT::v4i32)
12888 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12889 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
12891 if (VT == MVT::v8i16)
12892 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12893 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
12897 if (VT == MVT::v4i32)
12898 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12899 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
12901 if (VT == MVT::v8i16)
12902 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12903 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
12907 if (VT == MVT::v2i64)
12908 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12909 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
12911 if (VT == MVT::v4i32)
12912 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12913 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
12915 if (VT == MVT::v8i16)
12916 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12917 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
12925 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
12926 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
12927 // and friends. Likewise for OR -> CMPNEQSS.
12928 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
12929 TargetLowering::DAGCombinerInfo &DCI,
12930 const X86Subtarget *Subtarget) {
12933 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
12934 // we're requiring SSE2 for both.
12935 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
12936 SDValue N0 = N->getOperand(0);
12937 SDValue N1 = N->getOperand(1);
12938 SDValue CMP0 = N0->getOperand(1);
12939 SDValue CMP1 = N1->getOperand(1);
12940 DebugLoc DL = N->getDebugLoc();
12942 // The SETCCs should both refer to the same CMP.
12943 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
12946 SDValue CMP00 = CMP0->getOperand(0);
12947 SDValue CMP01 = CMP0->getOperand(1);
12948 EVT VT = CMP00.getValueType();
12950 if (VT == MVT::f32 || VT == MVT::f64) {
12951 bool ExpectingFlags = false;
12952 // Check for any users that want flags:
12953 for (SDNode::use_iterator UI = N->use_begin(),
12955 !ExpectingFlags && UI != UE; ++UI)
12956 switch (UI->getOpcode()) {
12961 ExpectingFlags = true;
12963 case ISD::CopyToReg:
12964 case ISD::SIGN_EXTEND:
12965 case ISD::ZERO_EXTEND:
12966 case ISD::ANY_EXTEND:
12970 if (!ExpectingFlags) {
12971 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
12972 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
12974 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
12975 X86::CondCode tmp = cc0;
12980 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
12981 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
12982 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
12983 X86ISD::NodeType NTOperator = is64BitFP ?
12984 X86ISD::FSETCCsd : X86ISD::FSETCCss;
12985 // FIXME: need symbolic constants for these magic numbers.
12986 // See X86ATTInstPrinter.cpp:printSSECC().
12987 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
12988 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
12989 DAG.getConstant(x86cc, MVT::i8));
12990 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
12992 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
12993 DAG.getConstant(1, MVT::i32));
12994 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
12995 return OneBitOfTruth;
13003 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13004 /// so it can be folded inside ANDNP.
13005 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13006 EVT VT = N->getValueType(0);
13008 // Match direct AllOnes for 128 and 256-bit vectors
13009 if (ISD::isBuildVectorAllOnes(N))
13012 // Look through a bit convert.
13013 if (N->getOpcode() == ISD::BITCAST)
13014 N = N->getOperand(0).getNode();
13016 // Sometimes the operand may come from a insert_subvector building a 256-bit
13018 if (VT.getSizeInBits() == 256 &&
13019 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13020 SDValue V1 = N->getOperand(0);
13021 SDValue V2 = N->getOperand(1);
13023 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13024 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13025 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13026 ISD::isBuildVectorAllOnes(V2.getNode()))
13033 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13034 TargetLowering::DAGCombinerInfo &DCI,
13035 const X86Subtarget *Subtarget) {
13036 if (DCI.isBeforeLegalizeOps())
13039 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13043 // Want to form ANDNP nodes:
13044 // 1) In the hopes of then easily combining them with OR and AND nodes
13045 // to form PBLEND/PSIGN.
13046 // 2) To match ANDN packed intrinsics
13047 EVT VT = N->getValueType(0);
13048 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13051 SDValue N0 = N->getOperand(0);
13052 SDValue N1 = N->getOperand(1);
13053 DebugLoc DL = N->getDebugLoc();
13055 // Check LHS for vnot
13056 if (N0.getOpcode() == ISD::XOR &&
13057 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13058 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13059 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13061 // Check RHS for vnot
13062 if (N1.getOpcode() == ISD::XOR &&
13063 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13064 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13065 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13070 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13071 TargetLowering::DAGCombinerInfo &DCI,
13072 const X86Subtarget *Subtarget) {
13073 if (DCI.isBeforeLegalizeOps())
13076 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13080 EVT VT = N->getValueType(0);
13081 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
13084 SDValue N0 = N->getOperand(0);
13085 SDValue N1 = N->getOperand(1);
13087 // look for psign/blend
13088 if (Subtarget->hasSSSE3()) {
13089 if (VT == MVT::v2i64) {
13090 // Canonicalize pandn to RHS
13091 if (N0.getOpcode() == X86ISD::ANDNP)
13093 // or (and (m, x), (pandn m, y))
13094 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13095 SDValue Mask = N1.getOperand(0);
13096 SDValue X = N1.getOperand(1);
13098 if (N0.getOperand(0) == Mask)
13099 Y = N0.getOperand(1);
13100 if (N0.getOperand(1) == Mask)
13101 Y = N0.getOperand(0);
13103 // Check to see if the mask appeared in both the AND and ANDNP and
13107 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13108 if (Mask.getOpcode() != ISD::BITCAST ||
13109 X.getOpcode() != ISD::BITCAST ||
13110 Y.getOpcode() != ISD::BITCAST)
13113 // Look through mask bitcast.
13114 Mask = Mask.getOperand(0);
13115 EVT MaskVT = Mask.getValueType();
13117 // Validate that the Mask operand is a vector sra node. The sra node
13118 // will be an intrinsic.
13119 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13122 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13123 // there is no psrai.b
13124 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13125 case Intrinsic::x86_sse2_psrai_w:
13126 case Intrinsic::x86_sse2_psrai_d:
13128 default: return SDValue();
13131 // Check that the SRA is all signbits.
13132 SDValue SraC = Mask.getOperand(2);
13133 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13134 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13135 if ((SraAmt + 1) != EltBits)
13138 DebugLoc DL = N->getDebugLoc();
13140 // Now we know we at least have a plendvb with the mask val. See if
13141 // we can form a psignb/w/d.
13142 // psign = x.type == y.type == mask.type && y = sub(0, x);
13143 X = X.getOperand(0);
13144 Y = Y.getOperand(0);
13145 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13146 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13147 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
13150 case 8: Opc = X86ISD::PSIGNB; break;
13151 case 16: Opc = X86ISD::PSIGNW; break;
13152 case 32: Opc = X86ISD::PSIGND; break;
13156 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
13157 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
13160 // PBLENDVB only available on SSE 4.1
13161 if (!Subtarget->hasSSE41())
13164 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
13165 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
13166 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
13167 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
13168 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
13173 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13174 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13176 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13178 if (!N0.hasOneUse() || !N1.hasOneUse())
13181 SDValue ShAmt0 = N0.getOperand(1);
13182 if (ShAmt0.getValueType() != MVT::i8)
13184 SDValue ShAmt1 = N1.getOperand(1);
13185 if (ShAmt1.getValueType() != MVT::i8)
13187 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13188 ShAmt0 = ShAmt0.getOperand(0);
13189 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13190 ShAmt1 = ShAmt1.getOperand(0);
13192 DebugLoc DL = N->getDebugLoc();
13193 unsigned Opc = X86ISD::SHLD;
13194 SDValue Op0 = N0.getOperand(0);
13195 SDValue Op1 = N1.getOperand(0);
13196 if (ShAmt0.getOpcode() == ISD::SUB) {
13197 Opc = X86ISD::SHRD;
13198 std::swap(Op0, Op1);
13199 std::swap(ShAmt0, ShAmt1);
13202 unsigned Bits = VT.getSizeInBits();
13203 if (ShAmt1.getOpcode() == ISD::SUB) {
13204 SDValue Sum = ShAmt1.getOperand(0);
13205 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13206 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13207 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13208 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13209 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13210 return DAG.getNode(Opc, DL, VT,
13212 DAG.getNode(ISD::TRUNCATE, DL,
13215 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13216 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13218 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13219 return DAG.getNode(Opc, DL, VT,
13220 N0.getOperand(0), N1.getOperand(0),
13221 DAG.getNode(ISD::TRUNCATE, DL,
13228 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13229 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13230 const X86Subtarget *Subtarget) {
13231 StoreSDNode *St = cast<StoreSDNode>(N);
13232 EVT VT = St->getValue().getValueType();
13233 EVT StVT = St->getMemoryVT();
13234 DebugLoc dl = St->getDebugLoc();
13235 SDValue StoredVal = St->getOperand(1);
13236 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13238 // If we are saving a concatination of two XMM registers, perform two stores.
13239 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13240 // 128-bit ones. If in the future the cost becomes only one memory access the
13241 // first version would be better.
13242 if (VT.getSizeInBits() == 256 &&
13243 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
13244 StoredVal.getNumOperands() == 2) {
13246 SDValue Value0 = StoredVal.getOperand(0);
13247 SDValue Value1 = StoredVal.getOperand(1);
13249 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
13250 SDValue Ptr0 = St->getBasePtr();
13251 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
13253 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
13254 St->getPointerInfo(), St->isVolatile(),
13255 St->isNonTemporal(), St->getAlignment());
13256 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
13257 St->getPointerInfo(), St->isVolatile(),
13258 St->isNonTemporal(), St->getAlignment());
13259 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
13262 // Optimize trunc store (of multiple scalars) to shuffle and store.
13263 // First, pack all of the elements in one place. Next, store to memory
13264 // in fewer chunks.
13265 if (St->isTruncatingStore() && VT.isVector()) {
13266 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13267 unsigned NumElems = VT.getVectorNumElements();
13268 assert(StVT != VT && "Cannot truncate to the same type");
13269 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
13270 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
13272 // From, To sizes and ElemCount must be pow of two
13273 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
13274 // We are going to use the original vector elt for storing.
13275 // accumulated smaller vector elements must be a multiple of bigger size.
13276 if (0 != (NumElems * ToSz) % FromSz) return SDValue();
13277 unsigned SizeRatio = FromSz / ToSz;
13279 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
13281 // Create a type on which we perform the shuffle
13282 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
13283 StVT.getScalarType(), NumElems*SizeRatio);
13285 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
13287 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
13288 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13289 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
13291 // Can't shuffle using an illegal type
13292 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13294 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
13295 DAG.getUNDEF(WideVec.getValueType()),
13296 ShuffleVec.data());
13297 // At this point all of the data is stored at the bottom of the
13298 // register. We now need to save it to mem.
13300 // Find the largest store unit
13301 MVT StoreType = MVT::i8;
13302 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13303 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13304 MVT Tp = (MVT::SimpleValueType)tp;
13305 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
13309 // Bitcast the original vector into a vector of store-size units
13310 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
13311 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
13312 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
13313 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
13314 SmallVector<SDValue, 8> Chains;
13315 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
13316 TLI.getPointerTy());
13317 SDValue Ptr = St->getBasePtr();
13319 // Perform one or more big stores into memory.
13320 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
13321 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
13322 StoreType, ShuffWide,
13323 DAG.getIntPtrConstant(i));
13324 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
13325 St->getPointerInfo(), St->isVolatile(),
13326 St->isNonTemporal(), St->getAlignment());
13327 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13328 Chains.push_back(Ch);
13331 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
13336 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
13337 // the FP state in cases where an emms may be missing.
13338 // A preferable solution to the general problem is to figure out the right
13339 // places to insert EMMS. This qualifies as a quick hack.
13341 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
13342 if (VT.getSizeInBits() != 64)
13345 const Function *F = DAG.getMachineFunction().getFunction();
13346 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
13347 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
13348 && Subtarget->hasSSE2();
13349 if ((VT.isVector() ||
13350 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
13351 isa<LoadSDNode>(St->getValue()) &&
13352 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
13353 St->getChain().hasOneUse() && !St->isVolatile()) {
13354 SDNode* LdVal = St->getValue().getNode();
13355 LoadSDNode *Ld = 0;
13356 int TokenFactorIndex = -1;
13357 SmallVector<SDValue, 8> Ops;
13358 SDNode* ChainVal = St->getChain().getNode();
13359 // Must be a store of a load. We currently handle two cases: the load
13360 // is a direct child, and it's under an intervening TokenFactor. It is
13361 // possible to dig deeper under nested TokenFactors.
13362 if (ChainVal == LdVal)
13363 Ld = cast<LoadSDNode>(St->getChain());
13364 else if (St->getValue().hasOneUse() &&
13365 ChainVal->getOpcode() == ISD::TokenFactor) {
13366 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
13367 if (ChainVal->getOperand(i).getNode() == LdVal) {
13368 TokenFactorIndex = i;
13369 Ld = cast<LoadSDNode>(St->getValue());
13371 Ops.push_back(ChainVal->getOperand(i));
13375 if (!Ld || !ISD::isNormalLoad(Ld))
13378 // If this is not the MMX case, i.e. we are just turning i64 load/store
13379 // into f64 load/store, avoid the transformation if there are multiple
13380 // uses of the loaded value.
13381 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
13384 DebugLoc LdDL = Ld->getDebugLoc();
13385 DebugLoc StDL = N->getDebugLoc();
13386 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
13387 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
13389 if (Subtarget->is64Bit() || F64IsLegal) {
13390 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
13391 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
13392 Ld->getPointerInfo(), Ld->isVolatile(),
13393 Ld->isNonTemporal(), Ld->getAlignment());
13394 SDValue NewChain = NewLd.getValue(1);
13395 if (TokenFactorIndex != -1) {
13396 Ops.push_back(NewChain);
13397 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13400 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
13401 St->getPointerInfo(),
13402 St->isVolatile(), St->isNonTemporal(),
13403 St->getAlignment());
13406 // Otherwise, lower to two pairs of 32-bit loads / stores.
13407 SDValue LoAddr = Ld->getBasePtr();
13408 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
13409 DAG.getConstant(4, MVT::i32));
13411 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
13412 Ld->getPointerInfo(),
13413 Ld->isVolatile(), Ld->isNonTemporal(),
13414 Ld->getAlignment());
13415 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
13416 Ld->getPointerInfo().getWithOffset(4),
13417 Ld->isVolatile(), Ld->isNonTemporal(),
13418 MinAlign(Ld->getAlignment(), 4));
13420 SDValue NewChain = LoLd.getValue(1);
13421 if (TokenFactorIndex != -1) {
13422 Ops.push_back(LoLd);
13423 Ops.push_back(HiLd);
13424 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13428 LoAddr = St->getBasePtr();
13429 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
13430 DAG.getConstant(4, MVT::i32));
13432 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
13433 St->getPointerInfo(),
13434 St->isVolatile(), St->isNonTemporal(),
13435 St->getAlignment());
13436 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
13437 St->getPointerInfo().getWithOffset(4),
13439 St->isNonTemporal(),
13440 MinAlign(St->getAlignment(), 4));
13441 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
13446 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
13447 /// X86ISD::FXOR nodes.
13448 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
13449 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
13450 // F[X]OR(0.0, x) -> x
13451 // F[X]OR(x, 0.0) -> x
13452 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13453 if (C->getValueAPF().isPosZero())
13454 return N->getOperand(1);
13455 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13456 if (C->getValueAPF().isPosZero())
13457 return N->getOperand(0);
13461 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
13462 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
13463 // FAND(0.0, x) -> 0.0
13464 // FAND(x, 0.0) -> 0.0
13465 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13466 if (C->getValueAPF().isPosZero())
13467 return N->getOperand(0);
13468 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13469 if (C->getValueAPF().isPosZero())
13470 return N->getOperand(1);
13474 static SDValue PerformBTCombine(SDNode *N,
13476 TargetLowering::DAGCombinerInfo &DCI) {
13477 // BT ignores high bits in the bit index operand.
13478 SDValue Op1 = N->getOperand(1);
13479 if (Op1.hasOneUse()) {
13480 unsigned BitWidth = Op1.getValueSizeInBits();
13481 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
13482 APInt KnownZero, KnownOne;
13483 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
13484 !DCI.isBeforeLegalizeOps());
13485 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13486 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
13487 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
13488 DCI.CommitTargetLoweringOpt(TLO);
13493 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
13494 SDValue Op = N->getOperand(0);
13495 if (Op.getOpcode() == ISD::BITCAST)
13496 Op = Op.getOperand(0);
13497 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
13498 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
13499 VT.getVectorElementType().getSizeInBits() ==
13500 OpVT.getVectorElementType().getSizeInBits()) {
13501 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
13506 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
13507 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
13508 // (and (i32 x86isd::setcc_carry), 1)
13509 // This eliminates the zext. This transformation is necessary because
13510 // ISD::SETCC is always legalized to i8.
13511 DebugLoc dl = N->getDebugLoc();
13512 SDValue N0 = N->getOperand(0);
13513 EVT VT = N->getValueType(0);
13514 if (N0.getOpcode() == ISD::AND &&
13516 N0.getOperand(0).hasOneUse()) {
13517 SDValue N00 = N0.getOperand(0);
13518 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
13520 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
13521 if (!C || C->getZExtValue() != 1)
13523 return DAG.getNode(ISD::AND, dl, VT,
13524 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
13525 N00.getOperand(0), N00.getOperand(1)),
13526 DAG.getConstant(1, VT));
13532 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
13533 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
13534 unsigned X86CC = N->getConstantOperandVal(0);
13535 SDValue EFLAG = N->getOperand(1);
13536 DebugLoc DL = N->getDebugLoc();
13538 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
13539 // a zext and produces an all-ones bit which is more useful than 0/1 in some
13541 if (X86CC == X86::COND_B)
13542 return DAG.getNode(ISD::AND, DL, MVT::i8,
13543 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
13544 DAG.getConstant(X86CC, MVT::i8), EFLAG),
13545 DAG.getConstant(1, MVT::i8));
13550 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
13551 const X86TargetLowering *XTLI) {
13552 SDValue Op0 = N->getOperand(0);
13553 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
13554 // a 32-bit target where SSE doesn't support i64->FP operations.
13555 if (Op0.getOpcode() == ISD::LOAD) {
13556 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
13557 EVT VT = Ld->getValueType(0);
13558 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
13559 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
13560 !XTLI->getSubtarget()->is64Bit() &&
13561 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13562 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
13563 Ld->getChain(), Op0, DAG);
13564 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
13571 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
13572 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
13573 X86TargetLowering::DAGCombinerInfo &DCI) {
13574 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
13575 // the result is either zero or one (depending on the input carry bit).
13576 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
13577 if (X86::isZeroNode(N->getOperand(0)) &&
13578 X86::isZeroNode(N->getOperand(1)) &&
13579 // We don't have a good way to replace an EFLAGS use, so only do this when
13581 SDValue(N, 1).use_empty()) {
13582 DebugLoc DL = N->getDebugLoc();
13583 EVT VT = N->getValueType(0);
13584 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
13585 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
13586 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
13587 DAG.getConstant(X86::COND_B,MVT::i8),
13589 DAG.getConstant(1, VT));
13590 return DCI.CombineTo(N, Res1, CarryOut);
13596 // fold (add Y, (sete X, 0)) -> adc 0, Y
13597 // (add Y, (setne X, 0)) -> sbb -1, Y
13598 // (sub (sete X, 0), Y) -> sbb 0, Y
13599 // (sub (setne X, 0), Y) -> adc -1, Y
13600 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
13601 DebugLoc DL = N->getDebugLoc();
13603 // Look through ZExts.
13604 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
13605 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
13608 SDValue SetCC = Ext.getOperand(0);
13609 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
13612 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
13613 if (CC != X86::COND_E && CC != X86::COND_NE)
13616 SDValue Cmp = SetCC.getOperand(1);
13617 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
13618 !X86::isZeroNode(Cmp.getOperand(1)) ||
13619 !Cmp.getOperand(0).getValueType().isInteger())
13622 SDValue CmpOp0 = Cmp.getOperand(0);
13623 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
13624 DAG.getConstant(1, CmpOp0.getValueType()));
13626 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
13627 if (CC == X86::COND_NE)
13628 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
13629 DL, OtherVal.getValueType(), OtherVal,
13630 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
13631 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
13632 DL, OtherVal.getValueType(), OtherVal,
13633 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
13636 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
13637 SDValue Op0 = N->getOperand(0);
13638 SDValue Op1 = N->getOperand(1);
13640 // X86 can't encode an immediate LHS of a sub. See if we can push the
13641 // negation into a preceding instruction.
13642 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
13643 // If the RHS of the sub is a XOR with one use and a constant, invert the
13644 // immediate. Then add one to the LHS of the sub so we can turn
13645 // X-Y -> X+~Y+1, saving one register.
13646 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
13647 isa<ConstantSDNode>(Op1.getOperand(1))) {
13648 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
13649 EVT VT = Op0.getValueType();
13650 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
13652 DAG.getConstant(~XorC, VT));
13653 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
13654 DAG.getConstant(C->getAPIntValue()+1, VT));
13658 return OptimizeConditionalInDecrement(N, DAG);
13661 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
13662 DAGCombinerInfo &DCI) const {
13663 SelectionDAG &DAG = DCI.DAG;
13664 switch (N->getOpcode()) {
13666 case ISD::EXTRACT_VECTOR_ELT:
13667 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
13668 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
13669 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
13670 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
13671 case ISD::SUB: return PerformSubCombine(N, DAG);
13672 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
13673 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
13676 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
13677 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
13678 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
13679 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
13680 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
13682 case X86ISD::FOR: return PerformFORCombine(N, DAG);
13683 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
13684 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
13685 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
13686 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
13687 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
13688 case X86ISD::SHUFPS: // Handle all target specific shuffles
13689 case X86ISD::SHUFPD:
13690 case X86ISD::PALIGN:
13691 case X86ISD::PUNPCKHBW:
13692 case X86ISD::PUNPCKHWD:
13693 case X86ISD::PUNPCKHDQ:
13694 case X86ISD::PUNPCKHQDQ:
13695 case X86ISD::UNPCKHPS:
13696 case X86ISD::UNPCKHPD:
13697 case X86ISD::VUNPCKHPSY:
13698 case X86ISD::VUNPCKHPDY:
13699 case X86ISD::PUNPCKLBW:
13700 case X86ISD::PUNPCKLWD:
13701 case X86ISD::PUNPCKLDQ:
13702 case X86ISD::PUNPCKLQDQ:
13703 case X86ISD::UNPCKLPS:
13704 case X86ISD::UNPCKLPD:
13705 case X86ISD::VUNPCKLPSY:
13706 case X86ISD::VUNPCKLPDY:
13707 case X86ISD::MOVHLPS:
13708 case X86ISD::MOVLHPS:
13709 case X86ISD::PSHUFD:
13710 case X86ISD::PSHUFHW:
13711 case X86ISD::PSHUFLW:
13712 case X86ISD::MOVSS:
13713 case X86ISD::MOVSD:
13714 case X86ISD::VPERMILPS:
13715 case X86ISD::VPERMILPSY:
13716 case X86ISD::VPERMILPD:
13717 case X86ISD::VPERMILPDY:
13718 case X86ISD::VPERM2F128:
13719 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
13725 /// isTypeDesirableForOp - Return true if the target has native support for
13726 /// the specified value type and it is 'desirable' to use the type for the
13727 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
13728 /// instruction encodings are longer and some i16 instructions are slow.
13729 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
13730 if (!isTypeLegal(VT))
13732 if (VT != MVT::i16)
13739 case ISD::SIGN_EXTEND:
13740 case ISD::ZERO_EXTEND:
13741 case ISD::ANY_EXTEND:
13754 /// IsDesirableToPromoteOp - This method query the target whether it is
13755 /// beneficial for dag combiner to promote the specified node. If true, it
13756 /// should return the desired promotion type by reference.
13757 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
13758 EVT VT = Op.getValueType();
13759 if (VT != MVT::i16)
13762 bool Promote = false;
13763 bool Commute = false;
13764 switch (Op.getOpcode()) {
13767 LoadSDNode *LD = cast<LoadSDNode>(Op);
13768 // If the non-extending load has a single use and it's not live out, then it
13769 // might be folded.
13770 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
13771 Op.hasOneUse()*/) {
13772 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13773 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
13774 // The only case where we'd want to promote LOAD (rather then it being
13775 // promoted as an operand is when it's only use is liveout.
13776 if (UI->getOpcode() != ISD::CopyToReg)
13783 case ISD::SIGN_EXTEND:
13784 case ISD::ZERO_EXTEND:
13785 case ISD::ANY_EXTEND:
13790 SDValue N0 = Op.getOperand(0);
13791 // Look out for (store (shl (load), x)).
13792 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
13805 SDValue N0 = Op.getOperand(0);
13806 SDValue N1 = Op.getOperand(1);
13807 if (!Commute && MayFoldLoad(N1))
13809 // Avoid disabling potential load folding opportunities.
13810 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
13812 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
13822 //===----------------------------------------------------------------------===//
13823 // X86 Inline Assembly Support
13824 //===----------------------------------------------------------------------===//
13826 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
13827 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
13829 std::string AsmStr = IA->getAsmString();
13831 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
13832 SmallVector<StringRef, 4> AsmPieces;
13833 SplitString(AsmStr, AsmPieces, ";\n");
13835 switch (AsmPieces.size()) {
13836 default: return false;
13838 AsmStr = AsmPieces[0];
13840 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
13842 // FIXME: this should verify that we are targeting a 486 or better. If not,
13843 // we will turn this bswap into something that will be lowered to logical ops
13844 // instead of emitting the bswap asm. For now, we don't support 486 or lower
13845 // so don't worry about this.
13847 if (AsmPieces.size() == 2 &&
13848 (AsmPieces[0] == "bswap" ||
13849 AsmPieces[0] == "bswapq" ||
13850 AsmPieces[0] == "bswapl") &&
13851 (AsmPieces[1] == "$0" ||
13852 AsmPieces[1] == "${0:q}")) {
13853 // No need to check constraints, nothing other than the equivalent of
13854 // "=r,0" would be valid here.
13855 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13856 if (!Ty || Ty->getBitWidth() % 16 != 0)
13858 return IntrinsicLowering::LowerToByteSwap(CI);
13860 // rorw $$8, ${0:w} --> llvm.bswap.i16
13861 if (CI->getType()->isIntegerTy(16) &&
13862 AsmPieces.size() == 3 &&
13863 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
13864 AsmPieces[1] == "$$8," &&
13865 AsmPieces[2] == "${0:w}" &&
13866 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13868 const std::string &ConstraintsStr = IA->getConstraintString();
13869 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13870 std::sort(AsmPieces.begin(), AsmPieces.end());
13871 if (AsmPieces.size() == 4 &&
13872 AsmPieces[0] == "~{cc}" &&
13873 AsmPieces[1] == "~{dirflag}" &&
13874 AsmPieces[2] == "~{flags}" &&
13875 AsmPieces[3] == "~{fpsr}") {
13876 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13877 if (!Ty || Ty->getBitWidth() % 16 != 0)
13879 return IntrinsicLowering::LowerToByteSwap(CI);
13884 if (CI->getType()->isIntegerTy(32) &&
13885 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13886 SmallVector<StringRef, 4> Words;
13887 SplitString(AsmPieces[0], Words, " \t,");
13888 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13889 Words[2] == "${0:w}") {
13891 SplitString(AsmPieces[1], Words, " \t,");
13892 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
13893 Words[2] == "$0") {
13895 SplitString(AsmPieces[2], Words, " \t,");
13896 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13897 Words[2] == "${0:w}") {
13899 const std::string &ConstraintsStr = IA->getConstraintString();
13900 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13901 std::sort(AsmPieces.begin(), AsmPieces.end());
13902 if (AsmPieces.size() == 4 &&
13903 AsmPieces[0] == "~{cc}" &&
13904 AsmPieces[1] == "~{dirflag}" &&
13905 AsmPieces[2] == "~{flags}" &&
13906 AsmPieces[3] == "~{fpsr}") {
13907 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13908 if (!Ty || Ty->getBitWidth() % 16 != 0)
13910 return IntrinsicLowering::LowerToByteSwap(CI);
13917 if (CI->getType()->isIntegerTy(64)) {
13918 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
13919 if (Constraints.size() >= 2 &&
13920 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
13921 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
13922 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
13923 SmallVector<StringRef, 4> Words;
13924 SplitString(AsmPieces[0], Words, " \t");
13925 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
13927 SplitString(AsmPieces[1], Words, " \t");
13928 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
13930 SplitString(AsmPieces[2], Words, " \t,");
13931 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
13932 Words[2] == "%edx") {
13933 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13934 if (!Ty || Ty->getBitWidth() % 16 != 0)
13936 return IntrinsicLowering::LowerToByteSwap(CI);
13949 /// getConstraintType - Given a constraint letter, return the type of
13950 /// constraint it is for this target.
13951 X86TargetLowering::ConstraintType
13952 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
13953 if (Constraint.size() == 1) {
13954 switch (Constraint[0]) {
13965 return C_RegisterClass;
13989 return TargetLowering::getConstraintType(Constraint);
13992 /// Examine constraint type and operand type and determine a weight value.
13993 /// This object must already have been set up with the operand type
13994 /// and the current alternative constraint selected.
13995 TargetLowering::ConstraintWeight
13996 X86TargetLowering::getSingleConstraintMatchWeight(
13997 AsmOperandInfo &info, const char *constraint) const {
13998 ConstraintWeight weight = CW_Invalid;
13999 Value *CallOperandVal = info.CallOperandVal;
14000 // If we don't have a value, we can't do a match,
14001 // but allow it at the lowest weight.
14002 if (CallOperandVal == NULL)
14004 Type *type = CallOperandVal->getType();
14005 // Look at the constraint type.
14006 switch (*constraint) {
14008 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14019 if (CallOperandVal->getType()->isIntegerTy())
14020 weight = CW_SpecificReg;
14025 if (type->isFloatingPointTy())
14026 weight = CW_SpecificReg;
14029 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14030 weight = CW_SpecificReg;
14034 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
14035 weight = CW_Register;
14038 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14039 if (C->getZExtValue() <= 31)
14040 weight = CW_Constant;
14044 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14045 if (C->getZExtValue() <= 63)
14046 weight = CW_Constant;
14050 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14051 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14052 weight = CW_Constant;
14056 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14057 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14058 weight = CW_Constant;
14062 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14063 if (C->getZExtValue() <= 3)
14064 weight = CW_Constant;
14068 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14069 if (C->getZExtValue() <= 0xff)
14070 weight = CW_Constant;
14075 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14076 weight = CW_Constant;
14080 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14081 if ((C->getSExtValue() >= -0x80000000LL) &&
14082 (C->getSExtValue() <= 0x7fffffffLL))
14083 weight = CW_Constant;
14087 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14088 if (C->getZExtValue() <= 0xffffffff)
14089 weight = CW_Constant;
14096 /// LowerXConstraint - try to replace an X constraint, which matches anything,
14097 /// with another that has more specific requirements based on the type of the
14098 /// corresponding operand.
14099 const char *X86TargetLowering::
14100 LowerXConstraint(EVT ConstraintVT) const {
14101 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
14102 // 'f' like normal targets.
14103 if (ConstraintVT.isFloatingPoint()) {
14104 if (Subtarget->hasXMMInt())
14106 if (Subtarget->hasXMM())
14110 return TargetLowering::LowerXConstraint(ConstraintVT);
14113 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
14114 /// vector. If it is invalid, don't add anything to Ops.
14115 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
14116 std::string &Constraint,
14117 std::vector<SDValue>&Ops,
14118 SelectionDAG &DAG) const {
14119 SDValue Result(0, 0);
14121 // Only support length 1 constraints for now.
14122 if (Constraint.length() > 1) return;
14124 char ConstraintLetter = Constraint[0];
14125 switch (ConstraintLetter) {
14128 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14129 if (C->getZExtValue() <= 31) {
14130 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14136 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14137 if (C->getZExtValue() <= 63) {
14138 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14144 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14145 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
14146 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14153 if (C->getZExtValue() <= 255) {
14154 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14160 // 32-bit signed value
14161 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14162 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14163 C->getSExtValue())) {
14164 // Widen to 64 bits here to get it sign extended.
14165 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
14168 // FIXME gcc accepts some relocatable values here too, but only in certain
14169 // memory models; it's complicated.
14174 // 32-bit unsigned value
14175 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14176 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14177 C->getZExtValue())) {
14178 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14182 // FIXME gcc accepts some relocatable values here too, but only in certain
14183 // memory models; it's complicated.
14187 // Literal immediates are always ok.
14188 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
14189 // Widen to 64 bits here to get it sign extended.
14190 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
14194 // In any sort of PIC mode addresses need to be computed at runtime by
14195 // adding in a register or some sort of table lookup. These can't
14196 // be used as immediates.
14197 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
14200 // If we are in non-pic codegen mode, we allow the address of a global (with
14201 // an optional displacement) to be used with 'i'.
14202 GlobalAddressSDNode *GA = 0;
14203 int64_t Offset = 0;
14205 // Match either (GA), (GA+C), (GA+C1+C2), etc.
14207 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
14208 Offset += GA->getOffset();
14210 } else if (Op.getOpcode() == ISD::ADD) {
14211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14212 Offset += C->getZExtValue();
14213 Op = Op.getOperand(0);
14216 } else if (Op.getOpcode() == ISD::SUB) {
14217 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14218 Offset += -C->getZExtValue();
14219 Op = Op.getOperand(0);
14224 // Otherwise, this isn't something we can handle, reject it.
14228 const GlobalValue *GV = GA->getGlobal();
14229 // If we require an extra load to get this address, as in PIC mode, we
14230 // can't accept it.
14231 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
14232 getTargetMachine())))
14235 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
14236 GA->getValueType(0), Offset);
14241 if (Result.getNode()) {
14242 Ops.push_back(Result);
14245 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
14248 std::pair<unsigned, const TargetRegisterClass*>
14249 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
14251 // First, see if this is a constraint that directly corresponds to an LLVM
14253 if (Constraint.size() == 1) {
14254 // GCC Constraint Letters
14255 switch (Constraint[0]) {
14257 // TODO: Slight differences here in allocation order and leaving
14258 // RIP in the class. Do they matter any more here than they do
14259 // in the normal allocation?
14260 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
14261 if (Subtarget->is64Bit()) {
14262 if (VT == MVT::i32 || VT == MVT::f32)
14263 return std::make_pair(0U, X86::GR32RegisterClass);
14264 else if (VT == MVT::i16)
14265 return std::make_pair(0U, X86::GR16RegisterClass);
14266 else if (VT == MVT::i8 || VT == MVT::i1)
14267 return std::make_pair(0U, X86::GR8RegisterClass);
14268 else if (VT == MVT::i64 || VT == MVT::f64)
14269 return std::make_pair(0U, X86::GR64RegisterClass);
14272 // 32-bit fallthrough
14273 case 'Q': // Q_REGS
14274 if (VT == MVT::i32 || VT == MVT::f32)
14275 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
14276 else if (VT == MVT::i16)
14277 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
14278 else if (VT == MVT::i8 || VT == MVT::i1)
14279 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
14280 else if (VT == MVT::i64)
14281 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
14283 case 'r': // GENERAL_REGS
14284 case 'l': // INDEX_REGS
14285 if (VT == MVT::i8 || VT == MVT::i1)
14286 return std::make_pair(0U, X86::GR8RegisterClass);
14287 if (VT == MVT::i16)
14288 return std::make_pair(0U, X86::GR16RegisterClass);
14289 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
14290 return std::make_pair(0U, X86::GR32RegisterClass);
14291 return std::make_pair(0U, X86::GR64RegisterClass);
14292 case 'R': // LEGACY_REGS
14293 if (VT == MVT::i8 || VT == MVT::i1)
14294 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
14295 if (VT == MVT::i16)
14296 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
14297 if (VT == MVT::i32 || !Subtarget->is64Bit())
14298 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
14299 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
14300 case 'f': // FP Stack registers.
14301 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
14302 // value to the correct fpstack register class.
14303 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
14304 return std::make_pair(0U, X86::RFP32RegisterClass);
14305 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
14306 return std::make_pair(0U, X86::RFP64RegisterClass);
14307 return std::make_pair(0U, X86::RFP80RegisterClass);
14308 case 'y': // MMX_REGS if MMX allowed.
14309 if (!Subtarget->hasMMX()) break;
14310 return std::make_pair(0U, X86::VR64RegisterClass);
14311 case 'Y': // SSE_REGS if SSE2 allowed
14312 if (!Subtarget->hasXMMInt()) break;
14314 case 'x': // SSE_REGS if SSE1 allowed
14315 if (!Subtarget->hasXMM()) break;
14317 switch (VT.getSimpleVT().SimpleTy) {
14319 // Scalar SSE types.
14322 return std::make_pair(0U, X86::FR32RegisterClass);
14325 return std::make_pair(0U, X86::FR64RegisterClass);
14333 return std::make_pair(0U, X86::VR128RegisterClass);
14339 // Use the default implementation in TargetLowering to convert the register
14340 // constraint into a member of a register class.
14341 std::pair<unsigned, const TargetRegisterClass*> Res;
14342 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
14344 // Not found as a standard register?
14345 if (Res.second == 0) {
14346 // Map st(0) -> st(7) -> ST0
14347 if (Constraint.size() == 7 && Constraint[0] == '{' &&
14348 tolower(Constraint[1]) == 's' &&
14349 tolower(Constraint[2]) == 't' &&
14350 Constraint[3] == '(' &&
14351 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
14352 Constraint[5] == ')' &&
14353 Constraint[6] == '}') {
14355 Res.first = X86::ST0+Constraint[4]-'0';
14356 Res.second = X86::RFP80RegisterClass;
14360 // GCC allows "st(0)" to be called just plain "st".
14361 if (StringRef("{st}").equals_lower(Constraint)) {
14362 Res.first = X86::ST0;
14363 Res.second = X86::RFP80RegisterClass;
14368 if (StringRef("{flags}").equals_lower(Constraint)) {
14369 Res.first = X86::EFLAGS;
14370 Res.second = X86::CCRRegisterClass;
14374 // 'A' means EAX + EDX.
14375 if (Constraint == "A") {
14376 Res.first = X86::EAX;
14377 Res.second = X86::GR32_ADRegisterClass;
14383 // Otherwise, check to see if this is a register class of the wrong value
14384 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
14385 // turn into {ax},{dx}.
14386 if (Res.second->hasType(VT))
14387 return Res; // Correct type already, nothing to do.
14389 // All of the single-register GCC register classes map their values onto
14390 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
14391 // really want an 8-bit or 32-bit register, map to the appropriate register
14392 // class and return the appropriate register.
14393 if (Res.second == X86::GR16RegisterClass) {
14394 if (VT == MVT::i8) {
14395 unsigned DestReg = 0;
14396 switch (Res.first) {
14398 case X86::AX: DestReg = X86::AL; break;
14399 case X86::DX: DestReg = X86::DL; break;
14400 case X86::CX: DestReg = X86::CL; break;
14401 case X86::BX: DestReg = X86::BL; break;
14404 Res.first = DestReg;
14405 Res.second = X86::GR8RegisterClass;
14407 } else if (VT == MVT::i32) {
14408 unsigned DestReg = 0;
14409 switch (Res.first) {
14411 case X86::AX: DestReg = X86::EAX; break;
14412 case X86::DX: DestReg = X86::EDX; break;
14413 case X86::CX: DestReg = X86::ECX; break;
14414 case X86::BX: DestReg = X86::EBX; break;
14415 case X86::SI: DestReg = X86::ESI; break;
14416 case X86::DI: DestReg = X86::EDI; break;
14417 case X86::BP: DestReg = X86::EBP; break;
14418 case X86::SP: DestReg = X86::ESP; break;
14421 Res.first = DestReg;
14422 Res.second = X86::GR32RegisterClass;
14424 } else if (VT == MVT::i64) {
14425 unsigned DestReg = 0;
14426 switch (Res.first) {
14428 case X86::AX: DestReg = X86::RAX; break;
14429 case X86::DX: DestReg = X86::RDX; break;
14430 case X86::CX: DestReg = X86::RCX; break;
14431 case X86::BX: DestReg = X86::RBX; break;
14432 case X86::SI: DestReg = X86::RSI; break;
14433 case X86::DI: DestReg = X86::RDI; break;
14434 case X86::BP: DestReg = X86::RBP; break;
14435 case X86::SP: DestReg = X86::RSP; break;
14438 Res.first = DestReg;
14439 Res.second = X86::GR64RegisterClass;
14442 } else if (Res.second == X86::FR32RegisterClass ||
14443 Res.second == X86::FR64RegisterClass ||
14444 Res.second == X86::VR128RegisterClass) {
14445 // Handle references to XMM physical registers that got mapped into the
14446 // wrong class. This can happen with constraints like {xmm0} where the
14447 // target independent register mapper will just pick the first match it can
14448 // find, ignoring the required type.
14449 if (VT == MVT::f32)
14450 Res.second = X86::FR32RegisterClass;
14451 else if (VT == MVT::f64)
14452 Res.second = X86::FR64RegisterClass;
14453 else if (X86::VR128RegisterClass->hasType(VT))
14454 Res.second = X86::VR128RegisterClass;