1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/ADT/VectorExtras.h"
33 #include "llvm/Support/CommandLine.h"
34 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
35 cl::desc("Enable fastcc on X86"));
37 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
38 : TargetLowering(TM) {
39 Subtarget = &TM.getSubtarget<X86Subtarget>();
40 X86ScalarSSE = Subtarget->hasSSE2();
42 // Set up the TargetLowering object.
44 // X86 is weird, it always uses i8 for shift amounts and setcc results.
45 setShiftAmountType(MVT::i8);
46 setSetCCResultType(MVT::i8);
47 setSetCCResultContents(ZeroOrOneSetCCResult);
48 setSchedulingPreference(SchedulingForRegPressure);
49 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
50 setStackPointerRegisterToSaveRestore(X86::ESP);
52 // Set up the register classes.
53 addRegisterClass(MVT::i8, X86::R8RegisterClass);
54 addRegisterClass(MVT::i16, X86::R16RegisterClass);
55 addRegisterClass(MVT::i32, X86::R32RegisterClass);
57 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
59 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
60 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
61 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
64 // No SSE i64 SINT_TO_FP, so expand i32 UINT_TO_FP instead.
65 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
67 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
69 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
71 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
72 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
73 // SSE has no i16 to fp conversion, only i32
75 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
77 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
78 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
81 // We can handle SINT_TO_FP and FP_TO_SINT from/to i64 even though i64
83 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
84 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
86 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
88 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
89 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
92 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
94 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
95 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
98 // Handle FP_TO_UINT by promoting the destination to a larger signed
100 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
101 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
102 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
105 // Expand FP_TO_UINT into a select.
106 // FIXME: We would like to use a Custom expander here eventually to do
107 // the optimal thing for SSE vs. the default expansion in the legalizer.
108 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
110 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
112 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
113 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
115 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
116 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
117 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
118 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
119 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
120 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
124 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
125 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
126 setOperationAction(ISD::FREM , MVT::f64 , Expand);
127 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
128 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
129 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
130 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
131 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
132 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
133 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
134 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
135 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
136 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
137 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
139 setOperationAction(ISD::READIO , MVT::i1 , Expand);
140 setOperationAction(ISD::READIO , MVT::i8 , Expand);
141 setOperationAction(ISD::READIO , MVT::i16 , Expand);
142 setOperationAction(ISD::READIO , MVT::i32 , Expand);
143 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
144 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
145 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
146 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
148 // These should be promoted to a larger select which is supported.
149 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
150 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
152 // X86 wants to expand cmov itself.
153 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
154 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
155 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
156 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
157 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
158 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
159 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
160 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
161 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
162 // X86 ret instruction may pop stack.
163 setOperationAction(ISD::RET , MVT::Other, Custom);
165 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
166 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
167 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
168 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
169 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
170 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
171 // X86 wants to expand memset / memcpy itself.
172 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
173 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
175 // We don't have line number support yet.
176 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
177 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
178 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
180 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
181 setOperationAction(ISD::VASTART , MVT::Other, Custom);
183 // Use the default implementation.
184 setOperationAction(ISD::VAARG , MVT::Other, Expand);
185 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
186 setOperationAction(ISD::VAEND , MVT::Other, Expand);
187 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
188 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
189 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
192 // Set up the FP register classes.
193 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
194 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
196 // SSE has no load+extend ops
197 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
198 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
200 // Use ANDPD to simulate FABS.
201 setOperationAction(ISD::FABS , MVT::f64, Custom);
202 setOperationAction(ISD::FABS , MVT::f32, Custom);
204 // Use XORP to simulate FNEG.
205 setOperationAction(ISD::FNEG , MVT::f64, Custom);
206 setOperationAction(ISD::FNEG , MVT::f32, Custom);
208 // We don't support sin/cos/fmod
209 setOperationAction(ISD::FSIN , MVT::f64, Expand);
210 setOperationAction(ISD::FCOS , MVT::f64, Expand);
211 setOperationAction(ISD::FREM , MVT::f64, Expand);
212 setOperationAction(ISD::FSIN , MVT::f32, Expand);
213 setOperationAction(ISD::FCOS , MVT::f32, Expand);
214 setOperationAction(ISD::FREM , MVT::f32, Expand);
216 // Expand FP immediates into loads from the stack, except for the special
218 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
219 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
220 addLegalFPImmediate(+0.0); // xorps / xorpd
222 // Set up the FP register classes.
223 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
225 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
228 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
229 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
232 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
233 addLegalFPImmediate(+0.0); // FLD0
234 addLegalFPImmediate(+1.0); // FLD1
235 addLegalFPImmediate(-0.0); // FLD0/FCHS
236 addLegalFPImmediate(-1.0); // FLD1/FCHS
238 computeRegisterProperties();
240 // FIXME: These should be based on subtarget info. Plus, the values should
241 // be smaller when we are in optimizing for size mode.
242 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
243 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
244 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
245 allowUnalignedMemoryAccesses = true; // x86 supports it!
248 std::vector<SDOperand>
249 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
250 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
251 return LowerFastCCArguments(F, DAG);
252 return LowerCCCArguments(F, DAG);
255 std::pair<SDOperand, SDOperand>
256 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
257 bool isVarArg, unsigned CallingConv,
259 SDOperand Callee, ArgListTy &Args,
261 assert((!isVarArg || CallingConv == CallingConv::C) &&
262 "Only C takes varargs!");
264 // If the callee is a GlobalAddress node (quite common, every direct call is)
265 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
266 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
267 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
268 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
269 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
271 if (CallingConv == CallingConv::Fast && EnableFastCC)
272 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
273 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
276 //===----------------------------------------------------------------------===//
277 // C Calling Convention implementation
278 //===----------------------------------------------------------------------===//
280 std::vector<SDOperand>
281 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
282 std::vector<SDOperand> ArgValues;
284 MachineFunction &MF = DAG.getMachineFunction();
285 MachineFrameInfo *MFI = MF.getFrameInfo();
287 // Add DAG nodes to load the arguments... On entry to a function on the X86,
288 // the stack frame looks like this:
290 // [ESP] -- return address
291 // [ESP + 4] -- first argument (leftmost lexically)
292 // [ESP + 8] -- second argument, if first argument is four bytes in size
295 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
296 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
297 MVT::ValueType ObjectVT = getValueType(I->getType());
298 unsigned ArgIncrement = 4;
301 default: assert(0 && "Unhandled argument type!");
303 case MVT::i8: ObjSize = 1; break;
304 case MVT::i16: ObjSize = 2; break;
305 case MVT::i32: ObjSize = 4; break;
306 case MVT::i64: ObjSize = ArgIncrement = 8; break;
307 case MVT::f32: ObjSize = 4; break;
308 case MVT::f64: ObjSize = ArgIncrement = 8; break;
310 // Create the frame index object for this incoming parameter...
311 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
313 // Create the SelectionDAG nodes corresponding to a load from this parameter
314 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
316 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
320 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
321 DAG.getSrcValue(NULL));
323 if (MVT::isInteger(ObjectVT))
324 ArgValue = DAG.getConstant(0, ObjectVT);
326 ArgValue = DAG.getConstantFP(0, ObjectVT);
328 ArgValues.push_back(ArgValue);
330 ArgOffset += ArgIncrement; // Move on to the next argument...
333 // If the function takes variable number of arguments, make a frame index for
334 // the start of the first vararg value... for expansion of llvm.va_start.
336 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
337 ReturnAddrIndex = 0; // No return address slot generated yet.
338 BytesToPopOnReturn = 0; // Callee pops nothing.
339 BytesCallerReserves = ArgOffset;
341 // Finally, inform the code generator which regs we return values in.
342 switch (getValueType(F.getReturnType())) {
343 default: assert(0 && "Unknown type!");
344 case MVT::isVoid: break;
349 MF.addLiveOut(X86::EAX);
352 MF.addLiveOut(X86::EAX);
353 MF.addLiveOut(X86::EDX);
357 MF.addLiveOut(X86::ST0);
363 std::pair<SDOperand, SDOperand>
364 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
365 bool isVarArg, bool isTailCall,
366 SDOperand Callee, ArgListTy &Args,
368 // Count how many bytes are to be pushed on the stack.
369 unsigned NumBytes = 0;
373 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(0, getPointerTy()));
375 for (unsigned i = 0, e = Args.size(); i != e; ++i)
376 switch (getValueType(Args[i].second)) {
377 default: assert(0 && "Unknown value type!");
391 Chain = DAG.getCALLSEQ_START(Chain,
392 DAG.getConstant(NumBytes, getPointerTy()));
394 // Arguments go on the stack in reverse order, as specified by the ABI.
395 unsigned ArgOffset = 0;
396 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
397 std::vector<SDOperand> Stores;
399 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
400 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
401 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
403 switch (getValueType(Args[i].second)) {
404 default: assert(0 && "Unexpected ValueType for argument!");
408 // Promote the integer to 32 bits. If the input type is signed use a
409 // sign extend, otherwise use a zero extend.
410 if (Args[i].second->isSigned())
411 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
413 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
418 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
419 Args[i].first, PtrOff,
420 DAG.getSrcValue(NULL)));
425 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
426 Args[i].first, PtrOff,
427 DAG.getSrcValue(NULL)));
432 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
435 std::vector<MVT::ValueType> RetVals;
436 MVT::ValueType RetTyVT = getValueType(RetTy);
437 RetVals.push_back(MVT::Other);
439 // The result values produced have to be legal. Promote the result.
441 case MVT::isVoid: break;
443 RetVals.push_back(RetTyVT);
448 RetVals.push_back(MVT::i32);
452 RetVals.push_back(MVT::f32);
454 RetVals.push_back(MVT::f64);
457 RetVals.push_back(MVT::i32);
458 RetVals.push_back(MVT::i32);
462 std::vector<MVT::ValueType> NodeTys;
463 NodeTys.push_back(MVT::Other); // Returns a chain
464 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
465 std::vector<SDOperand> Ops;
466 Ops.push_back(Chain);
467 Ops.push_back(Callee);
469 // FIXME: Do not generate X86ISD::TAILCALL for now.
470 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
471 SDOperand InFlag = Chain.getValue(1);
474 NodeTys.push_back(MVT::Other); // Returns a chain
475 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
477 Ops.push_back(Chain);
478 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
479 Ops.push_back(DAG.getConstant(0, getPointerTy()));
480 Ops.push_back(InFlag);
481 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
482 InFlag = Chain.getValue(1);
485 if (RetTyVT != MVT::isVoid) {
487 default: assert(0 && "Unknown value type to return!");
490 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
491 Chain = RetVal.getValue(1);
492 if (RetTyVT == MVT::i1)
493 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
496 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
497 Chain = RetVal.getValue(1);
500 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
501 Chain = RetVal.getValue(1);
504 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
505 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
507 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
508 Chain = Hi.getValue(1);
513 std::vector<MVT::ValueType> Tys;
514 Tys.push_back(MVT::f64);
515 Tys.push_back(MVT::Other);
516 Tys.push_back(MVT::Flag);
517 std::vector<SDOperand> Ops;
518 Ops.push_back(Chain);
519 Ops.push_back(InFlag);
520 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
521 Chain = RetVal.getValue(1);
522 InFlag = RetVal.getValue(2);
524 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
525 // shouldn't be necessary except that RFP cannot be live across
526 // multiple blocks. When stackifier is fixed, they can be uncoupled.
527 MachineFunction &MF = DAG.getMachineFunction();
528 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
529 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
531 Tys.push_back(MVT::Other);
533 Ops.push_back(Chain);
534 Ops.push_back(RetVal);
535 Ops.push_back(StackSlot);
536 Ops.push_back(DAG.getValueType(RetTyVT));
537 Ops.push_back(InFlag);
538 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
539 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
540 DAG.getSrcValue(NULL));
541 Chain = RetVal.getValue(1);
544 if (RetTyVT == MVT::f32 && !X86ScalarSSE)
545 // FIXME: we would really like to remember that this FP_ROUND
546 // operation is okay to eliminate if we allow excess FP precision.
547 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
553 return std::make_pair(RetVal, Chain);
556 //===----------------------------------------------------------------------===//
557 // Fast Calling Convention implementation
558 //===----------------------------------------------------------------------===//
560 // The X86 'fast' calling convention passes up to two integer arguments in
561 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
562 // and requires that the callee pop its arguments off the stack (allowing proper
563 // tail calls), and has the same return value conventions as C calling convs.
565 // This calling convention always arranges for the callee pop value to be 8n+4
566 // bytes, which is needed for tail recursion elimination and stack alignment
569 // Note that this can be enhanced in the future to pass fp vals in registers
570 // (when we have a global fp allocator) and do other tricks.
573 /// AddLiveIn - This helper function adds the specified physical register to the
574 /// MachineFunction as a live in value. It also creates a corresponding virtual
576 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
577 TargetRegisterClass *RC) {
578 assert(RC->contains(PReg) && "Not the correct regclass!");
579 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
580 MF.addLiveIn(PReg, VReg);
585 std::vector<SDOperand>
586 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
587 std::vector<SDOperand> ArgValues;
589 MachineFunction &MF = DAG.getMachineFunction();
590 MachineFrameInfo *MFI = MF.getFrameInfo();
592 // Add DAG nodes to load the arguments... On entry to a function the stack
593 // frame looks like this:
595 // [ESP] -- return address
596 // [ESP + 4] -- first nonreg argument (leftmost lexically)
597 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
599 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
601 // Keep track of the number of integer regs passed so far. This can be either
602 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
604 unsigned NumIntRegs = 0;
606 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
607 MVT::ValueType ObjectVT = getValueType(I->getType());
608 unsigned ArgIncrement = 4;
609 unsigned ObjSize = 0;
613 default: assert(0 && "Unhandled argument type!");
616 if (NumIntRegs < 2) {
617 if (!I->use_empty()) {
618 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
619 X86::R8RegisterClass);
620 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
621 DAG.setRoot(ArgValue.getValue(1));
622 if (ObjectVT == MVT::i1)
623 // FIXME: Should insert a assertzext here.
624 ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue);
633 if (NumIntRegs < 2) {
634 if (!I->use_empty()) {
635 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
636 X86::R16RegisterClass);
637 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
638 DAG.setRoot(ArgValue.getValue(1));
646 if (NumIntRegs < 2) {
647 if (!I->use_empty()) {
648 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
649 X86::R32RegisterClass);
650 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
651 DAG.setRoot(ArgValue.getValue(1));
659 if (NumIntRegs == 0) {
660 if (!I->use_empty()) {
661 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
662 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
664 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
665 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
666 DAG.setRoot(Hi.getValue(1));
668 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
672 } else if (NumIntRegs == 1) {
673 if (!I->use_empty()) {
674 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
675 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
676 DAG.setRoot(Low.getValue(1));
678 // Load the high part from memory.
679 // Create the frame index object for this incoming parameter...
680 int FI = MFI->CreateFixedObject(4, ArgOffset);
681 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
682 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
683 DAG.getSrcValue(NULL));
684 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
690 ObjSize = ArgIncrement = 8;
692 case MVT::f32: ObjSize = 4; break;
693 case MVT::f64: ObjSize = ArgIncrement = 8; break;
696 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
698 if (ObjSize && !I->use_empty()) {
699 // Create the frame index object for this incoming parameter...
700 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
702 // Create the SelectionDAG nodes corresponding to a load from this
704 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
706 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
707 DAG.getSrcValue(NULL));
708 } else if (ArgValue.Val == 0) {
709 if (MVT::isInteger(ObjectVT))
710 ArgValue = DAG.getConstant(0, ObjectVT);
712 ArgValue = DAG.getConstantFP(0, ObjectVT);
714 ArgValues.push_back(ArgValue);
717 ArgOffset += ArgIncrement; // Move on to the next argument.
720 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
721 // arguments and the arguments after the retaddr has been pushed are aligned.
722 if ((ArgOffset & 7) == 0)
725 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
726 ReturnAddrIndex = 0; // No return address slot generated yet.
727 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
728 BytesCallerReserves = 0;
730 // Finally, inform the code generator which regs we return values in.
731 switch (getValueType(F.getReturnType())) {
732 default: assert(0 && "Unknown type!");
733 case MVT::isVoid: break;
738 MF.addLiveOut(X86::EAX);
741 MF.addLiveOut(X86::EAX);
742 MF.addLiveOut(X86::EDX);
746 MF.addLiveOut(X86::ST0);
752 std::pair<SDOperand, SDOperand>
753 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
754 bool isTailCall, SDOperand Callee,
755 ArgListTy &Args, SelectionDAG &DAG) {
756 // Count how many bytes are to be pushed on the stack.
757 unsigned NumBytes = 0;
759 // Keep track of the number of integer regs passed so far. This can be either
760 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
762 unsigned NumIntRegs = 0;
764 for (unsigned i = 0, e = Args.size(); i != e; ++i)
765 switch (getValueType(Args[i].second)) {
766 default: assert(0 && "Unknown value type!");
771 if (NumIntRegs < 2) {
780 if (NumIntRegs == 0) {
783 } else if (NumIntRegs == 1) {
795 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
796 // arguments and the arguments after the retaddr has been pushed are aligned.
797 if ((NumBytes & 7) == 0)
800 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
802 // Arguments go on the stack in reverse order, as specified by the ABI.
803 unsigned ArgOffset = 0;
804 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
806 std::vector<SDOperand> Stores;
807 std::vector<SDOperand> RegValuesToPass;
808 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
809 switch (getValueType(Args[i].second)) {
810 default: assert(0 && "Unexpected ValueType for argument!");
812 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first);
817 if (NumIntRegs < 2) {
818 RegValuesToPass.push_back(Args[i].first);
824 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
825 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
826 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
827 Args[i].first, PtrOff,
828 DAG.getSrcValue(NULL)));
833 if (NumIntRegs < 2) { // Can pass part of it in regs?
834 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
835 Args[i].first, DAG.getConstant(1, MVT::i32));
836 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
837 Args[i].first, DAG.getConstant(0, MVT::i32));
838 RegValuesToPass.push_back(Lo);
840 if (NumIntRegs < 2) { // Pass both parts in regs?
841 RegValuesToPass.push_back(Hi);
844 // Pass the high part in memory.
845 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
846 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
847 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
848 Hi, PtrOff, DAG.getSrcValue(NULL)));
855 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
856 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
857 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
858 Args[i].first, PtrOff,
859 DAG.getSrcValue(NULL)));
865 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
867 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
868 // arguments and the arguments after the retaddr has been pushed are aligned.
869 if ((ArgOffset & 7) == 0)
872 std::vector<MVT::ValueType> RetVals;
873 MVT::ValueType RetTyVT = getValueType(RetTy);
875 RetVals.push_back(MVT::Other);
877 // The result values produced have to be legal. Promote the result.
879 case MVT::isVoid: break;
881 RetVals.push_back(RetTyVT);
886 RetVals.push_back(MVT::i32);
890 RetVals.push_back(MVT::f32);
892 RetVals.push_back(MVT::f64);
895 RetVals.push_back(MVT::i32);
896 RetVals.push_back(MVT::i32);
900 // Build a sequence of copy-to-reg nodes chained together with token chain
901 // and flag operands which copy the outgoing args into registers.
903 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
905 SDOperand RegToPass = RegValuesToPass[i];
906 switch (RegToPass.getValueType()) {
907 default: assert(0 && "Bad thing to pass in regs");
909 CCReg = (i == 0) ? X86::AL : X86::DL;
912 CCReg = (i == 0) ? X86::AX : X86::DX;
915 CCReg = (i == 0) ? X86::EAX : X86::EDX;
919 Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag);
920 InFlag = Chain.getValue(1);
923 std::vector<MVT::ValueType> NodeTys;
924 NodeTys.push_back(MVT::Other); // Returns a chain
925 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
926 std::vector<SDOperand> Ops;
927 Ops.push_back(Chain);
928 Ops.push_back(Callee);
930 Ops.push_back(InFlag);
932 // FIXME: Do not generate X86ISD::TAILCALL for now.
933 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
934 InFlag = Chain.getValue(1);
937 NodeTys.push_back(MVT::Other); // Returns a chain
938 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
940 Ops.push_back(Chain);
941 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
942 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
943 Ops.push_back(InFlag);
944 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
945 InFlag = Chain.getValue(1);
948 if (RetTyVT != MVT::isVoid) {
950 default: assert(0 && "Unknown value type to return!");
953 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
954 Chain = RetVal.getValue(1);
955 if (RetTyVT == MVT::i1)
956 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
959 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
960 Chain = RetVal.getValue(1);
963 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
964 Chain = RetVal.getValue(1);
967 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
968 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
970 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
971 Chain = Hi.getValue(1);
976 std::vector<MVT::ValueType> Tys;
977 Tys.push_back(MVT::f64);
978 Tys.push_back(MVT::Other);
979 Tys.push_back(MVT::Flag);
980 std::vector<SDOperand> Ops;
981 Ops.push_back(Chain);
982 Ops.push_back(InFlag);
983 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
984 Chain = RetVal.getValue(1);
985 InFlag = RetVal.getValue(2);
987 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
988 // shouldn't be necessary except that RFP cannot be live across
989 // multiple blocks. When stackifier is fixed, they can be uncoupled.
990 MachineFunction &MF = DAG.getMachineFunction();
991 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
992 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
994 Tys.push_back(MVT::Other);
996 Ops.push_back(Chain);
997 Ops.push_back(RetVal);
998 Ops.push_back(StackSlot);
999 Ops.push_back(DAG.getValueType(RetTyVT));
1000 Ops.push_back(InFlag);
1001 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
1002 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
1003 DAG.getSrcValue(NULL));
1004 Chain = RetVal.getValue(1);
1007 if (RetTyVT == MVT::f32 && !X86ScalarSSE)
1008 // FIXME: we would really like to remember that this FP_ROUND
1009 // operation is okay to eliminate if we allow excess FP precision.
1010 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
1016 return std::make_pair(RetVal, Chain);
1019 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1020 if (ReturnAddrIndex == 0) {
1021 // Set up a frame object for the return address.
1022 MachineFunction &MF = DAG.getMachineFunction();
1023 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1026 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
1031 std::pair<SDOperand, SDOperand> X86TargetLowering::
1032 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
1033 SelectionDAG &DAG) {
1035 if (Depth) // Depths > 0 not supported yet!
1036 Result = DAG.getConstant(0, getPointerTy());
1038 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
1039 if (!isFrameAddress)
1040 // Just load the return address
1041 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
1042 DAG.getSrcValue(NULL));
1044 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
1045 DAG.getConstant(4, MVT::i32));
1047 return std::make_pair(Result, Chain);
1050 /// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode
1051 /// which corresponds to the condition code.
1052 static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
1054 default: assert(0 && "Unknown X86 conditional code!");
1055 case X86ISD::COND_A: return X86::JA;
1056 case X86ISD::COND_AE: return X86::JAE;
1057 case X86ISD::COND_B: return X86::JB;
1058 case X86ISD::COND_BE: return X86::JBE;
1059 case X86ISD::COND_E: return X86::JE;
1060 case X86ISD::COND_G: return X86::JG;
1061 case X86ISD::COND_GE: return X86::JGE;
1062 case X86ISD::COND_L: return X86::JL;
1063 case X86ISD::COND_LE: return X86::JLE;
1064 case X86ISD::COND_NE: return X86::JNE;
1065 case X86ISD::COND_NO: return X86::JNO;
1066 case X86ISD::COND_NP: return X86::JNP;
1067 case X86ISD::COND_NS: return X86::JNS;
1068 case X86ISD::COND_O: return X86::JO;
1069 case X86ISD::COND_P: return X86::JP;
1070 case X86ISD::COND_S: return X86::JS;
1074 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1075 /// specific condition code. It returns a false if it cannot do a direct
1076 /// translation. X86CC is the translated CondCode. Flip is set to true if the
1077 /// the order of comparison operands should be flipped.
1078 static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC,
1080 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1082 X86CC = X86ISD::COND_INVALID;
1084 switch (SetCCOpcode) {
1086 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1087 case ISD::SETGT: X86CC = X86ISD::COND_G; break;
1088 case ISD::SETGE: X86CC = X86ISD::COND_GE; break;
1089 case ISD::SETLT: X86CC = X86ISD::COND_L; break;
1090 case ISD::SETLE: X86CC = X86ISD::COND_LE; break;
1091 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1092 case ISD::SETULT: X86CC = X86ISD::COND_B; break;
1093 case ISD::SETUGT: X86CC = X86ISD::COND_A; break;
1094 case ISD::SETULE: X86CC = X86ISD::COND_BE; break;
1095 case ISD::SETUGE: X86CC = X86ISD::COND_AE; break;
1098 // On a floating point condition, the flags are set as follows:
1100 // 0 | 0 | 0 | X > Y
1101 // 0 | 0 | 1 | X < Y
1102 // 1 | 0 | 0 | X == Y
1103 // 1 | 1 | 1 | unordered
1104 switch (SetCCOpcode) {
1107 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1108 case ISD::SETOLE: Flip = true; // Fallthrough
1110 case ISD::SETGT: X86CC = X86ISD::COND_A; break;
1111 case ISD::SETOLT: Flip = true; // Fallthrough
1113 case ISD::SETGE: X86CC = X86ISD::COND_AE; break;
1114 case ISD::SETUGE: Flip = true; // Fallthrough
1116 case ISD::SETLT: X86CC = X86ISD::COND_B; break;
1117 case ISD::SETUGT: Flip = true; // Fallthrough
1119 case ISD::SETLE: X86CC = X86ISD::COND_BE; break;
1121 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1122 case ISD::SETUO: X86CC = X86ISD::COND_P; break;
1123 case ISD::SETO: X86CC = X86ISD::COND_NP; break;
1127 return X86CC != X86ISD::COND_INVALID;
1130 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1131 /// code. Current x86 isa includes the following FP cmov instructions:
1132 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1133 static bool hasFPCMov(unsigned X86CC) {
1137 case X86ISD::COND_B:
1138 case X86ISD::COND_BE:
1139 case X86ISD::COND_E:
1140 case X86ISD::COND_P:
1141 case X86ISD::COND_A:
1142 case X86ISD::COND_AE:
1143 case X86ISD::COND_NE:
1144 case X86ISD::COND_NP:
1150 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1151 MachineBasicBlock *BB) {
1152 switch (MI->getOpcode()) {
1153 default: assert(false && "Unexpected instr type to insert");
1154 case X86::CMOV_FR32:
1155 case X86::CMOV_FR64: {
1156 // To "insert" a SELECT_CC instruction, we actually have to insert the
1157 // diamond control-flow pattern. The incoming instruction knows the
1158 // destination vreg to set, the condition code register to branch on, the
1159 // true/false values to select between, and a branch opcode to use.
1160 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1161 ilist<MachineBasicBlock>::iterator It = BB;
1167 // cmpTY ccX, r1, r2
1169 // fallthrough --> copy0MBB
1170 MachineBasicBlock *thisMBB = BB;
1171 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1172 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1173 unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
1174 BuildMI(BB, Opc, 1).addMBB(sinkMBB);
1175 MachineFunction *F = BB->getParent();
1176 F->getBasicBlockList().insert(It, copy0MBB);
1177 F->getBasicBlockList().insert(It, sinkMBB);
1178 // Update machine-CFG edges
1179 BB->addSuccessor(copy0MBB);
1180 BB->addSuccessor(sinkMBB);
1183 // %FalseValue = ...
1184 // # fallthrough to sinkMBB
1187 // Update machine-CFG edges
1188 BB->addSuccessor(sinkMBB);
1191 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1194 BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
1195 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1196 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1198 delete MI; // The pseudo instruction is gone now.
1202 case X86::FP_TO_INT16_IN_MEM:
1203 case X86::FP_TO_INT32_IN_MEM:
1204 case X86::FP_TO_INT64_IN_MEM: {
1205 // Change the floating point control register to use "round towards zero"
1206 // mode when truncating to an integer value.
1207 MachineFunction *F = BB->getParent();
1208 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1209 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
1211 // Load the old value of the high byte of the control word...
1213 F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass);
1214 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
1216 // Set the high part to be round to zero...
1217 addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
1219 // Reload the modified control word now...
1220 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1222 // Restore the memory image of control word to original value
1223 addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
1225 // Get the X86 opcode to use.
1227 switch (MI->getOpcode()) {
1228 default: assert(0 && "illegal opcode!");
1229 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
1230 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
1231 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
1235 MachineOperand &Op = MI->getOperand(0);
1236 if (Op.isRegister()) {
1237 AM.BaseType = X86AddressMode::RegBase;
1238 AM.Base.Reg = Op.getReg();
1240 AM.BaseType = X86AddressMode::FrameIndexBase;
1241 AM.Base.FrameIndex = Op.getFrameIndex();
1243 Op = MI->getOperand(1);
1244 if (Op.isImmediate())
1245 AM.Scale = Op.getImmedValue();
1246 Op = MI->getOperand(2);
1247 if (Op.isImmediate())
1248 AM.IndexReg = Op.getImmedValue();
1249 Op = MI->getOperand(3);
1250 if (Op.isGlobalAddress()) {
1251 AM.GV = Op.getGlobal();
1253 AM.Disp = Op.getImmedValue();
1255 addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
1257 // Reload the original control word now.
1258 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1260 delete MI; // The pseudo instruction is gone now.
1267 //===----------------------------------------------------------------------===//
1268 // X86 Custom Lowering Hooks
1269 //===----------------------------------------------------------------------===//
1271 /// LowerOperation - Provide custom lowering hooks for some operations.
1273 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1274 switch (Op.getOpcode()) {
1275 default: assert(0 && "Should not custom lower this!");
1276 case ISD::SHL_PARTS:
1277 case ISD::SRA_PARTS:
1278 case ISD::SRL_PARTS: {
1279 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1280 "Not an i64 shift!");
1281 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
1282 SDOperand ShOpLo = Op.getOperand(0);
1283 SDOperand ShOpHi = Op.getOperand(1);
1284 SDOperand ShAmt = Op.getOperand(2);
1285 SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
1286 DAG.getConstant(31, MVT::i8))
1287 : DAG.getConstant(0, MVT::i32);
1289 SDOperand Tmp2, Tmp3;
1290 if (Op.getOpcode() == ISD::SHL_PARTS) {
1291 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
1292 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
1294 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
1295 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
1298 SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
1299 ShAmt, DAG.getConstant(32, MVT::i8));
1302 SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1304 std::vector<MVT::ValueType> Tys;
1305 Tys.push_back(MVT::i32);
1306 Tys.push_back(MVT::Flag);
1307 std::vector<SDOperand> Ops;
1308 if (Op.getOpcode() == ISD::SHL_PARTS) {
1309 Ops.push_back(Tmp2);
1310 Ops.push_back(Tmp3);
1312 Ops.push_back(InFlag);
1313 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1314 InFlag = Hi.getValue(1);
1317 Ops.push_back(Tmp3);
1318 Ops.push_back(Tmp1);
1320 Ops.push_back(InFlag);
1321 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1323 Ops.push_back(Tmp2);
1324 Ops.push_back(Tmp3);
1326 Ops.push_back(InFlag);
1327 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1328 InFlag = Lo.getValue(1);
1331 Ops.push_back(Tmp3);
1332 Ops.push_back(Tmp1);
1334 Ops.push_back(InFlag);
1335 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1339 Tys.push_back(MVT::i32);
1340 Tys.push_back(MVT::i32);
1344 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1346 case ISD::SINT_TO_FP: {
1347 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
1348 Op.getOperand(0).getValueType() >= MVT::i16 &&
1349 "Unknown SINT_TO_FP to lower!");
1352 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
1353 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
1354 MachineFunction &MF = DAG.getMachineFunction();
1355 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1356 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1357 SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other,
1358 DAG.getEntryNode(), Op.getOperand(0),
1359 StackSlot, DAG.getSrcValue(NULL));
1362 std::vector<MVT::ValueType> Tys;
1363 Tys.push_back(MVT::f64);
1364 Tys.push_back(MVT::Other);
1365 if (X86ScalarSSE) Tys.push_back(MVT::Flag);
1366 std::vector<SDOperand> Ops;
1367 Ops.push_back(Chain);
1368 Ops.push_back(StackSlot);
1369 Ops.push_back(DAG.getValueType(SrcVT));
1370 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
1374 Chain = Result.getValue(1);
1375 SDOperand InFlag = Result.getValue(2);
1377 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
1378 // shouldn't be necessary except that RFP cannot be live across
1379 // multiple blocks. When stackifier is fixed, they can be uncoupled.
1380 MachineFunction &MF = DAG.getMachineFunction();
1381 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
1382 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1383 std::vector<MVT::ValueType> Tys;
1384 Tys.push_back(MVT::Other);
1385 std::vector<SDOperand> Ops;
1386 Ops.push_back(Chain);
1387 Ops.push_back(Result);
1388 Ops.push_back(StackSlot);
1389 Ops.push_back(DAG.getValueType(Op.getValueType()));
1390 Ops.push_back(InFlag);
1391 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
1392 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
1393 DAG.getSrcValue(NULL));
1398 case ISD::FP_TO_SINT: {
1399 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
1400 "Unknown FP_TO_SINT to lower!");
1401 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
1403 MachineFunction &MF = DAG.getMachineFunction();
1404 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
1405 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1406 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1409 switch (Op.getValueType()) {
1410 default: assert(0 && "Invalid FP_TO_SINT to lower!");
1411 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
1412 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
1413 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
1416 SDOperand Chain = DAG.getEntryNode();
1417 SDOperand Value = Op.getOperand(0);
1419 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
1420 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, StackSlot,
1421 DAG.getSrcValue(0));
1422 std::vector<MVT::ValueType> Tys;
1423 Tys.push_back(MVT::f64);
1424 Tys.push_back(MVT::Other);
1425 std::vector<SDOperand> Ops;
1426 Ops.push_back(Chain);
1427 Ops.push_back(StackSlot);
1428 Ops.push_back(DAG.getValueType(Op.getOperand(0).getValueType()));
1429 Value = DAG.getNode(X86ISD::FLD, Tys, Ops);
1430 Chain = Value.getValue(1);
1431 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1432 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1435 // Build the FP_TO_INT*_IN_MEM
1436 std::vector<SDOperand> Ops;
1437 Ops.push_back(Chain);
1438 Ops.push_back(Value);
1439 Ops.push_back(StackSlot);
1440 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
1443 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
1444 DAG.getSrcValue(NULL));
1446 case ISD::READCYCLECOUNTER: {
1447 std::vector<MVT::ValueType> Tys;
1448 Tys.push_back(MVT::Other);
1449 Tys.push_back(MVT::Flag);
1450 std::vector<SDOperand> Ops;
1451 Ops.push_back(Op.getOperand(0));
1452 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
1454 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
1455 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
1456 MVT::i32, Ops[0].getValue(2)));
1457 Ops.push_back(Ops[1].getValue(1));
1458 Tys[0] = Tys[1] = MVT::i32;
1459 Tys.push_back(MVT::Other);
1460 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1463 MVT::ValueType VT = Op.getValueType();
1464 const Type *OpNTy = MVT::getTypeForValueType(VT);
1465 std::vector<Constant*> CV;
1466 if (VT == MVT::f64) {
1467 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
1468 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1470 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
1471 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1472 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1473 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1475 Constant *CS = ConstantStruct::get(CV);
1476 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
1478 = DAG.getNode(X86ISD::LOAD_PACK,
1479 VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
1480 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
1483 MVT::ValueType VT = Op.getValueType();
1484 const Type *OpNTy = MVT::getTypeForValueType(VT);
1485 std::vector<Constant*> CV;
1486 if (VT == MVT::f64) {
1487 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
1488 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1490 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
1491 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1492 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1493 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1495 Constant *CS = ConstantStruct::get(CV);
1496 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
1498 = DAG.getNode(X86ISD::LOAD_PACK,
1499 VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
1500 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
1503 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
1505 SDOperand CC = Op.getOperand(2);
1506 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1507 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
1510 if (translateX86CC(CC, isFP, X86CC, Flip)) {
1512 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1513 Op.getOperand(1), Op.getOperand(0));
1515 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1516 Op.getOperand(0), Op.getOperand(1));
1517 return DAG.getNode(X86ISD::SETCC, MVT::i8,
1518 DAG.getConstant(X86CC, MVT::i8), Cond);
1520 assert(isFP && "Illegal integer SetCC!");
1522 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1523 Op.getOperand(0), Op.getOperand(1));
1524 std::vector<MVT::ValueType> Tys;
1525 std::vector<SDOperand> Ops;
1526 switch (SetCCOpcode) {
1527 default: assert(false && "Illegal floating point SetCC!");
1528 case ISD::SETOEQ: { // !PF & ZF
1529 Tys.push_back(MVT::i8);
1530 Tys.push_back(MVT::Flag);
1531 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1532 Ops.push_back(Cond);
1533 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1534 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1535 DAG.getConstant(X86ISD::COND_E, MVT::i8),
1537 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1539 case ISD::SETUNE: { // PF | !ZF
1540 Tys.push_back(MVT::i8);
1541 Tys.push_back(MVT::Flag);
1542 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1543 Ops.push_back(Cond);
1544 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1545 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1546 DAG.getConstant(X86ISD::COND_NE, MVT::i8),
1548 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1554 MVT::ValueType VT = Op.getValueType();
1555 bool isFP = MVT::isFloatingPoint(VT);
1556 bool isFPStack = isFP && !X86ScalarSSE;
1557 bool isFPSSE = isFP && X86ScalarSSE;
1558 bool addTest = false;
1559 SDOperand Op0 = Op.getOperand(0);
1561 if (Op0.getOpcode() == ISD::SETCC)
1562 Op0 = LowerOperation(Op0, DAG);
1564 if (Op0.getOpcode() == X86ISD::SETCC) {
1565 // If condition flag is set by a X86ISD::CMP, then make a copy of it
1566 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
1567 // have another use it will be eliminated.
1568 // If the X86ISD::SETCC has more than one use, then it's probably better
1569 // to use a test instead of duplicating the X86ISD::CMP (for register
1570 // pressure reason).
1571 if (Op0.getOperand(1).getOpcode() == X86ISD::CMP) {
1572 if (!Op0.hasOneUse()) {
1573 std::vector<MVT::ValueType> Tys;
1574 for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i)
1575 Tys.push_back(Op0.Val->getValueType(i));
1576 std::vector<SDOperand> Ops;
1577 for (unsigned i = 0; i < Op0.getNumOperands(); ++i)
1578 Ops.push_back(Op0.getOperand(i));
1579 Op0 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1582 CC = Op0.getOperand(0);
1583 Cond = Op0.getOperand(1);
1584 // Make a copy as flag result cannot be used by more than one.
1585 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1586 Cond.getOperand(0), Cond.getOperand(1));
1588 isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
1595 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1596 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
1599 std::vector<MVT::ValueType> Tys;
1600 Tys.push_back(Op.getValueType());
1601 Tys.push_back(MVT::Flag);
1602 std::vector<SDOperand> Ops;
1603 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
1604 // condition is true.
1605 Ops.push_back(Op.getOperand(2));
1606 Ops.push_back(Op.getOperand(1));
1608 Ops.push_back(Cond);
1609 return DAG.getNode(X86ISD::CMOV, Tys, Ops);
1612 bool addTest = false;
1613 SDOperand Cond = Op.getOperand(1);
1614 SDOperand Dest = Op.getOperand(2);
1616 if (Cond.getOpcode() == ISD::SETCC)
1617 Cond = LowerOperation(Cond, DAG);
1619 if (Cond.getOpcode() == X86ISD::SETCC) {
1620 // If condition flag is set by a X86ISD::CMP, then make a copy of it
1621 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
1622 // have another use it will be eliminated.
1623 // If the X86ISD::SETCC has more than one use, then it's probably better
1624 // to use a test instead of duplicating the X86ISD::CMP (for register
1625 // pressure reason).
1626 if (Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
1627 if (!Cond.hasOneUse()) {
1628 std::vector<MVT::ValueType> Tys;
1629 for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i)
1630 Tys.push_back(Cond.Val->getValueType(i));
1631 std::vector<SDOperand> Ops;
1632 for (unsigned i = 0; i < Cond.getNumOperands(); ++i)
1633 Ops.push_back(Cond.getOperand(i));
1634 Cond = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1637 CC = Cond.getOperand(0);
1638 Cond = Cond.getOperand(1);
1639 // Make a copy as flag result cannot be used by more than one.
1640 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1641 Cond.getOperand(0), Cond.getOperand(1));
1648 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1649 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1651 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
1652 Op.getOperand(0), Op.getOperand(2), CC, Cond);
1656 SDOperand Chain = Op.getOperand(0);
1658 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1659 if (Align == 0) Align = 1;
1661 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
1662 // If not DWORD aligned, call memset if size is less than the threshold.
1663 // It knows how to align to the right boundary first.
1664 if ((Align & 3) != 0 &&
1665 !(I && I->getValue() >= Subtarget->getMinRepStrSizeThreshold())) {
1666 MVT::ValueType IntPtr = getPointerTy();
1667 const Type *IntPtrTy = getTargetData().getIntPtrType();
1668 std::vector<std::pair<SDOperand, const Type*> > Args;
1669 Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy));
1670 // Extend the ubyte argument to be an int value for the call.
1671 SDOperand Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
1672 Args.push_back(std::make_pair(Val, IntPtrTy));
1673 Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy));
1674 std::pair<SDOperand,SDOperand> CallResult =
1675 LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false,
1676 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
1677 return CallResult.second;
1682 if (ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2))) {
1684 unsigned Val = ValC->getValue() & 255;
1686 // If the value is a constant, then we can potentially use larger sets.
1687 switch (Align & 3) {
1688 case 2: // WORD aligned
1691 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1693 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1694 DAG.getConstant(1, MVT::i8));
1695 Val = (Val << 8) | Val;
1698 case 0: // DWORD aligned
1701 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1703 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1704 DAG.getConstant(2, MVT::i8));
1705 Val = (Val << 8) | Val;
1706 Val = (Val << 16) | Val;
1709 default: // Byte aligned
1711 Count = Op.getOperand(3);
1716 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
1718 InFlag = Chain.getValue(1);
1721 Count = Op.getOperand(3);
1722 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
1723 InFlag = Chain.getValue(1);
1726 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1727 InFlag = Chain.getValue(1);
1728 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1729 InFlag = Chain.getValue(1);
1731 return DAG.getNode(X86ISD::REP_STOS, MVT::Other, Chain,
1732 DAG.getValueType(AVT), InFlag);
1735 SDOperand Chain = Op.getOperand(0);
1737 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1738 if (Align == 0) Align = 1;
1740 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
1741 // If not DWORD aligned, call memcpy if size is less than the threshold.
1742 // It knows how to align to the right boundary first.
1743 if ((Align & 3) != 0 &&
1744 !(I && I->getValue() >= Subtarget->getMinRepStrSizeThreshold())) {
1745 MVT::ValueType IntPtr = getPointerTy();
1746 const Type *IntPtrTy = getTargetData().getIntPtrType();
1747 std::vector<std::pair<SDOperand, const Type*> > Args;
1748 Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy));
1749 Args.push_back(std::make_pair(Op.getOperand(2), IntPtrTy));
1750 Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy));
1751 std::pair<SDOperand,SDOperand> CallResult =
1752 LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false,
1753 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
1754 return CallResult.second;
1759 switch (Align & 3) {
1760 case 2: // WORD aligned
1763 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1765 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1767 case 0: // DWORD aligned
1770 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1772 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1773 DAG.getConstant(2, MVT::i8));
1775 default: // Byte aligned
1777 Count = Op.getOperand(3);
1782 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1783 InFlag = Chain.getValue(1);
1784 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1785 InFlag = Chain.getValue(1);
1786 Chain = DAG.getCopyToReg(Chain, X86::ESI, Op.getOperand(2), InFlag);
1787 InFlag = Chain.getValue(1);
1789 return DAG.getNode(X86ISD::REP_MOVS, MVT::Other, Chain,
1790 DAG.getValueType(AVT), InFlag);
1792 case ISD::ConstantPool: {
1793 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1795 DAG.getTargetConstantPool(CP->get(), getPointerTy(), CP->getAlignment());
1796 // Only lower ConstantPool on Darwin.
1797 if (getTargetMachine().
1798 getSubtarget<X86Subtarget>().isTargetDarwin()) {
1799 // With PIC, the address is actually $g + Offset.
1801 Result = DAG.getNode(ISD::ADD, getPointerTy(),
1802 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
1807 case ISD::GlobalAddress: {
1809 // Only lower GlobalAddress on Darwin.
1810 if (getTargetMachine().
1811 getSubtarget<X86Subtarget>().isTargetDarwin()) {
1812 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1813 SDOperand Addr = DAG.getTargetGlobalAddress(GV, getPointerTy());
1814 // With PIC, the address is actually $g + Offset.
1816 Addr = DAG.getNode(ISD::ADD, getPointerTy(),
1817 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Addr);
1819 // For Darwin, external and weak symbols are indirect, so we want to load
1820 // the value at address GV, not the value of GV itself. This means that
1821 // the GlobalAddress must be in the base or index register of the address,
1822 // not the GV offset field.
1823 if (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
1824 (GV->isExternal() && !GV->hasNotBeenReadFromBytecode()))
1825 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(),
1826 Addr, DAG.getSrcValue(NULL));
1831 case ISD::VASTART: {
1832 // vastart just stores the address of the VarArgsFrameIndex slot into the
1833 // memory location argument.
1834 // FIXME: Replace MVT::i32 with PointerTy
1835 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
1836 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
1837 Op.getOperand(1), Op.getOperand(2));
1842 switch(Op.getNumOperands()) {
1844 assert(0 && "Do not know how to return this many arguments!");
1847 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
1848 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1850 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1851 if (MVT::isInteger(ArgVT))
1852 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EAX, Op.getOperand(1),
1854 else if (!X86ScalarSSE) {
1855 std::vector<MVT::ValueType> Tys;
1856 Tys.push_back(MVT::Other);
1857 Tys.push_back(MVT::Flag);
1858 std::vector<SDOperand> Ops;
1859 Ops.push_back(Op.getOperand(0));
1860 Ops.push_back(Op.getOperand(1));
1861 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
1864 SDOperand Chain = Op.getOperand(0);
1865 SDOperand Value = Op.getOperand(1);
1867 if (Value.getOpcode() == ISD::LOAD &&
1868 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
1869 Chain = Value.getOperand(0);
1870 MemLoc = Value.getOperand(1);
1872 // Spill the value to memory and reload it into top of stack.
1873 unsigned Size = MVT::getSizeInBits(ArgVT)/8;
1874 MachineFunction &MF = DAG.getMachineFunction();
1875 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1876 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
1877 Chain = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0),
1878 Value, MemLoc, DAG.getSrcValue(0));
1880 std::vector<MVT::ValueType> Tys;
1881 Tys.push_back(MVT::f64);
1882 Tys.push_back(MVT::Other);
1883 std::vector<SDOperand> Ops;
1884 Ops.push_back(Chain);
1885 Ops.push_back(MemLoc);
1886 Ops.push_back(DAG.getValueType(ArgVT));
1887 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
1889 Tys.push_back(MVT::Other);
1890 Tys.push_back(MVT::Flag);
1892 Ops.push_back(Copy.getValue(1));
1893 Ops.push_back(Copy);
1894 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
1899 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2),
1901 Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1));
1904 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
1905 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
1911 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1913 default: return NULL;
1914 case X86ISD::SHLD: return "X86ISD::SHLD";
1915 case X86ISD::SHRD: return "X86ISD::SHRD";
1916 case X86ISD::FAND: return "X86ISD::FAND";
1917 case X86ISD::FXOR: return "X86ISD::FXOR";
1918 case X86ISD::FILD: return "X86ISD::FILD";
1919 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
1920 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
1921 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
1922 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
1923 case X86ISD::FLD: return "X86ISD::FLD";
1924 case X86ISD::FST: return "X86ISD::FST";
1925 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
1926 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
1927 case X86ISD::CALL: return "X86ISD::CALL";
1928 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
1929 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
1930 case X86ISD::CMP: return "X86ISD::CMP";
1931 case X86ISD::TEST: return "X86ISD::TEST";
1932 case X86ISD::SETCC: return "X86ISD::SETCC";
1933 case X86ISD::CMOV: return "X86ISD::CMOV";
1934 case X86ISD::BRCOND: return "X86ISD::BRCOND";
1935 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
1936 case X86ISD::REP_STOS: return "X86ISD::RET_STOS";
1937 case X86ISD::REP_MOVS: return "X86ISD::RET_MOVS";
1938 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
1939 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
1943 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1945 uint64_t &KnownZero,
1947 unsigned Depth) const {
1949 unsigned Opc = Op.getOpcode();
1950 KnownZero = KnownOne = 0; // Don't know anything.
1954 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
1957 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
1962 std::vector<unsigned> X86TargetLowering::
1963 getRegForInlineAsmConstraint(const std::string &Constraint) const {
1964 if (Constraint.size() == 1) {
1965 // FIXME: not handling fp-stack yet!
1966 // FIXME: not handling MMX registers yet ('y' constraint).
1967 switch (Constraint[0]) { // GCC X86 Constraint Letters
1968 default: break; // Unknown constriant letter
1969 case 'r': // GENERAL_REGS
1970 case 'R': // LEGACY_REGS
1971 return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX,
1972 X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
1973 case 'l': // INDEX_REGS
1974 return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX,
1975 X86::ESI, X86::EDI, X86::EBP, 0);
1976 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
1978 return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0);
1979 case 'x': // SSE_REGS if SSE1 allowed
1980 if (Subtarget->hasSSE1())
1981 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1982 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
1984 return std::vector<unsigned>();
1985 case 'Y': // SSE_REGS if SSE2 allowed
1986 if (Subtarget->hasSSE2())
1987 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1988 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
1990 return std::vector<unsigned>();
1994 // Handle explicit register names.
1995 return TargetLowering::getRegForInlineAsmConstraint(Constraint);