1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86ShuffleDecode.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/Dwarf.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
54 using namespace dwarf;
56 STATISTIC(NumTailCalls, "Number of tail calls");
59 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
61 // Forward declarations.
62 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
65 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
67 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
69 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
70 if (is64Bit) return new X8664_MachoTargetObjectFile();
71 return new TargetLoweringObjectFileMachO();
72 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
73 if (is64Bit) return new X8664_ELFTargetObjectFile(TM);
74 return new X8632_ELFTargetObjectFile(TM);
75 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) {
76 return new TargetLoweringObjectFileCOFF();
78 llvm_unreachable("unknown subtarget type");
81 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
82 : TargetLowering(TM, createTLOF(TM)) {
83 Subtarget = &TM.getSubtarget<X86Subtarget>();
84 X86ScalarSSEf64 = Subtarget->hasSSE2();
85 X86ScalarSSEf32 = Subtarget->hasSSE1();
86 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
88 RegInfo = TM.getRegisterInfo();
91 // Set up the TargetLowering object.
93 // X86 is weird, it always uses i8 for shift amounts and setcc results.
94 setShiftAmountType(MVT::i8);
95 setBooleanContents(ZeroOrOneBooleanContent);
96 setSchedulingPreference(Sched::RegPressure);
97 setStackPointerRegisterToSaveRestore(X86StackPtr);
99 if (Subtarget->isTargetDarwin()) {
100 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
101 setUseUnderscoreSetJmp(false);
102 setUseUnderscoreLongJmp(false);
103 } else if (Subtarget->isTargetMingw()) {
104 // MS runtime is weird: it exports _setjmp, but longjmp!
105 setUseUnderscoreSetJmp(true);
106 setUseUnderscoreLongJmp(false);
108 setUseUnderscoreSetJmp(true);
109 setUseUnderscoreLongJmp(true);
112 // Set up the register classes.
113 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
114 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
115 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
116 if (Subtarget->is64Bit())
117 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
119 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
121 // We don't accept any truncstore of integer registers.
122 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
124 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
125 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
127 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
129 // SETOEQ and SETUNE require checking two conditions.
130 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
131 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
132 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
133 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
135 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
137 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
139 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
140 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
141 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
143 if (Subtarget->is64Bit()) {
144 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
145 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
146 } else if (!UseSoftFloat) {
147 // We have an algorithm for SSE2->double, and we turn this into a
148 // 64-bit FILD followed by conditional FADD for other targets.
149 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
150 // We have an algorithm for SSE2, and we turn this into a 64-bit
151 // FILD for other targets.
152 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
155 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
157 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
158 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
161 // SSE has no i16 to fp conversion, only i32
162 if (X86ScalarSSEf32) {
163 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
164 // f32 and f64 cases are Legal, f80 case is not
165 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
167 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
168 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
172 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
175 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
176 // are Legal, f80 is custom lowered.
177 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
178 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
180 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
182 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
183 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
185 if (X86ScalarSSEf32) {
186 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
187 // f32 and f64 cases are Legal, f80 case is not
188 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
190 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
191 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
194 // Handle FP_TO_UINT by promoting the destination to a larger signed
196 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
197 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
198 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
200 if (Subtarget->is64Bit()) {
201 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
202 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
203 } else if (!UseSoftFloat) {
204 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
205 // Expand FP_TO_UINT into a select.
206 // FIXME: We would like to use a Custom expander here eventually to do
207 // the optimal thing for SSE vs. the default expansion in the legalizer.
208 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
210 // With SSE3 we can use fisttpll to convert to a signed i64; without
211 // SSE, we're stuck with a fistpll.
212 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
215 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
216 if (!X86ScalarSSEf64) {
217 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
218 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
219 if (Subtarget->is64Bit()) {
220 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
221 // Without SSE, i64->f64 goes through memory; i64->MMX is Legal.
222 if (Subtarget->hasMMX() && !DisableMMX)
223 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom);
225 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
229 // Scalar integer divide and remainder are lowered to use operations that
230 // produce two results, to match the available instructions. This exposes
231 // the two-result form to trivial CSE, which is able to combine x/y and x%y
232 // into a single instruction.
234 // Scalar integer multiply-high is also lowered to use two-result
235 // operations, to match the available instructions. However, plain multiply
236 // (low) operations are left as Legal, as there are single-result
237 // instructions for this in x86. Using the two-result multiply instructions
238 // when both high and low results are needed must be arranged by dagcombine.
239 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
240 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
241 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
242 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
243 setOperationAction(ISD::SREM , MVT::i8 , Expand);
244 setOperationAction(ISD::UREM , MVT::i8 , Expand);
245 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
246 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
247 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
248 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
249 setOperationAction(ISD::SREM , MVT::i16 , Expand);
250 setOperationAction(ISD::UREM , MVT::i16 , Expand);
251 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
252 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
253 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
254 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
255 setOperationAction(ISD::SREM , MVT::i32 , Expand);
256 setOperationAction(ISD::UREM , MVT::i32 , Expand);
257 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
258 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
259 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
260 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
261 setOperationAction(ISD::SREM , MVT::i64 , Expand);
262 setOperationAction(ISD::UREM , MVT::i64 , Expand);
264 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
265 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
266 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
267 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
268 if (Subtarget->is64Bit())
269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
273 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
274 setOperationAction(ISD::FREM , MVT::f32 , Expand);
275 setOperationAction(ISD::FREM , MVT::f64 , Expand);
276 setOperationAction(ISD::FREM , MVT::f80 , Expand);
277 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
279 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
280 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
281 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
282 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
283 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
285 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
286 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
287 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
288 if (Subtarget->is64Bit()) {
289 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
290 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
291 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
294 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
295 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
297 // These should be promoted to a larger select which is supported.
298 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
299 // X86 wants to expand cmov itself.
300 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
302 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
303 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
304 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
305 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
306 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
307 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
308 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
309 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
310 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
311 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
312 if (Subtarget->is64Bit()) {
313 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
314 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
316 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
319 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
320 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
321 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
322 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
323 if (Subtarget->is64Bit())
324 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
325 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
326 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
327 if (Subtarget->is64Bit()) {
328 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
329 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
330 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
331 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
332 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
334 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
335 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
336 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
337 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
338 if (Subtarget->is64Bit()) {
339 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
340 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
341 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
344 if (Subtarget->hasSSE1())
345 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
347 // We may not have a libcall for MEMBARRIER so we should lower this.
348 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
350 // On X86 and X86-64, atomic operations are lowered to locked instructions.
351 // Locked instructions, in turn, have implicit fence semantics (all memory
352 // operations are flushed before issuing the locked instruction, and they
353 // are not buffered), so we can fold away the common pattern of
354 // fence-atomic-fence.
355 setShouldFoldAtomicFences(true);
357 // Expand certain atomics
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
360 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
361 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
365 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
366 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
368 if (!Subtarget->is64Bit()) {
369 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
374 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
375 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
378 // FIXME - use subtarget debug flags
379 if (!Subtarget->isTargetDarwin() &&
380 !Subtarget->isTargetELF() &&
381 !Subtarget->isTargetCygMing()) {
382 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
385 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
386 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
387 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
388 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
389 if (Subtarget->is64Bit()) {
390 setExceptionPointerRegister(X86::RAX);
391 setExceptionSelectorRegister(X86::RDX);
393 setExceptionPointerRegister(X86::EAX);
394 setExceptionSelectorRegister(X86::EDX);
396 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
397 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
399 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
401 setOperationAction(ISD::TRAP, MVT::Other, Legal);
403 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
404 setOperationAction(ISD::VASTART , MVT::Other, Custom);
405 setOperationAction(ISD::VAEND , MVT::Other, Expand);
406 if (Subtarget->is64Bit()) {
407 setOperationAction(ISD::VAARG , MVT::Other, Custom);
408 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
410 setOperationAction(ISD::VAARG , MVT::Other, Expand);
411 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
414 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
415 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
416 if (Subtarget->is64Bit())
417 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
418 if (Subtarget->isTargetCygMing())
419 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
421 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
423 if (!UseSoftFloat && X86ScalarSSEf64) {
424 // f32 and f64 use SSE.
425 // Set up the FP register classes.
426 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
427 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
429 // Use ANDPD to simulate FABS.
430 setOperationAction(ISD::FABS , MVT::f64, Custom);
431 setOperationAction(ISD::FABS , MVT::f32, Custom);
433 // Use XORP to simulate FNEG.
434 setOperationAction(ISD::FNEG , MVT::f64, Custom);
435 setOperationAction(ISD::FNEG , MVT::f32, Custom);
437 // Use ANDPD and ORPD to simulate FCOPYSIGN.
438 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
439 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
441 // We don't support sin/cos/fmod
442 setOperationAction(ISD::FSIN , MVT::f64, Expand);
443 setOperationAction(ISD::FCOS , MVT::f64, Expand);
444 setOperationAction(ISD::FSIN , MVT::f32, Expand);
445 setOperationAction(ISD::FCOS , MVT::f32, Expand);
447 // Expand FP immediates into loads from the stack, except for the special
449 addLegalFPImmediate(APFloat(+0.0)); // xorpd
450 addLegalFPImmediate(APFloat(+0.0f)); // xorps
451 } else if (!UseSoftFloat && X86ScalarSSEf32) {
452 // Use SSE for f32, x87 for f64.
453 // Set up the FP register classes.
454 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
455 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
457 // Use ANDPS to simulate FABS.
458 setOperationAction(ISD::FABS , MVT::f32, Custom);
460 // Use XORP to simulate FNEG.
461 setOperationAction(ISD::FNEG , MVT::f32, Custom);
463 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
465 // Use ANDPS and ORPS to simulate FCOPYSIGN.
466 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
467 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
469 // We don't support sin/cos/fmod
470 setOperationAction(ISD::FSIN , MVT::f32, Expand);
471 setOperationAction(ISD::FCOS , MVT::f32, Expand);
473 // Special cases we handle for FP constants.
474 addLegalFPImmediate(APFloat(+0.0f)); // xorps
475 addLegalFPImmediate(APFloat(+0.0)); // FLD0
476 addLegalFPImmediate(APFloat(+1.0)); // FLD1
477 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
478 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
481 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
482 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
484 } else if (!UseSoftFloat) {
485 // f32 and f64 in x87.
486 // Set up the FP register classes.
487 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
488 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
490 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
491 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
492 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
493 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
496 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
497 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
499 addLegalFPImmediate(APFloat(+0.0)); // FLD0
500 addLegalFPImmediate(APFloat(+1.0)); // FLD1
501 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
502 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
503 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
504 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
505 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
506 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
509 // Long double always uses X87.
511 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
512 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
513 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
516 APFloat TmpFlt(+0.0);
517 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
519 addLegalFPImmediate(TmpFlt); // FLD0
521 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
522 APFloat TmpFlt2(+1.0);
523 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
525 addLegalFPImmediate(TmpFlt2); // FLD1
526 TmpFlt2.changeSign();
527 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
531 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
532 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
536 // Always use a library call for pow.
537 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
538 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
539 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
541 setOperationAction(ISD::FLOG, MVT::f80, Expand);
542 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
543 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
544 setOperationAction(ISD::FEXP, MVT::f80, Expand);
545 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
547 // First set operation action for all vector types to either promote
548 // (for widening) or expand (for scalarization). Then we will selectively
549 // turn on ones that can be effectively codegen'd.
550 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
551 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
552 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
567 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
568 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
601 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
605 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
606 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
607 setTruncStoreAction((MVT::SimpleValueType)VT,
608 (MVT::SimpleValueType)InnerVT, Expand);
609 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
610 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
611 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
614 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
615 // with -msoft-float, disable use of MMX as well.
616 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
617 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass, false);
619 // FIXME: Remove the rest of this stuff.
620 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false);
621 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
622 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
624 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
626 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
627 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
628 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
629 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
631 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
632 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
633 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
634 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
636 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
637 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
639 setOperationAction(ISD::AND, MVT::v8i8, Promote);
640 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
641 setOperationAction(ISD::AND, MVT::v4i16, Promote);
642 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
643 setOperationAction(ISD::AND, MVT::v2i32, Promote);
644 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
645 setOperationAction(ISD::AND, MVT::v1i64, Legal);
647 setOperationAction(ISD::OR, MVT::v8i8, Promote);
648 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
649 setOperationAction(ISD::OR, MVT::v4i16, Promote);
650 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
651 setOperationAction(ISD::OR, MVT::v2i32, Promote);
652 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
653 setOperationAction(ISD::OR, MVT::v1i64, Legal);
655 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
656 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
657 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
658 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
659 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
660 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
661 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
663 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
664 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
665 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
666 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
667 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
668 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
669 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
671 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
672 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
673 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
674 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
676 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
677 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
678 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
679 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
681 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
682 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
683 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
685 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
687 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
688 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
689 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
690 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
691 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
692 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
693 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
695 if (!X86ScalarSSEf64 && Subtarget->is64Bit()) {
696 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom);
697 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom);
698 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom);
699 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom);
703 if (!UseSoftFloat && Subtarget->hasSSE1()) {
704 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
706 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
707 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
708 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
709 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
710 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
711 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
712 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
713 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
714 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
715 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
716 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
717 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
720 if (!UseSoftFloat && Subtarget->hasSSE2()) {
721 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
723 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
724 // registers cannot be used even for integer operations.
725 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
726 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
727 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
728 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
730 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
731 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
732 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
733 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
734 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
735 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
736 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
737 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
738 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
739 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
740 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
741 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
742 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
743 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
744 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
745 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
747 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
748 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
749 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
750 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
753 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
754 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
755 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
756 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
758 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
759 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
760 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
764 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
765 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
766 EVT VT = (MVT::SimpleValueType)i;
767 // Do not attempt to custom lower non-power-of-2 vectors
768 if (!isPowerOf2_32(VT.getVectorNumElements()))
770 // Do not attempt to custom lower non-128-bit vectors
771 if (!VT.is128BitVector())
773 setOperationAction(ISD::BUILD_VECTOR,
774 VT.getSimpleVT().SimpleTy, Custom);
775 setOperationAction(ISD::VECTOR_SHUFFLE,
776 VT.getSimpleVT().SimpleTy, Custom);
777 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
778 VT.getSimpleVT().SimpleTy, Custom);
781 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
782 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
783 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
785 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
788 if (Subtarget->is64Bit()) {
789 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
790 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
793 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
794 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
795 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
798 // Do not attempt to promote non-128-bit vectors
799 if (!VT.is128BitVector())
802 setOperationAction(ISD::AND, SVT, Promote);
803 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
804 setOperationAction(ISD::OR, SVT, Promote);
805 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
806 setOperationAction(ISD::XOR, SVT, Promote);
807 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
808 setOperationAction(ISD::LOAD, SVT, Promote);
809 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
810 setOperationAction(ISD::SELECT, SVT, Promote);
811 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
814 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
816 // Custom lower v2i64 and v2f64 selects.
817 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
818 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
819 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
820 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
822 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
823 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
824 if (!DisableMMX && Subtarget->hasMMX()) {
825 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
826 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
830 if (Subtarget->hasSSE41()) {
831 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
832 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
833 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
834 setOperationAction(ISD::FRINT, MVT::f32, Legal);
835 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
836 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
837 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
838 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
839 setOperationAction(ISD::FRINT, MVT::f64, Legal);
840 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
842 // FIXME: Do we need to handle scalar-to-vector here?
843 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
845 // Can turn SHL into an integer multiply.
846 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
847 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
849 // i8 and i16 vectors are custom , because the source register and source
850 // source memory operand types are not the same width. f32 vectors are
851 // custom since the immediate controlling the insert encodes additional
853 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
854 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
855 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
856 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
858 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
859 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
860 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
861 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
863 if (Subtarget->is64Bit()) {
864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
869 if (Subtarget->hasSSE42()) {
870 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
873 if (!UseSoftFloat && Subtarget->hasAVX()) {
874 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
875 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
876 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
877 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
878 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
880 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
881 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
882 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
883 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
884 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
885 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
886 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
887 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
888 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
889 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
890 setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
891 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
892 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
893 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
894 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
896 // Operations to consider commented out -v16i16 v32i8
897 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
898 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
899 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
900 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
901 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
902 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
903 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
904 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
905 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
906 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
907 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
908 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
909 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
910 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
912 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
913 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
914 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
915 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
917 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
918 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
919 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
920 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
921 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
923 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
924 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
925 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
926 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
927 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
928 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
931 // Not sure we want to do this since there are no 256-bit integer
934 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
935 // This includes 256-bit vectors
936 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
937 EVT VT = (MVT::SimpleValueType)i;
939 // Do not attempt to custom lower non-power-of-2 vectors
940 if (!isPowerOf2_32(VT.getVectorNumElements()))
943 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
944 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
945 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
948 if (Subtarget->is64Bit()) {
949 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
950 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
955 // Not sure we want to do this since there are no 256-bit integer
958 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
959 // Including 256-bit vectors
960 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
961 EVT VT = (MVT::SimpleValueType)i;
963 if (!VT.is256BitVector()) {
966 setOperationAction(ISD::AND, VT, Promote);
967 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
968 setOperationAction(ISD::OR, VT, Promote);
969 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
970 setOperationAction(ISD::XOR, VT, Promote);
971 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
972 setOperationAction(ISD::LOAD, VT, Promote);
973 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
974 setOperationAction(ISD::SELECT, VT, Promote);
975 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
978 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
982 // We want to custom lower some of our intrinsics.
983 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
985 // Add/Sub/Mul with overflow operations are custom lowered.
986 setOperationAction(ISD::SADDO, MVT::i32, Custom);
987 setOperationAction(ISD::UADDO, MVT::i32, Custom);
988 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
989 setOperationAction(ISD::USUBO, MVT::i32, Custom);
990 setOperationAction(ISD::SMULO, MVT::i32, Custom);
992 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
993 // handle type legalization for these operations here.
995 // FIXME: We really should do custom legalization for addition and
996 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
997 // than generic legalization for 64-bit multiplication-with-overflow, though.
998 if (Subtarget->is64Bit()) {
999 setOperationAction(ISD::SADDO, MVT::i64, Custom);
1000 setOperationAction(ISD::UADDO, MVT::i64, Custom);
1001 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
1002 setOperationAction(ISD::USUBO, MVT::i64, Custom);
1003 setOperationAction(ISD::SMULO, MVT::i64, Custom);
1006 if (!Subtarget->is64Bit()) {
1007 // These libcalls are not available in 32-bit.
1008 setLibcallName(RTLIB::SHL_I128, 0);
1009 setLibcallName(RTLIB::SRL_I128, 0);
1010 setLibcallName(RTLIB::SRA_I128, 0);
1013 // We have target-specific dag combine patterns for the following nodes:
1014 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1015 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1016 setTargetDAGCombine(ISD::BUILD_VECTOR);
1017 setTargetDAGCombine(ISD::SELECT);
1018 setTargetDAGCombine(ISD::SHL);
1019 setTargetDAGCombine(ISD::SRA);
1020 setTargetDAGCombine(ISD::SRL);
1021 setTargetDAGCombine(ISD::OR);
1022 setTargetDAGCombine(ISD::STORE);
1023 setTargetDAGCombine(ISD::ZERO_EXTEND);
1024 if (Subtarget->is64Bit())
1025 setTargetDAGCombine(ISD::MUL);
1027 computeRegisterProperties();
1029 // FIXME: These should be based on subtarget info. Plus, the values should
1030 // be smaller when we are in optimizing for size mode.
1031 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1032 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1033 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1034 setPrefLoopAlignment(16);
1035 benefitFromCodePlacementOpt = true;
1039 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1044 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1045 /// the desired ByVal argument alignment.
1046 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1049 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1050 if (VTy->getBitWidth() == 128)
1052 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1053 unsigned EltAlign = 0;
1054 getMaxByValAlign(ATy->getElementType(), EltAlign);
1055 if (EltAlign > MaxAlign)
1056 MaxAlign = EltAlign;
1057 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1058 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1059 unsigned EltAlign = 0;
1060 getMaxByValAlign(STy->getElementType(i), EltAlign);
1061 if (EltAlign > MaxAlign)
1062 MaxAlign = EltAlign;
1070 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1071 /// function arguments in the caller parameter area. For X86, aggregates
1072 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1073 /// are at 4-byte boundaries.
1074 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1075 if (Subtarget->is64Bit()) {
1076 // Max of 8 and alignment of type.
1077 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1084 if (Subtarget->hasSSE1())
1085 getMaxByValAlign(Ty, Align);
1089 /// getOptimalMemOpType - Returns the target specific optimal type for load
1090 /// and store operations as a result of memset, memcpy, and memmove
1091 /// lowering. If DstAlign is zero that means it's safe to destination
1092 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1093 /// means there isn't a need to check it against alignment requirement,
1094 /// probably because the source does not need to be loaded. If
1095 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1096 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1097 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1098 /// constant so it does not need to be loaded.
1099 /// It returns EVT::Other if the type should be determined using generic
1100 /// target-independent logic.
1102 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1103 unsigned DstAlign, unsigned SrcAlign,
1104 bool NonScalarIntSafe,
1106 MachineFunction &MF) const {
1107 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1108 // linux. This is because the stack realignment code can't handle certain
1109 // cases like PR2962. This should be removed when PR2962 is fixed.
1110 const Function *F = MF.getFunction();
1111 if (NonScalarIntSafe &&
1112 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1114 (Subtarget->isUnalignedMemAccessFast() ||
1115 ((DstAlign == 0 || DstAlign >= 16) &&
1116 (SrcAlign == 0 || SrcAlign >= 16))) &&
1117 Subtarget->getStackAlignment() >= 16) {
1118 if (Subtarget->hasSSE2())
1120 if (Subtarget->hasSSE1())
1122 } else if (!MemcpyStrSrc && Size >= 8 &&
1123 !Subtarget->is64Bit() &&
1124 Subtarget->getStackAlignment() >= 8 &&
1125 Subtarget->hasSSE2()) {
1126 // Do not use f64 to lower memcpy if source is string constant. It's
1127 // better to use i32 to avoid the loads.
1131 if (Subtarget->is64Bit() && Size >= 8)
1136 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1137 /// current function. The returned value is a member of the
1138 /// MachineJumpTableInfo::JTEntryKind enum.
1139 unsigned X86TargetLowering::getJumpTableEncoding() const {
1140 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1142 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1143 Subtarget->isPICStyleGOT())
1144 return MachineJumpTableInfo::EK_Custom32;
1146 // Otherwise, use the normal jump table encoding heuristics.
1147 return TargetLowering::getJumpTableEncoding();
1150 /// getPICBaseSymbol - Return the X86-32 PIC base.
1152 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1153 MCContext &Ctx) const {
1154 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1155 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1156 Twine(MF->getFunctionNumber())+"$pb");
1161 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1162 const MachineBasicBlock *MBB,
1163 unsigned uid,MCContext &Ctx) const{
1164 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1165 Subtarget->isPICStyleGOT());
1166 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1168 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1169 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1172 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1174 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1175 SelectionDAG &DAG) const {
1176 if (!Subtarget->is64Bit())
1177 // This doesn't have DebugLoc associated with it, but is not really the
1178 // same as a Register.
1179 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1183 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1184 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1186 const MCExpr *X86TargetLowering::
1187 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1188 MCContext &Ctx) const {
1189 // X86-64 uses RIP relative addressing based on the jump table label.
1190 if (Subtarget->isPICStyleRIPRel())
1191 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1193 // Otherwise, the reference is relative to the PIC base.
1194 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1197 /// getFunctionAlignment - Return the Log2 alignment of this function.
1198 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1199 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1202 std::pair<const TargetRegisterClass*, uint8_t>
1203 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1204 const TargetRegisterClass *RRC = 0;
1206 switch (VT.getSimpleVT().SimpleTy) {
1208 return TargetLowering::findRepresentativeClass(VT);
1209 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1210 RRC = (Subtarget->is64Bit()
1211 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1213 case MVT::v8i8: case MVT::v4i16:
1214 case MVT::v2i32: case MVT::v1i64:
1215 RRC = X86::VR64RegisterClass;
1217 case MVT::f32: case MVT::f64:
1218 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1219 case MVT::v4f32: case MVT::v2f64:
1220 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1222 RRC = X86::VR128RegisterClass;
1225 return std::make_pair(RRC, Cost);
1229 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
1230 MachineFunction &MF) const {
1231 unsigned FPDiff = RegInfo->hasFP(MF) ? 1 : 0;
1232 switch (RC->getID()) {
1235 case X86::GR32RegClassID:
1237 case X86::GR64RegClassID:
1239 case X86::VR128RegClassID:
1240 return Subtarget->is64Bit() ? 10 : 4;
1241 case X86::VR64RegClassID:
1246 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1247 unsigned &Offset) const {
1248 if (!Subtarget->isTargetLinux())
1251 if (Subtarget->is64Bit()) {
1252 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1254 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1267 //===----------------------------------------------------------------------===//
1268 // Return Value Calling Convention Implementation
1269 //===----------------------------------------------------------------------===//
1271 #include "X86GenCallingConv.inc"
1274 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1275 const SmallVectorImpl<ISD::OutputArg> &Outs,
1276 LLVMContext &Context) const {
1277 SmallVector<CCValAssign, 16> RVLocs;
1278 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1280 return CCInfo.CheckReturn(Outs, RetCC_X86);
1284 X86TargetLowering::LowerReturn(SDValue Chain,
1285 CallingConv::ID CallConv, bool isVarArg,
1286 const SmallVectorImpl<ISD::OutputArg> &Outs,
1287 const SmallVectorImpl<SDValue> &OutVals,
1288 DebugLoc dl, SelectionDAG &DAG) const {
1289 MachineFunction &MF = DAG.getMachineFunction();
1290 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1292 SmallVector<CCValAssign, 16> RVLocs;
1293 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1294 RVLocs, *DAG.getContext());
1295 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1297 // Add the regs to the liveout set for the function.
1298 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1299 for (unsigned i = 0; i != RVLocs.size(); ++i)
1300 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1301 MRI.addLiveOut(RVLocs[i].getLocReg());
1305 SmallVector<SDValue, 6> RetOps;
1306 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1307 // Operand #1 = Bytes To Pop
1308 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1311 // Copy the result values into the output registers.
1312 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1313 CCValAssign &VA = RVLocs[i];
1314 assert(VA.isRegLoc() && "Can only return in registers!");
1315 SDValue ValToCopy = OutVals[i];
1316 EVT ValVT = ValToCopy.getValueType();
1318 // If this is x86-64, and we disabled SSE, we can't return FP values
1319 if ((ValVT == MVT::f32 || ValVT == MVT::f64) &&
1320 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1321 report_fatal_error("SSE register return with SSE disabled");
1323 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1324 // llvm-gcc has never done it right and no one has noticed, so this
1325 // should be OK for now.
1326 if (ValVT == MVT::f64 &&
1327 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1328 report_fatal_error("SSE2 register return with SSE2 disabled");
1330 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1331 // the RET instruction and handled by the FP Stackifier.
1332 if (VA.getLocReg() == X86::ST0 ||
1333 VA.getLocReg() == X86::ST1) {
1334 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1335 // change the value to the FP stack register class.
1336 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1337 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1338 RetOps.push_back(ValToCopy);
1339 // Don't emit a copytoreg.
1343 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1344 // which is returned in RAX / RDX.
1345 if (Subtarget->is64Bit()) {
1346 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1347 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1348 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1349 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1352 // If we don't have SSE2 available, convert to v4f32 so the generated
1353 // register is legal.
1354 if (!Subtarget->hasSSE2())
1355 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,ValToCopy);
1360 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1361 Flag = Chain.getValue(1);
1364 // The x86-64 ABI for returning structs by value requires that we copy
1365 // the sret argument into %rax for the return. We saved the argument into
1366 // a virtual register in the entry block, so now we copy the value out
1368 if (Subtarget->is64Bit() &&
1369 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1370 MachineFunction &MF = DAG.getMachineFunction();
1371 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1372 unsigned Reg = FuncInfo->getSRetReturnReg();
1374 "SRetReturnReg should have been set in LowerFormalArguments().");
1375 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1377 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1378 Flag = Chain.getValue(1);
1380 // RAX now acts like a return value.
1381 MRI.addLiveOut(X86::RAX);
1384 RetOps[0] = Chain; // Update chain.
1386 // Add the flag if we have it.
1388 RetOps.push_back(Flag);
1390 return DAG.getNode(X86ISD::RET_FLAG, dl,
1391 MVT::Other, &RetOps[0], RetOps.size());
1394 /// LowerCallResult - Lower the result values of a call into the
1395 /// appropriate copies out of appropriate physical registers.
1398 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1399 CallingConv::ID CallConv, bool isVarArg,
1400 const SmallVectorImpl<ISD::InputArg> &Ins,
1401 DebugLoc dl, SelectionDAG &DAG,
1402 SmallVectorImpl<SDValue> &InVals) const {
1404 // Assign locations to each value returned by this call.
1405 SmallVector<CCValAssign, 16> RVLocs;
1406 bool Is64Bit = Subtarget->is64Bit();
1407 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1408 RVLocs, *DAG.getContext());
1409 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1411 // Copy all of the result registers out of their specified physreg.
1412 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1413 CCValAssign &VA = RVLocs[i];
1414 EVT CopyVT = VA.getValVT();
1416 // If this is x86-64, and we disabled SSE, we can't return FP values
1417 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1418 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1419 report_fatal_error("SSE register return with SSE disabled");
1424 // If this is a call to a function that returns an fp value on the floating
1425 // point stack, we must guarantee the the value is popped from the stack, so
1426 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1427 // if the return value is not used. We use the FpGET_ST0 instructions
1429 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1430 // If we prefer to use the value in xmm registers, copy it out as f80 and
1431 // use a truncate to move it from fp stack reg to xmm reg.
1432 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1433 bool isST0 = VA.getLocReg() == X86::ST0;
1435 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1436 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1437 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1438 SDValue Ops[] = { Chain, InFlag };
1439 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag,
1441 Val = Chain.getValue(0);
1443 // Round the f80 to the right size, which also moves it to the appropriate
1445 if (CopyVT != VA.getValVT())
1446 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1447 // This truncation won't change the value.
1448 DAG.getIntPtrConstant(1));
1449 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1450 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1451 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1452 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1453 MVT::v2i64, InFlag).getValue(1);
1454 Val = Chain.getValue(0);
1455 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1456 Val, DAG.getConstant(0, MVT::i64));
1458 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1459 MVT::i64, InFlag).getValue(1);
1460 Val = Chain.getValue(0);
1462 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1464 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1465 CopyVT, InFlag).getValue(1);
1466 Val = Chain.getValue(0);
1468 InFlag = Chain.getValue(2);
1469 InVals.push_back(Val);
1476 //===----------------------------------------------------------------------===//
1477 // C & StdCall & Fast Calling Convention implementation
1478 //===----------------------------------------------------------------------===//
1479 // StdCall calling convention seems to be standard for many Windows' API
1480 // routines and around. It differs from C calling convention just a little:
1481 // callee should clean up the stack, not caller. Symbols should be also
1482 // decorated in some fancy way :) It doesn't support any vector arguments.
1483 // For info on fast calling convention see Fast Calling Convention (tail call)
1484 // implementation LowerX86_32FastCCCallTo.
1486 /// CallIsStructReturn - Determines whether a call uses struct return
1488 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1492 return Outs[0].Flags.isSRet();
1495 /// ArgsAreStructReturn - Determines whether a function uses struct
1496 /// return semantics.
1498 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1502 return Ins[0].Flags.isSRet();
1505 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1506 /// given CallingConvention value.
1507 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1508 if (Subtarget->is64Bit()) {
1509 if (CC == CallingConv::GHC)
1510 return CC_X86_64_GHC;
1511 else if (Subtarget->isTargetWin64())
1512 return CC_X86_Win64_C;
1517 if (CC == CallingConv::X86_FastCall)
1518 return CC_X86_32_FastCall;
1519 else if (CC == CallingConv::X86_ThisCall)
1520 return CC_X86_32_ThisCall;
1521 else if (CC == CallingConv::Fast)
1522 return CC_X86_32_FastCC;
1523 else if (CC == CallingConv::GHC)
1524 return CC_X86_32_GHC;
1529 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1530 /// by "Src" to address "Dst" with size and alignment information specified by
1531 /// the specific parameter attribute. The copy will be passed as a byval
1532 /// function parameter.
1534 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1535 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1537 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1538 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1539 /*isVolatile*/false, /*AlwaysInline=*/true,
1543 /// IsTailCallConvention - Return true if the calling convention is one that
1544 /// supports tail call optimization.
1545 static bool IsTailCallConvention(CallingConv::ID CC) {
1546 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1549 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1550 /// a tailcall target by changing its ABI.
1551 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1552 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1556 X86TargetLowering::LowerMemArgument(SDValue Chain,
1557 CallingConv::ID CallConv,
1558 const SmallVectorImpl<ISD::InputArg> &Ins,
1559 DebugLoc dl, SelectionDAG &DAG,
1560 const CCValAssign &VA,
1561 MachineFrameInfo *MFI,
1563 // Create the nodes corresponding to a load from this parameter slot.
1564 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1565 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1566 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1569 // If value is passed by pointer we have address passed instead of the value
1571 if (VA.getLocInfo() == CCValAssign::Indirect)
1572 ValVT = VA.getLocVT();
1574 ValVT = VA.getValVT();
1576 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1577 // changed with more analysis.
1578 // In case of tail call optimization mark all arguments mutable. Since they
1579 // could be overwritten by lowering of arguments in case of a tail call.
1580 if (Flags.isByVal()) {
1581 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1582 VA.getLocMemOffset(), isImmutable);
1583 return DAG.getFrameIndex(FI, getPointerTy());
1585 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1586 VA.getLocMemOffset(), isImmutable);
1587 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1588 return DAG.getLoad(ValVT, dl, Chain, FIN,
1589 PseudoSourceValue::getFixedStack(FI), 0,
1595 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1596 CallingConv::ID CallConv,
1598 const SmallVectorImpl<ISD::InputArg> &Ins,
1601 SmallVectorImpl<SDValue> &InVals)
1603 MachineFunction &MF = DAG.getMachineFunction();
1604 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1606 const Function* Fn = MF.getFunction();
1607 if (Fn->hasExternalLinkage() &&
1608 Subtarget->isTargetCygMing() &&
1609 Fn->getName() == "main")
1610 FuncInfo->setForceFramePointer(true);
1612 MachineFrameInfo *MFI = MF.getFrameInfo();
1613 bool Is64Bit = Subtarget->is64Bit();
1614 bool IsWin64 = Subtarget->isTargetWin64();
1616 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1617 "Var args not supported with calling convention fastcc or ghc");
1619 // Assign locations to all of the incoming arguments.
1620 SmallVector<CCValAssign, 16> ArgLocs;
1621 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1622 ArgLocs, *DAG.getContext());
1623 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1625 unsigned LastVal = ~0U;
1627 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1628 CCValAssign &VA = ArgLocs[i];
1629 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1631 assert(VA.getValNo() != LastVal &&
1632 "Don't support value assigned to multiple locs yet");
1633 LastVal = VA.getValNo();
1635 if (VA.isRegLoc()) {
1636 EVT RegVT = VA.getLocVT();
1637 TargetRegisterClass *RC = NULL;
1638 if (RegVT == MVT::i32)
1639 RC = X86::GR32RegisterClass;
1640 else if (Is64Bit && RegVT == MVT::i64)
1641 RC = X86::GR64RegisterClass;
1642 else if (RegVT == MVT::f32)
1643 RC = X86::FR32RegisterClass;
1644 else if (RegVT == MVT::f64)
1645 RC = X86::FR64RegisterClass;
1646 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1647 RC = X86::VR256RegisterClass;
1648 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1649 RC = X86::VR128RegisterClass;
1650 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1651 RC = X86::VR64RegisterClass;
1653 llvm_unreachable("Unknown argument type!");
1655 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1656 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1658 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1659 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1661 if (VA.getLocInfo() == CCValAssign::SExt)
1662 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1663 DAG.getValueType(VA.getValVT()));
1664 else if (VA.getLocInfo() == CCValAssign::ZExt)
1665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1666 DAG.getValueType(VA.getValVT()));
1667 else if (VA.getLocInfo() == CCValAssign::BCvt)
1668 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1670 if (VA.isExtInLoc()) {
1671 // Handle MMX values passed in XMM regs.
1672 if (RegVT.isVector()) {
1673 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1674 ArgValue, DAG.getConstant(0, MVT::i64));
1675 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1677 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1680 assert(VA.isMemLoc());
1681 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1684 // If value is passed via pointer - do a load.
1685 if (VA.getLocInfo() == CCValAssign::Indirect)
1686 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0,
1689 InVals.push_back(ArgValue);
1692 // The x86-64 ABI for returning structs by value requires that we copy
1693 // the sret argument into %rax for the return. Save the argument into
1694 // a virtual register so that we can access it from the return points.
1695 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1696 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1697 unsigned Reg = FuncInfo->getSRetReturnReg();
1699 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1700 FuncInfo->setSRetReturnReg(Reg);
1702 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1703 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1706 unsigned StackSize = CCInfo.getNextStackOffset();
1707 // Align stack specially for tail calls.
1708 if (FuncIsMadeTailCallSafe(CallConv))
1709 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1711 // If the function takes variable number of arguments, make a frame index for
1712 // the start of the first vararg value... for expansion of llvm.va_start.
1714 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1715 CallConv != CallingConv::X86_ThisCall)) {
1716 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1719 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1721 // FIXME: We should really autogenerate these arrays
1722 static const unsigned GPR64ArgRegsWin64[] = {
1723 X86::RCX, X86::RDX, X86::R8, X86::R9
1725 static const unsigned XMMArgRegsWin64[] = {
1726 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1728 static const unsigned GPR64ArgRegs64Bit[] = {
1729 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1731 static const unsigned XMMArgRegs64Bit[] = {
1732 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1733 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1735 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1738 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1739 GPR64ArgRegs = GPR64ArgRegsWin64;
1740 XMMArgRegs = XMMArgRegsWin64;
1742 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1743 GPR64ArgRegs = GPR64ArgRegs64Bit;
1744 XMMArgRegs = XMMArgRegs64Bit;
1746 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1748 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1751 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1752 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1753 "SSE register cannot be used when SSE is disabled!");
1754 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1755 "SSE register cannot be used when SSE is disabled!");
1756 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1757 // Kernel mode asks for SSE to be disabled, so don't push them
1759 TotalNumXMMRegs = 0;
1761 // For X86-64, if there are vararg parameters that are passed via
1762 // registers, then we must store them to their spots on the stack so they
1763 // may be loaded by deferencing the result of va_next.
1764 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1765 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1766 FuncInfo->setRegSaveFrameIndex(
1767 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1770 // Store the integer parameter registers.
1771 SmallVector<SDValue, 8> MemOps;
1772 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1774 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1775 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1776 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1777 DAG.getIntPtrConstant(Offset));
1778 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1779 X86::GR64RegisterClass);
1780 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1782 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1783 PseudoSourceValue::getFixedStack(
1784 FuncInfo->getRegSaveFrameIndex()),
1785 Offset, false, false, 0);
1786 MemOps.push_back(Store);
1790 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1791 // Now store the XMM (fp + vector) parameter registers.
1792 SmallVector<SDValue, 11> SaveXMMOps;
1793 SaveXMMOps.push_back(Chain);
1795 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1796 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1797 SaveXMMOps.push_back(ALVal);
1799 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1800 FuncInfo->getRegSaveFrameIndex()));
1801 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1802 FuncInfo->getVarArgsFPOffset()));
1804 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1805 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1806 X86::VR128RegisterClass);
1807 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1808 SaveXMMOps.push_back(Val);
1810 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1812 &SaveXMMOps[0], SaveXMMOps.size()));
1815 if (!MemOps.empty())
1816 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1817 &MemOps[0], MemOps.size());
1821 // Some CCs need callee pop.
1822 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1823 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1825 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1826 // If this is an sret function, the return should pop the hidden pointer.
1827 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1828 FuncInfo->setBytesToPopOnReturn(4);
1832 // RegSaveFrameIndex is X86-64 only.
1833 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1834 if (CallConv == CallingConv::X86_FastCall ||
1835 CallConv == CallingConv::X86_ThisCall)
1836 // fastcc functions can't have varargs.
1837 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1844 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1845 SDValue StackPtr, SDValue Arg,
1846 DebugLoc dl, SelectionDAG &DAG,
1847 const CCValAssign &VA,
1848 ISD::ArgFlagsTy Flags) const {
1849 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1850 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1851 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1852 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1853 if (Flags.isByVal()) {
1854 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1856 return DAG.getStore(Chain, dl, Arg, PtrOff,
1857 PseudoSourceValue::getStack(), LocMemOffset,
1861 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1862 /// optimization is performed and it is required.
1864 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1865 SDValue &OutRetAddr, SDValue Chain,
1866 bool IsTailCall, bool Is64Bit,
1867 int FPDiff, DebugLoc dl) const {
1868 // Adjust the Return address stack slot.
1869 EVT VT = getPointerTy();
1870 OutRetAddr = getReturnAddressFrameIndex(DAG);
1872 // Load the "old" Return address.
1873 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0, false, false, 0);
1874 return SDValue(OutRetAddr.getNode(), 1);
1877 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1878 /// optimization is performed and it is required (FPDiff!=0).
1880 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1881 SDValue Chain, SDValue RetAddrFrIdx,
1882 bool Is64Bit, int FPDiff, DebugLoc dl) {
1883 // Store the return address to the appropriate stack slot.
1884 if (!FPDiff) return Chain;
1885 // Calculate the new stack slot for the return address.
1886 int SlotSize = Is64Bit ? 8 : 4;
1887 int NewReturnAddrFI =
1888 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1889 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1890 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1891 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1892 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0,
1898 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1899 CallingConv::ID CallConv, bool isVarArg,
1901 const SmallVectorImpl<ISD::OutputArg> &Outs,
1902 const SmallVectorImpl<SDValue> &OutVals,
1903 const SmallVectorImpl<ISD::InputArg> &Ins,
1904 DebugLoc dl, SelectionDAG &DAG,
1905 SmallVectorImpl<SDValue> &InVals) const {
1906 MachineFunction &MF = DAG.getMachineFunction();
1907 bool Is64Bit = Subtarget->is64Bit();
1908 bool IsStructRet = CallIsStructReturn(Outs);
1909 bool IsSibcall = false;
1912 // Check if it's really possible to do a tail call.
1913 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1914 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1915 Outs, OutVals, Ins, DAG);
1917 // Sibcalls are automatically detected tailcalls which do not require
1919 if (!GuaranteedTailCallOpt && isTailCall)
1926 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1927 "Var args not supported with calling convention fastcc or ghc");
1929 // Analyze operands of the call, assigning locations to each operand.
1930 SmallVector<CCValAssign, 16> ArgLocs;
1931 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1932 ArgLocs, *DAG.getContext());
1933 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1935 // Get a count of how many bytes are to be pushed on the stack.
1936 unsigned NumBytes = CCInfo.getNextStackOffset();
1938 // This is a sibcall. The memory operands are available in caller's
1939 // own caller's stack.
1941 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1942 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1945 if (isTailCall && !IsSibcall) {
1946 // Lower arguments at fp - stackoffset + fpdiff.
1947 unsigned NumBytesCallerPushed =
1948 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1949 FPDiff = NumBytesCallerPushed - NumBytes;
1951 // Set the delta of movement of the returnaddr stackslot.
1952 // But only set if delta is greater than previous delta.
1953 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1954 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1958 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1960 SDValue RetAddrFrIdx;
1961 // Load return adress for tail calls.
1962 if (isTailCall && FPDiff)
1963 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1964 Is64Bit, FPDiff, dl);
1966 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1967 SmallVector<SDValue, 8> MemOpChains;
1970 // Walk the register/memloc assignments, inserting copies/loads. In the case
1971 // of tail call optimization arguments are handle later.
1972 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1973 CCValAssign &VA = ArgLocs[i];
1974 EVT RegVT = VA.getLocVT();
1975 SDValue Arg = OutVals[i];
1976 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1977 bool isByVal = Flags.isByVal();
1979 // Promote the value if needed.
1980 switch (VA.getLocInfo()) {
1981 default: llvm_unreachable("Unknown loc info!");
1982 case CCValAssign::Full: break;
1983 case CCValAssign::SExt:
1984 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1986 case CCValAssign::ZExt:
1987 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1989 case CCValAssign::AExt:
1990 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1991 // Special case: passing MMX values in XMM registers.
1992 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1993 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1994 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1996 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1998 case CCValAssign::BCvt:
1999 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
2001 case CCValAssign::Indirect: {
2002 // Store the argument.
2003 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2004 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2005 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2006 PseudoSourceValue::getFixedStack(FI), 0,
2013 if (VA.isRegLoc()) {
2014 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2015 if (isVarArg && Subtarget->isTargetWin64()) {
2016 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2017 // shadow reg if callee is a varargs function.
2018 unsigned ShadowReg = 0;
2019 switch (VA.getLocReg()) {
2020 case X86::XMM0: ShadowReg = X86::RCX; break;
2021 case X86::XMM1: ShadowReg = X86::RDX; break;
2022 case X86::XMM2: ShadowReg = X86::R8; break;
2023 case X86::XMM3: ShadowReg = X86::R9; break;
2026 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2028 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2029 assert(VA.isMemLoc());
2030 if (StackPtr.getNode() == 0)
2031 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2032 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2033 dl, DAG, VA, Flags));
2037 if (!MemOpChains.empty())
2038 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2039 &MemOpChains[0], MemOpChains.size());
2041 // Build a sequence of copy-to-reg nodes chained together with token chain
2042 // and flag operands which copy the outgoing args into registers.
2044 // Tail call byval lowering might overwrite argument registers so in case of
2045 // tail call optimization the copies to registers are lowered later.
2047 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2048 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2049 RegsToPass[i].second, InFlag);
2050 InFlag = Chain.getValue(1);
2053 if (Subtarget->isPICStyleGOT()) {
2054 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2057 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2058 DAG.getNode(X86ISD::GlobalBaseReg,
2059 DebugLoc(), getPointerTy()),
2061 InFlag = Chain.getValue(1);
2063 // If we are tail calling and generating PIC/GOT style code load the
2064 // address of the callee into ECX. The value in ecx is used as target of
2065 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2066 // for tail calls on PIC/GOT architectures. Normally we would just put the
2067 // address of GOT into ebx and then call target@PLT. But for tail calls
2068 // ebx would be restored (since ebx is callee saved) before jumping to the
2071 // Note: The actual moving to ECX is done further down.
2072 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2073 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2074 !G->getGlobal()->hasProtectedVisibility())
2075 Callee = LowerGlobalAddress(Callee, DAG);
2076 else if (isa<ExternalSymbolSDNode>(Callee))
2077 Callee = LowerExternalSymbol(Callee, DAG);
2081 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
2082 // From AMD64 ABI document:
2083 // For calls that may call functions that use varargs or stdargs
2084 // (prototype-less calls or calls to functions containing ellipsis (...) in
2085 // the declaration) %al is used as hidden argument to specify the number
2086 // of SSE registers used. The contents of %al do not need to match exactly
2087 // the number of registers, but must be an ubound on the number of SSE
2088 // registers used and is in the range 0 - 8 inclusive.
2090 // Count the number of XMM registers allocated.
2091 static const unsigned XMMArgRegs[] = {
2092 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2093 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2095 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2096 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2097 && "SSE registers cannot be used when SSE is disabled");
2099 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2100 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2101 InFlag = Chain.getValue(1);
2105 // For tail calls lower the arguments to the 'real' stack slot.
2107 // Force all the incoming stack arguments to be loaded from the stack
2108 // before any new outgoing arguments are stored to the stack, because the
2109 // outgoing stack slots may alias the incoming argument stack slots, and
2110 // the alias isn't otherwise explicit. This is slightly more conservative
2111 // than necessary, because it means that each store effectively depends
2112 // on every argument instead of just those arguments it would clobber.
2113 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2115 SmallVector<SDValue, 8> MemOpChains2;
2118 // Do not flag preceeding copytoreg stuff together with the following stuff.
2120 if (GuaranteedTailCallOpt) {
2121 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2122 CCValAssign &VA = ArgLocs[i];
2125 assert(VA.isMemLoc());
2126 SDValue Arg = OutVals[i];
2127 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2128 // Create frame index.
2129 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2130 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2131 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2132 FIN = DAG.getFrameIndex(FI, getPointerTy());
2134 if (Flags.isByVal()) {
2135 // Copy relative to framepointer.
2136 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2137 if (StackPtr.getNode() == 0)
2138 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2140 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2142 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2146 // Store relative to framepointer.
2147 MemOpChains2.push_back(
2148 DAG.getStore(ArgChain, dl, Arg, FIN,
2149 PseudoSourceValue::getFixedStack(FI), 0,
2155 if (!MemOpChains2.empty())
2156 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2157 &MemOpChains2[0], MemOpChains2.size());
2159 // Copy arguments to their registers.
2160 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2161 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2162 RegsToPass[i].second, InFlag);
2163 InFlag = Chain.getValue(1);
2167 // Store the return address to the appropriate stack slot.
2168 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2172 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2173 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2174 // In the 64-bit large code model, we have to make all calls
2175 // through a register, since the call instruction's 32-bit
2176 // pc-relative offset may not be large enough to hold the whole
2178 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2179 // If the callee is a GlobalAddress node (quite common, every direct call
2180 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2183 // We should use extra load for direct calls to dllimported functions in
2185 const GlobalValue *GV = G->getGlobal();
2186 if (!GV->hasDLLImportLinkage()) {
2187 unsigned char OpFlags = 0;
2189 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2190 // external symbols most go through the PLT in PIC mode. If the symbol
2191 // has hidden or protected visibility, or if it is static or local, then
2192 // we don't need to use the PLT - we can directly call it.
2193 if (Subtarget->isTargetELF() &&
2194 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2195 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2196 OpFlags = X86II::MO_PLT;
2197 } else if (Subtarget->isPICStyleStubAny() &&
2198 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2199 Subtarget->getDarwinVers() < 9) {
2200 // PC-relative references to external symbols should go through $stub,
2201 // unless we're building with the leopard linker or later, which
2202 // automatically synthesizes these stubs.
2203 OpFlags = X86II::MO_DARWIN_STUB;
2206 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2207 G->getOffset(), OpFlags);
2209 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2210 unsigned char OpFlags = 0;
2212 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2213 // symbols should go through the PLT.
2214 if (Subtarget->isTargetELF() &&
2215 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2216 OpFlags = X86II::MO_PLT;
2217 } else if (Subtarget->isPICStyleStubAny() &&
2218 Subtarget->getDarwinVers() < 9) {
2219 // PC-relative references to external symbols should go through $stub,
2220 // unless we're building with the leopard linker or later, which
2221 // automatically synthesizes these stubs.
2222 OpFlags = X86II::MO_DARWIN_STUB;
2225 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2229 // Returns a chain & a flag for retval copy to use.
2230 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2231 SmallVector<SDValue, 8> Ops;
2233 if (!IsSibcall && isTailCall) {
2234 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2235 DAG.getIntPtrConstant(0, true), InFlag);
2236 InFlag = Chain.getValue(1);
2239 Ops.push_back(Chain);
2240 Ops.push_back(Callee);
2243 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2245 // Add argument registers to the end of the list so that they are known live
2247 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2248 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2249 RegsToPass[i].second.getValueType()));
2251 // Add an implicit use GOT pointer in EBX.
2252 if (!isTailCall && Subtarget->isPICStyleGOT())
2253 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2255 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2256 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64())
2257 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2259 if (InFlag.getNode())
2260 Ops.push_back(InFlag);
2264 //// If this is the first return lowered for this function, add the regs
2265 //// to the liveout set for the function.
2266 // This isn't right, although it's probably harmless on x86; liveouts
2267 // should be computed from returns not tail calls. Consider a void
2268 // function making a tail call to a function returning int.
2269 return DAG.getNode(X86ISD::TC_RETURN, dl,
2270 NodeTys, &Ops[0], Ops.size());
2273 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2274 InFlag = Chain.getValue(1);
2276 // Create the CALLSEQ_END node.
2277 unsigned NumBytesForCalleeToPush;
2278 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2279 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2280 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2281 // If this is a call to a struct-return function, the callee
2282 // pops the hidden struct pointer, so we have to push it back.
2283 // This is common for Darwin/X86, Linux & Mingw32 targets.
2284 NumBytesForCalleeToPush = 4;
2286 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2288 // Returns a flag for retval copy to use.
2290 Chain = DAG.getCALLSEQ_END(Chain,
2291 DAG.getIntPtrConstant(NumBytes, true),
2292 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2295 InFlag = Chain.getValue(1);
2298 // Handle result values, copying them out of physregs into vregs that we
2300 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2301 Ins, dl, DAG, InVals);
2305 //===----------------------------------------------------------------------===//
2306 // Fast Calling Convention (tail call) implementation
2307 //===----------------------------------------------------------------------===//
2309 // Like std call, callee cleans arguments, convention except that ECX is
2310 // reserved for storing the tail called function address. Only 2 registers are
2311 // free for argument passing (inreg). Tail call optimization is performed
2313 // * tailcallopt is enabled
2314 // * caller/callee are fastcc
2315 // On X86_64 architecture with GOT-style position independent code only local
2316 // (within module) calls are supported at the moment.
2317 // To keep the stack aligned according to platform abi the function
2318 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2319 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2320 // If a tail called function callee has more arguments than the caller the
2321 // caller needs to make sure that there is room to move the RETADDR to. This is
2322 // achieved by reserving an area the size of the argument delta right after the
2323 // original REtADDR, but before the saved framepointer or the spilled registers
2324 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2336 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2337 /// for a 16 byte align requirement.
2339 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2340 SelectionDAG& DAG) const {
2341 MachineFunction &MF = DAG.getMachineFunction();
2342 const TargetMachine &TM = MF.getTarget();
2343 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2344 unsigned StackAlignment = TFI.getStackAlignment();
2345 uint64_t AlignMask = StackAlignment - 1;
2346 int64_t Offset = StackSize;
2347 uint64_t SlotSize = TD->getPointerSize();
2348 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2349 // Number smaller than 12 so just add the difference.
2350 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2352 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2353 Offset = ((~AlignMask) & Offset) + StackAlignment +
2354 (StackAlignment-SlotSize);
2359 /// MatchingStackOffset - Return true if the given stack call argument is
2360 /// already available in the same position (relatively) of the caller's
2361 /// incoming argument stack.
2363 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2364 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2365 const X86InstrInfo *TII) {
2366 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2368 if (Arg.getOpcode() == ISD::CopyFromReg) {
2369 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2370 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2372 MachineInstr *Def = MRI->getVRegDef(VR);
2375 if (!Flags.isByVal()) {
2376 if (!TII->isLoadFromStackSlot(Def, FI))
2379 unsigned Opcode = Def->getOpcode();
2380 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2381 Def->getOperand(1).isFI()) {
2382 FI = Def->getOperand(1).getIndex();
2383 Bytes = Flags.getByValSize();
2387 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2388 if (Flags.isByVal())
2389 // ByVal argument is passed in as a pointer but it's now being
2390 // dereferenced. e.g.
2391 // define @foo(%struct.X* %A) {
2392 // tail call @bar(%struct.X* byval %A)
2395 SDValue Ptr = Ld->getBasePtr();
2396 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2399 FI = FINode->getIndex();
2403 assert(FI != INT_MAX);
2404 if (!MFI->isFixedObjectIndex(FI))
2406 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2409 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2410 /// for tail call optimization. Targets which want to do tail call
2411 /// optimization should implement this function.
2413 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2414 CallingConv::ID CalleeCC,
2416 bool isCalleeStructRet,
2417 bool isCallerStructRet,
2418 const SmallVectorImpl<ISD::OutputArg> &Outs,
2419 const SmallVectorImpl<SDValue> &OutVals,
2420 const SmallVectorImpl<ISD::InputArg> &Ins,
2421 SelectionDAG& DAG) const {
2422 if (!IsTailCallConvention(CalleeCC) &&
2423 CalleeCC != CallingConv::C)
2426 // If -tailcallopt is specified, make fastcc functions tail-callable.
2427 const MachineFunction &MF = DAG.getMachineFunction();
2428 const Function *CallerF = DAG.getMachineFunction().getFunction();
2429 CallingConv::ID CallerCC = CallerF->getCallingConv();
2430 bool CCMatch = CallerCC == CalleeCC;
2432 if (GuaranteedTailCallOpt) {
2433 if (IsTailCallConvention(CalleeCC) && CCMatch)
2438 // Look for obvious safe cases to perform tail call optimization that do not
2439 // require ABI changes. This is what gcc calls sibcall.
2441 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2442 // emit a special epilogue.
2443 if (RegInfo->needsStackRealignment(MF))
2446 // Do not sibcall optimize vararg calls unless the call site is not passing
2448 if (isVarArg && !Outs.empty())
2451 // Also avoid sibcall optimization if either caller or callee uses struct
2452 // return semantics.
2453 if (isCalleeStructRet || isCallerStructRet)
2456 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2457 // Therefore if it's not used by the call it is not safe to optimize this into
2459 bool Unused = false;
2460 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2467 SmallVector<CCValAssign, 16> RVLocs;
2468 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2469 RVLocs, *DAG.getContext());
2470 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2471 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2472 CCValAssign &VA = RVLocs[i];
2473 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2478 // If the calling conventions do not match, then we'd better make sure the
2479 // results are returned in the same way as what the caller expects.
2481 SmallVector<CCValAssign, 16> RVLocs1;
2482 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2483 RVLocs1, *DAG.getContext());
2484 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2486 SmallVector<CCValAssign, 16> RVLocs2;
2487 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2488 RVLocs2, *DAG.getContext());
2489 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2491 if (RVLocs1.size() != RVLocs2.size())
2493 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2494 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2496 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2498 if (RVLocs1[i].isRegLoc()) {
2499 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2502 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2508 // If the callee takes no arguments then go on to check the results of the
2510 if (!Outs.empty()) {
2511 // Check if stack adjustment is needed. For now, do not do this if any
2512 // argument is passed on the stack.
2513 SmallVector<CCValAssign, 16> ArgLocs;
2514 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2515 ArgLocs, *DAG.getContext());
2516 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2517 if (CCInfo.getNextStackOffset()) {
2518 MachineFunction &MF = DAG.getMachineFunction();
2519 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2521 if (Subtarget->isTargetWin64())
2522 // Win64 ABI has additional complications.
2525 // Check if the arguments are already laid out in the right way as
2526 // the caller's fixed stack objects.
2527 MachineFrameInfo *MFI = MF.getFrameInfo();
2528 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2529 const X86InstrInfo *TII =
2530 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2531 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2532 CCValAssign &VA = ArgLocs[i];
2533 SDValue Arg = OutVals[i];
2534 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2535 if (VA.getLocInfo() == CCValAssign::Indirect)
2537 if (!VA.isRegLoc()) {
2538 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2545 // If the tailcall address may be in a register, then make sure it's
2546 // possible to register allocate for it. In 32-bit, the call address can
2547 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2548 // callee-saved registers are restored. These happen to be the same
2549 // registers used to pass 'inreg' arguments so watch out for those.
2550 if (!Subtarget->is64Bit() &&
2551 !isa<GlobalAddressSDNode>(Callee) &&
2552 !isa<ExternalSymbolSDNode>(Callee)) {
2553 unsigned NumInRegs = 0;
2554 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2555 CCValAssign &VA = ArgLocs[i];
2558 unsigned Reg = VA.getLocReg();
2561 case X86::EAX: case X86::EDX: case X86::ECX:
2562 if (++NumInRegs == 3)
2574 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2575 return X86::createFastISel(funcInfo);
2579 //===----------------------------------------------------------------------===//
2580 // Other Lowering Hooks
2581 //===----------------------------------------------------------------------===//
2583 static bool MayFoldLoad(SDValue Op) {
2584 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2587 static bool MayFoldIntoStore(SDValue Op) {
2588 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2591 static bool isTargetShuffle(unsigned Opcode) {
2593 default: return false;
2594 case X86ISD::PSHUFD:
2595 case X86ISD::PSHUFHW:
2596 case X86ISD::PSHUFLW:
2597 case X86ISD::SHUFPD:
2598 case X86ISD::PALIGN:
2599 case X86ISD::SHUFPS:
2600 case X86ISD::MOVLHPS:
2601 case X86ISD::MOVLHPD:
2602 case X86ISD::MOVHLPS:
2603 case X86ISD::MOVLPS:
2604 case X86ISD::MOVLPD:
2605 case X86ISD::MOVSHDUP:
2606 case X86ISD::MOVSLDUP:
2609 case X86ISD::UNPCKLPS:
2610 case X86ISD::UNPCKLPD:
2611 case X86ISD::PUNPCKLWD:
2612 case X86ISD::PUNPCKLBW:
2613 case X86ISD::PUNPCKLDQ:
2614 case X86ISD::PUNPCKLQDQ:
2615 case X86ISD::UNPCKHPS:
2616 case X86ISD::UNPCKHPD:
2617 case X86ISD::PUNPCKHWD:
2618 case X86ISD::PUNPCKHBW:
2619 case X86ISD::PUNPCKHDQ:
2620 case X86ISD::PUNPCKHQDQ:
2626 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2627 SDValue V1, SelectionDAG &DAG) {
2629 default: llvm_unreachable("Unknown x86 shuffle node");
2630 case X86ISD::MOVSHDUP:
2631 case X86ISD::MOVSLDUP:
2632 return DAG.getNode(Opc, dl, VT, V1);
2638 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2639 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2641 default: llvm_unreachable("Unknown x86 shuffle node");
2642 case X86ISD::PSHUFD:
2643 case X86ISD::PSHUFHW:
2644 case X86ISD::PSHUFLW:
2645 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2651 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2652 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2654 default: llvm_unreachable("Unknown x86 shuffle node");
2655 case X86ISD::PALIGN:
2656 case X86ISD::SHUFPD:
2657 case X86ISD::SHUFPS:
2658 return DAG.getNode(Opc, dl, VT, V1, V2,
2659 DAG.getConstant(TargetMask, MVT::i8));
2664 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2665 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2667 default: llvm_unreachable("Unknown x86 shuffle node");
2668 case X86ISD::MOVLHPS:
2669 case X86ISD::MOVLHPD:
2670 case X86ISD::MOVHLPS:
2671 case X86ISD::MOVLPS:
2672 case X86ISD::MOVLPD:
2675 case X86ISD::UNPCKLPS:
2676 case X86ISD::UNPCKLPD:
2677 case X86ISD::PUNPCKLWD:
2678 case X86ISD::PUNPCKLBW:
2679 case X86ISD::PUNPCKLDQ:
2680 case X86ISD::PUNPCKLQDQ:
2681 case X86ISD::UNPCKHPS:
2682 case X86ISD::UNPCKHPD:
2683 case X86ISD::PUNPCKHWD:
2684 case X86ISD::PUNPCKHBW:
2685 case X86ISD::PUNPCKHDQ:
2686 case X86ISD::PUNPCKHQDQ:
2687 return DAG.getNode(Opc, dl, VT, V1, V2);
2692 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2693 MachineFunction &MF = DAG.getMachineFunction();
2694 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2695 int ReturnAddrIndex = FuncInfo->getRAIndex();
2697 if (ReturnAddrIndex == 0) {
2698 // Set up a frame object for the return address.
2699 uint64_t SlotSize = TD->getPointerSize();
2700 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2702 FuncInfo->setRAIndex(ReturnAddrIndex);
2705 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2709 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2710 bool hasSymbolicDisplacement) {
2711 // Offset should fit into 32 bit immediate field.
2712 if (!isInt<32>(Offset))
2715 // If we don't have a symbolic displacement - we don't have any extra
2717 if (!hasSymbolicDisplacement)
2720 // FIXME: Some tweaks might be needed for medium code model.
2721 if (M != CodeModel::Small && M != CodeModel::Kernel)
2724 // For small code model we assume that latest object is 16MB before end of 31
2725 // bits boundary. We may also accept pretty large negative constants knowing
2726 // that all objects are in the positive half of address space.
2727 if (M == CodeModel::Small && Offset < 16*1024*1024)
2730 // For kernel code model we know that all object resist in the negative half
2731 // of 32bits address space. We may not accept negative offsets, since they may
2732 // be just off and we may accept pretty large positive ones.
2733 if (M == CodeModel::Kernel && Offset > 0)
2739 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2740 /// specific condition code, returning the condition code and the LHS/RHS of the
2741 /// comparison to make.
2742 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2743 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2745 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2746 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2747 // X > -1 -> X == 0, jump !sign.
2748 RHS = DAG.getConstant(0, RHS.getValueType());
2749 return X86::COND_NS;
2750 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2751 // X < 0 -> X == 0, jump on sign.
2753 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2755 RHS = DAG.getConstant(0, RHS.getValueType());
2756 return X86::COND_LE;
2760 switch (SetCCOpcode) {
2761 default: llvm_unreachable("Invalid integer condition!");
2762 case ISD::SETEQ: return X86::COND_E;
2763 case ISD::SETGT: return X86::COND_G;
2764 case ISD::SETGE: return X86::COND_GE;
2765 case ISD::SETLT: return X86::COND_L;
2766 case ISD::SETLE: return X86::COND_LE;
2767 case ISD::SETNE: return X86::COND_NE;
2768 case ISD::SETULT: return X86::COND_B;
2769 case ISD::SETUGT: return X86::COND_A;
2770 case ISD::SETULE: return X86::COND_BE;
2771 case ISD::SETUGE: return X86::COND_AE;
2775 // First determine if it is required or is profitable to flip the operands.
2777 // If LHS is a foldable load, but RHS is not, flip the condition.
2778 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2779 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2780 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2781 std::swap(LHS, RHS);
2784 switch (SetCCOpcode) {
2790 std::swap(LHS, RHS);
2794 // On a floating point condition, the flags are set as follows:
2796 // 0 | 0 | 0 | X > Y
2797 // 0 | 0 | 1 | X < Y
2798 // 1 | 0 | 0 | X == Y
2799 // 1 | 1 | 1 | unordered
2800 switch (SetCCOpcode) {
2801 default: llvm_unreachable("Condcode should be pre-legalized away");
2803 case ISD::SETEQ: return X86::COND_E;
2804 case ISD::SETOLT: // flipped
2806 case ISD::SETGT: return X86::COND_A;
2807 case ISD::SETOLE: // flipped
2809 case ISD::SETGE: return X86::COND_AE;
2810 case ISD::SETUGT: // flipped
2812 case ISD::SETLT: return X86::COND_B;
2813 case ISD::SETUGE: // flipped
2815 case ISD::SETLE: return X86::COND_BE;
2817 case ISD::SETNE: return X86::COND_NE;
2818 case ISD::SETUO: return X86::COND_P;
2819 case ISD::SETO: return X86::COND_NP;
2821 case ISD::SETUNE: return X86::COND_INVALID;
2825 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2826 /// code. Current x86 isa includes the following FP cmov instructions:
2827 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2828 static bool hasFPCMov(unsigned X86CC) {
2844 /// isFPImmLegal - Returns true if the target can instruction select the
2845 /// specified FP immediate natively. If false, the legalizer will
2846 /// materialize the FP immediate as a load from a constant pool.
2847 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2848 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2849 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2855 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2856 /// the specified range (L, H].
2857 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2858 return (Val < 0) || (Val >= Low && Val < Hi);
2861 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2862 /// specified value.
2863 static bool isUndefOrEqual(int Val, int CmpVal) {
2864 if (Val < 0 || Val == CmpVal)
2869 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2870 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2871 /// the second operand.
2872 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2873 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2874 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2875 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2876 return (Mask[0] < 2 && Mask[1] < 2);
2880 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2881 SmallVector<int, 8> M;
2883 return ::isPSHUFDMask(M, N->getValueType(0));
2886 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2887 /// is suitable for input to PSHUFHW.
2888 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2889 if (VT != MVT::v8i16)
2892 // Lower quadword copied in order or undef.
2893 for (int i = 0; i != 4; ++i)
2894 if (Mask[i] >= 0 && Mask[i] != i)
2897 // Upper quadword shuffled.
2898 for (int i = 4; i != 8; ++i)
2899 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2905 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2906 SmallVector<int, 8> M;
2908 return ::isPSHUFHWMask(M, N->getValueType(0));
2911 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2912 /// is suitable for input to PSHUFLW.
2913 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2914 if (VT != MVT::v8i16)
2917 // Upper quadword copied in order.
2918 for (int i = 4; i != 8; ++i)
2919 if (Mask[i] >= 0 && Mask[i] != i)
2922 // Lower quadword shuffled.
2923 for (int i = 0; i != 4; ++i)
2930 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2931 SmallVector<int, 8> M;
2933 return ::isPSHUFLWMask(M, N->getValueType(0));
2936 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2937 /// is suitable for input to PALIGNR.
2938 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2940 int i, e = VT.getVectorNumElements();
2942 // Do not handle v2i64 / v2f64 shuffles with palignr.
2943 if (e < 4 || !hasSSSE3)
2946 for (i = 0; i != e; ++i)
2950 // All undef, not a palignr.
2954 // Determine if it's ok to perform a palignr with only the LHS, since we
2955 // don't have access to the actual shuffle elements to see if RHS is undef.
2956 bool Unary = Mask[i] < (int)e;
2957 bool NeedsUnary = false;
2959 int s = Mask[i] - i;
2961 // Check the rest of the elements to see if they are consecutive.
2962 for (++i; i != e; ++i) {
2967 Unary = Unary && (m < (int)e);
2968 NeedsUnary = NeedsUnary || (m < s);
2970 if (NeedsUnary && !Unary)
2972 if (Unary && m != ((s+i) & (e-1)))
2974 if (!Unary && m != (s+i))
2980 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2981 SmallVector<int, 8> M;
2983 return ::isPALIGNRMask(M, N->getValueType(0), true);
2986 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2987 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2988 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2989 int NumElems = VT.getVectorNumElements();
2990 if (NumElems != 2 && NumElems != 4)
2993 int Half = NumElems / 2;
2994 for (int i = 0; i < Half; ++i)
2995 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2997 for (int i = Half; i < NumElems; ++i)
2998 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3004 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3005 SmallVector<int, 8> M;
3007 return ::isSHUFPMask(M, N->getValueType(0));
3010 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3011 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3012 /// half elements to come from vector 1 (which would equal the dest.) and
3013 /// the upper half to come from vector 2.
3014 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3015 int NumElems = VT.getVectorNumElements();
3017 if (NumElems != 2 && NumElems != 4)
3020 int Half = NumElems / 2;
3021 for (int i = 0; i < Half; ++i)
3022 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3024 for (int i = Half; i < NumElems; ++i)
3025 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3030 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3031 SmallVector<int, 8> M;
3033 return isCommutedSHUFPMask(M, N->getValueType(0));
3036 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3037 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3038 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3039 if (N->getValueType(0).getVectorNumElements() != 4)
3042 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3043 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3044 isUndefOrEqual(N->getMaskElt(1), 7) &&
3045 isUndefOrEqual(N->getMaskElt(2), 2) &&
3046 isUndefOrEqual(N->getMaskElt(3), 3);
3049 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3050 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3052 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3053 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3058 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3059 isUndefOrEqual(N->getMaskElt(1), 3) &&
3060 isUndefOrEqual(N->getMaskElt(2), 2) &&
3061 isUndefOrEqual(N->getMaskElt(3), 3);
3064 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3065 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3066 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3067 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3069 if (NumElems != 2 && NumElems != 4)
3072 for (unsigned i = 0; i < NumElems/2; ++i)
3073 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3076 for (unsigned i = NumElems/2; i < NumElems; ++i)
3077 if (!isUndefOrEqual(N->getMaskElt(i), i))
3083 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3084 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3085 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3086 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3088 if (NumElems != 2 && NumElems != 4)
3091 for (unsigned i = 0; i < NumElems/2; ++i)
3092 if (!isUndefOrEqual(N->getMaskElt(i), i))
3095 for (unsigned i = 0; i < NumElems/2; ++i)
3096 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3102 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3103 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3104 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3105 bool V2IsSplat = false) {
3106 int NumElts = VT.getVectorNumElements();
3107 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3110 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3112 int BitI1 = Mask[i+1];
3113 if (!isUndefOrEqual(BitI, j))
3116 if (!isUndefOrEqual(BitI1, NumElts))
3119 if (!isUndefOrEqual(BitI1, j + NumElts))
3126 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3127 SmallVector<int, 8> M;
3129 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3132 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3133 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3134 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3135 bool V2IsSplat = false) {
3136 int NumElts = VT.getVectorNumElements();
3137 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3140 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3142 int BitI1 = Mask[i+1];
3143 if (!isUndefOrEqual(BitI, j + NumElts/2))
3146 if (isUndefOrEqual(BitI1, NumElts))
3149 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
3156 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3157 SmallVector<int, 8> M;
3159 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3162 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3163 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3165 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3166 int NumElems = VT.getVectorNumElements();
3167 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3170 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
3172 int BitI1 = Mask[i+1];
3173 if (!isUndefOrEqual(BitI, j))
3175 if (!isUndefOrEqual(BitI1, j))
3181 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3182 SmallVector<int, 8> M;
3184 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3187 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3188 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3190 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3191 int NumElems = VT.getVectorNumElements();
3192 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3195 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3197 int BitI1 = Mask[i+1];
3198 if (!isUndefOrEqual(BitI, j))
3200 if (!isUndefOrEqual(BitI1, j))
3206 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3207 SmallVector<int, 8> M;
3209 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3212 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3213 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3214 /// MOVSD, and MOVD, i.e. setting the lowest element.
3215 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3216 if (VT.getVectorElementType().getSizeInBits() < 32)
3219 int NumElts = VT.getVectorNumElements();
3221 if (!isUndefOrEqual(Mask[0], NumElts))
3224 for (int i = 1; i < NumElts; ++i)
3225 if (!isUndefOrEqual(Mask[i], i))
3231 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3232 SmallVector<int, 8> M;
3234 return ::isMOVLMask(M, N->getValueType(0));
3237 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3238 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3239 /// element of vector 2 and the other elements to come from vector 1 in order.
3240 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3241 bool V2IsSplat = false, bool V2IsUndef = false) {
3242 int NumOps = VT.getVectorNumElements();
3243 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3246 if (!isUndefOrEqual(Mask[0], 0))
3249 for (int i = 1; i < NumOps; ++i)
3250 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3251 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3252 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3258 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3259 bool V2IsUndef = false) {
3260 SmallVector<int, 8> M;
3262 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3265 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3266 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3267 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3268 if (N->getValueType(0).getVectorNumElements() != 4)
3271 // Expect 1, 1, 3, 3
3272 for (unsigned i = 0; i < 2; ++i) {
3273 int Elt = N->getMaskElt(i);
3274 if (Elt >= 0 && Elt != 1)
3279 for (unsigned i = 2; i < 4; ++i) {
3280 int Elt = N->getMaskElt(i);
3281 if (Elt >= 0 && Elt != 3)
3286 // Don't use movshdup if it can be done with a shufps.
3287 // FIXME: verify that matching u, u, 3, 3 is what we want.
3291 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3292 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3293 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3294 if (N->getValueType(0).getVectorNumElements() != 4)
3297 // Expect 0, 0, 2, 2
3298 for (unsigned i = 0; i < 2; ++i)
3299 if (N->getMaskElt(i) > 0)
3303 for (unsigned i = 2; i < 4; ++i) {
3304 int Elt = N->getMaskElt(i);
3305 if (Elt >= 0 && Elt != 2)
3310 // Don't use movsldup if it can be done with a shufps.
3314 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3315 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3316 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3317 int e = N->getValueType(0).getVectorNumElements() / 2;
3319 for (int i = 0; i < e; ++i)
3320 if (!isUndefOrEqual(N->getMaskElt(i), i))
3322 for (int i = 0; i < e; ++i)
3323 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3328 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3329 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3330 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3331 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3332 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3334 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3336 for (int i = 0; i < NumOperands; ++i) {
3337 int Val = SVOp->getMaskElt(NumOperands-i-1);
3338 if (Val < 0) Val = 0;
3339 if (Val >= NumOperands) Val -= NumOperands;
3341 if (i != NumOperands - 1)
3347 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3348 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3349 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3350 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3352 // 8 nodes, but we only care about the last 4.
3353 for (unsigned i = 7; i >= 4; --i) {
3354 int Val = SVOp->getMaskElt(i);
3363 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3364 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3365 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3366 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3368 // 8 nodes, but we only care about the first 4.
3369 for (int i = 3; i >= 0; --i) {
3370 int Val = SVOp->getMaskElt(i);
3379 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3380 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3381 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3382 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3383 EVT VVT = N->getValueType(0);
3384 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3388 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3389 Val = SVOp->getMaskElt(i);
3393 return (Val - i) * EltSize;
3396 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3398 bool X86::isZeroNode(SDValue Elt) {
3399 return ((isa<ConstantSDNode>(Elt) &&
3400 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3401 (isa<ConstantFPSDNode>(Elt) &&
3402 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3405 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3406 /// their permute mask.
3407 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3408 SelectionDAG &DAG) {
3409 EVT VT = SVOp->getValueType(0);
3410 unsigned NumElems = VT.getVectorNumElements();
3411 SmallVector<int, 8> MaskVec;
3413 for (unsigned i = 0; i != NumElems; ++i) {
3414 int idx = SVOp->getMaskElt(i);
3416 MaskVec.push_back(idx);
3417 else if (idx < (int)NumElems)
3418 MaskVec.push_back(idx + NumElems);
3420 MaskVec.push_back(idx - NumElems);
3422 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3423 SVOp->getOperand(0), &MaskVec[0]);
3426 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3427 /// the two vector operands have swapped position.
3428 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3429 unsigned NumElems = VT.getVectorNumElements();
3430 for (unsigned i = 0; i != NumElems; ++i) {
3434 else if (idx < (int)NumElems)
3435 Mask[i] = idx + NumElems;
3437 Mask[i] = idx - NumElems;
3441 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3442 /// match movhlps. The lower half elements should come from upper half of
3443 /// V1 (and in order), and the upper half elements should come from the upper
3444 /// half of V2 (and in order).
3445 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3446 if (Op->getValueType(0).getVectorNumElements() != 4)
3448 for (unsigned i = 0, e = 2; i != e; ++i)
3449 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3451 for (unsigned i = 2; i != 4; ++i)
3452 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3457 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3458 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3460 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3461 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3463 N = N->getOperand(0).getNode();
3464 if (!ISD::isNON_EXTLoad(N))
3467 *LD = cast<LoadSDNode>(N);
3471 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3472 /// match movlp{s|d}. The lower half elements should come from lower half of
3473 /// V1 (and in order), and the upper half elements should come from the upper
3474 /// half of V2 (and in order). And since V1 will become the source of the
3475 /// MOVLP, it must be either a vector load or a scalar load to vector.
3476 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3477 ShuffleVectorSDNode *Op) {
3478 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3480 // Is V2 is a vector load, don't do this transformation. We will try to use
3481 // load folding shufps op.
3482 if (ISD::isNON_EXTLoad(V2))
3485 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3487 if (NumElems != 2 && NumElems != 4)
3489 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3490 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3492 for (unsigned i = NumElems/2; i != NumElems; ++i)
3493 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3498 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3500 static bool isSplatVector(SDNode *N) {
3501 if (N->getOpcode() != ISD::BUILD_VECTOR)
3504 SDValue SplatValue = N->getOperand(0);
3505 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3506 if (N->getOperand(i) != SplatValue)
3511 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3512 /// to an zero vector.
3513 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3514 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3515 SDValue V1 = N->getOperand(0);
3516 SDValue V2 = N->getOperand(1);
3517 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3518 for (unsigned i = 0; i != NumElems; ++i) {
3519 int Idx = N->getMaskElt(i);
3520 if (Idx >= (int)NumElems) {
3521 unsigned Opc = V2.getOpcode();
3522 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3524 if (Opc != ISD::BUILD_VECTOR ||
3525 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3527 } else if (Idx >= 0) {
3528 unsigned Opc = V1.getOpcode();
3529 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3531 if (Opc != ISD::BUILD_VECTOR ||
3532 !X86::isZeroNode(V1.getOperand(Idx)))
3539 /// getZeroVector - Returns a vector of specified type with all zero elements.
3541 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3543 assert(VT.isVector() && "Expected a vector type");
3545 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted
3546 // to their dest type. This ensures they get CSE'd.
3548 if (VT.getSizeInBits() == 64) { // MMX
3549 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3550 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3551 } else if (VT.getSizeInBits() == 128) {
3552 if (HasSSE2) { // SSE2
3553 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3554 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3556 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3557 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3559 } else if (VT.getSizeInBits() == 256) { // AVX
3560 // 256-bit logic and arithmetic instructions in AVX are
3561 // all floating-point, no support for integer ops. Default
3562 // to emitting fp zeroed vectors then.
3563 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3564 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3565 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
3567 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3570 /// getOnesVector - Returns a vector of specified type with all bits set.
3572 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3573 assert(VT.isVector() && "Expected a vector type");
3575 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3576 // type. This ensures they get CSE'd.
3577 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3579 if (VT.getSizeInBits() == 64) // MMX
3580 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3582 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3583 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3587 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3588 /// that point to V2 points to its first element.
3589 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3590 EVT VT = SVOp->getValueType(0);
3591 unsigned NumElems = VT.getVectorNumElements();
3593 bool Changed = false;
3594 SmallVector<int, 8> MaskVec;
3595 SVOp->getMask(MaskVec);
3597 for (unsigned i = 0; i != NumElems; ++i) {
3598 if (MaskVec[i] > (int)NumElems) {
3599 MaskVec[i] = NumElems;
3604 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3605 SVOp->getOperand(1), &MaskVec[0]);
3606 return SDValue(SVOp, 0);
3609 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3610 /// operation of specified width.
3611 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3613 unsigned NumElems = VT.getVectorNumElements();
3614 SmallVector<int, 8> Mask;
3615 Mask.push_back(NumElems);
3616 for (unsigned i = 1; i != NumElems; ++i)
3618 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3621 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3622 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3624 unsigned NumElems = VT.getVectorNumElements();
3625 SmallVector<int, 8> Mask;
3626 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3628 Mask.push_back(i + NumElems);
3630 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3633 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3634 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3636 unsigned NumElems = VT.getVectorNumElements();
3637 unsigned Half = NumElems/2;
3638 SmallVector<int, 8> Mask;
3639 for (unsigned i = 0; i != Half; ++i) {
3640 Mask.push_back(i + Half);
3641 Mask.push_back(i + NumElems + Half);
3643 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3646 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
3647 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
3648 if (SV->getValueType(0).getVectorNumElements() <= 4)
3649 return SDValue(SV, 0);
3651 EVT PVT = MVT::v4f32;
3652 EVT VT = SV->getValueType(0);
3653 DebugLoc dl = SV->getDebugLoc();
3654 SDValue V1 = SV->getOperand(0);
3655 int NumElems = VT.getVectorNumElements();
3656 int EltNo = SV->getSplatIndex();
3658 // unpack elements to the correct location
3659 while (NumElems > 4) {
3660 if (EltNo < NumElems/2) {
3661 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3663 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3664 EltNo -= NumElems/2;
3669 // Perform the splat.
3670 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3671 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3672 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3673 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3676 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3677 /// vector of zero or undef vector. This produces a shuffle where the low
3678 /// element of V2 is swizzled into the zero/undef vector, landing at element
3679 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3680 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3681 bool isZero, bool HasSSE2,
3682 SelectionDAG &DAG) {
3683 EVT VT = V2.getValueType();
3685 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3686 unsigned NumElems = VT.getVectorNumElements();
3687 SmallVector<int, 16> MaskVec;
3688 for (unsigned i = 0; i != NumElems; ++i)
3689 // If this is the insertion idx, put the low elt of V2 here.
3690 MaskVec.push_back(i == Idx ? NumElems : i);
3691 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3694 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
3695 /// element of the result of the vector shuffle.
3696 SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
3699 return SDValue(); // Limit search depth.
3701 SDValue V = SDValue(N, 0);
3702 EVT VT = V.getValueType();
3703 unsigned Opcode = V.getOpcode();
3705 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
3706 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
3707 Index = SV->getMaskElt(Index);
3710 return DAG.getUNDEF(VT.getVectorElementType());
3712 int NumElems = VT.getVectorNumElements();
3713 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
3714 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
3717 // Recurse into target specific vector shuffles to find scalars.
3718 if (isTargetShuffle(Opcode)) {
3719 int NumElems = VT.getVectorNumElements();
3720 SmallVector<unsigned, 16> ShuffleMask;
3724 case X86ISD::SHUFPS:
3725 case X86ISD::SHUFPD:
3726 ImmN = N->getOperand(N->getNumOperands()-1);
3727 DecodeSHUFPSMask(NumElems,
3728 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3731 case X86ISD::PUNPCKHBW:
3732 case X86ISD::PUNPCKHWD:
3733 case X86ISD::PUNPCKHDQ:
3734 case X86ISD::PUNPCKHQDQ:
3735 DecodePUNPCKHMask(NumElems, ShuffleMask);
3737 case X86ISD::UNPCKHPS:
3738 case X86ISD::UNPCKHPD:
3739 DecodeUNPCKHPMask(NumElems, ShuffleMask);
3741 case X86ISD::PUNPCKLBW:
3742 case X86ISD::PUNPCKLWD:
3743 case X86ISD::PUNPCKLDQ:
3744 case X86ISD::PUNPCKLQDQ:
3745 DecodePUNPCKLMask(NumElems, ShuffleMask);
3747 case X86ISD::UNPCKLPS:
3748 case X86ISD::UNPCKLPD:
3749 DecodeUNPCKLPMask(NumElems, ShuffleMask);
3751 case X86ISD::MOVHLPS:
3752 DecodeMOVHLPSMask(NumElems, ShuffleMask);
3754 case X86ISD::MOVLHPS:
3755 DecodeMOVLHPSMask(NumElems, ShuffleMask);
3757 case X86ISD::PSHUFD:
3758 ImmN = N->getOperand(N->getNumOperands()-1);
3759 DecodePSHUFMask(NumElems,
3760 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3763 case X86ISD::PSHUFHW:
3764 ImmN = N->getOperand(N->getNumOperands()-1);
3765 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3768 case X86ISD::PSHUFLW:
3769 ImmN = N->getOperand(N->getNumOperands()-1);
3770 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3774 case X86ISD::MOVSD: {
3775 // The index 0 always comes from the first element of the second source,
3776 // this is why MOVSS and MOVSD are used in the first place. The other
3777 // elements come from the other positions of the first source vector.
3778 unsigned OpNum = (Index == 0) ? 1 : 0;
3779 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
3783 assert("not implemented for target shuffle node");
3787 Index = ShuffleMask[Index];
3789 return DAG.getUNDEF(VT.getVectorElementType());
3791 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
3792 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
3796 // Actual nodes that may contain scalar elements
3797 if (Opcode == ISD::BIT_CONVERT) {
3798 V = V.getOperand(0);
3799 EVT SrcVT = V.getValueType();
3800 unsigned NumElems = VT.getVectorNumElements();
3802 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
3806 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
3807 return (Index == 0) ? V.getOperand(0)
3808 : DAG.getUNDEF(VT.getVectorElementType());
3810 if (V.getOpcode() == ISD::BUILD_VECTOR)
3811 return V.getOperand(Index);
3816 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
3817 /// shuffle operation which come from a consecutively from a zero. The
3818 /// search can start in two diferent directions, from left or right.
3820 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
3821 bool ZerosFromLeft, SelectionDAG &DAG) {
3824 while (i < NumElems) {
3825 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
3826 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
3827 if (!(Elt.getNode() &&
3828 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
3836 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
3837 /// MaskE correspond consecutively to elements from one of the vector operands,
3838 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
3840 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
3841 int OpIdx, int NumElems, unsigned &OpNum) {
3842 bool SeenV1 = false;
3843 bool SeenV2 = false;
3845 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
3846 int Idx = SVOp->getMaskElt(i);
3847 // Ignore undef indicies
3856 // Only accept consecutive elements from the same vector
3857 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
3861 OpNum = SeenV1 ? 0 : 1;
3865 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
3866 /// logical left shift of a vector.
3867 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3868 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3869 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3870 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3871 false /* check zeros from right */, DAG);
3877 // Considering the elements in the mask that are not consecutive zeros,
3878 // check if they consecutively come from only one of the source vectors.
3880 // V1 = {X, A, B, C} 0
3882 // vector_shuffle V1, V2 <1, 2, 3, X>
3884 if (!isShuffleMaskConsecutive(SVOp,
3885 0, // Mask Start Index
3886 NumElems-NumZeros-1, // Mask End Index
3887 NumZeros, // Where to start looking in the src vector
3888 NumElems, // Number of elements in vector
3889 OpSrc)) // Which source operand ?
3894 ShVal = SVOp->getOperand(OpSrc);
3898 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
3899 /// logical left shift of a vector.
3900 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3901 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3902 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3903 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3904 true /* check zeros from left */, DAG);
3910 // Considering the elements in the mask that are not consecutive zeros,
3911 // check if they consecutively come from only one of the source vectors.
3913 // 0 { A, B, X, X } = V2
3915 // vector_shuffle V1, V2 <X, X, 4, 5>
3917 if (!isShuffleMaskConsecutive(SVOp,
3918 NumZeros, // Mask Start Index
3919 NumElems-1, // Mask End Index
3920 0, // Where to start looking in the src vector
3921 NumElems, // Number of elements in vector
3922 OpSrc)) // Which source operand ?
3927 ShVal = SVOp->getOperand(OpSrc);
3931 /// isVectorShift - Returns true if the shuffle can be implemented as a
3932 /// logical left or right shift of a vector.
3933 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3934 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3935 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
3936 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
3942 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3944 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3945 unsigned NumNonZero, unsigned NumZero,
3947 const TargetLowering &TLI) {
3951 DebugLoc dl = Op.getDebugLoc();
3954 for (unsigned i = 0; i < 16; ++i) {
3955 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3956 if (ThisIsNonZero && First) {
3958 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3960 V = DAG.getUNDEF(MVT::v8i16);
3965 SDValue ThisElt(0, 0), LastElt(0, 0);
3966 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3967 if (LastIsNonZero) {
3968 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3969 MVT::i16, Op.getOperand(i-1));
3971 if (ThisIsNonZero) {
3972 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3973 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3974 ThisElt, DAG.getConstant(8, MVT::i8));
3976 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3980 if (ThisElt.getNode())
3981 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3982 DAG.getIntPtrConstant(i/2));
3986 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3989 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3991 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3992 unsigned NumNonZero, unsigned NumZero,
3994 const TargetLowering &TLI) {
3998 DebugLoc dl = Op.getDebugLoc();
4001 for (unsigned i = 0; i < 8; ++i) {
4002 bool isNonZero = (NonZeros & (1 << i)) != 0;
4006 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4008 V = DAG.getUNDEF(MVT::v8i16);
4011 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4012 MVT::v8i16, V, Op.getOperand(i),
4013 DAG.getIntPtrConstant(i));
4020 /// getVShift - Return a vector logical shift node.
4022 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4023 unsigned NumBits, SelectionDAG &DAG,
4024 const TargetLowering &TLI, DebugLoc dl) {
4025 bool isMMX = VT.getSizeInBits() == 64;
4026 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
4027 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4028 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
4029 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4030 DAG.getNode(Opc, dl, ShVT, SrcOp,
4031 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
4035 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4036 SelectionDAG &DAG) const {
4038 // Check if the scalar load can be widened into a vector load. And if
4039 // the address is "base + cst" see if the cst can be "absorbed" into
4040 // the shuffle mask.
4041 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4042 SDValue Ptr = LD->getBasePtr();
4043 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4045 EVT PVT = LD->getValueType(0);
4046 if (PVT != MVT::i32 && PVT != MVT::f32)
4051 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4052 FI = FINode->getIndex();
4054 } else if (Ptr.getOpcode() == ISD::ADD &&
4055 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4056 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4057 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4058 Offset = Ptr.getConstantOperandVal(1);
4059 Ptr = Ptr.getOperand(0);
4064 SDValue Chain = LD->getChain();
4065 // Make sure the stack object alignment is at least 16.
4066 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4067 if (DAG.InferPtrAlignment(Ptr) < 16) {
4068 if (MFI->isFixedObjectIndex(FI)) {
4069 // Can't change the alignment. FIXME: It's possible to compute
4070 // the exact stack offset and reference FI + adjust offset instead.
4071 // If someone *really* cares about this. That's the way to implement it.
4074 MFI->setObjectAlignment(FI, 16);
4078 // (Offset % 16) must be multiple of 4. Then address is then
4079 // Ptr + (Offset & ~15).
4082 if ((Offset % 16) & 3)
4084 int64_t StartOffset = Offset & ~15;
4086 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4087 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4089 int EltNo = (Offset - StartOffset) >> 2;
4090 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
4091 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
4092 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,LD->getSrcValue(),0,
4094 // Canonicalize it to a v4i32 shuffle.
4095 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
4096 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4097 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
4098 DAG.getUNDEF(MVT::v4i32), &Mask[0]));
4104 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4105 /// vector of type 'VT', see if the elements can be replaced by a single large
4106 /// load which has the same value as a build_vector whose operands are 'elts'.
4108 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4110 /// FIXME: we'd also like to handle the case where the last elements are zero
4111 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4112 /// There's even a handy isZeroNode for that purpose.
4113 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4114 DebugLoc &dl, SelectionDAG &DAG) {
4115 EVT EltVT = VT.getVectorElementType();
4116 unsigned NumElems = Elts.size();
4118 LoadSDNode *LDBase = NULL;
4119 unsigned LastLoadedElt = -1U;
4121 // For each element in the initializer, see if we've found a load or an undef.
4122 // If we don't find an initial load element, or later load elements are
4123 // non-consecutive, bail out.
4124 for (unsigned i = 0; i < NumElems; ++i) {
4125 SDValue Elt = Elts[i];
4127 if (!Elt.getNode() ||
4128 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4131 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4133 LDBase = cast<LoadSDNode>(Elt.getNode());
4137 if (Elt.getOpcode() == ISD::UNDEF)
4140 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4141 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4146 // If we have found an entire vector of loads and undefs, then return a large
4147 // load of the entire vector width starting at the base pointer. If we found
4148 // consecutive loads for the low half, generate a vzext_load node.
4149 if (LastLoadedElt == NumElems - 1) {
4150 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4151 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
4152 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
4153 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4154 return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
4155 LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
4156 LDBase->isVolatile(), LDBase->isNonTemporal(),
4157 LDBase->getAlignment());
4158 } else if (NumElems == 4 && LastLoadedElt == 1) {
4159 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4160 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4161 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
4162 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
4168 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4169 DebugLoc dl = Op.getDebugLoc();
4170 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1.
4171 // All one's are handled with pcmpeqd. In AVX, zero's are handled with
4172 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd
4173 // is present, so AllOnes is ignored.
4174 if (ISD::isBuildVectorAllZeros(Op.getNode()) ||
4175 (Op.getValueType().getSizeInBits() != 256 &&
4176 ISD::isBuildVectorAllOnes(Op.getNode()))) {
4177 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
4178 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
4179 // eliminated on x86-32 hosts.
4180 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
4183 if (ISD::isBuildVectorAllOnes(Op.getNode()))
4184 return getOnesVector(Op.getValueType(), DAG, dl);
4185 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4188 EVT VT = Op.getValueType();
4189 EVT ExtVT = VT.getVectorElementType();
4190 unsigned EVTBits = ExtVT.getSizeInBits();
4192 unsigned NumElems = Op.getNumOperands();
4193 unsigned NumZero = 0;
4194 unsigned NumNonZero = 0;
4195 unsigned NonZeros = 0;
4196 bool IsAllConstants = true;
4197 SmallSet<SDValue, 8> Values;
4198 for (unsigned i = 0; i < NumElems; ++i) {
4199 SDValue Elt = Op.getOperand(i);
4200 if (Elt.getOpcode() == ISD::UNDEF)
4203 if (Elt.getOpcode() != ISD::Constant &&
4204 Elt.getOpcode() != ISD::ConstantFP)
4205 IsAllConstants = false;
4206 if (X86::isZeroNode(Elt))
4209 NonZeros |= (1 << i);
4214 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4215 if (NumNonZero == 0)
4216 return DAG.getUNDEF(VT);
4218 // Special case for single non-zero, non-undef, element.
4219 if (NumNonZero == 1) {
4220 unsigned Idx = CountTrailingZeros_32(NonZeros);
4221 SDValue Item = Op.getOperand(Idx);
4223 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4224 // the value are obviously zero, truncate the value to i32 and do the
4225 // insertion that way. Only do this if the value is non-constant or if the
4226 // value is a constant being inserted into element 0. It is cheaper to do
4227 // a constant pool load than it is to do a movd + shuffle.
4228 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4229 (!IsAllConstants || Idx == 0)) {
4230 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4231 // Handle MMX and SSE both.
4232 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
4233 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
4235 // Truncate the value (which may itself be a constant) to i32, and
4236 // convert it to a vector with movd (S2V+shuffle to zero extend).
4237 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4238 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4239 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4240 Subtarget->hasSSE2(), DAG);
4242 // Now we have our 32-bit value zero extended in the low element of
4243 // a vector. If Idx != 0, swizzle it into place.
4245 SmallVector<int, 4> Mask;
4246 Mask.push_back(Idx);
4247 for (unsigned i = 1; i != VecElts; ++i)
4249 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4250 DAG.getUNDEF(Item.getValueType()),
4253 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
4257 // If we have a constant or non-constant insertion into the low element of
4258 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4259 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4260 // depending on what the source datatype is.
4263 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4264 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4265 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4266 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4267 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4268 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4270 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4271 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4272 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
4273 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4274 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4275 Subtarget->hasSSE2(), DAG);
4276 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
4280 // Is it a vector logical left shift?
4281 if (NumElems == 2 && Idx == 1 &&
4282 X86::isZeroNode(Op.getOperand(0)) &&
4283 !X86::isZeroNode(Op.getOperand(1))) {
4284 unsigned NumBits = VT.getSizeInBits();
4285 return getVShift(true, VT,
4286 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4287 VT, Op.getOperand(1)),
4288 NumBits/2, DAG, *this, dl);
4291 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4294 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4295 // is a non-constant being inserted into an element other than the low one,
4296 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4297 // movd/movss) to move this into the low element, then shuffle it into
4299 if (EVTBits == 32) {
4300 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4302 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4303 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4304 Subtarget->hasSSE2(), DAG);
4305 SmallVector<int, 8> MaskVec;
4306 for (unsigned i = 0; i < NumElems; i++)
4307 MaskVec.push_back(i == Idx ? 0 : 1);
4308 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4312 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4313 if (Values.size() == 1) {
4314 if (EVTBits == 32) {
4315 // Instead of a shuffle like this:
4316 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4317 // Check if it's possible to issue this instead.
4318 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4319 unsigned Idx = CountTrailingZeros_32(NonZeros);
4320 SDValue Item = Op.getOperand(Idx);
4321 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4322 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4327 // A vector full of immediates; various special cases are already
4328 // handled, so this is best done with a single constant-pool load.
4332 // Let legalizer expand 2-wide build_vectors.
4333 if (EVTBits == 64) {
4334 if (NumNonZero == 1) {
4335 // One half is zero or undef.
4336 unsigned Idx = CountTrailingZeros_32(NonZeros);
4337 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4338 Op.getOperand(Idx));
4339 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4340 Subtarget->hasSSE2(), DAG);
4345 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4346 if (EVTBits == 8 && NumElems == 16) {
4347 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4349 if (V.getNode()) return V;
4352 if (EVTBits == 16 && NumElems == 8) {
4353 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4355 if (V.getNode()) return V;
4358 // If element VT is == 32 bits, turn it into a number of shuffles.
4359 SmallVector<SDValue, 8> V;
4361 if (NumElems == 4 && NumZero > 0) {
4362 for (unsigned i = 0; i < 4; ++i) {
4363 bool isZero = !(NonZeros & (1 << i));
4365 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4367 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4370 for (unsigned i = 0; i < 2; ++i) {
4371 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4374 V[i] = V[i*2]; // Must be a zero vector.
4377 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4380 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4383 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4388 SmallVector<int, 8> MaskVec;
4389 bool Reverse = (NonZeros & 0x3) == 2;
4390 for (unsigned i = 0; i < 2; ++i)
4391 MaskVec.push_back(Reverse ? 1-i : i);
4392 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4393 for (unsigned i = 0; i < 2; ++i)
4394 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4395 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4398 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4399 // Check for a build vector of consecutive loads.
4400 for (unsigned i = 0; i < NumElems; ++i)
4401 V[i] = Op.getOperand(i);
4403 // Check for elements which are consecutive loads.
4404 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4408 // For SSE 4.1, use insertps to put the high elements into the low element.
4409 if (getSubtarget()->hasSSE41()) {
4411 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
4412 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
4414 Result = DAG.getUNDEF(VT);
4416 for (unsigned i = 1; i < NumElems; ++i) {
4417 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
4418 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
4419 Op.getOperand(i), DAG.getIntPtrConstant(i));
4424 // Otherwise, expand into a number of unpckl*, start by extending each of
4425 // our (non-undef) elements to the full vector width with the element in the
4426 // bottom slot of the vector (which generates no code for SSE).
4427 for (unsigned i = 0; i < NumElems; ++i) {
4428 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4429 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4431 V[i] = DAG.getUNDEF(VT);
4434 // Next, we iteratively mix elements, e.g. for v4f32:
4435 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4436 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4437 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4438 unsigned EltStride = NumElems >> 1;
4439 while (EltStride != 0) {
4440 for (unsigned i = 0; i < EltStride; ++i) {
4441 // If V[i+EltStride] is undef and this is the first round of mixing,
4442 // then it is safe to just drop this shuffle: V[i] is already in the
4443 // right place, the one element (since it's the first round) being
4444 // inserted as undef can be dropped. This isn't safe for successive
4445 // rounds because they will permute elements within both vectors.
4446 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
4447 EltStride == NumElems/2)
4450 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
4460 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4461 // We support concatenate two MMX registers and place them in a MMX
4462 // register. This is better than doing a stack convert.
4463 DebugLoc dl = Op.getDebugLoc();
4464 EVT ResVT = Op.getValueType();
4465 assert(Op.getNumOperands() == 2);
4466 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4467 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4469 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
4470 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4471 InVec = Op.getOperand(1);
4472 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4473 unsigned NumElts = ResVT.getVectorNumElements();
4474 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4475 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4476 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4478 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
4479 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4480 Mask[0] = 0; Mask[1] = 2;
4481 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4483 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4486 // v8i16 shuffles - Prefer shuffles in the following order:
4487 // 1. [all] pshuflw, pshufhw, optional move
4488 // 2. [ssse3] 1 x pshufb
4489 // 3. [ssse3] 2 x pshufb + 1 x por
4490 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4492 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
4493 SelectionDAG &DAG) const {
4494 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4495 SDValue V1 = SVOp->getOperand(0);
4496 SDValue V2 = SVOp->getOperand(1);
4497 DebugLoc dl = SVOp->getDebugLoc();
4498 SmallVector<int, 8> MaskVals;
4500 // Determine if more than 1 of the words in each of the low and high quadwords
4501 // of the result come from the same quadword of one of the two inputs. Undef
4502 // mask values count as coming from any quadword, for better codegen.
4503 SmallVector<unsigned, 4> LoQuad(4);
4504 SmallVector<unsigned, 4> HiQuad(4);
4505 BitVector InputQuads(4);
4506 for (unsigned i = 0; i < 8; ++i) {
4507 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4508 int EltIdx = SVOp->getMaskElt(i);
4509 MaskVals.push_back(EltIdx);
4518 InputQuads.set(EltIdx / 4);
4521 int BestLoQuad = -1;
4522 unsigned MaxQuad = 1;
4523 for (unsigned i = 0; i < 4; ++i) {
4524 if (LoQuad[i] > MaxQuad) {
4526 MaxQuad = LoQuad[i];
4530 int BestHiQuad = -1;
4532 for (unsigned i = 0; i < 4; ++i) {
4533 if (HiQuad[i] > MaxQuad) {
4535 MaxQuad = HiQuad[i];
4539 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4540 // of the two input vectors, shuffle them into one input vector so only a
4541 // single pshufb instruction is necessary. If There are more than 2 input
4542 // quads, disable the next transformation since it does not help SSSE3.
4543 bool V1Used = InputQuads[0] || InputQuads[1];
4544 bool V2Used = InputQuads[2] || InputQuads[3];
4545 if (Subtarget->hasSSSE3()) {
4546 if (InputQuads.count() == 2 && V1Used && V2Used) {
4547 BestLoQuad = InputQuads.find_first();
4548 BestHiQuad = InputQuads.find_next(BestLoQuad);
4550 if (InputQuads.count() > 2) {
4556 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4557 // the shuffle mask. If a quad is scored as -1, that means that it contains
4558 // words from all 4 input quadwords.
4560 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4561 SmallVector<int, 8> MaskV;
4562 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4563 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4564 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4565 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
4566 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
4567 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
4569 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4570 // source words for the shuffle, to aid later transformations.
4571 bool AllWordsInNewV = true;
4572 bool InOrder[2] = { true, true };
4573 for (unsigned i = 0; i != 8; ++i) {
4574 int idx = MaskVals[i];
4576 InOrder[i/4] = false;
4577 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4579 AllWordsInNewV = false;
4583 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4584 if (AllWordsInNewV) {
4585 for (int i = 0; i != 8; ++i) {
4586 int idx = MaskVals[i];
4589 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4590 if ((idx != i) && idx < 4)
4592 if ((idx != i) && idx > 3)
4601 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4602 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4603 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4604 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
4605 unsigned TargetMask = 0;
4606 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4607 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4608 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
4609 X86::getShufflePSHUFLWImmediate(NewV.getNode());
4610 V1 = NewV.getOperand(0);
4611 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
4615 // If we have SSSE3, and all words of the result are from 1 input vector,
4616 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4617 // is present, fall back to case 4.
4618 if (Subtarget->hasSSSE3()) {
4619 SmallVector<SDValue,16> pshufbMask;
4621 // If we have elements from both input vectors, set the high bit of the
4622 // shuffle mask element to zero out elements that come from V2 in the V1
4623 // mask, and elements that come from V1 in the V2 mask, so that the two
4624 // results can be OR'd together.
4625 bool TwoInputs = V1Used && V2Used;
4626 for (unsigned i = 0; i != 8; ++i) {
4627 int EltIdx = MaskVals[i] * 2;
4628 if (TwoInputs && (EltIdx >= 16)) {
4629 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4630 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4633 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4634 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4636 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4637 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4638 DAG.getNode(ISD::BUILD_VECTOR, dl,
4639 MVT::v16i8, &pshufbMask[0], 16));
4641 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4643 // Calculate the shuffle mask for the second input, shuffle it, and
4644 // OR it with the first shuffled input.
4646 for (unsigned i = 0; i != 8; ++i) {
4647 int EltIdx = MaskVals[i] * 2;
4649 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4650 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4653 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4654 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4656 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4657 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4658 DAG.getNode(ISD::BUILD_VECTOR, dl,
4659 MVT::v16i8, &pshufbMask[0], 16));
4660 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4661 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4664 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4665 // and update MaskVals with new element order.
4666 BitVector InOrder(8);
4667 if (BestLoQuad >= 0) {
4668 SmallVector<int, 8> MaskV;
4669 for (int i = 0; i != 4; ++i) {
4670 int idx = MaskVals[i];
4672 MaskV.push_back(-1);
4674 } else if ((idx / 4) == BestLoQuad) {
4675 MaskV.push_back(idx & 3);
4678 MaskV.push_back(-1);
4681 for (unsigned i = 4; i != 8; ++i)
4683 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4686 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4687 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
4689 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
4693 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4694 // and update MaskVals with the new element order.
4695 if (BestHiQuad >= 0) {
4696 SmallVector<int, 8> MaskV;
4697 for (unsigned i = 0; i != 4; ++i)
4699 for (unsigned i = 4; i != 8; ++i) {
4700 int idx = MaskVals[i];
4702 MaskV.push_back(-1);
4704 } else if ((idx / 4) == BestHiQuad) {
4705 MaskV.push_back((idx & 3) + 4);
4708 MaskV.push_back(-1);
4711 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4714 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4715 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
4717 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
4721 // In case BestHi & BestLo were both -1, which means each quadword has a word
4722 // from each of the four input quadwords, calculate the InOrder bitvector now
4723 // before falling through to the insert/extract cleanup.
4724 if (BestLoQuad == -1 && BestHiQuad == -1) {
4726 for (int i = 0; i != 8; ++i)
4727 if (MaskVals[i] < 0 || MaskVals[i] == i)
4731 // The other elements are put in the right place using pextrw and pinsrw.
4732 for (unsigned i = 0; i != 8; ++i) {
4735 int EltIdx = MaskVals[i];
4738 SDValue ExtOp = (EltIdx < 8)
4739 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4740 DAG.getIntPtrConstant(EltIdx))
4741 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4742 DAG.getIntPtrConstant(EltIdx - 8));
4743 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4744 DAG.getIntPtrConstant(i));
4749 // v16i8 shuffles - Prefer shuffles in the following order:
4750 // 1. [ssse3] 1 x pshufb
4751 // 2. [ssse3] 2 x pshufb + 1 x por
4752 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4754 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4756 const X86TargetLowering &TLI) {
4757 SDValue V1 = SVOp->getOperand(0);
4758 SDValue V2 = SVOp->getOperand(1);
4759 DebugLoc dl = SVOp->getDebugLoc();
4760 SmallVector<int, 16> MaskVals;
4761 SVOp->getMask(MaskVals);
4763 // If we have SSSE3, case 1 is generated when all result bytes come from
4764 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4765 // present, fall back to case 3.
4766 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4769 for (unsigned i = 0; i < 16; ++i) {
4770 int EltIdx = MaskVals[i];
4779 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4780 if (TLI.getSubtarget()->hasSSSE3()) {
4781 SmallVector<SDValue,16> pshufbMask;
4783 // If all result elements are from one input vector, then only translate
4784 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4786 // Otherwise, we have elements from both input vectors, and must zero out
4787 // elements that come from V2 in the first mask, and V1 in the second mask
4788 // so that we can OR them together.
4789 bool TwoInputs = !(V1Only || V2Only);
4790 for (unsigned i = 0; i != 16; ++i) {
4791 int EltIdx = MaskVals[i];
4792 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4793 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4796 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4798 // If all the elements are from V2, assign it to V1 and return after
4799 // building the first pshufb.
4802 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4803 DAG.getNode(ISD::BUILD_VECTOR, dl,
4804 MVT::v16i8, &pshufbMask[0], 16));
4808 // Calculate the shuffle mask for the second input, shuffle it, and
4809 // OR it with the first shuffled input.
4811 for (unsigned i = 0; i != 16; ++i) {
4812 int EltIdx = MaskVals[i];
4814 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4817 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4819 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4820 DAG.getNode(ISD::BUILD_VECTOR, dl,
4821 MVT::v16i8, &pshufbMask[0], 16));
4822 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4825 // No SSSE3 - Calculate in place words and then fix all out of place words
4826 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4827 // the 16 different words that comprise the two doublequadword input vectors.
4828 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4829 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4830 SDValue NewV = V2Only ? V2 : V1;
4831 for (int i = 0; i != 8; ++i) {
4832 int Elt0 = MaskVals[i*2];
4833 int Elt1 = MaskVals[i*2+1];
4835 // This word of the result is all undef, skip it.
4836 if (Elt0 < 0 && Elt1 < 0)
4839 // This word of the result is already in the correct place, skip it.
4840 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4842 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4845 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4846 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4849 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4850 // using a single extract together, load it and store it.
4851 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4852 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4853 DAG.getIntPtrConstant(Elt1 / 2));
4854 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4855 DAG.getIntPtrConstant(i));
4859 // If Elt1 is defined, extract it from the appropriate source. If the
4860 // source byte is not also odd, shift the extracted word left 8 bits
4861 // otherwise clear the bottom 8 bits if we need to do an or.
4863 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4864 DAG.getIntPtrConstant(Elt1 / 2));
4865 if ((Elt1 & 1) == 0)
4866 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4867 DAG.getConstant(8, TLI.getShiftAmountTy()));
4869 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4870 DAG.getConstant(0xFF00, MVT::i16));
4872 // If Elt0 is defined, extract it from the appropriate source. If the
4873 // source byte is not also even, shift the extracted word right 8 bits. If
4874 // Elt1 was also defined, OR the extracted values together before
4875 // inserting them in the result.
4877 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4878 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4879 if ((Elt0 & 1) != 0)
4880 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4881 DAG.getConstant(8, TLI.getShiftAmountTy()));
4883 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4884 DAG.getConstant(0x00FF, MVT::i16));
4885 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4888 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4889 DAG.getIntPtrConstant(i));
4891 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4894 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4895 /// ones, or rewriting v4i32 / v2i32 as 2 wide ones if possible. This can be
4896 /// done when every pair / quad of shuffle mask elements point to elements in
4897 /// the right sequence. e.g.
4898 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
4900 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4902 const TargetLowering &TLI, DebugLoc dl) {
4903 EVT VT = SVOp->getValueType(0);
4904 SDValue V1 = SVOp->getOperand(0);
4905 SDValue V2 = SVOp->getOperand(1);
4906 unsigned NumElems = VT.getVectorNumElements();
4907 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4908 EVT MaskVT = (NewWidth == 4) ? MVT::v4i16 : MVT::v2i32;
4910 switch (VT.getSimpleVT().SimpleTy) {
4911 default: assert(false && "Unexpected!");
4912 case MVT::v4f32: NewVT = MVT::v2f64; break;
4913 case MVT::v4i32: NewVT = MVT::v2i64; break;
4914 case MVT::v8i16: NewVT = MVT::v4i32; break;
4915 case MVT::v16i8: NewVT = MVT::v4i32; break;
4918 if (NewWidth == 2) {
4924 int Scale = NumElems / NewWidth;
4925 SmallVector<int, 8> MaskVec;
4926 for (unsigned i = 0; i < NumElems; i += Scale) {
4928 for (int j = 0; j < Scale; ++j) {
4929 int EltIdx = SVOp->getMaskElt(i+j);
4933 StartIdx = EltIdx - (EltIdx % Scale);
4934 if (EltIdx != StartIdx + j)
4938 MaskVec.push_back(-1);
4940 MaskVec.push_back(StartIdx / Scale);
4943 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4944 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4945 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4948 /// getVZextMovL - Return a zero-extending vector move low node.
4950 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4951 SDValue SrcOp, SelectionDAG &DAG,
4952 const X86Subtarget *Subtarget, DebugLoc dl) {
4953 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4954 LoadSDNode *LD = NULL;
4955 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4956 LD = dyn_cast<LoadSDNode>(SrcOp);
4958 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4960 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4961 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4962 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4963 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4964 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4966 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4967 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4968 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4969 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4977 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4978 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4979 DAG.getNode(ISD::BIT_CONVERT, dl,
4983 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4986 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4987 SDValue V1 = SVOp->getOperand(0);
4988 SDValue V2 = SVOp->getOperand(1);
4989 DebugLoc dl = SVOp->getDebugLoc();
4990 EVT VT = SVOp->getValueType(0);
4992 SmallVector<std::pair<int, int>, 8> Locs;
4994 SmallVector<int, 8> Mask1(4U, -1);
4995 SmallVector<int, 8> PermMask;
4996 SVOp->getMask(PermMask);
5000 for (unsigned i = 0; i != 4; ++i) {
5001 int Idx = PermMask[i];
5003 Locs[i] = std::make_pair(-1, -1);
5005 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5007 Locs[i] = std::make_pair(0, NumLo);
5011 Locs[i] = std::make_pair(1, NumHi);
5013 Mask1[2+NumHi] = Idx;
5019 if (NumLo <= 2 && NumHi <= 2) {
5020 // If no more than two elements come from either vector. This can be
5021 // implemented with two shuffles. First shuffle gather the elements.
5022 // The second shuffle, which takes the first shuffle as both of its
5023 // vector operands, put the elements into the right order.
5024 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5026 SmallVector<int, 8> Mask2(4U, -1);
5028 for (unsigned i = 0; i != 4; ++i) {
5029 if (Locs[i].first == -1)
5032 unsigned Idx = (i < 2) ? 0 : 4;
5033 Idx += Locs[i].first * 2 + Locs[i].second;
5038 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5039 } else if (NumLo == 3 || NumHi == 3) {
5040 // Otherwise, we must have three elements from one vector, call it X, and
5041 // one element from the other, call it Y. First, use a shufps to build an
5042 // intermediate vector with the one element from Y and the element from X
5043 // that will be in the same half in the final destination (the indexes don't
5044 // matter). Then, use a shufps to build the final vector, taking the half
5045 // containing the element from Y from the intermediate, and the other half
5048 // Normalize it so the 3 elements come from V1.
5049 CommuteVectorShuffleMask(PermMask, VT);
5053 // Find the element from V2.
5055 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5056 int Val = PermMask[HiIndex];
5063 Mask1[0] = PermMask[HiIndex];
5065 Mask1[2] = PermMask[HiIndex^1];
5067 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5070 Mask1[0] = PermMask[0];
5071 Mask1[1] = PermMask[1];
5072 Mask1[2] = HiIndex & 1 ? 6 : 4;
5073 Mask1[3] = HiIndex & 1 ? 4 : 6;
5074 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5076 Mask1[0] = HiIndex & 1 ? 2 : 0;
5077 Mask1[1] = HiIndex & 1 ? 0 : 2;
5078 Mask1[2] = PermMask[2];
5079 Mask1[3] = PermMask[3];
5084 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5088 // Break it into (shuffle shuffle_hi, shuffle_lo).
5090 SmallVector<int,8> LoMask(4U, -1);
5091 SmallVector<int,8> HiMask(4U, -1);
5093 SmallVector<int,8> *MaskPtr = &LoMask;
5094 unsigned MaskIdx = 0;
5097 for (unsigned i = 0; i != 4; ++i) {
5104 int Idx = PermMask[i];
5106 Locs[i] = std::make_pair(-1, -1);
5107 } else if (Idx < 4) {
5108 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5109 (*MaskPtr)[LoIdx] = Idx;
5112 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5113 (*MaskPtr)[HiIdx] = Idx;
5118 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5119 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5120 SmallVector<int, 8> MaskOps;
5121 for (unsigned i = 0; i != 4; ++i) {
5122 if (Locs[i].first == -1) {
5123 MaskOps.push_back(-1);
5125 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5126 MaskOps.push_back(Idx);
5129 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5132 static bool MayFoldVectorLoad(SDValue V) {
5133 if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT)
5134 V = V.getOperand(0);
5135 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5136 V = V.getOperand(0);
5143 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
5145 SDValue V1 = Op.getOperand(0);
5146 SDValue V2 = Op.getOperand(1);
5147 EVT VT = Op.getValueType();
5149 assert(VT != MVT::v2i64 && "unsupported shuffle type");
5151 if (HasSSE2 && VT == MVT::v2f64)
5152 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
5155 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
5159 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
5160 SDValue V1 = Op.getOperand(0);
5161 SDValue V2 = Op.getOperand(1);
5162 EVT VT = Op.getValueType();
5164 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
5165 "unsupported shuffle type");
5167 if (V2.getOpcode() == ISD::UNDEF)
5171 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
5175 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
5176 SDValue V1 = Op.getOperand(0);
5177 SDValue V2 = Op.getOperand(1);
5178 EVT VT = Op.getValueType();
5179 unsigned NumElems = VT.getVectorNumElements();
5181 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
5182 // operand of these instructions is only memory, so check if there's a
5183 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
5185 bool CanFoldLoad = false;
5187 // Trivial case, when V2 comes from a load.
5188 if (MayFoldVectorLoad(V2))
5191 // When V1 is a load, it can be folded later into a store in isel, example:
5192 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
5194 // (MOVLPSmr addr:$src1, VR128:$src2)
5195 // So, recognize this potential and also use MOVLPS or MOVLPD
5196 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5200 if (HasSSE2 && NumElems == 2)
5201 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
5204 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
5207 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5208 // movl and movlp will both match v2i64, but v2i64 is never matched by
5209 // movl earlier because we make it strict to avoid messing with the movlp load
5210 // folding logic (see the code above getMOVLP call). Match it here then,
5211 // this is horrible, but will stay like this until we move all shuffle
5212 // matching to x86 specific nodes. Note that for the 1st condition all
5213 // types are matched with movsd.
5214 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
5215 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5217 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5220 assert(VT != MVT::v4i32 && "unsupported shuffle type");
5222 // Invert the operand order and use SHUFPS to match it.
5223 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
5224 X86::getShuffleSHUFImmediate(SVOp), DAG);
5227 static inline unsigned getUNPCKLOpcode(EVT VT) {
5228 switch(VT.getSimpleVT().SimpleTy) {
5229 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5230 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5231 case MVT::v4f32: return X86ISD::UNPCKLPS;
5232 case MVT::v2f64: return X86ISD::UNPCKLPD;
5233 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5234 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5236 llvm_unreachable("Unknow type for unpckl");
5241 static inline unsigned getUNPCKHOpcode(EVT VT) {
5242 switch(VT.getSimpleVT().SimpleTy) {
5243 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
5244 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
5245 case MVT::v4f32: return X86ISD::UNPCKHPS;
5246 case MVT::v2f64: return X86ISD::UNPCKHPD;
5247 case MVT::v16i8: return X86ISD::PUNPCKHBW;
5248 case MVT::v8i16: return X86ISD::PUNPCKHWD;
5250 llvm_unreachable("Unknow type for unpckh");
5256 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
5257 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5258 SDValue V1 = Op.getOperand(0);
5259 SDValue V2 = Op.getOperand(1);
5260 EVT VT = Op.getValueType();
5261 DebugLoc dl = Op.getDebugLoc();
5262 unsigned NumElems = VT.getVectorNumElements();
5263 bool isMMX = VT.getSizeInBits() == 64;
5264 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
5265 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5266 bool V1IsSplat = false;
5267 bool V2IsSplat = false;
5268 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
5269 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
5270 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
5271 MachineFunction &MF = DAG.getMachineFunction();
5272 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
5274 if (isZeroShuffle(SVOp))
5275 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5277 // FIXME: this is somehow handled during isel by MMX pattern fragments. Remove
5278 // the check or come up with another solution when all MMX move to intrinsics,
5279 // but don't allow this to be considered legal, we don't want vector_shuffle
5280 // operations to be matched during isel anymore.
5281 if (isMMX && SVOp->isSplat())
5284 // Promote splats to v4f32.
5285 if (SVOp->isSplat())
5286 return PromoteSplat(SVOp, DAG);
5288 // If the shuffle can be profitably rewritten as a narrower shuffle, then
5290 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
5291 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
5292 if (NewOp.getNode())
5293 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5294 LowerVECTOR_SHUFFLE(NewOp, DAG));
5295 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
5296 // FIXME: Figure out a cleaner way to do this.
5297 // Try to make use of movq to zero out the top part.
5298 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
5299 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
5300 if (NewOp.getNode()) {
5301 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
5302 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
5303 DAG, Subtarget, dl);
5305 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
5306 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
5307 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
5308 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
5309 DAG, Subtarget, dl);
5313 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
5314 // unpckh_undef). Only use pshufd if speed is more important than size.
5315 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
5316 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5317 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5318 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
5319 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5320 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5322 if (X86::isPSHUFDMask(SVOp)) {
5323 // The actual implementation will match the mask in the if above and then
5324 // during isel it can match several different instructions, not only pshufd
5325 // as its name says, sad but true, emulate the behavior for now...
5326 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
5327 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
5329 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5331 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
5332 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
5334 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5335 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
5338 if (VT == MVT::v4f32)
5339 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
5343 // Check if this can be converted into a logical shift.
5344 bool isLeft = false;
5347 bool isShift = getSubtarget()->hasSSE2() &&
5348 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
5349 if (isShift && ShVal.hasOneUse()) {
5350 // If the shifted value has multiple uses, it may be cheaper to use
5351 // v_set0 + movlhps or movhlps, etc.
5352 EVT EltVT = VT.getVectorElementType();
5353 ShAmt *= EltVT.getSizeInBits();
5354 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5357 if (X86::isMOVLMask(SVOp)) {
5360 if (ISD::isBuildVectorAllZeros(V1.getNode()))
5361 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
5362 if (!isMMX && !X86::isMOVLPMask(SVOp)) {
5363 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5364 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5366 if (VT == MVT::v4i32 || VT == MVT::v4f32)
5367 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5371 // FIXME: fold these into legal mask.
5373 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
5374 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
5376 if (X86::isMOVHLPSMask(SVOp))
5377 return getMOVHighToLow(Op, dl, DAG);
5379 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5380 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
5382 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5383 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
5385 if (X86::isMOVLPMask(SVOp))
5386 return getMOVLP(Op, dl, DAG, HasSSE2);
5389 if (ShouldXformToMOVHLPS(SVOp) ||
5390 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
5391 return CommuteVectorShuffle(SVOp, DAG);
5394 // No better options. Use a vshl / vsrl.
5395 EVT EltVT = VT.getVectorElementType();
5396 ShAmt *= EltVT.getSizeInBits();
5397 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5400 bool Commuted = false;
5401 // FIXME: This should also accept a bitcast of a splat? Be careful, not
5402 // 1,1,1,1 -> v8i16 though.
5403 V1IsSplat = isSplatVector(V1.getNode());
5404 V2IsSplat = isSplatVector(V2.getNode());
5406 // Canonicalize the splat or undef, if present, to be on the RHS.
5407 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
5408 Op = CommuteVectorShuffle(SVOp, DAG);
5409 SVOp = cast<ShuffleVectorSDNode>(Op);
5410 V1 = SVOp->getOperand(0);
5411 V2 = SVOp->getOperand(1);
5412 std::swap(V1IsSplat, V2IsSplat);
5413 std::swap(V1IsUndef, V2IsUndef);
5417 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
5418 // Shuffling low element of v1 into undef, just return v1.
5421 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
5422 // the instruction selector will not match, so get a canonical MOVL with
5423 // swapped operands to undo the commute.
5424 return getMOVL(DAG, dl, VT, V2, V1);
5427 if (X86::isUNPCKLMask(SVOp))
5429 Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
5431 if (X86::isUNPCKHMask(SVOp))
5433 Op : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
5436 // Normalize mask so all entries that point to V2 points to its first
5437 // element then try to match unpck{h|l} again. If match, return a
5438 // new vector_shuffle with the corrected mask.
5439 SDValue NewMask = NormalizeMask(SVOp, DAG);
5440 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
5441 if (NSVOp != SVOp) {
5442 if (X86::isUNPCKLMask(NSVOp, true)) {
5444 } else if (X86::isUNPCKHMask(NSVOp, true)) {
5451 // Commute is back and try unpck* again.
5452 // FIXME: this seems wrong.
5453 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
5454 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
5456 if (X86::isUNPCKLMask(NewSVOp))
5458 NewOp : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
5460 if (X86::isUNPCKHMask(NewSVOp))
5462 NewOp : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
5465 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
5467 // Normalize the node to match x86 shuffle ops if needed
5468 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
5469 return CommuteVectorShuffle(SVOp, DAG);
5471 // The checks below are all present in isShuffleMaskLegal, but they are
5472 // inlined here right now to enable us to directly emit target specific
5473 // nodes, and remove one by one until they don't return Op anymore.
5474 SmallVector<int, 16> M;
5477 if (isPALIGNRMask(M, VT, HasSSSE3))
5478 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
5479 X86::getShufflePALIGNRImmediate(SVOp),
5482 // Only a few shuffle masks are handled for 64-bit vectors (MMX), and
5483 // 64-bit vectors which made to this point can't be handled, they are
5488 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
5489 SVOp->getSplatIndex() == 0 && V2IsUndef) {
5490 if (VT == MVT::v2f64)
5491 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
5492 if (VT == MVT::v2i64)
5493 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
5496 if (isPSHUFHWMask(M, VT))
5497 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
5498 X86::getShufflePSHUFHWImmediate(SVOp),
5501 if (isPSHUFLWMask(M, VT))
5502 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
5503 X86::getShufflePSHUFLWImmediate(SVOp),
5506 if (isSHUFPMask(M, VT)) {
5507 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5508 if (VT == MVT::v4f32 || VT == MVT::v4i32)
5509 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
5511 if (VT == MVT::v2f64 || VT == MVT::v2i64)
5512 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
5516 if (X86::isUNPCKL_v_undef_Mask(SVOp))
5517 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5518 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5519 if (X86::isUNPCKH_v_undef_Mask(SVOp))
5520 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5521 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5523 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
5524 if (VT == MVT::v8i16) {
5525 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
5526 if (NewOp.getNode())
5530 if (VT == MVT::v16i8) {
5531 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
5532 if (NewOp.getNode())
5536 // Handle all 4 wide cases with a number of shuffles except for MMX.
5537 if (NumElems == 4 && !isMMX)
5538 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
5544 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
5545 SelectionDAG &DAG) const {
5546 EVT VT = Op.getValueType();
5547 DebugLoc dl = Op.getDebugLoc();
5548 if (VT.getSizeInBits() == 8) {
5549 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
5550 Op.getOperand(0), Op.getOperand(1));
5551 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5552 DAG.getValueType(VT));
5553 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5554 } else if (VT.getSizeInBits() == 16) {
5555 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5556 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
5558 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5559 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5560 DAG.getNode(ISD::BIT_CONVERT, dl,
5564 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
5565 Op.getOperand(0), Op.getOperand(1));
5566 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5567 DAG.getValueType(VT));
5568 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5569 } else if (VT == MVT::f32) {
5570 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
5571 // the result back to FR32 register. It's only worth matching if the
5572 // result has a single use which is a store or a bitcast to i32. And in
5573 // the case of a store, it's not worth it if the index is a constant 0,
5574 // because a MOVSSmr can be used instead, which is smaller and faster.
5575 if (!Op.hasOneUse())
5577 SDNode *User = *Op.getNode()->use_begin();
5578 if ((User->getOpcode() != ISD::STORE ||
5579 (isa<ConstantSDNode>(Op.getOperand(1)) &&
5580 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
5581 (User->getOpcode() != ISD::BIT_CONVERT ||
5582 User->getValueType(0) != MVT::i32))
5584 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5585 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
5588 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
5589 } else if (VT == MVT::i32) {
5590 // ExtractPS works with constant index.
5591 if (isa<ConstantSDNode>(Op.getOperand(1)))
5599 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5600 SelectionDAG &DAG) const {
5601 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5604 if (Subtarget->hasSSE41()) {
5605 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
5610 EVT VT = Op.getValueType();
5611 DebugLoc dl = Op.getDebugLoc();
5612 // TODO: handle v16i8.
5613 if (VT.getSizeInBits() == 16) {
5614 SDValue Vec = Op.getOperand(0);
5615 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5617 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5618 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5619 DAG.getNode(ISD::BIT_CONVERT, dl,
5622 // Transform it so it match pextrw which produces a 32-bit result.
5623 EVT EltVT = MVT::i32;
5624 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
5625 Op.getOperand(0), Op.getOperand(1));
5626 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
5627 DAG.getValueType(VT));
5628 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5629 } else if (VT.getSizeInBits() == 32) {
5630 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5634 // SHUFPS the element to the lowest double word, then movss.
5635 int Mask[4] = { Idx, -1, -1, -1 };
5636 EVT VVT = Op.getOperand(0).getValueType();
5637 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5638 DAG.getUNDEF(VVT), Mask);
5639 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5640 DAG.getIntPtrConstant(0));
5641 } else if (VT.getSizeInBits() == 64) {
5642 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
5643 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
5644 // to match extract_elt for f64.
5645 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5649 // UNPCKHPD the element to the lowest double word, then movsd.
5650 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
5651 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
5652 int Mask[2] = { 1, -1 };
5653 EVT VVT = Op.getOperand(0).getValueType();
5654 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5655 DAG.getUNDEF(VVT), Mask);
5656 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5657 DAG.getIntPtrConstant(0));
5664 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5665 SelectionDAG &DAG) const {
5666 EVT VT = Op.getValueType();
5667 EVT EltVT = VT.getVectorElementType();
5668 DebugLoc dl = Op.getDebugLoc();
5670 SDValue N0 = Op.getOperand(0);
5671 SDValue N1 = Op.getOperand(1);
5672 SDValue N2 = Op.getOperand(2);
5674 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5675 isa<ConstantSDNode>(N2)) {
5677 if (VT == MVT::v8i16)
5678 Opc = X86ISD::PINSRW;
5679 else if (VT == MVT::v4i16)
5680 Opc = X86ISD::MMX_PINSRW;
5681 else if (VT == MVT::v16i8)
5682 Opc = X86ISD::PINSRB;
5684 Opc = X86ISD::PINSRB;
5686 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5688 if (N1.getValueType() != MVT::i32)
5689 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5690 if (N2.getValueType() != MVT::i32)
5691 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5692 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5693 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5694 // Bits [7:6] of the constant are the source select. This will always be
5695 // zero here. The DAG Combiner may combine an extract_elt index into these
5696 // bits. For example (insert (extract, 3), 2) could be matched by putting
5697 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5698 // Bits [5:4] of the constant are the destination select. This is the
5699 // value of the incoming immediate.
5700 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5701 // combine either bitwise AND or insert of float 0.0 to set these bits.
5702 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5703 // Create this as a scalar to vector..
5704 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5705 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5706 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5707 // PINSR* works with constant index.
5714 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5715 EVT VT = Op.getValueType();
5716 EVT EltVT = VT.getVectorElementType();
5718 if (Subtarget->hasSSE41())
5719 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5721 if (EltVT == MVT::i8)
5724 DebugLoc dl = Op.getDebugLoc();
5725 SDValue N0 = Op.getOperand(0);
5726 SDValue N1 = Op.getOperand(1);
5727 SDValue N2 = Op.getOperand(2);
5729 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5730 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5731 // as its second argument.
5732 if (N1.getValueType() != MVT::i32)
5733 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5734 if (N2.getValueType() != MVT::i32)
5735 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5736 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW,
5737 dl, VT, N0, N1, N2);
5743 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5744 DebugLoc dl = Op.getDebugLoc();
5746 if (Op.getValueType() == MVT::v1i64 &&
5747 Op.getOperand(0).getValueType() == MVT::i64)
5748 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5750 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5751 EVT VT = MVT::v2i32;
5752 switch (Op.getValueType().getSimpleVT().SimpleTy) {
5759 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
5760 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
5763 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5764 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5765 // one of the above mentioned nodes. It has to be wrapped because otherwise
5766 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5767 // be used to form addressing mode. These wrapped nodes will be selected
5770 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5771 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5773 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5775 unsigned char OpFlag = 0;
5776 unsigned WrapperKind = X86ISD::Wrapper;
5777 CodeModel::Model M = getTargetMachine().getCodeModel();
5779 if (Subtarget->isPICStyleRIPRel() &&
5780 (M == CodeModel::Small || M == CodeModel::Kernel))
5781 WrapperKind = X86ISD::WrapperRIP;
5782 else if (Subtarget->isPICStyleGOT())
5783 OpFlag = X86II::MO_GOTOFF;
5784 else if (Subtarget->isPICStyleStubPIC())
5785 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5787 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5789 CP->getOffset(), OpFlag);
5790 DebugLoc DL = CP->getDebugLoc();
5791 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5792 // With PIC, the address is actually $g + Offset.
5794 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5795 DAG.getNode(X86ISD::GlobalBaseReg,
5796 DebugLoc(), getPointerTy()),
5803 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5804 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5806 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5808 unsigned char OpFlag = 0;
5809 unsigned WrapperKind = X86ISD::Wrapper;
5810 CodeModel::Model M = getTargetMachine().getCodeModel();
5812 if (Subtarget->isPICStyleRIPRel() &&
5813 (M == CodeModel::Small || M == CodeModel::Kernel))
5814 WrapperKind = X86ISD::WrapperRIP;
5815 else if (Subtarget->isPICStyleGOT())
5816 OpFlag = X86II::MO_GOTOFF;
5817 else if (Subtarget->isPICStyleStubPIC())
5818 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5820 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5822 DebugLoc DL = JT->getDebugLoc();
5823 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5825 // With PIC, the address is actually $g + Offset.
5827 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5828 DAG.getNode(X86ISD::GlobalBaseReg,
5829 DebugLoc(), getPointerTy()),
5837 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5838 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5840 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5842 unsigned char OpFlag = 0;
5843 unsigned WrapperKind = X86ISD::Wrapper;
5844 CodeModel::Model M = getTargetMachine().getCodeModel();
5846 if (Subtarget->isPICStyleRIPRel() &&
5847 (M == CodeModel::Small || M == CodeModel::Kernel))
5848 WrapperKind = X86ISD::WrapperRIP;
5849 else if (Subtarget->isPICStyleGOT())
5850 OpFlag = X86II::MO_GOTOFF;
5851 else if (Subtarget->isPICStyleStubPIC())
5852 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5854 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5856 DebugLoc DL = Op.getDebugLoc();
5857 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5860 // With PIC, the address is actually $g + Offset.
5861 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5862 !Subtarget->is64Bit()) {
5863 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5864 DAG.getNode(X86ISD::GlobalBaseReg,
5865 DebugLoc(), getPointerTy()),
5873 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5874 // Create the TargetBlockAddressAddress node.
5875 unsigned char OpFlags =
5876 Subtarget->ClassifyBlockAddressReference();
5877 CodeModel::Model M = getTargetMachine().getCodeModel();
5878 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5879 DebugLoc dl = Op.getDebugLoc();
5880 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5881 /*isTarget=*/true, OpFlags);
5883 if (Subtarget->isPICStyleRIPRel() &&
5884 (M == CodeModel::Small || M == CodeModel::Kernel))
5885 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5887 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5889 // With PIC, the address is actually $g + Offset.
5890 if (isGlobalRelativeToPICBase(OpFlags)) {
5891 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5892 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5900 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5902 SelectionDAG &DAG) const {
5903 // Create the TargetGlobalAddress node, folding in the constant
5904 // offset if it is legal.
5905 unsigned char OpFlags =
5906 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5907 CodeModel::Model M = getTargetMachine().getCodeModel();
5909 if (OpFlags == X86II::MO_NO_FLAG &&
5910 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5911 // A direct static reference to a global.
5912 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
5915 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
5918 if (Subtarget->isPICStyleRIPRel() &&
5919 (M == CodeModel::Small || M == CodeModel::Kernel))
5920 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5922 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5924 // With PIC, the address is actually $g + Offset.
5925 if (isGlobalRelativeToPICBase(OpFlags)) {
5926 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5927 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5931 // For globals that require a load from a stub to get the address, emit the
5933 if (isGlobalStubReference(OpFlags))
5934 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
5935 PseudoSourceValue::getGOT(), 0, false, false, 0);
5937 // If there was a non-zero offset that we didn't fold, create an explicit
5940 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
5941 DAG.getConstant(Offset, getPointerTy()));
5947 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
5948 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
5949 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
5950 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
5954 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
5955 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
5956 unsigned char OperandFlags) {
5957 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5958 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5959 DebugLoc dl = GA->getDebugLoc();
5960 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
5961 GA->getValueType(0),
5965 SDValue Ops[] = { Chain, TGA, *InFlag };
5966 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
5968 SDValue Ops[] = { Chain, TGA };
5969 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
5972 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
5973 MFI->setAdjustsStack(true);
5975 SDValue Flag = Chain.getValue(1);
5976 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
5979 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
5981 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5984 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
5985 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
5986 DAG.getNode(X86ISD::GlobalBaseReg,
5987 DebugLoc(), PtrVT), InFlag);
5988 InFlag = Chain.getValue(1);
5990 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
5993 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
5995 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
5997 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
5998 X86::RAX, X86II::MO_TLSGD);
6001 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
6002 // "local exec" model.
6003 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6004 const EVT PtrVT, TLSModel::Model model,
6006 DebugLoc dl = GA->getDebugLoc();
6007 // Get the Thread Pointer
6008 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
6010 DAG.getRegister(is64Bit? X86::FS : X86::GS,
6013 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
6014 NULL, 0, false, false, 0);
6016 unsigned char OperandFlags = 0;
6017 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
6019 unsigned WrapperKind = X86ISD::Wrapper;
6020 if (model == TLSModel::LocalExec) {
6021 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
6022 } else if (is64Bit) {
6023 assert(model == TLSModel::InitialExec);
6024 OperandFlags = X86II::MO_GOTTPOFF;
6025 WrapperKind = X86ISD::WrapperRIP;
6027 assert(model == TLSModel::InitialExec);
6028 OperandFlags = X86II::MO_INDNTPOFF;
6031 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
6033 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6034 GA->getValueType(0),
6035 GA->getOffset(), OperandFlags);
6036 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
6038 if (model == TLSModel::InitialExec)
6039 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
6040 PseudoSourceValue::getGOT(), 0, false, false, 0);
6042 // The address of the thread local variable is the add of the thread
6043 // pointer with the offset of the variable.
6044 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
6048 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
6050 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6051 const GlobalValue *GV = GA->getGlobal();
6053 if (Subtarget->isTargetELF()) {
6054 // TODO: implement the "local dynamic" model
6055 // TODO: implement the "initial exec"model for pic executables
6057 // If GV is an alias then use the aliasee for determining
6058 // thread-localness.
6059 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
6060 GV = GA->resolveAliasedGlobal(false);
6062 TLSModel::Model model
6063 = getTLSModel(GV, getTargetMachine().getRelocationModel());
6066 case TLSModel::GeneralDynamic:
6067 case TLSModel::LocalDynamic: // not implemented
6068 if (Subtarget->is64Bit())
6069 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
6070 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
6072 case TLSModel::InitialExec:
6073 case TLSModel::LocalExec:
6074 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
6075 Subtarget->is64Bit());
6077 } else if (Subtarget->isTargetDarwin()) {
6078 // Darwin only has one model of TLS. Lower to that.
6079 unsigned char OpFlag = 0;
6080 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
6081 X86ISD::WrapperRIP : X86ISD::Wrapper;
6083 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6085 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
6086 !Subtarget->is64Bit();
6088 OpFlag = X86II::MO_TLVP_PIC_BASE;
6090 OpFlag = X86II::MO_TLVP;
6091 DebugLoc DL = Op.getDebugLoc();
6092 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
6094 GA->getOffset(), OpFlag);
6095 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6097 // With PIC32, the address is actually $g + Offset.
6099 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6100 DAG.getNode(X86ISD::GlobalBaseReg,
6101 DebugLoc(), getPointerTy()),
6104 // Lowering the machine isd will make sure everything is in the right
6106 SDValue Args[] = { Offset };
6107 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
6109 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
6110 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6111 MFI->setAdjustsStack(true);
6113 // And our return value (tls address) is in the standard call return value
6115 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
6116 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
6120 "TLS not implemented for this target.");
6122 llvm_unreachable("Unreachable");
6127 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
6128 /// take a 2 x i32 value to shift plus a shift amount.
6129 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
6130 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
6131 EVT VT = Op.getValueType();
6132 unsigned VTBits = VT.getSizeInBits();
6133 DebugLoc dl = Op.getDebugLoc();
6134 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
6135 SDValue ShOpLo = Op.getOperand(0);
6136 SDValue ShOpHi = Op.getOperand(1);
6137 SDValue ShAmt = Op.getOperand(2);
6138 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
6139 DAG.getConstant(VTBits - 1, MVT::i8))
6140 : DAG.getConstant(0, VT);
6143 if (Op.getOpcode() == ISD::SHL_PARTS) {
6144 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
6145 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6147 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
6148 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
6151 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
6152 DAG.getConstant(VTBits, MVT::i8));
6153 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6154 AndNode, DAG.getConstant(0, MVT::i8));
6157 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6158 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
6159 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
6161 if (Op.getOpcode() == ISD::SHL_PARTS) {
6162 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6163 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6165 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6166 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6169 SDValue Ops[2] = { Lo, Hi };
6170 return DAG.getMergeValues(Ops, 2, dl);
6173 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
6174 SelectionDAG &DAG) const {
6175 EVT SrcVT = Op.getOperand(0).getValueType();
6177 if (SrcVT.isVector()) {
6178 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
6184 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
6185 "Unknown SINT_TO_FP to lower!");
6187 // These are really Legal; return the operand so the caller accepts it as
6189 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
6191 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
6192 Subtarget->is64Bit()) {
6196 DebugLoc dl = Op.getDebugLoc();
6197 unsigned Size = SrcVT.getSizeInBits()/8;
6198 MachineFunction &MF = DAG.getMachineFunction();
6199 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
6200 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6201 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6203 PseudoSourceValue::getFixedStack(SSFI), 0,
6205 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
6208 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
6210 SelectionDAG &DAG) const {
6212 DebugLoc dl = Op.getDebugLoc();
6214 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
6216 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
6218 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
6219 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
6220 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
6221 Tys, Ops, array_lengthof(Ops));
6224 Chain = Result.getValue(1);
6225 SDValue InFlag = Result.getValue(2);
6227 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
6228 // shouldn't be necessary except that RFP cannot be live across
6229 // multiple blocks. When stackifier is fixed, they can be uncoupled.
6230 MachineFunction &MF = DAG.getMachineFunction();
6231 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6232 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6233 Tys = DAG.getVTList(MVT::Other);
6235 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
6237 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
6238 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
6239 PseudoSourceValue::getFixedStack(SSFI), 0,
6246 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
6247 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
6248 SelectionDAG &DAG) const {
6249 // This algorithm is not obvious. Here it is in C code, more or less:
6251 double uint64_to_double( uint32_t hi, uint32_t lo ) {
6252 static const __m128i exp = { 0x4330000045300000ULL, 0 };
6253 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
6255 // Copy ints to xmm registers.
6256 __m128i xh = _mm_cvtsi32_si128( hi );
6257 __m128i xl = _mm_cvtsi32_si128( lo );
6259 // Combine into low half of a single xmm register.
6260 __m128i x = _mm_unpacklo_epi32( xh, xl );
6264 // Merge in appropriate exponents to give the integer bits the right
6266 x = _mm_unpacklo_epi32( x, exp );
6268 // Subtract away the biases to deal with the IEEE-754 double precision
6270 d = _mm_sub_pd( (__m128d) x, bias );
6272 // All conversions up to here are exact. The correctly rounded result is
6273 // calculated using the current rounding mode using the following
6275 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
6276 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
6277 // store doesn't really need to be here (except
6278 // maybe to zero the other double)
6283 DebugLoc dl = Op.getDebugLoc();
6284 LLVMContext *Context = DAG.getContext();
6286 // Build some magic constants.
6287 std::vector<Constant*> CV0;
6288 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
6289 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
6290 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6291 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6292 Constant *C0 = ConstantVector::get(CV0);
6293 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
6295 std::vector<Constant*> CV1;
6297 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
6299 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
6300 Constant *C1 = ConstantVector::get(CV1);
6301 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
6303 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6304 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6306 DAG.getIntPtrConstant(1)));
6307 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6308 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6310 DAG.getIntPtrConstant(0)));
6311 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
6312 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
6313 PseudoSourceValue::getConstantPool(), 0,
6315 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
6316 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
6317 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
6318 PseudoSourceValue::getConstantPool(), 0,
6320 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
6322 // Add the halves; easiest way is to swap them into another reg first.
6323 int ShufMask[2] = { 1, -1 };
6324 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
6325 DAG.getUNDEF(MVT::v2f64), ShufMask);
6326 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
6327 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
6328 DAG.getIntPtrConstant(0));
6331 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
6332 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
6333 SelectionDAG &DAG) const {
6334 DebugLoc dl = Op.getDebugLoc();
6335 // FP constant to bias correct the final result.
6336 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
6339 // Load the 32-bit value into an XMM register.
6340 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6341 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6343 DAG.getIntPtrConstant(0)));
6345 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6346 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
6347 DAG.getIntPtrConstant(0));
6349 // Or the load with the bias.
6350 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
6351 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6352 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6354 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6355 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6356 MVT::v2f64, Bias)));
6357 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6358 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
6359 DAG.getIntPtrConstant(0));
6361 // Subtract the bias.
6362 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
6364 // Handle final rounding.
6365 EVT DestVT = Op.getValueType();
6367 if (DestVT.bitsLT(MVT::f64)) {
6368 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6369 DAG.getIntPtrConstant(0));
6370 } else if (DestVT.bitsGT(MVT::f64)) {
6371 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6374 // Handle final rounding.
6378 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
6379 SelectionDAG &DAG) const {
6380 SDValue N0 = Op.getOperand(0);
6381 DebugLoc dl = Op.getDebugLoc();
6383 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
6384 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
6385 // the optimization here.
6386 if (DAG.SignBitIsZero(N0))
6387 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
6389 EVT SrcVT = N0.getValueType();
6390 EVT DstVT = Op.getValueType();
6391 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
6392 return LowerUINT_TO_FP_i64(Op, DAG);
6393 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
6394 return LowerUINT_TO_FP_i32(Op, DAG);
6396 // Make a 64-bit buffer, and use it to build an FILD.
6397 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
6398 if (SrcVT == MVT::i32) {
6399 SDValue WordOff = DAG.getConstant(4, getPointerTy());
6400 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
6401 getPointerTy(), StackSlot, WordOff);
6402 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6403 StackSlot, NULL, 0, false, false, 0);
6404 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
6405 OffsetSlot, NULL, 0, false, false, 0);
6406 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
6410 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
6411 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6412 StackSlot, NULL, 0, false, false, 0);
6413 // For i64 source, we need to add the appropriate power of 2 if the input
6414 // was negative. This is the same as the optimization in
6415 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
6416 // we must be careful to do the computation in x87 extended precision, not
6417 // in SSE. (The generic code can't know it's OK to do this, or how to.)
6418 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
6419 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
6420 SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3);
6422 APInt FF(32, 0x5F800000ULL);
6424 // Check whether the sign bit is set.
6425 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
6426 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
6429 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
6430 SDValue FudgePtr = DAG.getConstantPool(
6431 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
6434 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
6435 SDValue Zero = DAG.getIntPtrConstant(0);
6436 SDValue Four = DAG.getIntPtrConstant(4);
6437 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
6439 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
6441 // Load the value out, extending it from f32 to f80.
6442 // FIXME: Avoid the extend by constructing the right constant pool?
6443 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
6444 FudgePtr, PseudoSourceValue::getConstantPool(),
6445 0, MVT::f32, false, false, 4);
6446 // Extend everything to 80 bits to force it to be done on x87.
6447 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
6448 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
6451 std::pair<SDValue,SDValue> X86TargetLowering::
6452 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
6453 DebugLoc dl = Op.getDebugLoc();
6455 EVT DstTy = Op.getValueType();
6458 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
6462 assert(DstTy.getSimpleVT() <= MVT::i64 &&
6463 DstTy.getSimpleVT() >= MVT::i16 &&
6464 "Unknown FP_TO_SINT to lower!");
6466 // These are really Legal.
6467 if (DstTy == MVT::i32 &&
6468 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6469 return std::make_pair(SDValue(), SDValue());
6470 if (Subtarget->is64Bit() &&
6471 DstTy == MVT::i64 &&
6472 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6473 return std::make_pair(SDValue(), SDValue());
6475 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
6477 MachineFunction &MF = DAG.getMachineFunction();
6478 unsigned MemSize = DstTy.getSizeInBits()/8;
6479 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6480 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6483 switch (DstTy.getSimpleVT().SimpleTy) {
6484 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
6485 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
6486 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
6487 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
6490 SDValue Chain = DAG.getEntryNode();
6491 SDValue Value = Op.getOperand(0);
6492 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
6493 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
6494 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
6495 PseudoSourceValue::getFixedStack(SSFI), 0,
6497 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
6499 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
6501 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
6502 Chain = Value.getValue(1);
6503 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6504 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6507 // Build the FP_TO_INT*_IN_MEM
6508 SDValue Ops[] = { Chain, Value, StackSlot };
6509 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
6511 return std::make_pair(FIST, StackSlot);
6514 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
6515 SelectionDAG &DAG) const {
6516 if (Op.getValueType().isVector()) {
6517 if (Op.getValueType() == MVT::v2i32 &&
6518 Op.getOperand(0).getValueType() == MVT::v2f64) {
6524 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
6525 SDValue FIST = Vals.first, StackSlot = Vals.second;
6526 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
6527 if (FIST.getNode() == 0) return Op;
6530 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6531 FIST, StackSlot, NULL, 0, false, false, 0);
6534 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
6535 SelectionDAG &DAG) const {
6536 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
6537 SDValue FIST = Vals.first, StackSlot = Vals.second;
6538 assert(FIST.getNode() && "Unexpected failure");
6541 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6542 FIST, StackSlot, NULL, 0, false, false, 0);
6545 SDValue X86TargetLowering::LowerFABS(SDValue Op,
6546 SelectionDAG &DAG) const {
6547 LLVMContext *Context = DAG.getContext();
6548 DebugLoc dl = Op.getDebugLoc();
6549 EVT VT = Op.getValueType();
6552 EltVT = VT.getVectorElementType();
6553 std::vector<Constant*> CV;
6554 if (EltVT == MVT::f64) {
6555 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
6559 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
6565 Constant *C = ConstantVector::get(CV);
6566 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6567 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6568 PseudoSourceValue::getConstantPool(), 0,
6570 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
6573 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
6574 LLVMContext *Context = DAG.getContext();
6575 DebugLoc dl = Op.getDebugLoc();
6576 EVT VT = Op.getValueType();
6579 EltVT = VT.getVectorElementType();
6580 std::vector<Constant*> CV;
6581 if (EltVT == MVT::f64) {
6582 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
6586 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
6592 Constant *C = ConstantVector::get(CV);
6593 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6594 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6595 PseudoSourceValue::getConstantPool(), 0,
6597 if (VT.isVector()) {
6598 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6599 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
6600 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6602 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
6604 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
6608 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
6609 LLVMContext *Context = DAG.getContext();
6610 SDValue Op0 = Op.getOperand(0);
6611 SDValue Op1 = Op.getOperand(1);
6612 DebugLoc dl = Op.getDebugLoc();
6613 EVT VT = Op.getValueType();
6614 EVT SrcVT = Op1.getValueType();
6616 // If second operand is smaller, extend it first.
6617 if (SrcVT.bitsLT(VT)) {
6618 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
6621 // And if it is bigger, shrink it first.
6622 if (SrcVT.bitsGT(VT)) {
6623 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
6627 // At this point the operands and the result should have the same
6628 // type, and that won't be f80 since that is not custom lowered.
6630 // First get the sign bit of second operand.
6631 std::vector<Constant*> CV;
6632 if (SrcVT == MVT::f64) {
6633 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
6634 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6636 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
6637 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6638 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6639 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6641 Constant *C = ConstantVector::get(CV);
6642 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6643 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
6644 PseudoSourceValue::getConstantPool(), 0,
6646 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
6648 // Shift sign bit right or left if the two operands have different types.
6649 if (SrcVT.bitsGT(VT)) {
6650 // Op0 is MVT::f32, Op1 is MVT::f64.
6651 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
6652 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
6653 DAG.getConstant(32, MVT::i32));
6654 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
6655 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
6656 DAG.getIntPtrConstant(0));
6659 // Clear first operand sign bit.
6661 if (VT == MVT::f64) {
6662 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6663 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6665 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6666 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6667 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6668 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6670 C = ConstantVector::get(CV);
6671 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6672 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6673 PseudoSourceValue::getConstantPool(), 0,
6675 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6677 // Or the value with the sign bit.
6678 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6681 /// Emit nodes that will be selected as "test Op0,Op0", or something
6683 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6684 SelectionDAG &DAG) const {
6685 DebugLoc dl = Op.getDebugLoc();
6687 // CF and OF aren't always set the way we want. Determine which
6688 // of these we need.
6689 bool NeedCF = false;
6690 bool NeedOF = false;
6693 case X86::COND_A: case X86::COND_AE:
6694 case X86::COND_B: case X86::COND_BE:
6697 case X86::COND_G: case X86::COND_GE:
6698 case X86::COND_L: case X86::COND_LE:
6699 case X86::COND_O: case X86::COND_NO:
6704 // See if we can use the EFLAGS value from the operand instead of
6705 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6706 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6707 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6708 // Emit a CMP with 0, which is the TEST pattern.
6709 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6710 DAG.getConstant(0, Op.getValueType()));
6712 unsigned Opcode = 0;
6713 unsigned NumOperands = 0;
6714 switch (Op.getNode()->getOpcode()) {
6716 // Due to an isel shortcoming, be conservative if this add is likely to be
6717 // selected as part of a load-modify-store instruction. When the root node
6718 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6719 // uses of other nodes in the match, such as the ADD in this case. This
6720 // leads to the ADD being left around and reselected, with the result being
6721 // two adds in the output. Alas, even if none our users are stores, that
6722 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6723 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6724 // climbing the DAG back to the root, and it doesn't seem to be worth the
6726 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6727 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6728 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6731 if (ConstantSDNode *C =
6732 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6733 // An add of one will be selected as an INC.
6734 if (C->getAPIntValue() == 1) {
6735 Opcode = X86ISD::INC;
6740 // An add of negative one (subtract of one) will be selected as a DEC.
6741 if (C->getAPIntValue().isAllOnesValue()) {
6742 Opcode = X86ISD::DEC;
6748 // Otherwise use a regular EFLAGS-setting add.
6749 Opcode = X86ISD::ADD;
6753 // If the primary and result isn't used, don't bother using X86ISD::AND,
6754 // because a TEST instruction will be better.
6755 bool NonFlagUse = false;
6756 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6757 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6759 unsigned UOpNo = UI.getOperandNo();
6760 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6761 // Look pass truncate.
6762 UOpNo = User->use_begin().getOperandNo();
6763 User = *User->use_begin();
6766 if (User->getOpcode() != ISD::BRCOND &&
6767 User->getOpcode() != ISD::SETCC &&
6768 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6781 // Due to the ISEL shortcoming noted above, be conservative if this op is
6782 // likely to be selected as part of a load-modify-store instruction.
6783 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6784 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6785 if (UI->getOpcode() == ISD::STORE)
6788 // Otherwise use a regular EFLAGS-setting instruction.
6789 switch (Op.getNode()->getOpcode()) {
6790 default: llvm_unreachable("unexpected operator!");
6791 case ISD::SUB: Opcode = X86ISD::SUB; break;
6792 case ISD::OR: Opcode = X86ISD::OR; break;
6793 case ISD::XOR: Opcode = X86ISD::XOR; break;
6794 case ISD::AND: Opcode = X86ISD::AND; break;
6806 return SDValue(Op.getNode(), 1);
6813 // Emit a CMP with 0, which is the TEST pattern.
6814 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6815 DAG.getConstant(0, Op.getValueType()));
6817 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6818 SmallVector<SDValue, 4> Ops;
6819 for (unsigned i = 0; i != NumOperands; ++i)
6820 Ops.push_back(Op.getOperand(i));
6822 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6823 DAG.ReplaceAllUsesWith(Op, New);
6824 return SDValue(New.getNode(), 1);
6827 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6829 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6830 SelectionDAG &DAG) const {
6831 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6832 if (C->getAPIntValue() == 0)
6833 return EmitTest(Op0, X86CC, DAG);
6835 DebugLoc dl = Op0.getDebugLoc();
6836 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6839 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6840 /// if it's possible.
6841 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6842 DebugLoc dl, SelectionDAG &DAG) const {
6843 SDValue Op0 = And.getOperand(0);
6844 SDValue Op1 = And.getOperand(1);
6845 if (Op0.getOpcode() == ISD::TRUNCATE)
6846 Op0 = Op0.getOperand(0);
6847 if (Op1.getOpcode() == ISD::TRUNCATE)
6848 Op1 = Op1.getOperand(0);
6851 if (Op1.getOpcode() == ISD::SHL)
6852 std::swap(Op0, Op1);
6853 if (Op0.getOpcode() == ISD::SHL) {
6854 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6855 if (And00C->getZExtValue() == 1) {
6856 // If we looked past a truncate, check that it's only truncating away
6858 unsigned BitWidth = Op0.getValueSizeInBits();
6859 unsigned AndBitWidth = And.getValueSizeInBits();
6860 if (BitWidth > AndBitWidth) {
6861 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6862 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6863 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6867 RHS = Op0.getOperand(1);
6869 } else if (Op1.getOpcode() == ISD::Constant) {
6870 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6871 SDValue AndLHS = Op0;
6872 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6873 LHS = AndLHS.getOperand(0);
6874 RHS = AndLHS.getOperand(1);
6878 if (LHS.getNode()) {
6879 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
6880 // instruction. Since the shift amount is in-range-or-undefined, we know
6881 // that doing a bittest on the i32 value is ok. We extend to i32 because
6882 // the encoding for the i16 version is larger than the i32 version.
6883 // Also promote i16 to i32 for performance / code size reason.
6884 if (LHS.getValueType() == MVT::i8 ||
6885 LHS.getValueType() == MVT::i16)
6886 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
6888 // If the operand types disagree, extend the shift amount to match. Since
6889 // BT ignores high bits (like shifts) we can use anyextend.
6890 if (LHS.getValueType() != RHS.getValueType())
6891 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
6893 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
6894 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
6895 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6896 DAG.getConstant(Cond, MVT::i8), BT);
6902 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
6903 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
6904 SDValue Op0 = Op.getOperand(0);
6905 SDValue Op1 = Op.getOperand(1);
6906 DebugLoc dl = Op.getDebugLoc();
6907 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6909 // Optimize to BT if possible.
6910 // Lower (X & (1 << N)) == 0 to BT(X, N).
6911 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
6912 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
6913 if (Op0.getOpcode() == ISD::AND &&
6915 Op1.getOpcode() == ISD::Constant &&
6916 cast<ConstantSDNode>(Op1)->isNullValue() &&
6917 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6918 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
6919 if (NewSetCC.getNode())
6923 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
6924 if (Op0.getOpcode() == X86ISD::SETCC &&
6925 Op1.getOpcode() == ISD::Constant &&
6926 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
6927 cast<ConstantSDNode>(Op1)->isNullValue()) &&
6928 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
6929 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
6930 bool Invert = (CC == ISD::SETNE) ^
6931 cast<ConstantSDNode>(Op1)->isNullValue();
6933 CCode = X86::GetOppositeBranchCondition(CCode);
6934 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6935 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
6938 bool isFP = Op1.getValueType().isFloatingPoint();
6939 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
6940 if (X86CC == X86::COND_INVALID)
6943 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
6945 // Use sbb x, x to materialize carry bit into a GPR.
6946 if (X86CC == X86::COND_B)
6947 return DAG.getNode(ISD::AND, dl, MVT::i8,
6948 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
6949 DAG.getConstant(X86CC, MVT::i8), Cond),
6950 DAG.getConstant(1, MVT::i8));
6952 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6953 DAG.getConstant(X86CC, MVT::i8), Cond);
6956 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
6958 SDValue Op0 = Op.getOperand(0);
6959 SDValue Op1 = Op.getOperand(1);
6960 SDValue CC = Op.getOperand(2);
6961 EVT VT = Op.getValueType();
6962 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6963 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
6964 DebugLoc dl = Op.getDebugLoc();
6968 EVT VT0 = Op0.getValueType();
6969 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
6970 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
6973 switch (SetCCOpcode) {
6976 case ISD::SETEQ: SSECC = 0; break;
6978 case ISD::SETGT: Swap = true; // Fallthrough
6980 case ISD::SETOLT: SSECC = 1; break;
6982 case ISD::SETGE: Swap = true; // Fallthrough
6984 case ISD::SETOLE: SSECC = 2; break;
6985 case ISD::SETUO: SSECC = 3; break;
6987 case ISD::SETNE: SSECC = 4; break;
6988 case ISD::SETULE: Swap = true;
6989 case ISD::SETUGE: SSECC = 5; break;
6990 case ISD::SETULT: Swap = true;
6991 case ISD::SETUGT: SSECC = 6; break;
6992 case ISD::SETO: SSECC = 7; break;
6995 std::swap(Op0, Op1);
6997 // In the two special cases we can't handle, emit two comparisons.
6999 if (SetCCOpcode == ISD::SETUEQ) {
7001 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
7002 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
7003 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
7005 else if (SetCCOpcode == ISD::SETONE) {
7007 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
7008 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
7009 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
7011 llvm_unreachable("Illegal FP comparison");
7013 // Handle all other FP comparisons here.
7014 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
7017 // We are handling one of the integer comparisons here. Since SSE only has
7018 // GT and EQ comparisons for integer, swapping operands and multiple
7019 // operations may be required for some comparisons.
7020 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
7021 bool Swap = false, Invert = false, FlipSigns = false;
7023 switch (VT.getSimpleVT().SimpleTy) {
7026 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
7028 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
7030 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
7031 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
7034 switch (SetCCOpcode) {
7036 case ISD::SETNE: Invert = true;
7037 case ISD::SETEQ: Opc = EQOpc; break;
7038 case ISD::SETLT: Swap = true;
7039 case ISD::SETGT: Opc = GTOpc; break;
7040 case ISD::SETGE: Swap = true;
7041 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
7042 case ISD::SETULT: Swap = true;
7043 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
7044 case ISD::SETUGE: Swap = true;
7045 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
7048 std::swap(Op0, Op1);
7050 // Since SSE has no unsigned integer comparisons, we need to flip the sign
7051 // bits of the inputs before performing those operations.
7053 EVT EltVT = VT.getVectorElementType();
7054 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
7056 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
7057 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
7059 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
7060 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
7063 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
7065 // If the logical-not of the result is required, perform that now.
7067 Result = DAG.getNOT(dl, Result, VT);
7072 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
7073 static bool isX86LogicalCmp(SDValue Op) {
7074 unsigned Opc = Op.getNode()->getOpcode();
7075 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
7077 if (Op.getResNo() == 1 &&
7078 (Opc == X86ISD::ADD ||
7079 Opc == X86ISD::SUB ||
7080 Opc == X86ISD::SMUL ||
7081 Opc == X86ISD::UMUL ||
7082 Opc == X86ISD::INC ||
7083 Opc == X86ISD::DEC ||
7084 Opc == X86ISD::OR ||
7085 Opc == X86ISD::XOR ||
7086 Opc == X86ISD::AND))
7092 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7093 bool addTest = true;
7094 SDValue Cond = Op.getOperand(0);
7095 DebugLoc dl = Op.getDebugLoc();
7098 if (Cond.getOpcode() == ISD::SETCC) {
7099 SDValue NewCond = LowerSETCC(Cond, DAG);
7100 if (NewCond.getNode())
7104 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
7105 SDValue Op1 = Op.getOperand(1);
7106 SDValue Op2 = Op.getOperand(2);
7107 if (Cond.getOpcode() == X86ISD::SETCC &&
7108 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
7109 SDValue Cmp = Cond.getOperand(1);
7110 if (Cmp.getOpcode() == X86ISD::CMP) {
7111 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
7112 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
7113 ConstantSDNode *RHSC =
7114 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
7115 if (N1C && N1C->isAllOnesValue() &&
7116 N2C && N2C->isNullValue() &&
7117 RHSC && RHSC->isNullValue()) {
7118 SDValue CmpOp0 = Cmp.getOperand(0);
7119 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7120 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
7121 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
7122 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
7127 // Look pass (and (setcc_carry (cmp ...)), 1).
7128 if (Cond.getOpcode() == ISD::AND &&
7129 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7130 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7131 if (C && C->getAPIntValue() == 1)
7132 Cond = Cond.getOperand(0);
7135 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7136 // setting operand in place of the X86ISD::SETCC.
7137 if (Cond.getOpcode() == X86ISD::SETCC ||
7138 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7139 CC = Cond.getOperand(0);
7141 SDValue Cmp = Cond.getOperand(1);
7142 unsigned Opc = Cmp.getOpcode();
7143 EVT VT = Op.getValueType();
7145 bool IllegalFPCMov = false;
7146 if (VT.isFloatingPoint() && !VT.isVector() &&
7147 !isScalarFPTypeInSSEReg(VT)) // FPStack?
7148 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
7150 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
7151 Opc == X86ISD::BT) { // FIXME
7158 // Look pass the truncate.
7159 if (Cond.getOpcode() == ISD::TRUNCATE)
7160 Cond = Cond.getOperand(0);
7162 // We know the result of AND is compared against zero. Try to match
7164 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7165 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7166 if (NewSetCC.getNode()) {
7167 CC = NewSetCC.getOperand(0);
7168 Cond = NewSetCC.getOperand(1);
7175 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7176 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7179 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
7180 // condition is true.
7181 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
7182 SDValue Ops[] = { Op2, Op1, CC, Cond };
7183 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
7186 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
7187 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
7188 // from the AND / OR.
7189 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
7190 Opc = Op.getOpcode();
7191 if (Opc != ISD::OR && Opc != ISD::AND)
7193 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7194 Op.getOperand(0).hasOneUse() &&
7195 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
7196 Op.getOperand(1).hasOneUse());
7199 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
7200 // 1 and that the SETCC node has a single use.
7201 static bool isXor1OfSetCC(SDValue Op) {
7202 if (Op.getOpcode() != ISD::XOR)
7204 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7205 if (N1C && N1C->getAPIntValue() == 1) {
7206 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7207 Op.getOperand(0).hasOneUse();
7212 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
7213 bool addTest = true;
7214 SDValue Chain = Op.getOperand(0);
7215 SDValue Cond = Op.getOperand(1);
7216 SDValue Dest = Op.getOperand(2);
7217 DebugLoc dl = Op.getDebugLoc();
7220 if (Cond.getOpcode() == ISD::SETCC) {
7221 SDValue NewCond = LowerSETCC(Cond, DAG);
7222 if (NewCond.getNode())
7226 // FIXME: LowerXALUO doesn't handle these!!
7227 else if (Cond.getOpcode() == X86ISD::ADD ||
7228 Cond.getOpcode() == X86ISD::SUB ||
7229 Cond.getOpcode() == X86ISD::SMUL ||
7230 Cond.getOpcode() == X86ISD::UMUL)
7231 Cond = LowerXALUO(Cond, DAG);
7234 // Look pass (and (setcc_carry (cmp ...)), 1).
7235 if (Cond.getOpcode() == ISD::AND &&
7236 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7237 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7238 if (C && C->getAPIntValue() == 1)
7239 Cond = Cond.getOperand(0);
7242 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7243 // setting operand in place of the X86ISD::SETCC.
7244 if (Cond.getOpcode() == X86ISD::SETCC ||
7245 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7246 CC = Cond.getOperand(0);
7248 SDValue Cmp = Cond.getOperand(1);
7249 unsigned Opc = Cmp.getOpcode();
7250 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
7251 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
7255 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
7259 // These can only come from an arithmetic instruction with overflow,
7260 // e.g. SADDO, UADDO.
7261 Cond = Cond.getNode()->getOperand(1);
7268 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
7269 SDValue Cmp = Cond.getOperand(0).getOperand(1);
7270 if (CondOpc == ISD::OR) {
7271 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
7272 // two branches instead of an explicit OR instruction with a
7274 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7275 isX86LogicalCmp(Cmp)) {
7276 CC = Cond.getOperand(0).getOperand(0);
7277 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7278 Chain, Dest, CC, Cmp);
7279 CC = Cond.getOperand(1).getOperand(0);
7283 } else { // ISD::AND
7284 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
7285 // two branches instead of an explicit AND instruction with a
7286 // separate test. However, we only do this if this block doesn't
7287 // have a fall-through edge, because this requires an explicit
7288 // jmp when the condition is false.
7289 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7290 isX86LogicalCmp(Cmp) &&
7291 Op.getNode()->hasOneUse()) {
7292 X86::CondCode CCode =
7293 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7294 CCode = X86::GetOppositeBranchCondition(CCode);
7295 CC = DAG.getConstant(CCode, MVT::i8);
7296 SDNode *User = *Op.getNode()->use_begin();
7297 // Look for an unconditional branch following this conditional branch.
7298 // We need this because we need to reverse the successors in order
7299 // to implement FCMP_OEQ.
7300 if (User->getOpcode() == ISD::BR) {
7301 SDValue FalseBB = User->getOperand(1);
7303 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
7304 assert(NewBR == User);
7308 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7309 Chain, Dest, CC, Cmp);
7310 X86::CondCode CCode =
7311 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
7312 CCode = X86::GetOppositeBranchCondition(CCode);
7313 CC = DAG.getConstant(CCode, MVT::i8);
7319 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
7320 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
7321 // It should be transformed during dag combiner except when the condition
7322 // is set by a arithmetics with overflow node.
7323 X86::CondCode CCode =
7324 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7325 CCode = X86::GetOppositeBranchCondition(CCode);
7326 CC = DAG.getConstant(CCode, MVT::i8);
7327 Cond = Cond.getOperand(0).getOperand(1);
7333 // Look pass the truncate.
7334 if (Cond.getOpcode() == ISD::TRUNCATE)
7335 Cond = Cond.getOperand(0);
7337 // We know the result of AND is compared against zero. Try to match
7339 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7340 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7341 if (NewSetCC.getNode()) {
7342 CC = NewSetCC.getOperand(0);
7343 Cond = NewSetCC.getOperand(1);
7350 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7351 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7353 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7354 Chain, Dest, CC, Cond);
7358 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
7359 // Calls to _alloca is needed to probe the stack when allocating more than 4k
7360 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
7361 // that the guard pages used by the OS virtual memory manager are allocated in
7362 // correct sequence.
7364 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
7365 SelectionDAG &DAG) const {
7366 assert(Subtarget->isTargetCygMing() &&
7367 "This should be used only on Cygwin/Mingw targets");
7368 DebugLoc dl = Op.getDebugLoc();
7371 SDValue Chain = Op.getOperand(0);
7372 SDValue Size = Op.getOperand(1);
7373 // FIXME: Ensure alignment here
7377 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
7379 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
7380 Flag = Chain.getValue(1);
7382 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
7384 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
7385 Flag = Chain.getValue(1);
7387 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
7389 SDValue Ops1[2] = { Chain.getValue(0), Chain };
7390 return DAG.getMergeValues(Ops1, 2, dl);
7393 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
7394 MachineFunction &MF = DAG.getMachineFunction();
7395 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
7397 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7398 DebugLoc dl = Op.getDebugLoc();
7400 if (!Subtarget->is64Bit()) {
7401 // vastart just stores the address of the VarArgsFrameIndex slot into the
7402 // memory location argument.
7403 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7405 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
7410 // gp_offset (0 - 6 * 8)
7411 // fp_offset (48 - 48 + 8 * 16)
7412 // overflow_arg_area (point to parameters coming in memory).
7414 SmallVector<SDValue, 8> MemOps;
7415 SDValue FIN = Op.getOperand(1);
7417 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
7418 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
7420 FIN, SV, 0, false, false, 0);
7421 MemOps.push_back(Store);
7424 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7425 FIN, DAG.getIntPtrConstant(4));
7426 Store = DAG.getStore(Op.getOperand(0), dl,
7427 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
7429 FIN, SV, 4, false, false, 0);
7430 MemOps.push_back(Store);
7432 // Store ptr to overflow_arg_area
7433 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7434 FIN, DAG.getIntPtrConstant(4));
7435 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7437 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 8,
7439 MemOps.push_back(Store);
7441 // Store ptr to reg_save_area.
7442 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7443 FIN, DAG.getIntPtrConstant(8));
7444 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
7446 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 16,
7448 MemOps.push_back(Store);
7449 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7450 &MemOps[0], MemOps.size());
7453 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
7454 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7455 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
7457 report_fatal_error("VAArgInst is not yet implemented for x86-64!");
7461 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
7462 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7463 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
7464 SDValue Chain = Op.getOperand(0);
7465 SDValue DstPtr = Op.getOperand(1);
7466 SDValue SrcPtr = Op.getOperand(2);
7467 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
7468 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7469 DebugLoc dl = Op.getDebugLoc();
7471 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
7472 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
7473 false, DstSV, 0, SrcSV, 0);
7477 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
7478 DebugLoc dl = Op.getDebugLoc();
7479 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7481 default: return SDValue(); // Don't custom lower most intrinsics.
7482 // Comparison intrinsics.
7483 case Intrinsic::x86_sse_comieq_ss:
7484 case Intrinsic::x86_sse_comilt_ss:
7485 case Intrinsic::x86_sse_comile_ss:
7486 case Intrinsic::x86_sse_comigt_ss:
7487 case Intrinsic::x86_sse_comige_ss:
7488 case Intrinsic::x86_sse_comineq_ss:
7489 case Intrinsic::x86_sse_ucomieq_ss:
7490 case Intrinsic::x86_sse_ucomilt_ss:
7491 case Intrinsic::x86_sse_ucomile_ss:
7492 case Intrinsic::x86_sse_ucomigt_ss:
7493 case Intrinsic::x86_sse_ucomige_ss:
7494 case Intrinsic::x86_sse_ucomineq_ss:
7495 case Intrinsic::x86_sse2_comieq_sd:
7496 case Intrinsic::x86_sse2_comilt_sd:
7497 case Intrinsic::x86_sse2_comile_sd:
7498 case Intrinsic::x86_sse2_comigt_sd:
7499 case Intrinsic::x86_sse2_comige_sd:
7500 case Intrinsic::x86_sse2_comineq_sd:
7501 case Intrinsic::x86_sse2_ucomieq_sd:
7502 case Intrinsic::x86_sse2_ucomilt_sd:
7503 case Intrinsic::x86_sse2_ucomile_sd:
7504 case Intrinsic::x86_sse2_ucomigt_sd:
7505 case Intrinsic::x86_sse2_ucomige_sd:
7506 case Intrinsic::x86_sse2_ucomineq_sd: {
7508 ISD::CondCode CC = ISD::SETCC_INVALID;
7511 case Intrinsic::x86_sse_comieq_ss:
7512 case Intrinsic::x86_sse2_comieq_sd:
7516 case Intrinsic::x86_sse_comilt_ss:
7517 case Intrinsic::x86_sse2_comilt_sd:
7521 case Intrinsic::x86_sse_comile_ss:
7522 case Intrinsic::x86_sse2_comile_sd:
7526 case Intrinsic::x86_sse_comigt_ss:
7527 case Intrinsic::x86_sse2_comigt_sd:
7531 case Intrinsic::x86_sse_comige_ss:
7532 case Intrinsic::x86_sse2_comige_sd:
7536 case Intrinsic::x86_sse_comineq_ss:
7537 case Intrinsic::x86_sse2_comineq_sd:
7541 case Intrinsic::x86_sse_ucomieq_ss:
7542 case Intrinsic::x86_sse2_ucomieq_sd:
7543 Opc = X86ISD::UCOMI;
7546 case Intrinsic::x86_sse_ucomilt_ss:
7547 case Intrinsic::x86_sse2_ucomilt_sd:
7548 Opc = X86ISD::UCOMI;
7551 case Intrinsic::x86_sse_ucomile_ss:
7552 case Intrinsic::x86_sse2_ucomile_sd:
7553 Opc = X86ISD::UCOMI;
7556 case Intrinsic::x86_sse_ucomigt_ss:
7557 case Intrinsic::x86_sse2_ucomigt_sd:
7558 Opc = X86ISD::UCOMI;
7561 case Intrinsic::x86_sse_ucomige_ss:
7562 case Intrinsic::x86_sse2_ucomige_sd:
7563 Opc = X86ISD::UCOMI;
7566 case Intrinsic::x86_sse_ucomineq_ss:
7567 case Intrinsic::x86_sse2_ucomineq_sd:
7568 Opc = X86ISD::UCOMI;
7573 SDValue LHS = Op.getOperand(1);
7574 SDValue RHS = Op.getOperand(2);
7575 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
7576 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
7577 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
7578 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7579 DAG.getConstant(X86CC, MVT::i8), Cond);
7580 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7582 // ptest and testp intrinsics. The intrinsic these come from are designed to
7583 // return an integer value, not just an instruction so lower it to the ptest
7584 // or testp pattern and a setcc for the result.
7585 case Intrinsic::x86_sse41_ptestz:
7586 case Intrinsic::x86_sse41_ptestc:
7587 case Intrinsic::x86_sse41_ptestnzc:
7588 case Intrinsic::x86_avx_ptestz_256:
7589 case Intrinsic::x86_avx_ptestc_256:
7590 case Intrinsic::x86_avx_ptestnzc_256:
7591 case Intrinsic::x86_avx_vtestz_ps:
7592 case Intrinsic::x86_avx_vtestc_ps:
7593 case Intrinsic::x86_avx_vtestnzc_ps:
7594 case Intrinsic::x86_avx_vtestz_pd:
7595 case Intrinsic::x86_avx_vtestc_pd:
7596 case Intrinsic::x86_avx_vtestnzc_pd:
7597 case Intrinsic::x86_avx_vtestz_ps_256:
7598 case Intrinsic::x86_avx_vtestc_ps_256:
7599 case Intrinsic::x86_avx_vtestnzc_ps_256:
7600 case Intrinsic::x86_avx_vtestz_pd_256:
7601 case Intrinsic::x86_avx_vtestc_pd_256:
7602 case Intrinsic::x86_avx_vtestnzc_pd_256: {
7603 bool IsTestPacked = false;
7606 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
7607 case Intrinsic::x86_avx_vtestz_ps:
7608 case Intrinsic::x86_avx_vtestz_pd:
7609 case Intrinsic::x86_avx_vtestz_ps_256:
7610 case Intrinsic::x86_avx_vtestz_pd_256:
7611 IsTestPacked = true; // Fallthrough
7612 case Intrinsic::x86_sse41_ptestz:
7613 case Intrinsic::x86_avx_ptestz_256:
7615 X86CC = X86::COND_E;
7617 case Intrinsic::x86_avx_vtestc_ps:
7618 case Intrinsic::x86_avx_vtestc_pd:
7619 case Intrinsic::x86_avx_vtestc_ps_256:
7620 case Intrinsic::x86_avx_vtestc_pd_256:
7621 IsTestPacked = true; // Fallthrough
7622 case Intrinsic::x86_sse41_ptestc:
7623 case Intrinsic::x86_avx_ptestc_256:
7625 X86CC = X86::COND_B;
7627 case Intrinsic::x86_avx_vtestnzc_ps:
7628 case Intrinsic::x86_avx_vtestnzc_pd:
7629 case Intrinsic::x86_avx_vtestnzc_ps_256:
7630 case Intrinsic::x86_avx_vtestnzc_pd_256:
7631 IsTestPacked = true; // Fallthrough
7632 case Intrinsic::x86_sse41_ptestnzc:
7633 case Intrinsic::x86_avx_ptestnzc_256:
7635 X86CC = X86::COND_A;
7639 SDValue LHS = Op.getOperand(1);
7640 SDValue RHS = Op.getOperand(2);
7641 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
7642 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
7643 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
7644 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
7645 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7648 // Fix vector shift instructions where the last operand is a non-immediate
7650 case Intrinsic::x86_sse2_pslli_w:
7651 case Intrinsic::x86_sse2_pslli_d:
7652 case Intrinsic::x86_sse2_pslli_q:
7653 case Intrinsic::x86_sse2_psrli_w:
7654 case Intrinsic::x86_sse2_psrli_d:
7655 case Intrinsic::x86_sse2_psrli_q:
7656 case Intrinsic::x86_sse2_psrai_w:
7657 case Intrinsic::x86_sse2_psrai_d:
7658 case Intrinsic::x86_mmx_pslli_w:
7659 case Intrinsic::x86_mmx_pslli_d:
7660 case Intrinsic::x86_mmx_pslli_q:
7661 case Intrinsic::x86_mmx_psrli_w:
7662 case Intrinsic::x86_mmx_psrli_d:
7663 case Intrinsic::x86_mmx_psrli_q:
7664 case Intrinsic::x86_mmx_psrai_w:
7665 case Intrinsic::x86_mmx_psrai_d: {
7666 SDValue ShAmt = Op.getOperand(2);
7667 if (isa<ConstantSDNode>(ShAmt))
7670 unsigned NewIntNo = 0;
7671 EVT ShAmtVT = MVT::v4i32;
7673 case Intrinsic::x86_sse2_pslli_w:
7674 NewIntNo = Intrinsic::x86_sse2_psll_w;
7676 case Intrinsic::x86_sse2_pslli_d:
7677 NewIntNo = Intrinsic::x86_sse2_psll_d;
7679 case Intrinsic::x86_sse2_pslli_q:
7680 NewIntNo = Intrinsic::x86_sse2_psll_q;
7682 case Intrinsic::x86_sse2_psrli_w:
7683 NewIntNo = Intrinsic::x86_sse2_psrl_w;
7685 case Intrinsic::x86_sse2_psrli_d:
7686 NewIntNo = Intrinsic::x86_sse2_psrl_d;
7688 case Intrinsic::x86_sse2_psrli_q:
7689 NewIntNo = Intrinsic::x86_sse2_psrl_q;
7691 case Intrinsic::x86_sse2_psrai_w:
7692 NewIntNo = Intrinsic::x86_sse2_psra_w;
7694 case Intrinsic::x86_sse2_psrai_d:
7695 NewIntNo = Intrinsic::x86_sse2_psra_d;
7698 ShAmtVT = MVT::v2i32;
7700 case Intrinsic::x86_mmx_pslli_w:
7701 NewIntNo = Intrinsic::x86_mmx_psll_w;
7703 case Intrinsic::x86_mmx_pslli_d:
7704 NewIntNo = Intrinsic::x86_mmx_psll_d;
7706 case Intrinsic::x86_mmx_pslli_q:
7707 NewIntNo = Intrinsic::x86_mmx_psll_q;
7709 case Intrinsic::x86_mmx_psrli_w:
7710 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7712 case Intrinsic::x86_mmx_psrli_d:
7713 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7715 case Intrinsic::x86_mmx_psrli_q:
7716 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7718 case Intrinsic::x86_mmx_psrai_w:
7719 NewIntNo = Intrinsic::x86_mmx_psra_w;
7721 case Intrinsic::x86_mmx_psrai_d:
7722 NewIntNo = Intrinsic::x86_mmx_psra_d;
7724 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7730 // The vector shift intrinsics with scalars uses 32b shift amounts but
7731 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7735 ShOps[1] = DAG.getConstant(0, MVT::i32);
7736 if (ShAmtVT == MVT::v4i32) {
7737 ShOps[2] = DAG.getUNDEF(MVT::i32);
7738 ShOps[3] = DAG.getUNDEF(MVT::i32);
7739 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7741 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7744 EVT VT = Op.getValueType();
7745 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
7746 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7747 DAG.getConstant(NewIntNo, MVT::i32),
7748 Op.getOperand(1), ShAmt);
7753 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7754 SelectionDAG &DAG) const {
7755 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7756 MFI->setReturnAddressIsTaken(true);
7758 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7759 DebugLoc dl = Op.getDebugLoc();
7762 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7764 DAG.getConstant(TD->getPointerSize(),
7765 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7766 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7767 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7769 NULL, 0, false, false, 0);
7772 // Just load the return address.
7773 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7774 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7775 RetAddrFI, NULL, 0, false, false, 0);
7778 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7779 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7780 MFI->setFrameAddressIsTaken(true);
7782 EVT VT = Op.getValueType();
7783 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7784 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7785 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7786 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7788 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
7793 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7794 SelectionDAG &DAG) const {
7795 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7798 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
7799 MachineFunction &MF = DAG.getMachineFunction();
7800 SDValue Chain = Op.getOperand(0);
7801 SDValue Offset = Op.getOperand(1);
7802 SDValue Handler = Op.getOperand(2);
7803 DebugLoc dl = Op.getDebugLoc();
7805 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
7806 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7808 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7810 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
7811 DAG.getIntPtrConstant(TD->getPointerSize()));
7812 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7813 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0, false, false, 0);
7814 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7815 MF.getRegInfo().addLiveOut(StoreAddrReg);
7817 return DAG.getNode(X86ISD::EH_RETURN, dl,
7819 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7822 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7823 SelectionDAG &DAG) const {
7824 SDValue Root = Op.getOperand(0);
7825 SDValue Trmp = Op.getOperand(1); // trampoline
7826 SDValue FPtr = Op.getOperand(2); // nested function
7827 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7828 DebugLoc dl = Op.getDebugLoc();
7830 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7832 if (Subtarget->is64Bit()) {
7833 SDValue OutChains[6];
7835 // Large code-model.
7836 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7837 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7839 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7840 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7842 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7844 // Load the pointer to the nested function into R11.
7845 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7846 SDValue Addr = Trmp;
7847 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7848 Addr, TrmpAddr, 0, false, false, 0);
7850 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7851 DAG.getConstant(2, MVT::i64));
7852 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2,
7855 // Load the 'nest' parameter value into R10.
7856 // R10 is specified in X86CallingConv.td
7857 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7858 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7859 DAG.getConstant(10, MVT::i64));
7860 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7861 Addr, TrmpAddr, 10, false, false, 0);
7863 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7864 DAG.getConstant(12, MVT::i64));
7865 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12,
7868 // Jump to the nested function.
7869 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7870 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7871 DAG.getConstant(20, MVT::i64));
7872 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7873 Addr, TrmpAddr, 20, false, false, 0);
7875 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
7876 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7877 DAG.getConstant(22, MVT::i64));
7878 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
7879 TrmpAddr, 22, false, false, 0);
7882 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
7883 return DAG.getMergeValues(Ops, 2, dl);
7885 const Function *Func =
7886 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
7887 CallingConv::ID CC = Func->getCallingConv();
7892 llvm_unreachable("Unsupported calling convention");
7893 case CallingConv::C:
7894 case CallingConv::X86_StdCall: {
7895 // Pass 'nest' parameter in ECX.
7896 // Must be kept in sync with X86CallingConv.td
7899 // Check that ECX wasn't needed by an 'inreg' parameter.
7900 const FunctionType *FTy = Func->getFunctionType();
7901 const AttrListPtr &Attrs = Func->getAttributes();
7903 if (!Attrs.isEmpty() && !Func->isVarArg()) {
7904 unsigned InRegCount = 0;
7907 for (FunctionType::param_iterator I = FTy->param_begin(),
7908 E = FTy->param_end(); I != E; ++I, ++Idx)
7909 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
7910 // FIXME: should only count parameters that are lowered to integers.
7911 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
7913 if (InRegCount > 2) {
7914 report_fatal_error("Nest register in use - reduce number of inreg"
7920 case CallingConv::X86_FastCall:
7921 case CallingConv::X86_ThisCall:
7922 case CallingConv::Fast:
7923 // Pass 'nest' parameter in EAX.
7924 // Must be kept in sync with X86CallingConv.td
7929 SDValue OutChains[4];
7932 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7933 DAG.getConstant(10, MVT::i32));
7934 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
7936 // This is storing the opcode for MOV32ri.
7937 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
7938 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
7939 OutChains[0] = DAG.getStore(Root, dl,
7940 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
7941 Trmp, TrmpAddr, 0, false, false, 0);
7943 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7944 DAG.getConstant(1, MVT::i32));
7945 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1,
7948 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
7949 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7950 DAG.getConstant(5, MVT::i32));
7951 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
7952 TrmpAddr, 5, false, false, 1);
7954 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
7955 DAG.getConstant(6, MVT::i32));
7956 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6,
7960 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
7961 return DAG.getMergeValues(Ops, 2, dl);
7965 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
7966 SelectionDAG &DAG) const {
7968 The rounding mode is in bits 11:10 of FPSR, and has the following
7975 FLT_ROUNDS, on the other hand, expects the following:
7982 To perform the conversion, we do:
7983 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
7986 MachineFunction &MF = DAG.getMachineFunction();
7987 const TargetMachine &TM = MF.getTarget();
7988 const TargetFrameInfo &TFI = *TM.getFrameInfo();
7989 unsigned StackAlignment = TFI.getStackAlignment();
7990 EVT VT = Op.getValueType();
7991 DebugLoc dl = Op.getDebugLoc();
7993 // Save FP Control Word to stack slot
7994 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
7995 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7997 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
7998 DAG.getEntryNode(), StackSlot);
8000 // Load FP Control Word from stack slot
8001 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0,
8004 // Transform as necessary
8006 DAG.getNode(ISD::SRL, dl, MVT::i16,
8007 DAG.getNode(ISD::AND, dl, MVT::i16,
8008 CWD, DAG.getConstant(0x800, MVT::i16)),
8009 DAG.getConstant(11, MVT::i8));
8011 DAG.getNode(ISD::SRL, dl, MVT::i16,
8012 DAG.getNode(ISD::AND, dl, MVT::i16,
8013 CWD, DAG.getConstant(0x400, MVT::i16)),
8014 DAG.getConstant(9, MVT::i8));
8017 DAG.getNode(ISD::AND, dl, MVT::i16,
8018 DAG.getNode(ISD::ADD, dl, MVT::i16,
8019 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
8020 DAG.getConstant(1, MVT::i16)),
8021 DAG.getConstant(3, MVT::i16));
8024 return DAG.getNode((VT.getSizeInBits() < 16 ?
8025 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
8028 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
8029 EVT VT = Op.getValueType();
8031 unsigned NumBits = VT.getSizeInBits();
8032 DebugLoc dl = Op.getDebugLoc();
8034 Op = Op.getOperand(0);
8035 if (VT == MVT::i8) {
8036 // Zero extend to i32 since there is not an i8 bsr.
8038 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8041 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
8042 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8043 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
8045 // If src is zero (i.e. bsr sets ZF), returns NumBits.
8048 DAG.getConstant(NumBits+NumBits-1, OpVT),
8049 DAG.getConstant(X86::COND_E, MVT::i8),
8052 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8054 // Finally xor with NumBits-1.
8055 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
8058 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8062 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
8063 EVT VT = Op.getValueType();
8065 unsigned NumBits = VT.getSizeInBits();
8066 DebugLoc dl = Op.getDebugLoc();
8068 Op = Op.getOperand(0);
8069 if (VT == MVT::i8) {
8071 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8074 // Issue a bsf (scan bits forward) which also sets EFLAGS.
8075 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8076 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
8078 // If src is zero (i.e. bsf sets ZF), returns NumBits.
8081 DAG.getConstant(NumBits, OpVT),
8082 DAG.getConstant(X86::COND_E, MVT::i8),
8085 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8088 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8092 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
8093 EVT VT = Op.getValueType();
8094 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
8095 DebugLoc dl = Op.getDebugLoc();
8097 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
8098 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
8099 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
8100 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
8101 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
8103 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
8104 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
8105 // return AloBlo + AloBhi + AhiBlo;
8107 SDValue A = Op.getOperand(0);
8108 SDValue B = Op.getOperand(1);
8110 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8111 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8112 A, DAG.getConstant(32, MVT::i32));
8113 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8114 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8115 B, DAG.getConstant(32, MVT::i32));
8116 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8117 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8119 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8120 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8122 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8123 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8125 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8126 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8127 AloBhi, DAG.getConstant(32, MVT::i32));
8128 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8129 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8130 AhiBlo, DAG.getConstant(32, MVT::i32));
8131 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
8132 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
8136 SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
8137 EVT VT = Op.getValueType();
8138 DebugLoc dl = Op.getDebugLoc();
8139 SDValue R = Op.getOperand(0);
8141 LLVMContext *Context = DAG.getContext();
8143 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later");
8145 if (VT == MVT::v4i32) {
8146 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8147 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8148 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
8150 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
8152 std::vector<Constant*> CV(4, CI);
8153 Constant *C = ConstantVector::get(CV);
8154 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8155 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8156 PseudoSourceValue::getConstantPool(), 0,
8159 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
8160 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, Op);
8161 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
8162 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
8164 if (VT == MVT::v16i8) {
8166 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8167 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8168 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
8170 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
8171 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
8173 std::vector<Constant*> CVM1(16, CM1);
8174 std::vector<Constant*> CVM2(16, CM2);
8175 Constant *C = ConstantVector::get(CVM1);
8176 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8177 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8178 PseudoSourceValue::getConstantPool(), 0,
8181 // r = pblendv(r, psllw(r & (char16)15, 4), a);
8182 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8183 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8184 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8185 DAG.getConstant(4, MVT::i32));
8186 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8187 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8190 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8192 C = ConstantVector::get(CVM2);
8193 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8194 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8195 PseudoSourceValue::getConstantPool(), 0, false, false, 16);
8197 // r = pblendv(r, psllw(r & (char16)63, 2), a);
8198 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8199 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8200 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8201 DAG.getConstant(2, MVT::i32));
8202 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8203 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8206 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8208 // return pblendv(r, r+r, a);
8209 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8210 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8211 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
8217 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
8218 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
8219 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
8220 // looks for this combo and may remove the "setcc" instruction if the "setcc"
8221 // has only one use.
8222 SDNode *N = Op.getNode();
8223 SDValue LHS = N->getOperand(0);
8224 SDValue RHS = N->getOperand(1);
8225 unsigned BaseOp = 0;
8227 DebugLoc dl = Op.getDebugLoc();
8229 switch (Op.getOpcode()) {
8230 default: llvm_unreachable("Unknown ovf instruction!");
8232 // A subtract of one will be selected as a INC. Note that INC doesn't
8233 // set CF, so we can't do this for UADDO.
8234 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8235 if (C->getAPIntValue() == 1) {
8236 BaseOp = X86ISD::INC;
8240 BaseOp = X86ISD::ADD;
8244 BaseOp = X86ISD::ADD;
8248 // A subtract of one will be selected as a DEC. Note that DEC doesn't
8249 // set CF, so we can't do this for USUBO.
8250 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8251 if (C->getAPIntValue() == 1) {
8252 BaseOp = X86ISD::DEC;
8256 BaseOp = X86ISD::SUB;
8260 BaseOp = X86ISD::SUB;
8264 BaseOp = X86ISD::SMUL;
8268 BaseOp = X86ISD::UMUL;
8273 // Also sets EFLAGS.
8274 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
8275 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
8278 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
8279 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
8281 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8285 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
8286 DebugLoc dl = Op.getDebugLoc();
8288 if (!Subtarget->hasSSE2()) {
8289 SDValue Chain = Op.getOperand(0);
8290 SDValue Zero = DAG.getConstant(0,
8291 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
8293 DAG.getRegister(X86::ESP, MVT::i32), // Base
8294 DAG.getTargetConstant(1, MVT::i8), // Scale
8295 DAG.getRegister(0, MVT::i32), // Index
8296 DAG.getTargetConstant(0, MVT::i32), // Disp
8297 DAG.getRegister(0, MVT::i32), // Segment.
8302 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
8303 array_lengthof(Ops));
8304 return SDValue(Res, 0);
8307 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
8309 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
8311 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8312 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
8313 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
8314 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
8316 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
8317 if (!Op1 && !Op2 && !Op3 && Op4)
8318 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
8320 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
8321 if (Op1 && !Op2 && !Op3 && !Op4)
8322 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
8324 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
8326 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
8329 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
8330 EVT T = Op.getValueType();
8331 DebugLoc dl = Op.getDebugLoc();
8334 switch(T.getSimpleVT().SimpleTy) {
8336 assert(false && "Invalid value type!");
8337 case MVT::i8: Reg = X86::AL; size = 1; break;
8338 case MVT::i16: Reg = X86::AX; size = 2; break;
8339 case MVT::i32: Reg = X86::EAX; size = 4; break;
8341 assert(Subtarget->is64Bit() && "Node not type legal!");
8342 Reg = X86::RAX; size = 8;
8345 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
8346 Op.getOperand(2), SDValue());
8347 SDValue Ops[] = { cpIn.getValue(0),
8350 DAG.getTargetConstant(size, MVT::i8),
8352 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8353 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
8355 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
8359 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
8360 SelectionDAG &DAG) const {
8361 assert(Subtarget->is64Bit() && "Result not type legalized?");
8362 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8363 SDValue TheChain = Op.getOperand(0);
8364 DebugLoc dl = Op.getDebugLoc();
8365 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8366 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
8367 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
8369 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
8370 DAG.getConstant(32, MVT::i8));
8372 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
8375 return DAG.getMergeValues(Ops, 2, dl);
8378 SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
8379 SelectionDAG &DAG) const {
8380 EVT SrcVT = Op.getOperand(0).getValueType();
8381 EVT DstVT = Op.getValueType();
8382 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
8383 Subtarget->hasMMX() && !DisableMMX) &&
8384 "Unexpected custom BIT_CONVERT");
8385 assert((DstVT == MVT::i64 ||
8386 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
8387 "Unexpected custom BIT_CONVERT");
8388 // i64 <=> MMX conversions are Legal.
8389 if (SrcVT==MVT::i64 && DstVT.isVector())
8391 if (DstVT==MVT::i64 && SrcVT.isVector())
8393 // MMX <=> MMX conversions are Legal.
8394 if (SrcVT.isVector() && DstVT.isVector())
8396 // All other conversions need to be expanded.
8399 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
8400 SDNode *Node = Op.getNode();
8401 DebugLoc dl = Node->getDebugLoc();
8402 EVT T = Node->getValueType(0);
8403 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
8404 DAG.getConstant(0, T), Node->getOperand(2));
8405 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
8406 cast<AtomicSDNode>(Node)->getMemoryVT(),
8407 Node->getOperand(0),
8408 Node->getOperand(1), negOp,
8409 cast<AtomicSDNode>(Node)->getSrcValue(),
8410 cast<AtomicSDNode>(Node)->getAlignment());
8413 /// LowerOperation - Provide custom lowering hooks for some operations.
8415 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8416 switch (Op.getOpcode()) {
8417 default: llvm_unreachable("Should not custom lower this!");
8418 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
8419 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
8420 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
8421 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
8422 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
8423 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
8424 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8425 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
8426 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
8427 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
8428 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
8429 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
8430 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
8431 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
8432 case ISD::SHL_PARTS:
8433 case ISD::SRA_PARTS:
8434 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
8435 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
8436 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
8437 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
8438 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
8439 case ISD::FABS: return LowerFABS(Op, DAG);
8440 case ISD::FNEG: return LowerFNEG(Op, DAG);
8441 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
8442 case ISD::SETCC: return LowerSETCC(Op, DAG);
8443 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
8444 case ISD::SELECT: return LowerSELECT(Op, DAG);
8445 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
8446 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
8447 case ISD::VASTART: return LowerVASTART(Op, DAG);
8448 case ISD::VAARG: return LowerVAARG(Op, DAG);
8449 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
8450 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
8451 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8452 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8453 case ISD::FRAME_TO_ARGS_OFFSET:
8454 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
8455 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
8456 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
8457 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
8458 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
8459 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
8460 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
8461 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
8462 case ISD::SHL: return LowerSHL(Op, DAG);
8468 case ISD::UMULO: return LowerXALUO(Op, DAG);
8469 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
8470 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
8474 void X86TargetLowering::
8475 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
8476 SelectionDAG &DAG, unsigned NewOp) const {
8477 EVT T = Node->getValueType(0);
8478 DebugLoc dl = Node->getDebugLoc();
8479 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
8481 SDValue Chain = Node->getOperand(0);
8482 SDValue In1 = Node->getOperand(1);
8483 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8484 Node->getOperand(2), DAG.getIntPtrConstant(0));
8485 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8486 Node->getOperand(2), DAG.getIntPtrConstant(1));
8487 SDValue Ops[] = { Chain, In1, In2L, In2H };
8488 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
8490 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
8491 cast<MemSDNode>(Node)->getMemOperand());
8492 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
8493 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8494 Results.push_back(Result.getValue(2));
8497 /// ReplaceNodeResults - Replace a node with an illegal result type
8498 /// with a new node built out of custom code.
8499 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
8500 SmallVectorImpl<SDValue>&Results,
8501 SelectionDAG &DAG) const {
8502 DebugLoc dl = N->getDebugLoc();
8503 switch (N->getOpcode()) {
8505 assert(false && "Do not know how to custom type legalize this operation!");
8507 case ISD::FP_TO_SINT: {
8508 std::pair<SDValue,SDValue> Vals =
8509 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
8510 SDValue FIST = Vals.first, StackSlot = Vals.second;
8511 if (FIST.getNode() != 0) {
8512 EVT VT = N->getValueType(0);
8513 // Return a load from the stack slot.
8514 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0,
8519 case ISD::READCYCLECOUNTER: {
8520 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8521 SDValue TheChain = N->getOperand(0);
8522 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8523 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
8525 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
8527 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
8528 SDValue Ops[] = { eax, edx };
8529 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
8530 Results.push_back(edx.getValue(1));
8533 case ISD::ATOMIC_CMP_SWAP: {
8534 EVT T = N->getValueType(0);
8535 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
8536 SDValue cpInL, cpInH;
8537 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8538 DAG.getConstant(0, MVT::i32));
8539 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8540 DAG.getConstant(1, MVT::i32));
8541 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
8542 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
8544 SDValue swapInL, swapInH;
8545 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8546 DAG.getConstant(0, MVT::i32));
8547 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8548 DAG.getConstant(1, MVT::i32));
8549 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
8551 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
8552 swapInL.getValue(1));
8553 SDValue Ops[] = { swapInH.getValue(0),
8555 swapInH.getValue(1) };
8556 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8557 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
8558 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
8559 MVT::i32, Result.getValue(1));
8560 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
8561 MVT::i32, cpOutL.getValue(2));
8562 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
8563 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8564 Results.push_back(cpOutH.getValue(1));
8567 case ISD::ATOMIC_LOAD_ADD:
8568 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
8570 case ISD::ATOMIC_LOAD_AND:
8571 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
8573 case ISD::ATOMIC_LOAD_NAND:
8574 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
8576 case ISD::ATOMIC_LOAD_OR:
8577 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
8579 case ISD::ATOMIC_LOAD_SUB:
8580 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
8582 case ISD::ATOMIC_LOAD_XOR:
8583 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
8585 case ISD::ATOMIC_SWAP:
8586 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
8591 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
8593 default: return NULL;
8594 case X86ISD::BSF: return "X86ISD::BSF";
8595 case X86ISD::BSR: return "X86ISD::BSR";
8596 case X86ISD::SHLD: return "X86ISD::SHLD";
8597 case X86ISD::SHRD: return "X86ISD::SHRD";
8598 case X86ISD::FAND: return "X86ISD::FAND";
8599 case X86ISD::FOR: return "X86ISD::FOR";
8600 case X86ISD::FXOR: return "X86ISD::FXOR";
8601 case X86ISD::FSRL: return "X86ISD::FSRL";
8602 case X86ISD::FILD: return "X86ISD::FILD";
8603 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
8604 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
8605 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
8606 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
8607 case X86ISD::FLD: return "X86ISD::FLD";
8608 case X86ISD::FST: return "X86ISD::FST";
8609 case X86ISD::CALL: return "X86ISD::CALL";
8610 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
8611 case X86ISD::BT: return "X86ISD::BT";
8612 case X86ISD::CMP: return "X86ISD::CMP";
8613 case X86ISD::COMI: return "X86ISD::COMI";
8614 case X86ISD::UCOMI: return "X86ISD::UCOMI";
8615 case X86ISD::SETCC: return "X86ISD::SETCC";
8616 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
8617 case X86ISD::CMOV: return "X86ISD::CMOV";
8618 case X86ISD::BRCOND: return "X86ISD::BRCOND";
8619 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
8620 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
8621 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
8622 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
8623 case X86ISD::Wrapper: return "X86ISD::Wrapper";
8624 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
8625 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
8626 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
8627 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
8628 case X86ISD::PINSRB: return "X86ISD::PINSRB";
8629 case X86ISD::PINSRW: return "X86ISD::PINSRW";
8630 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
8631 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
8632 case X86ISD::FMAX: return "X86ISD::FMAX";
8633 case X86ISD::FMIN: return "X86ISD::FMIN";
8634 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
8635 case X86ISD::FRCP: return "X86ISD::FRCP";
8636 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
8637 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
8638 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
8639 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
8640 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
8641 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
8642 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
8643 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
8644 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
8645 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
8646 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
8647 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
8648 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
8649 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
8650 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
8651 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
8652 case X86ISD::VSHL: return "X86ISD::VSHL";
8653 case X86ISD::VSRL: return "X86ISD::VSRL";
8654 case X86ISD::CMPPD: return "X86ISD::CMPPD";
8655 case X86ISD::CMPPS: return "X86ISD::CMPPS";
8656 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
8657 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
8658 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
8659 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
8660 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
8661 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
8662 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
8663 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
8664 case X86ISD::ADD: return "X86ISD::ADD";
8665 case X86ISD::SUB: return "X86ISD::SUB";
8666 case X86ISD::SMUL: return "X86ISD::SMUL";
8667 case X86ISD::UMUL: return "X86ISD::UMUL";
8668 case X86ISD::INC: return "X86ISD::INC";
8669 case X86ISD::DEC: return "X86ISD::DEC";
8670 case X86ISD::OR: return "X86ISD::OR";
8671 case X86ISD::XOR: return "X86ISD::XOR";
8672 case X86ISD::AND: return "X86ISD::AND";
8673 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
8674 case X86ISD::PTEST: return "X86ISD::PTEST";
8675 case X86ISD::TESTP: return "X86ISD::TESTP";
8676 case X86ISD::PALIGN: return "X86ISD::PALIGN";
8677 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
8678 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
8679 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
8680 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
8681 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
8682 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
8683 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
8684 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
8685 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
8686 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
8687 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
8688 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
8689 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
8690 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
8691 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
8692 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
8693 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
8694 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
8695 case X86ISD::MOVSD: return "X86ISD::MOVSD";
8696 case X86ISD::MOVSS: return "X86ISD::MOVSS";
8697 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
8698 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
8699 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
8700 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
8701 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
8702 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
8703 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
8704 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
8705 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
8706 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
8707 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
8708 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
8709 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
8710 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
8714 // isLegalAddressingMode - Return true if the addressing mode represented
8715 // by AM is legal for this target, for a load/store of the specified type.
8716 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
8717 const Type *Ty) const {
8718 // X86 supports extremely general addressing modes.
8719 CodeModel::Model M = getTargetMachine().getCodeModel();
8720 Reloc::Model R = getTargetMachine().getRelocationModel();
8722 // X86 allows a sign-extended 32-bit immediate field as a displacement.
8723 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
8728 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
8730 // If a reference to this global requires an extra load, we can't fold it.
8731 if (isGlobalStubReference(GVFlags))
8734 // If BaseGV requires a register for the PIC base, we cannot also have a
8735 // BaseReg specified.
8736 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
8739 // If lower 4G is not available, then we must use rip-relative addressing.
8740 if ((M != CodeModel::Small || R != Reloc::Static) &&
8741 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
8751 // These scales always work.
8756 // These scales are formed with basereg+scalereg. Only accept if there is
8761 default: // Other stuff never works.
8769 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
8770 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8772 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8773 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8774 if (NumBits1 <= NumBits2)
8779 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8780 if (!VT1.isInteger() || !VT2.isInteger())
8782 unsigned NumBits1 = VT1.getSizeInBits();
8783 unsigned NumBits2 = VT2.getSizeInBits();
8784 if (NumBits1 <= NumBits2)
8789 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
8790 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8791 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
8794 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
8795 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8796 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
8799 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
8800 // i16 instructions are longer (0x66 prefix) and potentially slower.
8801 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
8804 /// isShuffleMaskLegal - Targets can use this to indicate that they only
8805 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
8806 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
8807 /// are assumed to be legal.
8809 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
8811 // Very little shuffling can be done for 64-bit vectors right now.
8812 if (VT.getSizeInBits() == 64)
8813 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
8815 // FIXME: pshufb, blends, shifts.
8816 return (VT.getVectorNumElements() == 2 ||
8817 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
8818 isMOVLMask(M, VT) ||
8819 isSHUFPMask(M, VT) ||
8820 isPSHUFDMask(M, VT) ||
8821 isPSHUFHWMask(M, VT) ||
8822 isPSHUFLWMask(M, VT) ||
8823 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
8824 isUNPCKLMask(M, VT) ||
8825 isUNPCKHMask(M, VT) ||
8826 isUNPCKL_v_undef_Mask(M, VT) ||
8827 isUNPCKH_v_undef_Mask(M, VT));
8831 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
8833 unsigned NumElts = VT.getVectorNumElements();
8834 // FIXME: This collection of masks seems suspect.
8837 if (NumElts == 4 && VT.getSizeInBits() == 128) {
8838 return (isMOVLMask(Mask, VT) ||
8839 isCommutedMOVLMask(Mask, VT, true) ||
8840 isSHUFPMask(Mask, VT) ||
8841 isCommutedSHUFPMask(Mask, VT));
8846 //===----------------------------------------------------------------------===//
8847 // X86 Scheduler Hooks
8848 //===----------------------------------------------------------------------===//
8850 // private utility function
8852 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
8853 MachineBasicBlock *MBB,
8860 TargetRegisterClass *RC,
8861 bool invSrc) const {
8862 // For the atomic bitwise operator, we generate
8865 // ld t1 = [bitinstr.addr]
8866 // op t2 = t1, [bitinstr.val]
8868 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
8870 // fallthrough -->nextMBB
8871 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8872 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8873 MachineFunction::iterator MBBIter = MBB;
8876 /// First build the CFG
8877 MachineFunction *F = MBB->getParent();
8878 MachineBasicBlock *thisMBB = MBB;
8879 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8880 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8881 F->insert(MBBIter, newMBB);
8882 F->insert(MBBIter, nextMBB);
8884 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8885 nextMBB->splice(nextMBB->begin(), thisMBB,
8886 llvm::next(MachineBasicBlock::iterator(bInstr)),
8888 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
8890 // Update thisMBB to fall through to newMBB
8891 thisMBB->addSuccessor(newMBB);
8893 // newMBB jumps to itself and fall through to nextMBB
8894 newMBB->addSuccessor(nextMBB);
8895 newMBB->addSuccessor(newMBB);
8897 // Insert instructions into newMBB based on incoming instruction
8898 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
8899 "unexpected number of operands");
8900 DebugLoc dl = bInstr->getDebugLoc();
8901 MachineOperand& destOper = bInstr->getOperand(0);
8902 MachineOperand* argOpers[2 + X86::AddrNumOperands];
8903 int numArgs = bInstr->getNumOperands() - 1;
8904 for (int i=0; i < numArgs; ++i)
8905 argOpers[i] = &bInstr->getOperand(i+1);
8907 // x86 address has 4 operands: base, index, scale, and displacement
8908 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
8909 int valArgIndx = lastAddrIndx + 1;
8911 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
8912 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
8913 for (int i=0; i <= lastAddrIndx; ++i)
8914 (*MIB).addOperand(*argOpers[i]);
8916 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
8918 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
8923 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
8924 assert((argOpers[valArgIndx]->isReg() ||
8925 argOpers[valArgIndx]->isImm()) &&
8927 if (argOpers[valArgIndx]->isReg())
8928 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
8930 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
8932 (*MIB).addOperand(*argOpers[valArgIndx]);
8934 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
8937 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
8938 for (int i=0; i <= lastAddrIndx; ++i)
8939 (*MIB).addOperand(*argOpers[i]);
8941 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
8942 (*MIB).setMemRefs(bInstr->memoperands_begin(),
8943 bInstr->memoperands_end());
8945 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
8949 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
8951 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
8955 // private utility function: 64 bit atomics on 32 bit host.
8957 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
8958 MachineBasicBlock *MBB,
8963 bool invSrc) const {
8964 // For the atomic bitwise operator, we generate
8965 // thisMBB (instructions are in pairs, except cmpxchg8b)
8966 // ld t1,t2 = [bitinstr.addr]
8968 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
8969 // op t5, t6 <- out1, out2, [bitinstr.val]
8970 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
8971 // mov ECX, EBX <- t5, t6
8972 // mov EAX, EDX <- t1, t2
8973 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
8974 // mov t3, t4 <- EAX, EDX
8976 // result in out1, out2
8977 // fallthrough -->nextMBB
8979 const TargetRegisterClass *RC = X86::GR32RegisterClass;
8980 const unsigned LoadOpc = X86::MOV32rm;
8981 const unsigned NotOpc = X86::NOT32r;
8982 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8983 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
8984 MachineFunction::iterator MBBIter = MBB;
8987 /// First build the CFG
8988 MachineFunction *F = MBB->getParent();
8989 MachineBasicBlock *thisMBB = MBB;
8990 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
8991 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
8992 F->insert(MBBIter, newMBB);
8993 F->insert(MBBIter, nextMBB);
8995 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
8996 nextMBB->splice(nextMBB->begin(), thisMBB,
8997 llvm::next(MachineBasicBlock::iterator(bInstr)),
8999 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9001 // Update thisMBB to fall through to newMBB
9002 thisMBB->addSuccessor(newMBB);
9004 // newMBB jumps to itself and fall through to nextMBB
9005 newMBB->addSuccessor(nextMBB);
9006 newMBB->addSuccessor(newMBB);
9008 DebugLoc dl = bInstr->getDebugLoc();
9009 // Insert instructions into newMBB based on incoming instruction
9010 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
9011 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
9012 "unexpected number of operands");
9013 MachineOperand& dest1Oper = bInstr->getOperand(0);
9014 MachineOperand& dest2Oper = bInstr->getOperand(1);
9015 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9016 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
9017 argOpers[i] = &bInstr->getOperand(i+2);
9019 // We use some of the operands multiple times, so conservatively just
9020 // clear any kill flags that might be present.
9021 if (argOpers[i]->isReg() && argOpers[i]->isUse())
9022 argOpers[i]->setIsKill(false);
9025 // x86 address has 5 operands: base, index, scale, displacement, and segment.
9026 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9028 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9029 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
9030 for (int i=0; i <= lastAddrIndx; ++i)
9031 (*MIB).addOperand(*argOpers[i]);
9032 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9033 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
9034 // add 4 to displacement.
9035 for (int i=0; i <= lastAddrIndx-2; ++i)
9036 (*MIB).addOperand(*argOpers[i]);
9037 MachineOperand newOp3 = *(argOpers[3]);
9039 newOp3.setImm(newOp3.getImm()+4);
9041 newOp3.setOffset(newOp3.getOffset()+4);
9042 (*MIB).addOperand(newOp3);
9043 (*MIB).addOperand(*argOpers[lastAddrIndx]);
9045 // t3/4 are defined later, at the bottom of the loop
9046 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
9047 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
9048 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
9049 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
9050 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
9051 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
9053 // The subsequent operations should be using the destination registers of
9054 //the PHI instructions.
9056 t1 = F->getRegInfo().createVirtualRegister(RC);
9057 t2 = F->getRegInfo().createVirtualRegister(RC);
9058 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
9059 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
9061 t1 = dest1Oper.getReg();
9062 t2 = dest2Oper.getReg();
9065 int valArgIndx = lastAddrIndx + 1;
9066 assert((argOpers[valArgIndx]->isReg() ||
9067 argOpers[valArgIndx]->isImm()) &&
9069 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
9070 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
9071 if (argOpers[valArgIndx]->isReg())
9072 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
9074 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
9075 if (regOpcL != X86::MOV32rr)
9077 (*MIB).addOperand(*argOpers[valArgIndx]);
9078 assert(argOpers[valArgIndx + 1]->isReg() ==
9079 argOpers[valArgIndx]->isReg());
9080 assert(argOpers[valArgIndx + 1]->isImm() ==
9081 argOpers[valArgIndx]->isImm());
9082 if (argOpers[valArgIndx + 1]->isReg())
9083 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
9085 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
9086 if (regOpcH != X86::MOV32rr)
9088 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
9090 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9092 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
9095 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
9097 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
9100 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
9101 for (int i=0; i <= lastAddrIndx; ++i)
9102 (*MIB).addOperand(*argOpers[i]);
9104 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9105 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9106 bInstr->memoperands_end());
9108 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
9109 MIB.addReg(X86::EAX);
9110 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
9111 MIB.addReg(X86::EDX);
9114 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9116 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9120 // private utility function
9122 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
9123 MachineBasicBlock *MBB,
9124 unsigned cmovOpc) const {
9125 // For the atomic min/max operator, we generate
9128 // ld t1 = [min/max.addr]
9129 // mov t2 = [min/max.val]
9131 // cmov[cond] t2 = t1
9133 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9135 // fallthrough -->nextMBB
9137 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9138 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9139 MachineFunction::iterator MBBIter = MBB;
9142 /// First build the CFG
9143 MachineFunction *F = MBB->getParent();
9144 MachineBasicBlock *thisMBB = MBB;
9145 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9146 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9147 F->insert(MBBIter, newMBB);
9148 F->insert(MBBIter, nextMBB);
9150 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9151 nextMBB->splice(nextMBB->begin(), thisMBB,
9152 llvm::next(MachineBasicBlock::iterator(mInstr)),
9154 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9156 // Update thisMBB to fall through to newMBB
9157 thisMBB->addSuccessor(newMBB);
9159 // newMBB jumps to newMBB and fall through to nextMBB
9160 newMBB->addSuccessor(nextMBB);
9161 newMBB->addSuccessor(newMBB);
9163 DebugLoc dl = mInstr->getDebugLoc();
9164 // Insert instructions into newMBB based on incoming instruction
9165 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9166 "unexpected number of operands");
9167 MachineOperand& destOper = mInstr->getOperand(0);
9168 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9169 int numArgs = mInstr->getNumOperands() - 1;
9170 for (int i=0; i < numArgs; ++i)
9171 argOpers[i] = &mInstr->getOperand(i+1);
9173 // x86 address has 4 operands: base, index, scale, and displacement
9174 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9175 int valArgIndx = lastAddrIndx + 1;
9177 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9178 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
9179 for (int i=0; i <= lastAddrIndx; ++i)
9180 (*MIB).addOperand(*argOpers[i]);
9182 // We only support register and immediate values
9183 assert((argOpers[valArgIndx]->isReg() ||
9184 argOpers[valArgIndx]->isImm()) &&
9187 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9188 if (argOpers[valArgIndx]->isReg())
9189 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
9191 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
9192 (*MIB).addOperand(*argOpers[valArgIndx]);
9194 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9197 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
9202 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9203 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
9207 // Cmp and exchange if none has modified the memory location
9208 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
9209 for (int i=0; i <= lastAddrIndx; ++i)
9210 (*MIB).addOperand(*argOpers[i]);
9212 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9213 (*MIB).setMemRefs(mInstr->memoperands_begin(),
9214 mInstr->memoperands_end());
9216 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9217 MIB.addReg(X86::EAX);
9220 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9222 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
9226 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
9227 // or XMM0_V32I8 in AVX all of this code can be replaced with that
9230 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
9231 unsigned numArgs, bool memArg) const {
9233 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
9234 "Target must have SSE4.2 or AVX features enabled");
9236 DebugLoc dl = MI->getDebugLoc();
9237 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9241 if (!Subtarget->hasAVX()) {
9243 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
9245 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
9248 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
9250 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
9253 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
9255 for (unsigned i = 0; i < numArgs; ++i) {
9256 MachineOperand &Op = MI->getOperand(i+1);
9258 if (!(Op.isReg() && Op.isImplicit()))
9262 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
9265 MI->eraseFromParent();
9271 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
9273 MachineBasicBlock *MBB) const {
9274 // Emit code to save XMM registers to the stack. The ABI says that the
9275 // number of registers to save is given in %al, so it's theoretically
9276 // possible to do an indirect jump trick to avoid saving all of them,
9277 // however this code takes a simpler approach and just executes all
9278 // of the stores if %al is non-zero. It's less code, and it's probably
9279 // easier on the hardware branch predictor, and stores aren't all that
9280 // expensive anyway.
9282 // Create the new basic blocks. One block contains all the XMM stores,
9283 // and one block is the final destination regardless of whether any
9284 // stores were performed.
9285 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9286 MachineFunction *F = MBB->getParent();
9287 MachineFunction::iterator MBBIter = MBB;
9289 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
9290 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
9291 F->insert(MBBIter, XMMSaveMBB);
9292 F->insert(MBBIter, EndMBB);
9294 // Transfer the remainder of MBB and its successor edges to EndMBB.
9295 EndMBB->splice(EndMBB->begin(), MBB,
9296 llvm::next(MachineBasicBlock::iterator(MI)),
9298 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
9300 // The original block will now fall through to the XMM save block.
9301 MBB->addSuccessor(XMMSaveMBB);
9302 // The XMMSaveMBB will fall through to the end block.
9303 XMMSaveMBB->addSuccessor(EndMBB);
9305 // Now add the instructions.
9306 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9307 DebugLoc DL = MI->getDebugLoc();
9309 unsigned CountReg = MI->getOperand(0).getReg();
9310 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
9311 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
9313 if (!Subtarget->isTargetWin64()) {
9314 // If %al is 0, branch around the XMM save block.
9315 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
9316 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
9317 MBB->addSuccessor(EndMBB);
9320 // In the XMM save block, save all the XMM argument registers.
9321 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
9322 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
9323 MachineMemOperand *MMO =
9324 F->getMachineMemOperand(
9325 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
9326 MachineMemOperand::MOStore, Offset,
9327 /*Size=*/16, /*Align=*/16);
9328 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
9329 .addFrameIndex(RegSaveFrameIndex)
9330 .addImm(/*Scale=*/1)
9331 .addReg(/*IndexReg=*/0)
9332 .addImm(/*Disp=*/Offset)
9333 .addReg(/*Segment=*/0)
9334 .addReg(MI->getOperand(i).getReg())
9335 .addMemOperand(MMO);
9338 MI->eraseFromParent(); // The pseudo instruction is gone now.
9344 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
9345 MachineBasicBlock *BB) const {
9346 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9347 DebugLoc DL = MI->getDebugLoc();
9349 // To "insert" a SELECT_CC instruction, we actually have to insert the
9350 // diamond control-flow pattern. The incoming instruction knows the
9351 // destination vreg to set, the condition code register to branch on, the
9352 // true/false values to select between, and a branch opcode to use.
9353 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9354 MachineFunction::iterator It = BB;
9360 // cmpTY ccX, r1, r2
9362 // fallthrough --> copy0MBB
9363 MachineBasicBlock *thisMBB = BB;
9364 MachineFunction *F = BB->getParent();
9365 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
9366 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
9367 F->insert(It, copy0MBB);
9368 F->insert(It, sinkMBB);
9370 // If the EFLAGS register isn't dead in the terminator, then claim that it's
9371 // live into the sink and copy blocks.
9372 const MachineFunction *MF = BB->getParent();
9373 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
9374 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
9376 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
9377 const MachineOperand &MO = MI->getOperand(I);
9378 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
9379 unsigned Reg = MO.getReg();
9380 if (Reg != X86::EFLAGS) continue;
9381 copy0MBB->addLiveIn(Reg);
9382 sinkMBB->addLiveIn(Reg);
9385 // Transfer the remainder of BB and its successor edges to sinkMBB.
9386 sinkMBB->splice(sinkMBB->begin(), BB,
9387 llvm::next(MachineBasicBlock::iterator(MI)),
9389 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
9391 // Add the true and fallthrough blocks as its successors.
9392 BB->addSuccessor(copy0MBB);
9393 BB->addSuccessor(sinkMBB);
9395 // Create the conditional branch instruction.
9397 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
9398 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
9401 // %FalseValue = ...
9402 // # fallthrough to sinkMBB
9403 copy0MBB->addSuccessor(sinkMBB);
9406 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
9408 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
9409 TII->get(X86::PHI), MI->getOperand(0).getReg())
9410 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
9411 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
9413 MI->eraseFromParent(); // The pseudo instruction is gone now.
9418 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
9419 MachineBasicBlock *BB) const {
9420 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9421 DebugLoc DL = MI->getDebugLoc();
9423 // The lowering is pretty easy: we're just emitting the call to _alloca. The
9424 // non-trivial part is impdef of ESP.
9425 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
9428 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
9429 .addExternalSymbol("_alloca")
9430 .addReg(X86::EAX, RegState::Implicit)
9431 .addReg(X86::ESP, RegState::Implicit)
9432 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
9433 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
9434 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
9436 MI->eraseFromParent(); // The pseudo instruction is gone now.
9441 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
9442 MachineBasicBlock *BB) const {
9443 // This is pretty easy. We're taking the value that we received from
9444 // our load from the relocation, sticking it in either RDI (x86-64)
9445 // or EAX and doing an indirect call. The return value will then
9446 // be in the normal return register.
9447 const X86InstrInfo *TII
9448 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
9449 DebugLoc DL = MI->getDebugLoc();
9450 MachineFunction *F = BB->getParent();
9451 bool IsWin64 = Subtarget->isTargetWin64();
9453 assert(MI->getOperand(3).isGlobal() && "This should be a global");
9455 if (Subtarget->is64Bit()) {
9456 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9457 TII->get(X86::MOV64rm), X86::RDI)
9459 .addImm(0).addReg(0)
9460 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9461 MI->getOperand(3).getTargetFlags())
9463 MIB = BuildMI(*BB, MI, DL, TII->get(IsWin64 ? X86::WINCALL64m : X86::CALL64m));
9464 addDirectMem(MIB, X86::RDI);
9465 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
9466 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9467 TII->get(X86::MOV32rm), X86::EAX)
9469 .addImm(0).addReg(0)
9470 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9471 MI->getOperand(3).getTargetFlags())
9473 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
9474 addDirectMem(MIB, X86::EAX);
9476 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9477 TII->get(X86::MOV32rm), X86::EAX)
9478 .addReg(TII->getGlobalBaseReg(F))
9479 .addImm(0).addReg(0)
9480 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9481 MI->getOperand(3).getTargetFlags())
9483 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
9484 addDirectMem(MIB, X86::EAX);
9487 MI->eraseFromParent(); // The pseudo instruction is gone now.
9492 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
9493 MachineBasicBlock *BB) const {
9494 switch (MI->getOpcode()) {
9495 default: assert(false && "Unexpected instr type to insert");
9496 case X86::MINGW_ALLOCA:
9497 return EmitLoweredMingwAlloca(MI, BB);
9498 case X86::TLSCall_32:
9499 case X86::TLSCall_64:
9500 return EmitLoweredTLSCall(MI, BB);
9502 case X86::CMOV_V1I64:
9503 case X86::CMOV_FR32:
9504 case X86::CMOV_FR64:
9505 case X86::CMOV_V4F32:
9506 case X86::CMOV_V2F64:
9507 case X86::CMOV_V2I64:
9508 case X86::CMOV_GR16:
9509 case X86::CMOV_GR32:
9510 case X86::CMOV_RFP32:
9511 case X86::CMOV_RFP64:
9512 case X86::CMOV_RFP80:
9513 return EmitLoweredSelect(MI, BB);
9515 case X86::FP32_TO_INT16_IN_MEM:
9516 case X86::FP32_TO_INT32_IN_MEM:
9517 case X86::FP32_TO_INT64_IN_MEM:
9518 case X86::FP64_TO_INT16_IN_MEM:
9519 case X86::FP64_TO_INT32_IN_MEM:
9520 case X86::FP64_TO_INT64_IN_MEM:
9521 case X86::FP80_TO_INT16_IN_MEM:
9522 case X86::FP80_TO_INT32_IN_MEM:
9523 case X86::FP80_TO_INT64_IN_MEM: {
9524 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9525 DebugLoc DL = MI->getDebugLoc();
9527 // Change the floating point control register to use "round towards zero"
9528 // mode when truncating to an integer value.
9529 MachineFunction *F = BB->getParent();
9530 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
9531 addFrameReference(BuildMI(*BB, MI, DL,
9532 TII->get(X86::FNSTCW16m)), CWFrameIdx);
9534 // Load the old value of the high byte of the control word...
9536 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
9537 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
9540 // Set the high part to be round to zero...
9541 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
9544 // Reload the modified control word now...
9545 addFrameReference(BuildMI(*BB, MI, DL,
9546 TII->get(X86::FLDCW16m)), CWFrameIdx);
9548 // Restore the memory image of control word to original value
9549 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
9552 // Get the X86 opcode to use.
9554 switch (MI->getOpcode()) {
9555 default: llvm_unreachable("illegal opcode!");
9556 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
9557 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
9558 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
9559 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
9560 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
9561 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
9562 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
9563 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
9564 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
9568 MachineOperand &Op = MI->getOperand(0);
9570 AM.BaseType = X86AddressMode::RegBase;
9571 AM.Base.Reg = Op.getReg();
9573 AM.BaseType = X86AddressMode::FrameIndexBase;
9574 AM.Base.FrameIndex = Op.getIndex();
9576 Op = MI->getOperand(1);
9578 AM.Scale = Op.getImm();
9579 Op = MI->getOperand(2);
9581 AM.IndexReg = Op.getImm();
9582 Op = MI->getOperand(3);
9583 if (Op.isGlobal()) {
9584 AM.GV = Op.getGlobal();
9586 AM.Disp = Op.getImm();
9588 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
9589 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
9591 // Reload the original control word now.
9592 addFrameReference(BuildMI(*BB, MI, DL,
9593 TII->get(X86::FLDCW16m)), CWFrameIdx);
9595 MI->eraseFromParent(); // The pseudo instruction is gone now.
9598 // String/text processing lowering.
9599 case X86::PCMPISTRM128REG:
9600 case X86::VPCMPISTRM128REG:
9601 return EmitPCMP(MI, BB, 3, false /* in-mem */);
9602 case X86::PCMPISTRM128MEM:
9603 case X86::VPCMPISTRM128MEM:
9604 return EmitPCMP(MI, BB, 3, true /* in-mem */);
9605 case X86::PCMPESTRM128REG:
9606 case X86::VPCMPESTRM128REG:
9607 return EmitPCMP(MI, BB, 5, false /* in mem */);
9608 case X86::PCMPESTRM128MEM:
9609 case X86::VPCMPESTRM128MEM:
9610 return EmitPCMP(MI, BB, 5, true /* in mem */);
9613 case X86::ATOMAND32:
9614 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
9615 X86::AND32ri, X86::MOV32rm,
9617 X86::NOT32r, X86::EAX,
9618 X86::GR32RegisterClass);
9620 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
9621 X86::OR32ri, X86::MOV32rm,
9623 X86::NOT32r, X86::EAX,
9624 X86::GR32RegisterClass);
9625 case X86::ATOMXOR32:
9626 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
9627 X86::XOR32ri, X86::MOV32rm,
9629 X86::NOT32r, X86::EAX,
9630 X86::GR32RegisterClass);
9631 case X86::ATOMNAND32:
9632 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
9633 X86::AND32ri, X86::MOV32rm,
9635 X86::NOT32r, X86::EAX,
9636 X86::GR32RegisterClass, true);
9637 case X86::ATOMMIN32:
9638 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
9639 case X86::ATOMMAX32:
9640 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
9641 case X86::ATOMUMIN32:
9642 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
9643 case X86::ATOMUMAX32:
9644 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
9646 case X86::ATOMAND16:
9647 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
9648 X86::AND16ri, X86::MOV16rm,
9650 X86::NOT16r, X86::AX,
9651 X86::GR16RegisterClass);
9653 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
9654 X86::OR16ri, X86::MOV16rm,
9656 X86::NOT16r, X86::AX,
9657 X86::GR16RegisterClass);
9658 case X86::ATOMXOR16:
9659 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
9660 X86::XOR16ri, X86::MOV16rm,
9662 X86::NOT16r, X86::AX,
9663 X86::GR16RegisterClass);
9664 case X86::ATOMNAND16:
9665 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
9666 X86::AND16ri, X86::MOV16rm,
9668 X86::NOT16r, X86::AX,
9669 X86::GR16RegisterClass, true);
9670 case X86::ATOMMIN16:
9671 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
9672 case X86::ATOMMAX16:
9673 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
9674 case X86::ATOMUMIN16:
9675 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
9676 case X86::ATOMUMAX16:
9677 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
9680 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
9681 X86::AND8ri, X86::MOV8rm,
9683 X86::NOT8r, X86::AL,
9684 X86::GR8RegisterClass);
9686 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
9687 X86::OR8ri, X86::MOV8rm,
9689 X86::NOT8r, X86::AL,
9690 X86::GR8RegisterClass);
9692 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
9693 X86::XOR8ri, X86::MOV8rm,
9695 X86::NOT8r, X86::AL,
9696 X86::GR8RegisterClass);
9697 case X86::ATOMNAND8:
9698 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
9699 X86::AND8ri, X86::MOV8rm,
9701 X86::NOT8r, X86::AL,
9702 X86::GR8RegisterClass, true);
9703 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
9704 // This group is for 64-bit host.
9705 case X86::ATOMAND64:
9706 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
9707 X86::AND64ri32, X86::MOV64rm,
9709 X86::NOT64r, X86::RAX,
9710 X86::GR64RegisterClass);
9712 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
9713 X86::OR64ri32, X86::MOV64rm,
9715 X86::NOT64r, X86::RAX,
9716 X86::GR64RegisterClass);
9717 case X86::ATOMXOR64:
9718 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
9719 X86::XOR64ri32, X86::MOV64rm,
9721 X86::NOT64r, X86::RAX,
9722 X86::GR64RegisterClass);
9723 case X86::ATOMNAND64:
9724 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
9725 X86::AND64ri32, X86::MOV64rm,
9727 X86::NOT64r, X86::RAX,
9728 X86::GR64RegisterClass, true);
9729 case X86::ATOMMIN64:
9730 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
9731 case X86::ATOMMAX64:
9732 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
9733 case X86::ATOMUMIN64:
9734 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
9735 case X86::ATOMUMAX64:
9736 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
9738 // This group does 64-bit operations on a 32-bit host.
9739 case X86::ATOMAND6432:
9740 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9741 X86::AND32rr, X86::AND32rr,
9742 X86::AND32ri, X86::AND32ri,
9744 case X86::ATOMOR6432:
9745 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9746 X86::OR32rr, X86::OR32rr,
9747 X86::OR32ri, X86::OR32ri,
9749 case X86::ATOMXOR6432:
9750 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9751 X86::XOR32rr, X86::XOR32rr,
9752 X86::XOR32ri, X86::XOR32ri,
9754 case X86::ATOMNAND6432:
9755 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9756 X86::AND32rr, X86::AND32rr,
9757 X86::AND32ri, X86::AND32ri,
9759 case X86::ATOMADD6432:
9760 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9761 X86::ADD32rr, X86::ADC32rr,
9762 X86::ADD32ri, X86::ADC32ri,
9764 case X86::ATOMSUB6432:
9765 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9766 X86::SUB32rr, X86::SBB32rr,
9767 X86::SUB32ri, X86::SBB32ri,
9769 case X86::ATOMSWAP6432:
9770 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9771 X86::MOV32rr, X86::MOV32rr,
9772 X86::MOV32ri, X86::MOV32ri,
9774 case X86::VASTART_SAVE_XMM_REGS:
9775 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
9779 //===----------------------------------------------------------------------===//
9780 // X86 Optimization Hooks
9781 //===----------------------------------------------------------------------===//
9783 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
9787 const SelectionDAG &DAG,
9788 unsigned Depth) const {
9789 unsigned Opc = Op.getOpcode();
9790 assert((Opc >= ISD::BUILTIN_OP_END ||
9791 Opc == ISD::INTRINSIC_WO_CHAIN ||
9792 Opc == ISD::INTRINSIC_W_CHAIN ||
9793 Opc == ISD::INTRINSIC_VOID) &&
9794 "Should use MaskedValueIsZero if you don't know whether Op"
9795 " is a target node!");
9797 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
9809 // These nodes' second result is a boolean.
9810 if (Op.getResNo() == 0)
9814 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
9815 Mask.getBitWidth() - 1);
9820 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
9821 /// node is a GlobalAddress + offset.
9822 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
9823 const GlobalValue* &GA,
9824 int64_t &Offset) const {
9825 if (N->getOpcode() == X86ISD::Wrapper) {
9826 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
9827 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
9828 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
9832 return TargetLowering::isGAPlusOffset(N, GA, Offset);
9835 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
9836 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
9837 /// if the load addresses are consecutive, non-overlapping, and in the right
9839 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
9840 const TargetLowering &TLI) {
9841 DebugLoc dl = N->getDebugLoc();
9842 EVT VT = N->getValueType(0);
9844 if (VT.getSizeInBits() != 128)
9847 SmallVector<SDValue, 16> Elts;
9848 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
9849 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
9851 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
9854 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
9855 /// generation and convert it from being a bunch of shuffles and extracts
9856 /// to a simple store and scalar loads to extract the elements.
9857 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
9858 const TargetLowering &TLI) {
9859 SDValue InputVector = N->getOperand(0);
9861 // Only operate on vectors of 4 elements, where the alternative shuffling
9862 // gets to be more expensive.
9863 if (InputVector.getValueType() != MVT::v4i32)
9866 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
9867 // single use which is a sign-extend or zero-extend, and all elements are
9869 SmallVector<SDNode *, 4> Uses;
9870 unsigned ExtractedElements = 0;
9871 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
9872 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
9873 if (UI.getUse().getResNo() != InputVector.getResNo())
9876 SDNode *Extract = *UI;
9877 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9880 if (Extract->getValueType(0) != MVT::i32)
9882 if (!Extract->hasOneUse())
9884 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
9885 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
9887 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
9890 // Record which element was extracted.
9891 ExtractedElements |=
9892 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
9894 Uses.push_back(Extract);
9897 // If not all the elements were used, this may not be worthwhile.
9898 if (ExtractedElements != 15)
9901 // Ok, we've now decided to do the transformation.
9902 DebugLoc dl = InputVector.getDebugLoc();
9904 // Store the value to a temporary stack slot.
9905 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
9906 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, NULL,
9907 0, false, false, 0);
9909 // Replace each use (extract) with a load of the appropriate element.
9910 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
9911 UE = Uses.end(); UI != UE; ++UI) {
9912 SDNode *Extract = *UI;
9914 // Compute the element's address.
9915 SDValue Idx = Extract->getOperand(1);
9917 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
9918 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
9919 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
9921 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
9922 OffsetVal, StackPtr);
9925 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
9926 ScalarAddr, NULL, 0, false, false, 0);
9928 // Replace the exact with the load.
9929 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
9932 // The replacement was made in place; don't return anything.
9936 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
9937 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
9938 const X86Subtarget *Subtarget) {
9939 DebugLoc DL = N->getDebugLoc();
9940 SDValue Cond = N->getOperand(0);
9941 // Get the LHS/RHS of the select.
9942 SDValue LHS = N->getOperand(1);
9943 SDValue RHS = N->getOperand(2);
9945 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
9946 // instructions match the semantics of the common C idiom x<y?x:y but not
9947 // x<=y?x:y, because of how they handle negative zero (which can be
9948 // ignored in unsafe-math mode).
9949 if (Subtarget->hasSSE2() &&
9950 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
9951 Cond.getOpcode() == ISD::SETCC) {
9952 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
9954 unsigned Opcode = 0;
9955 // Check for x CC y ? x : y.
9956 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
9957 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
9961 // Converting this to a min would handle NaNs incorrectly, and swapping
9962 // the operands would cause it to handle comparisons between positive
9963 // and negative zero incorrectly.
9964 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
9965 if (!UnsafeFPMath &&
9966 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9968 std::swap(LHS, RHS);
9970 Opcode = X86ISD::FMIN;
9973 // Converting this to a min would handle comparisons between positive
9974 // and negative zero incorrectly.
9975 if (!UnsafeFPMath &&
9976 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
9978 Opcode = X86ISD::FMIN;
9981 // Converting this to a min would handle both negative zeros and NaNs
9982 // incorrectly, but we can swap the operands to fix both.
9983 std::swap(LHS, RHS);
9987 Opcode = X86ISD::FMIN;
9991 // Converting this to a max would handle comparisons between positive
9992 // and negative zero incorrectly.
9993 if (!UnsafeFPMath &&
9994 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
9996 Opcode = X86ISD::FMAX;
9999 // Converting this to a max would handle NaNs incorrectly, and swapping
10000 // the operands would cause it to handle comparisons between positive
10001 // and negative zero incorrectly.
10002 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10003 if (!UnsafeFPMath &&
10004 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10006 std::swap(LHS, RHS);
10008 Opcode = X86ISD::FMAX;
10011 // Converting this to a max would handle both negative zeros and NaNs
10012 // incorrectly, but we can swap the operands to fix both.
10013 std::swap(LHS, RHS);
10017 Opcode = X86ISD::FMAX;
10020 // Check for x CC y ? y : x -- a min/max with reversed arms.
10021 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
10022 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
10026 // Converting this to a min would handle comparisons between positive
10027 // and negative zero incorrectly, and swapping the operands would
10028 // cause it to handle NaNs incorrectly.
10029 if (!UnsafeFPMath &&
10030 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
10031 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10033 std::swap(LHS, RHS);
10035 Opcode = X86ISD::FMIN;
10038 // Converting this to a min would handle NaNs incorrectly.
10039 if (!UnsafeFPMath &&
10040 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
10042 Opcode = X86ISD::FMIN;
10045 // Converting this to a min would handle both negative zeros and NaNs
10046 // incorrectly, but we can swap the operands to fix both.
10047 std::swap(LHS, RHS);
10051 Opcode = X86ISD::FMIN;
10055 // Converting this to a max would handle NaNs incorrectly.
10056 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10058 Opcode = X86ISD::FMAX;
10061 // Converting this to a max would handle comparisons between positive
10062 // and negative zero incorrectly, and swapping the operands would
10063 // cause it to handle NaNs incorrectly.
10064 if (!UnsafeFPMath &&
10065 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
10066 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10068 std::swap(LHS, RHS);
10070 Opcode = X86ISD::FMAX;
10073 // Converting this to a max would handle both negative zeros and NaNs
10074 // incorrectly, but we can swap the operands to fix both.
10075 std::swap(LHS, RHS);
10079 Opcode = X86ISD::FMAX;
10085 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
10088 // If this is a select between two integer constants, try to do some
10090 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
10091 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
10092 // Don't do this for crazy integer types.
10093 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
10094 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
10095 // so that TrueC (the true value) is larger than FalseC.
10096 bool NeedsCondInvert = false;
10098 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
10099 // Efficiently invertible.
10100 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
10101 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
10102 isa<ConstantSDNode>(Cond.getOperand(1))))) {
10103 NeedsCondInvert = true;
10104 std::swap(TrueC, FalseC);
10107 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
10108 if (FalseC->getAPIntValue() == 0 &&
10109 TrueC->getAPIntValue().isPowerOf2()) {
10110 if (NeedsCondInvert) // Invert the condition if needed.
10111 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10112 DAG.getConstant(1, Cond.getValueType()));
10114 // Zero extend the condition if needed.
10115 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
10117 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10118 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
10119 DAG.getConstant(ShAmt, MVT::i8));
10122 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
10123 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10124 if (NeedsCondInvert) // Invert the condition if needed.
10125 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10126 DAG.getConstant(1, Cond.getValueType()));
10128 // Zero extend the condition if needed.
10129 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10130 FalseC->getValueType(0), Cond);
10131 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10132 SDValue(FalseC, 0));
10135 // Optimize cases that will turn into an LEA instruction. This requires
10136 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10137 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10138 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10139 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10141 bool isFastMultiplier = false;
10143 switch ((unsigned char)Diff) {
10145 case 1: // result = add base, cond
10146 case 2: // result = lea base( , cond*2)
10147 case 3: // result = lea base(cond, cond*2)
10148 case 4: // result = lea base( , cond*4)
10149 case 5: // result = lea base(cond, cond*4)
10150 case 8: // result = lea base( , cond*8)
10151 case 9: // result = lea base(cond, cond*8)
10152 isFastMultiplier = true;
10157 if (isFastMultiplier) {
10158 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10159 if (NeedsCondInvert) // Invert the condition if needed.
10160 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10161 DAG.getConstant(1, Cond.getValueType()));
10163 // Zero extend the condition if needed.
10164 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10166 // Scale the condition by the difference.
10168 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10169 DAG.getConstant(Diff, Cond.getValueType()));
10171 // Add the base if non-zero.
10172 if (FalseC->getAPIntValue() != 0)
10173 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10174 SDValue(FalseC, 0));
10184 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
10185 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
10186 TargetLowering::DAGCombinerInfo &DCI) {
10187 DebugLoc DL = N->getDebugLoc();
10189 // If the flag operand isn't dead, don't touch this CMOV.
10190 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
10193 // If this is a select between two integer constants, try to do some
10194 // optimizations. Note that the operands are ordered the opposite of SELECT
10196 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
10197 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10198 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
10199 // larger than FalseC (the false value).
10200 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
10202 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
10203 CC = X86::GetOppositeBranchCondition(CC);
10204 std::swap(TrueC, FalseC);
10207 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
10208 // This is efficient for any integer data type (including i8/i16) and
10210 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
10211 SDValue Cond = N->getOperand(3);
10212 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10213 DAG.getConstant(CC, MVT::i8), Cond);
10215 // Zero extend the condition if needed.
10216 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
10218 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10219 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
10220 DAG.getConstant(ShAmt, MVT::i8));
10221 if (N->getNumValues() == 2) // Dead flag value?
10222 return DCI.CombineTo(N, Cond, SDValue());
10226 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
10227 // for any integer data type, including i8/i16.
10228 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10229 SDValue Cond = N->getOperand(3);
10230 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10231 DAG.getConstant(CC, MVT::i8), Cond);
10233 // Zero extend the condition if needed.
10234 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10235 FalseC->getValueType(0), Cond);
10236 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10237 SDValue(FalseC, 0));
10239 if (N->getNumValues() == 2) // Dead flag value?
10240 return DCI.CombineTo(N, Cond, SDValue());
10244 // Optimize cases that will turn into an LEA instruction. This requires
10245 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10246 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10247 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10248 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10250 bool isFastMultiplier = false;
10252 switch ((unsigned char)Diff) {
10254 case 1: // result = add base, cond
10255 case 2: // result = lea base( , cond*2)
10256 case 3: // result = lea base(cond, cond*2)
10257 case 4: // result = lea base( , cond*4)
10258 case 5: // result = lea base(cond, cond*4)
10259 case 8: // result = lea base( , cond*8)
10260 case 9: // result = lea base(cond, cond*8)
10261 isFastMultiplier = true;
10266 if (isFastMultiplier) {
10267 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10268 SDValue Cond = N->getOperand(3);
10269 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10270 DAG.getConstant(CC, MVT::i8), Cond);
10271 // Zero extend the condition if needed.
10272 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10274 // Scale the condition by the difference.
10276 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10277 DAG.getConstant(Diff, Cond.getValueType()));
10279 // Add the base if non-zero.
10280 if (FalseC->getAPIntValue() != 0)
10281 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10282 SDValue(FalseC, 0));
10283 if (N->getNumValues() == 2) // Dead flag value?
10284 return DCI.CombineTo(N, Cond, SDValue());
10294 /// PerformMulCombine - Optimize a single multiply with constant into two
10295 /// in order to implement it with two cheaper instructions, e.g.
10296 /// LEA + SHL, LEA + LEA.
10297 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
10298 TargetLowering::DAGCombinerInfo &DCI) {
10299 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
10302 EVT VT = N->getValueType(0);
10303 if (VT != MVT::i64)
10306 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
10309 uint64_t MulAmt = C->getZExtValue();
10310 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
10313 uint64_t MulAmt1 = 0;
10314 uint64_t MulAmt2 = 0;
10315 if ((MulAmt % 9) == 0) {
10317 MulAmt2 = MulAmt / 9;
10318 } else if ((MulAmt % 5) == 0) {
10320 MulAmt2 = MulAmt / 5;
10321 } else if ((MulAmt % 3) == 0) {
10323 MulAmt2 = MulAmt / 3;
10326 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
10327 DebugLoc DL = N->getDebugLoc();
10329 if (isPowerOf2_64(MulAmt2) &&
10330 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
10331 // If second multiplifer is pow2, issue it first. We want the multiply by
10332 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
10334 std::swap(MulAmt1, MulAmt2);
10337 if (isPowerOf2_64(MulAmt1))
10338 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
10339 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
10341 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
10342 DAG.getConstant(MulAmt1, VT));
10344 if (isPowerOf2_64(MulAmt2))
10345 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
10346 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
10348 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
10349 DAG.getConstant(MulAmt2, VT));
10351 // Do not add new nodes to DAG combiner worklist.
10352 DCI.CombineTo(N, NewMul, false);
10357 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
10358 SDValue N0 = N->getOperand(0);
10359 SDValue N1 = N->getOperand(1);
10360 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
10361 EVT VT = N0.getValueType();
10363 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
10364 // since the result of setcc_c is all zero's or all ones.
10365 if (N1C && N0.getOpcode() == ISD::AND &&
10366 N0.getOperand(1).getOpcode() == ISD::Constant) {
10367 SDValue N00 = N0.getOperand(0);
10368 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
10369 ((N00.getOpcode() == ISD::ANY_EXTEND ||
10370 N00.getOpcode() == ISD::ZERO_EXTEND) &&
10371 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
10372 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
10373 APInt ShAmt = N1C->getAPIntValue();
10374 Mask = Mask.shl(ShAmt);
10376 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
10377 N00, DAG.getConstant(Mask, VT));
10384 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
10386 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
10387 const X86Subtarget *Subtarget) {
10388 EVT VT = N->getValueType(0);
10389 if (!VT.isVector() && VT.isInteger() &&
10390 N->getOpcode() == ISD::SHL)
10391 return PerformSHLCombine(N, DAG);
10393 // On X86 with SSE2 support, we can transform this to a vector shift if
10394 // all elements are shifted by the same amount. We can't do this in legalize
10395 // because the a constant vector is typically transformed to a constant pool
10396 // so we have no knowledge of the shift amount.
10397 if (!Subtarget->hasSSE2())
10400 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
10403 SDValue ShAmtOp = N->getOperand(1);
10404 EVT EltVT = VT.getVectorElementType();
10405 DebugLoc DL = N->getDebugLoc();
10406 SDValue BaseShAmt = SDValue();
10407 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
10408 unsigned NumElts = VT.getVectorNumElements();
10410 for (; i != NumElts; ++i) {
10411 SDValue Arg = ShAmtOp.getOperand(i);
10412 if (Arg.getOpcode() == ISD::UNDEF) continue;
10416 for (; i != NumElts; ++i) {
10417 SDValue Arg = ShAmtOp.getOperand(i);
10418 if (Arg.getOpcode() == ISD::UNDEF) continue;
10419 if (Arg != BaseShAmt) {
10423 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
10424 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
10425 SDValue InVec = ShAmtOp.getOperand(0);
10426 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
10427 unsigned NumElts = InVec.getValueType().getVectorNumElements();
10429 for (; i != NumElts; ++i) {
10430 SDValue Arg = InVec.getOperand(i);
10431 if (Arg.getOpcode() == ISD::UNDEF) continue;
10435 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
10436 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
10437 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
10438 if (C->getZExtValue() == SplatIdx)
10439 BaseShAmt = InVec.getOperand(1);
10442 if (BaseShAmt.getNode() == 0)
10443 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
10444 DAG.getIntPtrConstant(0));
10448 // The shift amount is an i32.
10449 if (EltVT.bitsGT(MVT::i32))
10450 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
10451 else if (EltVT.bitsLT(MVT::i32))
10452 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
10454 // The shift amount is identical so we can do a vector shift.
10455 SDValue ValOp = N->getOperand(0);
10456 switch (N->getOpcode()) {
10458 llvm_unreachable("Unknown shift opcode!");
10461 if (VT == MVT::v2i64)
10462 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10463 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10465 if (VT == MVT::v4i32)
10466 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10467 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10469 if (VT == MVT::v8i16)
10470 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10471 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10475 if (VT == MVT::v4i32)
10476 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10477 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
10479 if (VT == MVT::v8i16)
10480 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10481 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
10485 if (VT == MVT::v2i64)
10486 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10487 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10489 if (VT == MVT::v4i32)
10490 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10491 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
10493 if (VT == MVT::v8i16)
10494 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10495 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10502 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
10503 TargetLowering::DAGCombinerInfo &DCI,
10504 const X86Subtarget *Subtarget) {
10505 if (DCI.isBeforeLegalizeOps())
10508 EVT VT = N->getValueType(0);
10509 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
10512 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
10513 SDValue N0 = N->getOperand(0);
10514 SDValue N1 = N->getOperand(1);
10515 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
10517 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
10519 if (!N0.hasOneUse() || !N1.hasOneUse())
10522 SDValue ShAmt0 = N0.getOperand(1);
10523 if (ShAmt0.getValueType() != MVT::i8)
10525 SDValue ShAmt1 = N1.getOperand(1);
10526 if (ShAmt1.getValueType() != MVT::i8)
10528 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
10529 ShAmt0 = ShAmt0.getOperand(0);
10530 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
10531 ShAmt1 = ShAmt1.getOperand(0);
10533 DebugLoc DL = N->getDebugLoc();
10534 unsigned Opc = X86ISD::SHLD;
10535 SDValue Op0 = N0.getOperand(0);
10536 SDValue Op1 = N1.getOperand(0);
10537 if (ShAmt0.getOpcode() == ISD::SUB) {
10538 Opc = X86ISD::SHRD;
10539 std::swap(Op0, Op1);
10540 std::swap(ShAmt0, ShAmt1);
10543 unsigned Bits = VT.getSizeInBits();
10544 if (ShAmt1.getOpcode() == ISD::SUB) {
10545 SDValue Sum = ShAmt1.getOperand(0);
10546 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
10547 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
10548 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
10549 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
10550 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
10551 return DAG.getNode(Opc, DL, VT,
10553 DAG.getNode(ISD::TRUNCATE, DL,
10556 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
10557 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
10559 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
10560 return DAG.getNode(Opc, DL, VT,
10561 N0.getOperand(0), N1.getOperand(0),
10562 DAG.getNode(ISD::TRUNCATE, DL,
10569 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
10570 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
10571 const X86Subtarget *Subtarget) {
10572 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
10573 // the FP state in cases where an emms may be missing.
10574 // A preferable solution to the general problem is to figure out the right
10575 // places to insert EMMS. This qualifies as a quick hack.
10577 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
10578 StoreSDNode *St = cast<StoreSDNode>(N);
10579 EVT VT = St->getValue().getValueType();
10580 if (VT.getSizeInBits() != 64)
10583 const Function *F = DAG.getMachineFunction().getFunction();
10584 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
10585 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
10586 && Subtarget->hasSSE2();
10587 if ((VT.isVector() ||
10588 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
10589 isa<LoadSDNode>(St->getValue()) &&
10590 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
10591 St->getChain().hasOneUse() && !St->isVolatile()) {
10592 SDNode* LdVal = St->getValue().getNode();
10593 LoadSDNode *Ld = 0;
10594 int TokenFactorIndex = -1;
10595 SmallVector<SDValue, 8> Ops;
10596 SDNode* ChainVal = St->getChain().getNode();
10597 // Must be a store of a load. We currently handle two cases: the load
10598 // is a direct child, and it's under an intervening TokenFactor. It is
10599 // possible to dig deeper under nested TokenFactors.
10600 if (ChainVal == LdVal)
10601 Ld = cast<LoadSDNode>(St->getChain());
10602 else if (St->getValue().hasOneUse() &&
10603 ChainVal->getOpcode() == ISD::TokenFactor) {
10604 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
10605 if (ChainVal->getOperand(i).getNode() == LdVal) {
10606 TokenFactorIndex = i;
10607 Ld = cast<LoadSDNode>(St->getValue());
10609 Ops.push_back(ChainVal->getOperand(i));
10613 if (!Ld || !ISD::isNormalLoad(Ld))
10616 // If this is not the MMX case, i.e. we are just turning i64 load/store
10617 // into f64 load/store, avoid the transformation if there are multiple
10618 // uses of the loaded value.
10619 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
10622 DebugLoc LdDL = Ld->getDebugLoc();
10623 DebugLoc StDL = N->getDebugLoc();
10624 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
10625 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
10627 if (Subtarget->is64Bit() || F64IsLegal) {
10628 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
10629 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
10630 Ld->getBasePtr(), Ld->getSrcValue(),
10631 Ld->getSrcValueOffset(), Ld->isVolatile(),
10632 Ld->isNonTemporal(), Ld->getAlignment());
10633 SDValue NewChain = NewLd.getValue(1);
10634 if (TokenFactorIndex != -1) {
10635 Ops.push_back(NewChain);
10636 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
10639 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
10640 St->getSrcValue(), St->getSrcValueOffset(),
10641 St->isVolatile(), St->isNonTemporal(),
10642 St->getAlignment());
10645 // Otherwise, lower to two pairs of 32-bit loads / stores.
10646 SDValue LoAddr = Ld->getBasePtr();
10647 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
10648 DAG.getConstant(4, MVT::i32));
10650 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
10651 Ld->getSrcValue(), Ld->getSrcValueOffset(),
10652 Ld->isVolatile(), Ld->isNonTemporal(),
10653 Ld->getAlignment());
10654 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
10655 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
10656 Ld->isVolatile(), Ld->isNonTemporal(),
10657 MinAlign(Ld->getAlignment(), 4));
10659 SDValue NewChain = LoLd.getValue(1);
10660 if (TokenFactorIndex != -1) {
10661 Ops.push_back(LoLd);
10662 Ops.push_back(HiLd);
10663 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
10667 LoAddr = St->getBasePtr();
10668 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
10669 DAG.getConstant(4, MVT::i32));
10671 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
10672 St->getSrcValue(), St->getSrcValueOffset(),
10673 St->isVolatile(), St->isNonTemporal(),
10674 St->getAlignment());
10675 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
10677 St->getSrcValueOffset() + 4,
10679 St->isNonTemporal(),
10680 MinAlign(St->getAlignment(), 4));
10681 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
10686 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
10687 /// X86ISD::FXOR nodes.
10688 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
10689 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
10690 // F[X]OR(0.0, x) -> x
10691 // F[X]OR(x, 0.0) -> x
10692 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
10693 if (C->getValueAPF().isPosZero())
10694 return N->getOperand(1);
10695 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
10696 if (C->getValueAPF().isPosZero())
10697 return N->getOperand(0);
10701 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
10702 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
10703 // FAND(0.0, x) -> 0.0
10704 // FAND(x, 0.0) -> 0.0
10705 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
10706 if (C->getValueAPF().isPosZero())
10707 return N->getOperand(0);
10708 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
10709 if (C->getValueAPF().isPosZero())
10710 return N->getOperand(1);
10714 static SDValue PerformBTCombine(SDNode *N,
10716 TargetLowering::DAGCombinerInfo &DCI) {
10717 // BT ignores high bits in the bit index operand.
10718 SDValue Op1 = N->getOperand(1);
10719 if (Op1.hasOneUse()) {
10720 unsigned BitWidth = Op1.getValueSizeInBits();
10721 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
10722 APInt KnownZero, KnownOne;
10723 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
10724 !DCI.isBeforeLegalizeOps());
10725 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10726 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
10727 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
10728 DCI.CommitTargetLoweringOpt(TLO);
10733 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
10734 SDValue Op = N->getOperand(0);
10735 if (Op.getOpcode() == ISD::BIT_CONVERT)
10736 Op = Op.getOperand(0);
10737 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
10738 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
10739 VT.getVectorElementType().getSizeInBits() ==
10740 OpVT.getVectorElementType().getSizeInBits()) {
10741 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
10746 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
10747 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
10748 // (and (i32 x86isd::setcc_carry), 1)
10749 // This eliminates the zext. This transformation is necessary because
10750 // ISD::SETCC is always legalized to i8.
10751 DebugLoc dl = N->getDebugLoc();
10752 SDValue N0 = N->getOperand(0);
10753 EVT VT = N->getValueType(0);
10754 if (N0.getOpcode() == ISD::AND &&
10756 N0.getOperand(0).hasOneUse()) {
10757 SDValue N00 = N0.getOperand(0);
10758 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
10760 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
10761 if (!C || C->getZExtValue() != 1)
10763 return DAG.getNode(ISD::AND, dl, VT,
10764 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
10765 N00.getOperand(0), N00.getOperand(1)),
10766 DAG.getConstant(1, VT));
10772 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
10773 DAGCombinerInfo &DCI) const {
10774 SelectionDAG &DAG = DCI.DAG;
10775 switch (N->getOpcode()) {
10777 case ISD::EXTRACT_VECTOR_ELT:
10778 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
10779 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
10780 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
10781 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
10784 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
10785 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
10786 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
10788 case X86ISD::FOR: return PerformFORCombine(N, DAG);
10789 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
10790 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
10791 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
10792 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
10793 case X86ISD::SHUFPS: // Handle all target specific shuffles
10794 case X86ISD::SHUFPD:
10795 case X86ISD::PALIGN:
10796 case X86ISD::PUNPCKHBW:
10797 case X86ISD::PUNPCKHWD:
10798 case X86ISD::PUNPCKHDQ:
10799 case X86ISD::PUNPCKHQDQ:
10800 case X86ISD::UNPCKHPS:
10801 case X86ISD::UNPCKHPD:
10802 case X86ISD::PUNPCKLBW:
10803 case X86ISD::PUNPCKLWD:
10804 case X86ISD::PUNPCKLDQ:
10805 case X86ISD::PUNPCKLQDQ:
10806 case X86ISD::UNPCKLPS:
10807 case X86ISD::UNPCKLPD:
10808 case X86ISD::MOVHLPS:
10809 case X86ISD::MOVLHPS:
10810 case X86ISD::PSHUFD:
10811 case X86ISD::PSHUFHW:
10812 case X86ISD::PSHUFLW:
10813 case X86ISD::MOVSS:
10814 case X86ISD::MOVSD:
10815 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
10821 /// isTypeDesirableForOp - Return true if the target has native support for
10822 /// the specified value type and it is 'desirable' to use the type for the
10823 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
10824 /// instruction encodings are longer and some i16 instructions are slow.
10825 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
10826 if (!isTypeLegal(VT))
10828 if (VT != MVT::i16)
10835 case ISD::SIGN_EXTEND:
10836 case ISD::ZERO_EXTEND:
10837 case ISD::ANY_EXTEND:
10850 /// IsDesirableToPromoteOp - This method query the target whether it is
10851 /// beneficial for dag combiner to promote the specified node. If true, it
10852 /// should return the desired promotion type by reference.
10853 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
10854 EVT VT = Op.getValueType();
10855 if (VT != MVT::i16)
10858 bool Promote = false;
10859 bool Commute = false;
10860 switch (Op.getOpcode()) {
10863 LoadSDNode *LD = cast<LoadSDNode>(Op);
10864 // If the non-extending load has a single use and it's not live out, then it
10865 // might be folded.
10866 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
10867 Op.hasOneUse()*/) {
10868 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
10869 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
10870 // The only case where we'd want to promote LOAD (rather then it being
10871 // promoted as an operand is when it's only use is liveout.
10872 if (UI->getOpcode() != ISD::CopyToReg)
10879 case ISD::SIGN_EXTEND:
10880 case ISD::ZERO_EXTEND:
10881 case ISD::ANY_EXTEND:
10886 SDValue N0 = Op.getOperand(0);
10887 // Look out for (store (shl (load), x)).
10888 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
10901 SDValue N0 = Op.getOperand(0);
10902 SDValue N1 = Op.getOperand(1);
10903 if (!Commute && MayFoldLoad(N1))
10905 // Avoid disabling potential load folding opportunities.
10906 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
10908 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
10918 //===----------------------------------------------------------------------===//
10919 // X86 Inline Assembly Support
10920 //===----------------------------------------------------------------------===//
10922 static bool LowerToBSwap(CallInst *CI) {
10923 // FIXME: this should verify that we are targetting a 486 or better. If not,
10924 // we will turn this bswap into something that will be lowered to logical ops
10925 // instead of emitting the bswap asm. For now, we don't support 486 or lower
10926 // so don't worry about this.
10928 // Verify this is a simple bswap.
10929 if (CI->getNumArgOperands() != 1 ||
10930 CI->getType() != CI->getArgOperand(0)->getType() ||
10931 !CI->getType()->isIntegerTy())
10934 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10935 if (!Ty || Ty->getBitWidth() % 16 != 0)
10938 // Okay, we can do this xform, do so now.
10939 const Type *Tys[] = { Ty };
10940 Module *M = CI->getParent()->getParent()->getParent();
10941 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
10943 Value *Op = CI->getArgOperand(0);
10944 Op = CallInst::Create(Int, Op, CI->getName(), CI);
10946 CI->replaceAllUsesWith(Op);
10947 CI->eraseFromParent();
10951 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
10952 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10953 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
10955 std::string AsmStr = IA->getAsmString();
10957 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
10958 SmallVector<StringRef, 4> AsmPieces;
10959 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
10961 switch (AsmPieces.size()) {
10962 default: return false;
10964 AsmStr = AsmPieces[0];
10966 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
10969 if (AsmPieces.size() == 2 &&
10970 (AsmPieces[0] == "bswap" ||
10971 AsmPieces[0] == "bswapq" ||
10972 AsmPieces[0] == "bswapl") &&
10973 (AsmPieces[1] == "$0" ||
10974 AsmPieces[1] == "${0:q}")) {
10975 // No need to check constraints, nothing other than the equivalent of
10976 // "=r,0" would be valid here.
10977 return LowerToBSwap(CI);
10979 // rorw $$8, ${0:w} --> llvm.bswap.i16
10980 if (CI->getType()->isIntegerTy(16) &&
10981 AsmPieces.size() == 3 &&
10982 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
10983 AsmPieces[1] == "$$8," &&
10984 AsmPieces[2] == "${0:w}" &&
10985 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
10987 const std::string &Constraints = IA->getConstraintString();
10988 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
10989 std::sort(AsmPieces.begin(), AsmPieces.end());
10990 if (AsmPieces.size() == 4 &&
10991 AsmPieces[0] == "~{cc}" &&
10992 AsmPieces[1] == "~{dirflag}" &&
10993 AsmPieces[2] == "~{flags}" &&
10994 AsmPieces[3] == "~{fpsr}") {
10995 return LowerToBSwap(CI);
11000 if (CI->getType()->isIntegerTy(64) &&
11001 Constraints.size() >= 2 &&
11002 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
11003 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
11004 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
11005 SmallVector<StringRef, 4> Words;
11006 SplitString(AsmPieces[0], Words, " \t");
11007 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
11009 SplitString(AsmPieces[1], Words, " \t");
11010 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
11012 SplitString(AsmPieces[2], Words, " \t,");
11013 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
11014 Words[2] == "%edx") {
11015 return LowerToBSwap(CI);
11027 /// getConstraintType - Given a constraint letter, return the type of
11028 /// constraint it is for this target.
11029 X86TargetLowering::ConstraintType
11030 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
11031 if (Constraint.size() == 1) {
11032 switch (Constraint[0]) {
11044 return C_RegisterClass;
11052 return TargetLowering::getConstraintType(Constraint);
11055 /// LowerXConstraint - try to replace an X constraint, which matches anything,
11056 /// with another that has more specific requirements based on the type of the
11057 /// corresponding operand.
11058 const char *X86TargetLowering::
11059 LowerXConstraint(EVT ConstraintVT) const {
11060 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
11061 // 'f' like normal targets.
11062 if (ConstraintVT.isFloatingPoint()) {
11063 if (Subtarget->hasSSE2())
11065 if (Subtarget->hasSSE1())
11069 return TargetLowering::LowerXConstraint(ConstraintVT);
11072 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
11073 /// vector. If it is invalid, don't add anything to Ops.
11074 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
11076 std::vector<SDValue>&Ops,
11077 SelectionDAG &DAG) const {
11078 SDValue Result(0, 0);
11080 switch (Constraint) {
11083 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11084 if (C->getZExtValue() <= 31) {
11085 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11091 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11092 if (C->getZExtValue() <= 63) {
11093 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11099 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11100 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
11101 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11107 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11108 if (C->getZExtValue() <= 255) {
11109 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11115 // 32-bit signed value
11116 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11117 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
11118 C->getSExtValue())) {
11119 // Widen to 64 bits here to get it sign extended.
11120 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
11123 // FIXME gcc accepts some relocatable values here too, but only in certain
11124 // memory models; it's complicated.
11129 // 32-bit unsigned value
11130 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11131 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
11132 C->getZExtValue())) {
11133 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11137 // FIXME gcc accepts some relocatable values here too, but only in certain
11138 // memory models; it's complicated.
11142 // Literal immediates are always ok.
11143 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
11144 // Widen to 64 bits here to get it sign extended.
11145 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
11149 // In any sort of PIC mode addresses need to be computed at runtime by
11150 // adding in a register or some sort of table lookup. These can't
11151 // be used as immediates.
11152 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
11155 // If we are in non-pic codegen mode, we allow the address of a global (with
11156 // an optional displacement) to be used with 'i'.
11157 GlobalAddressSDNode *GA = 0;
11158 int64_t Offset = 0;
11160 // Match either (GA), (GA+C), (GA+C1+C2), etc.
11162 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
11163 Offset += GA->getOffset();
11165 } else if (Op.getOpcode() == ISD::ADD) {
11166 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
11167 Offset += C->getZExtValue();
11168 Op = Op.getOperand(0);
11171 } else if (Op.getOpcode() == ISD::SUB) {
11172 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
11173 Offset += -C->getZExtValue();
11174 Op = Op.getOperand(0);
11179 // Otherwise, this isn't something we can handle, reject it.
11183 const GlobalValue *GV = GA->getGlobal();
11184 // If we require an extra load to get this address, as in PIC mode, we
11185 // can't accept it.
11186 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
11187 getTargetMachine())))
11190 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
11191 GA->getValueType(0), Offset);
11196 if (Result.getNode()) {
11197 Ops.push_back(Result);
11200 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11203 std::vector<unsigned> X86TargetLowering::
11204 getRegClassForInlineAsmConstraint(const std::string &Constraint,
11206 if (Constraint.size() == 1) {
11207 // FIXME: not handling fp-stack yet!
11208 switch (Constraint[0]) { // GCC X86 Constraint Letters
11209 default: break; // Unknown constraint letter
11210 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
11211 if (Subtarget->is64Bit()) {
11212 if (VT == MVT::i32)
11213 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
11214 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
11215 X86::R10D,X86::R11D,X86::R12D,
11216 X86::R13D,X86::R14D,X86::R15D,
11217 X86::EBP, X86::ESP, 0);
11218 else if (VT == MVT::i16)
11219 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
11220 X86::SI, X86::DI, X86::R8W,X86::R9W,
11221 X86::R10W,X86::R11W,X86::R12W,
11222 X86::R13W,X86::R14W,X86::R15W,
11223 X86::BP, X86::SP, 0);
11224 else if (VT == MVT::i8)
11225 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
11226 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
11227 X86::R10B,X86::R11B,X86::R12B,
11228 X86::R13B,X86::R14B,X86::R15B,
11229 X86::BPL, X86::SPL, 0);
11231 else if (VT == MVT::i64)
11232 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
11233 X86::RSI, X86::RDI, X86::R8, X86::R9,
11234 X86::R10, X86::R11, X86::R12,
11235 X86::R13, X86::R14, X86::R15,
11236 X86::RBP, X86::RSP, 0);
11240 // 32-bit fallthrough
11241 case 'Q': // Q_REGS
11242 if (VT == MVT::i32)
11243 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
11244 else if (VT == MVT::i16)
11245 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
11246 else if (VT == MVT::i8)
11247 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
11248 else if (VT == MVT::i64)
11249 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
11254 return std::vector<unsigned>();
11257 std::pair<unsigned, const TargetRegisterClass*>
11258 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
11260 // First, see if this is a constraint that directly corresponds to an LLVM
11262 if (Constraint.size() == 1) {
11263 // GCC Constraint Letters
11264 switch (Constraint[0]) {
11266 case 'r': // GENERAL_REGS
11267 case 'l': // INDEX_REGS
11269 return std::make_pair(0U, X86::GR8RegisterClass);
11270 if (VT == MVT::i16)
11271 return std::make_pair(0U, X86::GR16RegisterClass);
11272 if (VT == MVT::i32 || !Subtarget->is64Bit())
11273 return std::make_pair(0U, X86::GR32RegisterClass);
11274 return std::make_pair(0U, X86::GR64RegisterClass);
11275 case 'R': // LEGACY_REGS
11277 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
11278 if (VT == MVT::i16)
11279 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
11280 if (VT == MVT::i32 || !Subtarget->is64Bit())
11281 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
11282 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
11283 case 'f': // FP Stack registers.
11284 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
11285 // value to the correct fpstack register class.
11286 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
11287 return std::make_pair(0U, X86::RFP32RegisterClass);
11288 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
11289 return std::make_pair(0U, X86::RFP64RegisterClass);
11290 return std::make_pair(0U, X86::RFP80RegisterClass);
11291 case 'y': // MMX_REGS if MMX allowed.
11292 if (!Subtarget->hasMMX()) break;
11293 return std::make_pair(0U, X86::VR64RegisterClass);
11294 case 'Y': // SSE_REGS if SSE2 allowed
11295 if (!Subtarget->hasSSE2()) break;
11297 case 'x': // SSE_REGS if SSE1 allowed
11298 if (!Subtarget->hasSSE1()) break;
11300 switch (VT.getSimpleVT().SimpleTy) {
11302 // Scalar SSE types.
11305 return std::make_pair(0U, X86::FR32RegisterClass);
11308 return std::make_pair(0U, X86::FR64RegisterClass);
11316 return std::make_pair(0U, X86::VR128RegisterClass);
11322 // Use the default implementation in TargetLowering to convert the register
11323 // constraint into a member of a register class.
11324 std::pair<unsigned, const TargetRegisterClass*> Res;
11325 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
11327 // Not found as a standard register?
11328 if (Res.second == 0) {
11329 // Map st(0) -> st(7) -> ST0
11330 if (Constraint.size() == 7 && Constraint[0] == '{' &&
11331 tolower(Constraint[1]) == 's' &&
11332 tolower(Constraint[2]) == 't' &&
11333 Constraint[3] == '(' &&
11334 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
11335 Constraint[5] == ')' &&
11336 Constraint[6] == '}') {
11338 Res.first = X86::ST0+Constraint[4]-'0';
11339 Res.second = X86::RFP80RegisterClass;
11343 // GCC allows "st(0)" to be called just plain "st".
11344 if (StringRef("{st}").equals_lower(Constraint)) {
11345 Res.first = X86::ST0;
11346 Res.second = X86::RFP80RegisterClass;
11351 if (StringRef("{flags}").equals_lower(Constraint)) {
11352 Res.first = X86::EFLAGS;
11353 Res.second = X86::CCRRegisterClass;
11357 // 'A' means EAX + EDX.
11358 if (Constraint == "A") {
11359 Res.first = X86::EAX;
11360 Res.second = X86::GR32_ADRegisterClass;
11366 // Otherwise, check to see if this is a register class of the wrong value
11367 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
11368 // turn into {ax},{dx}.
11369 if (Res.second->hasType(VT))
11370 return Res; // Correct type already, nothing to do.
11372 // All of the single-register GCC register classes map their values onto
11373 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
11374 // really want an 8-bit or 32-bit register, map to the appropriate register
11375 // class and return the appropriate register.
11376 if (Res.second == X86::GR16RegisterClass) {
11377 if (VT == MVT::i8) {
11378 unsigned DestReg = 0;
11379 switch (Res.first) {
11381 case X86::AX: DestReg = X86::AL; break;
11382 case X86::DX: DestReg = X86::DL; break;
11383 case X86::CX: DestReg = X86::CL; break;
11384 case X86::BX: DestReg = X86::BL; break;
11387 Res.first = DestReg;
11388 Res.second = X86::GR8RegisterClass;
11390 } else if (VT == MVT::i32) {
11391 unsigned DestReg = 0;
11392 switch (Res.first) {
11394 case X86::AX: DestReg = X86::EAX; break;
11395 case X86::DX: DestReg = X86::EDX; break;
11396 case X86::CX: DestReg = X86::ECX; break;
11397 case X86::BX: DestReg = X86::EBX; break;
11398 case X86::SI: DestReg = X86::ESI; break;
11399 case X86::DI: DestReg = X86::EDI; break;
11400 case X86::BP: DestReg = X86::EBP; break;
11401 case X86::SP: DestReg = X86::ESP; break;
11404 Res.first = DestReg;
11405 Res.second = X86::GR32RegisterClass;
11407 } else if (VT == MVT::i64) {
11408 unsigned DestReg = 0;
11409 switch (Res.first) {
11411 case X86::AX: DestReg = X86::RAX; break;
11412 case X86::DX: DestReg = X86::RDX; break;
11413 case X86::CX: DestReg = X86::RCX; break;
11414 case X86::BX: DestReg = X86::RBX; break;
11415 case X86::SI: DestReg = X86::RSI; break;
11416 case X86::DI: DestReg = X86::RDI; break;
11417 case X86::BP: DestReg = X86::RBP; break;
11418 case X86::SP: DestReg = X86::RSP; break;
11421 Res.first = DestReg;
11422 Res.second = X86::GR64RegisterClass;
11425 } else if (Res.second == X86::FR32RegisterClass ||
11426 Res.second == X86::FR64RegisterClass ||
11427 Res.second == X86::VR128RegisterClass) {
11428 // Handle references to XMM physical registers that got mapped into the
11429 // wrong class. This can happen with constraints like {xmm0} where the
11430 // target independent register mapper will just pick the first match it can
11431 // find, ignoring the required type.
11432 if (VT == MVT::f32)
11433 Res.second = X86::FR32RegisterClass;
11434 else if (VT == MVT::f64)
11435 Res.second = X86::FR64RegisterClass;
11436 else if (X86::VR128RegisterClass->hasType(VT))
11437 Res.second = X86::VR128RegisterClass;