1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/ADT/VectorExtras.h"
26 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/SSARegMap.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/ADT/StringExtras.h"
39 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
40 cl::desc("Enable fastcc on X86"));
41 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
42 : TargetLowering(TM) {
43 Subtarget = &TM.getSubtarget<X86Subtarget>();
44 X86ScalarSSE = Subtarget->hasSSE2();
45 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
47 // Set up the TargetLowering object.
49 // X86 is weird, it always uses i8 for shift amounts and setcc results.
50 setShiftAmountType(MVT::i8);
51 setSetCCResultType(MVT::i8);
52 setSetCCResultContents(ZeroOrOneSetCCResult);
53 setSchedulingPreference(SchedulingForRegPressure);
54 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
55 setStackPointerRegisterToSaveRestore(X86StackPtr);
57 if (Subtarget->isTargetDarwin()) {
58 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
59 setUseUnderscoreSetJmp(false);
60 setUseUnderscoreLongJmp(false);
61 } else if (Subtarget->isTargetMingw()) {
62 // MS runtime is weird: it exports _setjmp, but longjmp!
63 setUseUnderscoreSetJmp(true);
64 setUseUnderscoreLongJmp(false);
66 setUseUnderscoreSetJmp(true);
67 setUseUnderscoreLongJmp(true);
70 // Add legal addressing mode scale values.
71 addLegalAddressScale(8);
72 addLegalAddressScale(4);
73 addLegalAddressScale(2);
74 // Enter the ones which require both scale + index last. These are more
76 addLegalAddressScale(9);
77 addLegalAddressScale(5);
78 addLegalAddressScale(3);
80 // Set up the register classes.
81 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
82 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
83 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
84 if (Subtarget->is64Bit())
85 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
87 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
89 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
91 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
92 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
93 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
95 if (Subtarget->is64Bit()) {
96 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
97 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
100 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
101 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
103 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
106 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
108 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
109 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
110 // SSE has no i16 to fp conversion, only i32
112 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
114 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
115 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
118 if (!Subtarget->is64Bit()) {
119 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode.
120 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
121 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
124 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
126 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
127 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
130 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
132 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
133 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
136 // Handle FP_TO_UINT by promoting the destination to a larger signed
138 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
139 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
140 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
142 if (Subtarget->is64Bit()) {
143 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
144 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
146 if (X86ScalarSSE && !Subtarget->hasSSE3())
147 // Expand FP_TO_UINT into a select.
148 // FIXME: We would like to use a Custom expander here eventually to do
149 // the optimal thing for SSE vs. the default expansion in the legalizer.
150 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
152 // With SSE3 we can use fisttpll to convert to a signed i64.
153 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
156 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
158 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
159 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
162 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
163 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
164 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
165 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
166 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
167 if (Subtarget->is64Bit())
168 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
169 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
170 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
171 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
172 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
173 setOperationAction(ISD::FREM , MVT::f64 , Expand);
175 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
176 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
177 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
178 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
179 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
180 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
181 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
182 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
183 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
184 if (Subtarget->is64Bit()) {
185 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
186 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
187 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
190 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
191 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
193 // These should be promoted to a larger select which is supported.
194 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
195 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
196 // X86 wants to expand cmov itself.
197 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
198 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
199 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
200 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
201 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
202 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
203 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
204 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
205 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
206 if (Subtarget->is64Bit()) {
207 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
208 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
210 // X86 ret instruction may pop stack.
211 setOperationAction(ISD::RET , MVT::Other, Custom);
213 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
214 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
215 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
216 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
217 if (Subtarget->is64Bit()) {
218 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
219 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
220 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
221 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
223 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
224 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
225 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
226 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
227 // X86 wants to expand memset / memcpy itself.
228 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
229 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
231 // We don't have line number support yet.
232 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
233 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
234 // FIXME - use subtarget debug flags
235 if (!Subtarget->isTargetDarwin() &&
236 !Subtarget->isTargetELF() &&
237 !Subtarget->isTargetCygMing())
238 setOperationAction(ISD::LABEL, MVT::Other, Expand);
240 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
241 setOperationAction(ISD::VASTART , MVT::Other, Custom);
243 // Use the default implementation.
244 setOperationAction(ISD::VAARG , MVT::Other, Expand);
245 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
246 setOperationAction(ISD::VAEND , MVT::Other, Expand);
247 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
248 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
249 if (Subtarget->is64Bit())
250 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
251 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
254 // Set up the FP register classes.
255 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
256 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
258 // Use ANDPD to simulate FABS.
259 setOperationAction(ISD::FABS , MVT::f64, Custom);
260 setOperationAction(ISD::FABS , MVT::f32, Custom);
262 // Use XORP to simulate FNEG.
263 setOperationAction(ISD::FNEG , MVT::f64, Custom);
264 setOperationAction(ISD::FNEG , MVT::f32, Custom);
266 // Use ANDPD and ORPD to simulate FCOPYSIGN.
267 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
268 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
270 // We don't support sin/cos/fmod
271 setOperationAction(ISD::FSIN , MVT::f64, Expand);
272 setOperationAction(ISD::FCOS , MVT::f64, Expand);
273 setOperationAction(ISD::FREM , MVT::f64, Expand);
274 setOperationAction(ISD::FSIN , MVT::f32, Expand);
275 setOperationAction(ISD::FCOS , MVT::f32, Expand);
276 setOperationAction(ISD::FREM , MVT::f32, Expand);
278 // Expand FP immediates into loads from the stack, except for the special
280 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
281 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
282 addLegalFPImmediate(+0.0); // xorps / xorpd
284 // Set up the FP register classes.
285 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
287 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
288 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
289 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
292 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
293 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
296 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
297 addLegalFPImmediate(+0.0); // FLD0
298 addLegalFPImmediate(+1.0); // FLD1
299 addLegalFPImmediate(-0.0); // FLD0/FCHS
300 addLegalFPImmediate(-1.0); // FLD1/FCHS
303 // First set operation action for all vector types to expand. Then we
304 // will selectively turn on ones that can be effectively codegen'd.
305 for (unsigned VT = (unsigned)MVT::Vector + 1;
306 VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
307 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
308 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
309 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
310 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
311 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
312 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
313 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
314 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
315 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
316 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
317 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
318 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
319 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
320 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
321 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
324 if (Subtarget->hasMMX()) {
325 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
326 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
327 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
329 // FIXME: add MMX packed arithmetics
330 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
331 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
332 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
335 if (Subtarget->hasSSE1()) {
336 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
338 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
339 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
340 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
341 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
342 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
343 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
344 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
345 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
346 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
349 if (Subtarget->hasSSE2()) {
350 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
351 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
352 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
353 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
354 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
356 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
357 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
358 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
359 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
360 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
361 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
362 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
363 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
364 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
365 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
366 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
368 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
369 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
370 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
371 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
372 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
373 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
375 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
376 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
377 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
378 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
379 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
381 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
382 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
383 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
384 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
385 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
386 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
388 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
389 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
390 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
391 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
392 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
393 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
394 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
395 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
396 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
397 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
398 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
399 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
402 // Custom lower v2i64 and v2f64 selects.
403 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
404 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
405 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
406 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
409 // We want to custom lower some of our intrinsics.
410 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
412 // We have target-specific dag combine patterns for the following nodes:
413 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
414 setTargetDAGCombine(ISD::SELECT);
416 computeRegisterProperties();
418 // FIXME: These should be based on subtarget info. Plus, the values should
419 // be smaller when we are in optimizing for size mode.
420 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
421 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
422 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
423 allowUnalignedMemoryAccesses = true; // x86 supports it!
427 //===----------------------------------------------------------------------===//
428 // Return Value Calling Convention Implementation
429 //===----------------------------------------------------------------------===//
431 /// GetRetValueLocs - If we are returning a set of values with the specified
432 /// value types, determine the set of registers each one will land in. This
433 /// sets one element of the ResultRegs array for each element in the VTs array.
434 static void GetRetValueLocs(const MVT::ValueType *VTs, unsigned NumVTs,
435 unsigned *ResultRegs,
436 const X86Subtarget *Subtarget,
437 unsigned CallingConv) {
438 if (NumVTs == 0) return;
441 ResultRegs[0] = VTs[0] == MVT::i64 ? X86::RAX : X86::EAX;
442 ResultRegs[1] = VTs[1] == MVT::i64 ? X86::RDX : X86::EDX;
446 // Otherwise, NumVTs is 1.
447 MVT::ValueType ArgVT = VTs[0];
451 case MVT::i8: Reg = X86::AL; break;
452 case MVT::i16: Reg = X86::AX; break;
453 case MVT::i32: Reg = X86::EAX; break;
454 case MVT::i64: Reg = X86::RAX; break;
457 if (Subtarget->is64Bit())
458 Reg = X86::XMM0; // FP values in X86-64 go in XMM0.
460 Reg = X86::ST0; // FP values in X86-32 go in ST0.
463 assert(MVT::isVector(ArgVT) && "Unknown return value type!");
464 Reg = X86::XMM0; // Int/FP vector result -> XMM0.
470 /// LowerRET - Lower an ISD::RET node.
471 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
472 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
474 // Support up returning up to two registers.
475 MVT::ValueType VTs[2];
476 unsigned DestRegs[2];
477 unsigned NumRegs = Op.getNumOperands() / 2;
478 assert(NumRegs <= 2 && "Can only return up to two regs!");
480 for (unsigned i = 0; i != NumRegs; ++i)
481 VTs[i] = Op.getOperand(i*2+1).getValueType();
483 // Determine which register each value should be copied into.
484 GetRetValueLocs(VTs, NumRegs, DestRegs, Subtarget,
485 DAG.getMachineFunction().getFunction()->getCallingConv());
487 // If this is the first return lowered for this function, add the regs to the
488 // liveout set for the function.
489 if (DAG.getMachineFunction().liveout_empty()) {
490 for (unsigned i = 0; i != NumRegs; ++i)
491 DAG.getMachineFunction().addLiveOut(DestRegs[i]);
494 SDOperand Chain = Op.getOperand(0);
497 // Copy the result values into the output registers.
498 if (NumRegs != 1 || DestRegs[0] != X86::ST0) {
499 for (unsigned i = 0; i != NumRegs; ++i) {
500 Chain = DAG.getCopyToReg(Chain, DestRegs[i], Op.getOperand(i*2+1), Flag);
501 Flag = Chain.getValue(1);
504 // We need to handle a destination of ST0 specially, because it isn't really
506 SDOperand Value = Op.getOperand(1);
508 // If this is an FP return with ScalarSSE, we need to move the value from
509 // an XMM register onto the fp-stack.
513 // If this is a load into a scalarsse value, don't store the loaded value
514 // back to the stack, only to reload it: just replace the scalar-sse load.
515 if (ISD::isNON_EXTLoad(Value.Val) &&
516 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
517 Chain = Value.getOperand(0);
518 MemLoc = Value.getOperand(1);
520 // Spill the value to memory and reload it into top of stack.
521 unsigned Size = MVT::getSizeInBits(VTs[0])/8;
522 MachineFunction &MF = DAG.getMachineFunction();
523 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
524 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
525 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
527 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
528 SDOperand Ops[] = { Chain, MemLoc, DAG.getValueType(VTs[0]) };
529 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
530 Chain = Value.getValue(1);
533 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
534 SDOperand Ops[] = { Chain, Value };
535 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
536 Flag = Chain.getValue(1);
539 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
541 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
543 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
547 /// LowerCallResult - Lower the result values of an ISD::CALL into the
548 /// appropriate copies out of appropriate physical registers. This assumes that
549 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
550 /// being lowered. The returns a SDNode with the same number of values as the
552 SDNode *X86TargetLowering::
553 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
554 unsigned CallingConv, SelectionDAG &DAG) {
555 SmallVector<SDOperand, 8> ResultVals;
557 // We support returning up to two registers.
558 MVT::ValueType VTs[2];
559 unsigned DestRegs[2];
560 unsigned NumRegs = TheCall->getNumValues() - 1;
561 assert(NumRegs <= 2 && "Can only return up to two regs!");
563 for (unsigned i = 0; i != NumRegs; ++i)
564 VTs[i] = TheCall->getValueType(i);
566 // Determine which register each value should be copied into.
567 GetRetValueLocs(VTs, NumRegs, DestRegs, Subtarget, CallingConv);
569 // Copy all of the result registers out of their specified physreg.
570 if (NumRegs != 1 || DestRegs[0] != X86::ST0) {
571 for (unsigned i = 0; i != NumRegs; ++i) {
572 Chain = DAG.getCopyFromReg(Chain, DestRegs[i], VTs[i],
574 InFlag = Chain.getValue(2);
575 ResultVals.push_back(Chain.getValue(0));
578 // Copies from the FP stack are special, as ST0 isn't a valid register
579 // before the fp stackifier runs.
581 // Copy ST0 into an RFP register with FP_GET_RESULT.
582 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
583 SDOperand GROps[] = { Chain, InFlag };
584 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
585 Chain = RetVal.getValue(1);
586 InFlag = RetVal.getValue(2);
588 // If we are using ScalarSSE, store ST(0) to the stack and reload it into
591 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
592 // shouldn't be necessary except that RFP cannot be live across
593 // multiple blocks. When stackifier is fixed, they can be uncoupled.
594 MachineFunction &MF = DAG.getMachineFunction();
595 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
596 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
598 Chain, RetVal, StackSlot, DAG.getValueType(VTs[0]), InFlag
600 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
601 RetVal = DAG.getLoad(VTs[0], Chain, StackSlot, NULL, 0);
602 Chain = RetVal.getValue(1);
605 if (VTs[0] == MVT::f32 && !X86ScalarSSE)
606 // FIXME: we would really like to remember that this FP_ROUND
607 // operation is okay to eliminate if we allow excess FP precision.
608 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
609 ResultVals.push_back(RetVal);
612 // Merge everything together with a MERGE_VALUES node.
613 ResultVals.push_back(Chain);
614 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
615 &ResultVals[0], ResultVals.size()).Val;
619 //===----------------------------------------------------------------------===//
620 // C & StdCall Calling Convention implementation
621 //===----------------------------------------------------------------------===//
622 // StdCall calling convention seems to be standard for many Windows' API
623 // routines and around. It differs from C calling convention just a little:
624 // callee should clean up the stack, not caller. Symbols should be also
625 // decorated in some fancy way :) It doesn't support any vector arguments.
627 /// AddLiveIn - This helper function adds the specified physical register to the
628 /// MachineFunction as a live in value. It also creates a corresponding virtual
630 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
631 const TargetRegisterClass *RC) {
632 assert(RC->contains(PReg) && "Not the correct regclass!");
633 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
634 MF.addLiveIn(PReg, VReg);
638 /// HowToPassArgument - Returns how an formal argument of the specified type
639 /// should be passed. If it is through stack, returns the size of the stack
640 /// slot; if it is through integer or XMM register, returns the number of
641 /// integer or XMM registers are needed.
643 HowToPassCallArgument(MVT::ValueType ObjectVT,
645 unsigned NumIntRegs, unsigned NumXMMRegs,
646 unsigned MaxNumIntRegs,
647 unsigned &ObjSize, unsigned &ObjIntRegs,
648 unsigned &ObjXMMRegs) {
653 if (MaxNumIntRegs>3) {
654 // We don't have too much registers on ia32! :)
659 default: assert(0 && "Unhandled argument type!");
661 if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
667 if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
673 if (ArgInReg && (NumIntRegs < MaxNumIntRegs))
679 if (ArgInReg && (NumIntRegs+2 <= MaxNumIntRegs)) {
681 } else if (ArgInReg && (NumIntRegs+1 <= MaxNumIntRegs)) {
706 SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
708 unsigned NumArgs = Op.Val->getNumValues() - 1;
709 MachineFunction &MF = DAG.getMachineFunction();
710 MachineFrameInfo *MFI = MF.getFrameInfo();
711 SDOperand Root = Op.getOperand(0);
712 SmallVector<SDOperand, 8> ArgValues;
713 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
715 // Add DAG nodes to load the arguments... On entry to a function on the X86,
716 // the stack frame looks like this:
718 // [ESP] -- return address
719 // [ESP + 4] -- first argument (leftmost lexically)
720 // [ESP + 8] -- second argument, if first argument is <= 4 bytes in size
723 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
724 unsigned NumSRetBytes= 0; // How much bytes on stack used for struct return
725 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
726 unsigned NumIntRegs = 0; // Integer regs used for parameter passing
728 static const unsigned XMMArgRegs[] = {
729 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
731 static const unsigned GPRArgRegs[][3] = {
732 { X86::AL, X86::DL, X86::CL },
733 { X86::AX, X86::DX, X86::CX },
734 { X86::EAX, X86::EDX, X86::ECX }
736 static const TargetRegisterClass* GPRClasses[3] = {
737 X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
740 // Handle regparm attribute
741 SmallVector<bool, 8> ArgInRegs(NumArgs, false);
742 SmallVector<bool, 8> SRetArgs(NumArgs, false);
744 for (unsigned i = 0; i<NumArgs; ++i) {
745 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue();
746 ArgInRegs[i] = (Flags >> 1) & 1;
747 SRetArgs[i] = (Flags >> 2) & 1;
751 for (unsigned i = 0; i < NumArgs; ++i) {
752 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
753 unsigned ArgIncrement = 4;
754 unsigned ObjSize = 0;
755 unsigned ObjXMMRegs = 0;
756 unsigned ObjIntRegs = 0;
760 HowToPassCallArgument(ObjectVT,
762 NumIntRegs, NumXMMRegs, 3,
763 ObjSize, ObjIntRegs, ObjXMMRegs);
766 ArgIncrement = ObjSize;
768 if (ObjIntRegs || ObjXMMRegs) {
770 default: assert(0 && "Unhandled argument type!");
774 unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][NumIntRegs];
775 Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
776 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
785 assert(!isStdCall && "Unhandled argument type!");
786 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
787 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
790 NumIntRegs += ObjIntRegs;
791 NumXMMRegs += ObjXMMRegs;
794 // XMM arguments have to be aligned on 16-byte boundary.
796 ArgOffset = ((ArgOffset + 15) / 16) * 16;
797 // Create the SelectionDAG nodes corresponding to a load from this
799 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
800 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
801 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
803 ArgOffset += ArgIncrement; // Move on to the next argument.
805 NumSRetBytes += ArgIncrement;
808 ArgValues.push_back(ArgValue);
811 ArgValues.push_back(Root);
813 // If the function takes variable number of arguments, make a frame index for
814 // the start of the first vararg value... for expansion of llvm.va_start.
816 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
818 if (isStdCall && !isVarArg) {
819 BytesToPopOnReturn = ArgOffset; // Callee pops everything..
820 BytesCallerReserves = 0;
822 BytesToPopOnReturn = NumSRetBytes; // Callee pops hidden struct pointer.
823 BytesCallerReserves = ArgOffset;
826 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
827 ReturnAddrIndex = 0; // No return address slot generated yet.
830 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn);
832 // Return the new list of results.
833 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
834 &ArgValues[0], ArgValues.size());
837 SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
839 SDOperand Chain = Op.getOperand(0);
840 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
841 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
842 SDOperand Callee = Op.getOperand(4);
843 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
845 static const unsigned XMMArgRegs[] = {
846 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
848 static const unsigned GPR32ArgRegs[] = {
849 X86::EAX, X86::EDX, X86::ECX
852 // Count how many bytes are to be pushed on the stack.
853 unsigned NumBytes = 0;
854 // Keep track of the number of integer regs passed so far.
855 unsigned NumIntRegs = 0;
856 // Keep track of the number of XMM regs passed so far.
857 unsigned NumXMMRegs = 0;
858 // How much bytes on stack used for struct return
859 unsigned NumSRetBytes= 0;
861 // Handle regparm attribute
862 SmallVector<bool, 8> ArgInRegs(NumOps, false);
863 SmallVector<bool, 8> SRetArgs(NumOps, false);
864 for (unsigned i = 0; i<NumOps; ++i) {
866 dyn_cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
867 ArgInRegs[i] = (Flags >> 1) & 1;
868 SRetArgs[i] = (Flags >> 2) & 1;
871 // Calculate stack frame size
872 for (unsigned i = 0; i != NumOps; ++i) {
873 SDOperand Arg = Op.getOperand(5+2*i);
874 unsigned ArgIncrement = 4;
875 unsigned ObjSize = 0;
876 unsigned ObjIntRegs = 0;
877 unsigned ObjXMMRegs = 0;
879 HowToPassCallArgument(Arg.getValueType(),
881 NumIntRegs, NumXMMRegs, 3,
882 ObjSize, ObjIntRegs, ObjXMMRegs);
884 ArgIncrement = ObjSize;
886 NumIntRegs += ObjIntRegs;
887 NumXMMRegs += ObjXMMRegs;
889 // XMM arguments have to be aligned on 16-byte boundary.
891 NumBytes = ((NumBytes + 15) / 16) * 16;
892 NumBytes += ArgIncrement;
896 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
898 // Arguments go on the stack in reverse order, as specified by the ABI.
899 unsigned ArgOffset = 0;
902 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
903 SmallVector<SDOperand, 8> MemOpChains;
904 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
905 for (unsigned i = 0; i != NumOps; ++i) {
906 SDOperand Arg = Op.getOperand(5+2*i);
907 unsigned ArgIncrement = 4;
908 unsigned ObjSize = 0;
909 unsigned ObjIntRegs = 0;
910 unsigned ObjXMMRegs = 0;
912 HowToPassCallArgument(Arg.getValueType(),
914 NumIntRegs, NumXMMRegs, 3,
915 ObjSize, ObjIntRegs, ObjXMMRegs);
918 ArgIncrement = ObjSize;
920 if (Arg.getValueType() == MVT::i8 || Arg.getValueType() == MVT::i16) {
921 // Promote the integer to 32 bits. If the input type is signed use a
922 // sign extend, otherwise use a zero extend.
923 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
925 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
926 Arg = DAG.getNode(ExtOp, MVT::i32, Arg);
929 if (ObjIntRegs || ObjXMMRegs) {
930 switch (Arg.getValueType()) {
931 default: assert(0 && "Unhandled argument type!");
933 RegsToPass.push_back(std::make_pair(GPR32ArgRegs[NumIntRegs], Arg));
941 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
945 NumIntRegs += ObjIntRegs;
946 NumXMMRegs += ObjXMMRegs;
949 // XMM arguments have to be aligned on 16-byte boundary.
951 ArgOffset = ((ArgOffset + 15) / 16) * 16;
953 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
954 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
955 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
957 ArgOffset += ArgIncrement; // Move on to the next argument.
959 NumSRetBytes += ArgIncrement;
963 // Sanity check: we haven't seen NumSRetBytes > 4
964 assert((NumSRetBytes<=4) &&
965 "Too much space for struct-return pointer requested");
967 if (!MemOpChains.empty())
968 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
969 &MemOpChains[0], MemOpChains.size());
971 // Build a sequence of copy-to-reg nodes chained together with token chain
972 // and flag operands which copy the outgoing args into registers.
974 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
975 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
977 InFlag = Chain.getValue(1);
980 // ELF / PIC requires GOT in the EBX register before function calls via PLT
982 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
983 Subtarget->isPICStyleGOT()) {
984 Chain = DAG.getCopyToReg(Chain, X86::EBX,
985 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
987 InFlag = Chain.getValue(1);
990 // If the callee is a GlobalAddress node (quite common, every direct call is)
991 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
992 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
993 // We should use extra load for direct calls to dllimported functions in
995 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
996 getTargetMachine(), true))
997 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
998 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
999 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1001 // Returns a chain & a flag for retval copy to use.
1002 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1003 SmallVector<SDOperand, 8> Ops;
1004 Ops.push_back(Chain);
1005 Ops.push_back(Callee);
1007 // Add argument registers to the end of the list so that they are known live
1009 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1010 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1011 RegsToPass[i].second.getValueType()));
1013 // Add an implicit use GOT pointer in EBX.
1014 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1015 Subtarget->isPICStyleGOT())
1016 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1019 Ops.push_back(InFlag);
1021 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1022 NodeTys, &Ops[0], Ops.size());
1023 InFlag = Chain.getValue(1);
1025 // Create the CALLSEQ_END node.
1026 unsigned NumBytesForCalleeToPush = 0;
1028 if (CC == CallingConv::X86_StdCall) {
1030 NumBytesForCalleeToPush = NumSRetBytes;
1032 NumBytesForCalleeToPush = NumBytes;
1034 // If this is is a call to a struct-return function, the callee
1035 // pops the hidden struct pointer, so we have to push it back.
1036 // This is common for Darwin/X86, Linux & Mingw32 targets.
1037 NumBytesForCalleeToPush = NumSRetBytes;
1040 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1042 Ops.push_back(Chain);
1043 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1044 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
1045 Ops.push_back(InFlag);
1046 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1047 InFlag = Chain.getValue(1);
1049 // Handle result values, copying them out of physregs into vregs that we
1051 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1055 //===----------------------------------------------------------------------===//
1056 // X86-64 C Calling Convention implementation
1057 //===----------------------------------------------------------------------===//
1059 /// HowToPassX86_64CCCArgument - Returns how an formal argument of the specified
1060 /// type should be passed. If it is through stack, returns the size of the stack
1061 /// slot; if it is through integer or XMM register, returns the number of
1062 /// integer or XMM registers are needed.
1064 HowToPassX86_64CCCArgument(MVT::ValueType ObjectVT,
1065 unsigned NumIntRegs, unsigned NumXMMRegs,
1066 unsigned &ObjSize, unsigned &ObjIntRegs,
1067 unsigned &ObjXMMRegs) {
1073 default: assert(0 && "Unhandled argument type!");
1083 case MVT::i8: ObjSize = 1; break;
1084 case MVT::i16: ObjSize = 2; break;
1085 case MVT::i32: ObjSize = 4; break;
1086 case MVT::i64: ObjSize = 8; break;
1103 case MVT::f32: ObjSize = 4; break;
1104 case MVT::f64: ObjSize = 8; break;
1110 case MVT::v2f64: ObjSize = 16; break;
1118 X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
1119 unsigned NumArgs = Op.Val->getNumValues() - 1;
1120 MachineFunction &MF = DAG.getMachineFunction();
1121 MachineFrameInfo *MFI = MF.getFrameInfo();
1122 SDOperand Root = Op.getOperand(0);
1123 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1124 SmallVector<SDOperand, 8> ArgValues;
1126 // Add DAG nodes to load the arguments... On entry to a function on the X86,
1127 // the stack frame looks like this:
1129 // [RSP] -- return address
1130 // [RSP + 8] -- first nonreg argument (leftmost lexically)
1131 // [RSP +16] -- second nonreg argument, if 1st argument is <= 8 bytes in size
1134 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
1135 unsigned NumIntRegs = 0; // Int regs used for parameter passing.
1136 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1138 static const unsigned GPR8ArgRegs[] = {
1139 X86::DIL, X86::SIL, X86::DL, X86::CL, X86::R8B, X86::R9B
1141 static const unsigned GPR16ArgRegs[] = {
1142 X86::DI, X86::SI, X86::DX, X86::CX, X86::R8W, X86::R9W
1144 static const unsigned GPR32ArgRegs[] = {
1145 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1147 static const unsigned GPR64ArgRegs[] = {
1148 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1150 static const unsigned XMMArgRegs[] = {
1151 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1152 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1155 for (unsigned i = 0; i < NumArgs; ++i) {
1156 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
1157 unsigned ArgIncrement = 8;
1158 unsigned ObjSize = 0;
1159 unsigned ObjIntRegs = 0;
1160 unsigned ObjXMMRegs = 0;
1162 // FIXME: __int128 and long double support?
1163 HowToPassX86_64CCCArgument(ObjectVT, NumIntRegs, NumXMMRegs,
1164 ObjSize, ObjIntRegs, ObjXMMRegs);
1166 ArgIncrement = ObjSize;
1170 if (ObjIntRegs || ObjXMMRegs) {
1172 default: assert(0 && "Unhandled argument type!");
1177 TargetRegisterClass *RC = NULL;
1181 RC = X86::GR8RegisterClass;
1182 Reg = GPR8ArgRegs[NumIntRegs];
1185 RC = X86::GR16RegisterClass;
1186 Reg = GPR16ArgRegs[NumIntRegs];
1189 RC = X86::GR32RegisterClass;
1190 Reg = GPR32ArgRegs[NumIntRegs];
1193 RC = X86::GR64RegisterClass;
1194 Reg = GPR64ArgRegs[NumIntRegs];
1197 Reg = AddLiveIn(MF, Reg, RC);
1198 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
1209 TargetRegisterClass *RC= (ObjectVT == MVT::f32) ?
1210 X86::FR32RegisterClass : ((ObjectVT == MVT::f64) ?
1211 X86::FR64RegisterClass : X86::VR128RegisterClass);
1212 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], RC);
1213 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
1217 NumIntRegs += ObjIntRegs;
1218 NumXMMRegs += ObjXMMRegs;
1219 } else if (ObjSize) {
1220 // XMM arguments have to be aligned on 16-byte boundary.
1222 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1223 // Create the SelectionDAG nodes corresponding to a load from this
1225 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
1226 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1227 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
1228 ArgOffset += ArgIncrement; // Move on to the next argument.
1231 ArgValues.push_back(ArgValue);
1234 // If the function takes variable number of arguments, make a frame index for
1235 // the start of the first vararg value... for expansion of llvm.va_start.
1237 // For X86-64, if there are vararg parameters that are passed via
1238 // registers, then we must store them to their spots on the stack so they
1239 // may be loaded by deferencing the result of va_next.
1240 VarArgsGPOffset = NumIntRegs * 8;
1241 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1242 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
1243 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1245 // Store the integer parameter registers.
1246 SmallVector<SDOperand, 8> MemOps;
1247 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1248 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1249 DAG.getConstant(VarArgsGPOffset, getPointerTy()));
1250 for (; NumIntRegs != 6; ++NumIntRegs) {
1251 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1252 X86::GR64RegisterClass);
1253 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1254 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1255 MemOps.push_back(Store);
1256 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1257 DAG.getConstant(8, getPointerTy()));
1260 // Now store the XMM (fp + vector) parameter registers.
1261 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1262 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1263 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1264 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1265 X86::VR128RegisterClass);
1266 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1267 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1268 MemOps.push_back(Store);
1269 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1270 DAG.getConstant(16, getPointerTy()));
1272 if (!MemOps.empty())
1273 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1274 &MemOps[0], MemOps.size());
1277 ArgValues.push_back(Root);
1279 ReturnAddrIndex = 0; // No return address slot generated yet.
1280 BytesToPopOnReturn = 0; // Callee pops nothing.
1281 BytesCallerReserves = ArgOffset;
1283 // Return the new list of results.
1284 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1285 &ArgValues[0], ArgValues.size());
1289 X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
1291 SDOperand Chain = Op.getOperand(0);
1292 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1293 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1294 SDOperand Callee = Op.getOperand(4);
1295 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1297 // Count how many bytes are to be pushed on the stack.
1298 unsigned NumBytes = 0;
1299 unsigned NumIntRegs = 0; // Int regs used for parameter passing.
1300 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1302 static const unsigned GPR8ArgRegs[] = {
1303 X86::DIL, X86::SIL, X86::DL, X86::CL, X86::R8B, X86::R9B
1305 static const unsigned GPR16ArgRegs[] = {
1306 X86::DI, X86::SI, X86::DX, X86::CX, X86::R8W, X86::R9W
1308 static const unsigned GPR32ArgRegs[] = {
1309 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1311 static const unsigned GPR64ArgRegs[] = {
1312 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1314 static const unsigned XMMArgRegs[] = {
1315 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1316 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1319 for (unsigned i = 0; i != NumOps; ++i) {
1320 SDOperand Arg = Op.getOperand(5+2*i);
1321 MVT::ValueType ArgVT = Arg.getValueType();
1324 default: assert(0 && "Unknown value type!");
1344 else if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
1347 // XMM arguments have to be aligned on 16-byte boundary.
1348 NumBytes = ((NumBytes + 15) / 16) * 16;
1355 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1357 // Arguments go on the stack in reverse order, as specified by the ABI.
1358 unsigned ArgOffset = 0;
1361 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1362 SmallVector<SDOperand, 8> MemOpChains;
1363 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
1364 for (unsigned i = 0; i != NumOps; ++i) {
1365 SDOperand Arg = Op.getOperand(5+2*i);
1366 MVT::ValueType ArgVT = Arg.getValueType();
1369 default: assert(0 && "Unexpected ValueType for argument!");
1374 if (NumIntRegs < 6) {
1378 case MVT::i8: Reg = GPR8ArgRegs[NumIntRegs]; break;
1379 case MVT::i16: Reg = GPR16ArgRegs[NumIntRegs]; break;
1380 case MVT::i32: Reg = GPR32ArgRegs[NumIntRegs]; break;
1381 case MVT::i64: Reg = GPR64ArgRegs[NumIntRegs]; break;
1383 RegsToPass.push_back(std::make_pair(Reg, Arg));
1386 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1387 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1388 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1400 if (NumXMMRegs < 8) {
1401 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
1404 if (ArgVT != MVT::f32 && ArgVT != MVT::f64) {
1405 // XMM arguments have to be aligned on 16-byte boundary.
1406 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1408 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1409 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1410 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1411 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
1419 if (!MemOpChains.empty())
1420 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1421 &MemOpChains[0], MemOpChains.size());
1423 // Build a sequence of copy-to-reg nodes chained together with token chain
1424 // and flag operands which copy the outgoing args into registers.
1426 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1427 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1429 InFlag = Chain.getValue(1);
1433 // From AMD64 ABI document:
1434 // For calls that may call functions that use varargs or stdargs
1435 // (prototype-less calls or calls to functions containing ellipsis (...) in
1436 // the declaration) %al is used as hidden argument to specify the number
1437 // of SSE registers used. The contents of %al do not need to match exactly
1438 // the number of registers, but must be an ubound on the number of SSE
1439 // registers used and is in the range 0 - 8 inclusive.
1440 Chain = DAG.getCopyToReg(Chain, X86::AL,
1441 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1442 InFlag = Chain.getValue(1);
1445 // If the callee is a GlobalAddress node (quite common, every direct call is)
1446 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1447 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1448 // We should use extra load for direct calls to dllimported functions in
1450 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1451 getTargetMachine(), true))
1452 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1453 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1454 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1456 // Returns a chain & a flag for retval copy to use.
1457 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1458 SmallVector<SDOperand, 8> Ops;
1459 Ops.push_back(Chain);
1460 Ops.push_back(Callee);
1462 // Add argument registers to the end of the list so that they are known live
1464 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1465 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1466 RegsToPass[i].second.getValueType()));
1469 Ops.push_back(InFlag);
1471 // FIXME: Do not generate X86ISD::TAILCALL for now.
1472 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1473 NodeTys, &Ops[0], Ops.size());
1474 InFlag = Chain.getValue(1);
1476 // Returns a flag for retval copy to use.
1477 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1479 Ops.push_back(Chain);
1480 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1481 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1482 Ops.push_back(InFlag);
1483 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1484 InFlag = Chain.getValue(1);
1486 // Handle result values, copying them out of physregs into vregs that we
1488 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1491 //===----------------------------------------------------------------------===//
1492 // Fast & FastCall Calling Convention implementation
1493 //===----------------------------------------------------------------------===//
1495 // The X86 'fast' calling convention passes up to two integer arguments in
1496 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
1497 // and requires that the callee pop its arguments off the stack (allowing proper
1498 // tail calls), and has the same return value conventions as C calling convs.
1500 // This calling convention always arranges for the callee pop value to be 8n+4
1501 // bytes, which is needed for tail recursion elimination and stack alignment
1504 // Note that this can be enhanced in the future to pass fp vals in registers
1505 // (when we have a global fp allocator) and do other tricks.
1507 //===----------------------------------------------------------------------===//
1508 // The X86 'fastcall' calling convention passes up to two integer arguments in
1509 // registers (an appropriate portion of ECX/EDX), passes arguments in C order,
1510 // and requires that the callee pop its arguments off the stack (allowing proper
1511 // tail calls), and has the same return value conventions as C calling convs.
1513 // This calling convention always arranges for the callee pop value to be 8n+4
1514 // bytes, which is needed for tail recursion elimination and stack alignment
1519 X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
1521 unsigned NumArgs = Op.Val->getNumValues()-1;
1522 MachineFunction &MF = DAG.getMachineFunction();
1523 MachineFrameInfo *MFI = MF.getFrameInfo();
1524 SDOperand Root = Op.getOperand(0);
1525 SmallVector<SDOperand, 8> ArgValues;
1527 // Add DAG nodes to load the arguments... On entry to a function the stack
1528 // frame looks like this:
1530 // [ESP] -- return address
1531 // [ESP + 4] -- first nonreg argument (leftmost lexically)
1532 // [ESP + 8] -- second nonreg argument, if 1st argument is <= 4 bytes in size
1534 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
1536 // Keep track of the number of integer regs passed so far. This can be either
1537 // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX
1539 unsigned NumIntRegs = 0;
1540 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1542 static const unsigned XMMArgRegs[] = {
1543 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1546 static const unsigned GPRArgRegs[][2][2] = {
1547 {{ X86::AL, X86::DL }, { X86::CL, X86::DL }},
1548 {{ X86::AX, X86::DX }, { X86::CX, X86::DX }},
1549 {{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }}
1552 static const TargetRegisterClass* GPRClasses[3] = {
1553 X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
1556 unsigned GPRInd = (isFastCall ? 1 : 0);
1557 for (unsigned i = 0; i < NumArgs; ++i) {
1558 MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
1559 unsigned ArgIncrement = 4;
1560 unsigned ObjSize = 0;
1561 unsigned ObjXMMRegs = 0;
1562 unsigned ObjIntRegs = 0;
1566 HowToPassCallArgument(ObjectVT,
1567 true, // Use as much registers as possible
1568 NumIntRegs, NumXMMRegs,
1569 (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS),
1570 ObjSize, ObjIntRegs, ObjXMMRegs);
1573 ArgIncrement = ObjSize;
1575 if (ObjIntRegs || ObjXMMRegs) {
1577 default: assert(0 && "Unhandled argument type!");
1581 unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][GPRInd][NumIntRegs];
1582 Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
1583 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
1592 assert(!isFastCall && "Unhandled argument type!");
1593 Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
1594 ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
1598 NumIntRegs += ObjIntRegs;
1599 NumXMMRegs += ObjXMMRegs;
1602 // XMM arguments have to be aligned on 16-byte boundary.
1604 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1605 // Create the SelectionDAG nodes corresponding to a load from this
1607 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
1608 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1609 ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN, NULL, 0);
1611 ArgOffset += ArgIncrement; // Move on to the next argument.
1614 ArgValues.push_back(ArgValue);
1617 ArgValues.push_back(Root);
1619 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1620 // arguments and the arguments after the retaddr has been pushed are aligned.
1621 if ((ArgOffset & 7) == 0)
1624 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1625 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
1626 ReturnAddrIndex = 0; // No return address slot generated yet.
1627 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
1628 BytesCallerReserves = 0;
1630 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn);
1632 // Finally, inform the code generator which regs we return values in.
1633 switch (getValueType(MF.getFunction()->getReturnType())) {
1634 default: assert(0 && "Unknown type!");
1635 case MVT::isVoid: break;
1640 MF.addLiveOut(X86::EAX);
1643 MF.addLiveOut(X86::EAX);
1644 MF.addLiveOut(X86::EDX);
1648 MF.addLiveOut(X86::ST0);
1656 assert(!isFastCall && "Unknown result type");
1657 MF.addLiveOut(X86::XMM0);
1661 // Return the new list of results.
1662 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1663 &ArgValues[0], ArgValues.size());
1666 SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
1668 SDOperand Chain = Op.getOperand(0);
1669 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1670 SDOperand Callee = Op.getOperand(4);
1671 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1673 // Count how many bytes are to be pushed on the stack.
1674 unsigned NumBytes = 0;
1676 // Keep track of the number of integer regs passed so far. This can be either
1677 // 0 (neither EAX/ECX or EDX used), 1 (EAX/ECX is used) or 2 (EAX/ECX and EDX
1679 unsigned NumIntRegs = 0;
1680 unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
1682 static const unsigned GPRArgRegs[][2][2] = {
1683 {{ X86::AL, X86::DL }, { X86::CL, X86::DL }},
1684 {{ X86::AX, X86::DX }, { X86::CX, X86::DX }},
1685 {{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }}
1687 static const unsigned XMMArgRegs[] = {
1688 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1691 bool isFastCall = CC == CallingConv::X86_FastCall;
1692 unsigned GPRInd = isFastCall ? 1 : 0;
1693 for (unsigned i = 0; i != NumOps; ++i) {
1694 SDOperand Arg = Op.getOperand(5+2*i);
1696 switch (Arg.getValueType()) {
1697 default: assert(0 && "Unknown value type!");
1701 unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
1702 if (NumIntRegs < MaxNumIntRegs) {
1719 assert(!isFastCall && "Unknown value type!");
1723 // XMM arguments have to be aligned on 16-byte boundary.
1724 NumBytes = ((NumBytes + 15) / 16) * 16;
1731 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1732 // arguments and the arguments after the retaddr has been pushed are aligned.
1733 if ((NumBytes & 7) == 0)
1736 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1738 // Arguments go on the stack in reverse order, as specified by the ABI.
1739 unsigned ArgOffset = 0;
1741 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1742 SmallVector<SDOperand, 8> MemOpChains;
1743 SDOperand StackPtr = DAG.getRegister(X86StackPtr, getPointerTy());
1744 for (unsigned i = 0; i != NumOps; ++i) {
1745 SDOperand Arg = Op.getOperand(5+2*i);
1747 switch (Arg.getValueType()) {
1748 default: assert(0 && "Unexpected ValueType for argument!");
1752 unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
1753 if (NumIntRegs < MaxNumIntRegs) {
1755 GPRArgRegs[Arg.getValueType()-MVT::i8][GPRInd][NumIntRegs];
1756 RegsToPass.push_back(std::make_pair(RegToUse, Arg));
1762 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1763 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1764 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1769 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1770 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1771 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1781 assert(!isFastCall && "Unexpected ValueType for argument!");
1782 if (NumXMMRegs < 4) {
1783 RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
1786 // XMM arguments have to be aligned on 16-byte boundary.
1787 ArgOffset = ((ArgOffset + 15) / 16) * 16;
1788 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1789 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1790 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1797 if (!MemOpChains.empty())
1798 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1799 &MemOpChains[0], MemOpChains.size());
1801 // Build a sequence of copy-to-reg nodes chained together with token chain
1802 // and flag operands which copy the outgoing args into registers.
1804 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1805 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1807 InFlag = Chain.getValue(1);
1810 // If the callee is a GlobalAddress node (quite common, every direct call is)
1811 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1812 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1813 // We should use extra load for direct calls to dllimported functions in
1815 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1816 getTargetMachine(), true))
1817 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1818 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1819 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1821 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1823 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1824 Subtarget->isPICStyleGOT()) {
1825 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1826 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1828 InFlag = Chain.getValue(1);
1831 // Returns a chain & a flag for retval copy to use.
1832 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1833 SmallVector<SDOperand, 8> Ops;
1834 Ops.push_back(Chain);
1835 Ops.push_back(Callee);
1837 // Add argument registers to the end of the list so that they are known live
1839 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1840 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1841 RegsToPass[i].second.getValueType()));
1843 // Add an implicit use GOT pointer in EBX.
1844 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1845 Subtarget->isPICStyleGOT())
1846 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1849 Ops.push_back(InFlag);
1851 // FIXME: Do not generate X86ISD::TAILCALL for now.
1852 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1853 NodeTys, &Ops[0], Ops.size());
1854 InFlag = Chain.getValue(1);
1856 // Returns a flag for retval copy to use.
1857 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1859 Ops.push_back(Chain);
1860 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1861 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1862 Ops.push_back(InFlag);
1863 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1864 InFlag = Chain.getValue(1);
1866 // Handle result values, copying them out of physregs into vregs that we
1868 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1871 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1872 if (ReturnAddrIndex == 0) {
1873 // Set up a frame object for the return address.
1874 MachineFunction &MF = DAG.getMachineFunction();
1875 if (Subtarget->is64Bit())
1876 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1878 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1881 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1886 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1887 /// specific condition code. It returns a false if it cannot do a direct
1888 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1890 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1891 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1892 SelectionDAG &DAG) {
1893 X86CC = X86::COND_INVALID;
1895 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1896 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1897 // X > -1 -> X == 0, jump !sign.
1898 RHS = DAG.getConstant(0, RHS.getValueType());
1899 X86CC = X86::COND_NS;
1901 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1902 // X < 0 -> X == 0, jump on sign.
1903 X86CC = X86::COND_S;
1908 switch (SetCCOpcode) {
1910 case ISD::SETEQ: X86CC = X86::COND_E; break;
1911 case ISD::SETGT: X86CC = X86::COND_G; break;
1912 case ISD::SETGE: X86CC = X86::COND_GE; break;
1913 case ISD::SETLT: X86CC = X86::COND_L; break;
1914 case ISD::SETLE: X86CC = X86::COND_LE; break;
1915 case ISD::SETNE: X86CC = X86::COND_NE; break;
1916 case ISD::SETULT: X86CC = X86::COND_B; break;
1917 case ISD::SETUGT: X86CC = X86::COND_A; break;
1918 case ISD::SETULE: X86CC = X86::COND_BE; break;
1919 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1922 // On a floating point condition, the flags are set as follows:
1924 // 0 | 0 | 0 | X > Y
1925 // 0 | 0 | 1 | X < Y
1926 // 1 | 0 | 0 | X == Y
1927 // 1 | 1 | 1 | unordered
1929 switch (SetCCOpcode) {
1932 case ISD::SETEQ: X86CC = X86::COND_E; break;
1933 case ISD::SETOLT: Flip = true; // Fallthrough
1935 case ISD::SETGT: X86CC = X86::COND_A; break;
1936 case ISD::SETOLE: Flip = true; // Fallthrough
1938 case ISD::SETGE: X86CC = X86::COND_AE; break;
1939 case ISD::SETUGT: Flip = true; // Fallthrough
1941 case ISD::SETLT: X86CC = X86::COND_B; break;
1942 case ISD::SETUGE: Flip = true; // Fallthrough
1944 case ISD::SETLE: X86CC = X86::COND_BE; break;
1946 case ISD::SETNE: X86CC = X86::COND_NE; break;
1947 case ISD::SETUO: X86CC = X86::COND_P; break;
1948 case ISD::SETO: X86CC = X86::COND_NP; break;
1951 std::swap(LHS, RHS);
1954 return X86CC != X86::COND_INVALID;
1957 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1958 /// code. Current x86 isa includes the following FP cmov instructions:
1959 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1960 static bool hasFPCMov(unsigned X86CC) {
1976 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1977 /// true if Op is undef or if its value falls within the specified range (L, H].
1978 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1979 if (Op.getOpcode() == ISD::UNDEF)
1982 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1983 return (Val >= Low && Val < Hi);
1986 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1987 /// true if Op is undef or if its value equal to the specified value.
1988 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1989 if (Op.getOpcode() == ISD::UNDEF)
1991 return cast<ConstantSDNode>(Op)->getValue() == Val;
1994 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1995 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1996 bool X86::isPSHUFDMask(SDNode *N) {
1997 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1999 if (N->getNumOperands() != 4)
2002 // Check if the value doesn't reference the second vector.
2003 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2004 SDOperand Arg = N->getOperand(i);
2005 if (Arg.getOpcode() == ISD::UNDEF) continue;
2006 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2007 if (cast<ConstantSDNode>(Arg)->getValue() >= 4)
2014 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2015 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2016 bool X86::isPSHUFHWMask(SDNode *N) {
2017 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2019 if (N->getNumOperands() != 8)
2022 // Lower quadword copied in order.
2023 for (unsigned i = 0; i != 4; ++i) {
2024 SDOperand Arg = N->getOperand(i);
2025 if (Arg.getOpcode() == ISD::UNDEF) continue;
2026 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2027 if (cast<ConstantSDNode>(Arg)->getValue() != i)
2031 // Upper quadword shuffled.
2032 for (unsigned i = 4; i != 8; ++i) {
2033 SDOperand Arg = N->getOperand(i);
2034 if (Arg.getOpcode() == ISD::UNDEF) continue;
2035 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2036 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2037 if (Val < 4 || Val > 7)
2044 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2045 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2046 bool X86::isPSHUFLWMask(SDNode *N) {
2047 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2049 if (N->getNumOperands() != 8)
2052 // Upper quadword copied in order.
2053 for (unsigned i = 4; i != 8; ++i)
2054 if (!isUndefOrEqual(N->getOperand(i), i))
2057 // Lower quadword shuffled.
2058 for (unsigned i = 0; i != 4; ++i)
2059 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2065 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2066 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2067 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
2068 if (NumElems != 2 && NumElems != 4) return false;
2070 unsigned Half = NumElems / 2;
2071 for (unsigned i = 0; i < Half; ++i)
2072 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2074 for (unsigned i = Half; i < NumElems; ++i)
2075 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2081 bool X86::isSHUFPMask(SDNode *N) {
2082 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2083 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2086 /// isCommutedSHUFP - Returns true if the shuffle mask is except
2087 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2088 /// half elements to come from vector 1 (which would equal the dest.) and
2089 /// the upper half to come from vector 2.
2090 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
2091 if (NumOps != 2 && NumOps != 4) return false;
2093 unsigned Half = NumOps / 2;
2094 for (unsigned i = 0; i < Half; ++i)
2095 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2097 for (unsigned i = Half; i < NumOps; ++i)
2098 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2103 static bool isCommutedSHUFP(SDNode *N) {
2104 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2105 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2108 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2109 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2110 bool X86::isMOVHLPSMask(SDNode *N) {
2111 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2113 if (N->getNumOperands() != 4)
2116 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2117 return isUndefOrEqual(N->getOperand(0), 6) &&
2118 isUndefOrEqual(N->getOperand(1), 7) &&
2119 isUndefOrEqual(N->getOperand(2), 2) &&
2120 isUndefOrEqual(N->getOperand(3), 3);
2123 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2124 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2126 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2127 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2129 if (N->getNumOperands() != 4)
2132 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2133 return isUndefOrEqual(N->getOperand(0), 2) &&
2134 isUndefOrEqual(N->getOperand(1), 3) &&
2135 isUndefOrEqual(N->getOperand(2), 2) &&
2136 isUndefOrEqual(N->getOperand(3), 3);
2139 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2140 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2141 bool X86::isMOVLPMask(SDNode *N) {
2142 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2144 unsigned NumElems = N->getNumOperands();
2145 if (NumElems != 2 && NumElems != 4)
2148 for (unsigned i = 0; i < NumElems/2; ++i)
2149 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2152 for (unsigned i = NumElems/2; i < NumElems; ++i)
2153 if (!isUndefOrEqual(N->getOperand(i), i))
2159 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2160 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2162 bool X86::isMOVHPMask(SDNode *N) {
2163 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2165 unsigned NumElems = N->getNumOperands();
2166 if (NumElems != 2 && NumElems != 4)
2169 for (unsigned i = 0; i < NumElems/2; ++i)
2170 if (!isUndefOrEqual(N->getOperand(i), i))
2173 for (unsigned i = 0; i < NumElems/2; ++i) {
2174 SDOperand Arg = N->getOperand(i + NumElems/2);
2175 if (!isUndefOrEqual(Arg, i + NumElems))
2182 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2183 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2184 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
2185 bool V2IsSplat = false) {
2186 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2189 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2190 SDOperand BitI = Elts[i];
2191 SDOperand BitI1 = Elts[i+1];
2192 if (!isUndefOrEqual(BitI, j))
2195 if (isUndefOrEqual(BitI1, NumElts))
2198 if (!isUndefOrEqual(BitI1, j + NumElts))
2206 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2207 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2208 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2211 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2212 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2213 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
2214 bool V2IsSplat = false) {
2215 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2218 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2219 SDOperand BitI = Elts[i];
2220 SDOperand BitI1 = Elts[i+1];
2221 if (!isUndefOrEqual(BitI, j + NumElts/2))
2224 if (isUndefOrEqual(BitI1, NumElts))
2227 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2235 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2236 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2237 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2240 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2241 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2243 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2244 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2246 unsigned NumElems = N->getNumOperands();
2247 if (NumElems != 4 && NumElems != 8 && NumElems != 16)
2250 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2251 SDOperand BitI = N->getOperand(i);
2252 SDOperand BitI1 = N->getOperand(i+1);
2254 if (!isUndefOrEqual(BitI, j))
2256 if (!isUndefOrEqual(BitI1, j))
2263 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2264 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2265 /// MOVSD, and MOVD, i.e. setting the lowest element.
2266 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
2267 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2270 if (!isUndefOrEqual(Elts[0], NumElts))
2273 for (unsigned i = 1; i < NumElts; ++i) {
2274 if (!isUndefOrEqual(Elts[i], i))
2281 bool X86::isMOVLMask(SDNode *N) {
2282 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2283 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2286 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2287 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2288 /// element of vector 2 and the other elements to come from vector 1 in order.
2289 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
2290 bool V2IsSplat = false,
2291 bool V2IsUndef = false) {
2292 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2295 if (!isUndefOrEqual(Ops[0], 0))
2298 for (unsigned i = 1; i < NumOps; ++i) {
2299 SDOperand Arg = Ops[i];
2300 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2301 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2302 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2309 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2310 bool V2IsUndef = false) {
2311 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2312 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2313 V2IsSplat, V2IsUndef);
2316 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2317 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2318 bool X86::isMOVSHDUPMask(SDNode *N) {
2319 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2321 if (N->getNumOperands() != 4)
2324 // Expect 1, 1, 3, 3
2325 for (unsigned i = 0; i < 2; ++i) {
2326 SDOperand Arg = N->getOperand(i);
2327 if (Arg.getOpcode() == ISD::UNDEF) continue;
2328 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2329 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2330 if (Val != 1) return false;
2334 for (unsigned i = 2; i < 4; ++i) {
2335 SDOperand Arg = N->getOperand(i);
2336 if (Arg.getOpcode() == ISD::UNDEF) continue;
2337 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2338 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2339 if (Val != 3) return false;
2343 // Don't use movshdup if it can be done with a shufps.
2347 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2348 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2349 bool X86::isMOVSLDUPMask(SDNode *N) {
2350 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2352 if (N->getNumOperands() != 4)
2355 // Expect 0, 0, 2, 2
2356 for (unsigned i = 0; i < 2; ++i) {
2357 SDOperand Arg = N->getOperand(i);
2358 if (Arg.getOpcode() == ISD::UNDEF) continue;
2359 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2360 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2361 if (Val != 0) return false;
2365 for (unsigned i = 2; i < 4; ++i) {
2366 SDOperand Arg = N->getOperand(i);
2367 if (Arg.getOpcode() == ISD::UNDEF) continue;
2368 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2369 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2370 if (Val != 2) return false;
2374 // Don't use movshdup if it can be done with a shufps.
2378 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2379 /// a splat of a single element.
2380 static bool isSplatMask(SDNode *N) {
2381 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2383 // This is a splat operation if each element of the permute is the same, and
2384 // if the value doesn't reference the second vector.
2385 unsigned NumElems = N->getNumOperands();
2386 SDOperand ElementBase;
2388 for (; i != NumElems; ++i) {
2389 SDOperand Elt = N->getOperand(i);
2390 if (isa<ConstantSDNode>(Elt)) {
2396 if (!ElementBase.Val)
2399 for (; i != NumElems; ++i) {
2400 SDOperand Arg = N->getOperand(i);
2401 if (Arg.getOpcode() == ISD::UNDEF) continue;
2402 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2403 if (Arg != ElementBase) return false;
2406 // Make sure it is a splat of the first vector operand.
2407 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2410 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2411 /// a splat of a single element and it's a 2 or 4 element mask.
2412 bool X86::isSplatMask(SDNode *N) {
2413 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2415 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2416 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2418 return ::isSplatMask(N);
2421 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2422 /// specifies a splat of zero element.
2423 bool X86::isSplatLoMask(SDNode *N) {
2424 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2426 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2427 if (!isUndefOrEqual(N->getOperand(i), 0))
2432 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2433 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2435 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2436 unsigned NumOperands = N->getNumOperands();
2437 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2439 for (unsigned i = 0; i < NumOperands; ++i) {
2441 SDOperand Arg = N->getOperand(NumOperands-i-1);
2442 if (Arg.getOpcode() != ISD::UNDEF)
2443 Val = cast<ConstantSDNode>(Arg)->getValue();
2444 if (Val >= NumOperands) Val -= NumOperands;
2446 if (i != NumOperands - 1)
2453 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2454 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2456 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2458 // 8 nodes, but we only care about the last 4.
2459 for (unsigned i = 7; i >= 4; --i) {
2461 SDOperand Arg = N->getOperand(i);
2462 if (Arg.getOpcode() != ISD::UNDEF)
2463 Val = cast<ConstantSDNode>(Arg)->getValue();
2472 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2473 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2475 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2477 // 8 nodes, but we only care about the first 4.
2478 for (int i = 3; i >= 0; --i) {
2480 SDOperand Arg = N->getOperand(i);
2481 if (Arg.getOpcode() != ISD::UNDEF)
2482 Val = cast<ConstantSDNode>(Arg)->getValue();
2491 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2492 /// specifies a 8 element shuffle that can be broken into a pair of
2493 /// PSHUFHW and PSHUFLW.
2494 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2495 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2497 if (N->getNumOperands() != 8)
2500 // Lower quadword shuffled.
2501 for (unsigned i = 0; i != 4; ++i) {
2502 SDOperand Arg = N->getOperand(i);
2503 if (Arg.getOpcode() == ISD::UNDEF) continue;
2504 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2505 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2510 // Upper quadword shuffled.
2511 for (unsigned i = 4; i != 8; ++i) {
2512 SDOperand Arg = N->getOperand(i);
2513 if (Arg.getOpcode() == ISD::UNDEF) continue;
2514 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2515 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2516 if (Val < 4 || Val > 7)
2523 /// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
2524 /// values in ther permute mask.
2525 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2526 SDOperand &V2, SDOperand &Mask,
2527 SelectionDAG &DAG) {
2528 MVT::ValueType VT = Op.getValueType();
2529 MVT::ValueType MaskVT = Mask.getValueType();
2530 MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT);
2531 unsigned NumElems = Mask.getNumOperands();
2532 SmallVector<SDOperand, 8> MaskVec;
2534 for (unsigned i = 0; i != NumElems; ++i) {
2535 SDOperand Arg = Mask.getOperand(i);
2536 if (Arg.getOpcode() == ISD::UNDEF) {
2537 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2540 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2541 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2543 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2545 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2549 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2550 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2553 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2554 /// match movhlps. The lower half elements should come from upper half of
2555 /// V1 (and in order), and the upper half elements should come from the upper
2556 /// half of V2 (and in order).
2557 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2558 unsigned NumElems = Mask->getNumOperands();
2561 for (unsigned i = 0, e = 2; i != e; ++i)
2562 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2564 for (unsigned i = 2; i != 4; ++i)
2565 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2570 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2571 /// is promoted to a vector.
2572 static inline bool isScalarLoadToVector(SDNode *N) {
2573 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2574 N = N->getOperand(0).Val;
2575 return ISD::isNON_EXTLoad(N);
2580 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2581 /// match movlp{s|d}. The lower half elements should come from lower half of
2582 /// V1 (and in order), and the upper half elements should come from the upper
2583 /// half of V2 (and in order). And since V1 will become the source of the
2584 /// MOVLP, it must be either a vector load or a scalar load to vector.
2585 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2586 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2588 // Is V2 is a vector load, don't do this transformation. We will try to use
2589 // load folding shufps op.
2590 if (ISD::isNON_EXTLoad(V2))
2593 unsigned NumElems = Mask->getNumOperands();
2594 if (NumElems != 2 && NumElems != 4)
2596 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2597 if (!isUndefOrEqual(Mask->getOperand(i), i))
2599 for (unsigned i = NumElems/2; i != NumElems; ++i)
2600 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2605 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2607 static bool isSplatVector(SDNode *N) {
2608 if (N->getOpcode() != ISD::BUILD_VECTOR)
2611 SDOperand SplatValue = N->getOperand(0);
2612 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2613 if (N->getOperand(i) != SplatValue)
2618 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2620 static bool isUndefShuffle(SDNode *N) {
2621 if (N->getOpcode() != ISD::BUILD_VECTOR)
2624 SDOperand V1 = N->getOperand(0);
2625 SDOperand V2 = N->getOperand(1);
2626 SDOperand Mask = N->getOperand(2);
2627 unsigned NumElems = Mask.getNumOperands();
2628 for (unsigned i = 0; i != NumElems; ++i) {
2629 SDOperand Arg = Mask.getOperand(i);
2630 if (Arg.getOpcode() != ISD::UNDEF) {
2631 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2632 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2634 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2641 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2642 /// that point to V2 points to its first element.
2643 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2644 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2646 bool Changed = false;
2647 SmallVector<SDOperand, 8> MaskVec;
2648 unsigned NumElems = Mask.getNumOperands();
2649 for (unsigned i = 0; i != NumElems; ++i) {
2650 SDOperand Arg = Mask.getOperand(i);
2651 if (Arg.getOpcode() != ISD::UNDEF) {
2652 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2653 if (Val > NumElems) {
2654 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2658 MaskVec.push_back(Arg);
2662 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2663 &MaskVec[0], MaskVec.size());
2667 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2668 /// operation of specified width.
2669 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2670 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2671 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2673 SmallVector<SDOperand, 8> MaskVec;
2674 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2675 for (unsigned i = 1; i != NumElems; ++i)
2676 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2677 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2680 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2681 /// of specified width.
2682 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2683 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2684 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2685 SmallVector<SDOperand, 8> MaskVec;
2686 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2687 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2688 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2690 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2693 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2694 /// of specified width.
2695 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2696 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2697 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2698 unsigned Half = NumElems/2;
2699 SmallVector<SDOperand, 8> MaskVec;
2700 for (unsigned i = 0; i != Half; ++i) {
2701 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2702 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2704 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2707 /// getZeroVector - Returns a vector of specified type with all zero elements.
2709 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2710 assert(MVT::isVector(VT) && "Expected a vector type");
2711 unsigned NumElems = getVectorNumElements(VT);
2712 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2713 bool isFP = MVT::isFloatingPoint(EVT);
2714 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
2715 SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero);
2716 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
2719 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2721 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2722 SDOperand V1 = Op.getOperand(0);
2723 SDOperand Mask = Op.getOperand(2);
2724 MVT::ValueType VT = Op.getValueType();
2725 unsigned NumElems = Mask.getNumOperands();
2726 Mask = getUnpacklMask(NumElems, DAG);
2727 while (NumElems != 4) {
2728 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2731 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2733 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2734 Mask = getZeroVector(MaskVT, DAG);
2735 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2736 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2737 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2740 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2742 static inline bool isZeroNode(SDOperand Elt) {
2743 return ((isa<ConstantSDNode>(Elt) &&
2744 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2745 (isa<ConstantFPSDNode>(Elt) &&
2746 cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
2749 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2750 /// vector and zero or undef vector.
2751 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2752 unsigned NumElems, unsigned Idx,
2753 bool isZero, SelectionDAG &DAG) {
2754 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2755 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2756 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
2757 SDOperand Zero = DAG.getConstant(0, EVT);
2758 SmallVector<SDOperand, 8> MaskVec(NumElems, Zero);
2759 MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
2760 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2761 &MaskVec[0], MaskVec.size());
2762 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2765 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2767 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2768 unsigned NumNonZero, unsigned NumZero,
2769 SelectionDAG &DAG, TargetLowering &TLI) {
2775 for (unsigned i = 0; i < 16; ++i) {
2776 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2777 if (ThisIsNonZero && First) {
2779 V = getZeroVector(MVT::v8i16, DAG);
2781 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2786 SDOperand ThisElt(0, 0), LastElt(0, 0);
2787 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2788 if (LastIsNonZero) {
2789 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2791 if (ThisIsNonZero) {
2792 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2793 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2794 ThisElt, DAG.getConstant(8, MVT::i8));
2796 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2801 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2802 DAG.getConstant(i/2, TLI.getPointerTy()));
2806 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2809 /// LowerBuildVectorv16i8 - Custom lower build_vector of v8i16.
2811 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2812 unsigned NumNonZero, unsigned NumZero,
2813 SelectionDAG &DAG, TargetLowering &TLI) {
2819 for (unsigned i = 0; i < 8; ++i) {
2820 bool isNonZero = (NonZeros & (1 << i)) != 0;
2824 V = getZeroVector(MVT::v8i16, DAG);
2826 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2829 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2830 DAG.getConstant(i, TLI.getPointerTy()));
2838 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2839 // All zero's are handled with pxor.
2840 if (ISD::isBuildVectorAllZeros(Op.Val))
2843 // All one's are handled with pcmpeqd.
2844 if (ISD::isBuildVectorAllOnes(Op.Val))
2847 MVT::ValueType VT = Op.getValueType();
2848 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2849 unsigned EVTBits = MVT::getSizeInBits(EVT);
2851 unsigned NumElems = Op.getNumOperands();
2852 unsigned NumZero = 0;
2853 unsigned NumNonZero = 0;
2854 unsigned NonZeros = 0;
2855 std::set<SDOperand> Values;
2856 for (unsigned i = 0; i < NumElems; ++i) {
2857 SDOperand Elt = Op.getOperand(i);
2858 if (Elt.getOpcode() != ISD::UNDEF) {
2860 if (isZeroNode(Elt))
2863 NonZeros |= (1 << i);
2869 if (NumNonZero == 0)
2870 // Must be a mix of zero and undef. Return a zero vector.
2871 return getZeroVector(VT, DAG);
2873 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2874 if (Values.size() == 1)
2877 // Special case for single non-zero element.
2878 if (NumNonZero == 1) {
2879 unsigned Idx = CountTrailingZeros_32(NonZeros);
2880 SDOperand Item = Op.getOperand(Idx);
2881 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2883 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2884 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2887 if (EVTBits == 32) {
2888 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2889 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2891 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2892 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
2893 SmallVector<SDOperand, 8> MaskVec;
2894 for (unsigned i = 0; i < NumElems; i++)
2895 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2896 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2897 &MaskVec[0], MaskVec.size());
2898 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2899 DAG.getNode(ISD::UNDEF, VT), Mask);
2903 // Let legalizer expand 2-wide build_vector's.
2907 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2909 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2911 if (V.Val) return V;
2914 if (EVTBits == 16) {
2915 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2917 if (V.Val) return V;
2920 // If element VT is == 32 bits, turn it into a number of shuffles.
2921 SmallVector<SDOperand, 8> V;
2923 if (NumElems == 4 && NumZero > 0) {
2924 for (unsigned i = 0; i < 4; ++i) {
2925 bool isZero = !(NonZeros & (1 << i));
2927 V[i] = getZeroVector(VT, DAG);
2929 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2932 for (unsigned i = 0; i < 2; ++i) {
2933 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2936 V[i] = V[i*2]; // Must be a zero vector.
2939 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2940 getMOVLMask(NumElems, DAG));
2943 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2944 getMOVLMask(NumElems, DAG));
2947 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2948 getUnpacklMask(NumElems, DAG));
2953 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
2954 // clears the upper bits.
2955 // FIXME: we can do the same for v4f32 case when we know both parts of
2956 // the lower half come from scalar_to_vector (loadf32). We should do
2957 // that in post legalizer dag combiner with target specific hooks.
2958 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2960 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2961 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
2962 SmallVector<SDOperand, 8> MaskVec;
2963 bool Reverse = (NonZeros & 0x3) == 2;
2964 for (unsigned i = 0; i < 2; ++i)
2966 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2968 MaskVec.push_back(DAG.getConstant(i, EVT));
2969 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2970 for (unsigned i = 0; i < 2; ++i)
2972 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2974 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2975 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2976 &MaskVec[0], MaskVec.size());
2977 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2980 if (Values.size() > 2) {
2981 // Expand into a number of unpckl*.
2983 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2984 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2985 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2986 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2987 for (unsigned i = 0; i < NumElems; ++i)
2988 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2990 while (NumElems != 0) {
2991 for (unsigned i = 0; i < NumElems; ++i)
2992 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3003 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
3004 SDOperand V1 = Op.getOperand(0);
3005 SDOperand V2 = Op.getOperand(1);
3006 SDOperand PermMask = Op.getOperand(2);
3007 MVT::ValueType VT = Op.getValueType();
3008 unsigned NumElems = PermMask.getNumOperands();
3009 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3010 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3011 bool V1IsSplat = false;
3012 bool V2IsSplat = false;
3014 if (isUndefShuffle(Op.Val))
3015 return DAG.getNode(ISD::UNDEF, VT);
3017 if (isSplatMask(PermMask.Val)) {
3018 if (NumElems <= 4) return Op;
3019 // Promote it to a v4i32 splat.
3020 return PromoteSplat(Op, DAG);
3023 if (X86::isMOVLMask(PermMask.Val))
3024 return (V1IsUndef) ? V2 : Op;
3026 if (X86::isMOVSHDUPMask(PermMask.Val) ||
3027 X86::isMOVSLDUPMask(PermMask.Val) ||
3028 X86::isMOVHLPSMask(PermMask.Val) ||
3029 X86::isMOVHPMask(PermMask.Val) ||
3030 X86::isMOVLPMask(PermMask.Val))
3033 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3034 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
3035 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3037 bool Commuted = false;
3038 V1IsSplat = isSplatVector(V1.Val);
3039 V2IsSplat = isSplatVector(V2.Val);
3040 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3041 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3042 std::swap(V1IsSplat, V2IsSplat);
3043 std::swap(V1IsUndef, V2IsUndef);
3047 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3048 if (V2IsUndef) return V1;
3049 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3051 // V2 is a splat, so the mask may be malformed. That is, it may point
3052 // to any V2 element. The instruction selectior won't like this. Get
3053 // a corrected mask and commute to form a proper MOVS{S|D}.
3054 SDOperand NewMask = getMOVLMask(NumElems, DAG);
3055 if (NewMask.Val != PermMask.Val)
3056 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3061 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3062 X86::isUNPCKLMask(PermMask.Val) ||
3063 X86::isUNPCKHMask(PermMask.Val))
3067 // Normalize mask so all entries that point to V2 points to its first
3068 // element then try to match unpck{h|l} again. If match, return a
3069 // new vector_shuffle with the corrected mask.
3070 SDOperand NewMask = NormalizeMask(PermMask, DAG);
3071 if (NewMask.Val != PermMask.Val) {
3072 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3073 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
3074 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3075 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3076 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
3077 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3082 // Normalize the node to match x86 shuffle ops if needed
3083 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3084 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3087 // Commute is back and try unpck* again.
3088 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3089 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3090 X86::isUNPCKLMask(PermMask.Val) ||
3091 X86::isUNPCKHMask(PermMask.Val))
3095 // If VT is integer, try PSHUF* first, then SHUFP*.
3096 if (MVT::isInteger(VT)) {
3097 if (X86::isPSHUFDMask(PermMask.Val) ||
3098 X86::isPSHUFHWMask(PermMask.Val) ||
3099 X86::isPSHUFLWMask(PermMask.Val)) {
3100 if (V2.getOpcode() != ISD::UNDEF)
3101 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3102 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3106 if (X86::isSHUFPMask(PermMask.Val))
3109 // Handle v8i16 shuffle high / low shuffle node pair.
3110 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
3111 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3112 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
3113 SmallVector<SDOperand, 8> MaskVec;
3114 for (unsigned i = 0; i != 4; ++i)
3115 MaskVec.push_back(PermMask.getOperand(i));
3116 for (unsigned i = 4; i != 8; ++i)
3117 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3118 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3119 &MaskVec[0], MaskVec.size());
3120 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3122 for (unsigned i = 0; i != 4; ++i)
3123 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3124 for (unsigned i = 4; i != 8; ++i)
3125 MaskVec.push_back(PermMask.getOperand(i));
3126 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size());
3127 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3130 // Floating point cases in the other order.
3131 if (X86::isSHUFPMask(PermMask.Val))
3133 if (X86::isPSHUFDMask(PermMask.Val) ||
3134 X86::isPSHUFHWMask(PermMask.Val) ||
3135 X86::isPSHUFLWMask(PermMask.Val)) {
3136 if (V2.getOpcode() != ISD::UNDEF)
3137 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3138 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3143 if (NumElems == 4) {
3144 MVT::ValueType MaskVT = PermMask.getValueType();
3145 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
3146 SmallVector<std::pair<int, int>, 8> Locs;
3147 Locs.reserve(NumElems);
3148 SmallVector<SDOperand, 8> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3149 SmallVector<SDOperand, 8> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3152 // If no more than two elements come from either vector. This can be
3153 // implemented with two shuffles. First shuffle gather the elements.
3154 // The second shuffle, which takes the first shuffle as both of its
3155 // vector operands, put the elements into the right order.
3156 for (unsigned i = 0; i != NumElems; ++i) {
3157 SDOperand Elt = PermMask.getOperand(i);
3158 if (Elt.getOpcode() == ISD::UNDEF) {
3159 Locs[i] = std::make_pair(-1, -1);
3161 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3162 if (Val < NumElems) {
3163 Locs[i] = std::make_pair(0, NumLo);
3167 Locs[i] = std::make_pair(1, NumHi);
3168 if (2+NumHi < NumElems)
3169 Mask1[2+NumHi] = Elt;
3174 if (NumLo <= 2 && NumHi <= 2) {
3175 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3176 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3177 &Mask1[0], Mask1.size()));
3178 for (unsigned i = 0; i != NumElems; ++i) {
3179 if (Locs[i].first == -1)
3182 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3183 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3184 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3188 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3189 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3190 &Mask2[0], Mask2.size()));
3193 // Break it into (shuffle shuffle_hi, shuffle_lo).
3195 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3196 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3197 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
3198 unsigned MaskIdx = 0;
3200 unsigned HiIdx = NumElems/2;
3201 for (unsigned i = 0; i != NumElems; ++i) {
3202 if (i == NumElems/2) {
3208 SDOperand Elt = PermMask.getOperand(i);
3209 if (Elt.getOpcode() == ISD::UNDEF) {
3210 Locs[i] = std::make_pair(-1, -1);
3211 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3212 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3213 (*MaskPtr)[LoIdx] = Elt;
3216 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3217 (*MaskPtr)[HiIdx] = Elt;
3222 SDOperand LoShuffle =
3223 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3224 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3225 &LoMask[0], LoMask.size()));
3226 SDOperand HiShuffle =
3227 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3228 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3229 &HiMask[0], HiMask.size()));
3230 SmallVector<SDOperand, 8> MaskOps;
3231 for (unsigned i = 0; i != NumElems; ++i) {
3232 if (Locs[i].first == -1) {
3233 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3235 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3236 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3239 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3240 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3241 &MaskOps[0], MaskOps.size()));
3248 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3249 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3252 MVT::ValueType VT = Op.getValueType();
3253 // TODO: handle v16i8.
3254 if (MVT::getSizeInBits(VT) == 16) {
3255 // Transform it so it match pextrw which produces a 32-bit result.
3256 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
3257 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
3258 Op.getOperand(0), Op.getOperand(1));
3259 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
3260 DAG.getValueType(VT));
3261 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3262 } else if (MVT::getSizeInBits(VT) == 32) {
3263 SDOperand Vec = Op.getOperand(0);
3264 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3267 // SHUFPS the element to the lowest double word, then movss.
3268 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3269 SmallVector<SDOperand, 8> IdxVec;
3270 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT)));
3271 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3272 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3273 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3274 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3275 &IdxVec[0], IdxVec.size());
3276 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3277 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3278 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3279 DAG.getConstant(0, getPointerTy()));
3280 } else if (MVT::getSizeInBits(VT) == 64) {
3281 SDOperand Vec = Op.getOperand(0);
3282 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3286 // UNPCKHPD the element to the lowest double word, then movsd.
3287 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3288 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3289 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3290 SmallVector<SDOperand, 8> IdxVec;
3291 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT)));
3292 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
3293 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3294 &IdxVec[0], IdxVec.size());
3295 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3296 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3297 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3298 DAG.getConstant(0, getPointerTy()));
3305 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3306 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
3307 // as its second argument.
3308 MVT::ValueType VT = Op.getValueType();
3309 MVT::ValueType BaseVT = MVT::getVectorBaseType(VT);
3310 SDOperand N0 = Op.getOperand(0);
3311 SDOperand N1 = Op.getOperand(1);
3312 SDOperand N2 = Op.getOperand(2);
3313 if (MVT::getSizeInBits(BaseVT) == 16) {
3314 if (N1.getValueType() != MVT::i32)
3315 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3316 if (N2.getValueType() != MVT::i32)
3317 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
3318 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
3319 } else if (MVT::getSizeInBits(BaseVT) == 32) {
3320 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
3323 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
3324 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3325 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
3326 SmallVector<SDOperand, 8> MaskVec;
3327 MaskVec.push_back(DAG.getConstant(4, BaseVT));
3328 for (unsigned i = 1; i <= 3; ++i)
3329 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3330 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
3331 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3332 &MaskVec[0], MaskVec.size()));
3334 // Use two pinsrw instructions to insert a 32 bit value.
3336 if (MVT::isFloatingPoint(N1.getValueType())) {
3337 if (ISD::isNON_EXTLoad(N1.Val)) {
3338 // Just load directly from f32mem to GR32.
3339 LoadSDNode *LD = cast<LoadSDNode>(N1);
3340 N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(),
3341 LD->getSrcValue(), LD->getSrcValueOffset());
3343 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
3344 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
3345 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
3346 DAG.getConstant(0, getPointerTy()));
3349 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
3350 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3351 DAG.getConstant(Idx, getPointerTy()));
3352 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
3353 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3354 DAG.getConstant(Idx+1, getPointerTy()));
3355 return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3363 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3364 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3365 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
3368 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3369 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3370 // one of the above mentioned nodes. It has to be wrapped because otherwise
3371 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3372 // be used to form addressing mode. These wrapped nodes will be selected
3375 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3376 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3377 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
3379 CP->getAlignment());
3380 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3381 // With PIC, the address is actually $g + Offset.
3382 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3383 !Subtarget->isPICStyleRIPRel()) {
3384 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3385 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3393 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3394 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3395 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
3396 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3397 // With PIC, the address is actually $g + Offset.
3398 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3399 !Subtarget->isPICStyleRIPRel()) {
3400 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3401 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3405 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
3406 // load the value at address GV, not the value of GV itself. This means that
3407 // the GlobalAddress must be in the base or index register of the address, not
3408 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
3409 // The same applies for external symbols during PIC codegen
3410 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
3411 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
3417 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3418 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3419 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
3420 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3421 // With PIC, the address is actually $g + Offset.
3422 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3423 !Subtarget->isPICStyleRIPRel()) {
3424 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3425 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3432 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3433 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3434 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
3435 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3436 // With PIC, the address is actually $g + Offset.
3437 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3438 !Subtarget->isPICStyleRIPRel()) {
3439 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3440 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3447 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3448 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3449 "Not an i64 shift!");
3450 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3451 SDOperand ShOpLo = Op.getOperand(0);
3452 SDOperand ShOpHi = Op.getOperand(1);
3453 SDOperand ShAmt = Op.getOperand(2);
3454 SDOperand Tmp1 = isSRA ?
3455 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3456 DAG.getConstant(0, MVT::i32);
3458 SDOperand Tmp2, Tmp3;
3459 if (Op.getOpcode() == ISD::SHL_PARTS) {
3460 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3461 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3463 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3464 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3467 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3468 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3469 DAG.getConstant(32, MVT::i8));
3470 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
3471 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
3474 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3476 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3477 SmallVector<SDOperand, 4> Ops;
3478 if (Op.getOpcode() == ISD::SHL_PARTS) {
3479 Ops.push_back(Tmp2);
3480 Ops.push_back(Tmp3);
3482 Ops.push_back(InFlag);
3483 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3484 InFlag = Hi.getValue(1);
3487 Ops.push_back(Tmp3);
3488 Ops.push_back(Tmp1);
3490 Ops.push_back(InFlag);
3491 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3493 Ops.push_back(Tmp2);
3494 Ops.push_back(Tmp3);
3496 Ops.push_back(InFlag);
3497 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3498 InFlag = Lo.getValue(1);
3501 Ops.push_back(Tmp3);
3502 Ops.push_back(Tmp1);
3504 Ops.push_back(InFlag);
3505 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3508 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3512 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3515 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3516 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3517 Op.getOperand(0).getValueType() >= MVT::i16 &&
3518 "Unknown SINT_TO_FP to lower!");
3521 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3522 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3523 MachineFunction &MF = DAG.getMachineFunction();
3524 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3525 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3526 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3527 StackSlot, NULL, 0);
3532 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3534 Tys = DAG.getVTList(MVT::f64, MVT::Other);
3535 SmallVector<SDOperand, 8> Ops;
3536 Ops.push_back(Chain);
3537 Ops.push_back(StackSlot);
3538 Ops.push_back(DAG.getValueType(SrcVT));
3539 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3540 Tys, &Ops[0], Ops.size());
3543 Chain = Result.getValue(1);
3544 SDOperand InFlag = Result.getValue(2);
3546 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3547 // shouldn't be necessary except that RFP cannot be live across
3548 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3549 MachineFunction &MF = DAG.getMachineFunction();
3550 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3551 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3552 Tys = DAG.getVTList(MVT::Other);
3553 SmallVector<SDOperand, 8> Ops;
3554 Ops.push_back(Chain);
3555 Ops.push_back(Result);
3556 Ops.push_back(StackSlot);
3557 Ops.push_back(DAG.getValueType(Op.getValueType()));
3558 Ops.push_back(InFlag);
3559 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3560 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3566 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3567 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3568 "Unknown FP_TO_SINT to lower!");
3569 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3571 MachineFunction &MF = DAG.getMachineFunction();
3572 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3573 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3574 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3577 switch (Op.getValueType()) {
3578 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3579 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3580 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3581 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3584 SDOperand Chain = DAG.getEntryNode();
3585 SDOperand Value = Op.getOperand(0);
3587 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3588 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3589 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
3591 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3593 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
3594 Chain = Value.getValue(1);
3595 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3596 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3599 // Build the FP_TO_INT*_IN_MEM
3600 SDOperand Ops[] = { Chain, Value, StackSlot };
3601 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
3604 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3607 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3608 MVT::ValueType VT = Op.getValueType();
3609 const Type *OpNTy = MVT::getTypeForValueType(VT);
3610 std::vector<Constant*> CV;
3611 if (VT == MVT::f64) {
3612 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
3613 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3615 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
3616 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3617 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3618 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3620 Constant *CS = ConstantStruct::get(CV);
3621 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3622 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3623 SmallVector<SDOperand, 3> Ops;
3624 Ops.push_back(DAG.getEntryNode());
3625 Ops.push_back(CPIdx);
3626 Ops.push_back(DAG.getSrcValue(NULL));
3627 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3628 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
3631 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
3632 MVT::ValueType VT = Op.getValueType();
3633 const Type *OpNTy = MVT::getTypeForValueType(VT);
3634 std::vector<Constant*> CV;
3635 if (VT == MVT::f64) {
3636 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
3637 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3639 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
3640 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3641 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3642 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3644 Constant *CS = ConstantStruct::get(CV);
3645 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3646 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3647 SmallVector<SDOperand, 3> Ops;
3648 Ops.push_back(DAG.getEntryNode());
3649 Ops.push_back(CPIdx);
3650 Ops.push_back(DAG.getSrcValue(NULL));
3651 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3652 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
3655 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
3656 SDOperand Op0 = Op.getOperand(0);
3657 SDOperand Op1 = Op.getOperand(1);
3658 MVT::ValueType VT = Op.getValueType();
3659 MVT::ValueType SrcVT = Op1.getValueType();
3660 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
3662 // If second operand is smaller, extend it first.
3663 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
3664 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
3668 // First get the sign bit of second operand.
3669 std::vector<Constant*> CV;
3670 if (SrcVT == MVT::f64) {
3671 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(1ULL << 63)));
3672 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3674 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(1U << 31)));
3675 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3676 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3677 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3679 Constant *CS = ConstantStruct::get(CV);
3680 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3681 SDVTList Tys = DAG.getVTList(SrcVT, MVT::Other);
3682 SmallVector<SDOperand, 3> Ops;
3683 Ops.push_back(DAG.getEntryNode());
3684 Ops.push_back(CPIdx);
3685 Ops.push_back(DAG.getSrcValue(NULL));
3686 SDOperand Mask1 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3687 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
3689 // Shift sign bit right or left if the two operands have different types.
3690 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
3691 // Op0 is MVT::f32, Op1 is MVT::f64.
3692 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
3693 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
3694 DAG.getConstant(32, MVT::i32));
3695 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
3696 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
3697 DAG.getConstant(0, getPointerTy()));
3700 // Clear first operand sign bit.
3702 if (VT == MVT::f64) {
3703 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(~(1ULL << 63))));
3704 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3706 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(~(1U << 31))));
3707 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3708 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3709 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3711 CS = ConstantStruct::get(CV);
3712 CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3713 Tys = DAG.getVTList(VT, MVT::Other);
3715 Ops.push_back(DAG.getEntryNode());
3716 Ops.push_back(CPIdx);
3717 Ops.push_back(DAG.getSrcValue(NULL));
3718 SDOperand Mask2 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3719 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
3721 // Or the value with the sign bit.
3722 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
3725 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
3727 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
3729 SDOperand Op0 = Op.getOperand(0);
3730 SDOperand Op1 = Op.getOperand(1);
3731 SDOperand CC = Op.getOperand(2);
3732 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3733 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3734 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
3735 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
3738 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
3740 SDOperand Ops1[] = { Chain, Op0, Op1 };
3741 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
3742 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
3743 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3746 assert(isFP && "Illegal integer SetCC!");
3748 SDOperand COps[] = { Chain, Op0, Op1 };
3749 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
3751 switch (SetCCOpcode) {
3752 default: assert(false && "Illegal floating point SetCC!");
3753 case ISD::SETOEQ: { // !PF & ZF
3754 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
3755 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3756 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
3758 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3759 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
3761 case ISD::SETUNE: { // PF | !ZF
3762 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
3763 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3764 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
3766 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3767 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
3772 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
3773 bool addTest = true;
3774 SDOperand Chain = DAG.getEntryNode();
3775 SDOperand Cond = Op.getOperand(0);
3777 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3779 if (Cond.getOpcode() == ISD::SETCC)
3780 Cond = LowerSETCC(Cond, DAG, Chain);
3782 if (Cond.getOpcode() == X86ISD::SETCC) {
3783 CC = Cond.getOperand(0);
3785 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3786 // (since flag operand cannot be shared). Use it as the condition setting
3787 // operand in place of the X86ISD::SETCC.
3788 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3789 // to use a test instead of duplicating the X86ISD::CMP (for register
3790 // pressure reason)?
3791 SDOperand Cmp = Cond.getOperand(1);
3792 unsigned Opc = Cmp.getOpcode();
3793 bool IllegalFPCMov = !X86ScalarSSE &&
3794 MVT::isFloatingPoint(Op.getValueType()) &&
3795 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
3796 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
3798 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3799 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3805 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3806 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3807 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3810 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
3811 SmallVector<SDOperand, 4> Ops;
3812 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
3813 // condition is true.
3814 Ops.push_back(Op.getOperand(2));
3815 Ops.push_back(Op.getOperand(1));
3817 Ops.push_back(Cond.getValue(1));
3818 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3821 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
3822 bool addTest = true;
3823 SDOperand Chain = Op.getOperand(0);
3824 SDOperand Cond = Op.getOperand(1);
3825 SDOperand Dest = Op.getOperand(2);
3827 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3829 if (Cond.getOpcode() == ISD::SETCC)
3830 Cond = LowerSETCC(Cond, DAG, Chain);
3832 if (Cond.getOpcode() == X86ISD::SETCC) {
3833 CC = Cond.getOperand(0);
3835 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3836 // (since flag operand cannot be shared). Use it as the condition setting
3837 // operand in place of the X86ISD::SETCC.
3838 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3839 // to use a test instead of duplicating the X86ISD::CMP (for register
3840 // pressure reason)?
3841 SDOperand Cmp = Cond.getOperand(1);
3842 unsigned Opc = Cmp.getOpcode();
3843 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
3844 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3845 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3851 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3852 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3853 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3855 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
3856 Cond, Op.getOperand(2), CC, Cond.getValue(1));
3859 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
3860 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3862 if (Subtarget->is64Bit())
3863 return LowerX86_64CCCCallTo(Op, DAG, CallingConv);
3865 switch (CallingConv) {
3867 assert(0 && "Unsupported calling convention");
3868 case CallingConv::Fast:
3870 return LowerFastCCCallTo(Op, DAG, CallingConv);
3872 case CallingConv::C:
3873 case CallingConv::X86_StdCall:
3874 return LowerCCCCallTo(Op, DAG, CallingConv);
3875 case CallingConv::X86_FastCall:
3876 return LowerFastCCCallTo(Op, DAG, CallingConv);
3881 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
3882 MachineFunction &MF = DAG.getMachineFunction();
3883 const Function* Fn = MF.getFunction();
3884 if (Fn->hasExternalLinkage() &&
3885 Subtarget->isTargetCygMing() &&
3886 Fn->getName() == "main")
3887 MF.getInfo<X86FunctionInfo>()->setForceFramePointer(true);
3889 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3890 if (Subtarget->is64Bit())
3891 return LowerX86_64CCCArguments(Op, DAG);
3895 assert(0 && "Unsupported calling convention");
3896 case CallingConv::Fast:
3898 return LowerFastCCArguments(Op, DAG);
3901 case CallingConv::C:
3902 return LowerCCCArguments(Op, DAG);
3903 case CallingConv::X86_StdCall:
3904 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(StdCall);
3905 return LowerCCCArguments(Op, DAG, true);
3906 case CallingConv::X86_FastCall:
3907 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(FastCall);
3908 return LowerFastCCArguments(Op, DAG, true);
3912 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
3913 SDOperand InFlag(0, 0);
3914 SDOperand Chain = Op.getOperand(0);
3916 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3917 if (Align == 0) Align = 1;
3919 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3920 // If not DWORD aligned, call memset if size is less than the threshold.
3921 // It knows how to align to the right boundary first.
3922 if ((Align & 3) != 0 ||
3923 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3924 MVT::ValueType IntPtr = getPointerTy();
3925 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3926 TargetLowering::ArgListTy Args;
3927 TargetLowering::ArgListEntry Entry;
3928 Entry.Node = Op.getOperand(1);
3929 Entry.Ty = IntPtrTy;
3930 Entry.isSigned = false;
3931 Entry.isInReg = false;
3932 Entry.isSRet = false;
3933 Args.push_back(Entry);
3934 // Extend the unsigned i8 argument to be an int value for the call.
3935 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
3936 Entry.Ty = IntPtrTy;
3937 Entry.isSigned = false;
3938 Entry.isInReg = false;
3939 Entry.isSRet = false;
3940 Args.push_back(Entry);
3941 Entry.Node = Op.getOperand(3);
3942 Args.push_back(Entry);
3943 std::pair<SDOperand,SDOperand> CallResult =
3944 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3945 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
3946 return CallResult.second;
3951 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3952 unsigned BytesLeft = 0;
3953 bool TwoRepStos = false;
3956 uint64_t Val = ValC->getValue() & 255;
3958 // If the value is a constant, then we can potentially use larger sets.
3959 switch (Align & 3) {
3960 case 2: // WORD aligned
3963 Val = (Val << 8) | Val;
3965 case 0: // DWORD aligned
3968 Val = (Val << 8) | Val;
3969 Val = (Val << 16) | Val;
3970 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
3973 Val = (Val << 32) | Val;
3976 default: // Byte aligned
3979 Count = Op.getOperand(3);
3983 if (AVT > MVT::i8) {
3985 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3986 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3987 BytesLeft = I->getValue() % UBytes;
3989 assert(AVT >= MVT::i32 &&
3990 "Do not use rep;stos if not at least DWORD aligned");
3991 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3992 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3997 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
3999 InFlag = Chain.getValue(1);
4002 Count = Op.getOperand(3);
4003 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
4004 InFlag = Chain.getValue(1);
4007 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4009 InFlag = Chain.getValue(1);
4010 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4011 Op.getOperand(1), InFlag);
4012 InFlag = Chain.getValue(1);
4014 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4015 SmallVector<SDOperand, 8> Ops;
4016 Ops.push_back(Chain);
4017 Ops.push_back(DAG.getValueType(AVT));
4018 Ops.push_back(InFlag);
4019 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4022 InFlag = Chain.getValue(1);
4023 Count = Op.getOperand(3);
4024 MVT::ValueType CVT = Count.getValueType();
4025 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4026 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4027 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4029 InFlag = Chain.getValue(1);
4030 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4032 Ops.push_back(Chain);
4033 Ops.push_back(DAG.getValueType(MVT::i8));
4034 Ops.push_back(InFlag);
4035 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4036 } else if (BytesLeft) {
4037 // Issue stores for the last 1 - 7 bytes.
4039 unsigned Val = ValC->getValue() & 255;
4040 unsigned Offset = I->getValue() - BytesLeft;
4041 SDOperand DstAddr = Op.getOperand(1);
4042 MVT::ValueType AddrVT = DstAddr.getValueType();
4043 if (BytesLeft >= 4) {
4044 Val = (Val << 8) | Val;
4045 Val = (Val << 16) | Val;
4046 Value = DAG.getConstant(Val, MVT::i32);
4047 Chain = DAG.getStore(Chain, Value,
4048 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4049 DAG.getConstant(Offset, AddrVT)),
4054 if (BytesLeft >= 2) {
4055 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
4056 Chain = DAG.getStore(Chain, Value,
4057 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4058 DAG.getConstant(Offset, AddrVT)),
4063 if (BytesLeft == 1) {
4064 Value = DAG.getConstant(Val, MVT::i8);
4065 Chain = DAG.getStore(Chain, Value,
4066 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4067 DAG.getConstant(Offset, AddrVT)),
4075 SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
4076 SDOperand Chain = Op.getOperand(0);
4078 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4079 if (Align == 0) Align = 1;
4081 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
4082 // If not DWORD aligned, call memcpy if size is less than the threshold.
4083 // It knows how to align to the right boundary first.
4084 if ((Align & 3) != 0 ||
4085 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
4086 MVT::ValueType IntPtr = getPointerTy();
4087 TargetLowering::ArgListTy Args;
4088 TargetLowering::ArgListEntry Entry;
4089 Entry.Ty = getTargetData()->getIntPtrType();
4090 Entry.isSigned = false;
4091 Entry.isInReg = false;
4092 Entry.isSRet = false;
4093 Entry.Node = Op.getOperand(1); Args.push_back(Entry);
4094 Entry.Node = Op.getOperand(2); Args.push_back(Entry);
4095 Entry.Node = Op.getOperand(3); Args.push_back(Entry);
4096 std::pair<SDOperand,SDOperand> CallResult =
4097 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
4098 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
4099 return CallResult.second;
4104 unsigned BytesLeft = 0;
4105 bool TwoRepMovs = false;
4106 switch (Align & 3) {
4107 case 2: // WORD aligned
4110 case 0: // DWORD aligned
4112 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
4115 default: // Byte aligned
4117 Count = Op.getOperand(3);
4121 if (AVT > MVT::i8) {
4123 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4124 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
4125 BytesLeft = I->getValue() % UBytes;
4127 assert(AVT >= MVT::i32 &&
4128 "Do not use rep;movs if not at least DWORD aligned");
4129 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4130 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4135 SDOperand InFlag(0, 0);
4136 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4138 InFlag = Chain.getValue(1);
4139 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4140 Op.getOperand(1), InFlag);
4141 InFlag = Chain.getValue(1);
4142 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
4143 Op.getOperand(2), InFlag);
4144 InFlag = Chain.getValue(1);
4146 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4147 SmallVector<SDOperand, 8> Ops;
4148 Ops.push_back(Chain);
4149 Ops.push_back(DAG.getValueType(AVT));
4150 Ops.push_back(InFlag);
4151 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4154 InFlag = Chain.getValue(1);
4155 Count = Op.getOperand(3);
4156 MVT::ValueType CVT = Count.getValueType();
4157 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4158 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4159 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4161 InFlag = Chain.getValue(1);
4162 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4164 Ops.push_back(Chain);
4165 Ops.push_back(DAG.getValueType(MVT::i8));
4166 Ops.push_back(InFlag);
4167 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4168 } else if (BytesLeft) {
4169 // Issue loads and stores for the last 1 - 7 bytes.
4170 unsigned Offset = I->getValue() - BytesLeft;
4171 SDOperand DstAddr = Op.getOperand(1);
4172 MVT::ValueType DstVT = DstAddr.getValueType();
4173 SDOperand SrcAddr = Op.getOperand(2);
4174 MVT::ValueType SrcVT = SrcAddr.getValueType();
4176 if (BytesLeft >= 4) {
4177 Value = DAG.getLoad(MVT::i32, Chain,
4178 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4179 DAG.getConstant(Offset, SrcVT)),
4181 Chain = Value.getValue(1);
4182 Chain = DAG.getStore(Chain, Value,
4183 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4184 DAG.getConstant(Offset, DstVT)),
4189 if (BytesLeft >= 2) {
4190 Value = DAG.getLoad(MVT::i16, Chain,
4191 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4192 DAG.getConstant(Offset, SrcVT)),
4194 Chain = Value.getValue(1);
4195 Chain = DAG.getStore(Chain, Value,
4196 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4197 DAG.getConstant(Offset, DstVT)),
4203 if (BytesLeft == 1) {
4204 Value = DAG.getLoad(MVT::i8, Chain,
4205 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4206 DAG.getConstant(Offset, SrcVT)),
4208 Chain = Value.getValue(1);
4209 Chain = DAG.getStore(Chain, Value,
4210 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4211 DAG.getConstant(Offset, DstVT)),
4220 X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
4221 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4222 SDOperand TheOp = Op.getOperand(0);
4223 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheOp, 1);
4224 if (Subtarget->is64Bit()) {
4225 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
4226 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX,
4227 MVT::i64, Copy1.getValue(2));
4228 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2,
4229 DAG.getConstant(32, MVT::i8));
4231 DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp), Copy2.getValue(1)
4234 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4235 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
4238 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
4239 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX,
4240 MVT::i32, Copy1.getValue(2));
4241 SDOperand Ops[] = { Copy1, Copy2, Copy2.getValue(1) };
4242 Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
4243 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 3);
4246 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
4247 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
4249 if (!Subtarget->is64Bit()) {
4250 // vastart just stores the address of the VarArgsFrameIndex slot into the
4251 // memory location argument.
4252 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4253 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
4258 // gp_offset (0 - 6 * 8)
4259 // fp_offset (48 - 48 + 8 * 16)
4260 // overflow_arg_area (point to parameters coming in memory).
4262 SmallVector<SDOperand, 8> MemOps;
4263 SDOperand FIN = Op.getOperand(1);
4265 SDOperand Store = DAG.getStore(Op.getOperand(0),
4266 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4267 FIN, SV->getValue(), SV->getOffset());
4268 MemOps.push_back(Store);
4271 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4272 DAG.getConstant(4, getPointerTy()));
4273 Store = DAG.getStore(Op.getOperand(0),
4274 DAG.getConstant(VarArgsFPOffset, MVT::i32),
4275 FIN, SV->getValue(), SV->getOffset());
4276 MemOps.push_back(Store);
4278 // Store ptr to overflow_arg_area
4279 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4280 DAG.getConstant(4, getPointerTy()));
4281 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4282 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
4284 MemOps.push_back(Store);
4286 // Store ptr to reg_save_area.
4287 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4288 DAG.getConstant(8, getPointerTy()));
4289 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
4290 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
4292 MemOps.push_back(Store);
4293 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
4297 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4298 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4300 default: return SDOperand(); // Don't custom lower most intrinsics.
4301 // Comparison intrinsics.
4302 case Intrinsic::x86_sse_comieq_ss:
4303 case Intrinsic::x86_sse_comilt_ss:
4304 case Intrinsic::x86_sse_comile_ss:
4305 case Intrinsic::x86_sse_comigt_ss:
4306 case Intrinsic::x86_sse_comige_ss:
4307 case Intrinsic::x86_sse_comineq_ss:
4308 case Intrinsic::x86_sse_ucomieq_ss:
4309 case Intrinsic::x86_sse_ucomilt_ss:
4310 case Intrinsic::x86_sse_ucomile_ss:
4311 case Intrinsic::x86_sse_ucomigt_ss:
4312 case Intrinsic::x86_sse_ucomige_ss:
4313 case Intrinsic::x86_sse_ucomineq_ss:
4314 case Intrinsic::x86_sse2_comieq_sd:
4315 case Intrinsic::x86_sse2_comilt_sd:
4316 case Intrinsic::x86_sse2_comile_sd:
4317 case Intrinsic::x86_sse2_comigt_sd:
4318 case Intrinsic::x86_sse2_comige_sd:
4319 case Intrinsic::x86_sse2_comineq_sd:
4320 case Intrinsic::x86_sse2_ucomieq_sd:
4321 case Intrinsic::x86_sse2_ucomilt_sd:
4322 case Intrinsic::x86_sse2_ucomile_sd:
4323 case Intrinsic::x86_sse2_ucomigt_sd:
4324 case Intrinsic::x86_sse2_ucomige_sd:
4325 case Intrinsic::x86_sse2_ucomineq_sd: {
4327 ISD::CondCode CC = ISD::SETCC_INVALID;
4330 case Intrinsic::x86_sse_comieq_ss:
4331 case Intrinsic::x86_sse2_comieq_sd:
4335 case Intrinsic::x86_sse_comilt_ss:
4336 case Intrinsic::x86_sse2_comilt_sd:
4340 case Intrinsic::x86_sse_comile_ss:
4341 case Intrinsic::x86_sse2_comile_sd:
4345 case Intrinsic::x86_sse_comigt_ss:
4346 case Intrinsic::x86_sse2_comigt_sd:
4350 case Intrinsic::x86_sse_comige_ss:
4351 case Intrinsic::x86_sse2_comige_sd:
4355 case Intrinsic::x86_sse_comineq_ss:
4356 case Intrinsic::x86_sse2_comineq_sd:
4360 case Intrinsic::x86_sse_ucomieq_ss:
4361 case Intrinsic::x86_sse2_ucomieq_sd:
4362 Opc = X86ISD::UCOMI;
4365 case Intrinsic::x86_sse_ucomilt_ss:
4366 case Intrinsic::x86_sse2_ucomilt_sd:
4367 Opc = X86ISD::UCOMI;
4370 case Intrinsic::x86_sse_ucomile_ss:
4371 case Intrinsic::x86_sse2_ucomile_sd:
4372 Opc = X86ISD::UCOMI;
4375 case Intrinsic::x86_sse_ucomigt_ss:
4376 case Intrinsic::x86_sse2_ucomigt_sd:
4377 Opc = X86ISD::UCOMI;
4380 case Intrinsic::x86_sse_ucomige_ss:
4381 case Intrinsic::x86_sse2_ucomige_sd:
4382 Opc = X86ISD::UCOMI;
4385 case Intrinsic::x86_sse_ucomineq_ss:
4386 case Intrinsic::x86_sse2_ucomineq_sd:
4387 Opc = X86ISD::UCOMI;
4393 SDOperand LHS = Op.getOperand(1);
4394 SDOperand RHS = Op.getOperand(2);
4395 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4397 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4398 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
4399 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
4400 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
4401 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
4402 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
4403 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4408 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4409 // Depths > 0 not supported yet!
4410 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4413 // Just load the return address
4414 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4415 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4418 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4419 // Depths > 0 not supported yet!
4420 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4423 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4424 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
4425 DAG.getConstant(4, getPointerTy()));
4428 /// LowerOperation - Provide custom lowering hooks for some operations.
4430 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4431 switch (Op.getOpcode()) {
4432 default: assert(0 && "Should not custom lower this!");
4433 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4434 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4435 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4436 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
4437 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4438 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4439 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4440 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
4441 case ISD::SHL_PARTS:
4442 case ISD::SRA_PARTS:
4443 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
4444 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4445 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
4446 case ISD::FABS: return LowerFABS(Op, DAG);
4447 case ISD::FNEG: return LowerFNEG(Op, DAG);
4448 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4449 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode());
4450 case ISD::SELECT: return LowerSELECT(Op, DAG);
4451 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4452 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4453 case ISD::CALL: return LowerCALL(Op, DAG);
4454 case ISD::RET: return LowerRET(Op, DAG);
4455 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
4456 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
4457 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
4458 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
4459 case ISD::VASTART: return LowerVASTART(Op, DAG);
4460 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4461 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4462 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4467 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
4469 default: return NULL;
4470 case X86ISD::SHLD: return "X86ISD::SHLD";
4471 case X86ISD::SHRD: return "X86ISD::SHRD";
4472 case X86ISD::FAND: return "X86ISD::FAND";
4473 case X86ISD::FOR: return "X86ISD::FOR";
4474 case X86ISD::FXOR: return "X86ISD::FXOR";
4475 case X86ISD::FSRL: return "X86ISD::FSRL";
4476 case X86ISD::FILD: return "X86ISD::FILD";
4477 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
4478 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
4479 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
4480 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
4481 case X86ISD::FLD: return "X86ISD::FLD";
4482 case X86ISD::FST: return "X86ISD::FST";
4483 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
4484 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
4485 case X86ISD::CALL: return "X86ISD::CALL";
4486 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
4487 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
4488 case X86ISD::CMP: return "X86ISD::CMP";
4489 case X86ISD::COMI: return "X86ISD::COMI";
4490 case X86ISD::UCOMI: return "X86ISD::UCOMI";
4491 case X86ISD::SETCC: return "X86ISD::SETCC";
4492 case X86ISD::CMOV: return "X86ISD::CMOV";
4493 case X86ISD::BRCOND: return "X86ISD::BRCOND";
4494 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
4495 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
4496 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
4497 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
4498 case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA";
4499 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
4500 case X86ISD::Wrapper: return "X86ISD::Wrapper";
4501 case X86ISD::S2VEC: return "X86ISD::S2VEC";
4502 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
4503 case X86ISD::PINSRW: return "X86ISD::PINSRW";
4504 case X86ISD::FMAX: return "X86ISD::FMAX";
4505 case X86ISD::FMIN: return "X86ISD::FMIN";
4509 /// isLegalAddressImmediate - Return true if the integer value or
4510 /// GlobalValue can be used as the offset of the target addressing mode.
4511 bool X86TargetLowering::isLegalAddressImmediate(int64_t V) const {
4512 // X86 allows a sign-extended 32-bit immediate field.
4513 return (V > -(1LL << 32) && V < (1LL << 32)-1);
4516 bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
4517 // In 64-bit mode, GV is 64-bit so it won't fit in the 32-bit displacement
4518 // field unless we are in small code model.
4519 if (Subtarget->is64Bit() &&
4520 getTargetMachine().getCodeModel() != CodeModel::Small)
4523 return (!Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false));
4526 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4527 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4528 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4529 /// are assumed to be legal.
4531 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
4532 // Only do shuffles on 128-bit vector types for now.
4533 if (MVT::getSizeInBits(VT) == 64) return false;
4534 return (Mask.Val->getNumOperands() <= 4 ||
4535 isSplatMask(Mask.Val) ||
4536 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
4537 X86::isUNPCKLMask(Mask.Val) ||
4538 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
4539 X86::isUNPCKHMask(Mask.Val));
4542 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
4544 SelectionDAG &DAG) const {
4545 unsigned NumElts = BVOps.size();
4546 // Only do shuffles on 128-bit vector types for now.
4547 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
4548 if (NumElts == 2) return true;
4550 return (isMOVLMask(&BVOps[0], 4) ||
4551 isCommutedMOVL(&BVOps[0], 4, true) ||
4552 isSHUFPMask(&BVOps[0], 4) ||
4553 isCommutedSHUFP(&BVOps[0], 4));
4558 //===----------------------------------------------------------------------===//
4559 // X86 Scheduler Hooks
4560 //===----------------------------------------------------------------------===//
4563 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
4564 MachineBasicBlock *BB) {
4565 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4566 switch (MI->getOpcode()) {
4567 default: assert(false && "Unexpected instr type to insert");
4568 case X86::CMOV_FR32:
4569 case X86::CMOV_FR64:
4570 case X86::CMOV_V4F32:
4571 case X86::CMOV_V2F64:
4572 case X86::CMOV_V2I64: {
4573 // To "insert" a SELECT_CC instruction, we actually have to insert the
4574 // diamond control-flow pattern. The incoming instruction knows the
4575 // destination vreg to set, the condition code register to branch on, the
4576 // true/false values to select between, and a branch opcode to use.
4577 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4578 ilist<MachineBasicBlock>::iterator It = BB;
4584 // cmpTY ccX, r1, r2
4586 // fallthrough --> copy0MBB
4587 MachineBasicBlock *thisMBB = BB;
4588 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4589 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4591 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
4592 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
4593 MachineFunction *F = BB->getParent();
4594 F->getBasicBlockList().insert(It, copy0MBB);
4595 F->getBasicBlockList().insert(It, sinkMBB);
4596 // Update machine-CFG edges by first adding all successors of the current
4597 // block to the new block which will contain the Phi node for the select.
4598 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
4599 e = BB->succ_end(); i != e; ++i)
4600 sinkMBB->addSuccessor(*i);
4601 // Next, remove all successors of the current block, and add the true
4602 // and fallthrough blocks as its successors.
4603 while(!BB->succ_empty())
4604 BB->removeSuccessor(BB->succ_begin());
4605 BB->addSuccessor(copy0MBB);
4606 BB->addSuccessor(sinkMBB);
4609 // %FalseValue = ...
4610 // # fallthrough to sinkMBB
4613 // Update machine-CFG edges
4614 BB->addSuccessor(sinkMBB);
4617 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4620 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
4621 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4622 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4624 delete MI; // The pseudo instruction is gone now.
4628 case X86::FP_TO_INT16_IN_MEM:
4629 case X86::FP_TO_INT32_IN_MEM:
4630 case X86::FP_TO_INT64_IN_MEM: {
4631 // Change the floating point control register to use "round towards zero"
4632 // mode when truncating to an integer value.
4633 MachineFunction *F = BB->getParent();
4634 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
4635 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
4637 // Load the old value of the high byte of the control word...
4639 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
4640 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
4642 // Set the high part to be round to zero...
4643 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
4646 // Reload the modified control word now...
4647 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4649 // Restore the memory image of control word to original value
4650 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
4653 // Get the X86 opcode to use.
4655 switch (MI->getOpcode()) {
4656 default: assert(0 && "illegal opcode!");
4657 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
4658 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
4659 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
4663 MachineOperand &Op = MI->getOperand(0);
4664 if (Op.isRegister()) {
4665 AM.BaseType = X86AddressMode::RegBase;
4666 AM.Base.Reg = Op.getReg();
4668 AM.BaseType = X86AddressMode::FrameIndexBase;
4669 AM.Base.FrameIndex = Op.getFrameIndex();
4671 Op = MI->getOperand(1);
4672 if (Op.isImmediate())
4673 AM.Scale = Op.getImm();
4674 Op = MI->getOperand(2);
4675 if (Op.isImmediate())
4676 AM.IndexReg = Op.getImm();
4677 Op = MI->getOperand(3);
4678 if (Op.isGlobalAddress()) {
4679 AM.GV = Op.getGlobal();
4681 AM.Disp = Op.getImm();
4683 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
4684 .addReg(MI->getOperand(4).getReg());
4686 // Reload the original control word now.
4687 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4689 delete MI; // The pseudo instruction is gone now.
4695 //===----------------------------------------------------------------------===//
4696 // X86 Optimization Hooks
4697 //===----------------------------------------------------------------------===//
4699 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
4701 uint64_t &KnownZero,
4703 unsigned Depth) const {
4704 unsigned Opc = Op.getOpcode();
4705 assert((Opc >= ISD::BUILTIN_OP_END ||
4706 Opc == ISD::INTRINSIC_WO_CHAIN ||
4707 Opc == ISD::INTRINSIC_W_CHAIN ||
4708 Opc == ISD::INTRINSIC_VOID) &&
4709 "Should use MaskedValueIsZero if you don't know whether Op"
4710 " is a target node!");
4712 KnownZero = KnownOne = 0; // Don't know anything.
4716 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
4721 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4722 /// element of the result of the vector shuffle.
4723 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
4724 MVT::ValueType VT = N->getValueType(0);
4725 SDOperand PermMask = N->getOperand(2);
4726 unsigned NumElems = PermMask.getNumOperands();
4727 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
4729 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4731 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
4732 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
4733 SDOperand Idx = PermMask.getOperand(i);
4734 if (Idx.getOpcode() == ISD::UNDEF)
4735 return DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
4736 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
4741 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
4742 /// node is a GlobalAddress + an offset.
4743 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
4744 unsigned Opc = N->getOpcode();
4745 if (Opc == X86ISD::Wrapper) {
4746 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
4747 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
4750 } else if (Opc == ISD::ADD) {
4751 SDOperand N1 = N->getOperand(0);
4752 SDOperand N2 = N->getOperand(1);
4753 if (isGAPlusOffset(N1.Val, GA, Offset)) {
4754 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
4756 Offset += V->getSignExtended();
4759 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
4760 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
4762 Offset += V->getSignExtended();
4770 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
4772 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
4773 MachineFrameInfo *MFI) {
4774 if (N->getOperand(0).Val != Base->getOperand(0).Val)
4777 SDOperand Loc = N->getOperand(1);
4778 SDOperand BaseLoc = Base->getOperand(1);
4779 if (Loc.getOpcode() == ISD::FrameIndex) {
4780 if (BaseLoc.getOpcode() != ISD::FrameIndex)
4782 int FI = dyn_cast<FrameIndexSDNode>(Loc)->getIndex();
4783 int BFI = dyn_cast<FrameIndexSDNode>(BaseLoc)->getIndex();
4784 int FS = MFI->getObjectSize(FI);
4785 int BFS = MFI->getObjectSize(BFI);
4786 if (FS != BFS || FS != Size) return false;
4787 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
4789 GlobalValue *GV1 = NULL;
4790 GlobalValue *GV2 = NULL;
4791 int64_t Offset1 = 0;
4792 int64_t Offset2 = 0;
4793 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
4794 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
4795 if (isGA1 && isGA2 && GV1 == GV2)
4796 return Offset1 == (Offset2 + Dist*Size);
4802 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
4803 const X86Subtarget *Subtarget) {
4806 if (isGAPlusOffset(Base, GV, Offset))
4807 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
4809 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
4810 int BFI = dyn_cast<FrameIndexSDNode>(Base)->getIndex();
4812 // Fixed objects do not specify alignment, however the offsets are known.
4813 return ((Subtarget->getStackAlignment() % 16) == 0 &&
4814 (MFI->getObjectOffset(BFI) % 16) == 0);
4816 return MFI->getObjectAlignment(BFI) >= 16;
4822 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
4823 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
4824 /// if the load addresses are consecutive, non-overlapping, and in the right
4826 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
4827 const X86Subtarget *Subtarget) {
4828 MachineFunction &MF = DAG.getMachineFunction();
4829 MachineFrameInfo *MFI = MF.getFrameInfo();
4830 MVT::ValueType VT = N->getValueType(0);
4831 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
4832 SDOperand PermMask = N->getOperand(2);
4833 int NumElems = (int)PermMask.getNumOperands();
4834 SDNode *Base = NULL;
4835 for (int i = 0; i < NumElems; ++i) {
4836 SDOperand Idx = PermMask.getOperand(i);
4837 if (Idx.getOpcode() == ISD::UNDEF) {
4838 if (!Base) return SDOperand();
4841 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
4842 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
4846 else if (!isConsecutiveLoad(Arg.Val, Base,
4847 i, MVT::getSizeInBits(EVT)/8,MFI))
4852 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
4854 LoadSDNode *LD = cast<LoadSDNode>(Base);
4855 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
4856 LD->getSrcValueOffset());
4858 // Just use movups, it's shorter.
4859 SDVTList Tys = DAG.getVTList(MVT::v4f32, MVT::Other);
4860 SmallVector<SDOperand, 3> Ops;
4861 Ops.push_back(Base->getOperand(0));
4862 Ops.push_back(Base->getOperand(1));
4863 Ops.push_back(Base->getOperand(2));
4864 return DAG.getNode(ISD::BIT_CONVERT, VT,
4865 DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size()));
4869 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
4870 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
4871 const X86Subtarget *Subtarget) {
4872 SDOperand Cond = N->getOperand(0);
4874 // If we have SSE[12] support, try to form min/max nodes.
4875 if (Subtarget->hasSSE2() &&
4876 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
4877 if (Cond.getOpcode() == ISD::SETCC) {
4878 // Get the LHS/RHS of the select.
4879 SDOperand LHS = N->getOperand(1);
4880 SDOperand RHS = N->getOperand(2);
4881 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
4883 unsigned Opcode = 0;
4884 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
4887 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
4890 if (!UnsafeFPMath) break;
4892 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
4894 Opcode = X86ISD::FMIN;
4897 case ISD::SETOGT: // (X > Y) ? X : Y -> max
4900 if (!UnsafeFPMath) break;
4902 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
4904 Opcode = X86ISD::FMAX;
4907 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
4910 case ISD::SETOGT: // (X > Y) ? Y : X -> min
4913 if (!UnsafeFPMath) break;
4915 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
4917 Opcode = X86ISD::FMIN;
4920 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
4923 if (!UnsafeFPMath) break;
4925 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
4927 Opcode = X86ISD::FMAX;
4933 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
4942 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
4943 DAGCombinerInfo &DCI) const {
4944 SelectionDAG &DAG = DCI.DAG;
4945 switch (N->getOpcode()) {
4947 case ISD::VECTOR_SHUFFLE:
4948 return PerformShuffleCombine(N, DAG, Subtarget);
4950 return PerformSELECTCombine(N, DAG, Subtarget);
4956 //===----------------------------------------------------------------------===//
4957 // X86 Inline Assembly Support
4958 //===----------------------------------------------------------------------===//
4960 /// getConstraintType - Given a constraint letter, return the type of
4961 /// constraint it is for this target.
4962 X86TargetLowering::ConstraintType
4963 X86TargetLowering::getConstraintType(char ConstraintLetter) const {
4964 switch (ConstraintLetter) {
4973 return C_RegisterClass;
4974 default: return TargetLowering::getConstraintType(ConstraintLetter);
4978 /// isOperandValidForConstraint - Return the specified operand (possibly
4979 /// modified) if the specified SDOperand is valid for the specified target
4980 /// constraint letter, otherwise return null.
4981 SDOperand X86TargetLowering::
4982 isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
4983 switch (Constraint) {
4986 // Literal immediates are always ok.
4987 if (isa<ConstantSDNode>(Op)) return Op;
4989 // If we are in non-pic codegen mode, we allow the address of a global to
4990 // be used with 'i'.
4991 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
4992 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4993 return SDOperand(0, 0);
4995 if (GA->getOpcode() != ISD::TargetGlobalAddress)
4996 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5001 // Otherwise, not valid for this mode.
5002 return SDOperand(0, 0);
5004 return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
5008 std::vector<unsigned> X86TargetLowering::
5009 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5010 MVT::ValueType VT) const {
5011 if (Constraint.size() == 1) {
5012 // FIXME: not handling fp-stack yet!
5013 // FIXME: not handling MMX registers yet ('y' constraint).
5014 switch (Constraint[0]) { // GCC X86 Constraint Letters
5015 default: break; // Unknown constraint letter
5016 case 'A': // EAX/EDX
5017 if (VT == MVT::i32 || VT == MVT::i64)
5018 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
5020 case 'r': // GENERAL_REGS
5021 case 'R': // LEGACY_REGS
5022 if (VT == MVT::i64 && Subtarget->is64Bit())
5023 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
5024 X86::RSI, X86::RDI, X86::RBP, X86::RSP,
5025 X86::R8, X86::R9, X86::R10, X86::R11,
5026 X86::R12, X86::R13, X86::R14, X86::R15, 0);
5028 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
5029 X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
5030 else if (VT == MVT::i16)
5031 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
5032 X86::SI, X86::DI, X86::BP, X86::SP, 0);
5033 else if (VT == MVT::i8)
5034 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
5036 case 'l': // INDEX_REGS
5038 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
5039 X86::ESI, X86::EDI, X86::EBP, 0);
5040 else if (VT == MVT::i16)
5041 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
5042 X86::SI, X86::DI, X86::BP, 0);
5043 else if (VT == MVT::i8)
5044 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
5046 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
5049 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
5050 else if (VT == MVT::i16)
5051 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
5052 else if (VT == MVT::i8)
5053 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
5055 case 'x': // SSE_REGS if SSE1 allowed
5056 if (Subtarget->hasSSE1())
5057 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
5058 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
5060 return std::vector<unsigned>();
5061 case 'Y': // SSE_REGS if SSE2 allowed
5062 if (Subtarget->hasSSE2())
5063 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
5064 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
5066 return std::vector<unsigned>();
5070 return std::vector<unsigned>();
5073 std::pair<unsigned, const TargetRegisterClass*>
5074 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5075 MVT::ValueType VT) const {
5076 // Use the default implementation in TargetLowering to convert the register
5077 // constraint into a member of a register class.
5078 std::pair<unsigned, const TargetRegisterClass*> Res;
5079 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5081 // Not found as a standard register?
5082 if (Res.second == 0) {
5083 // GCC calls "st(0)" just plain "st".
5084 if (StringsEqualNoCase("{st}", Constraint)) {
5085 Res.first = X86::ST0;
5086 Res.second = X86::RSTRegisterClass;
5092 // Otherwise, check to see if this is a register class of the wrong value
5093 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
5094 // turn into {ax},{dx}.
5095 if (Res.second->hasType(VT))
5096 return Res; // Correct type already, nothing to do.
5098 // All of the single-register GCC register classes map their values onto
5099 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
5100 // really want an 8-bit or 32-bit register, map to the appropriate register
5101 // class and return the appropriate register.
5102 if (Res.second != X86::GR16RegisterClass)
5105 if (VT == MVT::i8) {
5106 unsigned DestReg = 0;
5107 switch (Res.first) {
5109 case X86::AX: DestReg = X86::AL; break;
5110 case X86::DX: DestReg = X86::DL; break;
5111 case X86::CX: DestReg = X86::CL; break;
5112 case X86::BX: DestReg = X86::BL; break;
5115 Res.first = DestReg;
5116 Res.second = Res.second = X86::GR8RegisterClass;
5118 } else if (VT == MVT::i32) {
5119 unsigned DestReg = 0;
5120 switch (Res.first) {
5122 case X86::AX: DestReg = X86::EAX; break;
5123 case X86::DX: DestReg = X86::EDX; break;
5124 case X86::CX: DestReg = X86::ECX; break;
5125 case X86::BX: DestReg = X86::EBX; break;
5126 case X86::SI: DestReg = X86::ESI; break;
5127 case X86::DI: DestReg = X86::EDI; break;
5128 case X86::BP: DestReg = X86::EBP; break;
5129 case X86::SP: DestReg = X86::ESP; break;
5132 Res.first = DestReg;
5133 Res.second = Res.second = X86::GR32RegisterClass;
5135 } else if (VT == MVT::i64) {
5136 unsigned DestReg = 0;
5137 switch (Res.first) {
5139 case X86::AX: DestReg = X86::RAX; break;
5140 case X86::DX: DestReg = X86::RDX; break;
5141 case X86::CX: DestReg = X86::RCX; break;
5142 case X86::BX: DestReg = X86::RBX; break;
5143 case X86::SI: DestReg = X86::RSI; break;
5144 case X86::DI: DestReg = X86::RDI; break;
5145 case X86::BP: DestReg = X86::RBP; break;
5146 case X86::SP: DestReg = X86::RSP; break;
5149 Res.first = DestReg;
5150 Res.second = Res.second = X86::GR64RegisterClass;