1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86ISelLowering.h"
17 #include "X86TargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Support/CommandLine.h"
29 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
30 cl::desc("Enable fastcc on X86"));
32 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
33 : TargetLowering(TM) {
34 // Set up the TargetLowering object.
36 // X86 is weird, it always uses i8 for shift amounts and setcc results.
37 setShiftAmountType(MVT::i8);
38 setSetCCResultType(MVT::i8);
39 setSetCCResultContents(ZeroOrOneSetCCResult);
40 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
42 // Set up the register classes.
43 addRegisterClass(MVT::i8, X86::R8RegisterClass);
44 addRegisterClass(MVT::i16, X86::R16RegisterClass);
45 addRegisterClass(MVT::i32, X86::R32RegisterClass);
47 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
49 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
50 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
51 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
52 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
54 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
56 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
57 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
60 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
62 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
63 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
64 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
65 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
68 // Handle FP_TO_UINT by promoting the destination to a larger signed
70 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
71 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
72 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
75 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
77 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
79 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
80 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
81 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
83 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
84 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
87 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
89 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
90 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
91 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
92 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
93 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
94 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
95 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
96 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
97 setOperationAction(ISD::FREM , MVT::f64 , Expand);
98 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
99 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
100 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
101 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
102 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
103 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
104 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
105 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
106 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
107 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
109 setOperationAction(ISD::READIO , MVT::i1 , Expand);
110 setOperationAction(ISD::READIO , MVT::i8 , Expand);
111 setOperationAction(ISD::READIO , MVT::i16 , Expand);
112 setOperationAction(ISD::READIO , MVT::i32 , Expand);
113 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
114 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
115 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
116 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
118 // These should be promoted to a larger select which is supported.
119 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
120 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
121 // X86 wants to expand cmov itself.
123 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
124 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
125 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
126 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
127 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
128 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
131 // We don't have line number support yet.
132 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
133 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
136 // Set up the FP register classes.
137 addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
138 addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
140 // SSE has no load+extend ops
141 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
142 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
144 // SSE has no i16 to fp conversion, only i32
145 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
146 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
148 // Expand FP_TO_UINT into a select.
149 // FIXME: We would like to use a Custom expander here eventually to do
150 // the optimal thing for SSE vs. the default expansion in the legalizer.
151 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
153 // We don't support sin/cos/sqrt/fmod
154 setOperationAction(ISD::FSIN , MVT::f64, Expand);
155 setOperationAction(ISD::FCOS , MVT::f64, Expand);
156 setOperationAction(ISD::FABS , MVT::f64, Expand);
157 setOperationAction(ISD::FNEG , MVT::f64, Expand);
158 setOperationAction(ISD::FREM , MVT::f64, Expand);
159 setOperationAction(ISD::FSIN , MVT::f32, Expand);
160 setOperationAction(ISD::FCOS , MVT::f32, Expand);
161 setOperationAction(ISD::FABS , MVT::f32, Expand);
162 setOperationAction(ISD::FNEG , MVT::f32, Expand);
163 setOperationAction(ISD::FREM , MVT::f32, Expand);
165 addLegalFPImmediate(+0.0); // xorps / xorpd
167 // Set up the FP register classes.
168 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
171 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
172 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
175 addLegalFPImmediate(+0.0); // FLD0
176 addLegalFPImmediate(+1.0); // FLD1
177 addLegalFPImmediate(-0.0); // FLD0/FCHS
178 addLegalFPImmediate(-1.0); // FLD1/FCHS
180 computeRegisterProperties();
182 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
183 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
184 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
185 allowUnalignedMemoryAccesses = true; // x86 supports it!
188 std::vector<SDOperand>
189 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
190 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
191 return LowerFastCCArguments(F, DAG);
192 return LowerCCCArguments(F, DAG);
195 std::pair<SDOperand, SDOperand>
196 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
197 bool isVarArg, unsigned CallingConv,
199 SDOperand Callee, ArgListTy &Args,
201 assert((!isVarArg || CallingConv == CallingConv::C) &&
202 "Only C takes varargs!");
203 if (CallingConv == CallingConv::Fast && EnableFastCC)
204 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
205 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
208 SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
211 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
214 MVT::ValueType OpVT = Op.getValueType();
216 default: assert(0 && "Unknown type to return!");
218 Copy = DAG.getCopyToReg(Chain, X86::EAX, Op, SDOperand());
221 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
222 DAG.getConstant(1, MVT::i32));
223 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
224 DAG.getConstant(0, MVT::i32));
225 Copy = DAG.getCopyToReg(Chain, X86::EAX, Hi, SDOperand());
226 Copy = DAG.getCopyToReg(Copy, X86::EDX, Lo, Copy.getValue(1));
232 std::vector<MVT::ValueType> Tys;
233 Tys.push_back(MVT::Other);
234 Tys.push_back(MVT::Flag);
235 std::vector<SDOperand> Ops;
236 Ops.push_back(Chain);
237 if (OpVT == MVT::f32)
238 Op = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op);
240 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
242 // Spill the value to memory and reload it into top of stack.
243 unsigned Size = MVT::getSizeInBits(OpVT)/8;
244 MachineFunction &MF = DAG.getMachineFunction();
245 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
246 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
247 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Op,
248 StackSlot, DAG.getSrcValue(NULL));
249 std::vector<MVT::ValueType> Tys;
250 Tys.push_back(MVT::f64);
251 Tys.push_back(MVT::Other);
252 std::vector<SDOperand> Ops;
253 Ops.push_back(Chain);
254 Ops.push_back(StackSlot);
255 Ops.push_back(DAG.getValueType(OpVT));
256 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
258 Tys.push_back(MVT::Other);
259 Tys.push_back(MVT::Flag);
261 Ops.push_back(Copy.getValue(1));
263 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
268 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
269 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
273 //===----------------------------------------------------------------------===//
274 // C Calling Convention implementation
275 //===----------------------------------------------------------------------===//
277 std::vector<SDOperand>
278 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
279 std::vector<SDOperand> ArgValues;
281 MachineFunction &MF = DAG.getMachineFunction();
282 MachineFrameInfo *MFI = MF.getFrameInfo();
284 // Add DAG nodes to load the arguments... On entry to a function on the X86,
285 // the stack frame looks like this:
287 // [ESP] -- return address
288 // [ESP + 4] -- first argument (leftmost lexically)
289 // [ESP + 8] -- second argument, if first argument is four bytes in size
292 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
293 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
294 MVT::ValueType ObjectVT = getValueType(I->getType());
295 unsigned ArgIncrement = 4;
298 default: assert(0 && "Unhandled argument type!");
300 case MVT::i8: ObjSize = 1; break;
301 case MVT::i16: ObjSize = 2; break;
302 case MVT::i32: ObjSize = 4; break;
303 case MVT::i64: ObjSize = ArgIncrement = 8; break;
304 case MVT::f32: ObjSize = 4; break;
305 case MVT::f64: ObjSize = ArgIncrement = 8; break;
307 // Create the frame index object for this incoming parameter...
308 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
310 // Create the SelectionDAG nodes corresponding to a load from this parameter
311 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
313 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
317 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
318 DAG.getSrcValue(NULL));
320 if (MVT::isInteger(ObjectVT))
321 ArgValue = DAG.getConstant(0, ObjectVT);
323 ArgValue = DAG.getConstantFP(0, ObjectVT);
325 ArgValues.push_back(ArgValue);
327 ArgOffset += ArgIncrement; // Move on to the next argument...
330 // If the function takes variable number of arguments, make a frame index for
331 // the start of the first vararg value... for expansion of llvm.va_start.
333 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
334 ReturnAddrIndex = 0; // No return address slot generated yet.
335 BytesToPopOnReturn = 0; // Callee pops nothing.
336 BytesCallerReserves = ArgOffset;
338 // Finally, inform the code generator which regs we return values in.
339 switch (getValueType(F.getReturnType())) {
340 default: assert(0 && "Unknown type!");
341 case MVT::isVoid: break;
346 MF.addLiveOut(X86::EAX);
349 MF.addLiveOut(X86::EAX);
350 MF.addLiveOut(X86::EDX);
354 MF.addLiveOut(X86::ST0);
360 std::pair<SDOperand, SDOperand>
361 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
362 bool isVarArg, bool isTailCall,
363 SDOperand Callee, ArgListTy &Args,
365 // Count how many bytes are to be pushed on the stack.
366 unsigned NumBytes = 0;
370 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
371 DAG.getConstant(0, getPointerTy()));
373 for (unsigned i = 0, e = Args.size(); i != e; ++i)
374 switch (getValueType(Args[i].second)) {
375 default: assert(0 && "Unknown value type!");
389 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
390 DAG.getConstant(NumBytes, getPointerTy()));
392 // Arguments go on the stack in reverse order, as specified by the ABI.
393 unsigned ArgOffset = 0;
394 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
396 std::vector<SDOperand> Stores;
398 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
399 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
400 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
402 switch (getValueType(Args[i].second)) {
403 default: assert(0 && "Unexpected ValueType for argument!");
407 // Promote the integer to 32 bits. If the input type is signed use a
408 // sign extend, otherwise use a zero extend.
409 if (Args[i].second->isSigned())
410 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
412 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
417 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
418 Args[i].first, PtrOff,
419 DAG.getSrcValue(NULL)));
424 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
425 Args[i].first, PtrOff,
426 DAG.getSrcValue(NULL)));
431 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
434 std::vector<MVT::ValueType> RetVals;
435 MVT::ValueType RetTyVT = getValueType(RetTy);
436 RetVals.push_back(MVT::Other);
438 // The result values produced have to be legal. Promote the result.
440 case MVT::isVoid: break;
442 RetVals.push_back(RetTyVT);
447 RetVals.push_back(MVT::i32);
451 RetVals.push_back(MVT::f32);
453 RetVals.push_back(MVT::f64);
456 RetVals.push_back(MVT::i32);
457 RetVals.push_back(MVT::i32);
460 std::vector<SDOperand> Ops;
461 Ops.push_back(Chain);
462 Ops.push_back(Callee);
463 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
464 Ops.push_back(DAG.getConstant(0, getPointerTy()));
465 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
467 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
471 case MVT::isVoid: break;
473 ResultVal = TheCall.getValue(1);
478 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
481 // FIXME: we would really like to remember that this FP_ROUND operation is
482 // okay to eliminate if we allow excess FP precision.
483 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
486 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
487 TheCall.getValue(2));
491 return std::make_pair(ResultVal, Chain);
495 X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
496 Value *VAListV, SelectionDAG &DAG) {
497 // vastart just stores the address of the VarArgsFrameIndex slot.
498 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
499 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
500 DAG.getSrcValue(VAListV));
504 std::pair<SDOperand,SDOperand>
505 X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
506 Value *VAListV, const Type *ArgTy,
508 MVT::ValueType ArgVT = getValueType(ArgTy);
509 SDOperand Val = DAG.getLoad(MVT::i32, Chain,
510 VAListP, DAG.getSrcValue(VAListV));
511 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
512 DAG.getSrcValue(NULL));
514 if (ArgVT == MVT::i32)
517 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
518 "Other types should have been promoted for varargs!");
521 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
522 DAG.getConstant(Amt, Val.getValueType()));
523 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
524 Val, VAListP, DAG.getSrcValue(VAListV));
525 return std::make_pair(Result, Chain);
528 //===----------------------------------------------------------------------===//
529 // Fast Calling Convention implementation
530 //===----------------------------------------------------------------------===//
532 // The X86 'fast' calling convention passes up to two integer arguments in
533 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
534 // and requires that the callee pop its arguments off the stack (allowing proper
535 // tail calls), and has the same return value conventions as C calling convs.
537 // This calling convention always arranges for the callee pop value to be 8n+4
538 // bytes, which is needed for tail recursion elimination and stack alignment
541 // Note that this can be enhanced in the future to pass fp vals in registers
542 // (when we have a global fp allocator) and do other tricks.
545 /// AddLiveIn - This helper function adds the specified physical register to the
546 /// MachineFunction as a live in value. It also creates a corresponding virtual
548 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
549 TargetRegisterClass *RC) {
550 assert(RC->contains(PReg) && "Not the correct regclass!");
551 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
552 MF.addLiveIn(PReg, VReg);
557 std::vector<SDOperand>
558 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
559 std::vector<SDOperand> ArgValues;
561 MachineFunction &MF = DAG.getMachineFunction();
562 MachineFrameInfo *MFI = MF.getFrameInfo();
564 // Add DAG nodes to load the arguments... On entry to a function the stack
565 // frame looks like this:
567 // [ESP] -- return address
568 // [ESP + 4] -- first nonreg argument (leftmost lexically)
569 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
571 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
573 // Keep track of the number of integer regs passed so far. This can be either
574 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
576 unsigned NumIntRegs = 0;
578 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
579 MVT::ValueType ObjectVT = getValueType(I->getType());
580 unsigned ArgIncrement = 4;
581 unsigned ObjSize = 0;
585 default: assert(0 && "Unhandled argument type!");
588 if (NumIntRegs < 2) {
589 if (!I->use_empty()) {
590 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
591 X86::R8RegisterClass);
592 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
593 DAG.setRoot(ArgValue.getValue(1));
602 if (NumIntRegs < 2) {
603 if (!I->use_empty()) {
604 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
605 X86::R16RegisterClass);
606 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
607 DAG.setRoot(ArgValue.getValue(1));
615 if (NumIntRegs < 2) {
616 if (!I->use_empty()) {
617 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
618 X86::R32RegisterClass);
619 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
620 DAG.setRoot(ArgValue.getValue(1));
628 if (NumIntRegs == 0) {
629 if (!I->use_empty()) {
630 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
631 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
633 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
634 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
635 DAG.setRoot(Hi.getValue(1));
637 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
641 } else if (NumIntRegs == 1) {
642 if (!I->use_empty()) {
643 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
644 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
645 DAG.setRoot(Low.getValue(1));
647 // Load the high part from memory.
648 // Create the frame index object for this incoming parameter...
649 int FI = MFI->CreateFixedObject(4, ArgOffset);
650 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
651 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
652 DAG.getSrcValue(NULL));
653 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
659 ObjSize = ArgIncrement = 8;
661 case MVT::f32: ObjSize = 4; break;
662 case MVT::f64: ObjSize = ArgIncrement = 8; break;
665 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
667 if (ObjSize && !I->use_empty()) {
668 // Create the frame index object for this incoming parameter...
669 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
671 // Create the SelectionDAG nodes corresponding to a load from this
673 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
675 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
676 DAG.getSrcValue(NULL));
677 } else if (ArgValue.Val == 0) {
678 if (MVT::isInteger(ObjectVT))
679 ArgValue = DAG.getConstant(0, ObjectVT);
681 ArgValue = DAG.getConstantFP(0, ObjectVT);
683 ArgValues.push_back(ArgValue);
686 ArgOffset += ArgIncrement; // Move on to the next argument.
689 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
690 // arguments and the arguments after the retaddr has been pushed are aligned.
691 if ((ArgOffset & 7) == 0)
694 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
695 ReturnAddrIndex = 0; // No return address slot generated yet.
696 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
697 BytesCallerReserves = 0;
699 // Finally, inform the code generator which regs we return values in.
700 switch (getValueType(F.getReturnType())) {
701 default: assert(0 && "Unknown type!");
702 case MVT::isVoid: break;
707 MF.addLiveOut(X86::EAX);
710 MF.addLiveOut(X86::EAX);
711 MF.addLiveOut(X86::EDX);
715 MF.addLiveOut(X86::ST0);
721 std::pair<SDOperand, SDOperand>
722 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
723 bool isTailCall, SDOperand Callee,
724 ArgListTy &Args, SelectionDAG &DAG) {
725 // Count how many bytes are to be pushed on the stack.
726 unsigned NumBytes = 0;
728 // Keep track of the number of integer regs passed so far. This can be either
729 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
731 unsigned NumIntRegs = 0;
733 for (unsigned i = 0, e = Args.size(); i != e; ++i)
734 switch (getValueType(Args[i].second)) {
735 default: assert(0 && "Unknown value type!");
740 if (NumIntRegs < 2) {
749 if (NumIntRegs == 0) {
752 } else if (NumIntRegs == 1) {
764 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
765 // arguments and the arguments after the retaddr has been pushed are aligned.
766 if ((NumBytes & 7) == 0)
769 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
770 DAG.getConstant(NumBytes, getPointerTy()));
772 // Arguments go on the stack in reverse order, as specified by the ABI.
773 unsigned ArgOffset = 0;
774 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
777 std::vector<SDOperand> Stores;
778 std::vector<SDOperand> RegValuesToPass;
779 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
780 switch (getValueType(Args[i].second)) {
781 default: assert(0 && "Unexpected ValueType for argument!");
786 if (NumIntRegs < 2) {
787 RegValuesToPass.push_back(Args[i].first);
793 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
794 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
795 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
796 Args[i].first, PtrOff,
797 DAG.getSrcValue(NULL)));
802 if (NumIntRegs < 2) { // Can pass part of it in regs?
803 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
804 Args[i].first, DAG.getConstant(1, MVT::i32));
805 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
806 Args[i].first, DAG.getConstant(0, MVT::i32));
807 RegValuesToPass.push_back(Lo);
809 if (NumIntRegs < 2) { // Pass both parts in regs?
810 RegValuesToPass.push_back(Hi);
813 // Pass the high part in memory.
814 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
815 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
816 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
817 Hi, PtrOff, DAG.getSrcValue(NULL)));
824 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
825 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
826 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
827 Args[i].first, PtrOff,
828 DAG.getSrcValue(NULL)));
834 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
836 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
837 // arguments and the arguments after the retaddr has been pushed are aligned.
838 if ((ArgOffset & 7) == 0)
841 std::vector<MVT::ValueType> RetVals;
842 MVT::ValueType RetTyVT = getValueType(RetTy);
844 RetVals.push_back(MVT::Other);
846 // The result values produced have to be legal. Promote the result.
848 case MVT::isVoid: break;
850 RetVals.push_back(RetTyVT);
855 RetVals.push_back(MVT::i32);
859 RetVals.push_back(MVT::f32);
861 RetVals.push_back(MVT::f64);
864 RetVals.push_back(MVT::i32);
865 RetVals.push_back(MVT::i32);
869 std::vector<SDOperand> Ops;
870 Ops.push_back(Chain);
871 Ops.push_back(Callee);
872 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
873 // Callee pops all arg values on the stack.
874 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
876 // Pass register arguments as needed.
877 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
879 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
881 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
885 case MVT::isVoid: break;
887 ResultVal = TheCall.getValue(1);
892 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
895 // FIXME: we would really like to remember that this FP_ROUND operation is
896 // okay to eliminate if we allow excess FP precision.
897 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
900 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
901 TheCall.getValue(2));
905 return std::make_pair(ResultVal, Chain);
908 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
909 if (ReturnAddrIndex == 0) {
910 // Set up a frame object for the return address.
911 MachineFunction &MF = DAG.getMachineFunction();
912 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
915 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
920 std::pair<SDOperand, SDOperand> X86TargetLowering::
921 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
924 if (Depth) // Depths > 0 not supported yet!
925 Result = DAG.getConstant(0, getPointerTy());
927 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
929 // Just load the return address
930 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
931 DAG.getSrcValue(NULL));
933 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
934 DAG.getConstant(4, MVT::i32));
936 return std::make_pair(Result, Chain);
939 //===----------------------------------------------------------------------===//
940 // X86 Custom Lowering Hooks
941 //===----------------------------------------------------------------------===//
943 /// LowerOperation - Provide custom lowering hooks for some operations.
945 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
946 switch (Op.getOpcode()) {
947 default: assert(0 && "Should not custom lower this!");
948 case ISD::SINT_TO_FP: {
949 assert(Op.getValueType() == MVT::f64 &&
950 Op.getOperand(0).getValueType() == MVT::i64 &&
951 "Unknown SINT_TO_FP to lower!");
952 // We lower sint64->FP into a store to a temporary stack slot, followed by a
954 MachineFunction &MF = DAG.getMachineFunction();
955 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
956 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
957 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
958 Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
959 std::vector<MVT::ValueType> RTs;
960 RTs.push_back(MVT::f64);
961 RTs.push_back(MVT::Other);
962 std::vector<SDOperand> Ops;
963 Ops.push_back(Store);
964 Ops.push_back(StackSlot);
965 return DAG.getNode(X86ISD::FILD64m, RTs, Ops);
967 case ISD::FP_TO_SINT: {
968 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
969 Op.getOperand(0).getValueType() == MVT::f64 &&
970 "Unknown FP_TO_SINT to lower!");
971 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
973 MachineFunction &MF = DAG.getMachineFunction();
974 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
975 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
976 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
979 switch (Op.getValueType()) {
980 default: assert(0 && "Invalid FP_TO_SINT to lower!");
981 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
982 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
983 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
986 // Build the FP_TO_INT*_IN_MEM
987 std::vector<SDOperand> Ops;
988 Ops.push_back(DAG.getEntryNode());
989 Ops.push_back(Op.getOperand(0));
990 Ops.push_back(StackSlot);
991 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
994 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
995 DAG.getSrcValue(NULL));
997 case ISD::READCYCLECOUNTER: {
998 std::vector<MVT::ValueType> Tys;
999 Tys.push_back(MVT::Other);
1000 Tys.push_back(MVT::Flag);
1001 std::vector<SDOperand> Ops;
1002 Ops.push_back(Op.getOperand(0));
1003 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
1005 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
1006 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
1007 MVT::i32, Ops[0].getValue(2)));
1008 Ops.push_back(Ops[1].getValue(1));
1009 Tys[0] = Tys[1] = MVT::i32;
1010 Tys.push_back(MVT::Other);
1011 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1014 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
1015 SDOperand CC = Op.getOperand(2);
1016 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1017 Op.getOperand(0), Op.getOperand(1));
1018 return DAG.getNode(X86ISD::SETCC, MVT::i8, CC, Cond);
1021 SDOperand Cond = Op.getOperand(0);
1023 if (Cond.getOpcode() == X86ISD::SETCC) {
1024 CC = Cond.getOperand(0);
1025 Cond = Cond.getOperand(1);
1026 } else if (Cond.getOpcode() == ISD::SETCC) {
1027 CC = Cond.getOperand(2);
1028 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1029 Cond.getOperand(0), Cond.getOperand(1));
1031 CC = DAG.getCondCode(ISD::SETEQ);
1032 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1034 return DAG.getNode(X86ISD::CMOV, Op.getValueType(),
1035 Op.getOperand(1), Op.getOperand(2), CC, Cond);
1038 SDOperand Cond = Op.getOperand(1);
1039 SDOperand Dest = Op.getOperand(2);
1041 // TODO: handle Cond == OR / AND / XOR
1042 if (Cond.getOpcode() == X86ISD::SETCC) {
1043 CC = Cond.getOperand(0);
1044 Cond = Cond.getOperand(1);
1045 } else if (Cond.getOpcode() == ISD::SETCC) {
1046 CC = Cond.getOperand(2);
1047 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1048 Cond.getOperand(0), Cond.getOperand(1));
1050 CC = DAG.getCondCode(ISD::SETNE);
1051 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1053 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
1054 Op.getOperand(0), Op.getOperand(2), CC, Cond);
1056 case ISD::GlobalAddress: {
1057 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1058 SDOperand GVOp = DAG.getTargetGlobalAddress(GV, getPointerTy());
1059 // For Darwin, external and weak symbols are indirect, so we want to load
1060 // the value at address GV, not the value of GV itself. This means that
1061 // the GlobalAddress must be in the base or index register of the address,
1062 // not the GV offset field.
1063 if (getTargetMachine().
1064 getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() &&
1065 (GV->hasWeakLinkage() || GV->isExternal()))
1066 return DAG.getLoad(MVT::i32, DAG.getEntryNode(),
1067 GVOp, DAG.getSrcValue(NULL));
1075 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1077 default: return NULL;
1078 case X86ISD::FILD64m: return "X86ISD::FILD64m";
1079 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
1080 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
1081 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
1082 case X86ISD::FLD: return "X86ISD::FLD";
1083 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
1084 case X86ISD::CALL: return "X86ISD::CALL";
1085 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
1086 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
1087 case X86ISD::CMP: return "X86ISD::CMP";
1088 case X86ISD::TEST: return "X86ISD::TEST";
1089 case X86ISD::SETCC: return "X86ISD::SETCC";
1090 case X86ISD::CMOV: return "X86ISD::CMOV";
1091 case X86ISD::BRCOND: return "X86ISD::BRCOND";
1092 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
1096 bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
1097 uint64_t Mask) const {
1099 unsigned Opc = Op.getOpcode();
1103 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
1105 case X86ISD::SETCC: return (Mask & 1) == 0;