1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/ADT/VectorExtras.h"
26 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/SelectionDAG.h"
32 #include "llvm/CodeGen/SSARegMap.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/ADT/StringExtras.h"
38 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
39 : TargetLowering(TM) {
40 Subtarget = &TM.getSubtarget<X86Subtarget>();
41 X86ScalarSSE = Subtarget->hasSSE2();
42 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
44 // Set up the TargetLowering object.
46 // X86 is weird, it always uses i8 for shift amounts and setcc results.
47 setShiftAmountType(MVT::i8);
48 setSetCCResultType(MVT::i8);
49 setSetCCResultContents(ZeroOrOneSetCCResult);
50 setSchedulingPreference(SchedulingForRegPressure);
51 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
52 setStackPointerRegisterToSaveRestore(X86StackPtr);
54 if (Subtarget->isTargetDarwin()) {
55 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
56 setUseUnderscoreSetJmp(false);
57 setUseUnderscoreLongJmp(false);
58 } else if (Subtarget->isTargetMingw()) {
59 // MS runtime is weird: it exports _setjmp, but longjmp!
60 setUseUnderscoreSetJmp(true);
61 setUseUnderscoreLongJmp(false);
63 setUseUnderscoreSetJmp(true);
64 setUseUnderscoreLongJmp(true);
67 // Set up the register classes.
68 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
69 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
70 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
71 if (Subtarget->is64Bit())
72 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
74 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
76 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
78 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
79 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
80 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
82 if (Subtarget->is64Bit()) {
83 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
84 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
87 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
88 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
90 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
93 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
95 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
96 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
97 // SSE has no i16 to fp conversion, only i32
99 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
101 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
102 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
105 if (!Subtarget->is64Bit()) {
106 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode.
107 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
108 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
111 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
113 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
114 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
117 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
119 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
120 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
123 // Handle FP_TO_UINT by promoting the destination to a larger signed
125 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
126 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
127 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
129 if (Subtarget->is64Bit()) {
130 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
131 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
133 if (X86ScalarSSE && !Subtarget->hasSSE3())
134 // Expand FP_TO_UINT into a select.
135 // FIXME: We would like to use a Custom expander here eventually to do
136 // the optimal thing for SSE vs. the default expansion in the legalizer.
137 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
139 // With SSE3 we can use fisttpll to convert to a signed i64.
140 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
143 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
145 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
146 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
149 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
150 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
151 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
152 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
153 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
154 if (Subtarget->is64Bit())
155 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
159 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
160 setOperationAction(ISD::FREM , MVT::f64 , Expand);
162 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
163 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
164 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
165 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
166 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
167 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
168 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
169 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
170 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
171 if (Subtarget->is64Bit()) {
172 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
173 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
174 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
177 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
178 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
180 // These should be promoted to a larger select which is supported.
181 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
182 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
183 // X86 wants to expand cmov itself.
184 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
185 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
186 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
187 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
188 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
189 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
190 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
191 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
192 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
193 if (Subtarget->is64Bit()) {
194 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
195 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
197 // X86 ret instruction may pop stack.
198 setOperationAction(ISD::RET , MVT::Other, Custom);
200 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
201 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
202 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
203 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
204 if (Subtarget->is64Bit()) {
205 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
206 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
207 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
208 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
210 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
211 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
212 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
213 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
214 // X86 wants to expand memset / memcpy itself.
215 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
216 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
218 // We don't have line number support yet.
219 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
220 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
221 // FIXME - use subtarget debug flags
222 if (!Subtarget->isTargetDarwin() &&
223 !Subtarget->isTargetELF() &&
224 !Subtarget->isTargetCygMing())
225 setOperationAction(ISD::LABEL, MVT::Other, Expand);
227 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
228 setOperationAction(ISD::VASTART , MVT::Other, Custom);
229 setOperationAction(ISD::VAARG , MVT::Other, Expand);
230 setOperationAction(ISD::VAEND , MVT::Other, Expand);
231 if (Subtarget->is64Bit())
232 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
234 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
236 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
237 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
238 if (Subtarget->is64Bit())
239 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
240 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
243 // Set up the FP register classes.
244 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
245 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
247 // Use ANDPD to simulate FABS.
248 setOperationAction(ISD::FABS , MVT::f64, Custom);
249 setOperationAction(ISD::FABS , MVT::f32, Custom);
251 // Use XORP to simulate FNEG.
252 setOperationAction(ISD::FNEG , MVT::f64, Custom);
253 setOperationAction(ISD::FNEG , MVT::f32, Custom);
255 // Use ANDPD and ORPD to simulate FCOPYSIGN.
256 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
257 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
259 // We don't support sin/cos/fmod
260 setOperationAction(ISD::FSIN , MVT::f64, Expand);
261 setOperationAction(ISD::FCOS , MVT::f64, Expand);
262 setOperationAction(ISD::FREM , MVT::f64, Expand);
263 setOperationAction(ISD::FSIN , MVT::f32, Expand);
264 setOperationAction(ISD::FCOS , MVT::f32, Expand);
265 setOperationAction(ISD::FREM , MVT::f32, Expand);
267 // Expand FP immediates into loads from the stack, except for the special
269 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
270 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
271 addLegalFPImmediate(+0.0); // xorps / xorpd
273 // Set up the FP register classes.
274 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
276 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
277 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
278 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
281 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
282 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
285 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
286 addLegalFPImmediate(+0.0); // FLD0
287 addLegalFPImmediate(+1.0); // FLD1
288 addLegalFPImmediate(-0.0); // FLD0/FCHS
289 addLegalFPImmediate(-1.0); // FLD1/FCHS
292 // First set operation action for all vector types to expand. Then we
293 // will selectively turn on ones that can be effectively codegen'd.
294 for (unsigned VT = (unsigned)MVT::Vector + 1;
295 VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
296 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
297 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
298 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
299 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
300 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
301 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
302 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
303 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
304 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
305 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
306 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
307 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
308 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
309 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
310 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
313 if (Subtarget->hasMMX()) {
314 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
315 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
316 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
318 // FIXME: add MMX packed arithmetics
320 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
321 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
322 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
324 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
325 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
326 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
328 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
329 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
331 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
332 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
333 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
334 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32);
335 setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
337 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
338 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
339 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
342 if (Subtarget->hasSSE1()) {
343 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
345 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
346 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
347 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
348 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
349 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
350 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
351 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
352 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
353 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
356 if (Subtarget->hasSSE2()) {
357 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
358 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
359 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
360 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
361 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
363 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
364 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
365 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
366 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
367 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
368 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
369 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
370 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
371 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
372 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
373 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
374 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
375 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
377 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
378 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
379 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
380 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
381 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
382 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
384 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
385 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
386 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
387 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
388 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
390 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
391 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
392 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
393 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
394 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
395 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
397 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
398 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
399 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
400 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
401 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
402 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
403 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
404 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
405 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
406 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
407 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
408 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
411 // Custom lower v2i64 and v2f64 selects.
412 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
413 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
414 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
415 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
418 // We want to custom lower some of our intrinsics.
419 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
421 // We have target-specific dag combine patterns for the following nodes:
422 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
423 setTargetDAGCombine(ISD::SELECT);
425 computeRegisterProperties();
427 // FIXME: These should be based on subtarget info. Plus, the values should
428 // be smaller when we are in optimizing for size mode.
429 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
430 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
431 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
432 allowUnalignedMemoryAccesses = true; // x86 supports it!
436 //===----------------------------------------------------------------------===//
437 // Return Value Calling Convention Implementation
438 //===----------------------------------------------------------------------===//
440 #include "X86GenCallingConv.inc"
442 /// LowerRET - Lower an ISD::RET node.
443 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
444 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
446 SmallVector<CCValAssign, 16> RVLocs;
447 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
448 CCState CCInfo(CC, getTargetMachine(), RVLocs);
449 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
452 // If this is the first return lowered for this function, add the regs to the
453 // liveout set for the function.
454 if (DAG.getMachineFunction().liveout_empty()) {
455 for (unsigned i = 0; i != RVLocs.size(); ++i)
456 if (RVLocs[i].isRegLoc())
457 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
460 SDOperand Chain = Op.getOperand(0);
463 // Copy the result values into the output registers.
464 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
465 RVLocs[0].getLocReg() != X86::ST0) {
466 for (unsigned i = 0; i != RVLocs.size(); ++i) {
467 CCValAssign &VA = RVLocs[i];
468 assert(VA.isRegLoc() && "Can only return in registers!");
469 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1),
471 Flag = Chain.getValue(1);
474 // We need to handle a destination of ST0 specially, because it isn't really
476 SDOperand Value = Op.getOperand(1);
478 // If this is an FP return with ScalarSSE, we need to move the value from
479 // an XMM register onto the fp-stack.
483 // If this is a load into a scalarsse value, don't store the loaded value
484 // back to the stack, only to reload it: just replace the scalar-sse load.
485 if (ISD::isNON_EXTLoad(Value.Val) &&
486 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
487 Chain = Value.getOperand(0);
488 MemLoc = Value.getOperand(1);
490 // Spill the value to memory and reload it into top of stack.
491 unsigned Size = MVT::getSizeInBits(RVLocs[0].getValVT())/8;
492 MachineFunction &MF = DAG.getMachineFunction();
493 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
494 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
495 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
497 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
498 SDOperand Ops[] = {Chain, MemLoc, DAG.getValueType(RVLocs[0].getValVT())};
499 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
500 Chain = Value.getValue(1);
503 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
504 SDOperand Ops[] = { Chain, Value };
505 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
506 Flag = Chain.getValue(1);
509 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
511 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
513 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
517 /// LowerCallResult - Lower the result values of an ISD::CALL into the
518 /// appropriate copies out of appropriate physical registers. This assumes that
519 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
520 /// being lowered. The returns a SDNode with the same number of values as the
522 SDNode *X86TargetLowering::
523 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
524 unsigned CallingConv, SelectionDAG &DAG) {
526 // Assign locations to each value returned by this call.
527 SmallVector<CCValAssign, 16> RVLocs;
528 CCState CCInfo(CallingConv, getTargetMachine(), RVLocs);
529 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
532 SmallVector<SDOperand, 8> ResultVals;
534 // Copy all of the result registers out of their specified physreg.
535 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
536 for (unsigned i = 0; i != RVLocs.size(); ++i) {
537 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
538 RVLocs[i].getValVT(), InFlag).getValue(1);
539 InFlag = Chain.getValue(2);
540 ResultVals.push_back(Chain.getValue(0));
543 // Copies from the FP stack are special, as ST0 isn't a valid register
544 // before the fp stackifier runs.
546 // Copy ST0 into an RFP register with FP_GET_RESULT.
547 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
548 SDOperand GROps[] = { Chain, InFlag };
549 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
550 Chain = RetVal.getValue(1);
551 InFlag = RetVal.getValue(2);
553 // If we are using ScalarSSE, store ST(0) to the stack and reload it into
556 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
557 // shouldn't be necessary except that RFP cannot be live across
558 // multiple blocks. When stackifier is fixed, they can be uncoupled.
559 MachineFunction &MF = DAG.getMachineFunction();
560 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
561 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
563 Chain, RetVal, StackSlot, DAG.getValueType(RVLocs[0].getValVT()), InFlag
565 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
566 RetVal = DAG.getLoad(RVLocs[0].getValVT(), Chain, StackSlot, NULL, 0);
567 Chain = RetVal.getValue(1);
570 if (RVLocs[0].getValVT() == MVT::f32 && !X86ScalarSSE)
571 // FIXME: we would really like to remember that this FP_ROUND
572 // operation is okay to eliminate if we allow excess FP precision.
573 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
574 ResultVals.push_back(RetVal);
577 // Merge everything together with a MERGE_VALUES node.
578 ResultVals.push_back(Chain);
579 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
580 &ResultVals[0], ResultVals.size()).Val;
584 //===----------------------------------------------------------------------===//
585 // C & StdCall Calling Convention implementation
586 //===----------------------------------------------------------------------===//
587 // StdCall calling convention seems to be standard for many Windows' API
588 // routines and around. It differs from C calling convention just a little:
589 // callee should clean up the stack, not caller. Symbols should be also
590 // decorated in some fancy way :) It doesn't support any vector arguments.
592 /// AddLiveIn - This helper function adds the specified physical register to the
593 /// MachineFunction as a live in value. It also creates a corresponding virtual
595 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
596 const TargetRegisterClass *RC) {
597 assert(RC->contains(PReg) && "Not the correct regclass!");
598 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
599 MF.addLiveIn(PReg, VReg);
603 SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
605 unsigned NumArgs = Op.Val->getNumValues() - 1;
606 MachineFunction &MF = DAG.getMachineFunction();
607 MachineFrameInfo *MFI = MF.getFrameInfo();
608 SDOperand Root = Op.getOperand(0);
609 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
611 // Assign locations to all of the incoming arguments.
612 SmallVector<CCValAssign, 16> ArgLocs;
613 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
615 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_C);
617 SmallVector<SDOperand, 8> ArgValues;
618 unsigned LastVal = ~0U;
619 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
620 CCValAssign &VA = ArgLocs[i];
621 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
623 assert(VA.getValNo() != LastVal &&
624 "Don't support value assigned to multiple locs yet");
625 LastVal = VA.getValNo();
628 MVT::ValueType RegVT = VA.getLocVT();
629 TargetRegisterClass *RC;
630 if (RegVT == MVT::i32)
631 RC = X86::GR32RegisterClass;
633 assert(MVT::isVector(RegVT));
634 RC = X86::VR128RegisterClass;
637 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
638 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
640 // If this is an 8 or 16-bit value, it is really passed promoted to 32
641 // bits. Insert an assert[sz]ext to capture this, then truncate to the
643 if (VA.getLocInfo() == CCValAssign::SExt)
644 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
645 DAG.getValueType(VA.getValVT()));
646 else if (VA.getLocInfo() == CCValAssign::ZExt)
647 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
648 DAG.getValueType(VA.getValVT()));
650 if (VA.getLocInfo() != CCValAssign::Full)
651 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
653 ArgValues.push_back(ArgValue);
655 assert(VA.isMemLoc());
657 // Create the nodes corresponding to a load from this parameter slot.
658 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
659 VA.getLocMemOffset());
660 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
661 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
665 unsigned StackSize = CCInfo.getNextStackOffset();
667 ArgValues.push_back(Root);
669 // If the function takes variable number of arguments, make a frame index for
670 // the start of the first vararg value... for expansion of llvm.va_start.
672 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
674 if (isStdCall && !isVarArg) {
675 BytesToPopOnReturn = StackSize; // Callee pops everything..
676 BytesCallerReserves = 0;
678 BytesToPopOnReturn = 0; // Callee pops nothing.
680 // If this is an sret function, the return should pop the hidden pointer.
682 (cast<ConstantSDNode>(Op.getOperand(3))->getValue() &
683 ISD::ParamFlags::StructReturn))
684 BytesToPopOnReturn = 4;
686 BytesCallerReserves = StackSize;
689 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
690 ReturnAddrIndex = 0; // No return address slot generated yet.
692 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn);
694 // Return the new list of results.
695 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
696 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
699 SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
701 SDOperand Chain = Op.getOperand(0);
702 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
703 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
704 SDOperand Callee = Op.getOperand(4);
705 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
707 // Analyze operands of the call, assigning locations to each operand.
708 SmallVector<CCValAssign, 16> ArgLocs;
709 CCState CCInfo(CC, getTargetMachine(), ArgLocs);
710 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_C);
712 // Get a count of how many bytes are to be pushed on the stack.
713 unsigned NumBytes = CCInfo.getNextStackOffset();
715 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
717 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
718 SmallVector<SDOperand, 8> MemOpChains;
722 // Walk the register/memloc assignments, inserting copies/loads.
723 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
724 CCValAssign &VA = ArgLocs[i];
725 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
727 // Promote the value if needed.
728 switch (VA.getLocInfo()) {
729 default: assert(0 && "Unknown loc info!");
730 case CCValAssign::Full: break;
731 case CCValAssign::SExt:
732 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
734 case CCValAssign::ZExt:
735 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
737 case CCValAssign::AExt:
738 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
743 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
745 assert(VA.isMemLoc());
746 if (StackPtr.Val == 0)
747 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
748 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
749 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
750 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
754 // If the first argument is an sret pointer, remember it.
755 bool isSRet = NumOps &&
756 (cast<ConstantSDNode>(Op.getOperand(6))->getValue() &
757 ISD::ParamFlags::StructReturn);
759 if (!MemOpChains.empty())
760 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
761 &MemOpChains[0], MemOpChains.size());
763 // Build a sequence of copy-to-reg nodes chained together with token chain
764 // and flag operands which copy the outgoing args into registers.
766 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
767 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
769 InFlag = Chain.getValue(1);
772 // ELF / PIC requires GOT in the EBX register before function calls via PLT
774 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
775 Subtarget->isPICStyleGOT()) {
776 Chain = DAG.getCopyToReg(Chain, X86::EBX,
777 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
779 InFlag = Chain.getValue(1);
782 // If the callee is a GlobalAddress node (quite common, every direct call is)
783 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
784 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
785 // We should use extra load for direct calls to dllimported functions in
787 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
788 getTargetMachine(), true))
789 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
790 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
791 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
793 // Returns a chain & a flag for retval copy to use.
794 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
795 SmallVector<SDOperand, 8> Ops;
796 Ops.push_back(Chain);
797 Ops.push_back(Callee);
799 // Add argument registers to the end of the list so that they are known live
801 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
802 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
803 RegsToPass[i].second.getValueType()));
805 // Add an implicit use GOT pointer in EBX.
806 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
807 Subtarget->isPICStyleGOT())
808 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
811 Ops.push_back(InFlag);
813 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
814 NodeTys, &Ops[0], Ops.size());
815 InFlag = Chain.getValue(1);
817 // Create the CALLSEQ_END node.
818 unsigned NumBytesForCalleeToPush = 0;
820 if (CC == CallingConv::X86_StdCall) {
822 NumBytesForCalleeToPush = isSRet ? 4 : 0;
824 NumBytesForCalleeToPush = NumBytes;
826 // If this is is a call to a struct-return function, the callee
827 // pops the hidden struct pointer, so we have to push it back.
828 // This is common for Darwin/X86, Linux & Mingw32 targets.
829 NumBytesForCalleeToPush = isSRet ? 4 : 0;
832 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
834 Ops.push_back(Chain);
835 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
836 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
837 Ops.push_back(InFlag);
838 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
839 InFlag = Chain.getValue(1);
841 // Handle result values, copying them out of physregs into vregs that we
843 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
847 //===----------------------------------------------------------------------===//
848 // FastCall Calling Convention implementation
849 //===----------------------------------------------------------------------===//
851 // The X86 'fastcall' calling convention passes up to two integer arguments in
852 // registers (an appropriate portion of ECX/EDX), passes arguments in C order,
853 // and requires that the callee pop its arguments off the stack (allowing proper
854 // tail calls), and has the same return value conventions as C calling convs.
856 // This calling convention always arranges for the callee pop value to be 8n+4
857 // bytes, which is needed for tail recursion elimination and stack alignment
860 X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
861 MachineFunction &MF = DAG.getMachineFunction();
862 MachineFrameInfo *MFI = MF.getFrameInfo();
863 SDOperand Root = Op.getOperand(0);
865 // Assign locations to all of the incoming arguments.
866 SmallVector<CCValAssign, 16> ArgLocs;
867 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
869 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_FastCall);
871 SmallVector<SDOperand, 8> ArgValues;
872 unsigned LastVal = ~0U;
873 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
874 CCValAssign &VA = ArgLocs[i];
875 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
877 assert(VA.getValNo() != LastVal &&
878 "Don't support value assigned to multiple locs yet");
879 LastVal = VA.getValNo();
882 MVT::ValueType RegVT = VA.getLocVT();
883 TargetRegisterClass *RC;
884 if (RegVT == MVT::i32)
885 RC = X86::GR32RegisterClass;
887 assert(MVT::isVector(RegVT));
888 RC = X86::VR128RegisterClass;
891 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
892 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
894 // If this is an 8 or 16-bit value, it is really passed promoted to 32
895 // bits. Insert an assert[sz]ext to capture this, then truncate to the
897 if (VA.getLocInfo() == CCValAssign::SExt)
898 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
899 DAG.getValueType(VA.getValVT()));
900 else if (VA.getLocInfo() == CCValAssign::ZExt)
901 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
902 DAG.getValueType(VA.getValVT()));
904 if (VA.getLocInfo() != CCValAssign::Full)
905 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
907 ArgValues.push_back(ArgValue);
909 assert(VA.isMemLoc());
911 // Create the nodes corresponding to a load from this parameter slot.
912 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
913 VA.getLocMemOffset());
914 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
915 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
919 ArgValues.push_back(Root);
921 unsigned StackSize = CCInfo.getNextStackOffset();
923 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
924 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
925 // arguments and the arguments after the retaddr has been pushed are aligned.
926 if ((StackSize & 7) == 0)
930 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
931 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
932 ReturnAddrIndex = 0; // No return address slot generated yet.
933 BytesToPopOnReturn = StackSize; // Callee pops all stack arguments.
934 BytesCallerReserves = 0;
936 MF.getInfo<X86FunctionInfo>()->setBytesToPopOnReturn(BytesToPopOnReturn);
938 // Return the new list of results.
939 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
940 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
943 SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
945 SDOperand Chain = Op.getOperand(0);
946 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
947 SDOperand Callee = Op.getOperand(4);
949 // Analyze operands of the call, assigning locations to each operand.
950 SmallVector<CCValAssign, 16> ArgLocs;
951 CCState CCInfo(CC, getTargetMachine(), ArgLocs);
952 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_FastCall);
954 // Get a count of how many bytes are to be pushed on the stack.
955 unsigned NumBytes = CCInfo.getNextStackOffset();
957 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
958 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
959 // arguments and the arguments after the retaddr has been pushed are aligned.
960 if ((NumBytes & 7) == 0)
964 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
966 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
967 SmallVector<SDOperand, 8> MemOpChains;
971 // Walk the register/memloc assignments, inserting copies/loads.
972 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
973 CCValAssign &VA = ArgLocs[i];
974 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
976 // Promote the value if needed.
977 switch (VA.getLocInfo()) {
978 default: assert(0 && "Unknown loc info!");
979 case CCValAssign::Full: break;
980 case CCValAssign::SExt:
981 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
983 case CCValAssign::ZExt:
984 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
986 case CCValAssign::AExt:
987 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
992 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
994 assert(VA.isMemLoc());
995 if (StackPtr.Val == 0)
996 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
997 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
998 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
999 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1003 if (!MemOpChains.empty())
1004 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1005 &MemOpChains[0], MemOpChains.size());
1007 // Build a sequence of copy-to-reg nodes chained together with token chain
1008 // and flag operands which copy the outgoing args into registers.
1010 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1011 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1013 InFlag = Chain.getValue(1);
1016 // If the callee is a GlobalAddress node (quite common, every direct call is)
1017 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1018 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1019 // We should use extra load for direct calls to dllimported functions in
1021 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1022 getTargetMachine(), true))
1023 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1024 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1025 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1027 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1029 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1030 Subtarget->isPICStyleGOT()) {
1031 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1032 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1034 InFlag = Chain.getValue(1);
1037 // Returns a chain & a flag for retval copy to use.
1038 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1039 SmallVector<SDOperand, 8> Ops;
1040 Ops.push_back(Chain);
1041 Ops.push_back(Callee);
1043 // Add argument registers to the end of the list so that they are known live
1045 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1046 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1047 RegsToPass[i].second.getValueType()));
1049 // Add an implicit use GOT pointer in EBX.
1050 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1051 Subtarget->isPICStyleGOT())
1052 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1055 Ops.push_back(InFlag);
1057 // FIXME: Do not generate X86ISD::TAILCALL for now.
1058 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1059 NodeTys, &Ops[0], Ops.size());
1060 InFlag = Chain.getValue(1);
1062 // Returns a flag for retval copy to use.
1063 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1065 Ops.push_back(Chain);
1066 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1067 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1068 Ops.push_back(InFlag);
1069 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1070 InFlag = Chain.getValue(1);
1072 // Handle result values, copying them out of physregs into vregs that we
1074 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1078 //===----------------------------------------------------------------------===//
1079 // X86-64 C Calling Convention implementation
1080 //===----------------------------------------------------------------------===//
1083 X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
1084 MachineFunction &MF = DAG.getMachineFunction();
1085 MachineFrameInfo *MFI = MF.getFrameInfo();
1086 SDOperand Root = Op.getOperand(0);
1087 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1089 static const unsigned GPR64ArgRegs[] = {
1090 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1092 static const unsigned XMMArgRegs[] = {
1093 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1094 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1098 // Assign locations to all of the incoming arguments.
1099 SmallVector<CCValAssign, 16> ArgLocs;
1100 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
1102 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_64_C);
1104 SmallVector<SDOperand, 8> ArgValues;
1105 unsigned LastVal = ~0U;
1106 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1107 CCValAssign &VA = ArgLocs[i];
1108 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1110 assert(VA.getValNo() != LastVal &&
1111 "Don't support value assigned to multiple locs yet");
1112 LastVal = VA.getValNo();
1114 if (VA.isRegLoc()) {
1115 MVT::ValueType RegVT = VA.getLocVT();
1116 TargetRegisterClass *RC;
1117 if (RegVT == MVT::i32)
1118 RC = X86::GR32RegisterClass;
1119 else if (RegVT == MVT::i64)
1120 RC = X86::GR64RegisterClass;
1121 else if (RegVT == MVT::f32)
1122 RC = X86::FR32RegisterClass;
1123 else if (RegVT == MVT::f64)
1124 RC = X86::FR64RegisterClass;
1126 assert(MVT::isVector(RegVT));
1127 RC = X86::VR128RegisterClass;
1130 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1131 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1133 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1134 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1136 if (VA.getLocInfo() == CCValAssign::SExt)
1137 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1138 DAG.getValueType(VA.getValVT()));
1139 else if (VA.getLocInfo() == CCValAssign::ZExt)
1140 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1141 DAG.getValueType(VA.getValVT()));
1143 if (VA.getLocInfo() != CCValAssign::Full)
1144 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1146 ArgValues.push_back(ArgValue);
1148 assert(VA.isMemLoc());
1150 // Create the nodes corresponding to a load from this parameter slot.
1151 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1152 VA.getLocMemOffset());
1153 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1154 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
1158 unsigned StackSize = CCInfo.getNextStackOffset();
1160 // If the function takes variable number of arguments, make a frame index for
1161 // the start of the first vararg value... for expansion of llvm.va_start.
1163 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1164 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1166 // For X86-64, if there are vararg parameters that are passed via
1167 // registers, then we must store them to their spots on the stack so they
1168 // may be loaded by deferencing the result of va_next.
1169 VarArgsGPOffset = NumIntRegs * 8;
1170 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1171 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1172 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1174 // Store the integer parameter registers.
1175 SmallVector<SDOperand, 8> MemOps;
1176 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1177 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1178 DAG.getConstant(VarArgsGPOffset, getPointerTy()));
1179 for (; NumIntRegs != 6; ++NumIntRegs) {
1180 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1181 X86::GR64RegisterClass);
1182 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1183 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1184 MemOps.push_back(Store);
1185 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1186 DAG.getConstant(8, getPointerTy()));
1189 // Now store the XMM (fp + vector) parameter registers.
1190 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1191 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1192 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1193 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1194 X86::VR128RegisterClass);
1195 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1196 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1197 MemOps.push_back(Store);
1198 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1199 DAG.getConstant(16, getPointerTy()));
1201 if (!MemOps.empty())
1202 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1203 &MemOps[0], MemOps.size());
1206 ArgValues.push_back(Root);
1208 ReturnAddrIndex = 0; // No return address slot generated yet.
1209 BytesToPopOnReturn = 0; // Callee pops nothing.
1210 BytesCallerReserves = StackSize;
1212 // Return the new list of results.
1213 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1214 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1218 X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
1220 SDOperand Chain = Op.getOperand(0);
1221 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1222 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1223 SDOperand Callee = Op.getOperand(4);
1225 // Analyze operands of the call, assigning locations to each operand.
1226 SmallVector<CCValAssign, 16> ArgLocs;
1227 CCState CCInfo(CC, getTargetMachine(), ArgLocs);
1228 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_64_C);
1230 // Get a count of how many bytes are to be pushed on the stack.
1231 unsigned NumBytes = CCInfo.getNextStackOffset();
1232 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1234 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1235 SmallVector<SDOperand, 8> MemOpChains;
1239 // Walk the register/memloc assignments, inserting copies/loads.
1240 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1241 CCValAssign &VA = ArgLocs[i];
1242 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1244 // Promote the value if needed.
1245 switch (VA.getLocInfo()) {
1246 default: assert(0 && "Unknown loc info!");
1247 case CCValAssign::Full: break;
1248 case CCValAssign::SExt:
1249 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1251 case CCValAssign::ZExt:
1252 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1254 case CCValAssign::AExt:
1255 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1259 if (VA.isRegLoc()) {
1260 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1262 assert(VA.isMemLoc());
1263 if (StackPtr.Val == 0)
1264 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1265 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1266 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1267 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1271 if (!MemOpChains.empty())
1272 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1273 &MemOpChains[0], MemOpChains.size());
1275 // Build a sequence of copy-to-reg nodes chained together with token chain
1276 // and flag operands which copy the outgoing args into registers.
1278 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1279 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1281 InFlag = Chain.getValue(1);
1285 // From AMD64 ABI document:
1286 // For calls that may call functions that use varargs or stdargs
1287 // (prototype-less calls or calls to functions containing ellipsis (...) in
1288 // the declaration) %al is used as hidden argument to specify the number
1289 // of SSE registers used. The contents of %al do not need to match exactly
1290 // the number of registers, but must be an ubound on the number of SSE
1291 // registers used and is in the range 0 - 8 inclusive.
1293 // Count the number of XMM registers allocated.
1294 static const unsigned XMMArgRegs[] = {
1295 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1296 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1298 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1300 Chain = DAG.getCopyToReg(Chain, X86::AL,
1301 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1302 InFlag = Chain.getValue(1);
1305 // If the callee is a GlobalAddress node (quite common, every direct call is)
1306 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1307 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1308 // We should use extra load for direct calls to dllimported functions in
1310 if (getTargetMachine().getCodeModel() != CodeModel::Large
1311 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1312 getTargetMachine(), true))
1313 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1314 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1315 if (getTargetMachine().getCodeModel() != CodeModel::Large)
1316 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1318 // Returns a chain & a flag for retval copy to use.
1319 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1320 SmallVector<SDOperand, 8> Ops;
1321 Ops.push_back(Chain);
1322 Ops.push_back(Callee);
1324 // Add argument registers to the end of the list so that they are known live
1326 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1327 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1328 RegsToPass[i].second.getValueType()));
1331 Ops.push_back(InFlag);
1333 // FIXME: Do not generate X86ISD::TAILCALL for now.
1334 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1335 NodeTys, &Ops[0], Ops.size());
1336 InFlag = Chain.getValue(1);
1338 // Returns a flag for retval copy to use.
1339 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1341 Ops.push_back(Chain);
1342 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1343 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1344 Ops.push_back(InFlag);
1345 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1346 InFlag = Chain.getValue(1);
1348 // Handle result values, copying them out of physregs into vregs that we
1350 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1354 //===----------------------------------------------------------------------===//
1355 // Other Lowering Hooks
1356 //===----------------------------------------------------------------------===//
1359 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1360 if (ReturnAddrIndex == 0) {
1361 // Set up a frame object for the return address.
1362 MachineFunction &MF = DAG.getMachineFunction();
1363 if (Subtarget->is64Bit())
1364 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1366 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1369 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1374 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1375 /// specific condition code. It returns a false if it cannot do a direct
1376 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1378 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1379 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1380 SelectionDAG &DAG) {
1381 X86CC = X86::COND_INVALID;
1383 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1384 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1385 // X > -1 -> X == 0, jump !sign.
1386 RHS = DAG.getConstant(0, RHS.getValueType());
1387 X86CC = X86::COND_NS;
1389 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1390 // X < 0 -> X == 0, jump on sign.
1391 X86CC = X86::COND_S;
1396 switch (SetCCOpcode) {
1398 case ISD::SETEQ: X86CC = X86::COND_E; break;
1399 case ISD::SETGT: X86CC = X86::COND_G; break;
1400 case ISD::SETGE: X86CC = X86::COND_GE; break;
1401 case ISD::SETLT: X86CC = X86::COND_L; break;
1402 case ISD::SETLE: X86CC = X86::COND_LE; break;
1403 case ISD::SETNE: X86CC = X86::COND_NE; break;
1404 case ISD::SETULT: X86CC = X86::COND_B; break;
1405 case ISD::SETUGT: X86CC = X86::COND_A; break;
1406 case ISD::SETULE: X86CC = X86::COND_BE; break;
1407 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1410 // On a floating point condition, the flags are set as follows:
1412 // 0 | 0 | 0 | X > Y
1413 // 0 | 0 | 1 | X < Y
1414 // 1 | 0 | 0 | X == Y
1415 // 1 | 1 | 1 | unordered
1417 switch (SetCCOpcode) {
1420 case ISD::SETEQ: X86CC = X86::COND_E; break;
1421 case ISD::SETOLT: Flip = true; // Fallthrough
1423 case ISD::SETGT: X86CC = X86::COND_A; break;
1424 case ISD::SETOLE: Flip = true; // Fallthrough
1426 case ISD::SETGE: X86CC = X86::COND_AE; break;
1427 case ISD::SETUGT: Flip = true; // Fallthrough
1429 case ISD::SETLT: X86CC = X86::COND_B; break;
1430 case ISD::SETUGE: Flip = true; // Fallthrough
1432 case ISD::SETLE: X86CC = X86::COND_BE; break;
1434 case ISD::SETNE: X86CC = X86::COND_NE; break;
1435 case ISD::SETUO: X86CC = X86::COND_P; break;
1436 case ISD::SETO: X86CC = X86::COND_NP; break;
1439 std::swap(LHS, RHS);
1442 return X86CC != X86::COND_INVALID;
1445 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1446 /// code. Current x86 isa includes the following FP cmov instructions:
1447 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1448 static bool hasFPCMov(unsigned X86CC) {
1464 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1465 /// true if Op is undef or if its value falls within the specified range (L, H].
1466 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1467 if (Op.getOpcode() == ISD::UNDEF)
1470 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1471 return (Val >= Low && Val < Hi);
1474 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1475 /// true if Op is undef or if its value equal to the specified value.
1476 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1477 if (Op.getOpcode() == ISD::UNDEF)
1479 return cast<ConstantSDNode>(Op)->getValue() == Val;
1482 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1483 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1484 bool X86::isPSHUFDMask(SDNode *N) {
1485 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1487 if (N->getNumOperands() != 4)
1490 // Check if the value doesn't reference the second vector.
1491 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1492 SDOperand Arg = N->getOperand(i);
1493 if (Arg.getOpcode() == ISD::UNDEF) continue;
1494 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1495 if (cast<ConstantSDNode>(Arg)->getValue() >= 4)
1502 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
1503 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
1504 bool X86::isPSHUFHWMask(SDNode *N) {
1505 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1507 if (N->getNumOperands() != 8)
1510 // Lower quadword copied in order.
1511 for (unsigned i = 0; i != 4; ++i) {
1512 SDOperand Arg = N->getOperand(i);
1513 if (Arg.getOpcode() == ISD::UNDEF) continue;
1514 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1515 if (cast<ConstantSDNode>(Arg)->getValue() != i)
1519 // Upper quadword shuffled.
1520 for (unsigned i = 4; i != 8; ++i) {
1521 SDOperand Arg = N->getOperand(i);
1522 if (Arg.getOpcode() == ISD::UNDEF) continue;
1523 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1524 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1525 if (Val < 4 || Val > 7)
1532 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
1533 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
1534 bool X86::isPSHUFLWMask(SDNode *N) {
1535 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1537 if (N->getNumOperands() != 8)
1540 // Upper quadword copied in order.
1541 for (unsigned i = 4; i != 8; ++i)
1542 if (!isUndefOrEqual(N->getOperand(i), i))
1545 // Lower quadword shuffled.
1546 for (unsigned i = 0; i != 4; ++i)
1547 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
1553 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1554 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
1555 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
1556 if (NumElems != 2 && NumElems != 4) return false;
1558 unsigned Half = NumElems / 2;
1559 for (unsigned i = 0; i < Half; ++i)
1560 if (!isUndefOrInRange(Elems[i], 0, NumElems))
1562 for (unsigned i = Half; i < NumElems; ++i)
1563 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
1569 bool X86::isSHUFPMask(SDNode *N) {
1570 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1571 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
1574 /// isCommutedSHUFP - Returns true if the shuffle mask is except
1575 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
1576 /// half elements to come from vector 1 (which would equal the dest.) and
1577 /// the upper half to come from vector 2.
1578 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
1579 if (NumOps != 2 && NumOps != 4) return false;
1581 unsigned Half = NumOps / 2;
1582 for (unsigned i = 0; i < Half; ++i)
1583 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
1585 for (unsigned i = Half; i < NumOps; ++i)
1586 if (!isUndefOrInRange(Ops[i], 0, NumOps))
1591 static bool isCommutedSHUFP(SDNode *N) {
1592 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1593 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
1596 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
1597 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
1598 bool X86::isMOVHLPSMask(SDNode *N) {
1599 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1601 if (N->getNumOperands() != 4)
1604 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
1605 return isUndefOrEqual(N->getOperand(0), 6) &&
1606 isUndefOrEqual(N->getOperand(1), 7) &&
1607 isUndefOrEqual(N->getOperand(2), 2) &&
1608 isUndefOrEqual(N->getOperand(3), 3);
1611 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
1612 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
1614 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
1615 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1617 if (N->getNumOperands() != 4)
1620 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
1621 return isUndefOrEqual(N->getOperand(0), 2) &&
1622 isUndefOrEqual(N->getOperand(1), 3) &&
1623 isUndefOrEqual(N->getOperand(2), 2) &&
1624 isUndefOrEqual(N->getOperand(3), 3);
1627 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
1628 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
1629 bool X86::isMOVLPMask(SDNode *N) {
1630 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1632 unsigned NumElems = N->getNumOperands();
1633 if (NumElems != 2 && NumElems != 4)
1636 for (unsigned i = 0; i < NumElems/2; ++i)
1637 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
1640 for (unsigned i = NumElems/2; i < NumElems; ++i)
1641 if (!isUndefOrEqual(N->getOperand(i), i))
1647 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
1648 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
1650 bool X86::isMOVHPMask(SDNode *N) {
1651 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1653 unsigned NumElems = N->getNumOperands();
1654 if (NumElems != 2 && NumElems != 4)
1657 for (unsigned i = 0; i < NumElems/2; ++i)
1658 if (!isUndefOrEqual(N->getOperand(i), i))
1661 for (unsigned i = 0; i < NumElems/2; ++i) {
1662 SDOperand Arg = N->getOperand(i + NumElems/2);
1663 if (!isUndefOrEqual(Arg, i + NumElems))
1670 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
1671 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
1672 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
1673 bool V2IsSplat = false) {
1674 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1677 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1678 SDOperand BitI = Elts[i];
1679 SDOperand BitI1 = Elts[i+1];
1680 if (!isUndefOrEqual(BitI, j))
1683 if (isUndefOrEqual(BitI1, NumElts))
1686 if (!isUndefOrEqual(BitI1, j + NumElts))
1694 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
1695 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1696 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1699 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
1700 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
1701 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
1702 bool V2IsSplat = false) {
1703 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1706 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1707 SDOperand BitI = Elts[i];
1708 SDOperand BitI1 = Elts[i+1];
1709 if (!isUndefOrEqual(BitI, j + NumElts/2))
1712 if (isUndefOrEqual(BitI1, NumElts))
1715 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
1723 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
1724 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1725 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1728 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
1729 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
1731 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
1732 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1734 unsigned NumElems = N->getNumOperands();
1735 if (NumElems != 4 && NumElems != 8 && NumElems != 16)
1738 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
1739 SDOperand BitI = N->getOperand(i);
1740 SDOperand BitI1 = N->getOperand(i+1);
1742 if (!isUndefOrEqual(BitI, j))
1744 if (!isUndefOrEqual(BitI1, j))
1751 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
1752 /// specifies a shuffle of elements that is suitable for input to MOVSS,
1753 /// MOVSD, and MOVD, i.e. setting the lowest element.
1754 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
1755 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1758 if (!isUndefOrEqual(Elts[0], NumElts))
1761 for (unsigned i = 1; i < NumElts; ++i) {
1762 if (!isUndefOrEqual(Elts[i], i))
1769 bool X86::isMOVLMask(SDNode *N) {
1770 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1771 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
1774 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
1775 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
1776 /// element of vector 2 and the other elements to come from vector 1 in order.
1777 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
1778 bool V2IsSplat = false,
1779 bool V2IsUndef = false) {
1780 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
1783 if (!isUndefOrEqual(Ops[0], 0))
1786 for (unsigned i = 1; i < NumOps; ++i) {
1787 SDOperand Arg = Ops[i];
1788 if (!(isUndefOrEqual(Arg, i+NumOps) ||
1789 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
1790 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
1797 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
1798 bool V2IsUndef = false) {
1799 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1800 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
1801 V2IsSplat, V2IsUndef);
1804 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1805 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
1806 bool X86::isMOVSHDUPMask(SDNode *N) {
1807 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1809 if (N->getNumOperands() != 4)
1812 // Expect 1, 1, 3, 3
1813 for (unsigned i = 0; i < 2; ++i) {
1814 SDOperand Arg = N->getOperand(i);
1815 if (Arg.getOpcode() == ISD::UNDEF) continue;
1816 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1817 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1818 if (Val != 1) return false;
1822 for (unsigned i = 2; i < 4; ++i) {
1823 SDOperand Arg = N->getOperand(i);
1824 if (Arg.getOpcode() == ISD::UNDEF) continue;
1825 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1826 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1827 if (Val != 3) return false;
1831 // Don't use movshdup if it can be done with a shufps.
1835 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1836 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
1837 bool X86::isMOVSLDUPMask(SDNode *N) {
1838 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1840 if (N->getNumOperands() != 4)
1843 // Expect 0, 0, 2, 2
1844 for (unsigned i = 0; i < 2; ++i) {
1845 SDOperand Arg = N->getOperand(i);
1846 if (Arg.getOpcode() == ISD::UNDEF) continue;
1847 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1848 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1849 if (Val != 0) return false;
1853 for (unsigned i = 2; i < 4; ++i) {
1854 SDOperand Arg = N->getOperand(i);
1855 if (Arg.getOpcode() == ISD::UNDEF) continue;
1856 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1857 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1858 if (Val != 2) return false;
1862 // Don't use movshdup if it can be done with a shufps.
1866 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
1867 /// a splat of a single element.
1868 static bool isSplatMask(SDNode *N) {
1869 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1871 // This is a splat operation if each element of the permute is the same, and
1872 // if the value doesn't reference the second vector.
1873 unsigned NumElems = N->getNumOperands();
1874 SDOperand ElementBase;
1876 for (; i != NumElems; ++i) {
1877 SDOperand Elt = N->getOperand(i);
1878 if (isa<ConstantSDNode>(Elt)) {
1884 if (!ElementBase.Val)
1887 for (; i != NumElems; ++i) {
1888 SDOperand Arg = N->getOperand(i);
1889 if (Arg.getOpcode() == ISD::UNDEF) continue;
1890 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1891 if (Arg != ElementBase) return false;
1894 // Make sure it is a splat of the first vector operand.
1895 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
1898 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
1899 /// a splat of a single element and it's a 2 or 4 element mask.
1900 bool X86::isSplatMask(SDNode *N) {
1901 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1903 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
1904 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
1906 return ::isSplatMask(N);
1909 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
1910 /// specifies a splat of zero element.
1911 bool X86::isSplatLoMask(SDNode *N) {
1912 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1914 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
1915 if (!isUndefOrEqual(N->getOperand(i), 0))
1920 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
1921 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
1923 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
1924 unsigned NumOperands = N->getNumOperands();
1925 unsigned Shift = (NumOperands == 4) ? 2 : 1;
1927 for (unsigned i = 0; i < NumOperands; ++i) {
1929 SDOperand Arg = N->getOperand(NumOperands-i-1);
1930 if (Arg.getOpcode() != ISD::UNDEF)
1931 Val = cast<ConstantSDNode>(Arg)->getValue();
1932 if (Val >= NumOperands) Val -= NumOperands;
1934 if (i != NumOperands - 1)
1941 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
1942 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
1944 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
1946 // 8 nodes, but we only care about the last 4.
1947 for (unsigned i = 7; i >= 4; --i) {
1949 SDOperand Arg = N->getOperand(i);
1950 if (Arg.getOpcode() != ISD::UNDEF)
1951 Val = cast<ConstantSDNode>(Arg)->getValue();
1960 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
1961 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
1963 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
1965 // 8 nodes, but we only care about the first 4.
1966 for (int i = 3; i >= 0; --i) {
1968 SDOperand Arg = N->getOperand(i);
1969 if (Arg.getOpcode() != ISD::UNDEF)
1970 Val = cast<ConstantSDNode>(Arg)->getValue();
1979 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
1980 /// specifies a 8 element shuffle that can be broken into a pair of
1981 /// PSHUFHW and PSHUFLW.
1982 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
1983 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1985 if (N->getNumOperands() != 8)
1988 // Lower quadword shuffled.
1989 for (unsigned i = 0; i != 4; ++i) {
1990 SDOperand Arg = N->getOperand(i);
1991 if (Arg.getOpcode() == ISD::UNDEF) continue;
1992 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1993 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1998 // Upper quadword shuffled.
1999 for (unsigned i = 4; i != 8; ++i) {
2000 SDOperand Arg = N->getOperand(i);
2001 if (Arg.getOpcode() == ISD::UNDEF) continue;
2002 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2003 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2004 if (Val < 4 || Val > 7)
2011 /// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
2012 /// values in ther permute mask.
2013 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2014 SDOperand &V2, SDOperand &Mask,
2015 SelectionDAG &DAG) {
2016 MVT::ValueType VT = Op.getValueType();
2017 MVT::ValueType MaskVT = Mask.getValueType();
2018 MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT);
2019 unsigned NumElems = Mask.getNumOperands();
2020 SmallVector<SDOperand, 8> MaskVec;
2022 for (unsigned i = 0; i != NumElems; ++i) {
2023 SDOperand Arg = Mask.getOperand(i);
2024 if (Arg.getOpcode() == ISD::UNDEF) {
2025 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2028 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2029 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2031 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2033 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2037 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2038 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2041 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2042 /// match movhlps. The lower half elements should come from upper half of
2043 /// V1 (and in order), and the upper half elements should come from the upper
2044 /// half of V2 (and in order).
2045 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2046 unsigned NumElems = Mask->getNumOperands();
2049 for (unsigned i = 0, e = 2; i != e; ++i)
2050 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2052 for (unsigned i = 2; i != 4; ++i)
2053 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2058 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2059 /// is promoted to a vector.
2060 static inline bool isScalarLoadToVector(SDNode *N) {
2061 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2062 N = N->getOperand(0).Val;
2063 return ISD::isNON_EXTLoad(N);
2068 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2069 /// match movlp{s|d}. The lower half elements should come from lower half of
2070 /// V1 (and in order), and the upper half elements should come from the upper
2071 /// half of V2 (and in order). And since V1 will become the source of the
2072 /// MOVLP, it must be either a vector load or a scalar load to vector.
2073 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2074 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2076 // Is V2 is a vector load, don't do this transformation. We will try to use
2077 // load folding shufps op.
2078 if (ISD::isNON_EXTLoad(V2))
2081 unsigned NumElems = Mask->getNumOperands();
2082 if (NumElems != 2 && NumElems != 4)
2084 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2085 if (!isUndefOrEqual(Mask->getOperand(i), i))
2087 for (unsigned i = NumElems/2; i != NumElems; ++i)
2088 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2093 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2095 static bool isSplatVector(SDNode *N) {
2096 if (N->getOpcode() != ISD::BUILD_VECTOR)
2099 SDOperand SplatValue = N->getOperand(0);
2100 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2101 if (N->getOperand(i) != SplatValue)
2106 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2108 static bool isUndefShuffle(SDNode *N) {
2109 if (N->getOpcode() != ISD::BUILD_VECTOR)
2112 SDOperand V1 = N->getOperand(0);
2113 SDOperand V2 = N->getOperand(1);
2114 SDOperand Mask = N->getOperand(2);
2115 unsigned NumElems = Mask.getNumOperands();
2116 for (unsigned i = 0; i != NumElems; ++i) {
2117 SDOperand Arg = Mask.getOperand(i);
2118 if (Arg.getOpcode() != ISD::UNDEF) {
2119 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2120 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2122 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2129 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2130 /// that point to V2 points to its first element.
2131 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2132 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2134 bool Changed = false;
2135 SmallVector<SDOperand, 8> MaskVec;
2136 unsigned NumElems = Mask.getNumOperands();
2137 for (unsigned i = 0; i != NumElems; ++i) {
2138 SDOperand Arg = Mask.getOperand(i);
2139 if (Arg.getOpcode() != ISD::UNDEF) {
2140 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2141 if (Val > NumElems) {
2142 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2146 MaskVec.push_back(Arg);
2150 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2151 &MaskVec[0], MaskVec.size());
2155 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2156 /// operation of specified width.
2157 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2158 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2159 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2161 SmallVector<SDOperand, 8> MaskVec;
2162 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2163 for (unsigned i = 1; i != NumElems; ++i)
2164 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2165 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2168 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2169 /// of specified width.
2170 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2171 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2172 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2173 SmallVector<SDOperand, 8> MaskVec;
2174 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2175 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2176 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2178 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2181 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2182 /// of specified width.
2183 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2184 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2185 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2186 unsigned Half = NumElems/2;
2187 SmallVector<SDOperand, 8> MaskVec;
2188 for (unsigned i = 0; i != Half; ++i) {
2189 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2190 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2192 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2195 /// getZeroVector - Returns a vector of specified type with all zero elements.
2197 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2198 assert(MVT::isVector(VT) && "Expected a vector type");
2199 unsigned NumElems = getVectorNumElements(VT);
2200 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2201 bool isFP = MVT::isFloatingPoint(EVT);
2202 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
2203 SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero);
2204 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
2207 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2209 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2210 SDOperand V1 = Op.getOperand(0);
2211 SDOperand Mask = Op.getOperand(2);
2212 MVT::ValueType VT = Op.getValueType();
2213 unsigned NumElems = Mask.getNumOperands();
2214 Mask = getUnpacklMask(NumElems, DAG);
2215 while (NumElems != 4) {
2216 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2219 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2221 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2222 Mask = getZeroVector(MaskVT, DAG);
2223 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2224 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2225 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2228 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2230 static inline bool isZeroNode(SDOperand Elt) {
2231 return ((isa<ConstantSDNode>(Elt) &&
2232 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2233 (isa<ConstantFPSDNode>(Elt) &&
2234 cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
2237 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2238 /// vector and zero or undef vector.
2239 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2240 unsigned NumElems, unsigned Idx,
2241 bool isZero, SelectionDAG &DAG) {
2242 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2243 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2244 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
2245 SDOperand Zero = DAG.getConstant(0, EVT);
2246 SmallVector<SDOperand, 8> MaskVec(NumElems, Zero);
2247 MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
2248 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2249 &MaskVec[0], MaskVec.size());
2250 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2253 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2255 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2256 unsigned NumNonZero, unsigned NumZero,
2257 SelectionDAG &DAG, TargetLowering &TLI) {
2263 for (unsigned i = 0; i < 16; ++i) {
2264 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2265 if (ThisIsNonZero && First) {
2267 V = getZeroVector(MVT::v8i16, DAG);
2269 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2274 SDOperand ThisElt(0, 0), LastElt(0, 0);
2275 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2276 if (LastIsNonZero) {
2277 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2279 if (ThisIsNonZero) {
2280 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2281 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2282 ThisElt, DAG.getConstant(8, MVT::i8));
2284 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2289 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2290 DAG.getConstant(i/2, TLI.getPointerTy()));
2294 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2297 /// LowerBuildVectorv16i8 - Custom lower build_vector of v8i16.
2299 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2300 unsigned NumNonZero, unsigned NumZero,
2301 SelectionDAG &DAG, TargetLowering &TLI) {
2307 for (unsigned i = 0; i < 8; ++i) {
2308 bool isNonZero = (NonZeros & (1 << i)) != 0;
2312 V = getZeroVector(MVT::v8i16, DAG);
2314 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2317 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2318 DAG.getConstant(i, TLI.getPointerTy()));
2326 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2327 // All zero's are handled with pxor.
2328 if (ISD::isBuildVectorAllZeros(Op.Val))
2331 // All one's are handled with pcmpeqd.
2332 if (ISD::isBuildVectorAllOnes(Op.Val))
2335 MVT::ValueType VT = Op.getValueType();
2336 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2337 unsigned EVTBits = MVT::getSizeInBits(EVT);
2339 unsigned NumElems = Op.getNumOperands();
2340 unsigned NumZero = 0;
2341 unsigned NumNonZero = 0;
2342 unsigned NonZeros = 0;
2343 std::set<SDOperand> Values;
2344 for (unsigned i = 0; i < NumElems; ++i) {
2345 SDOperand Elt = Op.getOperand(i);
2346 if (Elt.getOpcode() != ISD::UNDEF) {
2348 if (isZeroNode(Elt))
2351 NonZeros |= (1 << i);
2357 if (NumNonZero == 0)
2358 // Must be a mix of zero and undef. Return a zero vector.
2359 return getZeroVector(VT, DAG);
2361 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2362 if (Values.size() == 1)
2365 // Special case for single non-zero element.
2366 if (NumNonZero == 1) {
2367 unsigned Idx = CountTrailingZeros_32(NonZeros);
2368 SDOperand Item = Op.getOperand(Idx);
2369 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2371 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2372 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2375 if (EVTBits == 32) {
2376 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2377 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2379 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2380 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
2381 SmallVector<SDOperand, 8> MaskVec;
2382 for (unsigned i = 0; i < NumElems; i++)
2383 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2384 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2385 &MaskVec[0], MaskVec.size());
2386 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2387 DAG.getNode(ISD::UNDEF, VT), Mask);
2391 // Let legalizer expand 2-wide build_vector's.
2395 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2397 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2399 if (V.Val) return V;
2402 if (EVTBits == 16) {
2403 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2405 if (V.Val) return V;
2408 // If element VT is == 32 bits, turn it into a number of shuffles.
2409 SmallVector<SDOperand, 8> V;
2411 if (NumElems == 4 && NumZero > 0) {
2412 for (unsigned i = 0; i < 4; ++i) {
2413 bool isZero = !(NonZeros & (1 << i));
2415 V[i] = getZeroVector(VT, DAG);
2417 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2420 for (unsigned i = 0; i < 2; ++i) {
2421 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2424 V[i] = V[i*2]; // Must be a zero vector.
2427 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2428 getMOVLMask(NumElems, DAG));
2431 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2432 getMOVLMask(NumElems, DAG));
2435 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2436 getUnpacklMask(NumElems, DAG));
2441 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
2442 // clears the upper bits.
2443 // FIXME: we can do the same for v4f32 case when we know both parts of
2444 // the lower half come from scalar_to_vector (loadf32). We should do
2445 // that in post legalizer dag combiner with target specific hooks.
2446 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2448 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2449 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
2450 SmallVector<SDOperand, 8> MaskVec;
2451 bool Reverse = (NonZeros & 0x3) == 2;
2452 for (unsigned i = 0; i < 2; ++i)
2454 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2456 MaskVec.push_back(DAG.getConstant(i, EVT));
2457 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2458 for (unsigned i = 0; i < 2; ++i)
2460 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2462 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2463 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2464 &MaskVec[0], MaskVec.size());
2465 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2468 if (Values.size() > 2) {
2469 // Expand into a number of unpckl*.
2471 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2472 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2473 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2474 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2475 for (unsigned i = 0; i < NumElems; ++i)
2476 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2478 while (NumElems != 0) {
2479 for (unsigned i = 0; i < NumElems; ++i)
2480 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
2491 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2492 SDOperand V1 = Op.getOperand(0);
2493 SDOperand V2 = Op.getOperand(1);
2494 SDOperand PermMask = Op.getOperand(2);
2495 MVT::ValueType VT = Op.getValueType();
2496 unsigned NumElems = PermMask.getNumOperands();
2497 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
2498 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
2499 bool V1IsSplat = false;
2500 bool V2IsSplat = false;
2502 if (isUndefShuffle(Op.Val))
2503 return DAG.getNode(ISD::UNDEF, VT);
2505 if (isSplatMask(PermMask.Val)) {
2506 if (NumElems <= 4) return Op;
2507 // Promote it to a v4i32 splat.
2508 return PromoteSplat(Op, DAG);
2511 if (X86::isMOVLMask(PermMask.Val))
2512 return (V1IsUndef) ? V2 : Op;
2514 if (X86::isMOVSHDUPMask(PermMask.Val) ||
2515 X86::isMOVSLDUPMask(PermMask.Val) ||
2516 X86::isMOVHLPSMask(PermMask.Val) ||
2517 X86::isMOVHPMask(PermMask.Val) ||
2518 X86::isMOVLPMask(PermMask.Val))
2521 if (ShouldXformToMOVHLPS(PermMask.Val) ||
2522 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
2523 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2525 bool Commuted = false;
2526 V1IsSplat = isSplatVector(V1.Val);
2527 V2IsSplat = isSplatVector(V2.Val);
2528 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
2529 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2530 std::swap(V1IsSplat, V2IsSplat);
2531 std::swap(V1IsUndef, V2IsUndef);
2535 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
2536 if (V2IsUndef) return V1;
2537 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2539 // V2 is a splat, so the mask may be malformed. That is, it may point
2540 // to any V2 element. The instruction selectior won't like this. Get
2541 // a corrected mask and commute to form a proper MOVS{S|D}.
2542 SDOperand NewMask = getMOVLMask(NumElems, DAG);
2543 if (NewMask.Val != PermMask.Val)
2544 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2549 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2550 X86::isUNPCKLMask(PermMask.Val) ||
2551 X86::isUNPCKHMask(PermMask.Val))
2555 // Normalize mask so all entries that point to V2 points to its first
2556 // element then try to match unpck{h|l} again. If match, return a
2557 // new vector_shuffle with the corrected mask.
2558 SDOperand NewMask = NormalizeMask(PermMask, DAG);
2559 if (NewMask.Val != PermMask.Val) {
2560 if (X86::isUNPCKLMask(PermMask.Val, true)) {
2561 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
2562 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2563 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
2564 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
2565 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2570 // Normalize the node to match x86 shuffle ops if needed
2571 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
2572 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2575 // Commute is back and try unpck* again.
2576 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2577 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2578 X86::isUNPCKLMask(PermMask.Val) ||
2579 X86::isUNPCKHMask(PermMask.Val))
2583 // If VT is integer, try PSHUF* first, then SHUFP*.
2584 if (MVT::isInteger(VT)) {
2585 if (X86::isPSHUFDMask(PermMask.Val) ||
2586 X86::isPSHUFHWMask(PermMask.Val) ||
2587 X86::isPSHUFLWMask(PermMask.Val)) {
2588 if (V2.getOpcode() != ISD::UNDEF)
2589 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2590 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2594 if (X86::isSHUFPMask(PermMask.Val))
2597 // Handle v8i16 shuffle high / low shuffle node pair.
2598 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
2599 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2600 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2601 SmallVector<SDOperand, 8> MaskVec;
2602 for (unsigned i = 0; i != 4; ++i)
2603 MaskVec.push_back(PermMask.getOperand(i));
2604 for (unsigned i = 4; i != 8; ++i)
2605 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2606 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2607 &MaskVec[0], MaskVec.size());
2608 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2610 for (unsigned i = 0; i != 4; ++i)
2611 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2612 for (unsigned i = 4; i != 8; ++i)
2613 MaskVec.push_back(PermMask.getOperand(i));
2614 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size());
2615 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2618 // Floating point cases in the other order.
2619 if (X86::isSHUFPMask(PermMask.Val))
2621 if (X86::isPSHUFDMask(PermMask.Val) ||
2622 X86::isPSHUFHWMask(PermMask.Val) ||
2623 X86::isPSHUFLWMask(PermMask.Val)) {
2624 if (V2.getOpcode() != ISD::UNDEF)
2625 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2626 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2631 if (NumElems == 4) {
2632 MVT::ValueType MaskVT = PermMask.getValueType();
2633 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
2634 SmallVector<std::pair<int, int>, 8> Locs;
2635 Locs.reserve(NumElems);
2636 SmallVector<SDOperand, 8> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2637 SmallVector<SDOperand, 8> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2640 // If no more than two elements come from either vector. This can be
2641 // implemented with two shuffles. First shuffle gather the elements.
2642 // The second shuffle, which takes the first shuffle as both of its
2643 // vector operands, put the elements into the right order.
2644 for (unsigned i = 0; i != NumElems; ++i) {
2645 SDOperand Elt = PermMask.getOperand(i);
2646 if (Elt.getOpcode() == ISD::UNDEF) {
2647 Locs[i] = std::make_pair(-1, -1);
2649 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
2650 if (Val < NumElems) {
2651 Locs[i] = std::make_pair(0, NumLo);
2655 Locs[i] = std::make_pair(1, NumHi);
2656 if (2+NumHi < NumElems)
2657 Mask1[2+NumHi] = Elt;
2662 if (NumLo <= 2 && NumHi <= 2) {
2663 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2664 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2665 &Mask1[0], Mask1.size()));
2666 for (unsigned i = 0; i != NumElems; ++i) {
2667 if (Locs[i].first == -1)
2670 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
2671 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
2672 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
2676 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
2677 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2678 &Mask2[0], Mask2.size()));
2681 // Break it into (shuffle shuffle_hi, shuffle_lo).
2683 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2684 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2685 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
2686 unsigned MaskIdx = 0;
2688 unsigned HiIdx = NumElems/2;
2689 for (unsigned i = 0; i != NumElems; ++i) {
2690 if (i == NumElems/2) {
2696 SDOperand Elt = PermMask.getOperand(i);
2697 if (Elt.getOpcode() == ISD::UNDEF) {
2698 Locs[i] = std::make_pair(-1, -1);
2699 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
2700 Locs[i] = std::make_pair(MaskIdx, LoIdx);
2701 (*MaskPtr)[LoIdx] = Elt;
2704 Locs[i] = std::make_pair(MaskIdx, HiIdx);
2705 (*MaskPtr)[HiIdx] = Elt;
2710 SDOperand LoShuffle =
2711 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2712 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2713 &LoMask[0], LoMask.size()));
2714 SDOperand HiShuffle =
2715 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2716 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2717 &HiMask[0], HiMask.size()));
2718 SmallVector<SDOperand, 8> MaskOps;
2719 for (unsigned i = 0; i != NumElems; ++i) {
2720 if (Locs[i].first == -1) {
2721 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
2723 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
2724 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
2727 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
2728 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2729 &MaskOps[0], MaskOps.size()));
2736 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2737 if (!isa<ConstantSDNode>(Op.getOperand(1)))
2740 MVT::ValueType VT = Op.getValueType();
2741 // TODO: handle v16i8.
2742 if (MVT::getSizeInBits(VT) == 16) {
2743 // Transform it so it match pextrw which produces a 32-bit result.
2744 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
2745 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
2746 Op.getOperand(0), Op.getOperand(1));
2747 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
2748 DAG.getValueType(VT));
2749 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
2750 } else if (MVT::getSizeInBits(VT) == 32) {
2751 SDOperand Vec = Op.getOperand(0);
2752 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2755 // SHUFPS the element to the lowest double word, then movss.
2756 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2757 SmallVector<SDOperand, 8> IdxVec;
2758 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT)));
2759 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2760 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2761 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2762 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2763 &IdxVec[0], IdxVec.size());
2764 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
2765 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
2766 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
2767 DAG.getConstant(0, getPointerTy()));
2768 } else if (MVT::getSizeInBits(VT) == 64) {
2769 SDOperand Vec = Op.getOperand(0);
2770 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2774 // UNPCKHPD the element to the lowest double word, then movsd.
2775 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
2776 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
2777 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2778 SmallVector<SDOperand, 8> IdxVec;
2779 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT)));
2780 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2781 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2782 &IdxVec[0], IdxVec.size());
2783 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
2784 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
2785 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
2786 DAG.getConstant(0, getPointerTy()));
2793 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2794 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
2795 // as its second argument.
2796 MVT::ValueType VT = Op.getValueType();
2797 MVT::ValueType BaseVT = MVT::getVectorBaseType(VT);
2798 SDOperand N0 = Op.getOperand(0);
2799 SDOperand N1 = Op.getOperand(1);
2800 SDOperand N2 = Op.getOperand(2);
2801 if (MVT::getSizeInBits(BaseVT) == 16) {
2802 if (N1.getValueType() != MVT::i32)
2803 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
2804 if (N2.getValueType() != MVT::i32)
2805 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
2806 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
2807 } else if (MVT::getSizeInBits(BaseVT) == 32) {
2808 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
2811 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
2812 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2813 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2814 SmallVector<SDOperand, 8> MaskVec;
2815 MaskVec.push_back(DAG.getConstant(4, BaseVT));
2816 for (unsigned i = 1; i <= 3; ++i)
2817 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2818 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
2819 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2820 &MaskVec[0], MaskVec.size()));
2822 // Use two pinsrw instructions to insert a 32 bit value.
2824 if (MVT::isFloatingPoint(N1.getValueType())) {
2825 if (ISD::isNON_EXTLoad(N1.Val)) {
2826 // Just load directly from f32mem to GR32.
2827 LoadSDNode *LD = cast<LoadSDNode>(N1);
2828 N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(),
2829 LD->getSrcValue(), LD->getSrcValueOffset());
2831 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
2832 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
2833 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
2834 DAG.getConstant(0, getPointerTy()));
2837 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
2838 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
2839 DAG.getConstant(Idx, getPointerTy()));
2840 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
2841 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
2842 DAG.getConstant(Idx+1, getPointerTy()));
2843 return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2851 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2852 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
2853 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
2856 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2857 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
2858 // one of the above mentioned nodes. It has to be wrapped because otherwise
2859 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2860 // be used to form addressing mode. These wrapped nodes will be selected
2863 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
2864 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2865 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
2867 CP->getAlignment());
2868 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
2869 // With PIC, the address is actually $g + Offset.
2870 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2871 !Subtarget->isPICStyleRIPRel()) {
2872 Result = DAG.getNode(ISD::ADD, getPointerTy(),
2873 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
2881 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
2882 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2883 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
2884 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
2885 // With PIC, the address is actually $g + Offset.
2886 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2887 !Subtarget->isPICStyleRIPRel()) {
2888 Result = DAG.getNode(ISD::ADD, getPointerTy(),
2889 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
2893 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
2894 // load the value at address GV, not the value of GV itself. This means that
2895 // the GlobalAddress must be in the base or index register of the address, not
2896 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
2897 // The same applies for external symbols during PIC codegen
2898 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
2899 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
2905 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
2906 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
2907 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
2908 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
2909 // With PIC, the address is actually $g + Offset.
2910 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2911 !Subtarget->isPICStyleRIPRel()) {
2912 Result = DAG.getNode(ISD::ADD, getPointerTy(),
2913 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
2920 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
2921 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2922 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
2923 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
2924 // With PIC, the address is actually $g + Offset.
2925 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2926 !Subtarget->isPICStyleRIPRel()) {
2927 Result = DAG.getNode(ISD::ADD, getPointerTy(),
2928 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
2935 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
2936 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2937 "Not an i64 shift!");
2938 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
2939 SDOperand ShOpLo = Op.getOperand(0);
2940 SDOperand ShOpHi = Op.getOperand(1);
2941 SDOperand ShAmt = Op.getOperand(2);
2942 SDOperand Tmp1 = isSRA ?
2943 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
2944 DAG.getConstant(0, MVT::i32);
2946 SDOperand Tmp2, Tmp3;
2947 if (Op.getOpcode() == ISD::SHL_PARTS) {
2948 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
2949 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
2951 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
2952 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
2955 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
2956 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
2957 DAG.getConstant(32, MVT::i8));
2958 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
2959 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
2962 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
2964 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
2965 SmallVector<SDOperand, 4> Ops;
2966 if (Op.getOpcode() == ISD::SHL_PARTS) {
2967 Ops.push_back(Tmp2);
2968 Ops.push_back(Tmp3);
2970 Ops.push_back(InFlag);
2971 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
2972 InFlag = Hi.getValue(1);
2975 Ops.push_back(Tmp3);
2976 Ops.push_back(Tmp1);
2978 Ops.push_back(InFlag);
2979 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
2981 Ops.push_back(Tmp2);
2982 Ops.push_back(Tmp3);
2984 Ops.push_back(InFlag);
2985 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
2986 InFlag = Lo.getValue(1);
2989 Ops.push_back(Tmp3);
2990 Ops.push_back(Tmp1);
2992 Ops.push_back(InFlag);
2993 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
2996 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3000 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3003 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3004 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3005 Op.getOperand(0).getValueType() >= MVT::i16 &&
3006 "Unknown SINT_TO_FP to lower!");
3009 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3010 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3011 MachineFunction &MF = DAG.getMachineFunction();
3012 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3013 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3014 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3015 StackSlot, NULL, 0);
3020 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3022 Tys = DAG.getVTList(MVT::f64, MVT::Other);
3023 SmallVector<SDOperand, 8> Ops;
3024 Ops.push_back(Chain);
3025 Ops.push_back(StackSlot);
3026 Ops.push_back(DAG.getValueType(SrcVT));
3027 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3028 Tys, &Ops[0], Ops.size());
3031 Chain = Result.getValue(1);
3032 SDOperand InFlag = Result.getValue(2);
3034 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3035 // shouldn't be necessary except that RFP cannot be live across
3036 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3037 MachineFunction &MF = DAG.getMachineFunction();
3038 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3039 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3040 Tys = DAG.getVTList(MVT::Other);
3041 SmallVector<SDOperand, 8> Ops;
3042 Ops.push_back(Chain);
3043 Ops.push_back(Result);
3044 Ops.push_back(StackSlot);
3045 Ops.push_back(DAG.getValueType(Op.getValueType()));
3046 Ops.push_back(InFlag);
3047 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3048 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3054 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3055 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3056 "Unknown FP_TO_SINT to lower!");
3057 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3059 MachineFunction &MF = DAG.getMachineFunction();
3060 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3061 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3062 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3065 switch (Op.getValueType()) {
3066 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3067 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3068 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3069 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3072 SDOperand Chain = DAG.getEntryNode();
3073 SDOperand Value = Op.getOperand(0);
3075 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3076 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3077 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
3079 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3081 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
3082 Chain = Value.getValue(1);
3083 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3084 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3087 // Build the FP_TO_INT*_IN_MEM
3088 SDOperand Ops[] = { Chain, Value, StackSlot };
3089 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
3092 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3095 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3096 MVT::ValueType VT = Op.getValueType();
3097 const Type *OpNTy = MVT::getTypeForValueType(VT);
3098 std::vector<Constant*> CV;
3099 if (VT == MVT::f64) {
3100 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
3101 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3103 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
3104 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3105 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3106 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3108 Constant *CS = ConstantStruct::get(CV);
3109 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3110 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3111 SmallVector<SDOperand, 3> Ops;
3112 Ops.push_back(DAG.getEntryNode());
3113 Ops.push_back(CPIdx);
3114 Ops.push_back(DAG.getSrcValue(NULL));
3115 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3116 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
3119 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
3120 MVT::ValueType VT = Op.getValueType();
3121 const Type *OpNTy = MVT::getTypeForValueType(VT);
3122 std::vector<Constant*> CV;
3123 if (VT == MVT::f64) {
3124 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
3125 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3127 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
3128 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3129 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3130 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3132 Constant *CS = ConstantStruct::get(CV);
3133 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3134 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3135 SmallVector<SDOperand, 3> Ops;
3136 Ops.push_back(DAG.getEntryNode());
3137 Ops.push_back(CPIdx);
3138 Ops.push_back(DAG.getSrcValue(NULL));
3139 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3140 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
3143 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
3144 SDOperand Op0 = Op.getOperand(0);
3145 SDOperand Op1 = Op.getOperand(1);
3146 MVT::ValueType VT = Op.getValueType();
3147 MVT::ValueType SrcVT = Op1.getValueType();
3148 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
3150 // If second operand is smaller, extend it first.
3151 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
3152 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
3156 // First get the sign bit of second operand.
3157 std::vector<Constant*> CV;
3158 if (SrcVT == MVT::f64) {
3159 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(1ULL << 63)));
3160 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3162 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(1U << 31)));
3163 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3164 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3165 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3167 Constant *CS = ConstantStruct::get(CV);
3168 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3169 SDVTList Tys = DAG.getVTList(SrcVT, MVT::Other);
3170 SmallVector<SDOperand, 3> Ops;
3171 Ops.push_back(DAG.getEntryNode());
3172 Ops.push_back(CPIdx);
3173 Ops.push_back(DAG.getSrcValue(NULL));
3174 SDOperand Mask1 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3175 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
3177 // Shift sign bit right or left if the two operands have different types.
3178 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
3179 // Op0 is MVT::f32, Op1 is MVT::f64.
3180 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
3181 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
3182 DAG.getConstant(32, MVT::i32));
3183 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
3184 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
3185 DAG.getConstant(0, getPointerTy()));
3188 // Clear first operand sign bit.
3190 if (VT == MVT::f64) {
3191 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(~(1ULL << 63))));
3192 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3194 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(~(1U << 31))));
3195 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3196 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3197 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3199 CS = ConstantStruct::get(CV);
3200 CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3201 Tys = DAG.getVTList(VT, MVT::Other);
3203 Ops.push_back(DAG.getEntryNode());
3204 Ops.push_back(CPIdx);
3205 Ops.push_back(DAG.getSrcValue(NULL));
3206 SDOperand Mask2 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3207 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
3209 // Or the value with the sign bit.
3210 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
3213 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
3215 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
3217 SDOperand Op0 = Op.getOperand(0);
3218 SDOperand Op1 = Op.getOperand(1);
3219 SDOperand CC = Op.getOperand(2);
3220 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3221 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3222 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
3223 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
3226 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
3228 SDOperand Ops1[] = { Chain, Op0, Op1 };
3229 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
3230 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
3231 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3234 assert(isFP && "Illegal integer SetCC!");
3236 SDOperand COps[] = { Chain, Op0, Op1 };
3237 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
3239 switch (SetCCOpcode) {
3240 default: assert(false && "Illegal floating point SetCC!");
3241 case ISD::SETOEQ: { // !PF & ZF
3242 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
3243 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3244 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
3246 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3247 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
3249 case ISD::SETUNE: { // PF | !ZF
3250 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
3251 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3252 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
3254 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3255 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
3260 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
3261 bool addTest = true;
3262 SDOperand Chain = DAG.getEntryNode();
3263 SDOperand Cond = Op.getOperand(0);
3265 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3267 if (Cond.getOpcode() == ISD::SETCC)
3268 Cond = LowerSETCC(Cond, DAG, Chain);
3270 if (Cond.getOpcode() == X86ISD::SETCC) {
3271 CC = Cond.getOperand(0);
3273 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3274 // (since flag operand cannot be shared). Use it as the condition setting
3275 // operand in place of the X86ISD::SETCC.
3276 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3277 // to use a test instead of duplicating the X86ISD::CMP (for register
3278 // pressure reason)?
3279 SDOperand Cmp = Cond.getOperand(1);
3280 unsigned Opc = Cmp.getOpcode();
3281 bool IllegalFPCMov = !X86ScalarSSE &&
3282 MVT::isFloatingPoint(Op.getValueType()) &&
3283 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
3284 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
3286 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3287 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3293 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3294 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3295 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3298 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
3299 SmallVector<SDOperand, 4> Ops;
3300 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
3301 // condition is true.
3302 Ops.push_back(Op.getOperand(2));
3303 Ops.push_back(Op.getOperand(1));
3305 Ops.push_back(Cond.getValue(1));
3306 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3309 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
3310 bool addTest = true;
3311 SDOperand Chain = Op.getOperand(0);
3312 SDOperand Cond = Op.getOperand(1);
3313 SDOperand Dest = Op.getOperand(2);
3315 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3317 if (Cond.getOpcode() == ISD::SETCC)
3318 Cond = LowerSETCC(Cond, DAG, Chain);
3320 if (Cond.getOpcode() == X86ISD::SETCC) {
3321 CC = Cond.getOperand(0);
3323 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3324 // (since flag operand cannot be shared). Use it as the condition setting
3325 // operand in place of the X86ISD::SETCC.
3326 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3327 // to use a test instead of duplicating the X86ISD::CMP (for register
3328 // pressure reason)?
3329 SDOperand Cmp = Cond.getOperand(1);
3330 unsigned Opc = Cmp.getOpcode();
3331 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
3332 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3333 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3339 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3340 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3341 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3343 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
3344 Cond, Op.getOperand(2), CC, Cond.getValue(1));
3347 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
3348 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3350 if (Subtarget->is64Bit())
3351 return LowerX86_64CCCCallTo(Op, DAG, CallingConv);
3353 switch (CallingConv) {
3355 assert(0 && "Unsupported calling convention");
3356 case CallingConv::Fast:
3357 // TODO: Implement fastcc
3359 case CallingConv::C:
3360 case CallingConv::X86_StdCall:
3361 return LowerCCCCallTo(Op, DAG, CallingConv);
3362 case CallingConv::X86_FastCall:
3363 return LowerFastCCCallTo(Op, DAG, CallingConv);
3368 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
3369 MachineFunction &MF = DAG.getMachineFunction();
3370 const Function* Fn = MF.getFunction();
3371 if (Fn->hasExternalLinkage() &&
3372 Subtarget->isTargetCygMing() &&
3373 Fn->getName() == "main")
3374 MF.getInfo<X86FunctionInfo>()->setForceFramePointer(true);
3376 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3377 if (Subtarget->is64Bit())
3378 return LowerX86_64CCCArguments(Op, DAG);
3382 assert(0 && "Unsupported calling convention");
3383 case CallingConv::Fast:
3384 // TODO: implement fastcc.
3387 case CallingConv::C:
3388 return LowerCCCArguments(Op, DAG);
3389 case CallingConv::X86_StdCall:
3390 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(StdCall);
3391 return LowerCCCArguments(Op, DAG, true);
3392 case CallingConv::X86_FastCall:
3393 MF.getInfo<X86FunctionInfo>()->setDecorationStyle(FastCall);
3394 return LowerFastCCArguments(Op, DAG);
3398 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
3399 SDOperand InFlag(0, 0);
3400 SDOperand Chain = Op.getOperand(0);
3402 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3403 if (Align == 0) Align = 1;
3405 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3406 // If not DWORD aligned, call memset if size is less than the threshold.
3407 // It knows how to align to the right boundary first.
3408 if ((Align & 3) != 0 ||
3409 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3410 MVT::ValueType IntPtr = getPointerTy();
3411 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3412 TargetLowering::ArgListTy Args;
3413 TargetLowering::ArgListEntry Entry;
3414 Entry.Node = Op.getOperand(1);
3415 Entry.Ty = IntPtrTy;
3416 Args.push_back(Entry);
3417 // Extend the unsigned i8 argument to be an int value for the call.
3418 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
3419 Entry.Ty = IntPtrTy;
3420 Args.push_back(Entry);
3421 Entry.Node = Op.getOperand(3);
3422 Args.push_back(Entry);
3423 std::pair<SDOperand,SDOperand> CallResult =
3424 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3425 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
3426 return CallResult.second;
3431 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3432 unsigned BytesLeft = 0;
3433 bool TwoRepStos = false;
3436 uint64_t Val = ValC->getValue() & 255;
3438 // If the value is a constant, then we can potentially use larger sets.
3439 switch (Align & 3) {
3440 case 2: // WORD aligned
3443 Val = (Val << 8) | Val;
3445 case 0: // DWORD aligned
3448 Val = (Val << 8) | Val;
3449 Val = (Val << 16) | Val;
3450 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
3453 Val = (Val << 32) | Val;
3456 default: // Byte aligned
3459 Count = Op.getOperand(3);
3463 if (AVT > MVT::i8) {
3465 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3466 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3467 BytesLeft = I->getValue() % UBytes;
3469 assert(AVT >= MVT::i32 &&
3470 "Do not use rep;stos if not at least DWORD aligned");
3471 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3472 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3477 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
3479 InFlag = Chain.getValue(1);
3482 Count = Op.getOperand(3);
3483 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
3484 InFlag = Chain.getValue(1);
3487 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3489 InFlag = Chain.getValue(1);
3490 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3491 Op.getOperand(1), InFlag);
3492 InFlag = Chain.getValue(1);
3494 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3495 SmallVector<SDOperand, 8> Ops;
3496 Ops.push_back(Chain);
3497 Ops.push_back(DAG.getValueType(AVT));
3498 Ops.push_back(InFlag);
3499 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3502 InFlag = Chain.getValue(1);
3503 Count = Op.getOperand(3);
3504 MVT::ValueType CVT = Count.getValueType();
3505 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3506 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3507 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
3509 InFlag = Chain.getValue(1);
3510 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3512 Ops.push_back(Chain);
3513 Ops.push_back(DAG.getValueType(MVT::i8));
3514 Ops.push_back(InFlag);
3515 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3516 } else if (BytesLeft) {
3517 // Issue stores for the last 1 - 7 bytes.
3519 unsigned Val = ValC->getValue() & 255;
3520 unsigned Offset = I->getValue() - BytesLeft;
3521 SDOperand DstAddr = Op.getOperand(1);
3522 MVT::ValueType AddrVT = DstAddr.getValueType();
3523 if (BytesLeft >= 4) {
3524 Val = (Val << 8) | Val;
3525 Val = (Val << 16) | Val;
3526 Value = DAG.getConstant(Val, MVT::i32);
3527 Chain = DAG.getStore(Chain, Value,
3528 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3529 DAG.getConstant(Offset, AddrVT)),
3534 if (BytesLeft >= 2) {
3535 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
3536 Chain = DAG.getStore(Chain, Value,
3537 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3538 DAG.getConstant(Offset, AddrVT)),
3543 if (BytesLeft == 1) {
3544 Value = DAG.getConstant(Val, MVT::i8);
3545 Chain = DAG.getStore(Chain, Value,
3546 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3547 DAG.getConstant(Offset, AddrVT)),
3555 SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
3556 SDOperand Chain = Op.getOperand(0);
3558 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3559 if (Align == 0) Align = 1;
3561 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3562 // If not DWORD aligned, call memcpy if size is less than the threshold.
3563 // It knows how to align to the right boundary first.
3564 if ((Align & 3) != 0 ||
3565 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3566 MVT::ValueType IntPtr = getPointerTy();
3567 TargetLowering::ArgListTy Args;
3568 TargetLowering::ArgListEntry Entry;
3569 Entry.Ty = getTargetData()->getIntPtrType();
3570 Entry.Node = Op.getOperand(1); Args.push_back(Entry);
3571 Entry.Node = Op.getOperand(2); Args.push_back(Entry);
3572 Entry.Node = Op.getOperand(3); Args.push_back(Entry);
3573 std::pair<SDOperand,SDOperand> CallResult =
3574 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3575 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
3576 return CallResult.second;
3581 unsigned BytesLeft = 0;
3582 bool TwoRepMovs = false;
3583 switch (Align & 3) {
3584 case 2: // WORD aligned
3587 case 0: // DWORD aligned
3589 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
3592 default: // Byte aligned
3594 Count = Op.getOperand(3);
3598 if (AVT > MVT::i8) {
3600 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3601 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3602 BytesLeft = I->getValue() % UBytes;
3604 assert(AVT >= MVT::i32 &&
3605 "Do not use rep;movs if not at least DWORD aligned");
3606 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3607 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3612 SDOperand InFlag(0, 0);
3613 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3615 InFlag = Chain.getValue(1);
3616 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3617 Op.getOperand(1), InFlag);
3618 InFlag = Chain.getValue(1);
3619 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
3620 Op.getOperand(2), InFlag);
3621 InFlag = Chain.getValue(1);
3623 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3624 SmallVector<SDOperand, 8> Ops;
3625 Ops.push_back(Chain);
3626 Ops.push_back(DAG.getValueType(AVT));
3627 Ops.push_back(InFlag);
3628 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
3631 InFlag = Chain.getValue(1);
3632 Count = Op.getOperand(3);
3633 MVT::ValueType CVT = Count.getValueType();
3634 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3635 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3636 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
3638 InFlag = Chain.getValue(1);
3639 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3641 Ops.push_back(Chain);
3642 Ops.push_back(DAG.getValueType(MVT::i8));
3643 Ops.push_back(InFlag);
3644 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
3645 } else if (BytesLeft) {
3646 // Issue loads and stores for the last 1 - 7 bytes.
3647 unsigned Offset = I->getValue() - BytesLeft;
3648 SDOperand DstAddr = Op.getOperand(1);
3649 MVT::ValueType DstVT = DstAddr.getValueType();
3650 SDOperand SrcAddr = Op.getOperand(2);
3651 MVT::ValueType SrcVT = SrcAddr.getValueType();
3653 if (BytesLeft >= 4) {
3654 Value = DAG.getLoad(MVT::i32, Chain,
3655 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3656 DAG.getConstant(Offset, SrcVT)),
3658 Chain = Value.getValue(1);
3659 Chain = DAG.getStore(Chain, Value,
3660 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3661 DAG.getConstant(Offset, DstVT)),
3666 if (BytesLeft >= 2) {
3667 Value = DAG.getLoad(MVT::i16, Chain,
3668 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3669 DAG.getConstant(Offset, SrcVT)),
3671 Chain = Value.getValue(1);
3672 Chain = DAG.getStore(Chain, Value,
3673 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3674 DAG.getConstant(Offset, DstVT)),
3680 if (BytesLeft == 1) {
3681 Value = DAG.getLoad(MVT::i8, Chain,
3682 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3683 DAG.getConstant(Offset, SrcVT)),
3685 Chain = Value.getValue(1);
3686 Chain = DAG.getStore(Chain, Value,
3687 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3688 DAG.getConstant(Offset, DstVT)),
3697 X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
3698 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3699 SDOperand TheOp = Op.getOperand(0);
3700 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheOp, 1);
3701 if (Subtarget->is64Bit()) {
3702 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
3703 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX,
3704 MVT::i64, Copy1.getValue(2));
3705 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2,
3706 DAG.getConstant(32, MVT::i8));
3708 DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp), Copy2.getValue(1)
3711 Tys = DAG.getVTList(MVT::i64, MVT::Other);
3712 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
3715 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
3716 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX,
3717 MVT::i32, Copy1.getValue(2));
3718 SDOperand Ops[] = { Copy1, Copy2, Copy2.getValue(1) };
3719 Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
3720 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 3);
3723 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
3724 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
3726 if (!Subtarget->is64Bit()) {
3727 // vastart just stores the address of the VarArgsFrameIndex slot into the
3728 // memory location argument.
3729 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
3730 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
3735 // gp_offset (0 - 6 * 8)
3736 // fp_offset (48 - 48 + 8 * 16)
3737 // overflow_arg_area (point to parameters coming in memory).
3739 SmallVector<SDOperand, 8> MemOps;
3740 SDOperand FIN = Op.getOperand(1);
3742 SDOperand Store = DAG.getStore(Op.getOperand(0),
3743 DAG.getConstant(VarArgsGPOffset, MVT::i32),
3744 FIN, SV->getValue(), SV->getOffset());
3745 MemOps.push_back(Store);
3748 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
3749 DAG.getConstant(4, getPointerTy()));
3750 Store = DAG.getStore(Op.getOperand(0),
3751 DAG.getConstant(VarArgsFPOffset, MVT::i32),
3752 FIN, SV->getValue(), SV->getOffset());
3753 MemOps.push_back(Store);
3755 // Store ptr to overflow_arg_area
3756 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
3757 DAG.getConstant(4, getPointerTy()));
3758 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
3759 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
3761 MemOps.push_back(Store);
3763 // Store ptr to reg_save_area.
3764 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
3765 DAG.getConstant(8, getPointerTy()));
3766 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
3767 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
3769 MemOps.push_back(Store);
3770 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
3773 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
3774 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
3775 SDOperand Chain = Op.getOperand(0);
3776 SDOperand DstPtr = Op.getOperand(1);
3777 SDOperand SrcPtr = Op.getOperand(2);
3778 SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3));
3779 SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4));
3781 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
3782 SrcSV->getValue(), SrcSV->getOffset());
3783 Chain = SrcPtr.getValue(1);
3784 for (unsigned i = 0; i < 3; ++i) {
3785 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
3786 SrcSV->getValue(), SrcSV->getOffset());
3787 Chain = Val.getValue(1);
3788 Chain = DAG.getStore(Chain, Val, DstPtr,
3789 DstSV->getValue(), DstSV->getOffset());
3792 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
3793 DAG.getConstant(8, getPointerTy()));
3794 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
3795 DAG.getConstant(8, getPointerTy()));
3801 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
3802 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
3804 default: return SDOperand(); // Don't custom lower most intrinsics.
3805 // Comparison intrinsics.
3806 case Intrinsic::x86_sse_comieq_ss:
3807 case Intrinsic::x86_sse_comilt_ss:
3808 case Intrinsic::x86_sse_comile_ss:
3809 case Intrinsic::x86_sse_comigt_ss:
3810 case Intrinsic::x86_sse_comige_ss:
3811 case Intrinsic::x86_sse_comineq_ss:
3812 case Intrinsic::x86_sse_ucomieq_ss:
3813 case Intrinsic::x86_sse_ucomilt_ss:
3814 case Intrinsic::x86_sse_ucomile_ss:
3815 case Intrinsic::x86_sse_ucomigt_ss:
3816 case Intrinsic::x86_sse_ucomige_ss:
3817 case Intrinsic::x86_sse_ucomineq_ss:
3818 case Intrinsic::x86_sse2_comieq_sd:
3819 case Intrinsic::x86_sse2_comilt_sd:
3820 case Intrinsic::x86_sse2_comile_sd:
3821 case Intrinsic::x86_sse2_comigt_sd:
3822 case Intrinsic::x86_sse2_comige_sd:
3823 case Intrinsic::x86_sse2_comineq_sd:
3824 case Intrinsic::x86_sse2_ucomieq_sd:
3825 case Intrinsic::x86_sse2_ucomilt_sd:
3826 case Intrinsic::x86_sse2_ucomile_sd:
3827 case Intrinsic::x86_sse2_ucomigt_sd:
3828 case Intrinsic::x86_sse2_ucomige_sd:
3829 case Intrinsic::x86_sse2_ucomineq_sd: {
3831 ISD::CondCode CC = ISD::SETCC_INVALID;
3834 case Intrinsic::x86_sse_comieq_ss:
3835 case Intrinsic::x86_sse2_comieq_sd:
3839 case Intrinsic::x86_sse_comilt_ss:
3840 case Intrinsic::x86_sse2_comilt_sd:
3844 case Intrinsic::x86_sse_comile_ss:
3845 case Intrinsic::x86_sse2_comile_sd:
3849 case Intrinsic::x86_sse_comigt_ss:
3850 case Intrinsic::x86_sse2_comigt_sd:
3854 case Intrinsic::x86_sse_comige_ss:
3855 case Intrinsic::x86_sse2_comige_sd:
3859 case Intrinsic::x86_sse_comineq_ss:
3860 case Intrinsic::x86_sse2_comineq_sd:
3864 case Intrinsic::x86_sse_ucomieq_ss:
3865 case Intrinsic::x86_sse2_ucomieq_sd:
3866 Opc = X86ISD::UCOMI;
3869 case Intrinsic::x86_sse_ucomilt_ss:
3870 case Intrinsic::x86_sse2_ucomilt_sd:
3871 Opc = X86ISD::UCOMI;
3874 case Intrinsic::x86_sse_ucomile_ss:
3875 case Intrinsic::x86_sse2_ucomile_sd:
3876 Opc = X86ISD::UCOMI;
3879 case Intrinsic::x86_sse_ucomigt_ss:
3880 case Intrinsic::x86_sse2_ucomigt_sd:
3881 Opc = X86ISD::UCOMI;
3884 case Intrinsic::x86_sse_ucomige_ss:
3885 case Intrinsic::x86_sse2_ucomige_sd:
3886 Opc = X86ISD::UCOMI;
3889 case Intrinsic::x86_sse_ucomineq_ss:
3890 case Intrinsic::x86_sse2_ucomineq_sd:
3891 Opc = X86ISD::UCOMI;
3897 SDOperand LHS = Op.getOperand(1);
3898 SDOperand RHS = Op.getOperand(2);
3899 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
3901 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3902 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
3903 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
3904 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
3905 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
3906 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
3907 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
3912 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
3913 // Depths > 0 not supported yet!
3914 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3917 // Just load the return address
3918 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
3919 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
3922 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
3923 // Depths > 0 not supported yet!
3924 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3927 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
3928 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
3929 DAG.getConstant(4, getPointerTy()));
3932 /// LowerOperation - Provide custom lowering hooks for some operations.
3934 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3935 switch (Op.getOpcode()) {
3936 default: assert(0 && "Should not custom lower this!");
3937 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3938 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3939 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3940 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
3941 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3942 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3943 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3944 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
3945 case ISD::SHL_PARTS:
3946 case ISD::SRA_PARTS:
3947 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
3948 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3949 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3950 case ISD::FABS: return LowerFABS(Op, DAG);
3951 case ISD::FNEG: return LowerFNEG(Op, DAG);
3952 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3953 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode());
3954 case ISD::SELECT: return LowerSELECT(Op, DAG);
3955 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
3956 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3957 case ISD::CALL: return LowerCALL(Op, DAG);
3958 case ISD::RET: return LowerRET(Op, DAG);
3959 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
3960 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
3961 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
3962 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
3963 case ISD::VASTART: return LowerVASTART(Op, DAG);
3964 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
3965 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3966 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3967 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3972 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
3974 default: return NULL;
3975 case X86ISD::SHLD: return "X86ISD::SHLD";
3976 case X86ISD::SHRD: return "X86ISD::SHRD";
3977 case X86ISD::FAND: return "X86ISD::FAND";
3978 case X86ISD::FOR: return "X86ISD::FOR";
3979 case X86ISD::FXOR: return "X86ISD::FXOR";
3980 case X86ISD::FSRL: return "X86ISD::FSRL";
3981 case X86ISD::FILD: return "X86ISD::FILD";
3982 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
3983 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
3984 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
3985 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
3986 case X86ISD::FLD: return "X86ISD::FLD";
3987 case X86ISD::FST: return "X86ISD::FST";
3988 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
3989 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
3990 case X86ISD::CALL: return "X86ISD::CALL";
3991 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
3992 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
3993 case X86ISD::CMP: return "X86ISD::CMP";
3994 case X86ISD::COMI: return "X86ISD::COMI";
3995 case X86ISD::UCOMI: return "X86ISD::UCOMI";
3996 case X86ISD::SETCC: return "X86ISD::SETCC";
3997 case X86ISD::CMOV: return "X86ISD::CMOV";
3998 case X86ISD::BRCOND: return "X86ISD::BRCOND";
3999 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
4000 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
4001 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
4002 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
4003 case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA";
4004 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
4005 case X86ISD::Wrapper: return "X86ISD::Wrapper";
4006 case X86ISD::S2VEC: return "X86ISD::S2VEC";
4007 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
4008 case X86ISD::PINSRW: return "X86ISD::PINSRW";
4009 case X86ISD::FMAX: return "X86ISD::FMAX";
4010 case X86ISD::FMIN: return "X86ISD::FMIN";
4014 /// isLegalAddressImmediate - Return true if the integer value can be used
4015 /// as the offset of the target addressing mode for load / store of the
4017 bool X86TargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
4018 // X86 allows a sign-extended 32-bit immediate field.
4019 return (V > -(1LL << 32) && V < (1LL << 32)-1);
4022 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
4023 /// the offset of the target addressing mode.
4024 bool X86TargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
4025 // In 64-bit mode, GV is 64-bit so it won't fit in the 32-bit displacement
4026 // field unless we are in small code model.
4027 if (Subtarget->is64Bit() &&
4028 getTargetMachine().getCodeModel() != CodeModel::Small)
4031 return (!Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false));
4034 /// isLegalAddressScale - Return true if the integer value can be used as the
4035 /// scale of the target addressing mode for load / store of the given type.
4036 bool X86TargetLowering::isLegalAddressScale(int64_t S, const Type *Ty) const {
4040 case 2: case 4: case 8:
4042 // FIXME: These require both scale + index last and thus more expensive.
4043 // How to tell LSR to try for 2, 4, 8 first?
4044 case 3: case 5: case 9:
4049 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4050 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4051 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4052 /// are assumed to be legal.
4054 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
4055 // Only do shuffles on 128-bit vector types for now.
4056 if (MVT::getSizeInBits(VT) == 64) return false;
4057 return (Mask.Val->getNumOperands() <= 4 ||
4058 isSplatMask(Mask.Val) ||
4059 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
4060 X86::isUNPCKLMask(Mask.Val) ||
4061 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
4062 X86::isUNPCKHMask(Mask.Val));
4065 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
4067 SelectionDAG &DAG) const {
4068 unsigned NumElts = BVOps.size();
4069 // Only do shuffles on 128-bit vector types for now.
4070 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
4071 if (NumElts == 2) return true;
4073 return (isMOVLMask(&BVOps[0], 4) ||
4074 isCommutedMOVL(&BVOps[0], 4, true) ||
4075 isSHUFPMask(&BVOps[0], 4) ||
4076 isCommutedSHUFP(&BVOps[0], 4));
4081 //===----------------------------------------------------------------------===//
4082 // X86 Scheduler Hooks
4083 //===----------------------------------------------------------------------===//
4086 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
4087 MachineBasicBlock *BB) {
4088 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4089 switch (MI->getOpcode()) {
4090 default: assert(false && "Unexpected instr type to insert");
4091 case X86::CMOV_FR32:
4092 case X86::CMOV_FR64:
4093 case X86::CMOV_V4F32:
4094 case X86::CMOV_V2F64:
4095 case X86::CMOV_V2I64: {
4096 // To "insert" a SELECT_CC instruction, we actually have to insert the
4097 // diamond control-flow pattern. The incoming instruction knows the
4098 // destination vreg to set, the condition code register to branch on, the
4099 // true/false values to select between, and a branch opcode to use.
4100 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4101 ilist<MachineBasicBlock>::iterator It = BB;
4107 // cmpTY ccX, r1, r2
4109 // fallthrough --> copy0MBB
4110 MachineBasicBlock *thisMBB = BB;
4111 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4112 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4114 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
4115 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
4116 MachineFunction *F = BB->getParent();
4117 F->getBasicBlockList().insert(It, copy0MBB);
4118 F->getBasicBlockList().insert(It, sinkMBB);
4119 // Update machine-CFG edges by first adding all successors of the current
4120 // block to the new block which will contain the Phi node for the select.
4121 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
4122 e = BB->succ_end(); i != e; ++i)
4123 sinkMBB->addSuccessor(*i);
4124 // Next, remove all successors of the current block, and add the true
4125 // and fallthrough blocks as its successors.
4126 while(!BB->succ_empty())
4127 BB->removeSuccessor(BB->succ_begin());
4128 BB->addSuccessor(copy0MBB);
4129 BB->addSuccessor(sinkMBB);
4132 // %FalseValue = ...
4133 // # fallthrough to sinkMBB
4136 // Update machine-CFG edges
4137 BB->addSuccessor(sinkMBB);
4140 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4143 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
4144 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4145 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4147 delete MI; // The pseudo instruction is gone now.
4151 case X86::FP_TO_INT16_IN_MEM:
4152 case X86::FP_TO_INT32_IN_MEM:
4153 case X86::FP_TO_INT64_IN_MEM: {
4154 // Change the floating point control register to use "round towards zero"
4155 // mode when truncating to an integer value.
4156 MachineFunction *F = BB->getParent();
4157 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
4158 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
4160 // Load the old value of the high byte of the control word...
4162 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
4163 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
4165 // Set the high part to be round to zero...
4166 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
4169 // Reload the modified control word now...
4170 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4172 // Restore the memory image of control word to original value
4173 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
4176 // Get the X86 opcode to use.
4178 switch (MI->getOpcode()) {
4179 default: assert(0 && "illegal opcode!");
4180 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
4181 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
4182 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
4186 MachineOperand &Op = MI->getOperand(0);
4187 if (Op.isRegister()) {
4188 AM.BaseType = X86AddressMode::RegBase;
4189 AM.Base.Reg = Op.getReg();
4191 AM.BaseType = X86AddressMode::FrameIndexBase;
4192 AM.Base.FrameIndex = Op.getFrameIndex();
4194 Op = MI->getOperand(1);
4195 if (Op.isImmediate())
4196 AM.Scale = Op.getImm();
4197 Op = MI->getOperand(2);
4198 if (Op.isImmediate())
4199 AM.IndexReg = Op.getImm();
4200 Op = MI->getOperand(3);
4201 if (Op.isGlobalAddress()) {
4202 AM.GV = Op.getGlobal();
4204 AM.Disp = Op.getImm();
4206 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
4207 .addReg(MI->getOperand(4).getReg());
4209 // Reload the original control word now.
4210 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4212 delete MI; // The pseudo instruction is gone now.
4218 //===----------------------------------------------------------------------===//
4219 // X86 Optimization Hooks
4220 //===----------------------------------------------------------------------===//
4222 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
4224 uint64_t &KnownZero,
4226 unsigned Depth) const {
4227 unsigned Opc = Op.getOpcode();
4228 assert((Opc >= ISD::BUILTIN_OP_END ||
4229 Opc == ISD::INTRINSIC_WO_CHAIN ||
4230 Opc == ISD::INTRINSIC_W_CHAIN ||
4231 Opc == ISD::INTRINSIC_VOID) &&
4232 "Should use MaskedValueIsZero if you don't know whether Op"
4233 " is a target node!");
4235 KnownZero = KnownOne = 0; // Don't know anything.
4239 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
4244 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4245 /// element of the result of the vector shuffle.
4246 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
4247 MVT::ValueType VT = N->getValueType(0);
4248 SDOperand PermMask = N->getOperand(2);
4249 unsigned NumElems = PermMask.getNumOperands();
4250 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
4252 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4254 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
4255 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
4256 SDOperand Idx = PermMask.getOperand(i);
4257 if (Idx.getOpcode() == ISD::UNDEF)
4258 return DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
4259 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
4264 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
4265 /// node is a GlobalAddress + an offset.
4266 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
4267 unsigned Opc = N->getOpcode();
4268 if (Opc == X86ISD::Wrapper) {
4269 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
4270 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
4273 } else if (Opc == ISD::ADD) {
4274 SDOperand N1 = N->getOperand(0);
4275 SDOperand N2 = N->getOperand(1);
4276 if (isGAPlusOffset(N1.Val, GA, Offset)) {
4277 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
4279 Offset += V->getSignExtended();
4282 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
4283 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
4285 Offset += V->getSignExtended();
4293 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
4295 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
4296 MachineFrameInfo *MFI) {
4297 if (N->getOperand(0).Val != Base->getOperand(0).Val)
4300 SDOperand Loc = N->getOperand(1);
4301 SDOperand BaseLoc = Base->getOperand(1);
4302 if (Loc.getOpcode() == ISD::FrameIndex) {
4303 if (BaseLoc.getOpcode() != ISD::FrameIndex)
4305 int FI = dyn_cast<FrameIndexSDNode>(Loc)->getIndex();
4306 int BFI = dyn_cast<FrameIndexSDNode>(BaseLoc)->getIndex();
4307 int FS = MFI->getObjectSize(FI);
4308 int BFS = MFI->getObjectSize(BFI);
4309 if (FS != BFS || FS != Size) return false;
4310 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
4312 GlobalValue *GV1 = NULL;
4313 GlobalValue *GV2 = NULL;
4314 int64_t Offset1 = 0;
4315 int64_t Offset2 = 0;
4316 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
4317 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
4318 if (isGA1 && isGA2 && GV1 == GV2)
4319 return Offset1 == (Offset2 + Dist*Size);
4325 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
4326 const X86Subtarget *Subtarget) {
4329 if (isGAPlusOffset(Base, GV, Offset))
4330 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
4332 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
4333 int BFI = dyn_cast<FrameIndexSDNode>(Base)->getIndex();
4335 // Fixed objects do not specify alignment, however the offsets are known.
4336 return ((Subtarget->getStackAlignment() % 16) == 0 &&
4337 (MFI->getObjectOffset(BFI) % 16) == 0);
4339 return MFI->getObjectAlignment(BFI) >= 16;
4345 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
4346 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
4347 /// if the load addresses are consecutive, non-overlapping, and in the right
4349 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
4350 const X86Subtarget *Subtarget) {
4351 MachineFunction &MF = DAG.getMachineFunction();
4352 MachineFrameInfo *MFI = MF.getFrameInfo();
4353 MVT::ValueType VT = N->getValueType(0);
4354 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
4355 SDOperand PermMask = N->getOperand(2);
4356 int NumElems = (int)PermMask.getNumOperands();
4357 SDNode *Base = NULL;
4358 for (int i = 0; i < NumElems; ++i) {
4359 SDOperand Idx = PermMask.getOperand(i);
4360 if (Idx.getOpcode() == ISD::UNDEF) {
4361 if (!Base) return SDOperand();
4364 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
4365 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
4369 else if (!isConsecutiveLoad(Arg.Val, Base,
4370 i, MVT::getSizeInBits(EVT)/8,MFI))
4375 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
4377 LoadSDNode *LD = cast<LoadSDNode>(Base);
4378 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
4379 LD->getSrcValueOffset());
4381 // Just use movups, it's shorter.
4382 SDVTList Tys = DAG.getVTList(MVT::v4f32, MVT::Other);
4383 SmallVector<SDOperand, 3> Ops;
4384 Ops.push_back(Base->getOperand(0));
4385 Ops.push_back(Base->getOperand(1));
4386 Ops.push_back(Base->getOperand(2));
4387 return DAG.getNode(ISD::BIT_CONVERT, VT,
4388 DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size()));
4392 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
4393 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
4394 const X86Subtarget *Subtarget) {
4395 SDOperand Cond = N->getOperand(0);
4397 // If we have SSE[12] support, try to form min/max nodes.
4398 if (Subtarget->hasSSE2() &&
4399 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
4400 if (Cond.getOpcode() == ISD::SETCC) {
4401 // Get the LHS/RHS of the select.
4402 SDOperand LHS = N->getOperand(1);
4403 SDOperand RHS = N->getOperand(2);
4404 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
4406 unsigned Opcode = 0;
4407 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
4410 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
4413 if (!UnsafeFPMath) break;
4415 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
4417 Opcode = X86ISD::FMIN;
4420 case ISD::SETOGT: // (X > Y) ? X : Y -> max
4423 if (!UnsafeFPMath) break;
4425 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
4427 Opcode = X86ISD::FMAX;
4430 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
4433 case ISD::SETOGT: // (X > Y) ? Y : X -> min
4436 if (!UnsafeFPMath) break;
4438 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
4440 Opcode = X86ISD::FMIN;
4443 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
4446 if (!UnsafeFPMath) break;
4448 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
4450 Opcode = X86ISD::FMAX;
4456 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
4465 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
4466 DAGCombinerInfo &DCI) const {
4467 SelectionDAG &DAG = DCI.DAG;
4468 switch (N->getOpcode()) {
4470 case ISD::VECTOR_SHUFFLE:
4471 return PerformShuffleCombine(N, DAG, Subtarget);
4473 return PerformSELECTCombine(N, DAG, Subtarget);
4479 //===----------------------------------------------------------------------===//
4480 // X86 Inline Assembly Support
4481 //===----------------------------------------------------------------------===//
4483 /// getConstraintType - Given a constraint letter, return the type of
4484 /// constraint it is for this target.
4485 X86TargetLowering::ConstraintType
4486 X86TargetLowering::getConstraintType(char ConstraintLetter) const {
4487 switch (ConstraintLetter) {
4496 return C_RegisterClass;
4497 default: return TargetLowering::getConstraintType(ConstraintLetter);
4501 /// isOperandValidForConstraint - Return the specified operand (possibly
4502 /// modified) if the specified SDOperand is valid for the specified target
4503 /// constraint letter, otherwise return null.
4504 SDOperand X86TargetLowering::
4505 isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
4506 switch (Constraint) {
4509 // Literal immediates are always ok.
4510 if (isa<ConstantSDNode>(Op)) return Op;
4512 // If we are in non-pic codegen mode, we allow the address of a global to
4513 // be used with 'i'.
4514 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
4515 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4516 return SDOperand(0, 0);
4518 if (GA->getOpcode() != ISD::TargetGlobalAddress)
4519 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4524 // Otherwise, not valid for this mode.
4525 return SDOperand(0, 0);
4527 return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
4531 std::vector<unsigned> X86TargetLowering::
4532 getRegClassForInlineAsmConstraint(const std::string &Constraint,
4533 MVT::ValueType VT) const {
4534 if (Constraint.size() == 1) {
4535 // FIXME: not handling fp-stack yet!
4536 // FIXME: not handling MMX registers yet ('y' constraint).
4537 switch (Constraint[0]) { // GCC X86 Constraint Letters
4538 default: break; // Unknown constraint letter
4539 case 'A': // EAX/EDX
4540 if (VT == MVT::i32 || VT == MVT::i64)
4541 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
4543 case 'r': // GENERAL_REGS
4544 case 'R': // LEGACY_REGS
4545 if (VT == MVT::i64 && Subtarget->is64Bit())
4546 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
4547 X86::RSI, X86::RDI, X86::RBP, X86::RSP,
4548 X86::R8, X86::R9, X86::R10, X86::R11,
4549 X86::R12, X86::R13, X86::R14, X86::R15, 0);
4551 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
4552 X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
4553 else if (VT == MVT::i16)
4554 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
4555 X86::SI, X86::DI, X86::BP, X86::SP, 0);
4556 else if (VT == MVT::i8)
4557 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
4559 case 'l': // INDEX_REGS
4561 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
4562 X86::ESI, X86::EDI, X86::EBP, 0);
4563 else if (VT == MVT::i16)
4564 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
4565 X86::SI, X86::DI, X86::BP, 0);
4566 else if (VT == MVT::i8)
4567 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
4569 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
4572 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
4573 else if (VT == MVT::i16)
4574 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
4575 else if (VT == MVT::i8)
4576 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
4578 case 'x': // SSE_REGS if SSE1 allowed
4579 if (Subtarget->hasSSE1())
4580 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
4581 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
4583 return std::vector<unsigned>();
4584 case 'Y': // SSE_REGS if SSE2 allowed
4585 if (Subtarget->hasSSE2())
4586 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
4587 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
4589 return std::vector<unsigned>();
4593 return std::vector<unsigned>();
4596 std::pair<unsigned, const TargetRegisterClass*>
4597 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4598 MVT::ValueType VT) const {
4599 // Use the default implementation in TargetLowering to convert the register
4600 // constraint into a member of a register class.
4601 std::pair<unsigned, const TargetRegisterClass*> Res;
4602 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4604 // Not found as a standard register?
4605 if (Res.second == 0) {
4606 // GCC calls "st(0)" just plain "st".
4607 if (StringsEqualNoCase("{st}", Constraint)) {
4608 Res.first = X86::ST0;
4609 Res.second = X86::RSTRegisterClass;
4615 // Otherwise, check to see if this is a register class of the wrong value
4616 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
4617 // turn into {ax},{dx}.
4618 if (Res.second->hasType(VT))
4619 return Res; // Correct type already, nothing to do.
4621 // All of the single-register GCC register classes map their values onto
4622 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
4623 // really want an 8-bit or 32-bit register, map to the appropriate register
4624 // class and return the appropriate register.
4625 if (Res.second != X86::GR16RegisterClass)
4628 if (VT == MVT::i8) {
4629 unsigned DestReg = 0;
4630 switch (Res.first) {
4632 case X86::AX: DestReg = X86::AL; break;
4633 case X86::DX: DestReg = X86::DL; break;
4634 case X86::CX: DestReg = X86::CL; break;
4635 case X86::BX: DestReg = X86::BL; break;
4638 Res.first = DestReg;
4639 Res.second = Res.second = X86::GR8RegisterClass;
4641 } else if (VT == MVT::i32) {
4642 unsigned DestReg = 0;
4643 switch (Res.first) {
4645 case X86::AX: DestReg = X86::EAX; break;
4646 case X86::DX: DestReg = X86::EDX; break;
4647 case X86::CX: DestReg = X86::ECX; break;
4648 case X86::BX: DestReg = X86::EBX; break;
4649 case X86::SI: DestReg = X86::ESI; break;
4650 case X86::DI: DestReg = X86::EDI; break;
4651 case X86::BP: DestReg = X86::EBP; break;
4652 case X86::SP: DestReg = X86::ESP; break;
4655 Res.first = DestReg;
4656 Res.second = Res.second = X86::GR32RegisterClass;
4658 } else if (VT == MVT::i64) {
4659 unsigned DestReg = 0;
4660 switch (Res.first) {
4662 case X86::AX: DestReg = X86::RAX; break;
4663 case X86::DX: DestReg = X86::RDX; break;
4664 case X86::CX: DestReg = X86::RCX; break;
4665 case X86::BX: DestReg = X86::RBX; break;
4666 case X86::SI: DestReg = X86::RSI; break;
4667 case X86::DI: DestReg = X86::RDI; break;
4668 case X86::BP: DestReg = X86::RBP; break;
4669 case X86::SP: DestReg = X86::RSP; break;
4672 Res.first = DestReg;
4673 Res.second = Res.second = X86::GR64RegisterClass;