1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static SDValue Insert128BitVector(SDValue Result,
69 static SDValue Extract128BitVector(SDValue Vec,
74 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
75 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
76 /// simple subregister reference. Idx is an index in the 128 bits we
77 /// want. It need not be aligned to a 128-bit bounday. That makes
78 /// lowering EXTRACT_VECTOR_ELT operations easier.
79 static SDValue Extract128BitVector(SDValue Vec,
83 EVT VT = Vec.getValueType();
84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
85 EVT ElVT = VT.getVectorElementType();
86 int Factor = VT.getSizeInBits()/128;
87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
88 VT.getVectorNumElements()/Factor);
90 // Extract from UNDEF is UNDEF.
91 if (Vec.getOpcode() == ISD::UNDEF)
92 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
94 if (isa<ConstantSDNode>(Idx)) {
95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
98 // we can match to VEXTRACTF128.
99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
101 // This is the index of the first element of the 128-bit chunk
103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
116 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
117 /// sets things up to match to an AVX VINSERTF128 instruction or a
118 /// simple superregister reference. Idx is an index in the 128 bits
119 /// we want. It need not be aligned to a 128-bit bounday. That makes
120 /// lowering INSERT_VECTOR_ELT operations easier.
121 static SDValue Insert128BitVector(SDValue Result,
126 if (isa<ConstantSDNode>(Idx)) {
127 EVT VT = Vec.getValueType();
128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
130 EVT ElVT = VT.getVectorElementType();
131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
132 EVT ResultVT = Result.getValueType();
134 // Insert the relevant 128 bits.
135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
137 // This is the index of the first element of the 128-bit chunk
139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
151 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
153 bool is64Bit = Subtarget->is64Bit();
155 if (Subtarget->isTargetEnvMacho()) {
157 return new X8664_MachoTargetObjectFile();
158 return new TargetLoweringObjectFileMachO();
161 if (Subtarget->isTargetELF())
162 return new TargetLoweringObjectFileELF();
163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
164 return new TargetLoweringObjectFileCOFF();
165 llvm_unreachable("unknown subtarget type");
168 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
169 : TargetLowering(TM, createTLOF(TM)) {
170 Subtarget = &TM.getSubtarget<X86Subtarget>();
171 X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX();
172 X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX();
173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
175 RegInfo = TM.getRegisterInfo();
176 TD = getTargetData();
178 // Set up the TargetLowering object.
179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
181 // X86 is weird, it always uses i8 for shift amounts and setcc results.
182 setBooleanContents(ZeroOrOneBooleanContent);
184 // For 64-bit since we have so many registers use the ILP scheduler, for
185 // 32-bit code use the register pressure specific scheduling.
186 if (Subtarget->is64Bit())
187 setSchedulingPreference(Sched::ILP);
189 setSchedulingPreference(Sched::RegPressure);
190 setStackPointerRegisterToSaveRestore(X86StackPtr);
192 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
193 // Setup Windows compiler runtime calls.
194 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
195 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
196 setLibcallName(RTLIB::SREM_I64, "_allrem");
197 setLibcallName(RTLIB::UREM_I64, "_aullrem");
198 setLibcallName(RTLIB::MUL_I64, "_allmul");
199 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
200 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
201 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
202 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
203 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
207 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
210 if (Subtarget->isTargetDarwin()) {
211 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
212 setUseUnderscoreSetJmp(false);
213 setUseUnderscoreLongJmp(false);
214 } else if (Subtarget->isTargetMingw()) {
215 // MS runtime is weird: it exports _setjmp, but longjmp!
216 setUseUnderscoreSetJmp(true);
217 setUseUnderscoreLongJmp(false);
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(true);
223 // Set up the register classes.
224 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
225 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
226 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
227 if (Subtarget->is64Bit())
228 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
232 // We don't accept any truncstore of integer registers.
233 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
235 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
236 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
237 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
238 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
240 // SETOEQ and SETUNE require checking two conditions.
241 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
243 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
248 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
254 if (Subtarget->is64Bit()) {
255 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
257 } else if (!UseSoftFloat) {
258 // We have an algorithm for SSE2->double, and we turn this into a
259 // 64-bit FILD followed by conditional FADD for other targets.
260 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
261 // We have an algorithm for SSE2, and we turn this into a 64-bit
262 // FILD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
272 // SSE has no i16 to fp conversion, only i32
273 if (X86ScalarSSEf32) {
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
275 // f32 and f64 cases are Legal, f80 case is not
276 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
286 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
287 // are Legal, f80 is custom lowered.
288 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
289 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
291 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
293 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
294 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
296 if (X86ScalarSSEf32) {
297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
298 // f32 and f64 cases are Legal, f80 case is not
299 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
305 // Handle FP_TO_UINT by promoting the destination to a larger signed
307 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
311 if (Subtarget->is64Bit()) {
312 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
313 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
314 } else if (!UseSoftFloat) {
315 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
327 if (!X86ScalarSSEf64) {
328 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
329 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
330 if (Subtarget->is64Bit()) {
331 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
332 // Without SSE, i64->f64 goes through memory.
333 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
337 // Scalar integer divide and remainder are lowered to use operations that
338 // produce two results, to match the available instructions. This exposes
339 // the two-result form to trivial CSE, which is able to combine x/y and x%y
340 // into a single instruction.
342 // Scalar integer multiply-high is also lowered to use two-result
343 // operations, to match the available instructions. However, plain multiply
344 // (low) operations are left as Legal, as there are single-result
345 // instructions for this in x86. Using the two-result multiply instructions
346 // when both high and low results are needed must be arranged by dagcombine.
347 for (unsigned i = 0, e = 4; i != e; ++i) {
349 setOperationAction(ISD::MULHS, VT, Expand);
350 setOperationAction(ISD::MULHU, VT, Expand);
351 setOperationAction(ISD::SDIV, VT, Expand);
352 setOperationAction(ISD::UDIV, VT, Expand);
353 setOperationAction(ISD::SREM, VT, Expand);
354 setOperationAction(ISD::UREM, VT, Expand);
356 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
357 setOperationAction(ISD::ADDC, VT, Custom);
358 setOperationAction(ISD::ADDE, VT, Custom);
359 setOperationAction(ISD::SUBC, VT, Custom);
360 setOperationAction(ISD::SUBE, VT, Custom);
363 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
364 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
365 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
366 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
367 if (Subtarget->is64Bit())
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
372 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
373 setOperationAction(ISD::FREM , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f64 , Expand);
375 setOperationAction(ISD::FREM , MVT::f80 , Expand);
376 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
378 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
379 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
380 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
381 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
382 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
383 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
384 if (Subtarget->is64Bit()) {
385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
386 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
400 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
402 // These should be promoted to a larger select which is supported.
403 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
404 // X86 wants to expand cmov itself.
405 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
406 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
407 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
409 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
412 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
415 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
421 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
425 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
426 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
427 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
430 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
431 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
432 if (Subtarget->is64Bit()) {
433 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
434 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
435 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
436 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
437 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
439 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
440 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
441 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
442 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
443 if (Subtarget->is64Bit()) {
444 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
449 if (Subtarget->hasXMM())
450 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
452 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
453 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
455 // On X86 and X86-64, atomic operations are lowered to locked instructions.
456 // Locked instructions, in turn, have implicit fence semantics (all memory
457 // operations are flushed before issuing the locked instruction, and they
458 // are not buffered), so we can fold away the common pattern of
459 // fence-atomic-fence.
460 setShouldFoldAtomicFences(true);
462 // Expand certain atomics
463 for (unsigned i = 0, e = 4; i != e; ++i) {
465 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
466 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 if (!Subtarget->is64Bit()) {
470 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
471 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
472 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
473 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
474 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
476 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
479 // FIXME - use subtarget debug flags
480 if (!Subtarget->isTargetDarwin() &&
481 !Subtarget->isTargetELF() &&
482 !Subtarget->isTargetCygMing()) {
483 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
486 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
487 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
488 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
489 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
490 if (Subtarget->is64Bit()) {
491 setExceptionPointerRegister(X86::RAX);
492 setExceptionSelectorRegister(X86::RDX);
494 setExceptionPointerRegister(X86::EAX);
495 setExceptionSelectorRegister(X86::EDX);
497 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
498 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
500 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
502 setOperationAction(ISD::TRAP, MVT::Other, Legal);
504 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
505 setOperationAction(ISD::VASTART , MVT::Other, Custom);
506 setOperationAction(ISD::VAEND , MVT::Other, Expand);
507 if (Subtarget->is64Bit()) {
508 setOperationAction(ISD::VAARG , MVT::Other, Custom);
509 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
511 setOperationAction(ISD::VAARG , MVT::Other, Expand);
512 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
515 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
516 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
517 setOperationAction(ISD::DYNAMIC_STACKALLOC,
518 (Subtarget->is64Bit() ? MVT::i64 : MVT::i32),
519 (Subtarget->isTargetCOFF()
520 && !Subtarget->isTargetEnvMacho()
523 if (!UseSoftFloat && X86ScalarSSEf64) {
524 // f32 and f64 use SSE.
525 // Set up the FP register classes.
526 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
527 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
529 // Use ANDPD to simulate FABS.
530 setOperationAction(ISD::FABS , MVT::f64, Custom);
531 setOperationAction(ISD::FABS , MVT::f32, Custom);
533 // Use XORP to simulate FNEG.
534 setOperationAction(ISD::FNEG , MVT::f64, Custom);
535 setOperationAction(ISD::FNEG , MVT::f32, Custom);
537 // Use ANDPD and ORPD to simulate FCOPYSIGN.
538 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
539 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
541 // Lower this to FGETSIGNx86 plus an AND.
542 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
543 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
545 // We don't support sin/cos/fmod
546 setOperationAction(ISD::FSIN , MVT::f64, Expand);
547 setOperationAction(ISD::FCOS , MVT::f64, Expand);
548 setOperationAction(ISD::FSIN , MVT::f32, Expand);
549 setOperationAction(ISD::FCOS , MVT::f32, Expand);
551 // Expand FP immediates into loads from the stack, except for the special
553 addLegalFPImmediate(APFloat(+0.0)); // xorpd
554 addLegalFPImmediate(APFloat(+0.0f)); // xorps
555 } else if (!UseSoftFloat && X86ScalarSSEf32) {
556 // Use SSE for f32, x87 for f64.
557 // Set up the FP register classes.
558 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
559 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
561 // Use ANDPS to simulate FABS.
562 setOperationAction(ISD::FABS , MVT::f32, Custom);
564 // Use XORP to simulate FNEG.
565 setOperationAction(ISD::FNEG , MVT::f32, Custom);
567 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
569 // Use ANDPS and ORPS to simulate FCOPYSIGN.
570 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
571 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
573 // We don't support sin/cos/fmod
574 setOperationAction(ISD::FSIN , MVT::f32, Expand);
575 setOperationAction(ISD::FCOS , MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
585 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
586 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
588 } else if (!UseSoftFloat) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
592 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
601 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
603 addLegalFPImmediate(APFloat(+0.0)); // FLD0
604 addLegalFPImmediate(APFloat(+1.0)); // FLD1
605 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
606 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
607 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
613 // We don't support FMA.
614 setOperationAction(ISD::FMA, MVT::f64, Expand);
615 setOperationAction(ISD::FMA, MVT::f32, Expand);
617 // Long double always uses X87.
619 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
620 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
621 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
623 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
624 addLegalFPImmediate(TmpFlt); // FLD0
626 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
629 APFloat TmpFlt2(+1.0);
630 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
632 addLegalFPImmediate(TmpFlt2); // FLD1
633 TmpFlt2.changeSign();
634 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
639 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
642 setOperationAction(ISD::FMA, MVT::f80, Expand);
645 // Always use a library call for pow.
646 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
647 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
648 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
650 setOperationAction(ISD::FLOG, MVT::f80, Expand);
651 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
652 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
653 setOperationAction(ISD::FEXP, MVT::f80, Expand);
654 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
656 // First set operation action for all vector types to either promote
657 // (for widening) or expand (for scalarization). Then we will selectively
658 // turn on ones that can be effectively codegen'd.
659 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
660 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
661 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
662 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
663 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
664 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
665 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
666 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
667 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
668 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
669 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
670 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
671 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
672 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
673 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
674 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
675 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
676 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
677 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
678 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
679 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
680 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
681 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
682 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
683 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
684 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
685 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
686 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
687 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
688 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
690 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
691 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
692 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
693 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
694 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
711 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
715 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
716 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
717 setTruncStoreAction((MVT::SimpleValueType)VT,
718 (MVT::SimpleValueType)InnerVT, Expand);
719 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
720 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
721 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
724 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
725 // with -msoft-float, disable use of MMX as well.
726 if (!UseSoftFloat && Subtarget->hasMMX()) {
727 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
728 // No operations on x86mmx supported, everything uses intrinsics.
731 // MMX-sized vectors (other than x86mmx) are expected to be expanded
732 // into smaller operations.
733 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
734 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
735 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
736 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
737 setOperationAction(ISD::AND, MVT::v8i8, Expand);
738 setOperationAction(ISD::AND, MVT::v4i16, Expand);
739 setOperationAction(ISD::AND, MVT::v2i32, Expand);
740 setOperationAction(ISD::AND, MVT::v1i64, Expand);
741 setOperationAction(ISD::OR, MVT::v8i8, Expand);
742 setOperationAction(ISD::OR, MVT::v4i16, Expand);
743 setOperationAction(ISD::OR, MVT::v2i32, Expand);
744 setOperationAction(ISD::OR, MVT::v1i64, Expand);
745 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
746 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
747 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
748 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
750 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
751 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
753 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
754 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
755 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
756 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
757 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
758 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
759 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
760 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
761 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
763 if (!UseSoftFloat && Subtarget->hasXMM()) {
764 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
766 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
767 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
768 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
769 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
770 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
771 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
772 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
773 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
774 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
776 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
777 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
780 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
781 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
783 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
784 // registers cannot be used even for integer operations.
785 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
786 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
787 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
788 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
790 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
791 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
792 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
793 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
794 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
795 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
796 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
797 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
798 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
799 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
800 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
801 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
802 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
803 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
804 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
805 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
807 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
808 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
809 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
810 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
812 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
813 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
814 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
815 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
818 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
819 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
820 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
821 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
822 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
824 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
825 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
826 EVT VT = (MVT::SimpleValueType)i;
827 // Do not attempt to custom lower non-power-of-2 vectors
828 if (!isPowerOf2_32(VT.getVectorNumElements()))
830 // Do not attempt to custom lower non-128-bit vectors
831 if (!VT.is128BitVector())
833 setOperationAction(ISD::BUILD_VECTOR,
834 VT.getSimpleVT().SimpleTy, Custom);
835 setOperationAction(ISD::VECTOR_SHUFFLE,
836 VT.getSimpleVT().SimpleTy, Custom);
837 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
838 VT.getSimpleVT().SimpleTy, Custom);
841 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
842 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
843 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
844 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
848 if (Subtarget->is64Bit()) {
849 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
853 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
854 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
855 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
858 // Do not attempt to promote non-128-bit vectors
859 if (!VT.is128BitVector())
862 setOperationAction(ISD::AND, SVT, Promote);
863 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
864 setOperationAction(ISD::OR, SVT, Promote);
865 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
866 setOperationAction(ISD::XOR, SVT, Promote);
867 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
868 setOperationAction(ISD::LOAD, SVT, Promote);
869 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
870 setOperationAction(ISD::SELECT, SVT, Promote);
871 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
874 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
876 // Custom lower v2i64 and v2f64 selects.
877 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
878 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
879 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
880 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
882 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
883 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
886 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
887 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
888 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
889 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
890 setOperationAction(ISD::FRINT, MVT::f32, Legal);
891 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
892 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
893 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
894 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
895 setOperationAction(ISD::FRINT, MVT::f64, Legal);
896 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
898 // FIXME: Do we need to handle scalar-to-vector here?
899 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
901 // Can turn SHL into an integer multiply.
902 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
903 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
905 // i8 and i16 vectors are custom , because the source register and source
906 // source memory operand types are not the same width. f32 vectors are
907 // custom since the immediate controlling the insert encodes additional
909 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
914 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
916 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
917 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
919 if (Subtarget->is64Bit()) {
920 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
921 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
925 if (Subtarget->hasSSE2() || Subtarget->hasAVX()) {
926 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
927 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
928 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
929 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
931 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
932 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
933 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
935 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
936 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
939 if (Subtarget->hasSSE42() || Subtarget->hasAVX())
940 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
942 if (!UseSoftFloat && Subtarget->hasAVX()) {
943 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
944 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
945 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
946 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
947 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
948 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
950 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
951 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
952 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
954 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
955 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
956 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
957 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
958 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
959 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
961 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
962 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
963 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
964 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
965 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
966 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
968 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
969 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
970 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
972 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
973 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
974 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
975 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
976 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
977 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
979 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
980 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
981 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
982 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
984 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
985 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
986 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
987 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
989 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
990 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
992 setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
993 setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
994 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
995 setOperationAction(ISD::VSETCC, MVT::v4i64, Custom);
997 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
998 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
999 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1001 // Custom lower several nodes for 256-bit types.
1002 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1003 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1004 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1007 // Extract subvector is special because the value type
1008 // (result) is 128-bit but the source is 256-bit wide.
1009 if (VT.is128BitVector())
1010 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1012 // Do not attempt to custom lower other non-256-bit vectors
1013 if (!VT.is256BitVector())
1016 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1017 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1018 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1019 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1020 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1021 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1024 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1025 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1026 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1029 // Do not attempt to promote non-256-bit vectors
1030 if (!VT.is256BitVector())
1033 setOperationAction(ISD::AND, SVT, Promote);
1034 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1035 setOperationAction(ISD::OR, SVT, Promote);
1036 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1037 setOperationAction(ISD::XOR, SVT, Promote);
1038 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1039 setOperationAction(ISD::LOAD, SVT, Promote);
1040 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1041 setOperationAction(ISD::SELECT, SVT, Promote);
1042 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1046 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1047 // of this type with custom code.
1048 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1049 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1050 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1053 // We want to custom lower some of our intrinsics.
1054 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1057 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1058 // handle type legalization for these operations here.
1060 // FIXME: We really should do custom legalization for addition and
1061 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1062 // than generic legalization for 64-bit multiplication-with-overflow, though.
1063 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1064 // Add/Sub/Mul with overflow operations are custom lowered.
1066 setOperationAction(ISD::SADDO, VT, Custom);
1067 setOperationAction(ISD::UADDO, VT, Custom);
1068 setOperationAction(ISD::SSUBO, VT, Custom);
1069 setOperationAction(ISD::USUBO, VT, Custom);
1070 setOperationAction(ISD::SMULO, VT, Custom);
1071 setOperationAction(ISD::UMULO, VT, Custom);
1074 // There are no 8-bit 3-address imul/mul instructions
1075 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1076 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1078 if (!Subtarget->is64Bit()) {
1079 // These libcalls are not available in 32-bit.
1080 setLibcallName(RTLIB::SHL_I128, 0);
1081 setLibcallName(RTLIB::SRL_I128, 0);
1082 setLibcallName(RTLIB::SRA_I128, 0);
1085 // We have target-specific dag combine patterns for the following nodes:
1086 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1087 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1088 setTargetDAGCombine(ISD::BUILD_VECTOR);
1089 setTargetDAGCombine(ISD::SELECT);
1090 setTargetDAGCombine(ISD::SHL);
1091 setTargetDAGCombine(ISD::SRA);
1092 setTargetDAGCombine(ISD::SRL);
1093 setTargetDAGCombine(ISD::OR);
1094 setTargetDAGCombine(ISD::AND);
1095 setTargetDAGCombine(ISD::ADD);
1096 setTargetDAGCombine(ISD::SUB);
1097 setTargetDAGCombine(ISD::STORE);
1098 setTargetDAGCombine(ISD::ZERO_EXTEND);
1099 setTargetDAGCombine(ISD::SINT_TO_FP);
1100 if (Subtarget->is64Bit())
1101 setTargetDAGCombine(ISD::MUL);
1103 computeRegisterProperties();
1105 // On Darwin, -Os means optimize for size without hurting performance,
1106 // do not reduce the limit.
1107 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1108 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1109 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1110 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1111 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1112 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1113 setPrefLoopAlignment(16);
1114 benefitFromCodePlacementOpt = true;
1116 setPrefFunctionAlignment(4);
1120 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1125 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1126 /// the desired ByVal argument alignment.
1127 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1130 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1131 if (VTy->getBitWidth() == 128)
1133 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1134 unsigned EltAlign = 0;
1135 getMaxByValAlign(ATy->getElementType(), EltAlign);
1136 if (EltAlign > MaxAlign)
1137 MaxAlign = EltAlign;
1138 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1139 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1140 unsigned EltAlign = 0;
1141 getMaxByValAlign(STy->getElementType(i), EltAlign);
1142 if (EltAlign > MaxAlign)
1143 MaxAlign = EltAlign;
1151 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1152 /// function arguments in the caller parameter area. For X86, aggregates
1153 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1154 /// are at 4-byte boundaries.
1155 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1156 if (Subtarget->is64Bit()) {
1157 // Max of 8 and alignment of type.
1158 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1165 if (Subtarget->hasXMM())
1166 getMaxByValAlign(Ty, Align);
1170 /// getOptimalMemOpType - Returns the target specific optimal type for load
1171 /// and store operations as a result of memset, memcpy, and memmove
1172 /// lowering. If DstAlign is zero that means it's safe to destination
1173 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1174 /// means there isn't a need to check it against alignment requirement,
1175 /// probably because the source does not need to be loaded. If
1176 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1177 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1178 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1179 /// constant so it does not need to be loaded.
1180 /// It returns EVT::Other if the type should be determined using generic
1181 /// target-independent logic.
1183 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1184 unsigned DstAlign, unsigned SrcAlign,
1185 bool NonScalarIntSafe,
1187 MachineFunction &MF) const {
1188 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1189 // linux. This is because the stack realignment code can't handle certain
1190 // cases like PR2962. This should be removed when PR2962 is fixed.
1191 const Function *F = MF.getFunction();
1192 if (NonScalarIntSafe &&
1193 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1195 (Subtarget->isUnalignedMemAccessFast() ||
1196 ((DstAlign == 0 || DstAlign >= 16) &&
1197 (SrcAlign == 0 || SrcAlign >= 16))) &&
1198 Subtarget->getStackAlignment() >= 16) {
1199 if (Subtarget->hasSSE2())
1201 if (Subtarget->hasSSE1())
1203 } else if (!MemcpyStrSrc && Size >= 8 &&
1204 !Subtarget->is64Bit() &&
1205 Subtarget->getStackAlignment() >= 8 &&
1206 Subtarget->hasXMMInt()) {
1207 // Do not use f64 to lower memcpy if source is string constant. It's
1208 // better to use i32 to avoid the loads.
1212 if (Subtarget->is64Bit() && Size >= 8)
1217 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1218 /// current function. The returned value is a member of the
1219 /// MachineJumpTableInfo::JTEntryKind enum.
1220 unsigned X86TargetLowering::getJumpTableEncoding() const {
1221 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1223 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1224 Subtarget->isPICStyleGOT())
1225 return MachineJumpTableInfo::EK_Custom32;
1227 // Otherwise, use the normal jump table encoding heuristics.
1228 return TargetLowering::getJumpTableEncoding();
1232 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1233 const MachineBasicBlock *MBB,
1234 unsigned uid,MCContext &Ctx) const{
1235 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1236 Subtarget->isPICStyleGOT());
1237 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1239 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1240 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1243 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1245 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1246 SelectionDAG &DAG) const {
1247 if (!Subtarget->is64Bit())
1248 // This doesn't have DebugLoc associated with it, but is not really the
1249 // same as a Register.
1250 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1254 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1255 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1257 const MCExpr *X86TargetLowering::
1258 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1259 MCContext &Ctx) const {
1260 // X86-64 uses RIP relative addressing based on the jump table label.
1261 if (Subtarget->isPICStyleRIPRel())
1262 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1264 // Otherwise, the reference is relative to the PIC base.
1265 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1268 // FIXME: Why this routine is here? Move to RegInfo!
1269 std::pair<const TargetRegisterClass*, uint8_t>
1270 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1271 const TargetRegisterClass *RRC = 0;
1273 switch (VT.getSimpleVT().SimpleTy) {
1275 return TargetLowering::findRepresentativeClass(VT);
1276 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1277 RRC = (Subtarget->is64Bit()
1278 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1281 RRC = X86::VR64RegisterClass;
1283 case MVT::f32: case MVT::f64:
1284 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1285 case MVT::v4f32: case MVT::v2f64:
1286 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1288 RRC = X86::VR128RegisterClass;
1291 return std::make_pair(RRC, Cost);
1294 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1295 unsigned &Offset) const {
1296 if (!Subtarget->isTargetLinux())
1299 if (Subtarget->is64Bit()) {
1300 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1302 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1315 //===----------------------------------------------------------------------===//
1316 // Return Value Calling Convention Implementation
1317 //===----------------------------------------------------------------------===//
1319 #include "X86GenCallingConv.inc"
1322 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1323 MachineFunction &MF, bool isVarArg,
1324 const SmallVectorImpl<ISD::OutputArg> &Outs,
1325 LLVMContext &Context) const {
1326 SmallVector<CCValAssign, 16> RVLocs;
1327 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1329 return CCInfo.CheckReturn(Outs, RetCC_X86);
1333 X86TargetLowering::LowerReturn(SDValue Chain,
1334 CallingConv::ID CallConv, bool isVarArg,
1335 const SmallVectorImpl<ISD::OutputArg> &Outs,
1336 const SmallVectorImpl<SDValue> &OutVals,
1337 DebugLoc dl, SelectionDAG &DAG) const {
1338 MachineFunction &MF = DAG.getMachineFunction();
1339 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1341 SmallVector<CCValAssign, 16> RVLocs;
1342 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1343 RVLocs, *DAG.getContext());
1344 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1346 // Add the regs to the liveout set for the function.
1347 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1348 for (unsigned i = 0; i != RVLocs.size(); ++i)
1349 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1350 MRI.addLiveOut(RVLocs[i].getLocReg());
1354 SmallVector<SDValue, 6> RetOps;
1355 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1356 // Operand #1 = Bytes To Pop
1357 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1360 // Copy the result values into the output registers.
1361 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1362 CCValAssign &VA = RVLocs[i];
1363 assert(VA.isRegLoc() && "Can only return in registers!");
1364 SDValue ValToCopy = OutVals[i];
1365 EVT ValVT = ValToCopy.getValueType();
1367 // If this is x86-64, and we disabled SSE, we can't return FP values,
1368 // or SSE or MMX vectors.
1369 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1370 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1371 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1372 report_fatal_error("SSE register return with SSE disabled");
1374 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1375 // llvm-gcc has never done it right and no one has noticed, so this
1376 // should be OK for now.
1377 if (ValVT == MVT::f64 &&
1378 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1379 report_fatal_error("SSE2 register return with SSE2 disabled");
1381 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1382 // the RET instruction and handled by the FP Stackifier.
1383 if (VA.getLocReg() == X86::ST0 ||
1384 VA.getLocReg() == X86::ST1) {
1385 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1386 // change the value to the FP stack register class.
1387 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1388 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1389 RetOps.push_back(ValToCopy);
1390 // Don't emit a copytoreg.
1394 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1395 // which is returned in RAX / RDX.
1396 if (Subtarget->is64Bit()) {
1397 if (ValVT == MVT::x86mmx) {
1398 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1399 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1400 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1402 // If we don't have SSE2 available, convert to v4f32 so the generated
1403 // register is legal.
1404 if (!Subtarget->hasSSE2())
1405 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1410 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1411 Flag = Chain.getValue(1);
1414 // The x86-64 ABI for returning structs by value requires that we copy
1415 // the sret argument into %rax for the return. We saved the argument into
1416 // a virtual register in the entry block, so now we copy the value out
1418 if (Subtarget->is64Bit() &&
1419 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1420 MachineFunction &MF = DAG.getMachineFunction();
1421 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1422 unsigned Reg = FuncInfo->getSRetReturnReg();
1424 "SRetReturnReg should have been set in LowerFormalArguments().");
1425 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1427 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1428 Flag = Chain.getValue(1);
1430 // RAX now acts like a return value.
1431 MRI.addLiveOut(X86::RAX);
1434 RetOps[0] = Chain; // Update chain.
1436 // Add the flag if we have it.
1438 RetOps.push_back(Flag);
1440 return DAG.getNode(X86ISD::RET_FLAG, dl,
1441 MVT::Other, &RetOps[0], RetOps.size());
1444 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1445 if (N->getNumValues() != 1)
1447 if (!N->hasNUsesOfValue(1, 0))
1450 SDNode *Copy = *N->use_begin();
1451 if (Copy->getOpcode() != ISD::CopyToReg &&
1452 Copy->getOpcode() != ISD::FP_EXTEND)
1455 bool HasRet = false;
1456 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1458 if (UI->getOpcode() != X86ISD::RET_FLAG)
1467 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1468 ISD::NodeType ExtendKind) const {
1470 // TODO: Is this also valid on 32-bit?
1471 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1472 ReturnMVT = MVT::i8;
1474 ReturnMVT = MVT::i32;
1476 EVT MinVT = getRegisterType(Context, ReturnMVT);
1477 return VT.bitsLT(MinVT) ? MinVT : VT;
1480 /// LowerCallResult - Lower the result values of a call into the
1481 /// appropriate copies out of appropriate physical registers.
1484 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1485 CallingConv::ID CallConv, bool isVarArg,
1486 const SmallVectorImpl<ISD::InputArg> &Ins,
1487 DebugLoc dl, SelectionDAG &DAG,
1488 SmallVectorImpl<SDValue> &InVals) const {
1490 // Assign locations to each value returned by this call.
1491 SmallVector<CCValAssign, 16> RVLocs;
1492 bool Is64Bit = Subtarget->is64Bit();
1493 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1494 getTargetMachine(), RVLocs, *DAG.getContext());
1495 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1497 // Copy all of the result registers out of their specified physreg.
1498 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1499 CCValAssign &VA = RVLocs[i];
1500 EVT CopyVT = VA.getValVT();
1502 // If this is x86-64, and we disabled SSE, we can't return FP values
1503 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1504 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1505 report_fatal_error("SSE register return with SSE disabled");
1510 // If this is a call to a function that returns an fp value on the floating
1511 // point stack, we must guarantee the the value is popped from the stack, so
1512 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1513 // if the return value is not used. We use the FpPOP_RETVAL instruction
1515 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1516 // If we prefer to use the value in xmm registers, copy it out as f80 and
1517 // use a truncate to move it from fp stack reg to xmm reg.
1518 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1519 SDValue Ops[] = { Chain, InFlag };
1520 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1521 MVT::Other, MVT::Glue, Ops, 2), 1);
1522 Val = Chain.getValue(0);
1524 // Round the f80 to the right size, which also moves it to the appropriate
1526 if (CopyVT != VA.getValVT())
1527 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1528 // This truncation won't change the value.
1529 DAG.getIntPtrConstant(1));
1531 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1532 CopyVT, InFlag).getValue(1);
1533 Val = Chain.getValue(0);
1535 InFlag = Chain.getValue(2);
1536 InVals.push_back(Val);
1543 //===----------------------------------------------------------------------===//
1544 // C & StdCall & Fast Calling Convention implementation
1545 //===----------------------------------------------------------------------===//
1546 // StdCall calling convention seems to be standard for many Windows' API
1547 // routines and around. It differs from C calling convention just a little:
1548 // callee should clean up the stack, not caller. Symbols should be also
1549 // decorated in some fancy way :) It doesn't support any vector arguments.
1550 // For info on fast calling convention see Fast Calling Convention (tail call)
1551 // implementation LowerX86_32FastCCCallTo.
1553 /// CallIsStructReturn - Determines whether a call uses struct return
1555 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1559 return Outs[0].Flags.isSRet();
1562 /// ArgsAreStructReturn - Determines whether a function uses struct
1563 /// return semantics.
1565 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1569 return Ins[0].Flags.isSRet();
1572 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1573 /// by "Src" to address "Dst" with size and alignment information specified by
1574 /// the specific parameter attribute. The copy will be passed as a byval
1575 /// function parameter.
1577 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1578 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1580 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1582 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1583 /*isVolatile*/false, /*AlwaysInline=*/true,
1584 MachinePointerInfo(), MachinePointerInfo());
1587 /// IsTailCallConvention - Return true if the calling convention is one that
1588 /// supports tail call optimization.
1589 static bool IsTailCallConvention(CallingConv::ID CC) {
1590 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1593 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1594 if (!CI->isTailCall())
1598 CallingConv::ID CalleeCC = CS.getCallingConv();
1599 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1605 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1606 /// a tailcall target by changing its ABI.
1607 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1608 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1612 X86TargetLowering::LowerMemArgument(SDValue Chain,
1613 CallingConv::ID CallConv,
1614 const SmallVectorImpl<ISD::InputArg> &Ins,
1615 DebugLoc dl, SelectionDAG &DAG,
1616 const CCValAssign &VA,
1617 MachineFrameInfo *MFI,
1619 // Create the nodes corresponding to a load from this parameter slot.
1620 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1621 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1622 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1625 // If value is passed by pointer we have address passed instead of the value
1627 if (VA.getLocInfo() == CCValAssign::Indirect)
1628 ValVT = VA.getLocVT();
1630 ValVT = VA.getValVT();
1632 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1633 // changed with more analysis.
1634 // In case of tail call optimization mark all arguments mutable. Since they
1635 // could be overwritten by lowering of arguments in case of a tail call.
1636 if (Flags.isByVal()) {
1637 unsigned Bytes = Flags.getByValSize();
1638 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1639 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1640 return DAG.getFrameIndex(FI, getPointerTy());
1642 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1643 VA.getLocMemOffset(), isImmutable);
1644 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1645 return DAG.getLoad(ValVT, dl, Chain, FIN,
1646 MachinePointerInfo::getFixedStack(FI),
1652 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1653 CallingConv::ID CallConv,
1655 const SmallVectorImpl<ISD::InputArg> &Ins,
1658 SmallVectorImpl<SDValue> &InVals)
1660 MachineFunction &MF = DAG.getMachineFunction();
1661 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1663 const Function* Fn = MF.getFunction();
1664 if (Fn->hasExternalLinkage() &&
1665 Subtarget->isTargetCygMing() &&
1666 Fn->getName() == "main")
1667 FuncInfo->setForceFramePointer(true);
1669 MachineFrameInfo *MFI = MF.getFrameInfo();
1670 bool Is64Bit = Subtarget->is64Bit();
1671 bool IsWin64 = Subtarget->isTargetWin64();
1673 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1674 "Var args not supported with calling convention fastcc or ghc");
1676 // Assign locations to all of the incoming arguments.
1677 SmallVector<CCValAssign, 16> ArgLocs;
1678 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1679 ArgLocs, *DAG.getContext());
1681 // Allocate shadow area for Win64
1683 CCInfo.AllocateStack(32, 8);
1686 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1688 unsigned LastVal = ~0U;
1690 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1691 CCValAssign &VA = ArgLocs[i];
1692 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1694 assert(VA.getValNo() != LastVal &&
1695 "Don't support value assigned to multiple locs yet");
1696 LastVal = VA.getValNo();
1698 if (VA.isRegLoc()) {
1699 EVT RegVT = VA.getLocVT();
1700 TargetRegisterClass *RC = NULL;
1701 if (RegVT == MVT::i32)
1702 RC = X86::GR32RegisterClass;
1703 else if (Is64Bit && RegVT == MVT::i64)
1704 RC = X86::GR64RegisterClass;
1705 else if (RegVT == MVT::f32)
1706 RC = X86::FR32RegisterClass;
1707 else if (RegVT == MVT::f64)
1708 RC = X86::FR64RegisterClass;
1709 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1710 RC = X86::VR256RegisterClass;
1711 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1712 RC = X86::VR128RegisterClass;
1713 else if (RegVT == MVT::x86mmx)
1714 RC = X86::VR64RegisterClass;
1716 llvm_unreachable("Unknown argument type!");
1718 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1719 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1721 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1722 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1724 if (VA.getLocInfo() == CCValAssign::SExt)
1725 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1726 DAG.getValueType(VA.getValVT()));
1727 else if (VA.getLocInfo() == CCValAssign::ZExt)
1728 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1729 DAG.getValueType(VA.getValVT()));
1730 else if (VA.getLocInfo() == CCValAssign::BCvt)
1731 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1733 if (VA.isExtInLoc()) {
1734 // Handle MMX values passed in XMM regs.
1735 if (RegVT.isVector()) {
1736 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1739 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1742 assert(VA.isMemLoc());
1743 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1746 // If value is passed via pointer - do a load.
1747 if (VA.getLocInfo() == CCValAssign::Indirect)
1748 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1749 MachinePointerInfo(), false, false, 0);
1751 InVals.push_back(ArgValue);
1754 // The x86-64 ABI for returning structs by value requires that we copy
1755 // the sret argument into %rax for the return. Save the argument into
1756 // a virtual register so that we can access it from the return points.
1757 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1758 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1759 unsigned Reg = FuncInfo->getSRetReturnReg();
1761 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1762 FuncInfo->setSRetReturnReg(Reg);
1764 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1765 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1768 unsigned StackSize = CCInfo.getNextStackOffset();
1769 // Align stack specially for tail calls.
1770 if (FuncIsMadeTailCallSafe(CallConv))
1771 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1773 // If the function takes variable number of arguments, make a frame index for
1774 // the start of the first vararg value... for expansion of llvm.va_start.
1776 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1777 CallConv != CallingConv::X86_ThisCall)) {
1778 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1781 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1783 // FIXME: We should really autogenerate these arrays
1784 static const unsigned GPR64ArgRegsWin64[] = {
1785 X86::RCX, X86::RDX, X86::R8, X86::R9
1787 static const unsigned GPR64ArgRegs64Bit[] = {
1788 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1790 static const unsigned XMMArgRegs64Bit[] = {
1791 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1792 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1794 const unsigned *GPR64ArgRegs;
1795 unsigned NumXMMRegs = 0;
1798 // The XMM registers which might contain var arg parameters are shadowed
1799 // in their paired GPR. So we only need to save the GPR to their home
1801 TotalNumIntRegs = 4;
1802 GPR64ArgRegs = GPR64ArgRegsWin64;
1804 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1805 GPR64ArgRegs = GPR64ArgRegs64Bit;
1807 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1809 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1812 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1813 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1814 "SSE register cannot be used when SSE is disabled!");
1815 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1816 "SSE register cannot be used when SSE is disabled!");
1817 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1818 // Kernel mode asks for SSE to be disabled, so don't push them
1820 TotalNumXMMRegs = 0;
1823 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1824 // Get to the caller-allocated home save location. Add 8 to account
1825 // for the return address.
1826 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1827 FuncInfo->setRegSaveFrameIndex(
1828 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1829 // Fixup to set vararg frame on shadow area (4 x i64).
1831 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1833 // For X86-64, if there are vararg parameters that are passed via
1834 // registers, then we must store them to their spots on the stack so they
1835 // may be loaded by deferencing the result of va_next.
1836 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1837 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1838 FuncInfo->setRegSaveFrameIndex(
1839 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1843 // Store the integer parameter registers.
1844 SmallVector<SDValue, 8> MemOps;
1845 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1847 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1848 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1849 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1850 DAG.getIntPtrConstant(Offset));
1851 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1852 X86::GR64RegisterClass);
1853 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1855 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1856 MachinePointerInfo::getFixedStack(
1857 FuncInfo->getRegSaveFrameIndex(), Offset),
1859 MemOps.push_back(Store);
1863 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1864 // Now store the XMM (fp + vector) parameter registers.
1865 SmallVector<SDValue, 11> SaveXMMOps;
1866 SaveXMMOps.push_back(Chain);
1868 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1869 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1870 SaveXMMOps.push_back(ALVal);
1872 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1873 FuncInfo->getRegSaveFrameIndex()));
1874 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1875 FuncInfo->getVarArgsFPOffset()));
1877 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1878 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1879 X86::VR128RegisterClass);
1880 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1881 SaveXMMOps.push_back(Val);
1883 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1885 &SaveXMMOps[0], SaveXMMOps.size()));
1888 if (!MemOps.empty())
1889 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1890 &MemOps[0], MemOps.size());
1894 // Some CCs need callee pop.
1895 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
1896 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1898 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1899 // If this is an sret function, the return should pop the hidden pointer.
1900 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1901 FuncInfo->setBytesToPopOnReturn(4);
1905 // RegSaveFrameIndex is X86-64 only.
1906 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1907 if (CallConv == CallingConv::X86_FastCall ||
1908 CallConv == CallingConv::X86_ThisCall)
1909 // fastcc functions can't have varargs.
1910 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1917 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1918 SDValue StackPtr, SDValue Arg,
1919 DebugLoc dl, SelectionDAG &DAG,
1920 const CCValAssign &VA,
1921 ISD::ArgFlagsTy Flags) const {
1922 unsigned LocMemOffset = VA.getLocMemOffset();
1923 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1924 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1925 if (Flags.isByVal())
1926 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1928 return DAG.getStore(Chain, dl, Arg, PtrOff,
1929 MachinePointerInfo::getStack(LocMemOffset),
1933 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1934 /// optimization is performed and it is required.
1936 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1937 SDValue &OutRetAddr, SDValue Chain,
1938 bool IsTailCall, bool Is64Bit,
1939 int FPDiff, DebugLoc dl) const {
1940 // Adjust the Return address stack slot.
1941 EVT VT = getPointerTy();
1942 OutRetAddr = getReturnAddressFrameIndex(DAG);
1944 // Load the "old" Return address.
1945 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1947 return SDValue(OutRetAddr.getNode(), 1);
1950 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
1951 /// optimization is performed and it is required (FPDiff!=0).
1953 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1954 SDValue Chain, SDValue RetAddrFrIdx,
1955 bool Is64Bit, int FPDiff, DebugLoc dl) {
1956 // Store the return address to the appropriate stack slot.
1957 if (!FPDiff) return Chain;
1958 // Calculate the new stack slot for the return address.
1959 int SlotSize = Is64Bit ? 8 : 4;
1960 int NewReturnAddrFI =
1961 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1962 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1963 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1964 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1965 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1971 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1972 CallingConv::ID CallConv, bool isVarArg,
1974 const SmallVectorImpl<ISD::OutputArg> &Outs,
1975 const SmallVectorImpl<SDValue> &OutVals,
1976 const SmallVectorImpl<ISD::InputArg> &Ins,
1977 DebugLoc dl, SelectionDAG &DAG,
1978 SmallVectorImpl<SDValue> &InVals) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 bool Is64Bit = Subtarget->is64Bit();
1981 bool IsWin64 = Subtarget->isTargetWin64();
1982 bool IsStructRet = CallIsStructReturn(Outs);
1983 bool IsSibcall = false;
1986 // Check if it's really possible to do a tail call.
1987 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1988 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1989 Outs, OutVals, Ins, DAG);
1991 // Sibcalls are automatically detected tailcalls which do not require
1993 if (!GuaranteedTailCallOpt && isTailCall)
2000 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2001 "Var args not supported with calling convention fastcc or ghc");
2003 // Analyze operands of the call, assigning locations to each operand.
2004 SmallVector<CCValAssign, 16> ArgLocs;
2005 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2006 ArgLocs, *DAG.getContext());
2008 // Allocate shadow area for Win64
2010 CCInfo.AllocateStack(32, 8);
2013 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2015 // Get a count of how many bytes are to be pushed on the stack.
2016 unsigned NumBytes = CCInfo.getNextStackOffset();
2018 // This is a sibcall. The memory operands are available in caller's
2019 // own caller's stack.
2021 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2022 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2025 if (isTailCall && !IsSibcall) {
2026 // Lower arguments at fp - stackoffset + fpdiff.
2027 unsigned NumBytesCallerPushed =
2028 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2029 FPDiff = NumBytesCallerPushed - NumBytes;
2031 // Set the delta of movement of the returnaddr stackslot.
2032 // But only set if delta is greater than previous delta.
2033 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2034 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2038 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2040 SDValue RetAddrFrIdx;
2041 // Load return address for tail calls.
2042 if (isTailCall && FPDiff)
2043 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2044 Is64Bit, FPDiff, dl);
2046 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2047 SmallVector<SDValue, 8> MemOpChains;
2050 // Walk the register/memloc assignments, inserting copies/loads. In the case
2051 // of tail call optimization arguments are handle later.
2052 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2053 CCValAssign &VA = ArgLocs[i];
2054 EVT RegVT = VA.getLocVT();
2055 SDValue Arg = OutVals[i];
2056 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2057 bool isByVal = Flags.isByVal();
2059 // Promote the value if needed.
2060 switch (VA.getLocInfo()) {
2061 default: llvm_unreachable("Unknown loc info!");
2062 case CCValAssign::Full: break;
2063 case CCValAssign::SExt:
2064 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2066 case CCValAssign::ZExt:
2067 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2069 case CCValAssign::AExt:
2070 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2071 // Special case: passing MMX values in XMM registers.
2072 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2073 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2074 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2076 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2078 case CCValAssign::BCvt:
2079 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2081 case CCValAssign::Indirect: {
2082 // Store the argument.
2083 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2084 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2085 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2086 MachinePointerInfo::getFixedStack(FI),
2093 if (VA.isRegLoc()) {
2094 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2095 if (isVarArg && IsWin64) {
2096 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2097 // shadow reg if callee is a varargs function.
2098 unsigned ShadowReg = 0;
2099 switch (VA.getLocReg()) {
2100 case X86::XMM0: ShadowReg = X86::RCX; break;
2101 case X86::XMM1: ShadowReg = X86::RDX; break;
2102 case X86::XMM2: ShadowReg = X86::R8; break;
2103 case X86::XMM3: ShadowReg = X86::R9; break;
2106 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2108 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2109 assert(VA.isMemLoc());
2110 if (StackPtr.getNode() == 0)
2111 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2112 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2113 dl, DAG, VA, Flags));
2117 if (!MemOpChains.empty())
2118 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2119 &MemOpChains[0], MemOpChains.size());
2121 // Build a sequence of copy-to-reg nodes chained together with token chain
2122 // and flag operands which copy the outgoing args into registers.
2124 // Tail call byval lowering might overwrite argument registers so in case of
2125 // tail call optimization the copies to registers are lowered later.
2127 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2128 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2129 RegsToPass[i].second, InFlag);
2130 InFlag = Chain.getValue(1);
2133 if (Subtarget->isPICStyleGOT()) {
2134 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2137 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2138 DAG.getNode(X86ISD::GlobalBaseReg,
2139 DebugLoc(), getPointerTy()),
2141 InFlag = Chain.getValue(1);
2143 // If we are tail calling and generating PIC/GOT style code load the
2144 // address of the callee into ECX. The value in ecx is used as target of
2145 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2146 // for tail calls on PIC/GOT architectures. Normally we would just put the
2147 // address of GOT into ebx and then call target@PLT. But for tail calls
2148 // ebx would be restored (since ebx is callee saved) before jumping to the
2151 // Note: The actual moving to ECX is done further down.
2152 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2153 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2154 !G->getGlobal()->hasProtectedVisibility())
2155 Callee = LowerGlobalAddress(Callee, DAG);
2156 else if (isa<ExternalSymbolSDNode>(Callee))
2157 Callee = LowerExternalSymbol(Callee, DAG);
2161 if (Is64Bit && isVarArg && !IsWin64) {
2162 // From AMD64 ABI document:
2163 // For calls that may call functions that use varargs or stdargs
2164 // (prototype-less calls or calls to functions containing ellipsis (...) in
2165 // the declaration) %al is used as hidden argument to specify the number
2166 // of SSE registers used. The contents of %al do not need to match exactly
2167 // the number of registers, but must be an ubound on the number of SSE
2168 // registers used and is in the range 0 - 8 inclusive.
2170 // Count the number of XMM registers allocated.
2171 static const unsigned XMMArgRegs[] = {
2172 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2173 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2175 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2176 assert((Subtarget->hasXMM() || !NumXMMRegs)
2177 && "SSE registers cannot be used when SSE is disabled");
2179 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2180 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2181 InFlag = Chain.getValue(1);
2185 // For tail calls lower the arguments to the 'real' stack slot.
2187 // Force all the incoming stack arguments to be loaded from the stack
2188 // before any new outgoing arguments are stored to the stack, because the
2189 // outgoing stack slots may alias the incoming argument stack slots, and
2190 // the alias isn't otherwise explicit. This is slightly more conservative
2191 // than necessary, because it means that each store effectively depends
2192 // on every argument instead of just those arguments it would clobber.
2193 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2195 SmallVector<SDValue, 8> MemOpChains2;
2198 // Do not flag preceding copytoreg stuff together with the following stuff.
2200 if (GuaranteedTailCallOpt) {
2201 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2202 CCValAssign &VA = ArgLocs[i];
2205 assert(VA.isMemLoc());
2206 SDValue Arg = OutVals[i];
2207 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2208 // Create frame index.
2209 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2210 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2211 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2212 FIN = DAG.getFrameIndex(FI, getPointerTy());
2214 if (Flags.isByVal()) {
2215 // Copy relative to framepointer.
2216 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2217 if (StackPtr.getNode() == 0)
2218 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2220 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2222 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2226 // Store relative to framepointer.
2227 MemOpChains2.push_back(
2228 DAG.getStore(ArgChain, dl, Arg, FIN,
2229 MachinePointerInfo::getFixedStack(FI),
2235 if (!MemOpChains2.empty())
2236 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2237 &MemOpChains2[0], MemOpChains2.size());
2239 // Copy arguments to their registers.
2240 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2241 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2242 RegsToPass[i].second, InFlag);
2243 InFlag = Chain.getValue(1);
2247 // Store the return address to the appropriate stack slot.
2248 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2252 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2253 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2254 // In the 64-bit large code model, we have to make all calls
2255 // through a register, since the call instruction's 32-bit
2256 // pc-relative offset may not be large enough to hold the whole
2258 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2259 // If the callee is a GlobalAddress node (quite common, every direct call
2260 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2263 // We should use extra load for direct calls to dllimported functions in
2265 const GlobalValue *GV = G->getGlobal();
2266 if (!GV->hasDLLImportLinkage()) {
2267 unsigned char OpFlags = 0;
2268 bool ExtraLoad = false;
2269 unsigned WrapperKind = ISD::DELETED_NODE;
2271 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2272 // external symbols most go through the PLT in PIC mode. If the symbol
2273 // has hidden or protected visibility, or if it is static or local, then
2274 // we don't need to use the PLT - we can directly call it.
2275 if (Subtarget->isTargetELF() &&
2276 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2277 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2278 OpFlags = X86II::MO_PLT;
2279 } else if (Subtarget->isPICStyleStubAny() &&
2280 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2281 (!Subtarget->getTargetTriple().isMacOSX() ||
2282 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2283 // PC-relative references to external symbols should go through $stub,
2284 // unless we're building with the leopard linker or later, which
2285 // automatically synthesizes these stubs.
2286 OpFlags = X86II::MO_DARWIN_STUB;
2287 } else if (Subtarget->isPICStyleRIPRel() &&
2288 isa<Function>(GV) &&
2289 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2290 // If the function is marked as non-lazy, generate an indirect call
2291 // which loads from the GOT directly. This avoids runtime overhead
2292 // at the cost of eager binding (and one extra byte of encoding).
2293 OpFlags = X86II::MO_GOTPCREL;
2294 WrapperKind = X86ISD::WrapperRIP;
2298 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2299 G->getOffset(), OpFlags);
2301 // Add a wrapper if needed.
2302 if (WrapperKind != ISD::DELETED_NODE)
2303 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2304 // Add extra indirection if needed.
2306 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2307 MachinePointerInfo::getGOT(),
2310 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2311 unsigned char OpFlags = 0;
2313 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2314 // external symbols should go through the PLT.
2315 if (Subtarget->isTargetELF() &&
2316 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2317 OpFlags = X86II::MO_PLT;
2318 } else if (Subtarget->isPICStyleStubAny() &&
2319 (!Subtarget->getTargetTriple().isMacOSX() ||
2320 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2321 // PC-relative references to external symbols should go through $stub,
2322 // unless we're building with the leopard linker or later, which
2323 // automatically synthesizes these stubs.
2324 OpFlags = X86II::MO_DARWIN_STUB;
2327 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2331 // Returns a chain & a flag for retval copy to use.
2332 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2333 SmallVector<SDValue, 8> Ops;
2335 if (!IsSibcall && isTailCall) {
2336 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2337 DAG.getIntPtrConstant(0, true), InFlag);
2338 InFlag = Chain.getValue(1);
2341 Ops.push_back(Chain);
2342 Ops.push_back(Callee);
2345 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2347 // Add argument registers to the end of the list so that they are known live
2349 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2350 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2351 RegsToPass[i].second.getValueType()));
2353 // Add an implicit use GOT pointer in EBX.
2354 if (!isTailCall && Subtarget->isPICStyleGOT())
2355 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2357 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2358 if (Is64Bit && isVarArg && !IsWin64)
2359 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2361 if (InFlag.getNode())
2362 Ops.push_back(InFlag);
2366 //// If this is the first return lowered for this function, add the regs
2367 //// to the liveout set for the function.
2368 // This isn't right, although it's probably harmless on x86; liveouts
2369 // should be computed from returns not tail calls. Consider a void
2370 // function making a tail call to a function returning int.
2371 return DAG.getNode(X86ISD::TC_RETURN, dl,
2372 NodeTys, &Ops[0], Ops.size());
2375 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2376 InFlag = Chain.getValue(1);
2378 // Create the CALLSEQ_END node.
2379 unsigned NumBytesForCalleeToPush;
2380 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2381 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2382 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2383 // If this is a call to a struct-return function, the callee
2384 // pops the hidden struct pointer, so we have to push it back.
2385 // This is common for Darwin/X86, Linux & Mingw32 targets.
2386 NumBytesForCalleeToPush = 4;
2388 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2390 // Returns a flag for retval copy to use.
2392 Chain = DAG.getCALLSEQ_END(Chain,
2393 DAG.getIntPtrConstant(NumBytes, true),
2394 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2397 InFlag = Chain.getValue(1);
2400 // Handle result values, copying them out of physregs into vregs that we
2402 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2403 Ins, dl, DAG, InVals);
2407 //===----------------------------------------------------------------------===//
2408 // Fast Calling Convention (tail call) implementation
2409 //===----------------------------------------------------------------------===//
2411 // Like std call, callee cleans arguments, convention except that ECX is
2412 // reserved for storing the tail called function address. Only 2 registers are
2413 // free for argument passing (inreg). Tail call optimization is performed
2415 // * tailcallopt is enabled
2416 // * caller/callee are fastcc
2417 // On X86_64 architecture with GOT-style position independent code only local
2418 // (within module) calls are supported at the moment.
2419 // To keep the stack aligned according to platform abi the function
2420 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2421 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2422 // If a tail called function callee has more arguments than the caller the
2423 // caller needs to make sure that there is room to move the RETADDR to. This is
2424 // achieved by reserving an area the size of the argument delta right after the
2425 // original REtADDR, but before the saved framepointer or the spilled registers
2426 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2438 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2439 /// for a 16 byte align requirement.
2441 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2442 SelectionDAG& DAG) const {
2443 MachineFunction &MF = DAG.getMachineFunction();
2444 const TargetMachine &TM = MF.getTarget();
2445 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2446 unsigned StackAlignment = TFI.getStackAlignment();
2447 uint64_t AlignMask = StackAlignment - 1;
2448 int64_t Offset = StackSize;
2449 uint64_t SlotSize = TD->getPointerSize();
2450 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2451 // Number smaller than 12 so just add the difference.
2452 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2454 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2455 Offset = ((~AlignMask) & Offset) + StackAlignment +
2456 (StackAlignment-SlotSize);
2461 /// MatchingStackOffset - Return true if the given stack call argument is
2462 /// already available in the same position (relatively) of the caller's
2463 /// incoming argument stack.
2465 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2466 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2467 const X86InstrInfo *TII) {
2468 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2470 if (Arg.getOpcode() == ISD::CopyFromReg) {
2471 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2472 if (!TargetRegisterInfo::isVirtualRegister(VR))
2474 MachineInstr *Def = MRI->getVRegDef(VR);
2477 if (!Flags.isByVal()) {
2478 if (!TII->isLoadFromStackSlot(Def, FI))
2481 unsigned Opcode = Def->getOpcode();
2482 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2483 Def->getOperand(1).isFI()) {
2484 FI = Def->getOperand(1).getIndex();
2485 Bytes = Flags.getByValSize();
2489 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2490 if (Flags.isByVal())
2491 // ByVal argument is passed in as a pointer but it's now being
2492 // dereferenced. e.g.
2493 // define @foo(%struct.X* %A) {
2494 // tail call @bar(%struct.X* byval %A)
2497 SDValue Ptr = Ld->getBasePtr();
2498 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2501 FI = FINode->getIndex();
2502 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2503 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2504 FI = FINode->getIndex();
2505 Bytes = Flags.getByValSize();
2509 assert(FI != INT_MAX);
2510 if (!MFI->isFixedObjectIndex(FI))
2512 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2515 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2516 /// for tail call optimization. Targets which want to do tail call
2517 /// optimization should implement this function.
2519 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2520 CallingConv::ID CalleeCC,
2522 bool isCalleeStructRet,
2523 bool isCallerStructRet,
2524 const SmallVectorImpl<ISD::OutputArg> &Outs,
2525 const SmallVectorImpl<SDValue> &OutVals,
2526 const SmallVectorImpl<ISD::InputArg> &Ins,
2527 SelectionDAG& DAG) const {
2528 if (!IsTailCallConvention(CalleeCC) &&
2529 CalleeCC != CallingConv::C)
2532 // If -tailcallopt is specified, make fastcc functions tail-callable.
2533 const MachineFunction &MF = DAG.getMachineFunction();
2534 const Function *CallerF = DAG.getMachineFunction().getFunction();
2535 CallingConv::ID CallerCC = CallerF->getCallingConv();
2536 bool CCMatch = CallerCC == CalleeCC;
2538 if (GuaranteedTailCallOpt) {
2539 if (IsTailCallConvention(CalleeCC) && CCMatch)
2544 // Look for obvious safe cases to perform tail call optimization that do not
2545 // require ABI changes. This is what gcc calls sibcall.
2547 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2548 // emit a special epilogue.
2549 if (RegInfo->needsStackRealignment(MF))
2552 // Also avoid sibcall optimization if either caller or callee uses struct
2553 // return semantics.
2554 if (isCalleeStructRet || isCallerStructRet)
2557 // An stdcall caller is expected to clean up its arguments; the callee
2558 // isn't going to do that.
2559 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2562 // Do not sibcall optimize vararg calls unless all arguments are passed via
2564 if (isVarArg && !Outs.empty()) {
2566 // Optimizing for varargs on Win64 is unlikely to be safe without
2567 // additional testing.
2568 if (Subtarget->isTargetWin64())
2571 SmallVector<CCValAssign, 16> ArgLocs;
2572 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2573 getTargetMachine(), ArgLocs, *DAG.getContext());
2575 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2576 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2577 if (!ArgLocs[i].isRegLoc())
2581 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2582 // Therefore if it's not used by the call it is not safe to optimize this into
2584 bool Unused = false;
2585 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2592 SmallVector<CCValAssign, 16> RVLocs;
2593 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2594 getTargetMachine(), RVLocs, *DAG.getContext());
2595 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2596 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2597 CCValAssign &VA = RVLocs[i];
2598 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2603 // If the calling conventions do not match, then we'd better make sure the
2604 // results are returned in the same way as what the caller expects.
2606 SmallVector<CCValAssign, 16> RVLocs1;
2607 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2608 getTargetMachine(), RVLocs1, *DAG.getContext());
2609 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2611 SmallVector<CCValAssign, 16> RVLocs2;
2612 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2613 getTargetMachine(), RVLocs2, *DAG.getContext());
2614 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2616 if (RVLocs1.size() != RVLocs2.size())
2618 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2619 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2621 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2623 if (RVLocs1[i].isRegLoc()) {
2624 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2627 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2633 // If the callee takes no arguments then go on to check the results of the
2635 if (!Outs.empty()) {
2636 // Check if stack adjustment is needed. For now, do not do this if any
2637 // argument is passed on the stack.
2638 SmallVector<CCValAssign, 16> ArgLocs;
2639 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2640 getTargetMachine(), ArgLocs, *DAG.getContext());
2642 // Allocate shadow area for Win64
2643 if (Subtarget->isTargetWin64()) {
2644 CCInfo.AllocateStack(32, 8);
2647 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2648 if (CCInfo.getNextStackOffset()) {
2649 MachineFunction &MF = DAG.getMachineFunction();
2650 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2653 // Check if the arguments are already laid out in the right way as
2654 // the caller's fixed stack objects.
2655 MachineFrameInfo *MFI = MF.getFrameInfo();
2656 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2657 const X86InstrInfo *TII =
2658 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2659 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2660 CCValAssign &VA = ArgLocs[i];
2661 SDValue Arg = OutVals[i];
2662 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2663 if (VA.getLocInfo() == CCValAssign::Indirect)
2665 if (!VA.isRegLoc()) {
2666 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2673 // If the tailcall address may be in a register, then make sure it's
2674 // possible to register allocate for it. In 32-bit, the call address can
2675 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2676 // callee-saved registers are restored. These happen to be the same
2677 // registers used to pass 'inreg' arguments so watch out for those.
2678 if (!Subtarget->is64Bit() &&
2679 !isa<GlobalAddressSDNode>(Callee) &&
2680 !isa<ExternalSymbolSDNode>(Callee)) {
2681 unsigned NumInRegs = 0;
2682 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2683 CCValAssign &VA = ArgLocs[i];
2686 unsigned Reg = VA.getLocReg();
2689 case X86::EAX: case X86::EDX: case X86::ECX:
2690 if (++NumInRegs == 3)
2702 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2703 return X86::createFastISel(funcInfo);
2707 //===----------------------------------------------------------------------===//
2708 // Other Lowering Hooks
2709 //===----------------------------------------------------------------------===//
2711 static bool MayFoldLoad(SDValue Op) {
2712 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2715 static bool MayFoldIntoStore(SDValue Op) {
2716 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2719 static bool isTargetShuffle(unsigned Opcode) {
2721 default: return false;
2722 case X86ISD::PSHUFD:
2723 case X86ISD::PSHUFHW:
2724 case X86ISD::PSHUFLW:
2725 case X86ISD::SHUFPD:
2726 case X86ISD::PALIGN:
2727 case X86ISD::SHUFPS:
2728 case X86ISD::MOVLHPS:
2729 case X86ISD::MOVLHPD:
2730 case X86ISD::MOVHLPS:
2731 case X86ISD::MOVLPS:
2732 case X86ISD::MOVLPD:
2733 case X86ISD::MOVSHDUP:
2734 case X86ISD::MOVSLDUP:
2735 case X86ISD::MOVDDUP:
2738 case X86ISD::UNPCKLPS:
2739 case X86ISD::UNPCKLPD:
2740 case X86ISD::VUNPCKLPSY:
2741 case X86ISD::VUNPCKLPDY:
2742 case X86ISD::PUNPCKLWD:
2743 case X86ISD::PUNPCKLBW:
2744 case X86ISD::PUNPCKLDQ:
2745 case X86ISD::PUNPCKLQDQ:
2746 case X86ISD::UNPCKHPS:
2747 case X86ISD::UNPCKHPD:
2748 case X86ISD::VUNPCKHPSY:
2749 case X86ISD::VUNPCKHPDY:
2750 case X86ISD::PUNPCKHWD:
2751 case X86ISD::PUNPCKHBW:
2752 case X86ISD::PUNPCKHDQ:
2753 case X86ISD::PUNPCKHQDQ:
2754 case X86ISD::VPERMILPS:
2755 case X86ISD::VPERMILPSY:
2756 case X86ISD::VPERMILPD:
2757 case X86ISD::VPERMILPDY:
2758 case X86ISD::VPERM2F128:
2764 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2765 SDValue V1, SelectionDAG &DAG) {
2767 default: llvm_unreachable("Unknown x86 shuffle node");
2768 case X86ISD::MOVSHDUP:
2769 case X86ISD::MOVSLDUP:
2770 case X86ISD::MOVDDUP:
2771 return DAG.getNode(Opc, dl, VT, V1);
2777 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2778 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2780 default: llvm_unreachable("Unknown x86 shuffle node");
2781 case X86ISD::PSHUFD:
2782 case X86ISD::PSHUFHW:
2783 case X86ISD::PSHUFLW:
2784 case X86ISD::VPERMILPS:
2785 case X86ISD::VPERMILPSY:
2786 case X86ISD::VPERMILPD:
2787 case X86ISD::VPERMILPDY:
2788 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2794 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2795 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2797 default: llvm_unreachable("Unknown x86 shuffle node");
2798 case X86ISD::PALIGN:
2799 case X86ISD::SHUFPD:
2800 case X86ISD::SHUFPS:
2801 case X86ISD::VPERM2F128:
2802 return DAG.getNode(Opc, dl, VT, V1, V2,
2803 DAG.getConstant(TargetMask, MVT::i8));
2808 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2809 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2811 default: llvm_unreachable("Unknown x86 shuffle node");
2812 case X86ISD::MOVLHPS:
2813 case X86ISD::MOVLHPD:
2814 case X86ISD::MOVHLPS:
2815 case X86ISD::MOVLPS:
2816 case X86ISD::MOVLPD:
2819 case X86ISD::UNPCKLPS:
2820 case X86ISD::UNPCKLPD:
2821 case X86ISD::VUNPCKLPSY:
2822 case X86ISD::VUNPCKLPDY:
2823 case X86ISD::PUNPCKLWD:
2824 case X86ISD::PUNPCKLBW:
2825 case X86ISD::PUNPCKLDQ:
2826 case X86ISD::PUNPCKLQDQ:
2827 case X86ISD::UNPCKHPS:
2828 case X86ISD::UNPCKHPD:
2829 case X86ISD::VUNPCKHPSY:
2830 case X86ISD::VUNPCKHPDY:
2831 case X86ISD::PUNPCKHWD:
2832 case X86ISD::PUNPCKHBW:
2833 case X86ISD::PUNPCKHDQ:
2834 case X86ISD::PUNPCKHQDQ:
2835 return DAG.getNode(Opc, dl, VT, V1, V2);
2840 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2841 MachineFunction &MF = DAG.getMachineFunction();
2842 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2843 int ReturnAddrIndex = FuncInfo->getRAIndex();
2845 if (ReturnAddrIndex == 0) {
2846 // Set up a frame object for the return address.
2847 uint64_t SlotSize = TD->getPointerSize();
2848 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2850 FuncInfo->setRAIndex(ReturnAddrIndex);
2853 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2857 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2858 bool hasSymbolicDisplacement) {
2859 // Offset should fit into 32 bit immediate field.
2860 if (!isInt<32>(Offset))
2863 // If we don't have a symbolic displacement - we don't have any extra
2865 if (!hasSymbolicDisplacement)
2868 // FIXME: Some tweaks might be needed for medium code model.
2869 if (M != CodeModel::Small && M != CodeModel::Kernel)
2872 // For small code model we assume that latest object is 16MB before end of 31
2873 // bits boundary. We may also accept pretty large negative constants knowing
2874 // that all objects are in the positive half of address space.
2875 if (M == CodeModel::Small && Offset < 16*1024*1024)
2878 // For kernel code model we know that all object resist in the negative half
2879 // of 32bits address space. We may not accept negative offsets, since they may
2880 // be just off and we may accept pretty large positive ones.
2881 if (M == CodeModel::Kernel && Offset > 0)
2887 /// isCalleePop - Determines whether the callee is required to pop its
2888 /// own arguments. Callee pop is necessary to support tail calls.
2889 bool X86::isCalleePop(CallingConv::ID CallingConv,
2890 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2894 switch (CallingConv) {
2897 case CallingConv::X86_StdCall:
2899 case CallingConv::X86_FastCall:
2901 case CallingConv::X86_ThisCall:
2903 case CallingConv::Fast:
2905 case CallingConv::GHC:
2910 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2911 /// specific condition code, returning the condition code and the LHS/RHS of the
2912 /// comparison to make.
2913 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2914 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2916 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2917 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2918 // X > -1 -> X == 0, jump !sign.
2919 RHS = DAG.getConstant(0, RHS.getValueType());
2920 return X86::COND_NS;
2921 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2922 // X < 0 -> X == 0, jump on sign.
2924 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2926 RHS = DAG.getConstant(0, RHS.getValueType());
2927 return X86::COND_LE;
2931 switch (SetCCOpcode) {
2932 default: llvm_unreachable("Invalid integer condition!");
2933 case ISD::SETEQ: return X86::COND_E;
2934 case ISD::SETGT: return X86::COND_G;
2935 case ISD::SETGE: return X86::COND_GE;
2936 case ISD::SETLT: return X86::COND_L;
2937 case ISD::SETLE: return X86::COND_LE;
2938 case ISD::SETNE: return X86::COND_NE;
2939 case ISD::SETULT: return X86::COND_B;
2940 case ISD::SETUGT: return X86::COND_A;
2941 case ISD::SETULE: return X86::COND_BE;
2942 case ISD::SETUGE: return X86::COND_AE;
2946 // First determine if it is required or is profitable to flip the operands.
2948 // If LHS is a foldable load, but RHS is not, flip the condition.
2949 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
2950 !ISD::isNON_EXTLoad(RHS.getNode())) {
2951 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2952 std::swap(LHS, RHS);
2955 switch (SetCCOpcode) {
2961 std::swap(LHS, RHS);
2965 // On a floating point condition, the flags are set as follows:
2967 // 0 | 0 | 0 | X > Y
2968 // 0 | 0 | 1 | X < Y
2969 // 1 | 0 | 0 | X == Y
2970 // 1 | 1 | 1 | unordered
2971 switch (SetCCOpcode) {
2972 default: llvm_unreachable("Condcode should be pre-legalized away");
2974 case ISD::SETEQ: return X86::COND_E;
2975 case ISD::SETOLT: // flipped
2977 case ISD::SETGT: return X86::COND_A;
2978 case ISD::SETOLE: // flipped
2980 case ISD::SETGE: return X86::COND_AE;
2981 case ISD::SETUGT: // flipped
2983 case ISD::SETLT: return X86::COND_B;
2984 case ISD::SETUGE: // flipped
2986 case ISD::SETLE: return X86::COND_BE;
2988 case ISD::SETNE: return X86::COND_NE;
2989 case ISD::SETUO: return X86::COND_P;
2990 case ISD::SETO: return X86::COND_NP;
2992 case ISD::SETUNE: return X86::COND_INVALID;
2996 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2997 /// code. Current x86 isa includes the following FP cmov instructions:
2998 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2999 static bool hasFPCMov(unsigned X86CC) {
3015 /// isFPImmLegal - Returns true if the target can instruction select the
3016 /// specified FP immediate natively. If false, the legalizer will
3017 /// materialize the FP immediate as a load from a constant pool.
3018 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3019 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3020 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3026 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3027 /// the specified range (L, H].
3028 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3029 return (Val < 0) || (Val >= Low && Val < Hi);
3032 /// isUndefOrInRange - Return true if every element in Mask, begining
3033 /// from position Pos and ending in Pos+Size, falls within the specified
3034 /// range (L, L+Pos]. or is undef.
3035 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3036 int Pos, int Size, int Low, int Hi) {
3037 for (int i = Pos, e = Pos+Size; i != e; ++i)
3038 if (!isUndefOrInRange(Mask[i], Low, Hi))
3043 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3044 /// specified value.
3045 static bool isUndefOrEqual(int Val, int CmpVal) {
3046 if (Val < 0 || Val == CmpVal)
3051 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3052 /// from position Pos and ending in Pos+Size, falls within the specified
3053 /// sequential range (L, L+Pos]. or is undef.
3054 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3055 int Pos, int Size, int Low) {
3056 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3057 if (!isUndefOrEqual(Mask[i], Low))
3062 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3063 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3064 /// the second operand.
3065 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3066 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3067 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3068 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3069 return (Mask[0] < 2 && Mask[1] < 2);
3073 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3074 SmallVector<int, 8> M;
3076 return ::isPSHUFDMask(M, N->getValueType(0));
3079 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3080 /// is suitable for input to PSHUFHW.
3081 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3082 if (VT != MVT::v8i16)
3085 // Lower quadword copied in order or undef.
3086 for (int i = 0; i != 4; ++i)
3087 if (Mask[i] >= 0 && Mask[i] != i)
3090 // Upper quadword shuffled.
3091 for (int i = 4; i != 8; ++i)
3092 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3098 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3099 SmallVector<int, 8> M;
3101 return ::isPSHUFHWMask(M, N->getValueType(0));
3104 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3105 /// is suitable for input to PSHUFLW.
3106 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3107 if (VT != MVT::v8i16)
3110 // Upper quadword copied in order.
3111 for (int i = 4; i != 8; ++i)
3112 if (Mask[i] >= 0 && Mask[i] != i)
3115 // Lower quadword shuffled.
3116 for (int i = 0; i != 4; ++i)
3123 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3124 SmallVector<int, 8> M;
3126 return ::isPSHUFLWMask(M, N->getValueType(0));
3129 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3130 /// is suitable for input to PALIGNR.
3131 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3133 int i, e = VT.getVectorNumElements();
3134 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64)
3137 // Do not handle v2i64 / v2f64 shuffles with palignr.
3138 if (e < 4 || !hasSSSE3)
3141 for (i = 0; i != e; ++i)
3145 // All undef, not a palignr.
3149 // Make sure we're shifting in the right direction.
3153 int s = Mask[i] - i;
3155 // Check the rest of the elements to see if they are consecutive.
3156 for (++i; i != e; ++i) {
3158 if (m >= 0 && m != s+i)
3164 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3165 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
3166 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3167 int NumElems = VT.getVectorNumElements();
3168 if (NumElems != 2 && NumElems != 4)
3171 int Half = NumElems / 2;
3172 for (int i = 0; i < Half; ++i)
3173 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3175 for (int i = Half; i < NumElems; ++i)
3176 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3182 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3183 SmallVector<int, 8> M;
3185 return ::isSHUFPMask(M, N->getValueType(0));
3188 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3189 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3190 /// half elements to come from vector 1 (which would equal the dest.) and
3191 /// the upper half to come from vector 2.
3192 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3193 int NumElems = VT.getVectorNumElements();
3195 if (NumElems != 2 && NumElems != 4)
3198 int Half = NumElems / 2;
3199 for (int i = 0; i < Half; ++i)
3200 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3202 for (int i = Half; i < NumElems; ++i)
3203 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3208 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3209 SmallVector<int, 8> M;
3211 return isCommutedSHUFPMask(M, N->getValueType(0));
3214 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3215 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3216 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3217 EVT VT = N->getValueType(0);
3218 unsigned NumElems = VT.getVectorNumElements();
3220 if (VT.getSizeInBits() != 128)
3226 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3227 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3228 isUndefOrEqual(N->getMaskElt(1), 7) &&
3229 isUndefOrEqual(N->getMaskElt(2), 2) &&
3230 isUndefOrEqual(N->getMaskElt(3), 3);
3233 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3234 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3236 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3237 EVT VT = N->getValueType(0);
3238 unsigned NumElems = VT.getVectorNumElements();
3240 if (VT.getSizeInBits() != 128)
3246 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3247 isUndefOrEqual(N->getMaskElt(1), 3) &&
3248 isUndefOrEqual(N->getMaskElt(2), 2) &&
3249 isUndefOrEqual(N->getMaskElt(3), 3);
3252 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3253 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3254 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3255 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3257 if (NumElems != 2 && NumElems != 4)
3260 for (unsigned i = 0; i < NumElems/2; ++i)
3261 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3264 for (unsigned i = NumElems/2; i < NumElems; ++i)
3265 if (!isUndefOrEqual(N->getMaskElt(i), i))
3271 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3272 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3273 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3274 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3276 if ((NumElems != 2 && NumElems != 4)
3277 || N->getValueType(0).getSizeInBits() > 128)
3280 for (unsigned i = 0; i < NumElems/2; ++i)
3281 if (!isUndefOrEqual(N->getMaskElt(i), i))
3284 for (unsigned i = 0; i < NumElems/2; ++i)
3285 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3291 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3292 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3293 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3294 bool V2IsSplat = false) {
3295 int NumElts = VT.getVectorNumElements();
3297 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3298 "Unsupported vector type for unpckh");
3300 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3303 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3304 // independently on 128-bit lanes.
3305 unsigned NumLanes = VT.getSizeInBits()/128;
3306 unsigned NumLaneElts = NumElts/NumLanes;
3309 unsigned End = NumLaneElts;
3310 for (unsigned s = 0; s < NumLanes; ++s) {
3311 for (unsigned i = Start, j = s * NumLaneElts;
3315 int BitI1 = Mask[i+1];
3316 if (!isUndefOrEqual(BitI, j))
3319 if (!isUndefOrEqual(BitI1, NumElts))
3322 if (!isUndefOrEqual(BitI1, j + NumElts))
3326 // Process the next 128 bits.
3327 Start += NumLaneElts;
3334 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3335 SmallVector<int, 8> M;
3337 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3340 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3341 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3342 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3343 bool V2IsSplat = false) {
3344 int NumElts = VT.getVectorNumElements();
3346 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3347 "Unsupported vector type for unpckh");
3349 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3352 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3353 // independently on 128-bit lanes.
3354 unsigned NumLanes = VT.getSizeInBits()/128;
3355 unsigned NumLaneElts = NumElts/NumLanes;
3358 unsigned End = NumLaneElts;
3359 for (unsigned l = 0; l != NumLanes; ++l) {
3360 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3361 i != End; i += 2, ++j) {
3363 int BitI1 = Mask[i+1];
3364 if (!isUndefOrEqual(BitI, j))
3367 if (isUndefOrEqual(BitI1, NumElts))
3370 if (!isUndefOrEqual(BitI1, j+NumElts))
3374 // Process the next 128 bits.
3375 Start += NumLaneElts;
3381 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3382 SmallVector<int, 8> M;
3384 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3387 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3388 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3390 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3391 int NumElems = VT.getVectorNumElements();
3392 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3395 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3396 // independently on 128-bit lanes.
3397 unsigned NumLanes = VT.getSizeInBits() / 128;
3398 unsigned NumLaneElts = NumElems / NumLanes;
3400 for (unsigned s = 0; s < NumLanes; ++s) {
3401 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3402 i != NumLaneElts * (s + 1);
3405 int BitI1 = Mask[i+1];
3407 if (!isUndefOrEqual(BitI, j))
3409 if (!isUndefOrEqual(BitI1, j))
3417 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3418 SmallVector<int, 8> M;
3420 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3423 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3424 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3426 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3427 int NumElems = VT.getVectorNumElements();
3428 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3431 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3433 int BitI1 = Mask[i+1];
3434 if (!isUndefOrEqual(BitI, j))
3436 if (!isUndefOrEqual(BitI1, j))
3442 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3443 SmallVector<int, 8> M;
3445 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3448 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3449 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3450 /// MOVSD, and MOVD, i.e. setting the lowest element.
3451 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3452 if (VT.getVectorElementType().getSizeInBits() < 32)
3455 int NumElts = VT.getVectorNumElements();
3457 if (!isUndefOrEqual(Mask[0], NumElts))
3460 for (int i = 1; i < NumElts; ++i)
3461 if (!isUndefOrEqual(Mask[i], i))
3467 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3468 SmallVector<int, 8> M;
3470 return ::isMOVLMask(M, N->getValueType(0));
3473 /// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered
3474 /// as permutations between 128-bit chunks or halves. As an example: this
3476 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3477 /// The first half comes from the second half of V1 and the second half from the
3478 /// the second half of V2.
3479 static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3480 const X86Subtarget *Subtarget) {
3481 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3484 // The shuffle result is divided into half A and half B. In total the two
3485 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3486 // B must come from C, D, E or F.
3487 int HalfSize = VT.getVectorNumElements()/2;
3488 bool MatchA = false, MatchB = false;
3490 // Check if A comes from one of C, D, E, F.
3491 for (int Half = 0; Half < 4; ++Half) {
3492 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3498 // Check if B comes from one of C, D, E, F.
3499 for (int Half = 0; Half < 4; ++Half) {
3500 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3506 return MatchA && MatchB;
3509 /// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle
3510 /// the specified VECTOR_MASK mask with VPERM2F128 instructions.
3511 static unsigned getShuffleVPERM2F128Immediate(SDNode *N) {
3512 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3513 EVT VT = SVOp->getValueType(0);
3515 int HalfSize = VT.getVectorNumElements()/2;
3517 int FstHalf = 0, SndHalf = 0;
3518 for (int i = 0; i < HalfSize; ++i) {
3519 if (SVOp->getMaskElt(i) > 0) {
3520 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3524 for (int i = HalfSize; i < HalfSize*2; ++i) {
3525 if (SVOp->getMaskElt(i) > 0) {
3526 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3531 return (FstHalf | (SndHalf << 4));
3534 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3535 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3536 /// Note that VPERMIL mask matching is different depending whether theunderlying
3537 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3538 /// to the same elements of the low, but to the higher half of the source.
3539 /// In VPERMILPD the two lanes could be shuffled independently of each other
3540 /// with the same restriction that lanes can't be crossed.
3541 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
3542 const X86Subtarget *Subtarget) {
3543 int NumElts = VT.getVectorNumElements();
3544 int NumLanes = VT.getSizeInBits()/128;
3546 if (!Subtarget->hasAVX())
3549 // Match any permutation of 128-bit vector with 64-bit types
3550 if (NumLanes == 1 && NumElts != 2)
3553 // Only match 256-bit with 32 types
3554 if (VT.getSizeInBits() == 256 && NumElts != 4)
3557 // The mask on the high lane is independent of the low. Both can match
3558 // any element in inside its own lane, but can't cross.
3559 int LaneSize = NumElts/NumLanes;
3560 for (int l = 0; l < NumLanes; ++l)
3561 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3562 int LaneStart = l*LaneSize;
3563 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize))
3570 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3571 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*.
3572 /// Note that VPERMIL mask matching is different depending whether theunderlying
3573 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3574 /// to the same elements of the low, but to the higher half of the source.
3575 /// In VPERMILPD the two lanes could be shuffled independently of each other
3576 /// with the same restriction that lanes can't be crossed.
3577 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
3578 const X86Subtarget *Subtarget) {
3579 unsigned NumElts = VT.getVectorNumElements();
3580 unsigned NumLanes = VT.getSizeInBits()/128;
3582 if (!Subtarget->hasAVX())
3585 // Match any permutation of 128-bit vector with 32-bit types
3586 if (NumLanes == 1 && NumElts != 4)
3589 // Only match 256-bit with 32 types
3590 if (VT.getSizeInBits() == 256 && NumElts != 8)
3593 // The mask on the high lane should be the same as the low. Actually,
3594 // they can differ if any of the corresponding index in a lane is undef
3595 // and the other stays in range.
3596 int LaneSize = NumElts/NumLanes;
3597 for (int i = 0; i < LaneSize; ++i) {
3598 int HighElt = i+LaneSize;
3599 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts);
3600 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize);
3602 if (!HighValid || !LowValid)
3604 if (Mask[i] < 0 || Mask[HighElt] < 0)
3606 if (Mask[HighElt]-Mask[i] != LaneSize)
3613 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle
3614 /// the specified VECTOR_MASK mask with VPERMILPS* instructions.
3615 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) {
3616 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3617 EVT VT = SVOp->getValueType(0);
3619 int NumElts = VT.getVectorNumElements();
3620 int NumLanes = VT.getSizeInBits()/128;
3621 int LaneSize = NumElts/NumLanes;
3623 // Although the mask is equal for both lanes do it twice to get the cases
3624 // where a mask will match because the same mask element is undef on the
3625 // first half but valid on the second. This would get pathological cases
3626 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3628 for (int l = 0; l < NumLanes; ++l) {
3629 for (int i = 0; i < LaneSize; ++i) {
3630 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize));
3633 if (MaskElt >= LaneSize)
3634 MaskElt -= LaneSize;
3635 Mask |= MaskElt << (i*2);
3642 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle
3643 /// the specified VECTOR_MASK mask with VPERMILPD* instructions.
3644 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) {
3645 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3646 EVT VT = SVOp->getValueType(0);
3648 int NumElts = VT.getVectorNumElements();
3649 int NumLanes = VT.getSizeInBits()/128;
3652 int LaneSize = NumElts/NumLanes;
3653 for (int l = 0; l < NumLanes; ++l)
3654 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3655 int MaskElt = SVOp->getMaskElt(i);
3658 Mask |= (MaskElt-l*LaneSize) << i;
3664 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3665 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3666 /// element of vector 2 and the other elements to come from vector 1 in order.
3667 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3668 bool V2IsSplat = false, bool V2IsUndef = false) {
3669 int NumOps = VT.getVectorNumElements();
3670 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3673 if (!isUndefOrEqual(Mask[0], 0))
3676 for (int i = 1; i < NumOps; ++i)
3677 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3678 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3679 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3685 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3686 bool V2IsUndef = false) {
3687 SmallVector<int, 8> M;
3689 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3692 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3693 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3694 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3695 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3696 const X86Subtarget *Subtarget) {
3697 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3700 // The second vector must be undef
3701 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3704 EVT VT = N->getValueType(0);
3705 unsigned NumElems = VT.getVectorNumElements();
3707 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3708 (VT.getSizeInBits() == 256 && NumElems != 8))
3711 // "i+1" is the value the indexed mask element must have
3712 for (unsigned i = 0; i < NumElems; i += 2)
3713 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3714 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3720 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3721 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3722 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3723 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3724 const X86Subtarget *Subtarget) {
3725 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3728 // The second vector must be undef
3729 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3732 EVT VT = N->getValueType(0);
3733 unsigned NumElems = VT.getVectorNumElements();
3735 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3736 (VT.getSizeInBits() == 256 && NumElems != 8))
3739 // "i" is the value the indexed mask element must have
3740 for (unsigned i = 0; i < NumElems; i += 2)
3741 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3742 !isUndefOrEqual(N->getMaskElt(i+1), i))
3748 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3749 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3750 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3751 int e = N->getValueType(0).getVectorNumElements() / 2;
3753 for (int i = 0; i < e; ++i)
3754 if (!isUndefOrEqual(N->getMaskElt(i), i))
3756 for (int i = 0; i < e; ++i)
3757 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3762 /// isVEXTRACTF128Index - Return true if the specified
3763 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3764 /// suitable for input to VEXTRACTF128.
3765 bool X86::isVEXTRACTF128Index(SDNode *N) {
3766 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3769 // The index should be aligned on a 128-bit boundary.
3771 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3773 unsigned VL = N->getValueType(0).getVectorNumElements();
3774 unsigned VBits = N->getValueType(0).getSizeInBits();
3775 unsigned ElSize = VBits / VL;
3776 bool Result = (Index * ElSize) % 128 == 0;
3781 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3782 /// operand specifies a subvector insert that is suitable for input to
3784 bool X86::isVINSERTF128Index(SDNode *N) {
3785 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3788 // The index should be aligned on a 128-bit boundary.
3790 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3792 unsigned VL = N->getValueType(0).getVectorNumElements();
3793 unsigned VBits = N->getValueType(0).getSizeInBits();
3794 unsigned ElSize = VBits / VL;
3795 bool Result = (Index * ElSize) % 128 == 0;
3800 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3801 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3802 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3803 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3804 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3806 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3808 for (int i = 0; i < NumOperands; ++i) {
3809 int Val = SVOp->getMaskElt(NumOperands-i-1);
3810 if (Val < 0) Val = 0;
3811 if (Val >= NumOperands) Val -= NumOperands;
3813 if (i != NumOperands - 1)
3819 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3820 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3821 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3822 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3824 // 8 nodes, but we only care about the last 4.
3825 for (unsigned i = 7; i >= 4; --i) {
3826 int Val = SVOp->getMaskElt(i);
3835 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3836 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3837 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3838 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3840 // 8 nodes, but we only care about the first 4.
3841 for (int i = 3; i >= 0; --i) {
3842 int Val = SVOp->getMaskElt(i);
3851 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3852 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3853 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3854 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3855 EVT VVT = N->getValueType(0);
3856 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3860 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3861 Val = SVOp->getMaskElt(i);
3865 assert(Val - i > 0 && "PALIGNR imm should be positive");
3866 return (Val - i) * EltSize;
3869 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3870 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3872 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3873 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3874 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3877 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3879 EVT VecVT = N->getOperand(0).getValueType();
3880 EVT ElVT = VecVT.getVectorElementType();
3882 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3883 return Index / NumElemsPerChunk;
3886 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3887 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3889 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3890 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3891 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3894 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3896 EVT VecVT = N->getValueType(0);
3897 EVT ElVT = VecVT.getVectorElementType();
3899 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3900 return Index / NumElemsPerChunk;
3903 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3905 bool X86::isZeroNode(SDValue Elt) {
3906 return ((isa<ConstantSDNode>(Elt) &&
3907 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3908 (isa<ConstantFPSDNode>(Elt) &&
3909 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3912 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3913 /// their permute mask.
3914 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3915 SelectionDAG &DAG) {
3916 EVT VT = SVOp->getValueType(0);
3917 unsigned NumElems = VT.getVectorNumElements();
3918 SmallVector<int, 8> MaskVec;
3920 for (unsigned i = 0; i != NumElems; ++i) {
3921 int idx = SVOp->getMaskElt(i);
3923 MaskVec.push_back(idx);
3924 else if (idx < (int)NumElems)
3925 MaskVec.push_back(idx + NumElems);
3927 MaskVec.push_back(idx - NumElems);
3929 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3930 SVOp->getOperand(0), &MaskVec[0]);
3933 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3934 /// the two vector operands have swapped position.
3935 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3936 unsigned NumElems = VT.getVectorNumElements();
3937 for (unsigned i = 0; i != NumElems; ++i) {
3941 else if (idx < (int)NumElems)
3942 Mask[i] = idx + NumElems;
3944 Mask[i] = idx - NumElems;
3948 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3949 /// match movhlps. The lower half elements should come from upper half of
3950 /// V1 (and in order), and the upper half elements should come from the upper
3951 /// half of V2 (and in order).
3952 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3953 EVT VT = Op->getValueType(0);
3954 if (VT.getSizeInBits() != 128)
3956 if (VT.getVectorNumElements() != 4)
3958 for (unsigned i = 0, e = 2; i != e; ++i)
3959 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3961 for (unsigned i = 2; i != 4; ++i)
3962 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3967 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3968 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3970 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3971 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3973 N = N->getOperand(0).getNode();
3974 if (!ISD::isNON_EXTLoad(N))
3977 *LD = cast<LoadSDNode>(N);
3981 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3982 /// match movlp{s|d}. The lower half elements should come from lower half of
3983 /// V1 (and in order), and the upper half elements should come from the upper
3984 /// half of V2 (and in order). And since V1 will become the source of the
3985 /// MOVLP, it must be either a vector load or a scalar load to vector.
3986 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3987 ShuffleVectorSDNode *Op) {
3988 EVT VT = Op->getValueType(0);
3989 if (VT.getSizeInBits() != 128)
3992 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3994 // Is V2 is a vector load, don't do this transformation. We will try to use
3995 // load folding shufps op.
3996 if (ISD::isNON_EXTLoad(V2))
3999 unsigned NumElems = VT.getVectorNumElements();
4001 if (NumElems != 2 && NumElems != 4)
4003 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4004 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4006 for (unsigned i = NumElems/2; i != NumElems; ++i)
4007 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4012 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4014 static bool isSplatVector(SDNode *N) {
4015 if (N->getOpcode() != ISD::BUILD_VECTOR)
4018 SDValue SplatValue = N->getOperand(0);
4019 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4020 if (N->getOperand(i) != SplatValue)
4025 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4026 /// to an zero vector.
4027 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4028 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4029 SDValue V1 = N->getOperand(0);
4030 SDValue V2 = N->getOperand(1);
4031 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4032 for (unsigned i = 0; i != NumElems; ++i) {
4033 int Idx = N->getMaskElt(i);
4034 if (Idx >= (int)NumElems) {
4035 unsigned Opc = V2.getOpcode();
4036 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4038 if (Opc != ISD::BUILD_VECTOR ||
4039 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4041 } else if (Idx >= 0) {
4042 unsigned Opc = V1.getOpcode();
4043 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4045 if (Opc != ISD::BUILD_VECTOR ||
4046 !X86::isZeroNode(V1.getOperand(Idx)))
4053 /// getZeroVector - Returns a vector of specified type with all zero elements.
4055 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
4057 assert(VT.isVector() && "Expected a vector type");
4059 // Always build SSE zero vectors as <4 x i32> bitcasted
4060 // to their dest type. This ensures they get CSE'd.
4062 if (VT.getSizeInBits() == 128) { // SSE
4063 if (HasSSE2) { // SSE2
4064 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4065 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4067 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4068 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4070 } else if (VT.getSizeInBits() == 256) { // AVX
4071 // 256-bit logic and arithmetic instructions in AVX are
4072 // all floating-point, no support for integer ops. Default
4073 // to emitting fp zeroed vectors then.
4074 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4075 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4076 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4078 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4081 /// getOnesVector - Returns a vector of specified type with all bits set.
4082 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two
4083 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
4084 /// original type, ensuring they get CSE'd.
4085 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4086 assert(VT.isVector() && "Expected a vector type");
4087 assert((VT.is128BitVector() || VT.is256BitVector())
4088 && "Expected a 128-bit or 256-bit vector type");
4090 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4091 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
4092 Cst, Cst, Cst, Cst);
4094 if (VT.is256BitVector()) {
4095 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4096 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4097 Vec = Insert128BitVector(InsV, Vec,
4098 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4101 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4104 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4105 /// that point to V2 points to its first element.
4106 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4107 EVT VT = SVOp->getValueType(0);
4108 unsigned NumElems = VT.getVectorNumElements();
4110 bool Changed = false;
4111 SmallVector<int, 8> MaskVec;
4112 SVOp->getMask(MaskVec);
4114 for (unsigned i = 0; i != NumElems; ++i) {
4115 if (MaskVec[i] > (int)NumElems) {
4116 MaskVec[i] = NumElems;
4121 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4122 SVOp->getOperand(1), &MaskVec[0]);
4123 return SDValue(SVOp, 0);
4126 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4127 /// operation of specified width.
4128 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4130 unsigned NumElems = VT.getVectorNumElements();
4131 SmallVector<int, 8> Mask;
4132 Mask.push_back(NumElems);
4133 for (unsigned i = 1; i != NumElems; ++i)
4135 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4138 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4139 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4141 unsigned NumElems = VT.getVectorNumElements();
4142 SmallVector<int, 8> Mask;
4143 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4145 Mask.push_back(i + NumElems);
4147 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4150 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4151 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4153 unsigned NumElems = VT.getVectorNumElements();
4154 unsigned Half = NumElems/2;
4155 SmallVector<int, 8> Mask;
4156 for (unsigned i = 0; i != Half; ++i) {
4157 Mask.push_back(i + Half);
4158 Mask.push_back(i + NumElems + Half);
4160 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4163 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4164 // a generic shuffle instruction because the target has no such instructions.
4165 // Generate shuffles which repeat i16 and i8 several times until they can be
4166 // represented by v4f32 and then be manipulated by target suported shuffles.
4167 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4168 EVT VT = V.getValueType();
4169 int NumElems = VT.getVectorNumElements();
4170 DebugLoc dl = V.getDebugLoc();
4172 while (NumElems > 4) {
4173 if (EltNo < NumElems/2) {
4174 V = getUnpackl(DAG, dl, VT, V, V);
4176 V = getUnpackh(DAG, dl, VT, V, V);
4177 EltNo -= NumElems/2;
4184 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4185 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4186 EVT VT = V.getValueType();
4187 DebugLoc dl = V.getDebugLoc();
4188 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4189 && "Vector size not supported");
4191 bool Is128 = VT.getSizeInBits() == 128;
4192 EVT NVT = Is128 ? MVT::v4f32 : MVT::v8f32;
4193 V = DAG.getNode(ISD::BITCAST, dl, NVT, V);
4196 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4197 V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]);
4199 // The second half of indicies refer to the higher part, which is a
4200 // duplication of the lower one. This makes this shuffle a perfect match
4201 // for the VPERM instruction.
4202 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4203 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4204 V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]);
4207 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4210 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4211 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4212 EVT SrcVT = SV->getValueType(0);
4213 SDValue V1 = SV->getOperand(0);
4214 DebugLoc dl = SV->getDebugLoc();
4216 int EltNo = SV->getSplatIndex();
4217 int NumElems = SrcVT.getVectorNumElements();
4218 unsigned Size = SrcVT.getSizeInBits();
4220 // Extract the 128-bit part containing the splat element and update
4221 // the splat element index when it refers to the higher register.
4223 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4224 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4226 EltNo -= NumElems/2;
4229 // All i16 and i8 vector types can't be used directly by a generic shuffle
4230 // instruction because the target has no such instruction. Generate shuffles
4231 // which repeat i16 and i8 several times until they fit in i32, and then can
4232 // be manipulated by target suported shuffles. After the insertion of the
4233 // necessary shuffles, the result is bitcasted back to v4f32 or v8f32.
4234 EVT EltVT = SrcVT.getVectorElementType();
4235 if (NumElems > 4 && (EltVT == MVT::i8 || EltVT == MVT::i16))
4236 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4238 // Recreate the 256-bit vector and place the same 128-bit vector
4239 // into the low and high part. This is necessary because we want
4240 // to use VPERM to shuffle the v8f32 vector, and VPERM only shuffles
4241 // inside each separate v4f32 lane.
4243 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4244 DAG.getConstant(0, MVT::i32), DAG, dl);
4245 V1 = Insert128BitVector(InsV, V1,
4246 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4249 return getLegalSplat(DAG, V1, EltNo);
4252 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4253 /// vector of zero or undef vector. This produces a shuffle where the low
4254 /// element of V2 is swizzled into the zero/undef vector, landing at element
4255 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4256 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4257 bool isZero, bool HasSSE2,
4258 SelectionDAG &DAG) {
4259 EVT VT = V2.getValueType();
4261 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4262 unsigned NumElems = VT.getVectorNumElements();
4263 SmallVector<int, 16> MaskVec;
4264 for (unsigned i = 0; i != NumElems; ++i)
4265 // If this is the insertion idx, put the low elt of V2 here.
4266 MaskVec.push_back(i == Idx ? NumElems : i);
4267 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4270 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4271 /// element of the result of the vector shuffle.
4272 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4275 return SDValue(); // Limit search depth.
4277 SDValue V = SDValue(N, 0);
4278 EVT VT = V.getValueType();
4279 unsigned Opcode = V.getOpcode();
4281 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4282 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4283 Index = SV->getMaskElt(Index);
4286 return DAG.getUNDEF(VT.getVectorElementType());
4288 int NumElems = VT.getVectorNumElements();
4289 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4290 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4293 // Recurse into target specific vector shuffles to find scalars.
4294 if (isTargetShuffle(Opcode)) {
4295 int NumElems = VT.getVectorNumElements();
4296 SmallVector<unsigned, 16> ShuffleMask;
4300 case X86ISD::SHUFPS:
4301 case X86ISD::SHUFPD:
4302 ImmN = N->getOperand(N->getNumOperands()-1);
4303 DecodeSHUFPSMask(NumElems,
4304 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4307 case X86ISD::PUNPCKHBW:
4308 case X86ISD::PUNPCKHWD:
4309 case X86ISD::PUNPCKHDQ:
4310 case X86ISD::PUNPCKHQDQ:
4311 DecodePUNPCKHMask(NumElems, ShuffleMask);
4313 case X86ISD::UNPCKHPS:
4314 case X86ISD::UNPCKHPD:
4315 case X86ISD::VUNPCKHPSY:
4316 case X86ISD::VUNPCKHPDY:
4317 DecodeUNPCKHPMask(NumElems, ShuffleMask);
4319 case X86ISD::PUNPCKLBW:
4320 case X86ISD::PUNPCKLWD:
4321 case X86ISD::PUNPCKLDQ:
4322 case X86ISD::PUNPCKLQDQ:
4323 DecodePUNPCKLMask(VT, ShuffleMask);
4325 case X86ISD::UNPCKLPS:
4326 case X86ISD::UNPCKLPD:
4327 case X86ISD::VUNPCKLPSY:
4328 case X86ISD::VUNPCKLPDY:
4329 DecodeUNPCKLPMask(VT, ShuffleMask);
4331 case X86ISD::MOVHLPS:
4332 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4334 case X86ISD::MOVLHPS:
4335 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4337 case X86ISD::PSHUFD:
4338 ImmN = N->getOperand(N->getNumOperands()-1);
4339 DecodePSHUFMask(NumElems,
4340 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4343 case X86ISD::PSHUFHW:
4344 ImmN = N->getOperand(N->getNumOperands()-1);
4345 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4348 case X86ISD::PSHUFLW:
4349 ImmN = N->getOperand(N->getNumOperands()-1);
4350 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4354 case X86ISD::MOVSD: {
4355 // The index 0 always comes from the first element of the second source,
4356 // this is why MOVSS and MOVSD are used in the first place. The other
4357 // elements come from the other positions of the first source vector.
4358 unsigned OpNum = (Index == 0) ? 1 : 0;
4359 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4362 case X86ISD::VPERMILPS:
4363 ImmN = N->getOperand(N->getNumOperands()-1);
4364 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4367 case X86ISD::VPERMILPSY:
4368 ImmN = N->getOperand(N->getNumOperands()-1);
4369 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4372 case X86ISD::VPERMILPD:
4373 ImmN = N->getOperand(N->getNumOperands()-1);
4374 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4377 case X86ISD::VPERMILPDY:
4378 ImmN = N->getOperand(N->getNumOperands()-1);
4379 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4382 case X86ISD::VPERM2F128:
4383 ImmN = N->getOperand(N->getNumOperands()-1);
4384 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4388 assert("not implemented for target shuffle node");
4392 Index = ShuffleMask[Index];
4394 return DAG.getUNDEF(VT.getVectorElementType());
4396 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4397 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4401 // Actual nodes that may contain scalar elements
4402 if (Opcode == ISD::BITCAST) {
4403 V = V.getOperand(0);
4404 EVT SrcVT = V.getValueType();
4405 unsigned NumElems = VT.getVectorNumElements();
4407 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4411 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4412 return (Index == 0) ? V.getOperand(0)
4413 : DAG.getUNDEF(VT.getVectorElementType());
4415 if (V.getOpcode() == ISD::BUILD_VECTOR)
4416 return V.getOperand(Index);
4421 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4422 /// shuffle operation which come from a consecutively from a zero. The
4423 /// search can start in two different directions, from left or right.
4425 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4426 bool ZerosFromLeft, SelectionDAG &DAG) {
4429 while (i < NumElems) {
4430 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4431 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4432 if (!(Elt.getNode() &&
4433 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4441 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4442 /// MaskE correspond consecutively to elements from one of the vector operands,
4443 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4445 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4446 int OpIdx, int NumElems, unsigned &OpNum) {
4447 bool SeenV1 = false;
4448 bool SeenV2 = false;
4450 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4451 int Idx = SVOp->getMaskElt(i);
4452 // Ignore undef indicies
4461 // Only accept consecutive elements from the same vector
4462 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4466 OpNum = SeenV1 ? 0 : 1;
4470 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4471 /// logical left shift of a vector.
4472 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4473 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4474 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4475 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4476 false /* check zeros from right */, DAG);
4482 // Considering the elements in the mask that are not consecutive zeros,
4483 // check if they consecutively come from only one of the source vectors.
4485 // V1 = {X, A, B, C} 0
4487 // vector_shuffle V1, V2 <1, 2, 3, X>
4489 if (!isShuffleMaskConsecutive(SVOp,
4490 0, // Mask Start Index
4491 NumElems-NumZeros-1, // Mask End Index
4492 NumZeros, // Where to start looking in the src vector
4493 NumElems, // Number of elements in vector
4494 OpSrc)) // Which source operand ?
4499 ShVal = SVOp->getOperand(OpSrc);
4503 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4504 /// logical left shift of a vector.
4505 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4506 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4507 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4508 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4509 true /* check zeros from left */, DAG);
4515 // Considering the elements in the mask that are not consecutive zeros,
4516 // check if they consecutively come from only one of the source vectors.
4518 // 0 { A, B, X, X } = V2
4520 // vector_shuffle V1, V2 <X, X, 4, 5>
4522 if (!isShuffleMaskConsecutive(SVOp,
4523 NumZeros, // Mask Start Index
4524 NumElems-1, // Mask End Index
4525 0, // Where to start looking in the src vector
4526 NumElems, // Number of elements in vector
4527 OpSrc)) // Which source operand ?
4532 ShVal = SVOp->getOperand(OpSrc);
4536 /// isVectorShift - Returns true if the shuffle can be implemented as a
4537 /// logical left or right shift of a vector.
4538 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4539 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4540 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4541 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4547 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4549 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4550 unsigned NumNonZero, unsigned NumZero,
4552 const TargetLowering &TLI) {
4556 DebugLoc dl = Op.getDebugLoc();
4559 for (unsigned i = 0; i < 16; ++i) {
4560 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4561 if (ThisIsNonZero && First) {
4563 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4565 V = DAG.getUNDEF(MVT::v8i16);
4570 SDValue ThisElt(0, 0), LastElt(0, 0);
4571 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4572 if (LastIsNonZero) {
4573 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4574 MVT::i16, Op.getOperand(i-1));
4576 if (ThisIsNonZero) {
4577 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4578 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4579 ThisElt, DAG.getConstant(8, MVT::i8));
4581 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4585 if (ThisElt.getNode())
4586 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4587 DAG.getIntPtrConstant(i/2));
4591 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4594 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4596 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4597 unsigned NumNonZero, unsigned NumZero,
4599 const TargetLowering &TLI) {
4603 DebugLoc dl = Op.getDebugLoc();
4606 for (unsigned i = 0; i < 8; ++i) {
4607 bool isNonZero = (NonZeros & (1 << i)) != 0;
4611 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4613 V = DAG.getUNDEF(MVT::v8i16);
4616 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4617 MVT::v8i16, V, Op.getOperand(i),
4618 DAG.getIntPtrConstant(i));
4625 /// getVShift - Return a vector logical shift node.
4627 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4628 unsigned NumBits, SelectionDAG &DAG,
4629 const TargetLowering &TLI, DebugLoc dl) {
4630 EVT ShVT = MVT::v2i64;
4631 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4632 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4633 return DAG.getNode(ISD::BITCAST, dl, VT,
4634 DAG.getNode(Opc, dl, ShVT, SrcOp,
4635 DAG.getConstant(NumBits,
4636 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4640 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4641 SelectionDAG &DAG) const {
4643 // Check if the scalar load can be widened into a vector load. And if
4644 // the address is "base + cst" see if the cst can be "absorbed" into
4645 // the shuffle mask.
4646 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4647 SDValue Ptr = LD->getBasePtr();
4648 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4650 EVT PVT = LD->getValueType(0);
4651 if (PVT != MVT::i32 && PVT != MVT::f32)
4656 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4657 FI = FINode->getIndex();
4659 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4660 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4661 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4662 Offset = Ptr.getConstantOperandVal(1);
4663 Ptr = Ptr.getOperand(0);
4668 // FIXME: 256-bit vector instructions don't require a strict alignment,
4669 // improve this code to support it better.
4670 unsigned RequiredAlign = VT.getSizeInBits()/8;
4671 SDValue Chain = LD->getChain();
4672 // Make sure the stack object alignment is at least 16 or 32.
4673 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4674 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4675 if (MFI->isFixedObjectIndex(FI)) {
4676 // Can't change the alignment. FIXME: It's possible to compute
4677 // the exact stack offset and reference FI + adjust offset instead.
4678 // If someone *really* cares about this. That's the way to implement it.
4681 MFI->setObjectAlignment(FI, RequiredAlign);
4685 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4686 // Ptr + (Offset & ~15).
4689 if ((Offset % RequiredAlign) & 3)
4691 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4693 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4694 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4696 int EltNo = (Offset - StartOffset) >> 2;
4697 int NumElems = VT.getVectorNumElements();
4699 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4700 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4701 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4702 LD->getPointerInfo().getWithOffset(StartOffset),
4705 // Canonicalize it to a v4i32 or v8i32 shuffle.
4706 SmallVector<int, 8> Mask;
4707 for (int i = 0; i < NumElems; ++i)
4708 Mask.push_back(EltNo);
4710 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4711 return DAG.getNode(ISD::BITCAST, dl, NVT,
4712 DAG.getVectorShuffle(CanonVT, dl, V1,
4713 DAG.getUNDEF(CanonVT),&Mask[0]));
4719 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4720 /// vector of type 'VT', see if the elements can be replaced by a single large
4721 /// load which has the same value as a build_vector whose operands are 'elts'.
4723 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4725 /// FIXME: we'd also like to handle the case where the last elements are zero
4726 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4727 /// There's even a handy isZeroNode for that purpose.
4728 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4729 DebugLoc &DL, SelectionDAG &DAG) {
4730 EVT EltVT = VT.getVectorElementType();
4731 unsigned NumElems = Elts.size();
4733 LoadSDNode *LDBase = NULL;
4734 unsigned LastLoadedElt = -1U;
4736 // For each element in the initializer, see if we've found a load or an undef.
4737 // If we don't find an initial load element, or later load elements are
4738 // non-consecutive, bail out.
4739 for (unsigned i = 0; i < NumElems; ++i) {
4740 SDValue Elt = Elts[i];
4742 if (!Elt.getNode() ||
4743 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4746 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4748 LDBase = cast<LoadSDNode>(Elt.getNode());
4752 if (Elt.getOpcode() == ISD::UNDEF)
4755 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4756 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4761 // If we have found an entire vector of loads and undefs, then return a large
4762 // load of the entire vector width starting at the base pointer. If we found
4763 // consecutive loads for the low half, generate a vzext_load node.
4764 if (LastLoadedElt == NumElems - 1) {
4765 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4766 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4767 LDBase->getPointerInfo(),
4768 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4769 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4770 LDBase->getPointerInfo(),
4771 LDBase->isVolatile(), LDBase->isNonTemporal(),
4772 LDBase->getAlignment());
4773 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4774 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4775 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4776 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4777 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4779 LDBase->getMemOperand());
4780 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4786 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4787 DebugLoc dl = Op.getDebugLoc();
4789 EVT VT = Op.getValueType();
4790 EVT ExtVT = VT.getVectorElementType();
4791 unsigned NumElems = Op.getNumOperands();
4793 // Vectors containing all zeros can be matched by pxor and xorps later
4794 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
4795 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
4796 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
4797 if (Op.getValueType() == MVT::v4i32 ||
4798 Op.getValueType() == MVT::v8i32)
4801 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4804 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
4805 // vectors or broken into v4i32 operations on 256-bit vectors.
4806 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
4807 if (Op.getValueType() == MVT::v4i32)
4810 return getOnesVector(Op.getValueType(), DAG, dl);
4813 unsigned EVTBits = ExtVT.getSizeInBits();
4815 unsigned NumZero = 0;
4816 unsigned NumNonZero = 0;
4817 unsigned NonZeros = 0;
4818 bool IsAllConstants = true;
4819 SmallSet<SDValue, 8> Values;
4820 for (unsigned i = 0; i < NumElems; ++i) {
4821 SDValue Elt = Op.getOperand(i);
4822 if (Elt.getOpcode() == ISD::UNDEF)
4825 if (Elt.getOpcode() != ISD::Constant &&
4826 Elt.getOpcode() != ISD::ConstantFP)
4827 IsAllConstants = false;
4828 if (X86::isZeroNode(Elt))
4831 NonZeros |= (1 << i);
4836 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4837 if (NumNonZero == 0)
4838 return DAG.getUNDEF(VT);
4840 // Special case for single non-zero, non-undef, element.
4841 if (NumNonZero == 1) {
4842 unsigned Idx = CountTrailingZeros_32(NonZeros);
4843 SDValue Item = Op.getOperand(Idx);
4845 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4846 // the value are obviously zero, truncate the value to i32 and do the
4847 // insertion that way. Only do this if the value is non-constant or if the
4848 // value is a constant being inserted into element 0. It is cheaper to do
4849 // a constant pool load than it is to do a movd + shuffle.
4850 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4851 (!IsAllConstants || Idx == 0)) {
4852 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4854 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4855 EVT VecVT = MVT::v4i32;
4856 unsigned VecElts = 4;
4858 // Truncate the value (which may itself be a constant) to i32, and
4859 // convert it to a vector with movd (S2V+shuffle to zero extend).
4860 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4861 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4862 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4863 Subtarget->hasSSE2(), DAG);
4865 // Now we have our 32-bit value zero extended in the low element of
4866 // a vector. If Idx != 0, swizzle it into place.
4868 SmallVector<int, 4> Mask;
4869 Mask.push_back(Idx);
4870 for (unsigned i = 1; i != VecElts; ++i)
4872 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4873 DAG.getUNDEF(Item.getValueType()),
4876 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
4880 // If we have a constant or non-constant insertion into the low element of
4881 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4882 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4883 // depending on what the source datatype is.
4886 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4887 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4888 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4889 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4890 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4891 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4893 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4894 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4895 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
4896 EVT MiddleVT = MVT::v4i32;
4897 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4898 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4899 Subtarget->hasSSE2(), DAG);
4900 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
4904 // Is it a vector logical left shift?
4905 if (NumElems == 2 && Idx == 1 &&
4906 X86::isZeroNode(Op.getOperand(0)) &&
4907 !X86::isZeroNode(Op.getOperand(1))) {
4908 unsigned NumBits = VT.getSizeInBits();
4909 return getVShift(true, VT,
4910 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4911 VT, Op.getOperand(1)),
4912 NumBits/2, DAG, *this, dl);
4915 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4918 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4919 // is a non-constant being inserted into an element other than the low one,
4920 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4921 // movd/movss) to move this into the low element, then shuffle it into
4923 if (EVTBits == 32) {
4924 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4926 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4927 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4928 Subtarget->hasSSE2(), DAG);
4929 SmallVector<int, 8> MaskVec;
4930 for (unsigned i = 0; i < NumElems; i++)
4931 MaskVec.push_back(i == Idx ? 0 : 1);
4932 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4936 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4937 if (Values.size() == 1) {
4938 if (EVTBits == 32) {
4939 // Instead of a shuffle like this:
4940 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4941 // Check if it's possible to issue this instead.
4942 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4943 unsigned Idx = CountTrailingZeros_32(NonZeros);
4944 SDValue Item = Op.getOperand(Idx);
4945 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4946 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4951 // A vector full of immediates; various special cases are already
4952 // handled, so this is best done with a single constant-pool load.
4956 // For AVX-length vectors, build the individual 128-bit pieces and use
4957 // shuffles to put them in place.
4958 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
4959 SmallVector<SDValue, 32> V;
4960 for (unsigned i = 0; i < NumElems; ++i)
4961 V.push_back(Op.getOperand(i));
4963 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
4965 // Build both the lower and upper subvector.
4966 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
4967 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
4970 // Recreate the wider vector with the lower and upper part.
4971 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
4972 DAG.getConstant(0, MVT::i32), DAG, dl);
4973 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
4977 // Let legalizer expand 2-wide build_vectors.
4978 if (EVTBits == 64) {
4979 if (NumNonZero == 1) {
4980 // One half is zero or undef.
4981 unsigned Idx = CountTrailingZeros_32(NonZeros);
4982 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4983 Op.getOperand(Idx));
4984 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4985 Subtarget->hasSSE2(), DAG);
4990 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4991 if (EVTBits == 8 && NumElems == 16) {
4992 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4994 if (V.getNode()) return V;
4997 if (EVTBits == 16 && NumElems == 8) {
4998 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5000 if (V.getNode()) return V;
5003 // If element VT is == 32 bits, turn it into a number of shuffles.
5004 SmallVector<SDValue, 8> V;
5006 if (NumElems == 4 && NumZero > 0) {
5007 for (unsigned i = 0; i < 4; ++i) {
5008 bool isZero = !(NonZeros & (1 << i));
5010 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5012 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5015 for (unsigned i = 0; i < 2; ++i) {
5016 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5019 V[i] = V[i*2]; // Must be a zero vector.
5022 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5025 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5028 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5033 SmallVector<int, 8> MaskVec;
5034 bool Reverse = (NonZeros & 0x3) == 2;
5035 for (unsigned i = 0; i < 2; ++i)
5036 MaskVec.push_back(Reverse ? 1-i : i);
5037 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5038 for (unsigned i = 0; i < 2; ++i)
5039 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5040 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5043 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5044 // Check for a build vector of consecutive loads.
5045 for (unsigned i = 0; i < NumElems; ++i)
5046 V[i] = Op.getOperand(i);
5048 // Check for elements which are consecutive loads.
5049 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5053 // For SSE 4.1, use insertps to put the high elements into the low element.
5054 if (getSubtarget()->hasSSE41()) {
5056 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5057 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5059 Result = DAG.getUNDEF(VT);
5061 for (unsigned i = 1; i < NumElems; ++i) {
5062 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5063 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5064 Op.getOperand(i), DAG.getIntPtrConstant(i));
5069 // Otherwise, expand into a number of unpckl*, start by extending each of
5070 // our (non-undef) elements to the full vector width with the element in the
5071 // bottom slot of the vector (which generates no code for SSE).
5072 for (unsigned i = 0; i < NumElems; ++i) {
5073 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5074 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5076 V[i] = DAG.getUNDEF(VT);
5079 // Next, we iteratively mix elements, e.g. for v4f32:
5080 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5081 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5082 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5083 unsigned EltStride = NumElems >> 1;
5084 while (EltStride != 0) {
5085 for (unsigned i = 0; i < EltStride; ++i) {
5086 // If V[i+EltStride] is undef and this is the first round of mixing,
5087 // then it is safe to just drop this shuffle: V[i] is already in the
5088 // right place, the one element (since it's the first round) being
5089 // inserted as undef can be dropped. This isn't safe for successive
5090 // rounds because they will permute elements within both vectors.
5091 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5092 EltStride == NumElems/2)
5095 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5104 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5105 // them in a MMX register. This is better than doing a stack convert.
5106 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5107 DebugLoc dl = Op.getDebugLoc();
5108 EVT ResVT = Op.getValueType();
5110 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5111 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5113 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5114 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5115 InVec = Op.getOperand(1);
5116 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5117 unsigned NumElts = ResVT.getVectorNumElements();
5118 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5119 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5120 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5122 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5123 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5124 Mask[0] = 0; Mask[1] = 2;
5125 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5127 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5130 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5131 // to create 256-bit vectors from two other 128-bit ones.
5132 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5133 DebugLoc dl = Op.getDebugLoc();
5134 EVT ResVT = Op.getValueType();
5136 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5138 SDValue V1 = Op.getOperand(0);
5139 SDValue V2 = Op.getOperand(1);
5140 unsigned NumElems = ResVT.getVectorNumElements();
5142 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5143 DAG.getConstant(0, MVT::i32), DAG, dl);
5144 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5149 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5150 EVT ResVT = Op.getValueType();
5152 assert(Op.getNumOperands() == 2);
5153 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5154 "Unsupported CONCAT_VECTORS for value type");
5156 // We support concatenate two MMX registers and place them in a MMX register.
5157 // This is better than doing a stack convert.
5158 if (ResVT.is128BitVector())
5159 return LowerMMXCONCAT_VECTORS(Op, DAG);
5161 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5162 // from two other 128-bit ones.
5163 return LowerAVXCONCAT_VECTORS(Op, DAG);
5166 // v8i16 shuffles - Prefer shuffles in the following order:
5167 // 1. [all] pshuflw, pshufhw, optional move
5168 // 2. [ssse3] 1 x pshufb
5169 // 3. [ssse3] 2 x pshufb + 1 x por
5170 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5172 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5173 SelectionDAG &DAG) const {
5174 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5175 SDValue V1 = SVOp->getOperand(0);
5176 SDValue V2 = SVOp->getOperand(1);
5177 DebugLoc dl = SVOp->getDebugLoc();
5178 SmallVector<int, 8> MaskVals;
5180 // Determine if more than 1 of the words in each of the low and high quadwords
5181 // of the result come from the same quadword of one of the two inputs. Undef
5182 // mask values count as coming from any quadword, for better codegen.
5183 SmallVector<unsigned, 4> LoQuad(4);
5184 SmallVector<unsigned, 4> HiQuad(4);
5185 BitVector InputQuads(4);
5186 for (unsigned i = 0; i < 8; ++i) {
5187 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
5188 int EltIdx = SVOp->getMaskElt(i);
5189 MaskVals.push_back(EltIdx);
5198 InputQuads.set(EltIdx / 4);
5201 int BestLoQuad = -1;
5202 unsigned MaxQuad = 1;
5203 for (unsigned i = 0; i < 4; ++i) {
5204 if (LoQuad[i] > MaxQuad) {
5206 MaxQuad = LoQuad[i];
5210 int BestHiQuad = -1;
5212 for (unsigned i = 0; i < 4; ++i) {
5213 if (HiQuad[i] > MaxQuad) {
5215 MaxQuad = HiQuad[i];
5219 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5220 // of the two input vectors, shuffle them into one input vector so only a
5221 // single pshufb instruction is necessary. If There are more than 2 input
5222 // quads, disable the next transformation since it does not help SSSE3.
5223 bool V1Used = InputQuads[0] || InputQuads[1];
5224 bool V2Used = InputQuads[2] || InputQuads[3];
5225 if (Subtarget->hasSSSE3()) {
5226 if (InputQuads.count() == 2 && V1Used && V2Used) {
5227 BestLoQuad = InputQuads.find_first();
5228 BestHiQuad = InputQuads.find_next(BestLoQuad);
5230 if (InputQuads.count() > 2) {
5236 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5237 // the shuffle mask. If a quad is scored as -1, that means that it contains
5238 // words from all 4 input quadwords.
5240 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5241 SmallVector<int, 8> MaskV;
5242 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5243 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5244 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5245 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5246 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5247 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5249 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5250 // source words for the shuffle, to aid later transformations.
5251 bool AllWordsInNewV = true;
5252 bool InOrder[2] = { true, true };
5253 for (unsigned i = 0; i != 8; ++i) {
5254 int idx = MaskVals[i];
5256 InOrder[i/4] = false;
5257 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5259 AllWordsInNewV = false;
5263 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5264 if (AllWordsInNewV) {
5265 for (int i = 0; i != 8; ++i) {
5266 int idx = MaskVals[i];
5269 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5270 if ((idx != i) && idx < 4)
5272 if ((idx != i) && idx > 3)
5281 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5282 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5283 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5284 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5285 unsigned TargetMask = 0;
5286 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5287 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5288 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5289 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5290 V1 = NewV.getOperand(0);
5291 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5295 // If we have SSSE3, and all words of the result are from 1 input vector,
5296 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5297 // is present, fall back to case 4.
5298 if (Subtarget->hasSSSE3()) {
5299 SmallVector<SDValue,16> pshufbMask;
5301 // If we have elements from both input vectors, set the high bit of the
5302 // shuffle mask element to zero out elements that come from V2 in the V1
5303 // mask, and elements that come from V1 in the V2 mask, so that the two
5304 // results can be OR'd together.
5305 bool TwoInputs = V1Used && V2Used;
5306 for (unsigned i = 0; i != 8; ++i) {
5307 int EltIdx = MaskVals[i] * 2;
5308 if (TwoInputs && (EltIdx >= 16)) {
5309 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5310 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5313 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5314 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5316 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5317 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5318 DAG.getNode(ISD::BUILD_VECTOR, dl,
5319 MVT::v16i8, &pshufbMask[0], 16));
5321 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5323 // Calculate the shuffle mask for the second input, shuffle it, and
5324 // OR it with the first shuffled input.
5326 for (unsigned i = 0; i != 8; ++i) {
5327 int EltIdx = MaskVals[i] * 2;
5329 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5330 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5333 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5334 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5336 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5337 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5338 DAG.getNode(ISD::BUILD_VECTOR, dl,
5339 MVT::v16i8, &pshufbMask[0], 16));
5340 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5341 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5344 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5345 // and update MaskVals with new element order.
5346 BitVector InOrder(8);
5347 if (BestLoQuad >= 0) {
5348 SmallVector<int, 8> MaskV;
5349 for (int i = 0; i != 4; ++i) {
5350 int idx = MaskVals[i];
5352 MaskV.push_back(-1);
5354 } else if ((idx / 4) == BestLoQuad) {
5355 MaskV.push_back(idx & 3);
5358 MaskV.push_back(-1);
5361 for (unsigned i = 4; i != 8; ++i)
5363 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5366 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5367 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5369 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5373 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5374 // and update MaskVals with the new element order.
5375 if (BestHiQuad >= 0) {
5376 SmallVector<int, 8> MaskV;
5377 for (unsigned i = 0; i != 4; ++i)
5379 for (unsigned i = 4; i != 8; ++i) {
5380 int idx = MaskVals[i];
5382 MaskV.push_back(-1);
5384 } else if ((idx / 4) == BestHiQuad) {
5385 MaskV.push_back((idx & 3) + 4);
5388 MaskV.push_back(-1);
5391 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5394 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5395 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5397 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5401 // In case BestHi & BestLo were both -1, which means each quadword has a word
5402 // from each of the four input quadwords, calculate the InOrder bitvector now
5403 // before falling through to the insert/extract cleanup.
5404 if (BestLoQuad == -1 && BestHiQuad == -1) {
5406 for (int i = 0; i != 8; ++i)
5407 if (MaskVals[i] < 0 || MaskVals[i] == i)
5411 // The other elements are put in the right place using pextrw and pinsrw.
5412 for (unsigned i = 0; i != 8; ++i) {
5415 int EltIdx = MaskVals[i];
5418 SDValue ExtOp = (EltIdx < 8)
5419 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5420 DAG.getIntPtrConstant(EltIdx))
5421 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5422 DAG.getIntPtrConstant(EltIdx - 8));
5423 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5424 DAG.getIntPtrConstant(i));
5429 // v16i8 shuffles - Prefer shuffles in the following order:
5430 // 1. [ssse3] 1 x pshufb
5431 // 2. [ssse3] 2 x pshufb + 1 x por
5432 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5434 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5436 const X86TargetLowering &TLI) {
5437 SDValue V1 = SVOp->getOperand(0);
5438 SDValue V2 = SVOp->getOperand(1);
5439 DebugLoc dl = SVOp->getDebugLoc();
5440 SmallVector<int, 16> MaskVals;
5441 SVOp->getMask(MaskVals);
5443 // If we have SSSE3, case 1 is generated when all result bytes come from
5444 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5445 // present, fall back to case 3.
5446 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5449 for (unsigned i = 0; i < 16; ++i) {
5450 int EltIdx = MaskVals[i];
5459 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5460 if (TLI.getSubtarget()->hasSSSE3()) {
5461 SmallVector<SDValue,16> pshufbMask;
5463 // If all result elements are from one input vector, then only translate
5464 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5466 // Otherwise, we have elements from both input vectors, and must zero out
5467 // elements that come from V2 in the first mask, and V1 in the second mask
5468 // so that we can OR them together.
5469 bool TwoInputs = !(V1Only || V2Only);
5470 for (unsigned i = 0; i != 16; ++i) {
5471 int EltIdx = MaskVals[i];
5472 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5473 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5476 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5478 // If all the elements are from V2, assign it to V1 and return after
5479 // building the first pshufb.
5482 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5483 DAG.getNode(ISD::BUILD_VECTOR, dl,
5484 MVT::v16i8, &pshufbMask[0], 16));
5488 // Calculate the shuffle mask for the second input, shuffle it, and
5489 // OR it with the first shuffled input.
5491 for (unsigned i = 0; i != 16; ++i) {
5492 int EltIdx = MaskVals[i];
5494 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5497 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5499 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5500 DAG.getNode(ISD::BUILD_VECTOR, dl,
5501 MVT::v16i8, &pshufbMask[0], 16));
5502 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5505 // No SSSE3 - Calculate in place words and then fix all out of place words
5506 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5507 // the 16 different words that comprise the two doublequadword input vectors.
5508 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5509 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5510 SDValue NewV = V2Only ? V2 : V1;
5511 for (int i = 0; i != 8; ++i) {
5512 int Elt0 = MaskVals[i*2];
5513 int Elt1 = MaskVals[i*2+1];
5515 // This word of the result is all undef, skip it.
5516 if (Elt0 < 0 && Elt1 < 0)
5519 // This word of the result is already in the correct place, skip it.
5520 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5522 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5525 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5526 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5529 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5530 // using a single extract together, load it and store it.
5531 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5532 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5533 DAG.getIntPtrConstant(Elt1 / 2));
5534 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5535 DAG.getIntPtrConstant(i));
5539 // If Elt1 is defined, extract it from the appropriate source. If the
5540 // source byte is not also odd, shift the extracted word left 8 bits
5541 // otherwise clear the bottom 8 bits if we need to do an or.
5543 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5544 DAG.getIntPtrConstant(Elt1 / 2));
5545 if ((Elt1 & 1) == 0)
5546 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5548 TLI.getShiftAmountTy(InsElt.getValueType())));
5550 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5551 DAG.getConstant(0xFF00, MVT::i16));
5553 // If Elt0 is defined, extract it from the appropriate source. If the
5554 // source byte is not also even, shift the extracted word right 8 bits. If
5555 // Elt1 was also defined, OR the extracted values together before
5556 // inserting them in the result.
5558 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5559 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5560 if ((Elt0 & 1) != 0)
5561 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5563 TLI.getShiftAmountTy(InsElt0.getValueType())));
5565 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5566 DAG.getConstant(0x00FF, MVT::i16));
5567 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5570 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5571 DAG.getIntPtrConstant(i));
5573 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5576 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5577 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5578 /// done when every pair / quad of shuffle mask elements point to elements in
5579 /// the right sequence. e.g.
5580 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5582 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5583 SelectionDAG &DAG, DebugLoc dl) {
5584 EVT VT = SVOp->getValueType(0);
5585 SDValue V1 = SVOp->getOperand(0);
5586 SDValue V2 = SVOp->getOperand(1);
5587 unsigned NumElems = VT.getVectorNumElements();
5588 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5590 switch (VT.getSimpleVT().SimpleTy) {
5591 default: assert(false && "Unexpected!");
5592 case MVT::v4f32: NewVT = MVT::v2f64; break;
5593 case MVT::v4i32: NewVT = MVT::v2i64; break;
5594 case MVT::v8i16: NewVT = MVT::v4i32; break;
5595 case MVT::v16i8: NewVT = MVT::v4i32; break;
5598 int Scale = NumElems / NewWidth;
5599 SmallVector<int, 8> MaskVec;
5600 for (unsigned i = 0; i < NumElems; i += Scale) {
5602 for (int j = 0; j < Scale; ++j) {
5603 int EltIdx = SVOp->getMaskElt(i+j);
5607 StartIdx = EltIdx - (EltIdx % Scale);
5608 if (EltIdx != StartIdx + j)
5612 MaskVec.push_back(-1);
5614 MaskVec.push_back(StartIdx / Scale);
5617 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5618 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5619 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5622 /// getVZextMovL - Return a zero-extending vector move low node.
5624 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5625 SDValue SrcOp, SelectionDAG &DAG,
5626 const X86Subtarget *Subtarget, DebugLoc dl) {
5627 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5628 LoadSDNode *LD = NULL;
5629 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5630 LD = dyn_cast<LoadSDNode>(SrcOp);
5632 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5634 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5635 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5636 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5637 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5638 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5640 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5641 return DAG.getNode(ISD::BITCAST, dl, VT,
5642 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5643 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5651 return DAG.getNode(ISD::BITCAST, dl, VT,
5652 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5653 DAG.getNode(ISD::BITCAST, dl,
5657 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5658 /// shuffle node referes to only one lane in the sources.
5659 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5660 EVT VT = SVOp->getValueType(0);
5661 int NumElems = VT.getVectorNumElements();
5662 int HalfSize = NumElems/2;
5663 SmallVector<int, 16> M;
5665 bool MatchA = false, MatchB = false;
5667 for (int l = 0; l < NumElems*2; l += HalfSize) {
5668 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5674 for (int l = 0; l < NumElems*2; l += HalfSize) {
5675 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5681 return MatchA && MatchB;
5684 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5685 /// which could not be matched by any known target speficic shuffle
5687 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5688 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5689 // If each half of a vector shuffle node referes to only one lane in the
5690 // source vectors, extract each used 128-bit lane and shuffle them using
5691 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5692 // the work to the legalizer.
5693 DebugLoc dl = SVOp->getDebugLoc();
5694 EVT VT = SVOp->getValueType(0);
5695 int NumElems = VT.getVectorNumElements();
5696 int HalfSize = NumElems/2;
5698 // Extract the reference for each half
5699 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5700 int FstVecOpNum = 0, SndVecOpNum = 0;
5701 for (int i = 0; i < HalfSize; ++i) {
5702 int Elt = SVOp->getMaskElt(i);
5703 if (SVOp->getMaskElt(i) < 0)
5705 FstVecOpNum = Elt/NumElems;
5706 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5709 for (int i = HalfSize; i < NumElems; ++i) {
5710 int Elt = SVOp->getMaskElt(i);
5711 if (SVOp->getMaskElt(i) < 0)
5713 SndVecOpNum = Elt/NumElems;
5714 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5718 // Extract the subvectors
5719 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5720 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5721 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5722 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5724 // Generate 128-bit shuffles
5725 SmallVector<int, 16> MaskV1, MaskV2;
5726 for (int i = 0; i < HalfSize; ++i) {
5727 int Elt = SVOp->getMaskElt(i);
5728 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5730 for (int i = HalfSize; i < NumElems; ++i) {
5731 int Elt = SVOp->getMaskElt(i);
5732 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5735 EVT NVT = V1.getValueType();
5736 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5737 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5739 // Concatenate the result back
5740 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5741 DAG.getConstant(0, MVT::i32), DAG, dl);
5742 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5749 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5750 /// 4 elements, and match them with several different shuffle types.
5752 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5753 SDValue V1 = SVOp->getOperand(0);
5754 SDValue V2 = SVOp->getOperand(1);
5755 DebugLoc dl = SVOp->getDebugLoc();
5756 EVT VT = SVOp->getValueType(0);
5758 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5760 SmallVector<std::pair<int, int>, 8> Locs;
5762 SmallVector<int, 8> Mask1(4U, -1);
5763 SmallVector<int, 8> PermMask;
5764 SVOp->getMask(PermMask);
5768 for (unsigned i = 0; i != 4; ++i) {
5769 int Idx = PermMask[i];
5771 Locs[i] = std::make_pair(-1, -1);
5773 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5775 Locs[i] = std::make_pair(0, NumLo);
5779 Locs[i] = std::make_pair(1, NumHi);
5781 Mask1[2+NumHi] = Idx;
5787 if (NumLo <= 2 && NumHi <= 2) {
5788 // If no more than two elements come from either vector. This can be
5789 // implemented with two shuffles. First shuffle gather the elements.
5790 // The second shuffle, which takes the first shuffle as both of its
5791 // vector operands, put the elements into the right order.
5792 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5794 SmallVector<int, 8> Mask2(4U, -1);
5796 for (unsigned i = 0; i != 4; ++i) {
5797 if (Locs[i].first == -1)
5800 unsigned Idx = (i < 2) ? 0 : 4;
5801 Idx += Locs[i].first * 2 + Locs[i].second;
5806 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5807 } else if (NumLo == 3 || NumHi == 3) {
5808 // Otherwise, we must have three elements from one vector, call it X, and
5809 // one element from the other, call it Y. First, use a shufps to build an
5810 // intermediate vector with the one element from Y and the element from X
5811 // that will be in the same half in the final destination (the indexes don't
5812 // matter). Then, use a shufps to build the final vector, taking the half
5813 // containing the element from Y from the intermediate, and the other half
5816 // Normalize it so the 3 elements come from V1.
5817 CommuteVectorShuffleMask(PermMask, VT);
5821 // Find the element from V2.
5823 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5824 int Val = PermMask[HiIndex];
5831 Mask1[0] = PermMask[HiIndex];
5833 Mask1[2] = PermMask[HiIndex^1];
5835 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5838 Mask1[0] = PermMask[0];
5839 Mask1[1] = PermMask[1];
5840 Mask1[2] = HiIndex & 1 ? 6 : 4;
5841 Mask1[3] = HiIndex & 1 ? 4 : 6;
5842 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5844 Mask1[0] = HiIndex & 1 ? 2 : 0;
5845 Mask1[1] = HiIndex & 1 ? 0 : 2;
5846 Mask1[2] = PermMask[2];
5847 Mask1[3] = PermMask[3];
5852 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5856 // Break it into (shuffle shuffle_hi, shuffle_lo).
5859 SmallVector<int,8> LoMask(4U, -1);
5860 SmallVector<int,8> HiMask(4U, -1);
5862 SmallVector<int,8> *MaskPtr = &LoMask;
5863 unsigned MaskIdx = 0;
5866 for (unsigned i = 0; i != 4; ++i) {
5873 int Idx = PermMask[i];
5875 Locs[i] = std::make_pair(-1, -1);
5876 } else if (Idx < 4) {
5877 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5878 (*MaskPtr)[LoIdx] = Idx;
5881 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5882 (*MaskPtr)[HiIdx] = Idx;
5887 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5888 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5889 SmallVector<int, 8> MaskOps;
5890 for (unsigned i = 0; i != 4; ++i) {
5891 if (Locs[i].first == -1) {
5892 MaskOps.push_back(-1);
5894 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5895 MaskOps.push_back(Idx);
5898 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5901 static bool MayFoldVectorLoad(SDValue V) {
5902 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5903 V = V.getOperand(0);
5904 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5905 V = V.getOperand(0);
5911 // FIXME: the version above should always be used. Since there's
5912 // a bug where several vector shuffles can't be folded because the
5913 // DAG is not updated during lowering and a node claims to have two
5914 // uses while it only has one, use this version, and let isel match
5915 // another instruction if the load really happens to have more than
5916 // one use. Remove this version after this bug get fixed.
5917 // rdar://8434668, PR8156
5918 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5919 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5920 V = V.getOperand(0);
5921 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5922 V = V.getOperand(0);
5923 if (ISD::isNormalLoad(V.getNode()))
5928 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5929 /// a vector extract, and if both can be later optimized into a single load.
5930 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5931 /// here because otherwise a target specific shuffle node is going to be
5932 /// emitted for this shuffle, and the optimization not done.
5933 /// FIXME: This is probably not the best approach, but fix the problem
5934 /// until the right path is decided.
5936 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5937 const TargetLowering &TLI) {
5938 EVT VT = V.getValueType();
5939 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5941 // Be sure that the vector shuffle is present in a pattern like this:
5942 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5946 SDNode *N = *V.getNode()->use_begin();
5947 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5950 SDValue EltNo = N->getOperand(1);
5951 if (!isa<ConstantSDNode>(EltNo))
5954 // If the bit convert changed the number of elements, it is unsafe
5955 // to examine the mask.
5956 bool HasShuffleIntoBitcast = false;
5957 if (V.getOpcode() == ISD::BITCAST) {
5958 EVT SrcVT = V.getOperand(0).getValueType();
5959 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5961 V = V.getOperand(0);
5962 HasShuffleIntoBitcast = true;
5965 // Select the input vector, guarding against out of range extract vector.
5966 unsigned NumElems = VT.getVectorNumElements();
5967 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5968 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5969 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5971 // Skip one more bit_convert if necessary
5972 if (V.getOpcode() == ISD::BITCAST)
5973 V = V.getOperand(0);
5975 if (ISD::isNormalLoad(V.getNode())) {
5976 // Is the original load suitable?
5977 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5979 // FIXME: avoid the multi-use bug that is preventing lots of
5980 // of foldings to be detected, this is still wrong of course, but
5981 // give the temporary desired behavior, and if it happens that
5982 // the load has real more uses, during isel it will not fold, and
5983 // will generate poor code.
5984 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
5987 if (!HasShuffleIntoBitcast)
5990 // If there's a bitcast before the shuffle, check if the load type and
5991 // alignment is valid.
5992 unsigned Align = LN0->getAlignment();
5994 TLI.getTargetData()->getABITypeAlignment(
5995 VT.getTypeForEVT(*DAG.getContext()));
5997 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6005 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6006 EVT VT = Op.getValueType();
6008 // Canonizalize to v2f64.
6009 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6010 return DAG.getNode(ISD::BITCAST, dl, VT,
6011 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6016 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6018 SDValue V1 = Op.getOperand(0);
6019 SDValue V2 = Op.getOperand(1);
6020 EVT VT = Op.getValueType();
6022 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6024 if (HasSSE2 && VT == MVT::v2f64)
6025 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6028 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
6032 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6033 SDValue V1 = Op.getOperand(0);
6034 SDValue V2 = Op.getOperand(1);
6035 EVT VT = Op.getValueType();
6037 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6038 "unsupported shuffle type");
6040 if (V2.getOpcode() == ISD::UNDEF)
6044 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6048 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6049 SDValue V1 = Op.getOperand(0);
6050 SDValue V2 = Op.getOperand(1);
6051 EVT VT = Op.getValueType();
6052 unsigned NumElems = VT.getVectorNumElements();
6054 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6055 // operand of these instructions is only memory, so check if there's a
6056 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6058 bool CanFoldLoad = false;
6060 // Trivial case, when V2 comes from a load.
6061 if (MayFoldVectorLoad(V2))
6064 // When V1 is a load, it can be folded later into a store in isel, example:
6065 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6067 // (MOVLPSmr addr:$src1, VR128:$src2)
6068 // So, recognize this potential and also use MOVLPS or MOVLPD
6069 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6072 // Both of them can't be memory operations though.
6073 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
6074 CanFoldLoad = false;
6077 if (HasSSE2 && NumElems == 2)
6078 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6081 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6084 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6085 // movl and movlp will both match v2i64, but v2i64 is never matched by
6086 // movl earlier because we make it strict to avoid messing with the movlp load
6087 // folding logic (see the code above getMOVLP call). Match it here then,
6088 // this is horrible, but will stay like this until we move all shuffle
6089 // matching to x86 specific nodes. Note that for the 1st condition all
6090 // types are matched with movsd.
6091 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
6092 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6094 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6097 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6099 // Invert the operand order and use SHUFPS to match it.
6100 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
6101 X86::getShuffleSHUFImmediate(SVOp), DAG);
6104 static inline unsigned getUNPCKLOpcode(EVT VT) {
6105 switch(VT.getSimpleVT().SimpleTy) {
6106 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
6107 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
6108 case MVT::v4f32: return X86ISD::UNPCKLPS;
6109 case MVT::v2f64: return X86ISD::UNPCKLPD;
6110 case MVT::v8i32: // Use fp unit for int unpack.
6111 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
6112 case MVT::v4i64: // Use fp unit for int unpack.
6113 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
6114 case MVT::v16i8: return X86ISD::PUNPCKLBW;
6115 case MVT::v8i16: return X86ISD::PUNPCKLWD;
6117 llvm_unreachable("Unknown type for unpckl");
6122 static inline unsigned getUNPCKHOpcode(EVT VT) {
6123 switch(VT.getSimpleVT().SimpleTy) {
6124 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
6125 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
6126 case MVT::v4f32: return X86ISD::UNPCKHPS;
6127 case MVT::v2f64: return X86ISD::UNPCKHPD;
6128 case MVT::v8i32: // Use fp unit for int unpack.
6129 case MVT::v8f32: return X86ISD::VUNPCKHPSY;
6130 case MVT::v4i64: // Use fp unit for int unpack.
6131 case MVT::v4f64: return X86ISD::VUNPCKHPDY;
6132 case MVT::v16i8: return X86ISD::PUNPCKHBW;
6133 case MVT::v8i16: return X86ISD::PUNPCKHWD;
6135 llvm_unreachable("Unknown type for unpckh");
6140 static inline unsigned getVPERMILOpcode(EVT VT) {
6141 switch(VT.getSimpleVT().SimpleTy) {
6143 case MVT::v4f32: return X86ISD::VPERMILPS;
6145 case MVT::v2f64: return X86ISD::VPERMILPD;
6147 case MVT::v8f32: return X86ISD::VPERMILPSY;
6149 case MVT::v4f64: return X86ISD::VPERMILPDY;
6151 llvm_unreachable("Unknown type for vpermil");
6156 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
6157 /// a vbroadcast node. The nodes are suitable whenever we can fold a load coming
6158 /// from a 32 or 64 bit scalar. Update Op to the desired load to be folded.
6159 static bool isVectorBroadcast(SDValue &Op) {
6160 EVT VT = Op.getValueType();
6161 bool Is256 = VT.getSizeInBits() == 256;
6163 assert((VT.getSizeInBits() == 128 || Is256) &&
6164 "Unsupported type for vbroadcast node");
6167 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6168 V = V.getOperand(0);
6170 if (Is256 && !(V.hasOneUse() &&
6171 V.getOpcode() == ISD::INSERT_SUBVECTOR &&
6172 V.getOperand(0).getOpcode() == ISD::UNDEF))
6176 V = V.getOperand(1);
6177 if (V.hasOneUse() && V.getOpcode() != ISD::SCALAR_TO_VECTOR)
6180 // Check the source scalar_to_vector type. 256-bit broadcasts are
6181 // supported for 32/64-bit sizes, while 128-bit ones are only supported
6182 // for 32-bit scalars.
6183 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits();
6184 if (ScalarSize != 32 && ScalarSize != 64)
6186 if (!Is256 && ScalarSize == 64)
6189 V = V.getOperand(0);
6190 if (!MayFoldLoad(V))
6193 // Return the load node
6199 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6200 const TargetLowering &TLI,
6201 const X86Subtarget *Subtarget) {
6202 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6203 EVT VT = Op.getValueType();
6204 DebugLoc dl = Op.getDebugLoc();
6205 SDValue V1 = Op.getOperand(0);
6206 SDValue V2 = Op.getOperand(1);
6208 if (isZeroShuffle(SVOp))
6209 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
6211 // Handle splat operations
6212 if (SVOp->isSplat()) {
6213 unsigned NumElem = VT.getVectorNumElements();
6214 // Special case, this is the only place now where it's allowed to return
6215 // a vector_shuffle operation without using a target specific node, because
6216 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6217 // this be moved to DAGCombine instead?
6218 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6221 // Use vbroadcast whenever the splat comes from a foldable load
6222 if (Subtarget->hasAVX() && isVectorBroadcast(V1))
6223 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1);
6225 // Handle splats by matching through known shuffle masks
6226 if (VT.is128BitVector() && NumElem <= 4)
6229 // All remaning splats are promoted to target supported vector shuffles.
6230 return PromoteSplat(SVOp, DAG);
6233 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6235 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6236 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6237 if (NewOp.getNode())
6238 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6239 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6240 // FIXME: Figure out a cleaner way to do this.
6241 // Try to make use of movq to zero out the top part.
6242 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6243 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6244 if (NewOp.getNode()) {
6245 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6246 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6247 DAG, Subtarget, dl);
6249 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6250 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6251 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6252 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6253 DAG, Subtarget, dl);
6260 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6261 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6262 SDValue V1 = Op.getOperand(0);
6263 SDValue V2 = Op.getOperand(1);
6264 EVT VT = Op.getValueType();
6265 DebugLoc dl = Op.getDebugLoc();
6266 unsigned NumElems = VT.getVectorNumElements();
6267 bool isMMX = VT.getSizeInBits() == 64;
6268 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6269 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6270 bool V1IsSplat = false;
6271 bool V2IsSplat = false;
6272 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
6273 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
6274 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
6275 MachineFunction &MF = DAG.getMachineFunction();
6276 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6278 // Shuffle operations on MMX not supported.
6282 // Vector shuffle lowering takes 3 steps:
6284 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6285 // narrowing and commutation of operands should be handled.
6286 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6288 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6289 // so the shuffle can be broken into other shuffles and the legalizer can
6290 // try the lowering again.
6292 // The general ideia is that no vector_shuffle operation should be left to
6293 // be matched during isel, all of them must be converted to a target specific
6296 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6297 // narrowing and commutation of operands should be handled. The actual code
6298 // doesn't include all of those, work in progress...
6299 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6300 if (NewOp.getNode())
6303 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6304 // unpckh_undef). Only use pshufd if speed is more important than size.
6305 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
6306 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6307 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
6308 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6310 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
6311 RelaxedMayFoldVectorLoad(V1))
6312 return getMOVDDup(Op, dl, V1, DAG);
6314 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6315 return getMOVHighToLow(Op, dl, DAG);
6317 // Use to match splats
6318 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
6319 (VT == MVT::v2f64 || VT == MVT::v2i64))
6320 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6322 if (X86::isPSHUFDMask(SVOp)) {
6323 // The actual implementation will match the mask in the if above and then
6324 // during isel it can match several different instructions, not only pshufd
6325 // as its name says, sad but true, emulate the behavior for now...
6326 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6327 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6329 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6331 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6332 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6334 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6335 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
6338 if (VT == MVT::v4f32)
6339 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
6343 // Check if this can be converted into a logical shift.
6344 bool isLeft = false;
6347 bool isShift = getSubtarget()->hasSSE2() &&
6348 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6349 if (isShift && ShVal.hasOneUse()) {
6350 // If the shifted value has multiple uses, it may be cheaper to use
6351 // v_set0 + movlhps or movhlps, etc.
6352 EVT EltVT = VT.getVectorElementType();
6353 ShAmt *= EltVT.getSizeInBits();
6354 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6357 if (X86::isMOVLMask(SVOp)) {
6360 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6361 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6362 if (!X86::isMOVLPMask(SVOp)) {
6363 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6364 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6366 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6367 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6371 // FIXME: fold these into legal mask.
6372 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
6373 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6375 if (X86::isMOVHLPSMask(SVOp))
6376 return getMOVHighToLow(Op, dl, DAG);
6378 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6379 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6381 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6382 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6384 if (X86::isMOVLPMask(SVOp))
6385 return getMOVLP(Op, dl, DAG, HasSSE2);
6387 if (ShouldXformToMOVHLPS(SVOp) ||
6388 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6389 return CommuteVectorShuffle(SVOp, DAG);
6392 // No better options. Use a vshl / vsrl.
6393 EVT EltVT = VT.getVectorElementType();
6394 ShAmt *= EltVT.getSizeInBits();
6395 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6398 bool Commuted = false;
6399 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6400 // 1,1,1,1 -> v8i16 though.
6401 V1IsSplat = isSplatVector(V1.getNode());
6402 V2IsSplat = isSplatVector(V2.getNode());
6404 // Canonicalize the splat or undef, if present, to be on the RHS.
6405 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
6406 Op = CommuteVectorShuffle(SVOp, DAG);
6407 SVOp = cast<ShuffleVectorSDNode>(Op);
6408 V1 = SVOp->getOperand(0);
6409 V2 = SVOp->getOperand(1);
6410 std::swap(V1IsSplat, V2IsSplat);
6411 std::swap(V1IsUndef, V2IsUndef);
6415 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
6416 // Shuffling low element of v1 into undef, just return v1.
6419 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6420 // the instruction selector will not match, so get a canonical MOVL with
6421 // swapped operands to undo the commute.
6422 return getMOVL(DAG, dl, VT, V2, V1);
6425 if (X86::isUNPCKLMask(SVOp))
6426 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
6428 if (X86::isUNPCKHMask(SVOp))
6429 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
6432 // Normalize mask so all entries that point to V2 points to its first
6433 // element then try to match unpck{h|l} again. If match, return a
6434 // new vector_shuffle with the corrected mask.
6435 SDValue NewMask = NormalizeMask(SVOp, DAG);
6436 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6437 if (NSVOp != SVOp) {
6438 if (X86::isUNPCKLMask(NSVOp, true)) {
6440 } else if (X86::isUNPCKHMask(NSVOp, true)) {
6447 // Commute is back and try unpck* again.
6448 // FIXME: this seems wrong.
6449 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6450 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6452 if (X86::isUNPCKLMask(NewSVOp))
6453 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
6455 if (X86::isUNPCKHMask(NewSVOp))
6456 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
6459 // Normalize the node to match x86 shuffle ops if needed
6460 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
6461 return CommuteVectorShuffle(SVOp, DAG);
6463 // The checks below are all present in isShuffleMaskLegal, but they are
6464 // inlined here right now to enable us to directly emit target specific
6465 // nodes, and remove one by one until they don't return Op anymore.
6466 SmallVector<int, 16> M;
6469 if (isPALIGNRMask(M, VT, HasSSSE3))
6470 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6471 X86::getShufflePALIGNRImmediate(SVOp),
6474 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6475 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6476 if (VT == MVT::v2f64)
6477 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
6478 if (VT == MVT::v2i64)
6479 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
6482 if (isPSHUFHWMask(M, VT))
6483 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6484 X86::getShufflePSHUFHWImmediate(SVOp),
6487 if (isPSHUFLWMask(M, VT))
6488 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6489 X86::getShufflePSHUFLWImmediate(SVOp),
6492 if (isSHUFPMask(M, VT)) {
6493 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6494 if (VT == MVT::v4f32 || VT == MVT::v4i32)
6495 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
6497 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6498 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
6502 if (X86::isUNPCKL_v_undef_Mask(SVOp))
6503 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6504 if (X86::isUNPCKH_v_undef_Mask(SVOp))
6505 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6507 //===--------------------------------------------------------------------===//
6508 // Generate target specific nodes for 128 or 256-bit shuffles only
6509 // supported in the AVX instruction set.
6512 // Handle VPERMILPS* permutations
6513 if (isVPERMILPSMask(M, VT, Subtarget))
6514 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6515 getShuffleVPERMILPSImmediate(SVOp), DAG);
6517 // Handle VPERMILPD* permutations
6518 if (isVPERMILPDMask(M, VT, Subtarget))
6519 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6520 getShuffleVPERMILPDImmediate(SVOp), DAG);
6522 // Handle VPERM2F128 permutations
6523 if (isVPERM2F128Mask(M, VT, Subtarget))
6524 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2,
6525 getShuffleVPERM2F128Immediate(SVOp), DAG);
6527 //===--------------------------------------------------------------------===//
6528 // Since no target specific shuffle was selected for this generic one,
6529 // lower it into other known shuffles. FIXME: this isn't true yet, but
6530 // this is the plan.
6533 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6534 if (VT == MVT::v8i16) {
6535 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6536 if (NewOp.getNode())
6540 if (VT == MVT::v16i8) {
6541 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6542 if (NewOp.getNode())
6546 // Handle all 128-bit wide vectors with 4 elements, and match them with
6547 // several different shuffle types.
6548 if (NumElems == 4 && VT.getSizeInBits() == 128)
6549 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6551 // Handle general 256-bit shuffles
6552 if (VT.is256BitVector())
6553 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6559 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6560 SelectionDAG &DAG) const {
6561 EVT VT = Op.getValueType();
6562 DebugLoc dl = Op.getDebugLoc();
6564 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6567 if (VT.getSizeInBits() == 8) {
6568 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6569 Op.getOperand(0), Op.getOperand(1));
6570 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6571 DAG.getValueType(VT));
6572 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6573 } else if (VT.getSizeInBits() == 16) {
6574 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6575 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6577 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6578 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6579 DAG.getNode(ISD::BITCAST, dl,
6583 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6584 Op.getOperand(0), Op.getOperand(1));
6585 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6586 DAG.getValueType(VT));
6587 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6588 } else if (VT == MVT::f32) {
6589 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6590 // the result back to FR32 register. It's only worth matching if the
6591 // result has a single use which is a store or a bitcast to i32. And in
6592 // the case of a store, it's not worth it if the index is a constant 0,
6593 // because a MOVSSmr can be used instead, which is smaller and faster.
6594 if (!Op.hasOneUse())
6596 SDNode *User = *Op.getNode()->use_begin();
6597 if ((User->getOpcode() != ISD::STORE ||
6598 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6599 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6600 (User->getOpcode() != ISD::BITCAST ||
6601 User->getValueType(0) != MVT::i32))
6603 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6604 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6607 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6608 } else if (VT == MVT::i32) {
6609 // ExtractPS works with constant index.
6610 if (isa<ConstantSDNode>(Op.getOperand(1)))
6618 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6619 SelectionDAG &DAG) const {
6620 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6623 SDValue Vec = Op.getOperand(0);
6624 EVT VecVT = Vec.getValueType();
6626 // If this is a 256-bit vector result, first extract the 128-bit vector and
6627 // then extract the element from the 128-bit vector.
6628 if (VecVT.getSizeInBits() == 256) {
6629 DebugLoc dl = Op.getNode()->getDebugLoc();
6630 unsigned NumElems = VecVT.getVectorNumElements();
6631 SDValue Idx = Op.getOperand(1);
6632 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6634 // Get the 128-bit vector.
6635 bool Upper = IdxVal >= NumElems/2;
6636 Vec = Extract128BitVector(Vec,
6637 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6639 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6640 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6643 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6645 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
6646 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6651 EVT VT = Op.getValueType();
6652 DebugLoc dl = Op.getDebugLoc();
6653 // TODO: handle v16i8.
6654 if (VT.getSizeInBits() == 16) {
6655 SDValue Vec = Op.getOperand(0);
6656 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6658 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6659 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6660 DAG.getNode(ISD::BITCAST, dl,
6663 // Transform it so it match pextrw which produces a 32-bit result.
6664 EVT EltVT = MVT::i32;
6665 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6666 Op.getOperand(0), Op.getOperand(1));
6667 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6668 DAG.getValueType(VT));
6669 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6670 } else if (VT.getSizeInBits() == 32) {
6671 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6675 // SHUFPS the element to the lowest double word, then movss.
6676 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6677 EVT VVT = Op.getOperand(0).getValueType();
6678 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6679 DAG.getUNDEF(VVT), Mask);
6680 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6681 DAG.getIntPtrConstant(0));
6682 } else if (VT.getSizeInBits() == 64) {
6683 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6684 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6685 // to match extract_elt for f64.
6686 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6690 // UNPCKHPD the element to the lowest double word, then movsd.
6691 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6692 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6693 int Mask[2] = { 1, -1 };
6694 EVT VVT = Op.getOperand(0).getValueType();
6695 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6696 DAG.getUNDEF(VVT), Mask);
6697 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6698 DAG.getIntPtrConstant(0));
6705 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6706 SelectionDAG &DAG) const {
6707 EVT VT = Op.getValueType();
6708 EVT EltVT = VT.getVectorElementType();
6709 DebugLoc dl = Op.getDebugLoc();
6711 SDValue N0 = Op.getOperand(0);
6712 SDValue N1 = Op.getOperand(1);
6713 SDValue N2 = Op.getOperand(2);
6715 if (VT.getSizeInBits() == 256)
6718 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6719 isa<ConstantSDNode>(N2)) {
6721 if (VT == MVT::v8i16)
6722 Opc = X86ISD::PINSRW;
6723 else if (VT == MVT::v16i8)
6724 Opc = X86ISD::PINSRB;
6726 Opc = X86ISD::PINSRB;
6728 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6730 if (N1.getValueType() != MVT::i32)
6731 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6732 if (N2.getValueType() != MVT::i32)
6733 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6734 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6735 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6736 // Bits [7:6] of the constant are the source select. This will always be
6737 // zero here. The DAG Combiner may combine an extract_elt index into these
6738 // bits. For example (insert (extract, 3), 2) could be matched by putting
6739 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6740 // Bits [5:4] of the constant are the destination select. This is the
6741 // value of the incoming immediate.
6742 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6743 // combine either bitwise AND or insert of float 0.0 to set these bits.
6744 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6745 // Create this as a scalar to vector..
6746 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6747 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6748 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
6749 // PINSR* works with constant index.
6756 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6757 EVT VT = Op.getValueType();
6758 EVT EltVT = VT.getVectorElementType();
6760 DebugLoc dl = Op.getDebugLoc();
6761 SDValue N0 = Op.getOperand(0);
6762 SDValue N1 = Op.getOperand(1);
6763 SDValue N2 = Op.getOperand(2);
6765 // If this is a 256-bit vector result, first extract the 128-bit vector,
6766 // insert the element into the extracted half and then place it back.
6767 if (VT.getSizeInBits() == 256) {
6768 if (!isa<ConstantSDNode>(N2))
6771 // Get the desired 128-bit vector half.
6772 unsigned NumElems = VT.getVectorNumElements();
6773 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6774 bool Upper = IdxVal >= NumElems/2;
6775 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6776 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6778 // Insert the element into the desired half.
6779 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6780 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6782 // Insert the changed part back to the 256-bit vector
6783 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6786 if (Subtarget->hasSSE41() || Subtarget->hasAVX())
6787 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6789 if (EltVT == MVT::i8)
6792 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6793 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6794 // as its second argument.
6795 if (N1.getValueType() != MVT::i32)
6796 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6797 if (N2.getValueType() != MVT::i32)
6798 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6799 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6805 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6806 LLVMContext *Context = DAG.getContext();
6807 DebugLoc dl = Op.getDebugLoc();
6808 EVT OpVT = Op.getValueType();
6810 // If this is a 256-bit vector result, first insert into a 128-bit
6811 // vector and then insert into the 256-bit vector.
6812 if (OpVT.getSizeInBits() > 128) {
6813 // Insert into a 128-bit vector.
6814 EVT VT128 = EVT::getVectorVT(*Context,
6815 OpVT.getVectorElementType(),
6816 OpVT.getVectorNumElements() / 2);
6818 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6820 // Insert the 128-bit vector.
6821 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6822 DAG.getConstant(0, MVT::i32),
6826 if (Op.getValueType() == MVT::v1i64 &&
6827 Op.getOperand(0).getValueType() == MVT::i64)
6828 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6830 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6831 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6832 "Expected an SSE type!");
6833 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6834 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6837 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6838 // a simple subregister reference or explicit instructions to grab
6839 // upper bits of a vector.
6841 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6842 if (Subtarget->hasAVX()) {
6843 DebugLoc dl = Op.getNode()->getDebugLoc();
6844 SDValue Vec = Op.getNode()->getOperand(0);
6845 SDValue Idx = Op.getNode()->getOperand(1);
6847 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
6848 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
6849 return Extract128BitVector(Vec, Idx, DAG, dl);
6855 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6856 // simple superregister reference or explicit instructions to insert
6857 // the upper bits of a vector.
6859 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6860 if (Subtarget->hasAVX()) {
6861 DebugLoc dl = Op.getNode()->getDebugLoc();
6862 SDValue Vec = Op.getNode()->getOperand(0);
6863 SDValue SubVec = Op.getNode()->getOperand(1);
6864 SDValue Idx = Op.getNode()->getOperand(2);
6866 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
6867 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
6868 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
6874 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
6875 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
6876 // one of the above mentioned nodes. It has to be wrapped because otherwise
6877 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
6878 // be used to form addressing mode. These wrapped nodes will be selected
6881 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
6882 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
6884 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6886 unsigned char OpFlag = 0;
6887 unsigned WrapperKind = X86ISD::Wrapper;
6888 CodeModel::Model M = getTargetMachine().getCodeModel();
6890 if (Subtarget->isPICStyleRIPRel() &&
6891 (M == CodeModel::Small || M == CodeModel::Kernel))
6892 WrapperKind = X86ISD::WrapperRIP;
6893 else if (Subtarget->isPICStyleGOT())
6894 OpFlag = X86II::MO_GOTOFF;
6895 else if (Subtarget->isPICStyleStubPIC())
6896 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6898 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
6900 CP->getOffset(), OpFlag);
6901 DebugLoc DL = CP->getDebugLoc();
6902 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6903 // With PIC, the address is actually $g + Offset.
6905 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6906 DAG.getNode(X86ISD::GlobalBaseReg,
6907 DebugLoc(), getPointerTy()),
6914 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
6915 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
6917 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6919 unsigned char OpFlag = 0;
6920 unsigned WrapperKind = X86ISD::Wrapper;
6921 CodeModel::Model M = getTargetMachine().getCodeModel();
6923 if (Subtarget->isPICStyleRIPRel() &&
6924 (M == CodeModel::Small || M == CodeModel::Kernel))
6925 WrapperKind = X86ISD::WrapperRIP;
6926 else if (Subtarget->isPICStyleGOT())
6927 OpFlag = X86II::MO_GOTOFF;
6928 else if (Subtarget->isPICStyleStubPIC())
6929 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6931 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
6933 DebugLoc DL = JT->getDebugLoc();
6934 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6936 // With PIC, the address is actually $g + Offset.
6938 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6939 DAG.getNode(X86ISD::GlobalBaseReg,
6940 DebugLoc(), getPointerTy()),
6947 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
6948 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
6950 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6952 unsigned char OpFlag = 0;
6953 unsigned WrapperKind = X86ISD::Wrapper;
6954 CodeModel::Model M = getTargetMachine().getCodeModel();
6956 if (Subtarget->isPICStyleRIPRel() &&
6957 (M == CodeModel::Small || M == CodeModel::Kernel)) {
6958 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
6959 OpFlag = X86II::MO_GOTPCREL;
6960 WrapperKind = X86ISD::WrapperRIP;
6961 } else if (Subtarget->isPICStyleGOT()) {
6962 OpFlag = X86II::MO_GOT;
6963 } else if (Subtarget->isPICStyleStubPIC()) {
6964 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
6965 } else if (Subtarget->isPICStyleStubNoDynamic()) {
6966 OpFlag = X86II::MO_DARWIN_NONLAZY;
6969 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
6971 DebugLoc DL = Op.getDebugLoc();
6972 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6975 // With PIC, the address is actually $g + Offset.
6976 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
6977 !Subtarget->is64Bit()) {
6978 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6979 DAG.getNode(X86ISD::GlobalBaseReg,
6980 DebugLoc(), getPointerTy()),
6984 // For symbols that require a load from a stub to get the address, emit the
6986 if (isGlobalStubReference(OpFlag))
6987 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
6988 MachinePointerInfo::getGOT(), false, false, 0);
6994 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
6995 // Create the TargetBlockAddressAddress node.
6996 unsigned char OpFlags =
6997 Subtarget->ClassifyBlockAddressReference();
6998 CodeModel::Model M = getTargetMachine().getCodeModel();
6999 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7000 DebugLoc dl = Op.getDebugLoc();
7001 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7002 /*isTarget=*/true, OpFlags);
7004 if (Subtarget->isPICStyleRIPRel() &&
7005 (M == CodeModel::Small || M == CodeModel::Kernel))
7006 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7008 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7010 // With PIC, the address is actually $g + Offset.
7011 if (isGlobalRelativeToPICBase(OpFlags)) {
7012 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7013 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7021 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7023 SelectionDAG &DAG) const {
7024 // Create the TargetGlobalAddress node, folding in the constant
7025 // offset if it is legal.
7026 unsigned char OpFlags =
7027 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7028 CodeModel::Model M = getTargetMachine().getCodeModel();
7030 if (OpFlags == X86II::MO_NO_FLAG &&
7031 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7032 // A direct static reference to a global.
7033 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7036 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7039 if (Subtarget->isPICStyleRIPRel() &&
7040 (M == CodeModel::Small || M == CodeModel::Kernel))
7041 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7043 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7045 // With PIC, the address is actually $g + Offset.
7046 if (isGlobalRelativeToPICBase(OpFlags)) {
7047 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7048 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7052 // For globals that require a load from a stub to get the address, emit the
7054 if (isGlobalStubReference(OpFlags))
7055 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7056 MachinePointerInfo::getGOT(), false, false, 0);
7058 // If there was a non-zero offset that we didn't fold, create an explicit
7061 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7062 DAG.getConstant(Offset, getPointerTy()));
7068 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7069 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7070 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7071 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7075 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7076 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7077 unsigned char OperandFlags) {
7078 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7079 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7080 DebugLoc dl = GA->getDebugLoc();
7081 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7082 GA->getValueType(0),
7086 SDValue Ops[] = { Chain, TGA, *InFlag };
7087 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7089 SDValue Ops[] = { Chain, TGA };
7090 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7093 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7094 MFI->setAdjustsStack(true);
7096 SDValue Flag = Chain.getValue(1);
7097 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7100 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7102 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7105 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7106 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7107 DAG.getNode(X86ISD::GlobalBaseReg,
7108 DebugLoc(), PtrVT), InFlag);
7109 InFlag = Chain.getValue(1);
7111 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7114 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7116 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7118 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7119 X86::RAX, X86II::MO_TLSGD);
7122 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7123 // "local exec" model.
7124 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7125 const EVT PtrVT, TLSModel::Model model,
7127 DebugLoc dl = GA->getDebugLoc();
7129 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7130 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7131 is64Bit ? 257 : 256));
7133 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7134 DAG.getIntPtrConstant(0),
7135 MachinePointerInfo(Ptr), false, false, 0);
7137 unsigned char OperandFlags = 0;
7138 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7140 unsigned WrapperKind = X86ISD::Wrapper;
7141 if (model == TLSModel::LocalExec) {
7142 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7143 } else if (is64Bit) {
7144 assert(model == TLSModel::InitialExec);
7145 OperandFlags = X86II::MO_GOTTPOFF;
7146 WrapperKind = X86ISD::WrapperRIP;
7148 assert(model == TLSModel::InitialExec);
7149 OperandFlags = X86II::MO_INDNTPOFF;
7152 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7154 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7155 GA->getValueType(0),
7156 GA->getOffset(), OperandFlags);
7157 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7159 if (model == TLSModel::InitialExec)
7160 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7161 MachinePointerInfo::getGOT(), false, false, 0);
7163 // The address of the thread local variable is the add of the thread
7164 // pointer with the offset of the variable.
7165 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7169 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7171 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7172 const GlobalValue *GV = GA->getGlobal();
7174 if (Subtarget->isTargetELF()) {
7175 // TODO: implement the "local dynamic" model
7176 // TODO: implement the "initial exec"model for pic executables
7178 // If GV is an alias then use the aliasee for determining
7179 // thread-localness.
7180 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7181 GV = GA->resolveAliasedGlobal(false);
7183 TLSModel::Model model
7184 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7187 case TLSModel::GeneralDynamic:
7188 case TLSModel::LocalDynamic: // not implemented
7189 if (Subtarget->is64Bit())
7190 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7191 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7193 case TLSModel::InitialExec:
7194 case TLSModel::LocalExec:
7195 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7196 Subtarget->is64Bit());
7198 } else if (Subtarget->isTargetDarwin()) {
7199 // Darwin only has one model of TLS. Lower to that.
7200 unsigned char OpFlag = 0;
7201 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7202 X86ISD::WrapperRIP : X86ISD::Wrapper;
7204 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7206 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7207 !Subtarget->is64Bit();
7209 OpFlag = X86II::MO_TLVP_PIC_BASE;
7211 OpFlag = X86II::MO_TLVP;
7212 DebugLoc DL = Op.getDebugLoc();
7213 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7214 GA->getValueType(0),
7215 GA->getOffset(), OpFlag);
7216 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7218 // With PIC32, the address is actually $g + Offset.
7220 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7221 DAG.getNode(X86ISD::GlobalBaseReg,
7222 DebugLoc(), getPointerTy()),
7225 // Lowering the machine isd will make sure everything is in the right
7227 SDValue Chain = DAG.getEntryNode();
7228 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7229 SDValue Args[] = { Chain, Offset };
7230 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7232 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7233 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7234 MFI->setAdjustsStack(true);
7236 // And our return value (tls address) is in the standard call return value
7238 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7239 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
7243 "TLS not implemented for this target.");
7245 llvm_unreachable("Unreachable");
7250 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7251 /// take a 2 x i32 value to shift plus a shift amount.
7252 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7253 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7254 EVT VT = Op.getValueType();
7255 unsigned VTBits = VT.getSizeInBits();
7256 DebugLoc dl = Op.getDebugLoc();
7257 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7258 SDValue ShOpLo = Op.getOperand(0);
7259 SDValue ShOpHi = Op.getOperand(1);
7260 SDValue ShAmt = Op.getOperand(2);
7261 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7262 DAG.getConstant(VTBits - 1, MVT::i8))
7263 : DAG.getConstant(0, VT);
7266 if (Op.getOpcode() == ISD::SHL_PARTS) {
7267 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7268 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7270 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7271 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7274 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7275 DAG.getConstant(VTBits, MVT::i8));
7276 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7277 AndNode, DAG.getConstant(0, MVT::i8));
7280 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7281 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7282 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7284 if (Op.getOpcode() == ISD::SHL_PARTS) {
7285 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7286 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7288 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7289 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7292 SDValue Ops[2] = { Lo, Hi };
7293 return DAG.getMergeValues(Ops, 2, dl);
7296 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7297 SelectionDAG &DAG) const {
7298 EVT SrcVT = Op.getOperand(0).getValueType();
7300 if (SrcVT.isVector())
7303 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7304 "Unknown SINT_TO_FP to lower!");
7306 // These are really Legal; return the operand so the caller accepts it as
7308 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7310 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7311 Subtarget->is64Bit()) {
7315 DebugLoc dl = Op.getDebugLoc();
7316 unsigned Size = SrcVT.getSizeInBits()/8;
7317 MachineFunction &MF = DAG.getMachineFunction();
7318 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7319 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7320 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7322 MachinePointerInfo::getFixedStack(SSFI),
7324 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7327 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7329 SelectionDAG &DAG) const {
7331 DebugLoc DL = Op.getDebugLoc();
7333 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7335 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7337 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7339 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7341 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7342 MachineMemOperand *MMO;
7344 int SSFI = FI->getIndex();
7346 DAG.getMachineFunction()
7347 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7348 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7350 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7351 StackSlot = StackSlot.getOperand(1);
7353 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7354 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7356 Tys, Ops, array_lengthof(Ops),
7360 Chain = Result.getValue(1);
7361 SDValue InFlag = Result.getValue(2);
7363 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7364 // shouldn't be necessary except that RFP cannot be live across
7365 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7366 MachineFunction &MF = DAG.getMachineFunction();
7367 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7368 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7369 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7370 Tys = DAG.getVTList(MVT::Other);
7372 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7374 MachineMemOperand *MMO =
7375 DAG.getMachineFunction()
7376 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7377 MachineMemOperand::MOStore, SSFISize, SSFISize);
7379 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7380 Ops, array_lengthof(Ops),
7381 Op.getValueType(), MMO);
7382 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7383 MachinePointerInfo::getFixedStack(SSFI),
7390 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7391 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7392 SelectionDAG &DAG) const {
7393 // This algorithm is not obvious. Here it is in C code, more or less:
7395 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7396 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7397 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7399 // Copy ints to xmm registers.
7400 __m128i xh = _mm_cvtsi32_si128( hi );
7401 __m128i xl = _mm_cvtsi32_si128( lo );
7403 // Combine into low half of a single xmm register.
7404 __m128i x = _mm_unpacklo_epi32( xh, xl );
7408 // Merge in appropriate exponents to give the integer bits the right
7410 x = _mm_unpacklo_epi32( x, exp );
7412 // Subtract away the biases to deal with the IEEE-754 double precision
7414 d = _mm_sub_pd( (__m128d) x, bias );
7416 // All conversions up to here are exact. The correctly rounded result is
7417 // calculated using the current rounding mode using the following
7419 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7420 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7421 // store doesn't really need to be here (except
7422 // maybe to zero the other double)
7427 DebugLoc dl = Op.getDebugLoc();
7428 LLVMContext *Context = DAG.getContext();
7430 // Build some magic constants.
7431 std::vector<Constant*> CV0;
7432 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7433 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7434 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7435 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7436 Constant *C0 = ConstantVector::get(CV0);
7437 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7439 std::vector<Constant*> CV1;
7441 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7443 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7444 Constant *C1 = ConstantVector::get(CV1);
7445 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7447 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7448 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7450 DAG.getIntPtrConstant(1)));
7451 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7452 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7454 DAG.getIntPtrConstant(0)));
7455 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7456 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7457 MachinePointerInfo::getConstantPool(),
7459 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7460 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7461 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7462 MachinePointerInfo::getConstantPool(),
7464 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7466 // Add the halves; easiest way is to swap them into another reg first.
7467 int ShufMask[2] = { 1, -1 };
7468 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7469 DAG.getUNDEF(MVT::v2f64), ShufMask);
7470 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7471 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7472 DAG.getIntPtrConstant(0));
7475 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7476 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7477 SelectionDAG &DAG) const {
7478 DebugLoc dl = Op.getDebugLoc();
7479 // FP constant to bias correct the final result.
7480 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7483 // Load the 32-bit value into an XMM register.
7484 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7487 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7488 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7489 DAG.getIntPtrConstant(0));
7491 // Or the load with the bias.
7492 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7493 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7494 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7496 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7497 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7498 MVT::v2f64, Bias)));
7499 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7500 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7501 DAG.getIntPtrConstant(0));
7503 // Subtract the bias.
7504 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7506 // Handle final rounding.
7507 EVT DestVT = Op.getValueType();
7509 if (DestVT.bitsLT(MVT::f64)) {
7510 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7511 DAG.getIntPtrConstant(0));
7512 } else if (DestVT.bitsGT(MVT::f64)) {
7513 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7516 // Handle final rounding.
7520 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7521 SelectionDAG &DAG) const {
7522 SDValue N0 = Op.getOperand(0);
7523 DebugLoc dl = Op.getDebugLoc();
7525 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7526 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7527 // the optimization here.
7528 if (DAG.SignBitIsZero(N0))
7529 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7531 EVT SrcVT = N0.getValueType();
7532 EVT DstVT = Op.getValueType();
7533 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7534 return LowerUINT_TO_FP_i64(Op, DAG);
7535 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7536 return LowerUINT_TO_FP_i32(Op, DAG);
7538 // Make a 64-bit buffer, and use it to build an FILD.
7539 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7540 if (SrcVT == MVT::i32) {
7541 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7542 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7543 getPointerTy(), StackSlot, WordOff);
7544 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7545 StackSlot, MachinePointerInfo(),
7547 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7548 OffsetSlot, MachinePointerInfo(),
7550 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7554 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7555 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7556 StackSlot, MachinePointerInfo(),
7558 // For i64 source, we need to add the appropriate power of 2 if the input
7559 // was negative. This is the same as the optimization in
7560 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7561 // we must be careful to do the computation in x87 extended precision, not
7562 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7563 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7564 MachineMemOperand *MMO =
7565 DAG.getMachineFunction()
7566 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7567 MachineMemOperand::MOLoad, 8, 8);
7569 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7570 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7571 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7574 APInt FF(32, 0x5F800000ULL);
7576 // Check whether the sign bit is set.
7577 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7578 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7581 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7582 SDValue FudgePtr = DAG.getConstantPool(
7583 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7586 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7587 SDValue Zero = DAG.getIntPtrConstant(0);
7588 SDValue Four = DAG.getIntPtrConstant(4);
7589 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7591 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7593 // Load the value out, extending it from f32 to f80.
7594 // FIXME: Avoid the extend by constructing the right constant pool?
7595 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7596 FudgePtr, MachinePointerInfo::getConstantPool(),
7597 MVT::f32, false, false, 4);
7598 // Extend everything to 80 bits to force it to be done on x87.
7599 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7600 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7603 std::pair<SDValue,SDValue> X86TargetLowering::
7604 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7605 DebugLoc DL = Op.getDebugLoc();
7607 EVT DstTy = Op.getValueType();
7610 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7614 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7615 DstTy.getSimpleVT() >= MVT::i16 &&
7616 "Unknown FP_TO_SINT to lower!");
7618 // These are really Legal.
7619 if (DstTy == MVT::i32 &&
7620 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7621 return std::make_pair(SDValue(), SDValue());
7622 if (Subtarget->is64Bit() &&
7623 DstTy == MVT::i64 &&
7624 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7625 return std::make_pair(SDValue(), SDValue());
7627 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7629 MachineFunction &MF = DAG.getMachineFunction();
7630 unsigned MemSize = DstTy.getSizeInBits()/8;
7631 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7632 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7637 switch (DstTy.getSimpleVT().SimpleTy) {
7638 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7639 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7640 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7641 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7644 SDValue Chain = DAG.getEntryNode();
7645 SDValue Value = Op.getOperand(0);
7646 EVT TheVT = Op.getOperand(0).getValueType();
7647 if (isScalarFPTypeInSSEReg(TheVT)) {
7648 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7649 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7650 MachinePointerInfo::getFixedStack(SSFI),
7652 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7654 Chain, StackSlot, DAG.getValueType(TheVT)
7657 MachineMemOperand *MMO =
7658 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7659 MachineMemOperand::MOLoad, MemSize, MemSize);
7660 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7662 Chain = Value.getValue(1);
7663 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7664 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7667 MachineMemOperand *MMO =
7668 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7669 MachineMemOperand::MOStore, MemSize, MemSize);
7671 // Build the FP_TO_INT*_IN_MEM
7672 SDValue Ops[] = { Chain, Value, StackSlot };
7673 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7674 Ops, 3, DstTy, MMO);
7676 return std::make_pair(FIST, StackSlot);
7679 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7680 SelectionDAG &DAG) const {
7681 if (Op.getValueType().isVector())
7684 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7685 SDValue FIST = Vals.first, StackSlot = Vals.second;
7686 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7687 if (FIST.getNode() == 0) return Op;
7690 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7691 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7694 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7695 SelectionDAG &DAG) const {
7696 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7697 SDValue FIST = Vals.first, StackSlot = Vals.second;
7698 assert(FIST.getNode() && "Unexpected failure");
7701 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7702 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7705 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7706 SelectionDAG &DAG) const {
7707 LLVMContext *Context = DAG.getContext();
7708 DebugLoc dl = Op.getDebugLoc();
7709 EVT VT = Op.getValueType();
7712 EltVT = VT.getVectorElementType();
7713 std::vector<Constant*> CV;
7714 if (EltVT == MVT::f64) {
7715 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7719 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7725 Constant *C = ConstantVector::get(CV);
7726 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7727 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7728 MachinePointerInfo::getConstantPool(),
7730 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7733 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7734 LLVMContext *Context = DAG.getContext();
7735 DebugLoc dl = Op.getDebugLoc();
7736 EVT VT = Op.getValueType();
7739 EltVT = VT.getVectorElementType();
7740 std::vector<Constant*> CV;
7741 if (EltVT == MVT::f64) {
7742 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7746 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7752 Constant *C = ConstantVector::get(CV);
7753 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7754 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7755 MachinePointerInfo::getConstantPool(),
7757 if (VT.isVector()) {
7758 return DAG.getNode(ISD::BITCAST, dl, VT,
7759 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
7760 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7762 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
7764 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7768 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7769 LLVMContext *Context = DAG.getContext();
7770 SDValue Op0 = Op.getOperand(0);
7771 SDValue Op1 = Op.getOperand(1);
7772 DebugLoc dl = Op.getDebugLoc();
7773 EVT VT = Op.getValueType();
7774 EVT SrcVT = Op1.getValueType();
7776 // If second operand is smaller, extend it first.
7777 if (SrcVT.bitsLT(VT)) {
7778 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7781 // And if it is bigger, shrink it first.
7782 if (SrcVT.bitsGT(VT)) {
7783 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7787 // At this point the operands and the result should have the same
7788 // type, and that won't be f80 since that is not custom lowered.
7790 // First get the sign bit of second operand.
7791 std::vector<Constant*> CV;
7792 if (SrcVT == MVT::f64) {
7793 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7794 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7796 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7797 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7798 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7799 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7801 Constant *C = ConstantVector::get(CV);
7802 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7803 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7804 MachinePointerInfo::getConstantPool(),
7806 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7808 // Shift sign bit right or left if the two operands have different types.
7809 if (SrcVT.bitsGT(VT)) {
7810 // Op0 is MVT::f32, Op1 is MVT::f64.
7811 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7812 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7813 DAG.getConstant(32, MVT::i32));
7814 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7815 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7816 DAG.getIntPtrConstant(0));
7819 // Clear first operand sign bit.
7821 if (VT == MVT::f64) {
7822 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7823 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7825 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7826 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7827 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7828 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7830 C = ConstantVector::get(CV);
7831 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7832 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7833 MachinePointerInfo::getConstantPool(),
7835 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7837 // Or the value with the sign bit.
7838 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7841 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
7842 SDValue N0 = Op.getOperand(0);
7843 DebugLoc dl = Op.getDebugLoc();
7844 EVT VT = Op.getValueType();
7846 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
7847 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
7848 DAG.getConstant(1, VT));
7849 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
7852 /// Emit nodes that will be selected as "test Op0,Op0", or something
7854 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7855 SelectionDAG &DAG) const {
7856 DebugLoc dl = Op.getDebugLoc();
7858 // CF and OF aren't always set the way we want. Determine which
7859 // of these we need.
7860 bool NeedCF = false;
7861 bool NeedOF = false;
7864 case X86::COND_A: case X86::COND_AE:
7865 case X86::COND_B: case X86::COND_BE:
7868 case X86::COND_G: case X86::COND_GE:
7869 case X86::COND_L: case X86::COND_LE:
7870 case X86::COND_O: case X86::COND_NO:
7875 // See if we can use the EFLAGS value from the operand instead of
7876 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
7877 // we prove that the arithmetic won't overflow, we can't use OF or CF.
7878 if (Op.getResNo() != 0 || NeedOF || NeedCF)
7879 // Emit a CMP with 0, which is the TEST pattern.
7880 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
7881 DAG.getConstant(0, Op.getValueType()));
7883 unsigned Opcode = 0;
7884 unsigned NumOperands = 0;
7885 switch (Op.getNode()->getOpcode()) {
7887 // Due to an isel shortcoming, be conservative if this add is likely to be
7888 // selected as part of a load-modify-store instruction. When the root node
7889 // in a match is a store, isel doesn't know how to remap non-chain non-flag
7890 // uses of other nodes in the match, such as the ADD in this case. This
7891 // leads to the ADD being left around and reselected, with the result being
7892 // two adds in the output. Alas, even if none our users are stores, that
7893 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
7894 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
7895 // climbing the DAG back to the root, and it doesn't seem to be worth the
7897 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7898 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7899 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
7902 if (ConstantSDNode *C =
7903 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
7904 // An add of one will be selected as an INC.
7905 if (C->getAPIntValue() == 1) {
7906 Opcode = X86ISD::INC;
7911 // An add of negative one (subtract of one) will be selected as a DEC.
7912 if (C->getAPIntValue().isAllOnesValue()) {
7913 Opcode = X86ISD::DEC;
7919 // Otherwise use a regular EFLAGS-setting add.
7920 Opcode = X86ISD::ADD;
7924 // If the primary and result isn't used, don't bother using X86ISD::AND,
7925 // because a TEST instruction will be better.
7926 bool NonFlagUse = false;
7927 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7928 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
7930 unsigned UOpNo = UI.getOperandNo();
7931 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
7932 // Look pass truncate.
7933 UOpNo = User->use_begin().getOperandNo();
7934 User = *User->use_begin();
7937 if (User->getOpcode() != ISD::BRCOND &&
7938 User->getOpcode() != ISD::SETCC &&
7939 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
7952 // Due to the ISEL shortcoming noted above, be conservative if this op is
7953 // likely to be selected as part of a load-modify-store instruction.
7954 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7955 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7956 if (UI->getOpcode() == ISD::STORE)
7959 // Otherwise use a regular EFLAGS-setting instruction.
7960 switch (Op.getNode()->getOpcode()) {
7961 default: llvm_unreachable("unexpected operator!");
7962 case ISD::SUB: Opcode = X86ISD::SUB; break;
7963 case ISD::OR: Opcode = X86ISD::OR; break;
7964 case ISD::XOR: Opcode = X86ISD::XOR; break;
7965 case ISD::AND: Opcode = X86ISD::AND; break;
7977 return SDValue(Op.getNode(), 1);
7984 // Emit a CMP with 0, which is the TEST pattern.
7985 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
7986 DAG.getConstant(0, Op.getValueType()));
7988 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
7989 SmallVector<SDValue, 4> Ops;
7990 for (unsigned i = 0; i != NumOperands; ++i)
7991 Ops.push_back(Op.getOperand(i));
7993 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
7994 DAG.ReplaceAllUsesWith(Op, New);
7995 return SDValue(New.getNode(), 1);
7998 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8000 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8001 SelectionDAG &DAG) const {
8002 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8003 if (C->getAPIntValue() == 0)
8004 return EmitTest(Op0, X86CC, DAG);
8006 DebugLoc dl = Op0.getDebugLoc();
8007 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8010 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8011 /// if it's possible.
8012 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8013 DebugLoc dl, SelectionDAG &DAG) const {
8014 SDValue Op0 = And.getOperand(0);
8015 SDValue Op1 = And.getOperand(1);
8016 if (Op0.getOpcode() == ISD::TRUNCATE)
8017 Op0 = Op0.getOperand(0);
8018 if (Op1.getOpcode() == ISD::TRUNCATE)
8019 Op1 = Op1.getOperand(0);
8022 if (Op1.getOpcode() == ISD::SHL)
8023 std::swap(Op0, Op1);
8024 if (Op0.getOpcode() == ISD::SHL) {
8025 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8026 if (And00C->getZExtValue() == 1) {
8027 // If we looked past a truncate, check that it's only truncating away
8029 unsigned BitWidth = Op0.getValueSizeInBits();
8030 unsigned AndBitWidth = And.getValueSizeInBits();
8031 if (BitWidth > AndBitWidth) {
8032 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8033 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8034 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8038 RHS = Op0.getOperand(1);
8040 } else if (Op1.getOpcode() == ISD::Constant) {
8041 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8042 SDValue AndLHS = Op0;
8043 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
8044 LHS = AndLHS.getOperand(0);
8045 RHS = AndLHS.getOperand(1);
8049 if (LHS.getNode()) {
8050 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8051 // instruction. Since the shift amount is in-range-or-undefined, we know
8052 // that doing a bittest on the i32 value is ok. We extend to i32 because
8053 // the encoding for the i16 version is larger than the i32 version.
8054 // Also promote i16 to i32 for performance / code size reason.
8055 if (LHS.getValueType() == MVT::i8 ||
8056 LHS.getValueType() == MVT::i16)
8057 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8059 // If the operand types disagree, extend the shift amount to match. Since
8060 // BT ignores high bits (like shifts) we can use anyextend.
8061 if (LHS.getValueType() != RHS.getValueType())
8062 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8064 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8065 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8066 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8067 DAG.getConstant(Cond, MVT::i8), BT);
8073 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8074 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8075 SDValue Op0 = Op.getOperand(0);
8076 SDValue Op1 = Op.getOperand(1);
8077 DebugLoc dl = Op.getDebugLoc();
8078 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8080 // Optimize to BT if possible.
8081 // Lower (X & (1 << N)) == 0 to BT(X, N).
8082 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8083 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8084 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8085 Op1.getOpcode() == ISD::Constant &&
8086 cast<ConstantSDNode>(Op1)->isNullValue() &&
8087 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8088 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8089 if (NewSetCC.getNode())
8093 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8095 if (Op1.getOpcode() == ISD::Constant &&
8096 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8097 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8098 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8100 // If the input is a setcc, then reuse the input setcc or use a new one with
8101 // the inverted condition.
8102 if (Op0.getOpcode() == X86ISD::SETCC) {
8103 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8104 bool Invert = (CC == ISD::SETNE) ^
8105 cast<ConstantSDNode>(Op1)->isNullValue();
8106 if (!Invert) return Op0;
8108 CCode = X86::GetOppositeBranchCondition(CCode);
8109 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8110 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8114 bool isFP = Op1.getValueType().isFloatingPoint();
8115 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8116 if (X86CC == X86::COND_INVALID)
8119 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8120 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8121 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8124 // Lower256IntVETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8125 // ones, and then concatenate the result back.
8126 static SDValue Lower256IntVETCC(SDValue Op, SelectionDAG &DAG) {
8127 EVT VT = Op.getValueType();
8129 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::VSETCC &&
8130 "Unsupported value type for operation");
8132 int NumElems = VT.getVectorNumElements();
8133 DebugLoc dl = Op.getDebugLoc();
8134 SDValue CC = Op.getOperand(2);
8135 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8136 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8138 // Extract the LHS vectors
8139 SDValue LHS = Op.getOperand(0);
8140 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8141 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8143 // Extract the RHS vectors
8144 SDValue RHS = Op.getOperand(1);
8145 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8146 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8148 // Issue the operation on the smaller types and concatenate the result back
8149 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8150 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8151 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8152 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8153 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8157 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8159 SDValue Op0 = Op.getOperand(0);
8160 SDValue Op1 = Op.getOperand(1);
8161 SDValue CC = Op.getOperand(2);
8162 EVT VT = Op.getValueType();
8163 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8164 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8165 DebugLoc dl = Op.getDebugLoc();
8169 EVT EltVT = Op0.getValueType().getVectorElementType();
8170 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8172 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8175 switch (SetCCOpcode) {
8178 case ISD::SETEQ: SSECC = 0; break;
8180 case ISD::SETGT: Swap = true; // Fallthrough
8182 case ISD::SETOLT: SSECC = 1; break;
8184 case ISD::SETGE: Swap = true; // Fallthrough
8186 case ISD::SETOLE: SSECC = 2; break;
8187 case ISD::SETUO: SSECC = 3; break;
8189 case ISD::SETNE: SSECC = 4; break;
8190 case ISD::SETULE: Swap = true;
8191 case ISD::SETUGE: SSECC = 5; break;
8192 case ISD::SETULT: Swap = true;
8193 case ISD::SETUGT: SSECC = 6; break;
8194 case ISD::SETO: SSECC = 7; break;
8197 std::swap(Op0, Op1);
8199 // In the two special cases we can't handle, emit two comparisons.
8201 if (SetCCOpcode == ISD::SETUEQ) {
8203 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8204 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8205 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8207 else if (SetCCOpcode == ISD::SETONE) {
8209 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8210 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8211 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8213 llvm_unreachable("Illegal FP comparison");
8215 // Handle all other FP comparisons here.
8216 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8219 // Break 256-bit integer vector compare into smaller ones.
8220 if (!isFP && VT.getSizeInBits() == 256)
8221 return Lower256IntVETCC(Op, DAG);
8223 // We are handling one of the integer comparisons here. Since SSE only has
8224 // GT and EQ comparisons for integer, swapping operands and multiple
8225 // operations may be required for some comparisons.
8226 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8227 bool Swap = false, Invert = false, FlipSigns = false;
8229 switch (VT.getSimpleVT().SimpleTy) {
8231 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8232 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8233 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8234 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8237 switch (SetCCOpcode) {
8239 case ISD::SETNE: Invert = true;
8240 case ISD::SETEQ: Opc = EQOpc; break;
8241 case ISD::SETLT: Swap = true;
8242 case ISD::SETGT: Opc = GTOpc; break;
8243 case ISD::SETGE: Swap = true;
8244 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8245 case ISD::SETULT: Swap = true;
8246 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8247 case ISD::SETUGE: Swap = true;
8248 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8251 std::swap(Op0, Op1);
8253 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8254 // bits of the inputs before performing those operations.
8256 EVT EltVT = VT.getVectorElementType();
8257 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8259 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8260 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8262 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8263 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8266 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8268 // If the logical-not of the result is required, perform that now.
8270 Result = DAG.getNOT(dl, Result, VT);
8275 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8276 static bool isX86LogicalCmp(SDValue Op) {
8277 unsigned Opc = Op.getNode()->getOpcode();
8278 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8280 if (Op.getResNo() == 1 &&
8281 (Opc == X86ISD::ADD ||
8282 Opc == X86ISD::SUB ||
8283 Opc == X86ISD::ADC ||
8284 Opc == X86ISD::SBB ||
8285 Opc == X86ISD::SMUL ||
8286 Opc == X86ISD::UMUL ||
8287 Opc == X86ISD::INC ||
8288 Opc == X86ISD::DEC ||
8289 Opc == X86ISD::OR ||
8290 Opc == X86ISD::XOR ||
8291 Opc == X86ISD::AND))
8294 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8300 static bool isZero(SDValue V) {
8301 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8302 return C && C->isNullValue();
8305 static bool isAllOnes(SDValue V) {
8306 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8307 return C && C->isAllOnesValue();
8310 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8311 bool addTest = true;
8312 SDValue Cond = Op.getOperand(0);
8313 SDValue Op1 = Op.getOperand(1);
8314 SDValue Op2 = Op.getOperand(2);
8315 DebugLoc DL = Op.getDebugLoc();
8318 if (Cond.getOpcode() == ISD::SETCC) {
8319 SDValue NewCond = LowerSETCC(Cond, DAG);
8320 if (NewCond.getNode())
8324 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8325 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8326 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8327 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8328 if (Cond.getOpcode() == X86ISD::SETCC &&
8329 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8330 isZero(Cond.getOperand(1).getOperand(1))) {
8331 SDValue Cmp = Cond.getOperand(1);
8333 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8335 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8336 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8337 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8339 SDValue CmpOp0 = Cmp.getOperand(0);
8340 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8341 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8343 SDValue Res = // Res = 0 or -1.
8344 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8345 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8347 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8348 Res = DAG.getNOT(DL, Res, Res.getValueType());
8350 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8351 if (N2C == 0 || !N2C->isNullValue())
8352 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8357 // Look past (and (setcc_carry (cmp ...)), 1).
8358 if (Cond.getOpcode() == ISD::AND &&
8359 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8360 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8361 if (C && C->getAPIntValue() == 1)
8362 Cond = Cond.getOperand(0);
8365 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8366 // setting operand in place of the X86ISD::SETCC.
8367 if (Cond.getOpcode() == X86ISD::SETCC ||
8368 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8369 CC = Cond.getOperand(0);
8371 SDValue Cmp = Cond.getOperand(1);
8372 unsigned Opc = Cmp.getOpcode();
8373 EVT VT = Op.getValueType();
8375 bool IllegalFPCMov = false;
8376 if (VT.isFloatingPoint() && !VT.isVector() &&
8377 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8378 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8380 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8381 Opc == X86ISD::BT) { // FIXME
8388 // Look pass the truncate.
8389 if (Cond.getOpcode() == ISD::TRUNCATE)
8390 Cond = Cond.getOperand(0);
8392 // We know the result of AND is compared against zero. Try to match
8394 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8395 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8396 if (NewSetCC.getNode()) {
8397 CC = NewSetCC.getOperand(0);
8398 Cond = NewSetCC.getOperand(1);
8405 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8406 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8409 // a < b ? -1 : 0 -> RES = ~setcc_carry
8410 // a < b ? 0 : -1 -> RES = setcc_carry
8411 // a >= b ? -1 : 0 -> RES = setcc_carry
8412 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8413 if (Cond.getOpcode() == X86ISD::CMP) {
8414 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8416 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8417 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8418 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8419 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8420 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8421 return DAG.getNOT(DL, Res, Res.getValueType());
8426 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8427 // condition is true.
8428 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8429 SDValue Ops[] = { Op2, Op1, CC, Cond };
8430 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8433 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8434 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8435 // from the AND / OR.
8436 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8437 Opc = Op.getOpcode();
8438 if (Opc != ISD::OR && Opc != ISD::AND)
8440 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8441 Op.getOperand(0).hasOneUse() &&
8442 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8443 Op.getOperand(1).hasOneUse());
8446 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8447 // 1 and that the SETCC node has a single use.
8448 static bool isXor1OfSetCC(SDValue Op) {
8449 if (Op.getOpcode() != ISD::XOR)
8451 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8452 if (N1C && N1C->getAPIntValue() == 1) {
8453 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8454 Op.getOperand(0).hasOneUse();
8459 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8460 bool addTest = true;
8461 SDValue Chain = Op.getOperand(0);
8462 SDValue Cond = Op.getOperand(1);
8463 SDValue Dest = Op.getOperand(2);
8464 DebugLoc dl = Op.getDebugLoc();
8467 if (Cond.getOpcode() == ISD::SETCC) {
8468 SDValue NewCond = LowerSETCC(Cond, DAG);
8469 if (NewCond.getNode())
8473 // FIXME: LowerXALUO doesn't handle these!!
8474 else if (Cond.getOpcode() == X86ISD::ADD ||
8475 Cond.getOpcode() == X86ISD::SUB ||
8476 Cond.getOpcode() == X86ISD::SMUL ||
8477 Cond.getOpcode() == X86ISD::UMUL)
8478 Cond = LowerXALUO(Cond, DAG);
8481 // Look pass (and (setcc_carry (cmp ...)), 1).
8482 if (Cond.getOpcode() == ISD::AND &&
8483 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8484 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8485 if (C && C->getAPIntValue() == 1)
8486 Cond = Cond.getOperand(0);
8489 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8490 // setting operand in place of the X86ISD::SETCC.
8491 if (Cond.getOpcode() == X86ISD::SETCC ||
8492 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8493 CC = Cond.getOperand(0);
8495 SDValue Cmp = Cond.getOperand(1);
8496 unsigned Opc = Cmp.getOpcode();
8497 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8498 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8502 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8506 // These can only come from an arithmetic instruction with overflow,
8507 // e.g. SADDO, UADDO.
8508 Cond = Cond.getNode()->getOperand(1);
8515 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8516 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8517 if (CondOpc == ISD::OR) {
8518 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8519 // two branches instead of an explicit OR instruction with a
8521 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8522 isX86LogicalCmp(Cmp)) {
8523 CC = Cond.getOperand(0).getOperand(0);
8524 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8525 Chain, Dest, CC, Cmp);
8526 CC = Cond.getOperand(1).getOperand(0);
8530 } else { // ISD::AND
8531 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8532 // two branches instead of an explicit AND instruction with a
8533 // separate test. However, we only do this if this block doesn't
8534 // have a fall-through edge, because this requires an explicit
8535 // jmp when the condition is false.
8536 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8537 isX86LogicalCmp(Cmp) &&
8538 Op.getNode()->hasOneUse()) {
8539 X86::CondCode CCode =
8540 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8541 CCode = X86::GetOppositeBranchCondition(CCode);
8542 CC = DAG.getConstant(CCode, MVT::i8);
8543 SDNode *User = *Op.getNode()->use_begin();
8544 // Look for an unconditional branch following this conditional branch.
8545 // We need this because we need to reverse the successors in order
8546 // to implement FCMP_OEQ.
8547 if (User->getOpcode() == ISD::BR) {
8548 SDValue FalseBB = User->getOperand(1);
8550 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8551 assert(NewBR == User);
8555 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8556 Chain, Dest, CC, Cmp);
8557 X86::CondCode CCode =
8558 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8559 CCode = X86::GetOppositeBranchCondition(CCode);
8560 CC = DAG.getConstant(CCode, MVT::i8);
8566 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8567 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8568 // It should be transformed during dag combiner except when the condition
8569 // is set by a arithmetics with overflow node.
8570 X86::CondCode CCode =
8571 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8572 CCode = X86::GetOppositeBranchCondition(CCode);
8573 CC = DAG.getConstant(CCode, MVT::i8);
8574 Cond = Cond.getOperand(0).getOperand(1);
8580 // Look pass the truncate.
8581 if (Cond.getOpcode() == ISD::TRUNCATE)
8582 Cond = Cond.getOperand(0);
8584 // We know the result of AND is compared against zero. Try to match
8586 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8587 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8588 if (NewSetCC.getNode()) {
8589 CC = NewSetCC.getOperand(0);
8590 Cond = NewSetCC.getOperand(1);
8597 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8598 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8600 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8601 Chain, Dest, CC, Cond);
8605 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8606 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8607 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8608 // that the guard pages used by the OS virtual memory manager are allocated in
8609 // correct sequence.
8611 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8612 SelectionDAG &DAG) const {
8613 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
8614 "This should be used only on Windows targets");
8615 assert(!Subtarget->isTargetEnvMacho());
8616 DebugLoc dl = Op.getDebugLoc();
8619 SDValue Chain = Op.getOperand(0);
8620 SDValue Size = Op.getOperand(1);
8621 // FIXME: Ensure alignment here
8625 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
8626 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8628 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8629 Flag = Chain.getValue(1);
8631 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8633 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8634 Flag = Chain.getValue(1);
8636 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8638 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8639 return DAG.getMergeValues(Ops1, 2, dl);
8642 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8643 MachineFunction &MF = DAG.getMachineFunction();
8644 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8646 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8647 DebugLoc DL = Op.getDebugLoc();
8649 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8650 // vastart just stores the address of the VarArgsFrameIndex slot into the
8651 // memory location argument.
8652 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8654 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8655 MachinePointerInfo(SV), false, false, 0);
8659 // gp_offset (0 - 6 * 8)
8660 // fp_offset (48 - 48 + 8 * 16)
8661 // overflow_arg_area (point to parameters coming in memory).
8663 SmallVector<SDValue, 8> MemOps;
8664 SDValue FIN = Op.getOperand(1);
8666 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8667 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
8669 FIN, MachinePointerInfo(SV), false, false, 0);
8670 MemOps.push_back(Store);
8673 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8674 FIN, DAG.getIntPtrConstant(4));
8675 Store = DAG.getStore(Op.getOperand(0), DL,
8676 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8678 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8679 MemOps.push_back(Store);
8681 // Store ptr to overflow_arg_area
8682 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8683 FIN, DAG.getIntPtrConstant(4));
8684 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8686 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
8687 MachinePointerInfo(SV, 8),
8689 MemOps.push_back(Store);
8691 // Store ptr to reg_save_area.
8692 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8693 FIN, DAG.getIntPtrConstant(8));
8694 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
8696 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
8697 MachinePointerInfo(SV, 16), false, false, 0);
8698 MemOps.push_back(Store);
8699 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
8700 &MemOps[0], MemOps.size());
8703 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
8704 assert(Subtarget->is64Bit() &&
8705 "LowerVAARG only handles 64-bit va_arg!");
8706 assert((Subtarget->isTargetLinux() ||
8707 Subtarget->isTargetDarwin()) &&
8708 "Unhandled target in LowerVAARG");
8709 assert(Op.getNode()->getNumOperands() == 4);
8710 SDValue Chain = Op.getOperand(0);
8711 SDValue SrcPtr = Op.getOperand(1);
8712 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8713 unsigned Align = Op.getConstantOperandVal(3);
8714 DebugLoc dl = Op.getDebugLoc();
8716 EVT ArgVT = Op.getNode()->getValueType(0);
8717 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
8718 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
8721 // Decide which area this value should be read from.
8722 // TODO: Implement the AMD64 ABI in its entirety. This simple
8723 // selection mechanism works only for the basic types.
8724 if (ArgVT == MVT::f80) {
8725 llvm_unreachable("va_arg for f80 not yet implemented");
8726 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
8727 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
8728 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
8729 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
8731 llvm_unreachable("Unhandled argument type in LowerVAARG");
8735 // Sanity Check: Make sure using fp_offset makes sense.
8736 assert(!UseSoftFloat &&
8737 !(DAG.getMachineFunction()
8738 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
8739 Subtarget->hasXMM());
8742 // Insert VAARG_64 node into the DAG
8743 // VAARG_64 returns two values: Variable Argument Address, Chain
8744 SmallVector<SDValue, 11> InstOps;
8745 InstOps.push_back(Chain);
8746 InstOps.push_back(SrcPtr);
8747 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
8748 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
8749 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
8750 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
8751 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
8752 VTs, &InstOps[0], InstOps.size(),
8754 MachinePointerInfo(SV),
8759 Chain = VAARG.getValue(1);
8761 // Load the next argument and return it
8762 return DAG.getLoad(ArgVT, dl,
8765 MachinePointerInfo(),
8769 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
8770 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
8771 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
8772 SDValue Chain = Op.getOperand(0);
8773 SDValue DstPtr = Op.getOperand(1);
8774 SDValue SrcPtr = Op.getOperand(2);
8775 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
8776 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8777 DebugLoc DL = Op.getDebugLoc();
8779 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
8780 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
8782 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
8786 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
8787 DebugLoc dl = Op.getDebugLoc();
8788 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8790 default: return SDValue(); // Don't custom lower most intrinsics.
8791 // Comparison intrinsics.
8792 case Intrinsic::x86_sse_comieq_ss:
8793 case Intrinsic::x86_sse_comilt_ss:
8794 case Intrinsic::x86_sse_comile_ss:
8795 case Intrinsic::x86_sse_comigt_ss:
8796 case Intrinsic::x86_sse_comige_ss:
8797 case Intrinsic::x86_sse_comineq_ss:
8798 case Intrinsic::x86_sse_ucomieq_ss:
8799 case Intrinsic::x86_sse_ucomilt_ss:
8800 case Intrinsic::x86_sse_ucomile_ss:
8801 case Intrinsic::x86_sse_ucomigt_ss:
8802 case Intrinsic::x86_sse_ucomige_ss:
8803 case Intrinsic::x86_sse_ucomineq_ss:
8804 case Intrinsic::x86_sse2_comieq_sd:
8805 case Intrinsic::x86_sse2_comilt_sd:
8806 case Intrinsic::x86_sse2_comile_sd:
8807 case Intrinsic::x86_sse2_comigt_sd:
8808 case Intrinsic::x86_sse2_comige_sd:
8809 case Intrinsic::x86_sse2_comineq_sd:
8810 case Intrinsic::x86_sse2_ucomieq_sd:
8811 case Intrinsic::x86_sse2_ucomilt_sd:
8812 case Intrinsic::x86_sse2_ucomile_sd:
8813 case Intrinsic::x86_sse2_ucomigt_sd:
8814 case Intrinsic::x86_sse2_ucomige_sd:
8815 case Intrinsic::x86_sse2_ucomineq_sd: {
8817 ISD::CondCode CC = ISD::SETCC_INVALID;
8820 case Intrinsic::x86_sse_comieq_ss:
8821 case Intrinsic::x86_sse2_comieq_sd:
8825 case Intrinsic::x86_sse_comilt_ss:
8826 case Intrinsic::x86_sse2_comilt_sd:
8830 case Intrinsic::x86_sse_comile_ss:
8831 case Intrinsic::x86_sse2_comile_sd:
8835 case Intrinsic::x86_sse_comigt_ss:
8836 case Intrinsic::x86_sse2_comigt_sd:
8840 case Intrinsic::x86_sse_comige_ss:
8841 case Intrinsic::x86_sse2_comige_sd:
8845 case Intrinsic::x86_sse_comineq_ss:
8846 case Intrinsic::x86_sse2_comineq_sd:
8850 case Intrinsic::x86_sse_ucomieq_ss:
8851 case Intrinsic::x86_sse2_ucomieq_sd:
8852 Opc = X86ISD::UCOMI;
8855 case Intrinsic::x86_sse_ucomilt_ss:
8856 case Intrinsic::x86_sse2_ucomilt_sd:
8857 Opc = X86ISD::UCOMI;
8860 case Intrinsic::x86_sse_ucomile_ss:
8861 case Intrinsic::x86_sse2_ucomile_sd:
8862 Opc = X86ISD::UCOMI;
8865 case Intrinsic::x86_sse_ucomigt_ss:
8866 case Intrinsic::x86_sse2_ucomigt_sd:
8867 Opc = X86ISD::UCOMI;
8870 case Intrinsic::x86_sse_ucomige_ss:
8871 case Intrinsic::x86_sse2_ucomige_sd:
8872 Opc = X86ISD::UCOMI;
8875 case Intrinsic::x86_sse_ucomineq_ss:
8876 case Intrinsic::x86_sse2_ucomineq_sd:
8877 Opc = X86ISD::UCOMI;
8882 SDValue LHS = Op.getOperand(1);
8883 SDValue RHS = Op.getOperand(2);
8884 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
8885 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
8886 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
8887 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8888 DAG.getConstant(X86CC, MVT::i8), Cond);
8889 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
8891 // ptest and testp intrinsics. The intrinsic these come from are designed to
8892 // return an integer value, not just an instruction so lower it to the ptest
8893 // or testp pattern and a setcc for the result.
8894 case Intrinsic::x86_sse41_ptestz:
8895 case Intrinsic::x86_sse41_ptestc:
8896 case Intrinsic::x86_sse41_ptestnzc:
8897 case Intrinsic::x86_avx_ptestz_256:
8898 case Intrinsic::x86_avx_ptestc_256:
8899 case Intrinsic::x86_avx_ptestnzc_256:
8900 case Intrinsic::x86_avx_vtestz_ps:
8901 case Intrinsic::x86_avx_vtestc_ps:
8902 case Intrinsic::x86_avx_vtestnzc_ps:
8903 case Intrinsic::x86_avx_vtestz_pd:
8904 case Intrinsic::x86_avx_vtestc_pd:
8905 case Intrinsic::x86_avx_vtestnzc_pd:
8906 case Intrinsic::x86_avx_vtestz_ps_256:
8907 case Intrinsic::x86_avx_vtestc_ps_256:
8908 case Intrinsic::x86_avx_vtestnzc_ps_256:
8909 case Intrinsic::x86_avx_vtestz_pd_256:
8910 case Intrinsic::x86_avx_vtestc_pd_256:
8911 case Intrinsic::x86_avx_vtestnzc_pd_256: {
8912 bool IsTestPacked = false;
8915 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
8916 case Intrinsic::x86_avx_vtestz_ps:
8917 case Intrinsic::x86_avx_vtestz_pd:
8918 case Intrinsic::x86_avx_vtestz_ps_256:
8919 case Intrinsic::x86_avx_vtestz_pd_256:
8920 IsTestPacked = true; // Fallthrough
8921 case Intrinsic::x86_sse41_ptestz:
8922 case Intrinsic::x86_avx_ptestz_256:
8924 X86CC = X86::COND_E;
8926 case Intrinsic::x86_avx_vtestc_ps:
8927 case Intrinsic::x86_avx_vtestc_pd:
8928 case Intrinsic::x86_avx_vtestc_ps_256:
8929 case Intrinsic::x86_avx_vtestc_pd_256:
8930 IsTestPacked = true; // Fallthrough
8931 case Intrinsic::x86_sse41_ptestc:
8932 case Intrinsic::x86_avx_ptestc_256:
8934 X86CC = X86::COND_B;
8936 case Intrinsic::x86_avx_vtestnzc_ps:
8937 case Intrinsic::x86_avx_vtestnzc_pd:
8938 case Intrinsic::x86_avx_vtestnzc_ps_256:
8939 case Intrinsic::x86_avx_vtestnzc_pd_256:
8940 IsTestPacked = true; // Fallthrough
8941 case Intrinsic::x86_sse41_ptestnzc:
8942 case Intrinsic::x86_avx_ptestnzc_256:
8944 X86CC = X86::COND_A;
8948 SDValue LHS = Op.getOperand(1);
8949 SDValue RHS = Op.getOperand(2);
8950 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
8951 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
8952 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
8953 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
8954 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
8957 // Fix vector shift instructions where the last operand is a non-immediate
8959 case Intrinsic::x86_sse2_pslli_w:
8960 case Intrinsic::x86_sse2_pslli_d:
8961 case Intrinsic::x86_sse2_pslli_q:
8962 case Intrinsic::x86_sse2_psrli_w:
8963 case Intrinsic::x86_sse2_psrli_d:
8964 case Intrinsic::x86_sse2_psrli_q:
8965 case Intrinsic::x86_sse2_psrai_w:
8966 case Intrinsic::x86_sse2_psrai_d:
8967 case Intrinsic::x86_mmx_pslli_w:
8968 case Intrinsic::x86_mmx_pslli_d:
8969 case Intrinsic::x86_mmx_pslli_q:
8970 case Intrinsic::x86_mmx_psrli_w:
8971 case Intrinsic::x86_mmx_psrli_d:
8972 case Intrinsic::x86_mmx_psrli_q:
8973 case Intrinsic::x86_mmx_psrai_w:
8974 case Intrinsic::x86_mmx_psrai_d: {
8975 SDValue ShAmt = Op.getOperand(2);
8976 if (isa<ConstantSDNode>(ShAmt))
8979 unsigned NewIntNo = 0;
8980 EVT ShAmtVT = MVT::v4i32;
8982 case Intrinsic::x86_sse2_pslli_w:
8983 NewIntNo = Intrinsic::x86_sse2_psll_w;
8985 case Intrinsic::x86_sse2_pslli_d:
8986 NewIntNo = Intrinsic::x86_sse2_psll_d;
8988 case Intrinsic::x86_sse2_pslli_q:
8989 NewIntNo = Intrinsic::x86_sse2_psll_q;
8991 case Intrinsic::x86_sse2_psrli_w:
8992 NewIntNo = Intrinsic::x86_sse2_psrl_w;
8994 case Intrinsic::x86_sse2_psrli_d:
8995 NewIntNo = Intrinsic::x86_sse2_psrl_d;
8997 case Intrinsic::x86_sse2_psrli_q:
8998 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9000 case Intrinsic::x86_sse2_psrai_w:
9001 NewIntNo = Intrinsic::x86_sse2_psra_w;
9003 case Intrinsic::x86_sse2_psrai_d:
9004 NewIntNo = Intrinsic::x86_sse2_psra_d;
9007 ShAmtVT = MVT::v2i32;
9009 case Intrinsic::x86_mmx_pslli_w:
9010 NewIntNo = Intrinsic::x86_mmx_psll_w;
9012 case Intrinsic::x86_mmx_pslli_d:
9013 NewIntNo = Intrinsic::x86_mmx_psll_d;
9015 case Intrinsic::x86_mmx_pslli_q:
9016 NewIntNo = Intrinsic::x86_mmx_psll_q;
9018 case Intrinsic::x86_mmx_psrli_w:
9019 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9021 case Intrinsic::x86_mmx_psrli_d:
9022 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9024 case Intrinsic::x86_mmx_psrli_q:
9025 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9027 case Intrinsic::x86_mmx_psrai_w:
9028 NewIntNo = Intrinsic::x86_mmx_psra_w;
9030 case Intrinsic::x86_mmx_psrai_d:
9031 NewIntNo = Intrinsic::x86_mmx_psra_d;
9033 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9039 // The vector shift intrinsics with scalars uses 32b shift amounts but
9040 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9044 ShOps[1] = DAG.getConstant(0, MVT::i32);
9045 if (ShAmtVT == MVT::v4i32) {
9046 ShOps[2] = DAG.getUNDEF(MVT::i32);
9047 ShOps[3] = DAG.getUNDEF(MVT::i32);
9048 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9050 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9051 // FIXME this must be lowered to get rid of the invalid type.
9054 EVT VT = Op.getValueType();
9055 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9056 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9057 DAG.getConstant(NewIntNo, MVT::i32),
9058 Op.getOperand(1), ShAmt);
9063 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9064 SelectionDAG &DAG) const {
9065 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9066 MFI->setReturnAddressIsTaken(true);
9068 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9069 DebugLoc dl = Op.getDebugLoc();
9072 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9074 DAG.getConstant(TD->getPointerSize(),
9075 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9076 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9077 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9079 MachinePointerInfo(), false, false, 0);
9082 // Just load the return address.
9083 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9084 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9085 RetAddrFI, MachinePointerInfo(), false, false, 0);
9088 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9089 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9090 MFI->setFrameAddressIsTaken(true);
9092 EVT VT = Op.getValueType();
9093 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9094 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9095 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9096 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9098 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9099 MachinePointerInfo(),
9104 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9105 SelectionDAG &DAG) const {
9106 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9109 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9110 MachineFunction &MF = DAG.getMachineFunction();
9111 SDValue Chain = Op.getOperand(0);
9112 SDValue Offset = Op.getOperand(1);
9113 SDValue Handler = Op.getOperand(2);
9114 DebugLoc dl = Op.getDebugLoc();
9116 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9117 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9119 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9121 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9122 DAG.getIntPtrConstant(TD->getPointerSize()));
9123 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9124 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9126 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9127 MF.getRegInfo().addLiveOut(StoreAddrReg);
9129 return DAG.getNode(X86ISD::EH_RETURN, dl,
9131 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9134 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
9135 SelectionDAG &DAG) const {
9136 SDValue Root = Op.getOperand(0);
9137 SDValue Trmp = Op.getOperand(1); // trampoline
9138 SDValue FPtr = Op.getOperand(2); // nested function
9139 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9140 DebugLoc dl = Op.getDebugLoc();
9142 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9144 if (Subtarget->is64Bit()) {
9145 SDValue OutChains[6];
9147 // Large code-model.
9148 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9149 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9151 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9152 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9154 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9156 // Load the pointer to the nested function into R11.
9157 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9158 SDValue Addr = Trmp;
9159 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9160 Addr, MachinePointerInfo(TrmpAddr),
9163 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9164 DAG.getConstant(2, MVT::i64));
9165 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9166 MachinePointerInfo(TrmpAddr, 2),
9169 // Load the 'nest' parameter value into R10.
9170 // R10 is specified in X86CallingConv.td
9171 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9172 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9173 DAG.getConstant(10, MVT::i64));
9174 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9175 Addr, MachinePointerInfo(TrmpAddr, 10),
9178 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9179 DAG.getConstant(12, MVT::i64));
9180 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9181 MachinePointerInfo(TrmpAddr, 12),
9184 // Jump to the nested function.
9185 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9186 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9187 DAG.getConstant(20, MVT::i64));
9188 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9189 Addr, MachinePointerInfo(TrmpAddr, 20),
9192 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9193 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9194 DAG.getConstant(22, MVT::i64));
9195 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9196 MachinePointerInfo(TrmpAddr, 22),
9200 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
9201 return DAG.getMergeValues(Ops, 2, dl);
9203 const Function *Func =
9204 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9205 CallingConv::ID CC = Func->getCallingConv();
9210 llvm_unreachable("Unsupported calling convention");
9211 case CallingConv::C:
9212 case CallingConv::X86_StdCall: {
9213 // Pass 'nest' parameter in ECX.
9214 // Must be kept in sync with X86CallingConv.td
9217 // Check that ECX wasn't needed by an 'inreg' parameter.
9218 FunctionType *FTy = Func->getFunctionType();
9219 const AttrListPtr &Attrs = Func->getAttributes();
9221 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9222 unsigned InRegCount = 0;
9225 for (FunctionType::param_iterator I = FTy->param_begin(),
9226 E = FTy->param_end(); I != E; ++I, ++Idx)
9227 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9228 // FIXME: should only count parameters that are lowered to integers.
9229 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9231 if (InRegCount > 2) {
9232 report_fatal_error("Nest register in use - reduce number of inreg"
9238 case CallingConv::X86_FastCall:
9239 case CallingConv::X86_ThisCall:
9240 case CallingConv::Fast:
9241 // Pass 'nest' parameter in EAX.
9242 // Must be kept in sync with X86CallingConv.td
9247 SDValue OutChains[4];
9250 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9251 DAG.getConstant(10, MVT::i32));
9252 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9254 // This is storing the opcode for MOV32ri.
9255 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9256 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9257 OutChains[0] = DAG.getStore(Root, dl,
9258 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9259 Trmp, MachinePointerInfo(TrmpAddr),
9262 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9263 DAG.getConstant(1, MVT::i32));
9264 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9265 MachinePointerInfo(TrmpAddr, 1),
9268 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9269 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9270 DAG.getConstant(5, MVT::i32));
9271 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9272 MachinePointerInfo(TrmpAddr, 5),
9275 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9276 DAG.getConstant(6, MVT::i32));
9277 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9278 MachinePointerInfo(TrmpAddr, 6),
9282 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
9283 return DAG.getMergeValues(Ops, 2, dl);
9287 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9288 SelectionDAG &DAG) const {
9290 The rounding mode is in bits 11:10 of FPSR, and has the following
9297 FLT_ROUNDS, on the other hand, expects the following:
9304 To perform the conversion, we do:
9305 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9308 MachineFunction &MF = DAG.getMachineFunction();
9309 const TargetMachine &TM = MF.getTarget();
9310 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9311 unsigned StackAlignment = TFI.getStackAlignment();
9312 EVT VT = Op.getValueType();
9313 DebugLoc DL = Op.getDebugLoc();
9315 // Save FP Control Word to stack slot
9316 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9317 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9320 MachineMemOperand *MMO =
9321 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9322 MachineMemOperand::MOStore, 2, 2);
9324 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9325 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9326 DAG.getVTList(MVT::Other),
9327 Ops, 2, MVT::i16, MMO);
9329 // Load FP Control Word from stack slot
9330 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9331 MachinePointerInfo(), false, false, 0);
9333 // Transform as necessary
9335 DAG.getNode(ISD::SRL, DL, MVT::i16,
9336 DAG.getNode(ISD::AND, DL, MVT::i16,
9337 CWD, DAG.getConstant(0x800, MVT::i16)),
9338 DAG.getConstant(11, MVT::i8));
9340 DAG.getNode(ISD::SRL, DL, MVT::i16,
9341 DAG.getNode(ISD::AND, DL, MVT::i16,
9342 CWD, DAG.getConstant(0x400, MVT::i16)),
9343 DAG.getConstant(9, MVT::i8));
9346 DAG.getNode(ISD::AND, DL, MVT::i16,
9347 DAG.getNode(ISD::ADD, DL, MVT::i16,
9348 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9349 DAG.getConstant(1, MVT::i16)),
9350 DAG.getConstant(3, MVT::i16));
9353 return DAG.getNode((VT.getSizeInBits() < 16 ?
9354 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9357 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9358 EVT VT = Op.getValueType();
9360 unsigned NumBits = VT.getSizeInBits();
9361 DebugLoc dl = Op.getDebugLoc();
9363 Op = Op.getOperand(0);
9364 if (VT == MVT::i8) {
9365 // Zero extend to i32 since there is not an i8 bsr.
9367 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9370 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9371 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9372 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9374 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9377 DAG.getConstant(NumBits+NumBits-1, OpVT),
9378 DAG.getConstant(X86::COND_E, MVT::i8),
9381 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9383 // Finally xor with NumBits-1.
9384 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9387 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9391 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9392 EVT VT = Op.getValueType();
9394 unsigned NumBits = VT.getSizeInBits();
9395 DebugLoc dl = Op.getDebugLoc();
9397 Op = Op.getOperand(0);
9398 if (VT == MVT::i8) {
9400 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9403 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9404 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9405 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9407 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9410 DAG.getConstant(NumBits, OpVT),
9411 DAG.getConstant(X86::COND_E, MVT::i8),
9414 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9417 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9421 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
9422 EVT VT = Op.getValueType();
9423 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9424 DebugLoc dl = Op.getDebugLoc();
9426 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9427 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9428 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9429 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9430 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9432 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9433 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9434 // return AloBlo + AloBhi + AhiBlo;
9436 SDValue A = Op.getOperand(0);
9437 SDValue B = Op.getOperand(1);
9439 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9440 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9441 A, DAG.getConstant(32, MVT::i32));
9442 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9443 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9444 B, DAG.getConstant(32, MVT::i32));
9445 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9446 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9448 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9449 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9451 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9452 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9454 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9455 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9456 AloBhi, DAG.getConstant(32, MVT::i32));
9457 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9458 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9459 AhiBlo, DAG.getConstant(32, MVT::i32));
9460 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9461 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9465 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9467 EVT VT = Op.getValueType();
9468 DebugLoc dl = Op.getDebugLoc();
9469 SDValue R = Op.getOperand(0);
9470 SDValue Amt = Op.getOperand(1);
9471 LLVMContext *Context = DAG.getContext();
9473 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
9476 // Decompose 256-bit shifts into smaller 128-bit shifts.
9477 if (VT.getSizeInBits() == 256) {
9478 int NumElems = VT.getVectorNumElements();
9479 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9480 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9482 // Extract the two vectors
9483 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
9484 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
9487 // Recreate the shift amount vectors
9489 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
9490 // Constant shift amount
9491 SmallVector<SDValue, 4> Amt1Csts;
9492 SmallVector<SDValue, 4> Amt2Csts;
9493 for (int i = 0; i < NumElems/2; ++i)
9494 Amt1Csts.push_back(Amt->getOperand(i));
9495 for (int i = NumElems/2; i < NumElems; ++i)
9496 Amt2Csts.push_back(Amt->getOperand(i));
9498 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9499 &Amt1Csts[0], NumElems/2);
9500 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9501 &Amt2Csts[0], NumElems/2);
9503 // Variable shift amount
9504 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
9505 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
9509 // Issue new vector shifts for the smaller types
9510 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
9511 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
9513 // Concatenate the result back
9514 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
9517 // Optimize shl/srl/sra with constant shift amount.
9518 if (isSplatVector(Amt.getNode())) {
9519 SDValue SclrAmt = Amt->getOperand(0);
9520 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9521 uint64_t ShiftAmt = C->getZExtValue();
9523 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
9524 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9525 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9526 R, DAG.getConstant(ShiftAmt, MVT::i32));
9528 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
9529 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9530 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9531 R, DAG.getConstant(ShiftAmt, MVT::i32));
9533 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
9534 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9535 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9536 R, DAG.getConstant(ShiftAmt, MVT::i32));
9538 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
9539 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9540 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9541 R, DAG.getConstant(ShiftAmt, MVT::i32));
9543 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
9544 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9545 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9546 R, DAG.getConstant(ShiftAmt, MVT::i32));
9548 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
9549 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9550 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9551 R, DAG.getConstant(ShiftAmt, MVT::i32));
9553 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
9554 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9555 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9556 R, DAG.getConstant(ShiftAmt, MVT::i32));
9558 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9559 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9560 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9561 R, DAG.getConstant(ShiftAmt, MVT::i32));
9565 // Lower SHL with variable shift amount.
9566 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
9567 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9568 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9569 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
9571 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
9573 std::vector<Constant*> CV(4, CI);
9574 Constant *C = ConstantVector::get(CV);
9575 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9576 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9577 MachinePointerInfo::getConstantPool(),
9580 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
9581 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
9582 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
9583 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
9585 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
9587 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9588 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9589 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
9591 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
9592 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
9594 std::vector<Constant*> CVM1(16, CM1);
9595 std::vector<Constant*> CVM2(16, CM2);
9596 Constant *C = ConstantVector::get(CVM1);
9597 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9598 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9599 MachinePointerInfo::getConstantPool(),
9602 // r = pblendv(r, psllw(r & (char16)15, 4), a);
9603 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9604 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9605 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9606 DAG.getConstant(4, MVT::i32));
9607 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9609 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9611 C = ConstantVector::get(CVM2);
9612 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9613 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9614 MachinePointerInfo::getConstantPool(),
9617 // r = pblendv(r, psllw(r & (char16)63, 2), a);
9618 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9619 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9620 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9621 DAG.getConstant(2, MVT::i32));
9622 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9624 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9626 // return pblendv(r, r+r, a);
9627 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
9628 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
9634 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
9635 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
9636 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
9637 // looks for this combo and may remove the "setcc" instruction if the "setcc"
9638 // has only one use.
9639 SDNode *N = Op.getNode();
9640 SDValue LHS = N->getOperand(0);
9641 SDValue RHS = N->getOperand(1);
9642 unsigned BaseOp = 0;
9644 DebugLoc DL = Op.getDebugLoc();
9645 switch (Op.getOpcode()) {
9646 default: llvm_unreachable("Unknown ovf instruction!");
9648 // A subtract of one will be selected as a INC. Note that INC doesn't
9649 // set CF, so we can't do this for UADDO.
9650 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9652 BaseOp = X86ISD::INC;
9656 BaseOp = X86ISD::ADD;
9660 BaseOp = X86ISD::ADD;
9664 // A subtract of one will be selected as a DEC. Note that DEC doesn't
9665 // set CF, so we can't do this for USUBO.
9666 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9668 BaseOp = X86ISD::DEC;
9672 BaseOp = X86ISD::SUB;
9676 BaseOp = X86ISD::SUB;
9680 BaseOp = X86ISD::SMUL;
9683 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
9684 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
9686 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
9689 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9690 DAG.getConstant(X86::COND_O, MVT::i32),
9691 SDValue(Sum.getNode(), 2));
9693 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9697 // Also sets EFLAGS.
9698 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
9699 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
9702 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
9703 DAG.getConstant(Cond, MVT::i32),
9704 SDValue(Sum.getNode(), 1));
9706 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9709 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
9710 DebugLoc dl = Op.getDebugLoc();
9711 SDNode* Node = Op.getNode();
9712 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
9713 EVT VT = Node->getValueType(0);
9715 if (Subtarget->hasSSE2() && VT.isVector()) {
9716 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
9717 ExtraVT.getScalarType().getSizeInBits();
9718 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
9720 unsigned SHLIntrinsicsID = 0;
9721 unsigned SRAIntrinsicsID = 0;
9722 switch (VT.getSimpleVT().SimpleTy) {
9726 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q;
9727 SRAIntrinsicsID = 0;
9731 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
9732 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
9736 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
9737 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
9742 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9743 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
9744 Node->getOperand(0), ShAmt);
9746 // In case of 1 bit sext, no need to shr
9747 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
9749 if (SRAIntrinsicsID) {
9750 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9751 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
9761 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
9762 DebugLoc dl = Op.getDebugLoc();
9764 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
9765 // There isn't any reason to disable it if the target processor supports it.
9766 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
9767 SDValue Chain = Op.getOperand(0);
9768 SDValue Zero = DAG.getConstant(0, MVT::i32);
9770 DAG.getRegister(X86::ESP, MVT::i32), // Base
9771 DAG.getTargetConstant(1, MVT::i8), // Scale
9772 DAG.getRegister(0, MVT::i32), // Index
9773 DAG.getTargetConstant(0, MVT::i32), // Disp
9774 DAG.getRegister(0, MVT::i32), // Segment.
9779 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
9780 array_lengthof(Ops));
9781 return SDValue(Res, 0);
9784 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
9786 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
9788 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9789 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
9790 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
9791 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
9793 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
9794 if (!Op1 && !Op2 && !Op3 && Op4)
9795 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
9797 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
9798 if (Op1 && !Op2 && !Op3 && !Op4)
9799 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
9801 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
9803 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
9806 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
9807 SelectionDAG &DAG) const {
9808 DebugLoc dl = Op.getDebugLoc();
9809 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
9810 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
9811 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
9812 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
9814 // The only fence that needs an instruction is a sequentially-consistent
9815 // cross-thread fence.
9816 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
9817 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
9818 // no-sse2). There isn't any reason to disable it if the target processor
9820 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
9821 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
9823 SDValue Chain = Op.getOperand(0);
9824 SDValue Zero = DAG.getConstant(0, MVT::i32);
9826 DAG.getRegister(X86::ESP, MVT::i32), // Base
9827 DAG.getTargetConstant(1, MVT::i8), // Scale
9828 DAG.getRegister(0, MVT::i32), // Index
9829 DAG.getTargetConstant(0, MVT::i32), // Disp
9830 DAG.getRegister(0, MVT::i32), // Segment.
9835 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
9836 array_lengthof(Ops));
9837 return SDValue(Res, 0);
9840 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
9841 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
9845 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
9846 EVT T = Op.getValueType();
9847 DebugLoc DL = Op.getDebugLoc();
9850 switch(T.getSimpleVT().SimpleTy) {
9852 assert(false && "Invalid value type!");
9853 case MVT::i8: Reg = X86::AL; size = 1; break;
9854 case MVT::i16: Reg = X86::AX; size = 2; break;
9855 case MVT::i32: Reg = X86::EAX; size = 4; break;
9857 assert(Subtarget->is64Bit() && "Node not type legal!");
9858 Reg = X86::RAX; size = 8;
9861 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
9862 Op.getOperand(2), SDValue());
9863 SDValue Ops[] = { cpIn.getValue(0),
9866 DAG.getTargetConstant(size, MVT::i8),
9868 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9869 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
9870 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
9873 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
9877 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
9878 SelectionDAG &DAG) const {
9879 assert(Subtarget->is64Bit() && "Result not type legalized?");
9880 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9881 SDValue TheChain = Op.getOperand(0);
9882 DebugLoc dl = Op.getDebugLoc();
9883 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
9884 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
9885 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
9887 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
9888 DAG.getConstant(32, MVT::i8));
9890 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
9893 return DAG.getMergeValues(Ops, 2, dl);
9896 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
9897 SelectionDAG &DAG) const {
9898 EVT SrcVT = Op.getOperand(0).getValueType();
9899 EVT DstVT = Op.getValueType();
9900 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
9901 Subtarget->hasMMX() && "Unexpected custom BITCAST");
9902 assert((DstVT == MVT::i64 ||
9903 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
9904 "Unexpected custom BITCAST");
9905 // i64 <=> MMX conversions are Legal.
9906 if (SrcVT==MVT::i64 && DstVT.isVector())
9908 if (DstVT==MVT::i64 && SrcVT.isVector())
9910 // MMX <=> MMX conversions are Legal.
9911 if (SrcVT.isVector() && DstVT.isVector())
9913 // All other conversions need to be expanded.
9917 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
9918 SDNode *Node = Op.getNode();
9919 DebugLoc dl = Node->getDebugLoc();
9920 EVT T = Node->getValueType(0);
9921 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
9922 DAG.getConstant(0, T), Node->getOperand(2));
9923 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
9924 cast<AtomicSDNode>(Node)->getMemoryVT(),
9925 Node->getOperand(0),
9926 Node->getOperand(1), negOp,
9927 cast<AtomicSDNode>(Node)->getSrcValue(),
9928 cast<AtomicSDNode>(Node)->getAlignment(),
9929 cast<AtomicSDNode>(Node)->getOrdering(),
9930 cast<AtomicSDNode>(Node)->getSynchScope());
9933 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
9934 EVT VT = Op.getNode()->getValueType(0);
9936 // Let legalize expand this if it isn't a legal type yet.
9937 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
9940 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
9943 bool ExtraOp = false;
9944 switch (Op.getOpcode()) {
9945 default: assert(0 && "Invalid code");
9946 case ISD::ADDC: Opc = X86ISD::ADD; break;
9947 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
9948 case ISD::SUBC: Opc = X86ISD::SUB; break;
9949 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
9953 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
9955 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
9956 Op.getOperand(1), Op.getOperand(2));
9959 /// LowerOperation - Provide custom lowering hooks for some operations.
9961 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
9962 switch (Op.getOpcode()) {
9963 default: llvm_unreachable("Should not custom lower this!");
9964 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
9965 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
9966 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
9967 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
9968 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
9969 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
9970 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
9971 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
9972 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
9973 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
9974 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
9975 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
9976 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
9977 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
9978 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
9979 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
9980 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
9981 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
9982 case ISD::SHL_PARTS:
9983 case ISD::SRA_PARTS:
9984 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
9985 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
9986 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
9987 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
9988 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
9989 case ISD::FABS: return LowerFABS(Op, DAG);
9990 case ISD::FNEG: return LowerFNEG(Op, DAG);
9991 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
9992 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
9993 case ISD::SETCC: return LowerSETCC(Op, DAG);
9994 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
9995 case ISD::SELECT: return LowerSELECT(Op, DAG);
9996 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
9997 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
9998 case ISD::VASTART: return LowerVASTART(Op, DAG);
9999 case ISD::VAARG: return LowerVAARG(Op, DAG);
10000 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10001 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10002 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10003 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10004 case ISD::FRAME_TO_ARGS_OFFSET:
10005 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10006 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10007 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10008 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
10009 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10010 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10011 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10012 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
10015 case ISD::SHL: return LowerShift(Op, DAG);
10021 case ISD::UMULO: return LowerXALUO(Op, DAG);
10022 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10023 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10027 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10031 void X86TargetLowering::
10032 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10033 SelectionDAG &DAG, unsigned NewOp) const {
10034 EVT T = Node->getValueType(0);
10035 DebugLoc dl = Node->getDebugLoc();
10036 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
10038 SDValue Chain = Node->getOperand(0);
10039 SDValue In1 = Node->getOperand(1);
10040 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10041 Node->getOperand(2), DAG.getIntPtrConstant(0));
10042 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10043 Node->getOperand(2), DAG.getIntPtrConstant(1));
10044 SDValue Ops[] = { Chain, In1, In2L, In2H };
10045 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10047 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10048 cast<MemSDNode>(Node)->getMemOperand());
10049 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10050 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10051 Results.push_back(Result.getValue(2));
10054 /// ReplaceNodeResults - Replace a node with an illegal result type
10055 /// with a new node built out of custom code.
10056 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10057 SmallVectorImpl<SDValue>&Results,
10058 SelectionDAG &DAG) const {
10059 DebugLoc dl = N->getDebugLoc();
10060 switch (N->getOpcode()) {
10062 assert(false && "Do not know how to custom type legalize this operation!");
10064 case ISD::SIGN_EXTEND_INREG:
10069 // We don't want to expand or promote these.
10071 case ISD::FP_TO_SINT: {
10072 std::pair<SDValue,SDValue> Vals =
10073 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10074 SDValue FIST = Vals.first, StackSlot = Vals.second;
10075 if (FIST.getNode() != 0) {
10076 EVT VT = N->getValueType(0);
10077 // Return a load from the stack slot.
10078 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10079 MachinePointerInfo(), false, false, 0));
10083 case ISD::READCYCLECOUNTER: {
10084 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10085 SDValue TheChain = N->getOperand(0);
10086 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10087 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10089 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10091 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10092 SDValue Ops[] = { eax, edx };
10093 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10094 Results.push_back(edx.getValue(1));
10097 case ISD::ATOMIC_CMP_SWAP: {
10098 EVT T = N->getValueType(0);
10099 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
10100 SDValue cpInL, cpInH;
10101 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
10102 DAG.getConstant(0, MVT::i32));
10103 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
10104 DAG.getConstant(1, MVT::i32));
10105 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
10106 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
10107 cpInL.getValue(1));
10108 SDValue swapInL, swapInH;
10109 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
10110 DAG.getConstant(0, MVT::i32));
10111 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
10112 DAG.getConstant(1, MVT::i32));
10113 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
10114 cpInH.getValue(1));
10115 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
10116 swapInL.getValue(1));
10117 SDValue Ops[] = { swapInH.getValue(0),
10119 swapInH.getValue(1) };
10120 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10121 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10122 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
10124 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
10125 MVT::i32, Result.getValue(1));
10126 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
10127 MVT::i32, cpOutL.getValue(2));
10128 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10129 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10130 Results.push_back(cpOutH.getValue(1));
10133 case ISD::ATOMIC_LOAD_ADD:
10134 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10136 case ISD::ATOMIC_LOAD_AND:
10137 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10139 case ISD::ATOMIC_LOAD_NAND:
10140 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10142 case ISD::ATOMIC_LOAD_OR:
10143 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10145 case ISD::ATOMIC_LOAD_SUB:
10146 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10148 case ISD::ATOMIC_LOAD_XOR:
10149 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10151 case ISD::ATOMIC_SWAP:
10152 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10157 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10159 default: return NULL;
10160 case X86ISD::BSF: return "X86ISD::BSF";
10161 case X86ISD::BSR: return "X86ISD::BSR";
10162 case X86ISD::SHLD: return "X86ISD::SHLD";
10163 case X86ISD::SHRD: return "X86ISD::SHRD";
10164 case X86ISD::FAND: return "X86ISD::FAND";
10165 case X86ISD::FOR: return "X86ISD::FOR";
10166 case X86ISD::FXOR: return "X86ISD::FXOR";
10167 case X86ISD::FSRL: return "X86ISD::FSRL";
10168 case X86ISD::FILD: return "X86ISD::FILD";
10169 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10170 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10171 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10172 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10173 case X86ISD::FLD: return "X86ISD::FLD";
10174 case X86ISD::FST: return "X86ISD::FST";
10175 case X86ISD::CALL: return "X86ISD::CALL";
10176 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10177 case X86ISD::BT: return "X86ISD::BT";
10178 case X86ISD::CMP: return "X86ISD::CMP";
10179 case X86ISD::COMI: return "X86ISD::COMI";
10180 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10181 case X86ISD::SETCC: return "X86ISD::SETCC";
10182 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10183 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10184 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10185 case X86ISD::CMOV: return "X86ISD::CMOV";
10186 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10187 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10188 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10189 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10190 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10191 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10192 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10193 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10194 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10195 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10196 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10197 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10198 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10199 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10200 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
10201 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
10202 case X86ISD::PSIGND: return "X86ISD::PSIGND";
10203 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
10204 case X86ISD::FMAX: return "X86ISD::FMAX";
10205 case X86ISD::FMIN: return "X86ISD::FMIN";
10206 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10207 case X86ISD::FRCP: return "X86ISD::FRCP";
10208 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10209 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10210 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10211 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10212 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10213 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10214 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10215 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10216 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10217 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10218 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10219 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10220 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10221 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10222 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10223 case X86ISD::VSHL: return "X86ISD::VSHL";
10224 case X86ISD::VSRL: return "X86ISD::VSRL";
10225 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10226 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10227 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10228 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10229 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10230 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10231 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10232 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10233 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10234 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10235 case X86ISD::ADD: return "X86ISD::ADD";
10236 case X86ISD::SUB: return "X86ISD::SUB";
10237 case X86ISD::ADC: return "X86ISD::ADC";
10238 case X86ISD::SBB: return "X86ISD::SBB";
10239 case X86ISD::SMUL: return "X86ISD::SMUL";
10240 case X86ISD::UMUL: return "X86ISD::UMUL";
10241 case X86ISD::INC: return "X86ISD::INC";
10242 case X86ISD::DEC: return "X86ISD::DEC";
10243 case X86ISD::OR: return "X86ISD::OR";
10244 case X86ISD::XOR: return "X86ISD::XOR";
10245 case X86ISD::AND: return "X86ISD::AND";
10246 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10247 case X86ISD::PTEST: return "X86ISD::PTEST";
10248 case X86ISD::TESTP: return "X86ISD::TESTP";
10249 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10250 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10251 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10252 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10253 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10254 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10255 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10256 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10257 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10258 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10259 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10260 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
10261 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10262 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10263 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10264 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10265 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10266 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10267 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10268 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10269 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10270 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
10271 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
10272 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
10273 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
10274 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
10275 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
10276 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
10277 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
10278 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
10279 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
10280 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
10281 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
10282 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
10283 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10284 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
10285 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
10286 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
10287 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
10288 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
10289 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10290 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10291 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10292 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10296 // isLegalAddressingMode - Return true if the addressing mode represented
10297 // by AM is legal for this target, for a load/store of the specified type.
10298 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10300 // X86 supports extremely general addressing modes.
10301 CodeModel::Model M = getTargetMachine().getCodeModel();
10302 Reloc::Model R = getTargetMachine().getRelocationModel();
10304 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10305 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10310 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10312 // If a reference to this global requires an extra load, we can't fold it.
10313 if (isGlobalStubReference(GVFlags))
10316 // If BaseGV requires a register for the PIC base, we cannot also have a
10317 // BaseReg specified.
10318 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
10321 // If lower 4G is not available, then we must use rip-relative addressing.
10322 if ((M != CodeModel::Small || R != Reloc::Static) &&
10323 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
10327 switch (AM.Scale) {
10333 // These scales always work.
10338 // These scales are formed with basereg+scalereg. Only accept if there is
10343 default: // Other stuff never works.
10351 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
10352 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10354 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
10355 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
10356 if (NumBits1 <= NumBits2)
10361 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
10362 if (!VT1.isInteger() || !VT2.isInteger())
10364 unsigned NumBits1 = VT1.getSizeInBits();
10365 unsigned NumBits2 = VT2.getSizeInBits();
10366 if (NumBits1 <= NumBits2)
10371 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
10372 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10373 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
10376 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
10377 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10378 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
10381 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
10382 // i16 instructions are longer (0x66 prefix) and potentially slower.
10383 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
10386 /// isShuffleMaskLegal - Targets can use this to indicate that they only
10387 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
10388 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
10389 /// are assumed to be legal.
10391 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
10393 // Very little shuffling can be done for 64-bit vectors right now.
10394 if (VT.getSizeInBits() == 64)
10395 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
10397 // FIXME: pshufb, blends, shifts.
10398 return (VT.getVectorNumElements() == 2 ||
10399 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
10400 isMOVLMask(M, VT) ||
10401 isSHUFPMask(M, VT) ||
10402 isPSHUFDMask(M, VT) ||
10403 isPSHUFHWMask(M, VT) ||
10404 isPSHUFLWMask(M, VT) ||
10405 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
10406 isUNPCKLMask(M, VT) ||
10407 isUNPCKHMask(M, VT) ||
10408 isUNPCKL_v_undef_Mask(M, VT) ||
10409 isUNPCKH_v_undef_Mask(M, VT));
10413 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
10415 unsigned NumElts = VT.getVectorNumElements();
10416 // FIXME: This collection of masks seems suspect.
10419 if (NumElts == 4 && VT.getSizeInBits() == 128) {
10420 return (isMOVLMask(Mask, VT) ||
10421 isCommutedMOVLMask(Mask, VT, true) ||
10422 isSHUFPMask(Mask, VT) ||
10423 isCommutedSHUFPMask(Mask, VT));
10428 //===----------------------------------------------------------------------===//
10429 // X86 Scheduler Hooks
10430 //===----------------------------------------------------------------------===//
10432 // private utility function
10433 MachineBasicBlock *
10434 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
10435 MachineBasicBlock *MBB,
10442 TargetRegisterClass *RC,
10443 bool invSrc) const {
10444 // For the atomic bitwise operator, we generate
10447 // ld t1 = [bitinstr.addr]
10448 // op t2 = t1, [bitinstr.val]
10450 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10452 // fallthrough -->nextMBB
10453 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10454 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10455 MachineFunction::iterator MBBIter = MBB;
10458 /// First build the CFG
10459 MachineFunction *F = MBB->getParent();
10460 MachineBasicBlock *thisMBB = MBB;
10461 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10462 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10463 F->insert(MBBIter, newMBB);
10464 F->insert(MBBIter, nextMBB);
10466 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10467 nextMBB->splice(nextMBB->begin(), thisMBB,
10468 llvm::next(MachineBasicBlock::iterator(bInstr)),
10470 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10472 // Update thisMBB to fall through to newMBB
10473 thisMBB->addSuccessor(newMBB);
10475 // newMBB jumps to itself and fall through to nextMBB
10476 newMBB->addSuccessor(nextMBB);
10477 newMBB->addSuccessor(newMBB);
10479 // Insert instructions into newMBB based on incoming instruction
10480 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10481 "unexpected number of operands");
10482 DebugLoc dl = bInstr->getDebugLoc();
10483 MachineOperand& destOper = bInstr->getOperand(0);
10484 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10485 int numArgs = bInstr->getNumOperands() - 1;
10486 for (int i=0; i < numArgs; ++i)
10487 argOpers[i] = &bInstr->getOperand(i+1);
10489 // x86 address has 4 operands: base, index, scale, and displacement
10490 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10491 int valArgIndx = lastAddrIndx + 1;
10493 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10494 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
10495 for (int i=0; i <= lastAddrIndx; ++i)
10496 (*MIB).addOperand(*argOpers[i]);
10498 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
10500 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
10505 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10506 assert((argOpers[valArgIndx]->isReg() ||
10507 argOpers[valArgIndx]->isImm()) &&
10508 "invalid operand");
10509 if (argOpers[valArgIndx]->isReg())
10510 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
10512 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
10514 (*MIB).addOperand(*argOpers[valArgIndx]);
10516 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
10519 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
10520 for (int i=0; i <= lastAddrIndx; ++i)
10521 (*MIB).addOperand(*argOpers[i]);
10523 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10524 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10525 bInstr->memoperands_end());
10527 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10528 MIB.addReg(EAXreg);
10531 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10533 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10537 // private utility function: 64 bit atomics on 32 bit host.
10538 MachineBasicBlock *
10539 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
10540 MachineBasicBlock *MBB,
10545 bool invSrc) const {
10546 // For the atomic bitwise operator, we generate
10547 // thisMBB (instructions are in pairs, except cmpxchg8b)
10548 // ld t1,t2 = [bitinstr.addr]
10550 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
10551 // op t5, t6 <- out1, out2, [bitinstr.val]
10552 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
10553 // mov ECX, EBX <- t5, t6
10554 // mov EAX, EDX <- t1, t2
10555 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
10556 // mov t3, t4 <- EAX, EDX
10558 // result in out1, out2
10559 // fallthrough -->nextMBB
10561 const TargetRegisterClass *RC = X86::GR32RegisterClass;
10562 const unsigned LoadOpc = X86::MOV32rm;
10563 const unsigned NotOpc = X86::NOT32r;
10564 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10565 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10566 MachineFunction::iterator MBBIter = MBB;
10569 /// First build the CFG
10570 MachineFunction *F = MBB->getParent();
10571 MachineBasicBlock *thisMBB = MBB;
10572 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10573 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10574 F->insert(MBBIter, newMBB);
10575 F->insert(MBBIter, nextMBB);
10577 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10578 nextMBB->splice(nextMBB->begin(), thisMBB,
10579 llvm::next(MachineBasicBlock::iterator(bInstr)),
10581 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10583 // Update thisMBB to fall through to newMBB
10584 thisMBB->addSuccessor(newMBB);
10586 // newMBB jumps to itself and fall through to nextMBB
10587 newMBB->addSuccessor(nextMBB);
10588 newMBB->addSuccessor(newMBB);
10590 DebugLoc dl = bInstr->getDebugLoc();
10591 // Insert instructions into newMBB based on incoming instruction
10592 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
10593 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
10594 "unexpected number of operands");
10595 MachineOperand& dest1Oper = bInstr->getOperand(0);
10596 MachineOperand& dest2Oper = bInstr->getOperand(1);
10597 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10598 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
10599 argOpers[i] = &bInstr->getOperand(i+2);
10601 // We use some of the operands multiple times, so conservatively just
10602 // clear any kill flags that might be present.
10603 if (argOpers[i]->isReg() && argOpers[i]->isUse())
10604 argOpers[i]->setIsKill(false);
10607 // x86 address has 5 operands: base, index, scale, displacement, and segment.
10608 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10610 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10611 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
10612 for (int i=0; i <= lastAddrIndx; ++i)
10613 (*MIB).addOperand(*argOpers[i]);
10614 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10615 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
10616 // add 4 to displacement.
10617 for (int i=0; i <= lastAddrIndx-2; ++i)
10618 (*MIB).addOperand(*argOpers[i]);
10619 MachineOperand newOp3 = *(argOpers[3]);
10620 if (newOp3.isImm())
10621 newOp3.setImm(newOp3.getImm()+4);
10623 newOp3.setOffset(newOp3.getOffset()+4);
10624 (*MIB).addOperand(newOp3);
10625 (*MIB).addOperand(*argOpers[lastAddrIndx]);
10627 // t3/4 are defined later, at the bottom of the loop
10628 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
10629 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
10630 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
10631 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
10632 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
10633 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
10635 // The subsequent operations should be using the destination registers of
10636 //the PHI instructions.
10638 t1 = F->getRegInfo().createVirtualRegister(RC);
10639 t2 = F->getRegInfo().createVirtualRegister(RC);
10640 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
10641 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
10643 t1 = dest1Oper.getReg();
10644 t2 = dest2Oper.getReg();
10647 int valArgIndx = lastAddrIndx + 1;
10648 assert((argOpers[valArgIndx]->isReg() ||
10649 argOpers[valArgIndx]->isImm()) &&
10650 "invalid operand");
10651 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
10652 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
10653 if (argOpers[valArgIndx]->isReg())
10654 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
10656 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
10657 if (regOpcL != X86::MOV32rr)
10659 (*MIB).addOperand(*argOpers[valArgIndx]);
10660 assert(argOpers[valArgIndx + 1]->isReg() ==
10661 argOpers[valArgIndx]->isReg());
10662 assert(argOpers[valArgIndx + 1]->isImm() ==
10663 argOpers[valArgIndx]->isImm());
10664 if (argOpers[valArgIndx + 1]->isReg())
10665 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
10667 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
10668 if (regOpcH != X86::MOV32rr)
10670 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
10672 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
10674 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
10677 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
10679 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
10682 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
10683 for (int i=0; i <= lastAddrIndx; ++i)
10684 (*MIB).addOperand(*argOpers[i]);
10686 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10687 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10688 bInstr->memoperands_end());
10690 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
10691 MIB.addReg(X86::EAX);
10692 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
10693 MIB.addReg(X86::EDX);
10696 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10698 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10702 // private utility function
10703 MachineBasicBlock *
10704 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
10705 MachineBasicBlock *MBB,
10706 unsigned cmovOpc) const {
10707 // For the atomic min/max operator, we generate
10710 // ld t1 = [min/max.addr]
10711 // mov t2 = [min/max.val]
10713 // cmov[cond] t2 = t1
10715 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10717 // fallthrough -->nextMBB
10719 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10720 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10721 MachineFunction::iterator MBBIter = MBB;
10724 /// First build the CFG
10725 MachineFunction *F = MBB->getParent();
10726 MachineBasicBlock *thisMBB = MBB;
10727 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10728 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10729 F->insert(MBBIter, newMBB);
10730 F->insert(MBBIter, nextMBB);
10732 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10733 nextMBB->splice(nextMBB->begin(), thisMBB,
10734 llvm::next(MachineBasicBlock::iterator(mInstr)),
10736 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10738 // Update thisMBB to fall through to newMBB
10739 thisMBB->addSuccessor(newMBB);
10741 // newMBB jumps to newMBB and fall through to nextMBB
10742 newMBB->addSuccessor(nextMBB);
10743 newMBB->addSuccessor(newMBB);
10745 DebugLoc dl = mInstr->getDebugLoc();
10746 // Insert instructions into newMBB based on incoming instruction
10747 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10748 "unexpected number of operands");
10749 MachineOperand& destOper = mInstr->getOperand(0);
10750 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10751 int numArgs = mInstr->getNumOperands() - 1;
10752 for (int i=0; i < numArgs; ++i)
10753 argOpers[i] = &mInstr->getOperand(i+1);
10755 // x86 address has 4 operands: base, index, scale, and displacement
10756 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10757 int valArgIndx = lastAddrIndx + 1;
10759 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10760 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
10761 for (int i=0; i <= lastAddrIndx; ++i)
10762 (*MIB).addOperand(*argOpers[i]);
10764 // We only support register and immediate values
10765 assert((argOpers[valArgIndx]->isReg() ||
10766 argOpers[valArgIndx]->isImm()) &&
10767 "invalid operand");
10769 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10770 if (argOpers[valArgIndx]->isReg())
10771 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
10773 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
10774 (*MIB).addOperand(*argOpers[valArgIndx]);
10776 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
10779 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
10784 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10785 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
10789 // Cmp and exchange if none has modified the memory location
10790 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
10791 for (int i=0; i <= lastAddrIndx; ++i)
10792 (*MIB).addOperand(*argOpers[i]);
10794 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10795 (*MIB).setMemRefs(mInstr->memoperands_begin(),
10796 mInstr->memoperands_end());
10798 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10799 MIB.addReg(X86::EAX);
10802 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10804 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
10808 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
10809 // or XMM0_V32I8 in AVX all of this code can be replaced with that
10810 // in the .td file.
10811 MachineBasicBlock *
10812 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
10813 unsigned numArgs, bool memArg) const {
10814 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
10815 "Target must have SSE4.2 or AVX features enabled");
10817 DebugLoc dl = MI->getDebugLoc();
10818 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10820 if (!Subtarget->hasAVX()) {
10822 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
10824 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
10827 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
10829 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
10832 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
10833 for (unsigned i = 0; i < numArgs; ++i) {
10834 MachineOperand &Op = MI->getOperand(i+1);
10835 if (!(Op.isReg() && Op.isImplicit()))
10836 MIB.addOperand(Op);
10838 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
10839 .addReg(X86::XMM0);
10841 MI->eraseFromParent();
10845 MachineBasicBlock *
10846 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
10847 DebugLoc dl = MI->getDebugLoc();
10848 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10850 // Address into RAX/EAX, other two args into ECX, EDX.
10851 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
10852 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10853 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
10854 for (int i = 0; i < X86::AddrNumOperands; ++i)
10855 MIB.addOperand(MI->getOperand(i));
10857 unsigned ValOps = X86::AddrNumOperands;
10858 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
10859 .addReg(MI->getOperand(ValOps).getReg());
10860 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
10861 .addReg(MI->getOperand(ValOps+1).getReg());
10863 // The instruction doesn't actually take any operands though.
10864 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
10866 MI->eraseFromParent(); // The pseudo is gone now.
10870 MachineBasicBlock *
10871 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
10872 DebugLoc dl = MI->getDebugLoc();
10873 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10875 // First arg in ECX, the second in EAX.
10876 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
10877 .addReg(MI->getOperand(0).getReg());
10878 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
10879 .addReg(MI->getOperand(1).getReg());
10881 // The instruction doesn't actually take any operands though.
10882 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
10884 MI->eraseFromParent(); // The pseudo is gone now.
10888 MachineBasicBlock *
10889 X86TargetLowering::EmitVAARG64WithCustomInserter(
10891 MachineBasicBlock *MBB) const {
10892 // Emit va_arg instruction on X86-64.
10894 // Operands to this pseudo-instruction:
10895 // 0 ) Output : destination address (reg)
10896 // 1-5) Input : va_list address (addr, i64mem)
10897 // 6 ) ArgSize : Size (in bytes) of vararg type
10898 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
10899 // 8 ) Align : Alignment of type
10900 // 9 ) EFLAGS (implicit-def)
10902 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
10903 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
10905 unsigned DestReg = MI->getOperand(0).getReg();
10906 MachineOperand &Base = MI->getOperand(1);
10907 MachineOperand &Scale = MI->getOperand(2);
10908 MachineOperand &Index = MI->getOperand(3);
10909 MachineOperand &Disp = MI->getOperand(4);
10910 MachineOperand &Segment = MI->getOperand(5);
10911 unsigned ArgSize = MI->getOperand(6).getImm();
10912 unsigned ArgMode = MI->getOperand(7).getImm();
10913 unsigned Align = MI->getOperand(8).getImm();
10915 // Memory Reference
10916 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
10917 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
10918 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
10920 // Machine Information
10921 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10922 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
10923 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
10924 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
10925 DebugLoc DL = MI->getDebugLoc();
10927 // struct va_list {
10930 // i64 overflow_area (address)
10931 // i64 reg_save_area (address)
10933 // sizeof(va_list) = 24
10934 // alignment(va_list) = 8
10936 unsigned TotalNumIntRegs = 6;
10937 unsigned TotalNumXMMRegs = 8;
10938 bool UseGPOffset = (ArgMode == 1);
10939 bool UseFPOffset = (ArgMode == 2);
10940 unsigned MaxOffset = TotalNumIntRegs * 8 +
10941 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
10943 /* Align ArgSize to a multiple of 8 */
10944 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
10945 bool NeedsAlign = (Align > 8);
10947 MachineBasicBlock *thisMBB = MBB;
10948 MachineBasicBlock *overflowMBB;
10949 MachineBasicBlock *offsetMBB;
10950 MachineBasicBlock *endMBB;
10952 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
10953 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
10954 unsigned OffsetReg = 0;
10956 if (!UseGPOffset && !UseFPOffset) {
10957 // If we only pull from the overflow region, we don't create a branch.
10958 // We don't need to alter control flow.
10959 OffsetDestReg = 0; // unused
10960 OverflowDestReg = DestReg;
10963 overflowMBB = thisMBB;
10966 // First emit code to check if gp_offset (or fp_offset) is below the bound.
10967 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
10968 // If not, pull from overflow_area. (branch to overflowMBB)
10973 // offsetMBB overflowMBB
10978 // Registers for the PHI in endMBB
10979 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
10980 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
10982 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10983 MachineFunction *MF = MBB->getParent();
10984 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10985 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10986 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10988 MachineFunction::iterator MBBIter = MBB;
10991 // Insert the new basic blocks
10992 MF->insert(MBBIter, offsetMBB);
10993 MF->insert(MBBIter, overflowMBB);
10994 MF->insert(MBBIter, endMBB);
10996 // Transfer the remainder of MBB and its successor edges to endMBB.
10997 endMBB->splice(endMBB->begin(), thisMBB,
10998 llvm::next(MachineBasicBlock::iterator(MI)),
11000 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11002 // Make offsetMBB and overflowMBB successors of thisMBB
11003 thisMBB->addSuccessor(offsetMBB);
11004 thisMBB->addSuccessor(overflowMBB);
11006 // endMBB is a successor of both offsetMBB and overflowMBB
11007 offsetMBB->addSuccessor(endMBB);
11008 overflowMBB->addSuccessor(endMBB);
11010 // Load the offset value into a register
11011 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11012 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11016 .addDisp(Disp, UseFPOffset ? 4 : 0)
11017 .addOperand(Segment)
11018 .setMemRefs(MMOBegin, MMOEnd);
11020 // Check if there is enough room left to pull this argument.
11021 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11023 .addImm(MaxOffset + 8 - ArgSizeA8);
11025 // Branch to "overflowMBB" if offset >= max
11026 // Fall through to "offsetMBB" otherwise
11027 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11028 .addMBB(overflowMBB);
11031 // In offsetMBB, emit code to use the reg_save_area.
11033 assert(OffsetReg != 0);
11035 // Read the reg_save_area address.
11036 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11037 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11042 .addOperand(Segment)
11043 .setMemRefs(MMOBegin, MMOEnd);
11045 // Zero-extend the offset
11046 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11047 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11050 .addImm(X86::sub_32bit);
11052 // Add the offset to the reg_save_area to get the final address.
11053 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11054 .addReg(OffsetReg64)
11055 .addReg(RegSaveReg);
11057 // Compute the offset for the next argument
11058 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11059 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11061 .addImm(UseFPOffset ? 16 : 8);
11063 // Store it back into the va_list.
11064 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11068 .addDisp(Disp, UseFPOffset ? 4 : 0)
11069 .addOperand(Segment)
11070 .addReg(NextOffsetReg)
11071 .setMemRefs(MMOBegin, MMOEnd);
11074 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11079 // Emit code to use overflow area
11082 // Load the overflow_area address into a register.
11083 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11084 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11089 .addOperand(Segment)
11090 .setMemRefs(MMOBegin, MMOEnd);
11092 // If we need to align it, do so. Otherwise, just copy the address
11093 // to OverflowDestReg.
11095 // Align the overflow address
11096 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11097 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11099 // aligned_addr = (addr + (align-1)) & ~(align-1)
11100 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11101 .addReg(OverflowAddrReg)
11104 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11106 .addImm(~(uint64_t)(Align-1));
11108 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11109 .addReg(OverflowAddrReg);
11112 // Compute the next overflow address after this argument.
11113 // (the overflow address should be kept 8-byte aligned)
11114 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11115 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11116 .addReg(OverflowDestReg)
11117 .addImm(ArgSizeA8);
11119 // Store the new overflow address.
11120 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11125 .addOperand(Segment)
11126 .addReg(NextAddrReg)
11127 .setMemRefs(MMOBegin, MMOEnd);
11129 // If we branched, emit the PHI to the front of endMBB.
11131 BuildMI(*endMBB, endMBB->begin(), DL,
11132 TII->get(X86::PHI), DestReg)
11133 .addReg(OffsetDestReg).addMBB(offsetMBB)
11134 .addReg(OverflowDestReg).addMBB(overflowMBB);
11137 // Erase the pseudo instruction
11138 MI->eraseFromParent();
11143 MachineBasicBlock *
11144 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11146 MachineBasicBlock *MBB) const {
11147 // Emit code to save XMM registers to the stack. The ABI says that the
11148 // number of registers to save is given in %al, so it's theoretically
11149 // possible to do an indirect jump trick to avoid saving all of them,
11150 // however this code takes a simpler approach and just executes all
11151 // of the stores if %al is non-zero. It's less code, and it's probably
11152 // easier on the hardware branch predictor, and stores aren't all that
11153 // expensive anyway.
11155 // Create the new basic blocks. One block contains all the XMM stores,
11156 // and one block is the final destination regardless of whether any
11157 // stores were performed.
11158 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11159 MachineFunction *F = MBB->getParent();
11160 MachineFunction::iterator MBBIter = MBB;
11162 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11163 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11164 F->insert(MBBIter, XMMSaveMBB);
11165 F->insert(MBBIter, EndMBB);
11167 // Transfer the remainder of MBB and its successor edges to EndMBB.
11168 EndMBB->splice(EndMBB->begin(), MBB,
11169 llvm::next(MachineBasicBlock::iterator(MI)),
11171 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11173 // The original block will now fall through to the XMM save block.
11174 MBB->addSuccessor(XMMSaveMBB);
11175 // The XMMSaveMBB will fall through to the end block.
11176 XMMSaveMBB->addSuccessor(EndMBB);
11178 // Now add the instructions.
11179 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11180 DebugLoc DL = MI->getDebugLoc();
11182 unsigned CountReg = MI->getOperand(0).getReg();
11183 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11184 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11186 if (!Subtarget->isTargetWin64()) {
11187 // If %al is 0, branch around the XMM save block.
11188 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11189 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11190 MBB->addSuccessor(EndMBB);
11193 // In the XMM save block, save all the XMM argument registers.
11194 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11195 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11196 MachineMemOperand *MMO =
11197 F->getMachineMemOperand(
11198 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11199 MachineMemOperand::MOStore,
11200 /*Size=*/16, /*Align=*/16);
11201 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
11202 .addFrameIndex(RegSaveFrameIndex)
11203 .addImm(/*Scale=*/1)
11204 .addReg(/*IndexReg=*/0)
11205 .addImm(/*Disp=*/Offset)
11206 .addReg(/*Segment=*/0)
11207 .addReg(MI->getOperand(i).getReg())
11208 .addMemOperand(MMO);
11211 MI->eraseFromParent(); // The pseudo instruction is gone now.
11216 MachineBasicBlock *
11217 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11218 MachineBasicBlock *BB) const {
11219 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11220 DebugLoc DL = MI->getDebugLoc();
11222 // To "insert" a SELECT_CC instruction, we actually have to insert the
11223 // diamond control-flow pattern. The incoming instruction knows the
11224 // destination vreg to set, the condition code register to branch on, the
11225 // true/false values to select between, and a branch opcode to use.
11226 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11227 MachineFunction::iterator It = BB;
11233 // cmpTY ccX, r1, r2
11235 // fallthrough --> copy0MBB
11236 MachineBasicBlock *thisMBB = BB;
11237 MachineFunction *F = BB->getParent();
11238 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11239 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11240 F->insert(It, copy0MBB);
11241 F->insert(It, sinkMBB);
11243 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11244 // live into the sink and copy blocks.
11245 const MachineFunction *MF = BB->getParent();
11246 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
11247 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
11249 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
11250 const MachineOperand &MO = MI->getOperand(I);
11251 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
11252 unsigned Reg = MO.getReg();
11253 if (Reg != X86::EFLAGS) continue;
11254 copy0MBB->addLiveIn(Reg);
11255 sinkMBB->addLiveIn(Reg);
11258 // Transfer the remainder of BB and its successor edges to sinkMBB.
11259 sinkMBB->splice(sinkMBB->begin(), BB,
11260 llvm::next(MachineBasicBlock::iterator(MI)),
11262 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11264 // Add the true and fallthrough blocks as its successors.
11265 BB->addSuccessor(copy0MBB);
11266 BB->addSuccessor(sinkMBB);
11268 // Create the conditional branch instruction.
11270 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11271 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11274 // %FalseValue = ...
11275 // # fallthrough to sinkMBB
11276 copy0MBB->addSuccessor(sinkMBB);
11279 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11281 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11282 TII->get(X86::PHI), MI->getOperand(0).getReg())
11283 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11284 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11286 MI->eraseFromParent(); // The pseudo instruction is gone now.
11290 MachineBasicBlock *
11291 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
11292 MachineBasicBlock *BB) const {
11293 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11294 DebugLoc DL = MI->getDebugLoc();
11296 assert(!Subtarget->isTargetEnvMacho());
11298 // The lowering is pretty easy: we're just emitting the call to _alloca. The
11299 // non-trivial part is impdef of ESP.
11301 if (Subtarget->isTargetWin64()) {
11302 if (Subtarget->isTargetCygMing()) {
11303 // ___chkstk(Mingw64):
11304 // Clobbers R10, R11, RAX and EFLAGS.
11306 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11307 .addExternalSymbol("___chkstk")
11308 .addReg(X86::RAX, RegState::Implicit)
11309 .addReg(X86::RSP, RegState::Implicit)
11310 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
11311 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
11312 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11314 // __chkstk(MSVCRT): does not update stack pointer.
11315 // Clobbers R10, R11 and EFLAGS.
11316 // FIXME: RAX(allocated size) might be reused and not killed.
11317 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11318 .addExternalSymbol("__chkstk")
11319 .addReg(X86::RAX, RegState::Implicit)
11320 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11321 // RAX has the offset to subtracted from RSP.
11322 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
11327 const char *StackProbeSymbol =
11328 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
11330 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
11331 .addExternalSymbol(StackProbeSymbol)
11332 .addReg(X86::EAX, RegState::Implicit)
11333 .addReg(X86::ESP, RegState::Implicit)
11334 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
11335 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
11336 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11339 MI->eraseFromParent(); // The pseudo instruction is gone now.
11343 MachineBasicBlock *
11344 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
11345 MachineBasicBlock *BB) const {
11346 // This is pretty easy. We're taking the value that we received from
11347 // our load from the relocation, sticking it in either RDI (x86-64)
11348 // or EAX and doing an indirect call. The return value will then
11349 // be in the normal return register.
11350 const X86InstrInfo *TII
11351 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
11352 DebugLoc DL = MI->getDebugLoc();
11353 MachineFunction *F = BB->getParent();
11355 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
11356 assert(MI->getOperand(3).isGlobal() && "This should be a global");
11358 if (Subtarget->is64Bit()) {
11359 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11360 TII->get(X86::MOV64rm), X86::RDI)
11362 .addImm(0).addReg(0)
11363 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11364 MI->getOperand(3).getTargetFlags())
11366 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
11367 addDirectMem(MIB, X86::RDI);
11368 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
11369 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11370 TII->get(X86::MOV32rm), X86::EAX)
11372 .addImm(0).addReg(0)
11373 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11374 MI->getOperand(3).getTargetFlags())
11376 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11377 addDirectMem(MIB, X86::EAX);
11379 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11380 TII->get(X86::MOV32rm), X86::EAX)
11381 .addReg(TII->getGlobalBaseReg(F))
11382 .addImm(0).addReg(0)
11383 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11384 MI->getOperand(3).getTargetFlags())
11386 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11387 addDirectMem(MIB, X86::EAX);
11390 MI->eraseFromParent(); // The pseudo instruction is gone now.
11394 MachineBasicBlock *
11395 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
11396 MachineBasicBlock *BB) const {
11397 switch (MI->getOpcode()) {
11398 default: assert(false && "Unexpected instr type to insert");
11399 case X86::TAILJMPd64:
11400 case X86::TAILJMPr64:
11401 case X86::TAILJMPm64:
11402 assert(!"TAILJMP64 would not be touched here.");
11403 case X86::TCRETURNdi64:
11404 case X86::TCRETURNri64:
11405 case X86::TCRETURNmi64:
11406 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
11407 // On AMD64, additional defs should be added before register allocation.
11408 if (!Subtarget->isTargetWin64()) {
11409 MI->addRegisterDefined(X86::RSI);
11410 MI->addRegisterDefined(X86::RDI);
11411 MI->addRegisterDefined(X86::XMM6);
11412 MI->addRegisterDefined(X86::XMM7);
11413 MI->addRegisterDefined(X86::XMM8);
11414 MI->addRegisterDefined(X86::XMM9);
11415 MI->addRegisterDefined(X86::XMM10);
11416 MI->addRegisterDefined(X86::XMM11);
11417 MI->addRegisterDefined(X86::XMM12);
11418 MI->addRegisterDefined(X86::XMM13);
11419 MI->addRegisterDefined(X86::XMM14);
11420 MI->addRegisterDefined(X86::XMM15);
11423 case X86::WIN_ALLOCA:
11424 return EmitLoweredWinAlloca(MI, BB);
11425 case X86::TLSCall_32:
11426 case X86::TLSCall_64:
11427 return EmitLoweredTLSCall(MI, BB);
11428 case X86::CMOV_GR8:
11429 case X86::CMOV_FR32:
11430 case X86::CMOV_FR64:
11431 case X86::CMOV_V4F32:
11432 case X86::CMOV_V2F64:
11433 case X86::CMOV_V2I64:
11434 case X86::CMOV_V8F32:
11435 case X86::CMOV_V4F64:
11436 case X86::CMOV_V4I64:
11437 case X86::CMOV_GR16:
11438 case X86::CMOV_GR32:
11439 case X86::CMOV_RFP32:
11440 case X86::CMOV_RFP64:
11441 case X86::CMOV_RFP80:
11442 return EmitLoweredSelect(MI, BB);
11444 case X86::FP32_TO_INT16_IN_MEM:
11445 case X86::FP32_TO_INT32_IN_MEM:
11446 case X86::FP32_TO_INT64_IN_MEM:
11447 case X86::FP64_TO_INT16_IN_MEM:
11448 case X86::FP64_TO_INT32_IN_MEM:
11449 case X86::FP64_TO_INT64_IN_MEM:
11450 case X86::FP80_TO_INT16_IN_MEM:
11451 case X86::FP80_TO_INT32_IN_MEM:
11452 case X86::FP80_TO_INT64_IN_MEM: {
11453 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11454 DebugLoc DL = MI->getDebugLoc();
11456 // Change the floating point control register to use "round towards zero"
11457 // mode when truncating to an integer value.
11458 MachineFunction *F = BB->getParent();
11459 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
11460 addFrameReference(BuildMI(*BB, MI, DL,
11461 TII->get(X86::FNSTCW16m)), CWFrameIdx);
11463 // Load the old value of the high byte of the control word...
11465 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
11466 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
11469 // Set the high part to be round to zero...
11470 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
11473 // Reload the modified control word now...
11474 addFrameReference(BuildMI(*BB, MI, DL,
11475 TII->get(X86::FLDCW16m)), CWFrameIdx);
11477 // Restore the memory image of control word to original value
11478 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
11481 // Get the X86 opcode to use.
11483 switch (MI->getOpcode()) {
11484 default: llvm_unreachable("illegal opcode!");
11485 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
11486 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
11487 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
11488 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
11489 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
11490 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
11491 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
11492 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
11493 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
11497 MachineOperand &Op = MI->getOperand(0);
11499 AM.BaseType = X86AddressMode::RegBase;
11500 AM.Base.Reg = Op.getReg();
11502 AM.BaseType = X86AddressMode::FrameIndexBase;
11503 AM.Base.FrameIndex = Op.getIndex();
11505 Op = MI->getOperand(1);
11507 AM.Scale = Op.getImm();
11508 Op = MI->getOperand(2);
11510 AM.IndexReg = Op.getImm();
11511 Op = MI->getOperand(3);
11512 if (Op.isGlobal()) {
11513 AM.GV = Op.getGlobal();
11515 AM.Disp = Op.getImm();
11517 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
11518 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
11520 // Reload the original control word now.
11521 addFrameReference(BuildMI(*BB, MI, DL,
11522 TII->get(X86::FLDCW16m)), CWFrameIdx);
11524 MI->eraseFromParent(); // The pseudo instruction is gone now.
11527 // String/text processing lowering.
11528 case X86::PCMPISTRM128REG:
11529 case X86::VPCMPISTRM128REG:
11530 return EmitPCMP(MI, BB, 3, false /* in-mem */);
11531 case X86::PCMPISTRM128MEM:
11532 case X86::VPCMPISTRM128MEM:
11533 return EmitPCMP(MI, BB, 3, true /* in-mem */);
11534 case X86::PCMPESTRM128REG:
11535 case X86::VPCMPESTRM128REG:
11536 return EmitPCMP(MI, BB, 5, false /* in mem */);
11537 case X86::PCMPESTRM128MEM:
11538 case X86::VPCMPESTRM128MEM:
11539 return EmitPCMP(MI, BB, 5, true /* in mem */);
11541 // Thread synchronization.
11543 return EmitMonitor(MI, BB);
11545 return EmitMwait(MI, BB);
11547 // Atomic Lowering.
11548 case X86::ATOMAND32:
11549 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11550 X86::AND32ri, X86::MOV32rm,
11552 X86::NOT32r, X86::EAX,
11553 X86::GR32RegisterClass);
11554 case X86::ATOMOR32:
11555 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
11556 X86::OR32ri, X86::MOV32rm,
11558 X86::NOT32r, X86::EAX,
11559 X86::GR32RegisterClass);
11560 case X86::ATOMXOR32:
11561 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
11562 X86::XOR32ri, X86::MOV32rm,
11564 X86::NOT32r, X86::EAX,
11565 X86::GR32RegisterClass);
11566 case X86::ATOMNAND32:
11567 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11568 X86::AND32ri, X86::MOV32rm,
11570 X86::NOT32r, X86::EAX,
11571 X86::GR32RegisterClass, true);
11572 case X86::ATOMMIN32:
11573 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
11574 case X86::ATOMMAX32:
11575 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
11576 case X86::ATOMUMIN32:
11577 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
11578 case X86::ATOMUMAX32:
11579 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
11581 case X86::ATOMAND16:
11582 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11583 X86::AND16ri, X86::MOV16rm,
11585 X86::NOT16r, X86::AX,
11586 X86::GR16RegisterClass);
11587 case X86::ATOMOR16:
11588 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
11589 X86::OR16ri, X86::MOV16rm,
11591 X86::NOT16r, X86::AX,
11592 X86::GR16RegisterClass);
11593 case X86::ATOMXOR16:
11594 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
11595 X86::XOR16ri, X86::MOV16rm,
11597 X86::NOT16r, X86::AX,
11598 X86::GR16RegisterClass);
11599 case X86::ATOMNAND16:
11600 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11601 X86::AND16ri, X86::MOV16rm,
11603 X86::NOT16r, X86::AX,
11604 X86::GR16RegisterClass, true);
11605 case X86::ATOMMIN16:
11606 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
11607 case X86::ATOMMAX16:
11608 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
11609 case X86::ATOMUMIN16:
11610 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
11611 case X86::ATOMUMAX16:
11612 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
11614 case X86::ATOMAND8:
11615 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11616 X86::AND8ri, X86::MOV8rm,
11618 X86::NOT8r, X86::AL,
11619 X86::GR8RegisterClass);
11621 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
11622 X86::OR8ri, X86::MOV8rm,
11624 X86::NOT8r, X86::AL,
11625 X86::GR8RegisterClass);
11626 case X86::ATOMXOR8:
11627 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
11628 X86::XOR8ri, X86::MOV8rm,
11630 X86::NOT8r, X86::AL,
11631 X86::GR8RegisterClass);
11632 case X86::ATOMNAND8:
11633 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11634 X86::AND8ri, X86::MOV8rm,
11636 X86::NOT8r, X86::AL,
11637 X86::GR8RegisterClass, true);
11638 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
11639 // This group is for 64-bit host.
11640 case X86::ATOMAND64:
11641 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11642 X86::AND64ri32, X86::MOV64rm,
11644 X86::NOT64r, X86::RAX,
11645 X86::GR64RegisterClass);
11646 case X86::ATOMOR64:
11647 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
11648 X86::OR64ri32, X86::MOV64rm,
11650 X86::NOT64r, X86::RAX,
11651 X86::GR64RegisterClass);
11652 case X86::ATOMXOR64:
11653 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
11654 X86::XOR64ri32, X86::MOV64rm,
11656 X86::NOT64r, X86::RAX,
11657 X86::GR64RegisterClass);
11658 case X86::ATOMNAND64:
11659 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11660 X86::AND64ri32, X86::MOV64rm,
11662 X86::NOT64r, X86::RAX,
11663 X86::GR64RegisterClass, true);
11664 case X86::ATOMMIN64:
11665 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
11666 case X86::ATOMMAX64:
11667 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
11668 case X86::ATOMUMIN64:
11669 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
11670 case X86::ATOMUMAX64:
11671 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
11673 // This group does 64-bit operations on a 32-bit host.
11674 case X86::ATOMAND6432:
11675 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11676 X86::AND32rr, X86::AND32rr,
11677 X86::AND32ri, X86::AND32ri,
11679 case X86::ATOMOR6432:
11680 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11681 X86::OR32rr, X86::OR32rr,
11682 X86::OR32ri, X86::OR32ri,
11684 case X86::ATOMXOR6432:
11685 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11686 X86::XOR32rr, X86::XOR32rr,
11687 X86::XOR32ri, X86::XOR32ri,
11689 case X86::ATOMNAND6432:
11690 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11691 X86::AND32rr, X86::AND32rr,
11692 X86::AND32ri, X86::AND32ri,
11694 case X86::ATOMADD6432:
11695 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11696 X86::ADD32rr, X86::ADC32rr,
11697 X86::ADD32ri, X86::ADC32ri,
11699 case X86::ATOMSUB6432:
11700 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11701 X86::SUB32rr, X86::SBB32rr,
11702 X86::SUB32ri, X86::SBB32ri,
11704 case X86::ATOMSWAP6432:
11705 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11706 X86::MOV32rr, X86::MOV32rr,
11707 X86::MOV32ri, X86::MOV32ri,
11709 case X86::VASTART_SAVE_XMM_REGS:
11710 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
11712 case X86::VAARG_64:
11713 return EmitVAARG64WithCustomInserter(MI, BB);
11717 //===----------------------------------------------------------------------===//
11718 // X86 Optimization Hooks
11719 //===----------------------------------------------------------------------===//
11721 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
11725 const SelectionDAG &DAG,
11726 unsigned Depth) const {
11727 unsigned Opc = Op.getOpcode();
11728 assert((Opc >= ISD::BUILTIN_OP_END ||
11729 Opc == ISD::INTRINSIC_WO_CHAIN ||
11730 Opc == ISD::INTRINSIC_W_CHAIN ||
11731 Opc == ISD::INTRINSIC_VOID) &&
11732 "Should use MaskedValueIsZero if you don't know whether Op"
11733 " is a target node!");
11735 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
11749 // These nodes' second result is a boolean.
11750 if (Op.getResNo() == 0)
11753 case X86ISD::SETCC:
11754 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
11755 Mask.getBitWidth() - 1);
11760 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
11761 unsigned Depth) const {
11762 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
11763 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
11764 return Op.getValueType().getScalarType().getSizeInBits();
11770 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
11771 /// node is a GlobalAddress + offset.
11772 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
11773 const GlobalValue* &GA,
11774 int64_t &Offset) const {
11775 if (N->getOpcode() == X86ISD::Wrapper) {
11776 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
11777 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
11778 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
11782 return TargetLowering::isGAPlusOffset(N, GA, Offset);
11785 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
11786 /// same as extracting the high 128-bit part of 256-bit vector and then
11787 /// inserting the result into the low part of a new 256-bit vector
11788 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
11789 EVT VT = SVOp->getValueType(0);
11790 int NumElems = VT.getVectorNumElements();
11792 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
11793 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
11794 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
11795 SVOp->getMaskElt(j) >= 0)
11801 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
11802 /// same as extracting the low 128-bit part of 256-bit vector and then
11803 /// inserting the result into the high part of a new 256-bit vector
11804 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
11805 EVT VT = SVOp->getValueType(0);
11806 int NumElems = VT.getVectorNumElements();
11808 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
11809 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
11810 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
11811 SVOp->getMaskElt(j) >= 0)
11817 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
11818 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
11819 TargetLowering::DAGCombinerInfo &DCI) {
11820 DebugLoc dl = N->getDebugLoc();
11821 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
11822 SDValue V1 = SVOp->getOperand(0);
11823 SDValue V2 = SVOp->getOperand(1);
11824 EVT VT = SVOp->getValueType(0);
11825 int NumElems = VT.getVectorNumElements();
11827 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
11828 V2.getOpcode() == ISD::CONCAT_VECTORS) {
11832 // V UNDEF BUILD_VECTOR UNDEF
11834 // CONCAT_VECTOR CONCAT_VECTOR
11837 // RESULT: V + zero extended
11839 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
11840 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
11841 V1.getOperand(1).getOpcode() != ISD::UNDEF)
11844 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
11847 // To match the shuffle mask, the first half of the mask should
11848 // be exactly the first vector, and all the rest a splat with the
11849 // first element of the second one.
11850 for (int i = 0; i < NumElems/2; ++i)
11851 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
11852 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
11855 // Emit a zeroed vector and insert the desired subvector on its
11857 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl);
11858 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
11859 DAG.getConstant(0, MVT::i32), DAG, dl);
11860 return DCI.CombineTo(N, InsV);
11863 //===--------------------------------------------------------------------===//
11864 // Combine some shuffles into subvector extracts and inserts:
11867 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
11868 if (isShuffleHigh128VectorInsertLow(SVOp)) {
11869 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
11871 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
11872 V, DAG.getConstant(0, MVT::i32), DAG, dl);
11873 return DCI.CombineTo(N, InsV);
11876 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
11877 if (isShuffleLow128VectorInsertHigh(SVOp)) {
11878 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
11879 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
11880 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
11881 return DCI.CombineTo(N, InsV);
11887 /// PerformShuffleCombine - Performs several different shuffle combines.
11888 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
11889 TargetLowering::DAGCombinerInfo &DCI,
11890 const X86Subtarget *Subtarget) {
11891 DebugLoc dl = N->getDebugLoc();
11892 EVT VT = N->getValueType(0);
11894 // Don't create instructions with illegal types after legalize types has run.
11895 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11896 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
11899 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
11900 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
11901 N->getOpcode() == ISD::VECTOR_SHUFFLE)
11902 return PerformShuffleCombine256(N, DAG, DCI);
11904 // Only handle 128 wide vector from here on.
11905 if (VT.getSizeInBits() != 128)
11908 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
11909 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
11910 // consecutive, non-overlapping, and in the right order.
11911 SmallVector<SDValue, 16> Elts;
11912 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
11913 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
11915 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
11918 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
11919 /// generation and convert it from being a bunch of shuffles and extracts
11920 /// to a simple store and scalar loads to extract the elements.
11921 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
11922 const TargetLowering &TLI) {
11923 SDValue InputVector = N->getOperand(0);
11925 // Only operate on vectors of 4 elements, where the alternative shuffling
11926 // gets to be more expensive.
11927 if (InputVector.getValueType() != MVT::v4i32)
11930 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
11931 // single use which is a sign-extend or zero-extend, and all elements are
11933 SmallVector<SDNode *, 4> Uses;
11934 unsigned ExtractedElements = 0;
11935 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
11936 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
11937 if (UI.getUse().getResNo() != InputVector.getResNo())
11940 SDNode *Extract = *UI;
11941 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11944 if (Extract->getValueType(0) != MVT::i32)
11946 if (!Extract->hasOneUse())
11948 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
11949 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
11951 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
11954 // Record which element was extracted.
11955 ExtractedElements |=
11956 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
11958 Uses.push_back(Extract);
11961 // If not all the elements were used, this may not be worthwhile.
11962 if (ExtractedElements != 15)
11965 // Ok, we've now decided to do the transformation.
11966 DebugLoc dl = InputVector.getDebugLoc();
11968 // Store the value to a temporary stack slot.
11969 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
11970 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
11971 MachinePointerInfo(), false, false, 0);
11973 // Replace each use (extract) with a load of the appropriate element.
11974 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
11975 UE = Uses.end(); UI != UE; ++UI) {
11976 SDNode *Extract = *UI;
11978 // cOMpute the element's address.
11979 SDValue Idx = Extract->getOperand(1);
11981 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
11982 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
11983 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
11985 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
11986 StackPtr, OffsetVal);
11988 // Load the scalar.
11989 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
11990 ScalarAddr, MachinePointerInfo(),
11993 // Replace the exact with the load.
11994 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
11997 // The replacement was made in place; don't return anything.
12001 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
12002 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12003 const X86Subtarget *Subtarget) {
12004 DebugLoc DL = N->getDebugLoc();
12005 SDValue Cond = N->getOperand(0);
12006 // Get the LHS/RHS of the select.
12007 SDValue LHS = N->getOperand(1);
12008 SDValue RHS = N->getOperand(2);
12010 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12011 // instructions match the semantics of the common C idiom x<y?x:y but not
12012 // x<=y?x:y, because of how they handle negative zero (which can be
12013 // ignored in unsafe-math mode).
12014 if (Subtarget->hasSSE2() &&
12015 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
12016 Cond.getOpcode() == ISD::SETCC) {
12017 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12019 unsigned Opcode = 0;
12020 // Check for x CC y ? x : y.
12021 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12022 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12026 // Converting this to a min would handle NaNs incorrectly, and swapping
12027 // the operands would cause it to handle comparisons between positive
12028 // and negative zero incorrectly.
12029 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12030 if (!UnsafeFPMath &&
12031 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12033 std::swap(LHS, RHS);
12035 Opcode = X86ISD::FMIN;
12038 // Converting this to a min would handle comparisons between positive
12039 // and negative zero incorrectly.
12040 if (!UnsafeFPMath &&
12041 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12043 Opcode = X86ISD::FMIN;
12046 // Converting this to a min would handle both negative zeros and NaNs
12047 // incorrectly, but we can swap the operands to fix both.
12048 std::swap(LHS, RHS);
12052 Opcode = X86ISD::FMIN;
12056 // Converting this to a max would handle comparisons between positive
12057 // and negative zero incorrectly.
12058 if (!UnsafeFPMath &&
12059 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12061 Opcode = X86ISD::FMAX;
12064 // Converting this to a max would handle NaNs incorrectly, and swapping
12065 // the operands would cause it to handle comparisons between positive
12066 // and negative zero incorrectly.
12067 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12068 if (!UnsafeFPMath &&
12069 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12071 std::swap(LHS, RHS);
12073 Opcode = X86ISD::FMAX;
12076 // Converting this to a max would handle both negative zeros and NaNs
12077 // incorrectly, but we can swap the operands to fix both.
12078 std::swap(LHS, RHS);
12082 Opcode = X86ISD::FMAX;
12085 // Check for x CC y ? y : x -- a min/max with reversed arms.
12086 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12087 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12091 // Converting this to a min would handle comparisons between positive
12092 // and negative zero incorrectly, and swapping the operands would
12093 // cause it to handle NaNs incorrectly.
12094 if (!UnsafeFPMath &&
12095 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12096 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12098 std::swap(LHS, RHS);
12100 Opcode = X86ISD::FMIN;
12103 // Converting this to a min would handle NaNs incorrectly.
12104 if (!UnsafeFPMath &&
12105 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12107 Opcode = X86ISD::FMIN;
12110 // Converting this to a min would handle both negative zeros and NaNs
12111 // incorrectly, but we can swap the operands to fix both.
12112 std::swap(LHS, RHS);
12116 Opcode = X86ISD::FMIN;
12120 // Converting this to a max would handle NaNs incorrectly.
12121 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12123 Opcode = X86ISD::FMAX;
12126 // Converting this to a max would handle comparisons between positive
12127 // and negative zero incorrectly, and swapping the operands would
12128 // cause it to handle NaNs incorrectly.
12129 if (!UnsafeFPMath &&
12130 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12131 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12133 std::swap(LHS, RHS);
12135 Opcode = X86ISD::FMAX;
12138 // Converting this to a max would handle both negative zeros and NaNs
12139 // incorrectly, but we can swap the operands to fix both.
12140 std::swap(LHS, RHS);
12144 Opcode = X86ISD::FMAX;
12150 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
12153 // If this is a select between two integer constants, try to do some
12155 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
12156 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
12157 // Don't do this for crazy integer types.
12158 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
12159 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
12160 // so that TrueC (the true value) is larger than FalseC.
12161 bool NeedsCondInvert = false;
12163 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
12164 // Efficiently invertible.
12165 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
12166 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
12167 isa<ConstantSDNode>(Cond.getOperand(1))))) {
12168 NeedsCondInvert = true;
12169 std::swap(TrueC, FalseC);
12172 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
12173 if (FalseC->getAPIntValue() == 0 &&
12174 TrueC->getAPIntValue().isPowerOf2()) {
12175 if (NeedsCondInvert) // Invert the condition if needed.
12176 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12177 DAG.getConstant(1, Cond.getValueType()));
12179 // Zero extend the condition if needed.
12180 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
12182 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12183 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
12184 DAG.getConstant(ShAmt, MVT::i8));
12187 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
12188 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12189 if (NeedsCondInvert) // Invert the condition if needed.
12190 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12191 DAG.getConstant(1, Cond.getValueType()));
12193 // Zero extend the condition if needed.
12194 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12195 FalseC->getValueType(0), Cond);
12196 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12197 SDValue(FalseC, 0));
12200 // Optimize cases that will turn into an LEA instruction. This requires
12201 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12202 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12203 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12204 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12206 bool isFastMultiplier = false;
12208 switch ((unsigned char)Diff) {
12210 case 1: // result = add base, cond
12211 case 2: // result = lea base( , cond*2)
12212 case 3: // result = lea base(cond, cond*2)
12213 case 4: // result = lea base( , cond*4)
12214 case 5: // result = lea base(cond, cond*4)
12215 case 8: // result = lea base( , cond*8)
12216 case 9: // result = lea base(cond, cond*8)
12217 isFastMultiplier = true;
12222 if (isFastMultiplier) {
12223 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12224 if (NeedsCondInvert) // Invert the condition if needed.
12225 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12226 DAG.getConstant(1, Cond.getValueType()));
12228 // Zero extend the condition if needed.
12229 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12231 // Scale the condition by the difference.
12233 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12234 DAG.getConstant(Diff, Cond.getValueType()));
12236 // Add the base if non-zero.
12237 if (FalseC->getAPIntValue() != 0)
12238 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12239 SDValue(FalseC, 0));
12249 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
12250 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
12251 TargetLowering::DAGCombinerInfo &DCI) {
12252 DebugLoc DL = N->getDebugLoc();
12254 // If the flag operand isn't dead, don't touch this CMOV.
12255 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
12258 SDValue FalseOp = N->getOperand(0);
12259 SDValue TrueOp = N->getOperand(1);
12260 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
12261 SDValue Cond = N->getOperand(3);
12262 if (CC == X86::COND_E || CC == X86::COND_NE) {
12263 switch (Cond.getOpcode()) {
12267 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
12268 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
12269 return (CC == X86::COND_E) ? FalseOp : TrueOp;
12273 // If this is a select between two integer constants, try to do some
12274 // optimizations. Note that the operands are ordered the opposite of SELECT
12276 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
12277 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
12278 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
12279 // larger than FalseC (the false value).
12280 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
12281 CC = X86::GetOppositeBranchCondition(CC);
12282 std::swap(TrueC, FalseC);
12285 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
12286 // This is efficient for any integer data type (including i8/i16) and
12288 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
12289 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12290 DAG.getConstant(CC, MVT::i8), Cond);
12292 // Zero extend the condition if needed.
12293 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
12295 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12296 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
12297 DAG.getConstant(ShAmt, MVT::i8));
12298 if (N->getNumValues() == 2) // Dead flag value?
12299 return DCI.CombineTo(N, Cond, SDValue());
12303 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
12304 // for any integer data type, including i8/i16.
12305 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12306 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12307 DAG.getConstant(CC, MVT::i8), Cond);
12309 // Zero extend the condition if needed.
12310 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12311 FalseC->getValueType(0), Cond);
12312 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12313 SDValue(FalseC, 0));
12315 if (N->getNumValues() == 2) // Dead flag value?
12316 return DCI.CombineTo(N, Cond, SDValue());
12320 // Optimize cases that will turn into an LEA instruction. This requires
12321 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12322 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12323 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12324 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12326 bool isFastMultiplier = false;
12328 switch ((unsigned char)Diff) {
12330 case 1: // result = add base, cond
12331 case 2: // result = lea base( , cond*2)
12332 case 3: // result = lea base(cond, cond*2)
12333 case 4: // result = lea base( , cond*4)
12334 case 5: // result = lea base(cond, cond*4)
12335 case 8: // result = lea base( , cond*8)
12336 case 9: // result = lea base(cond, cond*8)
12337 isFastMultiplier = true;
12342 if (isFastMultiplier) {
12343 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12344 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12345 DAG.getConstant(CC, MVT::i8), Cond);
12346 // Zero extend the condition if needed.
12347 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12349 // Scale the condition by the difference.
12351 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12352 DAG.getConstant(Diff, Cond.getValueType()));
12354 // Add the base if non-zero.
12355 if (FalseC->getAPIntValue() != 0)
12356 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12357 SDValue(FalseC, 0));
12358 if (N->getNumValues() == 2) // Dead flag value?
12359 return DCI.CombineTo(N, Cond, SDValue());
12369 /// PerformMulCombine - Optimize a single multiply with constant into two
12370 /// in order to implement it with two cheaper instructions, e.g.
12371 /// LEA + SHL, LEA + LEA.
12372 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
12373 TargetLowering::DAGCombinerInfo &DCI) {
12374 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
12377 EVT VT = N->getValueType(0);
12378 if (VT != MVT::i64)
12381 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
12384 uint64_t MulAmt = C->getZExtValue();
12385 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
12388 uint64_t MulAmt1 = 0;
12389 uint64_t MulAmt2 = 0;
12390 if ((MulAmt % 9) == 0) {
12392 MulAmt2 = MulAmt / 9;
12393 } else if ((MulAmt % 5) == 0) {
12395 MulAmt2 = MulAmt / 5;
12396 } else if ((MulAmt % 3) == 0) {
12398 MulAmt2 = MulAmt / 3;
12401 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
12402 DebugLoc DL = N->getDebugLoc();
12404 if (isPowerOf2_64(MulAmt2) &&
12405 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
12406 // If second multiplifer is pow2, issue it first. We want the multiply by
12407 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
12409 std::swap(MulAmt1, MulAmt2);
12412 if (isPowerOf2_64(MulAmt1))
12413 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
12414 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
12416 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
12417 DAG.getConstant(MulAmt1, VT));
12419 if (isPowerOf2_64(MulAmt2))
12420 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
12421 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
12423 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
12424 DAG.getConstant(MulAmt2, VT));
12426 // Do not add new nodes to DAG combiner worklist.
12427 DCI.CombineTo(N, NewMul, false);
12432 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
12433 SDValue N0 = N->getOperand(0);
12434 SDValue N1 = N->getOperand(1);
12435 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
12436 EVT VT = N0.getValueType();
12438 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
12439 // since the result of setcc_c is all zero's or all ones.
12440 if (N1C && N0.getOpcode() == ISD::AND &&
12441 N0.getOperand(1).getOpcode() == ISD::Constant) {
12442 SDValue N00 = N0.getOperand(0);
12443 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
12444 ((N00.getOpcode() == ISD::ANY_EXTEND ||
12445 N00.getOpcode() == ISD::ZERO_EXTEND) &&
12446 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
12447 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
12448 APInt ShAmt = N1C->getAPIntValue();
12449 Mask = Mask.shl(ShAmt);
12451 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
12452 N00, DAG.getConstant(Mask, VT));
12459 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
12461 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
12462 const X86Subtarget *Subtarget) {
12463 EVT VT = N->getValueType(0);
12464 if (!VT.isVector() && VT.isInteger() &&
12465 N->getOpcode() == ISD::SHL)
12466 return PerformSHLCombine(N, DAG);
12468 // On X86 with SSE2 support, we can transform this to a vector shift if
12469 // all elements are shifted by the same amount. We can't do this in legalize
12470 // because the a constant vector is typically transformed to a constant pool
12471 // so we have no knowledge of the shift amount.
12472 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
12475 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
12478 SDValue ShAmtOp = N->getOperand(1);
12479 EVT EltVT = VT.getVectorElementType();
12480 DebugLoc DL = N->getDebugLoc();
12481 SDValue BaseShAmt = SDValue();
12482 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
12483 unsigned NumElts = VT.getVectorNumElements();
12485 for (; i != NumElts; ++i) {
12486 SDValue Arg = ShAmtOp.getOperand(i);
12487 if (Arg.getOpcode() == ISD::UNDEF) continue;
12491 for (; i != NumElts; ++i) {
12492 SDValue Arg = ShAmtOp.getOperand(i);
12493 if (Arg.getOpcode() == ISD::UNDEF) continue;
12494 if (Arg != BaseShAmt) {
12498 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
12499 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
12500 SDValue InVec = ShAmtOp.getOperand(0);
12501 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12502 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12504 for (; i != NumElts; ++i) {
12505 SDValue Arg = InVec.getOperand(i);
12506 if (Arg.getOpcode() == ISD::UNDEF) continue;
12510 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12511 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12512 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
12513 if (C->getZExtValue() == SplatIdx)
12514 BaseShAmt = InVec.getOperand(1);
12517 if (BaseShAmt.getNode() == 0)
12518 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
12519 DAG.getIntPtrConstant(0));
12523 // The shift amount is an i32.
12524 if (EltVT.bitsGT(MVT::i32))
12525 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
12526 else if (EltVT.bitsLT(MVT::i32))
12527 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
12529 // The shift amount is identical so we can do a vector shift.
12530 SDValue ValOp = N->getOperand(0);
12531 switch (N->getOpcode()) {
12533 llvm_unreachable("Unknown shift opcode!");
12536 if (VT == MVT::v2i64)
12537 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12538 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
12540 if (VT == MVT::v4i32)
12541 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12542 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
12544 if (VT == MVT::v8i16)
12545 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12546 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
12550 if (VT == MVT::v4i32)
12551 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12552 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
12554 if (VT == MVT::v8i16)
12555 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12556 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
12560 if (VT == MVT::v2i64)
12561 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12562 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
12564 if (VT == MVT::v4i32)
12565 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12566 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
12568 if (VT == MVT::v8i16)
12569 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12570 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
12578 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
12579 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
12580 // and friends. Likewise for OR -> CMPNEQSS.
12581 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
12582 TargetLowering::DAGCombinerInfo &DCI,
12583 const X86Subtarget *Subtarget) {
12586 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
12587 // we're requiring SSE2 for both.
12588 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
12589 SDValue N0 = N->getOperand(0);
12590 SDValue N1 = N->getOperand(1);
12591 SDValue CMP0 = N0->getOperand(1);
12592 SDValue CMP1 = N1->getOperand(1);
12593 DebugLoc DL = N->getDebugLoc();
12595 // The SETCCs should both refer to the same CMP.
12596 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
12599 SDValue CMP00 = CMP0->getOperand(0);
12600 SDValue CMP01 = CMP0->getOperand(1);
12601 EVT VT = CMP00.getValueType();
12603 if (VT == MVT::f32 || VT == MVT::f64) {
12604 bool ExpectingFlags = false;
12605 // Check for any users that want flags:
12606 for (SDNode::use_iterator UI = N->use_begin(),
12608 !ExpectingFlags && UI != UE; ++UI)
12609 switch (UI->getOpcode()) {
12614 ExpectingFlags = true;
12616 case ISD::CopyToReg:
12617 case ISD::SIGN_EXTEND:
12618 case ISD::ZERO_EXTEND:
12619 case ISD::ANY_EXTEND:
12623 if (!ExpectingFlags) {
12624 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
12625 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
12627 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
12628 X86::CondCode tmp = cc0;
12633 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
12634 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
12635 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
12636 X86ISD::NodeType NTOperator = is64BitFP ?
12637 X86ISD::FSETCCsd : X86ISD::FSETCCss;
12638 // FIXME: need symbolic constants for these magic numbers.
12639 // See X86ATTInstPrinter.cpp:printSSECC().
12640 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
12641 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
12642 DAG.getConstant(x86cc, MVT::i8));
12643 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
12645 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
12646 DAG.getConstant(1, MVT::i32));
12647 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
12648 return OneBitOfTruth;
12656 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
12657 /// so it can be folded inside ANDNP.
12658 static bool CanFoldXORWithAllOnes(const SDNode *N) {
12659 EVT VT = N->getValueType(0);
12661 // Match direct AllOnes for 128 and 256-bit vectors
12662 if (ISD::isBuildVectorAllOnes(N))
12665 // Look through a bit convert.
12666 if (N->getOpcode() == ISD::BITCAST)
12667 N = N->getOperand(0).getNode();
12669 // Sometimes the operand may come from a insert_subvector building a 256-bit
12671 if (VT.getSizeInBits() == 256 &&
12672 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
12673 SDValue V1 = N->getOperand(0);
12674 SDValue V2 = N->getOperand(1);
12676 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
12677 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
12678 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
12679 ISD::isBuildVectorAllOnes(V2.getNode()))
12686 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
12687 TargetLowering::DAGCombinerInfo &DCI,
12688 const X86Subtarget *Subtarget) {
12689 if (DCI.isBeforeLegalizeOps())
12692 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
12696 // Want to form ANDNP nodes:
12697 // 1) In the hopes of then easily combining them with OR and AND nodes
12698 // to form PBLEND/PSIGN.
12699 // 2) To match ANDN packed intrinsics
12700 EVT VT = N->getValueType(0);
12701 if (VT != MVT::v2i64 && VT != MVT::v4i64)
12704 SDValue N0 = N->getOperand(0);
12705 SDValue N1 = N->getOperand(1);
12706 DebugLoc DL = N->getDebugLoc();
12708 // Check LHS for vnot
12709 if (N0.getOpcode() == ISD::XOR &&
12710 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
12711 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
12712 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
12714 // Check RHS for vnot
12715 if (N1.getOpcode() == ISD::XOR &&
12716 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
12717 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
12718 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
12723 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
12724 TargetLowering::DAGCombinerInfo &DCI,
12725 const X86Subtarget *Subtarget) {
12726 if (DCI.isBeforeLegalizeOps())
12729 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
12733 EVT VT = N->getValueType(0);
12734 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
12737 SDValue N0 = N->getOperand(0);
12738 SDValue N1 = N->getOperand(1);
12740 // look for psign/blend
12741 if (Subtarget->hasSSSE3()) {
12742 if (VT == MVT::v2i64) {
12743 // Canonicalize pandn to RHS
12744 if (N0.getOpcode() == X86ISD::ANDNP)
12746 // or (and (m, x), (pandn m, y))
12747 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
12748 SDValue Mask = N1.getOperand(0);
12749 SDValue X = N1.getOperand(1);
12751 if (N0.getOperand(0) == Mask)
12752 Y = N0.getOperand(1);
12753 if (N0.getOperand(1) == Mask)
12754 Y = N0.getOperand(0);
12756 // Check to see if the mask appeared in both the AND and ANDNP and
12760 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
12761 if (Mask.getOpcode() != ISD::BITCAST ||
12762 X.getOpcode() != ISD::BITCAST ||
12763 Y.getOpcode() != ISD::BITCAST)
12766 // Look through mask bitcast.
12767 Mask = Mask.getOperand(0);
12768 EVT MaskVT = Mask.getValueType();
12770 // Validate that the Mask operand is a vector sra node. The sra node
12771 // will be an intrinsic.
12772 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
12775 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
12776 // there is no psrai.b
12777 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
12778 case Intrinsic::x86_sse2_psrai_w:
12779 case Intrinsic::x86_sse2_psrai_d:
12781 default: return SDValue();
12784 // Check that the SRA is all signbits.
12785 SDValue SraC = Mask.getOperand(2);
12786 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
12787 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
12788 if ((SraAmt + 1) != EltBits)
12791 DebugLoc DL = N->getDebugLoc();
12793 // Now we know we at least have a plendvb with the mask val. See if
12794 // we can form a psignb/w/d.
12795 // psign = x.type == y.type == mask.type && y = sub(0, x);
12796 X = X.getOperand(0);
12797 Y = Y.getOperand(0);
12798 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
12799 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
12800 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
12803 case 8: Opc = X86ISD::PSIGNB; break;
12804 case 16: Opc = X86ISD::PSIGNW; break;
12805 case 32: Opc = X86ISD::PSIGND; break;
12809 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
12810 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
12813 // PBLENDVB only available on SSE 4.1
12814 if (!Subtarget->hasSSE41())
12817 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
12818 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
12819 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
12820 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
12821 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
12826 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
12827 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
12829 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
12831 if (!N0.hasOneUse() || !N1.hasOneUse())
12834 SDValue ShAmt0 = N0.getOperand(1);
12835 if (ShAmt0.getValueType() != MVT::i8)
12837 SDValue ShAmt1 = N1.getOperand(1);
12838 if (ShAmt1.getValueType() != MVT::i8)
12840 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
12841 ShAmt0 = ShAmt0.getOperand(0);
12842 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
12843 ShAmt1 = ShAmt1.getOperand(0);
12845 DebugLoc DL = N->getDebugLoc();
12846 unsigned Opc = X86ISD::SHLD;
12847 SDValue Op0 = N0.getOperand(0);
12848 SDValue Op1 = N1.getOperand(0);
12849 if (ShAmt0.getOpcode() == ISD::SUB) {
12850 Opc = X86ISD::SHRD;
12851 std::swap(Op0, Op1);
12852 std::swap(ShAmt0, ShAmt1);
12855 unsigned Bits = VT.getSizeInBits();
12856 if (ShAmt1.getOpcode() == ISD::SUB) {
12857 SDValue Sum = ShAmt1.getOperand(0);
12858 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
12859 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
12860 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
12861 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
12862 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
12863 return DAG.getNode(Opc, DL, VT,
12865 DAG.getNode(ISD::TRUNCATE, DL,
12868 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
12869 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
12871 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
12872 return DAG.getNode(Opc, DL, VT,
12873 N0.getOperand(0), N1.getOperand(0),
12874 DAG.getNode(ISD::TRUNCATE, DL,
12881 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
12882 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
12883 const X86Subtarget *Subtarget) {
12884 StoreSDNode *St = cast<StoreSDNode>(N);
12885 EVT VT = St->getValue().getValueType();
12886 EVT StVT = St->getMemoryVT();
12887 DebugLoc dl = St->getDebugLoc();
12888 SDValue StoredVal = St->getOperand(1);
12889 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12891 // If we are saving a concatination of two XMM registers, perform two stores.
12892 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
12893 // 128-bit ones. If in the future the cost becomes only one memory access the
12894 // first version would be better.
12895 if (VT.getSizeInBits() == 256 &&
12896 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
12897 StoredVal.getNumOperands() == 2) {
12899 SDValue Value0 = StoredVal.getOperand(0);
12900 SDValue Value1 = StoredVal.getOperand(1);
12902 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
12903 SDValue Ptr0 = St->getBasePtr();
12904 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
12906 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
12907 St->getPointerInfo(), St->isVolatile(),
12908 St->isNonTemporal(), St->getAlignment());
12909 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
12910 St->getPointerInfo(), St->isVolatile(),
12911 St->isNonTemporal(), St->getAlignment());
12912 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
12915 // Optimize trunc store (of multiple scalars) to shuffle and store.
12916 // First, pack all of the elements in one place. Next, store to memory
12917 // in fewer chunks.
12918 if (St->isTruncatingStore() && VT.isVector()) {
12919 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12920 unsigned NumElems = VT.getVectorNumElements();
12921 assert(StVT != VT && "Cannot truncate to the same type");
12922 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
12923 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
12925 // From, To sizes and ElemCount must be pow of two
12926 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
12927 // We are going to use the original vector elt for storing.
12928 // accumulated smaller vector elements must be a multiple of bigger size.
12929 if (0 != (NumElems * ToSz) % FromSz) return SDValue();
12930 unsigned SizeRatio = FromSz / ToSz;
12932 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
12934 // Create a type on which we perform the shuffle
12935 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
12936 StVT.getScalarType(), NumElems*SizeRatio);
12938 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
12940 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
12941 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
12942 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
12944 // Can't shuffle using an illegal type
12945 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
12947 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
12948 DAG.getUNDEF(WideVec.getValueType()),
12949 ShuffleVec.data());
12950 // At this point all of the data is stored at the bottom of the
12951 // register. We now need to save it to mem.
12953 // Find the largest store unit
12954 MVT StoreType = MVT::i8;
12955 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
12956 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
12957 MVT Tp = (MVT::SimpleValueType)tp;
12958 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
12962 // Bitcast the original vector into a vector of store-size units
12963 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
12964 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
12965 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
12966 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
12967 SmallVector<SDValue, 8> Chains;
12968 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
12969 TLI.getPointerTy());
12970 SDValue Ptr = St->getBasePtr();
12972 // Perform one or more big stores into memory.
12973 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
12974 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12975 StoreType, ShuffWide,
12976 DAG.getIntPtrConstant(i));
12977 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
12978 St->getPointerInfo(), St->isVolatile(),
12979 St->isNonTemporal(), St->getAlignment());
12980 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
12981 Chains.push_back(Ch);
12984 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
12989 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
12990 // the FP state in cases where an emms may be missing.
12991 // A preferable solution to the general problem is to figure out the right
12992 // places to insert EMMS. This qualifies as a quick hack.
12994 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
12995 if (VT.getSizeInBits() != 64)
12998 const Function *F = DAG.getMachineFunction().getFunction();
12999 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
13000 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
13001 && Subtarget->hasSSE2();
13002 if ((VT.isVector() ||
13003 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
13004 isa<LoadSDNode>(St->getValue()) &&
13005 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
13006 St->getChain().hasOneUse() && !St->isVolatile()) {
13007 SDNode* LdVal = St->getValue().getNode();
13008 LoadSDNode *Ld = 0;
13009 int TokenFactorIndex = -1;
13010 SmallVector<SDValue, 8> Ops;
13011 SDNode* ChainVal = St->getChain().getNode();
13012 // Must be a store of a load. We currently handle two cases: the load
13013 // is a direct child, and it's under an intervening TokenFactor. It is
13014 // possible to dig deeper under nested TokenFactors.
13015 if (ChainVal == LdVal)
13016 Ld = cast<LoadSDNode>(St->getChain());
13017 else if (St->getValue().hasOneUse() &&
13018 ChainVal->getOpcode() == ISD::TokenFactor) {
13019 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
13020 if (ChainVal->getOperand(i).getNode() == LdVal) {
13021 TokenFactorIndex = i;
13022 Ld = cast<LoadSDNode>(St->getValue());
13024 Ops.push_back(ChainVal->getOperand(i));
13028 if (!Ld || !ISD::isNormalLoad(Ld))
13031 // If this is not the MMX case, i.e. we are just turning i64 load/store
13032 // into f64 load/store, avoid the transformation if there are multiple
13033 // uses of the loaded value.
13034 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
13037 DebugLoc LdDL = Ld->getDebugLoc();
13038 DebugLoc StDL = N->getDebugLoc();
13039 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
13040 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
13042 if (Subtarget->is64Bit() || F64IsLegal) {
13043 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
13044 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
13045 Ld->getPointerInfo(), Ld->isVolatile(),
13046 Ld->isNonTemporal(), Ld->getAlignment());
13047 SDValue NewChain = NewLd.getValue(1);
13048 if (TokenFactorIndex != -1) {
13049 Ops.push_back(NewChain);
13050 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13053 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
13054 St->getPointerInfo(),
13055 St->isVolatile(), St->isNonTemporal(),
13056 St->getAlignment());
13059 // Otherwise, lower to two pairs of 32-bit loads / stores.
13060 SDValue LoAddr = Ld->getBasePtr();
13061 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
13062 DAG.getConstant(4, MVT::i32));
13064 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
13065 Ld->getPointerInfo(),
13066 Ld->isVolatile(), Ld->isNonTemporal(),
13067 Ld->getAlignment());
13068 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
13069 Ld->getPointerInfo().getWithOffset(4),
13070 Ld->isVolatile(), Ld->isNonTemporal(),
13071 MinAlign(Ld->getAlignment(), 4));
13073 SDValue NewChain = LoLd.getValue(1);
13074 if (TokenFactorIndex != -1) {
13075 Ops.push_back(LoLd);
13076 Ops.push_back(HiLd);
13077 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13081 LoAddr = St->getBasePtr();
13082 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
13083 DAG.getConstant(4, MVT::i32));
13085 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
13086 St->getPointerInfo(),
13087 St->isVolatile(), St->isNonTemporal(),
13088 St->getAlignment());
13089 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
13090 St->getPointerInfo().getWithOffset(4),
13092 St->isNonTemporal(),
13093 MinAlign(St->getAlignment(), 4));
13094 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
13099 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
13100 /// X86ISD::FXOR nodes.
13101 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
13102 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
13103 // F[X]OR(0.0, x) -> x
13104 // F[X]OR(x, 0.0) -> x
13105 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13106 if (C->getValueAPF().isPosZero())
13107 return N->getOperand(1);
13108 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13109 if (C->getValueAPF().isPosZero())
13110 return N->getOperand(0);
13114 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
13115 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
13116 // FAND(0.0, x) -> 0.0
13117 // FAND(x, 0.0) -> 0.0
13118 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13119 if (C->getValueAPF().isPosZero())
13120 return N->getOperand(0);
13121 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13122 if (C->getValueAPF().isPosZero())
13123 return N->getOperand(1);
13127 static SDValue PerformBTCombine(SDNode *N,
13129 TargetLowering::DAGCombinerInfo &DCI) {
13130 // BT ignores high bits in the bit index operand.
13131 SDValue Op1 = N->getOperand(1);
13132 if (Op1.hasOneUse()) {
13133 unsigned BitWidth = Op1.getValueSizeInBits();
13134 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
13135 APInt KnownZero, KnownOne;
13136 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
13137 !DCI.isBeforeLegalizeOps());
13138 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13139 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
13140 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
13141 DCI.CommitTargetLoweringOpt(TLO);
13146 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
13147 SDValue Op = N->getOperand(0);
13148 if (Op.getOpcode() == ISD::BITCAST)
13149 Op = Op.getOperand(0);
13150 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
13151 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
13152 VT.getVectorElementType().getSizeInBits() ==
13153 OpVT.getVectorElementType().getSizeInBits()) {
13154 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
13159 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
13160 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
13161 // (and (i32 x86isd::setcc_carry), 1)
13162 // This eliminates the zext. This transformation is necessary because
13163 // ISD::SETCC is always legalized to i8.
13164 DebugLoc dl = N->getDebugLoc();
13165 SDValue N0 = N->getOperand(0);
13166 EVT VT = N->getValueType(0);
13167 if (N0.getOpcode() == ISD::AND &&
13169 N0.getOperand(0).hasOneUse()) {
13170 SDValue N00 = N0.getOperand(0);
13171 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
13173 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
13174 if (!C || C->getZExtValue() != 1)
13176 return DAG.getNode(ISD::AND, dl, VT,
13177 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
13178 N00.getOperand(0), N00.getOperand(1)),
13179 DAG.getConstant(1, VT));
13185 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
13186 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
13187 unsigned X86CC = N->getConstantOperandVal(0);
13188 SDValue EFLAG = N->getOperand(1);
13189 DebugLoc DL = N->getDebugLoc();
13191 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
13192 // a zext and produces an all-ones bit which is more useful than 0/1 in some
13194 if (X86CC == X86::COND_B)
13195 return DAG.getNode(ISD::AND, DL, MVT::i8,
13196 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
13197 DAG.getConstant(X86CC, MVT::i8), EFLAG),
13198 DAG.getConstant(1, MVT::i8));
13203 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
13204 const X86TargetLowering *XTLI) {
13205 SDValue Op0 = N->getOperand(0);
13206 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
13207 // a 32-bit target where SSE doesn't support i64->FP operations.
13208 if (Op0.getOpcode() == ISD::LOAD) {
13209 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
13210 EVT VT = Ld->getValueType(0);
13211 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
13212 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
13213 !XTLI->getSubtarget()->is64Bit() &&
13214 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13215 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
13216 Ld->getChain(), Op0, DAG);
13217 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
13224 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
13225 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
13226 X86TargetLowering::DAGCombinerInfo &DCI) {
13227 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
13228 // the result is either zero or one (depending on the input carry bit).
13229 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
13230 if (X86::isZeroNode(N->getOperand(0)) &&
13231 X86::isZeroNode(N->getOperand(1)) &&
13232 // We don't have a good way to replace an EFLAGS use, so only do this when
13234 SDValue(N, 1).use_empty()) {
13235 DebugLoc DL = N->getDebugLoc();
13236 EVT VT = N->getValueType(0);
13237 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
13238 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
13239 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
13240 DAG.getConstant(X86::COND_B,MVT::i8),
13242 DAG.getConstant(1, VT));
13243 return DCI.CombineTo(N, Res1, CarryOut);
13249 // fold (add Y, (sete X, 0)) -> adc 0, Y
13250 // (add Y, (setne X, 0)) -> sbb -1, Y
13251 // (sub (sete X, 0), Y) -> sbb 0, Y
13252 // (sub (setne X, 0), Y) -> adc -1, Y
13253 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
13254 DebugLoc DL = N->getDebugLoc();
13256 // Look through ZExts.
13257 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
13258 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
13261 SDValue SetCC = Ext.getOperand(0);
13262 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
13265 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
13266 if (CC != X86::COND_E && CC != X86::COND_NE)
13269 SDValue Cmp = SetCC.getOperand(1);
13270 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
13271 !X86::isZeroNode(Cmp.getOperand(1)) ||
13272 !Cmp.getOperand(0).getValueType().isInteger())
13275 SDValue CmpOp0 = Cmp.getOperand(0);
13276 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
13277 DAG.getConstant(1, CmpOp0.getValueType()));
13279 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
13280 if (CC == X86::COND_NE)
13281 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
13282 DL, OtherVal.getValueType(), OtherVal,
13283 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
13284 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
13285 DL, OtherVal.getValueType(), OtherVal,
13286 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
13289 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
13290 SDValue Op0 = N->getOperand(0);
13291 SDValue Op1 = N->getOperand(1);
13293 // X86 can't encode an immediate LHS of a sub. See if we can push the
13294 // negation into a preceding instruction.
13295 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
13296 // If the RHS of the sub is a XOR with one use and a constant, invert the
13297 // immediate. Then add one to the LHS of the sub so we can turn
13298 // X-Y -> X+~Y+1, saving one register.
13299 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
13300 isa<ConstantSDNode>(Op1.getOperand(1))) {
13301 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
13302 EVT VT = Op0.getValueType();
13303 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
13305 DAG.getConstant(~XorC, VT));
13306 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
13307 DAG.getConstant(C->getAPIntValue()+1, VT));
13311 return OptimizeConditionalInDecrement(N, DAG);
13314 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
13315 DAGCombinerInfo &DCI) const {
13316 SelectionDAG &DAG = DCI.DAG;
13317 switch (N->getOpcode()) {
13319 case ISD::EXTRACT_VECTOR_ELT:
13320 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
13321 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
13322 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
13323 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
13324 case ISD::SUB: return PerformSubCombine(N, DAG);
13325 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
13326 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
13329 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
13330 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
13331 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
13332 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
13333 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
13335 case X86ISD::FOR: return PerformFORCombine(N, DAG);
13336 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
13337 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
13338 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
13339 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
13340 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
13341 case X86ISD::SHUFPS: // Handle all target specific shuffles
13342 case X86ISD::SHUFPD:
13343 case X86ISD::PALIGN:
13344 case X86ISD::PUNPCKHBW:
13345 case X86ISD::PUNPCKHWD:
13346 case X86ISD::PUNPCKHDQ:
13347 case X86ISD::PUNPCKHQDQ:
13348 case X86ISD::UNPCKHPS:
13349 case X86ISD::UNPCKHPD:
13350 case X86ISD::VUNPCKHPSY:
13351 case X86ISD::VUNPCKHPDY:
13352 case X86ISD::PUNPCKLBW:
13353 case X86ISD::PUNPCKLWD:
13354 case X86ISD::PUNPCKLDQ:
13355 case X86ISD::PUNPCKLQDQ:
13356 case X86ISD::UNPCKLPS:
13357 case X86ISD::UNPCKLPD:
13358 case X86ISD::VUNPCKLPSY:
13359 case X86ISD::VUNPCKLPDY:
13360 case X86ISD::MOVHLPS:
13361 case X86ISD::MOVLHPS:
13362 case X86ISD::PSHUFD:
13363 case X86ISD::PSHUFHW:
13364 case X86ISD::PSHUFLW:
13365 case X86ISD::MOVSS:
13366 case X86ISD::MOVSD:
13367 case X86ISD::VPERMILPS:
13368 case X86ISD::VPERMILPSY:
13369 case X86ISD::VPERMILPD:
13370 case X86ISD::VPERMILPDY:
13371 case X86ISD::VPERM2F128:
13372 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
13378 /// isTypeDesirableForOp - Return true if the target has native support for
13379 /// the specified value type and it is 'desirable' to use the type for the
13380 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
13381 /// instruction encodings are longer and some i16 instructions are slow.
13382 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
13383 if (!isTypeLegal(VT))
13385 if (VT != MVT::i16)
13392 case ISD::SIGN_EXTEND:
13393 case ISD::ZERO_EXTEND:
13394 case ISD::ANY_EXTEND:
13407 /// IsDesirableToPromoteOp - This method query the target whether it is
13408 /// beneficial for dag combiner to promote the specified node. If true, it
13409 /// should return the desired promotion type by reference.
13410 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
13411 EVT VT = Op.getValueType();
13412 if (VT != MVT::i16)
13415 bool Promote = false;
13416 bool Commute = false;
13417 switch (Op.getOpcode()) {
13420 LoadSDNode *LD = cast<LoadSDNode>(Op);
13421 // If the non-extending load has a single use and it's not live out, then it
13422 // might be folded.
13423 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
13424 Op.hasOneUse()*/) {
13425 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13426 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
13427 // The only case where we'd want to promote LOAD (rather then it being
13428 // promoted as an operand is when it's only use is liveout.
13429 if (UI->getOpcode() != ISD::CopyToReg)
13436 case ISD::SIGN_EXTEND:
13437 case ISD::ZERO_EXTEND:
13438 case ISD::ANY_EXTEND:
13443 SDValue N0 = Op.getOperand(0);
13444 // Look out for (store (shl (load), x)).
13445 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
13458 SDValue N0 = Op.getOperand(0);
13459 SDValue N1 = Op.getOperand(1);
13460 if (!Commute && MayFoldLoad(N1))
13462 // Avoid disabling potential load folding opportunities.
13463 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
13465 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
13475 //===----------------------------------------------------------------------===//
13476 // X86 Inline Assembly Support
13477 //===----------------------------------------------------------------------===//
13479 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
13480 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
13482 std::string AsmStr = IA->getAsmString();
13484 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
13485 SmallVector<StringRef, 4> AsmPieces;
13486 SplitString(AsmStr, AsmPieces, ";\n");
13488 switch (AsmPieces.size()) {
13489 default: return false;
13491 AsmStr = AsmPieces[0];
13493 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
13495 // FIXME: this should verify that we are targeting a 486 or better. If not,
13496 // we will turn this bswap into something that will be lowered to logical ops
13497 // instead of emitting the bswap asm. For now, we don't support 486 or lower
13498 // so don't worry about this.
13500 if (AsmPieces.size() == 2 &&
13501 (AsmPieces[0] == "bswap" ||
13502 AsmPieces[0] == "bswapq" ||
13503 AsmPieces[0] == "bswapl") &&
13504 (AsmPieces[1] == "$0" ||
13505 AsmPieces[1] == "${0:q}")) {
13506 // No need to check constraints, nothing other than the equivalent of
13507 // "=r,0" would be valid here.
13508 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13509 if (!Ty || Ty->getBitWidth() % 16 != 0)
13511 return IntrinsicLowering::LowerToByteSwap(CI);
13513 // rorw $$8, ${0:w} --> llvm.bswap.i16
13514 if (CI->getType()->isIntegerTy(16) &&
13515 AsmPieces.size() == 3 &&
13516 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
13517 AsmPieces[1] == "$$8," &&
13518 AsmPieces[2] == "${0:w}" &&
13519 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13521 const std::string &ConstraintsStr = IA->getConstraintString();
13522 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13523 std::sort(AsmPieces.begin(), AsmPieces.end());
13524 if (AsmPieces.size() == 4 &&
13525 AsmPieces[0] == "~{cc}" &&
13526 AsmPieces[1] == "~{dirflag}" &&
13527 AsmPieces[2] == "~{flags}" &&
13528 AsmPieces[3] == "~{fpsr}") {
13529 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13530 if (!Ty || Ty->getBitWidth() % 16 != 0)
13532 return IntrinsicLowering::LowerToByteSwap(CI);
13537 if (CI->getType()->isIntegerTy(32) &&
13538 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13539 SmallVector<StringRef, 4> Words;
13540 SplitString(AsmPieces[0], Words, " \t,");
13541 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13542 Words[2] == "${0:w}") {
13544 SplitString(AsmPieces[1], Words, " \t,");
13545 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
13546 Words[2] == "$0") {
13548 SplitString(AsmPieces[2], Words, " \t,");
13549 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13550 Words[2] == "${0:w}") {
13552 const std::string &ConstraintsStr = IA->getConstraintString();
13553 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13554 std::sort(AsmPieces.begin(), AsmPieces.end());
13555 if (AsmPieces.size() == 4 &&
13556 AsmPieces[0] == "~{cc}" &&
13557 AsmPieces[1] == "~{dirflag}" &&
13558 AsmPieces[2] == "~{flags}" &&
13559 AsmPieces[3] == "~{fpsr}") {
13560 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13561 if (!Ty || Ty->getBitWidth() % 16 != 0)
13563 return IntrinsicLowering::LowerToByteSwap(CI);
13570 if (CI->getType()->isIntegerTy(64)) {
13571 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
13572 if (Constraints.size() >= 2 &&
13573 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
13574 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
13575 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
13576 SmallVector<StringRef, 4> Words;
13577 SplitString(AsmPieces[0], Words, " \t");
13578 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
13580 SplitString(AsmPieces[1], Words, " \t");
13581 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
13583 SplitString(AsmPieces[2], Words, " \t,");
13584 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
13585 Words[2] == "%edx") {
13586 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13587 if (!Ty || Ty->getBitWidth() % 16 != 0)
13589 return IntrinsicLowering::LowerToByteSwap(CI);
13602 /// getConstraintType - Given a constraint letter, return the type of
13603 /// constraint it is for this target.
13604 X86TargetLowering::ConstraintType
13605 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
13606 if (Constraint.size() == 1) {
13607 switch (Constraint[0]) {
13618 return C_RegisterClass;
13642 return TargetLowering::getConstraintType(Constraint);
13645 /// Examine constraint type and operand type and determine a weight value.
13646 /// This object must already have been set up with the operand type
13647 /// and the current alternative constraint selected.
13648 TargetLowering::ConstraintWeight
13649 X86TargetLowering::getSingleConstraintMatchWeight(
13650 AsmOperandInfo &info, const char *constraint) const {
13651 ConstraintWeight weight = CW_Invalid;
13652 Value *CallOperandVal = info.CallOperandVal;
13653 // If we don't have a value, we can't do a match,
13654 // but allow it at the lowest weight.
13655 if (CallOperandVal == NULL)
13657 Type *type = CallOperandVal->getType();
13658 // Look at the constraint type.
13659 switch (*constraint) {
13661 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
13672 if (CallOperandVal->getType()->isIntegerTy())
13673 weight = CW_SpecificReg;
13678 if (type->isFloatingPointTy())
13679 weight = CW_SpecificReg;
13682 if (type->isX86_MMXTy() && Subtarget->hasMMX())
13683 weight = CW_SpecificReg;
13687 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
13688 weight = CW_Register;
13691 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
13692 if (C->getZExtValue() <= 31)
13693 weight = CW_Constant;
13697 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13698 if (C->getZExtValue() <= 63)
13699 weight = CW_Constant;
13703 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13704 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
13705 weight = CW_Constant;
13709 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13710 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
13711 weight = CW_Constant;
13715 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13716 if (C->getZExtValue() <= 3)
13717 weight = CW_Constant;
13721 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13722 if (C->getZExtValue() <= 0xff)
13723 weight = CW_Constant;
13728 if (dyn_cast<ConstantFP>(CallOperandVal)) {
13729 weight = CW_Constant;
13733 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13734 if ((C->getSExtValue() >= -0x80000000LL) &&
13735 (C->getSExtValue() <= 0x7fffffffLL))
13736 weight = CW_Constant;
13740 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13741 if (C->getZExtValue() <= 0xffffffff)
13742 weight = CW_Constant;
13749 /// LowerXConstraint - try to replace an X constraint, which matches anything,
13750 /// with another that has more specific requirements based on the type of the
13751 /// corresponding operand.
13752 const char *X86TargetLowering::
13753 LowerXConstraint(EVT ConstraintVT) const {
13754 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
13755 // 'f' like normal targets.
13756 if (ConstraintVT.isFloatingPoint()) {
13757 if (Subtarget->hasXMMInt())
13759 if (Subtarget->hasXMM())
13763 return TargetLowering::LowerXConstraint(ConstraintVT);
13766 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
13767 /// vector. If it is invalid, don't add anything to Ops.
13768 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
13769 std::string &Constraint,
13770 std::vector<SDValue>&Ops,
13771 SelectionDAG &DAG) const {
13772 SDValue Result(0, 0);
13774 // Only support length 1 constraints for now.
13775 if (Constraint.length() > 1) return;
13777 char ConstraintLetter = Constraint[0];
13778 switch (ConstraintLetter) {
13781 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13782 if (C->getZExtValue() <= 31) {
13783 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13789 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13790 if (C->getZExtValue() <= 63) {
13791 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13797 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13798 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
13799 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13805 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13806 if (C->getZExtValue() <= 255) {
13807 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13813 // 32-bit signed value
13814 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13815 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
13816 C->getSExtValue())) {
13817 // Widen to 64 bits here to get it sign extended.
13818 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
13821 // FIXME gcc accepts some relocatable values here too, but only in certain
13822 // memory models; it's complicated.
13827 // 32-bit unsigned value
13828 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13829 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
13830 C->getZExtValue())) {
13831 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13835 // FIXME gcc accepts some relocatable values here too, but only in certain
13836 // memory models; it's complicated.
13840 // Literal immediates are always ok.
13841 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
13842 // Widen to 64 bits here to get it sign extended.
13843 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
13847 // In any sort of PIC mode addresses need to be computed at runtime by
13848 // adding in a register or some sort of table lookup. These can't
13849 // be used as immediates.
13850 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
13853 // If we are in non-pic codegen mode, we allow the address of a global (with
13854 // an optional displacement) to be used with 'i'.
13855 GlobalAddressSDNode *GA = 0;
13856 int64_t Offset = 0;
13858 // Match either (GA), (GA+C), (GA+C1+C2), etc.
13860 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
13861 Offset += GA->getOffset();
13863 } else if (Op.getOpcode() == ISD::ADD) {
13864 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
13865 Offset += C->getZExtValue();
13866 Op = Op.getOperand(0);
13869 } else if (Op.getOpcode() == ISD::SUB) {
13870 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
13871 Offset += -C->getZExtValue();
13872 Op = Op.getOperand(0);
13877 // Otherwise, this isn't something we can handle, reject it.
13881 const GlobalValue *GV = GA->getGlobal();
13882 // If we require an extra load to get this address, as in PIC mode, we
13883 // can't accept it.
13884 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
13885 getTargetMachine())))
13888 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
13889 GA->getValueType(0), Offset);
13894 if (Result.getNode()) {
13895 Ops.push_back(Result);
13898 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
13901 std::pair<unsigned, const TargetRegisterClass*>
13902 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
13904 // First, see if this is a constraint that directly corresponds to an LLVM
13906 if (Constraint.size() == 1) {
13907 // GCC Constraint Letters
13908 switch (Constraint[0]) {
13910 // TODO: Slight differences here in allocation order and leaving
13911 // RIP in the class. Do they matter any more here than they do
13912 // in the normal allocation?
13913 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
13914 if (Subtarget->is64Bit()) {
13915 if (VT == MVT::i32 || VT == MVT::f32)
13916 return std::make_pair(0U, X86::GR32RegisterClass);
13917 else if (VT == MVT::i16)
13918 return std::make_pair(0U, X86::GR16RegisterClass);
13919 else if (VT == MVT::i8 || VT == MVT::i1)
13920 return std::make_pair(0U, X86::GR8RegisterClass);
13921 else if (VT == MVT::i64 || VT == MVT::f64)
13922 return std::make_pair(0U, X86::GR64RegisterClass);
13925 // 32-bit fallthrough
13926 case 'Q': // Q_REGS
13927 if (VT == MVT::i32 || VT == MVT::f32)
13928 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
13929 else if (VT == MVT::i16)
13930 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
13931 else if (VT == MVT::i8 || VT == MVT::i1)
13932 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
13933 else if (VT == MVT::i64)
13934 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
13936 case 'r': // GENERAL_REGS
13937 case 'l': // INDEX_REGS
13938 if (VT == MVT::i8 || VT == MVT::i1)
13939 return std::make_pair(0U, X86::GR8RegisterClass);
13940 if (VT == MVT::i16)
13941 return std::make_pair(0U, X86::GR16RegisterClass);
13942 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
13943 return std::make_pair(0U, X86::GR32RegisterClass);
13944 return std::make_pair(0U, X86::GR64RegisterClass);
13945 case 'R': // LEGACY_REGS
13946 if (VT == MVT::i8 || VT == MVT::i1)
13947 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
13948 if (VT == MVT::i16)
13949 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
13950 if (VT == MVT::i32 || !Subtarget->is64Bit())
13951 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
13952 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
13953 case 'f': // FP Stack registers.
13954 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
13955 // value to the correct fpstack register class.
13956 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
13957 return std::make_pair(0U, X86::RFP32RegisterClass);
13958 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
13959 return std::make_pair(0U, X86::RFP64RegisterClass);
13960 return std::make_pair(0U, X86::RFP80RegisterClass);
13961 case 'y': // MMX_REGS if MMX allowed.
13962 if (!Subtarget->hasMMX()) break;
13963 return std::make_pair(0U, X86::VR64RegisterClass);
13964 case 'Y': // SSE_REGS if SSE2 allowed
13965 if (!Subtarget->hasXMMInt()) break;
13967 case 'x': // SSE_REGS if SSE1 allowed
13968 if (!Subtarget->hasXMM()) break;
13970 switch (VT.getSimpleVT().SimpleTy) {
13972 // Scalar SSE types.
13975 return std::make_pair(0U, X86::FR32RegisterClass);
13978 return std::make_pair(0U, X86::FR64RegisterClass);
13986 return std::make_pair(0U, X86::VR128RegisterClass);
13992 // Use the default implementation in TargetLowering to convert the register
13993 // constraint into a member of a register class.
13994 std::pair<unsigned, const TargetRegisterClass*> Res;
13995 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
13997 // Not found as a standard register?
13998 if (Res.second == 0) {
13999 // Map st(0) -> st(7) -> ST0
14000 if (Constraint.size() == 7 && Constraint[0] == '{' &&
14001 tolower(Constraint[1]) == 's' &&
14002 tolower(Constraint[2]) == 't' &&
14003 Constraint[3] == '(' &&
14004 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
14005 Constraint[5] == ')' &&
14006 Constraint[6] == '}') {
14008 Res.first = X86::ST0+Constraint[4]-'0';
14009 Res.second = X86::RFP80RegisterClass;
14013 // GCC allows "st(0)" to be called just plain "st".
14014 if (StringRef("{st}").equals_lower(Constraint)) {
14015 Res.first = X86::ST0;
14016 Res.second = X86::RFP80RegisterClass;
14021 if (StringRef("{flags}").equals_lower(Constraint)) {
14022 Res.first = X86::EFLAGS;
14023 Res.second = X86::CCRRegisterClass;
14027 // 'A' means EAX + EDX.
14028 if (Constraint == "A") {
14029 Res.first = X86::EAX;
14030 Res.second = X86::GR32_ADRegisterClass;
14036 // Otherwise, check to see if this is a register class of the wrong value
14037 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
14038 // turn into {ax},{dx}.
14039 if (Res.second->hasType(VT))
14040 return Res; // Correct type already, nothing to do.
14042 // All of the single-register GCC register classes map their values onto
14043 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
14044 // really want an 8-bit or 32-bit register, map to the appropriate register
14045 // class and return the appropriate register.
14046 if (Res.second == X86::GR16RegisterClass) {
14047 if (VT == MVT::i8) {
14048 unsigned DestReg = 0;
14049 switch (Res.first) {
14051 case X86::AX: DestReg = X86::AL; break;
14052 case X86::DX: DestReg = X86::DL; break;
14053 case X86::CX: DestReg = X86::CL; break;
14054 case X86::BX: DestReg = X86::BL; break;
14057 Res.first = DestReg;
14058 Res.second = X86::GR8RegisterClass;
14060 } else if (VT == MVT::i32) {
14061 unsigned DestReg = 0;
14062 switch (Res.first) {
14064 case X86::AX: DestReg = X86::EAX; break;
14065 case X86::DX: DestReg = X86::EDX; break;
14066 case X86::CX: DestReg = X86::ECX; break;
14067 case X86::BX: DestReg = X86::EBX; break;
14068 case X86::SI: DestReg = X86::ESI; break;
14069 case X86::DI: DestReg = X86::EDI; break;
14070 case X86::BP: DestReg = X86::EBP; break;
14071 case X86::SP: DestReg = X86::ESP; break;
14074 Res.first = DestReg;
14075 Res.second = X86::GR32RegisterClass;
14077 } else if (VT == MVT::i64) {
14078 unsigned DestReg = 0;
14079 switch (Res.first) {
14081 case X86::AX: DestReg = X86::RAX; break;
14082 case X86::DX: DestReg = X86::RDX; break;
14083 case X86::CX: DestReg = X86::RCX; break;
14084 case X86::BX: DestReg = X86::RBX; break;
14085 case X86::SI: DestReg = X86::RSI; break;
14086 case X86::DI: DestReg = X86::RDI; break;
14087 case X86::BP: DestReg = X86::RBP; break;
14088 case X86::SP: DestReg = X86::RSP; break;
14091 Res.first = DestReg;
14092 Res.second = X86::GR64RegisterClass;
14095 } else if (Res.second == X86::FR32RegisterClass ||
14096 Res.second == X86::FR64RegisterClass ||
14097 Res.second == X86::VR128RegisterClass) {
14098 // Handle references to XMM physical registers that got mapped into the
14099 // wrong class. This can happen with constraints like {xmm0} where the
14100 // target independent register mapper will just pick the first match it can
14101 // find, ignoring the required type.
14102 if (VT == MVT::f32)
14103 Res.second = X86::FR32RegisterClass;
14104 else if (VT == MVT::f64)
14105 Res.second = X86::FR64RegisterClass;
14106 else if (X86::VR128RegisterClass->hasType(VT))
14107 Res.second = X86::VR128RegisterClass;