1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "x86-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> ExperimentalVectorWideningLegalization(
62 "x86-experimental-vector-widening-legalization", cl::init(false),
63 cl::desc("Enable an experimental vector type legalization through widening "
64 "rather than promotion."),
67 static cl::opt<bool> ExperimentalVectorShuffleLowering(
68 "x86-experimental-vector-shuffle-lowering", cl::init(false),
69 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 // Forward declarations.
73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
77 SelectionDAG &DAG, SDLoc dl,
78 unsigned vectorWidth) {
79 assert((vectorWidth == 128 || vectorWidth == 256) &&
80 "Unsupported vector width");
81 EVT VT = Vec.getValueType();
82 EVT ElVT = VT.getVectorElementType();
83 unsigned Factor = VT.getSizeInBits()/vectorWidth;
84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
85 VT.getVectorNumElements()/Factor);
87 // Extract from UNDEF is UNDEF.
88 if (Vec.getOpcode() == ISD::UNDEF)
89 return DAG.getUNDEF(ResultVT);
91 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
92 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
94 // This is the index of the first element of the vectorWidth-bit chunk
96 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 // If the input is a buildvector just emit a smaller one.
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
102 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
112 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
113 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
114 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
115 /// instructions or a simple subregister reference. Idx is an index in the
116 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
117 /// lowering EXTRACT_VECTOR_ELT operations easier.
118 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
119 SelectionDAG &DAG, SDLoc dl) {
120 assert((Vec.getValueType().is256BitVector() ||
121 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
122 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 /// Generate a DAG to grab 256-bits from a 512-bit vector.
126 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
129 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
133 unsigned IdxVal, SelectionDAG &DAG,
134 SDLoc dl, unsigned vectorWidth) {
135 assert((vectorWidth == 128 || vectorWidth == 256) &&
136 "Unsupported vector width");
137 // Inserting UNDEF is Result
138 if (Vec.getOpcode() == ISD::UNDEF)
140 EVT VT = Vec.getValueType();
141 EVT ElVT = VT.getVectorElementType();
142 EVT ResultVT = Result.getValueType();
144 // Insert the relevant vectorWidth bits.
145 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
147 // This is the index of the first element of the vectorWidth-bit chunk
149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
157 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
158 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
159 /// simple superregister reference. Idx is an index in the 128 bits
160 /// we want. It need not be aligned to a 128-bit bounday. That makes
161 /// lowering INSERT_VECTOR_ELT operations easier.
162 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
163 unsigned IdxVal, SelectionDAG &DAG,
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
170 unsigned IdxVal, SelectionDAG &DAG,
172 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
177 /// instructions. This is used because creating CONCAT_VECTOR nodes of
178 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
179 /// large BUILD_VECTORS.
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
181 unsigned NumElems, SelectionDAG &DAG,
183 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
184 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
188 unsigned NumElems, SelectionDAG &DAG,
190 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
191 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
195 if (TT.isOSBinFormatMachO()) {
196 if (TT.getArch() == Triple::x86_64)
197 return new X86_64MachoTargetObjectFile();
198 return new TargetLoweringObjectFileMachO();
202 return new X86LinuxTargetObjectFile();
203 if (TT.isOSBinFormatELF())
204 return new TargetLoweringObjectFileELF();
205 if (TT.isKnownWindowsMSVCEnvironment())
206 return new X86WindowsTargetObjectFile();
207 if (TT.isOSBinFormatCOFF())
208 return new TargetLoweringObjectFileCOFF();
209 llvm_unreachable("unknown subtarget type");
212 // FIXME: This should stop caching the target machine as soon as
213 // we can remove resetOperationActions et al.
214 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
215 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
216 Subtarget = &TM.getSubtarget<X86Subtarget>();
217 X86ScalarSSEf64 = Subtarget->hasSSE2();
218 X86ScalarSSEf32 = Subtarget->hasSSE1();
219 TD = getDataLayout();
221 resetOperationActions();
224 void X86TargetLowering::resetOperationActions() {
225 const TargetMachine &TM = getTargetMachine();
226 static bool FirstTimeThrough = true;
228 // If none of the target options have changed, then we don't need to reset the
229 // operation actions.
230 if (!FirstTimeThrough && TO == TM.Options) return;
232 if (!FirstTimeThrough) {
233 // Reinitialize the actions.
235 FirstTimeThrough = false;
240 // Set up the TargetLowering object.
241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
244 setBooleanContents(ZeroOrOneBooleanContent);
245 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
246 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
248 // For 64-bit since we have so many registers use the ILP scheduler, for
249 // 32-bit code use the register pressure specific scheduling.
250 // For Atom, always use ILP scheduling.
251 if (Subtarget->isAtom())
252 setSchedulingPreference(Sched::ILP);
253 else if (Subtarget->is64Bit())
254 setSchedulingPreference(Sched::ILP);
256 setSchedulingPreference(Sched::RegPressure);
257 const X86RegisterInfo *RegInfo =
258 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
259 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
261 // Bypass expensive divides on Atom when compiling with O2
262 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
263 addBypassSlowDiv(32, 8);
264 if (Subtarget->is64Bit())
265 addBypassSlowDiv(64, 16);
268 if (Subtarget->isTargetKnownWindowsMSVC()) {
269 // Setup Windows compiler runtime calls.
270 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
271 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
272 setLibcallName(RTLIB::SREM_I64, "_allrem");
273 setLibcallName(RTLIB::UREM_I64, "_aullrem");
274 setLibcallName(RTLIB::MUL_I64, "_allmul");
275 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
276 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
281 // The _ftol2 runtime function has an unusual calling conv, which
282 // is modeled by a special pseudo-instruction.
283 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
284 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 if (Subtarget->isTargetDarwin()) {
290 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
291 setUseUnderscoreSetJmp(false);
292 setUseUnderscoreLongJmp(false);
293 } else if (Subtarget->isTargetWindowsGNU()) {
294 // MS runtime is weird: it exports _setjmp, but longjmp!
295 setUseUnderscoreSetJmp(true);
296 setUseUnderscoreLongJmp(false);
298 setUseUnderscoreSetJmp(true);
299 setUseUnderscoreLongJmp(true);
302 // Set up the register classes.
303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
306 if (Subtarget->is64Bit())
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
311 // We don't accept any truncstore of integer registers.
312 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
313 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
315 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
319 // SETOEQ and SETUNE require checking two conditions.
320 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
323 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
327 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
329 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
330 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 } else if (!TM.Options.UseSoftFloat) {
337 // We have an algorithm for SSE2->double, and we turn this into a
338 // 64-bit FILD followed by conditional FADD for other targets.
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 // We have an algorithm for SSE2, and we turn this into a 64-bit
341 // FILD for other targets.
342 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
345 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
347 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
350 if (!TM.Options.UseSoftFloat) {
351 // SSE has no i16 to fp conversion, only i32
352 if (X86ScalarSSEf32) {
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 // f32 and f64 cases are Legal, f80 case is not
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
365 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
366 // are Legal, f80 is custom lowered.
367 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
368 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
370 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
372 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
375 if (X86ScalarSSEf32) {
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
377 // f32 and f64 cases are Legal, f80 case is not
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 // Handle FP_TO_UINT by promoting the destination to a larger signed
386 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
390 if (Subtarget->is64Bit()) {
391 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
393 } else if (!TM.Options.UseSoftFloat) {
394 // Since AVX is a superset of SSE3, only check for SSE here.
395 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
396 // Expand FP_TO_UINT into a select.
397 // FIXME: We would like to use a Custom expander here eventually to do
398 // the optimal thing for SSE vs. the default expansion in the legalizer.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
401 // With SSE3 we can use fisttpll to convert to a signed i64; without
402 // SSE, we're stuck with a fistpll.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
406 if (isTargetFTOL()) {
407 // Use the _ftol2 runtime function, which has a pseudo-instruction
408 // to handle its weird calling convention.
409 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
412 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
413 if (!X86ScalarSSEf64) {
414 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
415 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
418 // Without SSE, i64->f64 goes through memory.
419 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
423 // Scalar integer divide and remainder are lowered to use operations that
424 // produce two results, to match the available instructions. This exposes
425 // the two-result form to trivial CSE, which is able to combine x/y and x%y
426 // into a single instruction.
428 // Scalar integer multiply-high is also lowered to use two-result
429 // operations, to match the available instructions. However, plain multiply
430 // (low) operations are left as Legal, as there are single-result
431 // instructions for this in x86. Using the two-result multiply instructions
432 // when both high and low results are needed must be arranged by dagcombine.
433 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
435 setOperationAction(ISD::MULHS, VT, Expand);
436 setOperationAction(ISD::MULHU, VT, Expand);
437 setOperationAction(ISD::SDIV, VT, Expand);
438 setOperationAction(ISD::UDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UREM, VT, Expand);
442 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
443 setOperationAction(ISD::ADDC, VT, Custom);
444 setOperationAction(ISD::ADDE, VT, Custom);
445 setOperationAction(ISD::SUBC, VT, Custom);
446 setOperationAction(ISD::SUBE, VT, Custom);
449 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
450 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
451 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
465 if (Subtarget->is64Bit())
466 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
470 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
471 setOperationAction(ISD::FREM , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f64 , Expand);
473 setOperationAction(ISD::FREM , MVT::f80 , Expand);
474 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
476 // Promote the i8 variants and force them on up to i32 which has a shorter
478 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
481 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
482 if (Subtarget->hasBMI()) {
483 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
489 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
490 if (Subtarget->is64Bit())
491 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
494 if (Subtarget->hasLZCNT()) {
495 // When promoting the i8 variants, force them to i32 for a shorter
497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
500 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
512 if (Subtarget->is64Bit()) {
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
518 // Special handling for half-precision floating point conversions.
519 // If we don't have F16C support, then lower half float conversions
520 // into library calls.
521 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
522 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
523 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
526 // There's never any support for operations beyond MVT::f32.
527 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
528 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
529 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
530 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
532 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
533 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
534 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
535 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
537 if (Subtarget->hasPOPCNT()) {
538 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
540 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
541 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
542 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
547 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
549 if (!Subtarget->hasMOVBE())
550 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
552 // These should be promoted to a larger select which is supported.
553 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
554 // X86 wants to expand cmov itself.
555 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
556 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
557 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
558 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
559 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
560 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
563 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
564 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
565 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
566 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
567 if (Subtarget->is64Bit()) {
568 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
569 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
571 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
572 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
573 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
574 // support continuation, user-level threading, and etc.. As a result, no
575 // other SjLj exception interfaces are implemented and please don't build
576 // your own exception handling based on them.
577 // LLVM/Clang supports zero-cost DWARF exception handling.
578 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
579 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
582 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
585 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
586 if (Subtarget->is64Bit())
587 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
588 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
589 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
590 if (Subtarget->is64Bit()) {
591 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
592 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
593 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
594 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
595 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
597 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
598 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
599 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
600 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
601 if (Subtarget->is64Bit()) {
602 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
607 if (Subtarget->hasSSE1())
608 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
610 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
612 // Expand certain atomics
613 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
615 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
616 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
617 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
620 if (Subtarget->hasCmpxchg16b()) {
621 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
624 // FIXME - use subtarget debug flags
625 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
626 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
627 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
630 if (Subtarget->is64Bit()) {
631 setExceptionPointerRegister(X86::RAX);
632 setExceptionSelectorRegister(X86::RDX);
634 setExceptionPointerRegister(X86::EAX);
635 setExceptionSelectorRegister(X86::EDX);
637 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
638 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
640 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
641 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
643 setOperationAction(ISD::TRAP, MVT::Other, Legal);
644 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
646 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
647 setOperationAction(ISD::VASTART , MVT::Other, Custom);
648 setOperationAction(ISD::VAEND , MVT::Other, Expand);
649 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
650 // TargetInfo::X86_64ABIBuiltinVaList
651 setOperationAction(ISD::VAARG , MVT::Other, Custom);
652 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
654 // TargetInfo::CharPtrBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Expand);
656 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
659 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
660 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
662 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
664 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
665 // f32 and f64 use SSE.
666 // Set up the FP register classes.
667 addRegisterClass(MVT::f32, &X86::FR32RegClass);
668 addRegisterClass(MVT::f64, &X86::FR64RegClass);
670 // Use ANDPD to simulate FABS.
671 setOperationAction(ISD::FABS , MVT::f64, Custom);
672 setOperationAction(ISD::FABS , MVT::f32, Custom);
674 // Use XORP to simulate FNEG.
675 setOperationAction(ISD::FNEG , MVT::f64, Custom);
676 setOperationAction(ISD::FNEG , MVT::f32, Custom);
678 // Use ANDPD and ORPD to simulate FCOPYSIGN.
679 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
680 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
682 // Lower this to FGETSIGNx86 plus an AND.
683 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
684 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
686 // We don't support sin/cos/fmod
687 setOperationAction(ISD::FSIN , MVT::f64, Expand);
688 setOperationAction(ISD::FCOS , MVT::f64, Expand);
689 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
690 setOperationAction(ISD::FSIN , MVT::f32, Expand);
691 setOperationAction(ISD::FCOS , MVT::f32, Expand);
692 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
694 // Expand FP immediates into loads from the stack, except for the special
696 addLegalFPImmediate(APFloat(+0.0)); // xorpd
697 addLegalFPImmediate(APFloat(+0.0f)); // xorps
698 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
699 // Use SSE for f32, x87 for f64.
700 // Set up the FP register classes.
701 addRegisterClass(MVT::f32, &X86::FR32RegClass);
702 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
704 // Use ANDPS to simulate FABS.
705 setOperationAction(ISD::FABS , MVT::f32, Custom);
707 // Use XORP to simulate FNEG.
708 setOperationAction(ISD::FNEG , MVT::f32, Custom);
710 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
712 // Use ANDPS and ORPS to simulate FCOPYSIGN.
713 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
714 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
716 // We don't support sin/cos/fmod
717 setOperationAction(ISD::FSIN , MVT::f32, Expand);
718 setOperationAction(ISD::FCOS , MVT::f32, Expand);
719 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
721 // Special cases we handle for FP constants.
722 addLegalFPImmediate(APFloat(+0.0f)); // xorps
723 addLegalFPImmediate(APFloat(+0.0)); // FLD0
724 addLegalFPImmediate(APFloat(+1.0)); // FLD1
725 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
726 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
728 if (!TM.Options.UnsafeFPMath) {
729 setOperationAction(ISD::FSIN , MVT::f64, Expand);
730 setOperationAction(ISD::FCOS , MVT::f64, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
733 } else if (!TM.Options.UseSoftFloat) {
734 // f32 and f64 in x87.
735 // Set up the FP register classes.
736 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
737 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
739 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
740 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
741 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
742 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
744 if (!TM.Options.UnsafeFPMath) {
745 setOperationAction(ISD::FSIN , MVT::f64, Expand);
746 setOperationAction(ISD::FSIN , MVT::f32, Expand);
747 setOperationAction(ISD::FCOS , MVT::f64, Expand);
748 setOperationAction(ISD::FCOS , MVT::f32, Expand);
749 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
750 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
752 addLegalFPImmediate(APFloat(+0.0)); // FLD0
753 addLegalFPImmediate(APFloat(+1.0)); // FLD1
754 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
755 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
756 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
762 // We don't support FMA.
763 setOperationAction(ISD::FMA, MVT::f64, Expand);
764 setOperationAction(ISD::FMA, MVT::f32, Expand);
766 // Long double always uses X87.
767 if (!TM.Options.UseSoftFloat) {
768 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
769 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
770 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
772 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
773 addLegalFPImmediate(TmpFlt); // FLD0
775 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
778 APFloat TmpFlt2(+1.0);
779 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
781 addLegalFPImmediate(TmpFlt2); // FLD1
782 TmpFlt2.changeSign();
783 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
786 if (!TM.Options.UnsafeFPMath) {
787 setOperationAction(ISD::FSIN , MVT::f80, Expand);
788 setOperationAction(ISD::FCOS , MVT::f80, Expand);
789 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
792 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
793 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
794 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
795 setOperationAction(ISD::FRINT, MVT::f80, Expand);
796 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
797 setOperationAction(ISD::FMA, MVT::f80, Expand);
800 // Always use a library call for pow.
801 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
802 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
803 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
805 setOperationAction(ISD::FLOG, MVT::f80, Expand);
806 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
807 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
808 setOperationAction(ISD::FEXP, MVT::f80, Expand);
809 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
811 // First set operation action for all vector types to either promote
812 // (for widening) or expand (for scalarization). Then we will selectively
813 // turn on ones that can be effectively codegen'd.
814 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
815 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
816 MVT VT = (MVT::SimpleValueType)i;
817 setOperationAction(ISD::ADD , VT, Expand);
818 setOperationAction(ISD::SUB , VT, Expand);
819 setOperationAction(ISD::FADD, VT, Expand);
820 setOperationAction(ISD::FNEG, VT, Expand);
821 setOperationAction(ISD::FSUB, VT, Expand);
822 setOperationAction(ISD::MUL , VT, Expand);
823 setOperationAction(ISD::FMUL, VT, Expand);
824 setOperationAction(ISD::SDIV, VT, Expand);
825 setOperationAction(ISD::UDIV, VT, Expand);
826 setOperationAction(ISD::FDIV, VT, Expand);
827 setOperationAction(ISD::SREM, VT, Expand);
828 setOperationAction(ISD::UREM, VT, Expand);
829 setOperationAction(ISD::LOAD, VT, Expand);
830 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
831 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
833 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
834 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
835 setOperationAction(ISD::FABS, VT, Expand);
836 setOperationAction(ISD::FSIN, VT, Expand);
837 setOperationAction(ISD::FSINCOS, VT, Expand);
838 setOperationAction(ISD::FCOS, VT, Expand);
839 setOperationAction(ISD::FSINCOS, VT, Expand);
840 setOperationAction(ISD::FREM, VT, Expand);
841 setOperationAction(ISD::FMA, VT, Expand);
842 setOperationAction(ISD::FPOWI, VT, Expand);
843 setOperationAction(ISD::FSQRT, VT, Expand);
844 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
845 setOperationAction(ISD::FFLOOR, VT, Expand);
846 setOperationAction(ISD::FCEIL, VT, Expand);
847 setOperationAction(ISD::FTRUNC, VT, Expand);
848 setOperationAction(ISD::FRINT, VT, Expand);
849 setOperationAction(ISD::FNEARBYINT, VT, Expand);
850 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
851 setOperationAction(ISD::MULHS, VT, Expand);
852 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
853 setOperationAction(ISD::MULHU, VT, Expand);
854 setOperationAction(ISD::SDIVREM, VT, Expand);
855 setOperationAction(ISD::UDIVREM, VT, Expand);
856 setOperationAction(ISD::FPOW, VT, Expand);
857 setOperationAction(ISD::CTPOP, VT, Expand);
858 setOperationAction(ISD::CTTZ, VT, Expand);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
860 setOperationAction(ISD::CTLZ, VT, Expand);
861 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
862 setOperationAction(ISD::SHL, VT, Expand);
863 setOperationAction(ISD::SRA, VT, Expand);
864 setOperationAction(ISD::SRL, VT, Expand);
865 setOperationAction(ISD::ROTL, VT, Expand);
866 setOperationAction(ISD::ROTR, VT, Expand);
867 setOperationAction(ISD::BSWAP, VT, Expand);
868 setOperationAction(ISD::SETCC, VT, Expand);
869 setOperationAction(ISD::FLOG, VT, Expand);
870 setOperationAction(ISD::FLOG2, VT, Expand);
871 setOperationAction(ISD::FLOG10, VT, Expand);
872 setOperationAction(ISD::FEXP, VT, Expand);
873 setOperationAction(ISD::FEXP2, VT, Expand);
874 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
875 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
876 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
877 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
878 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
879 setOperationAction(ISD::TRUNCATE, VT, Expand);
880 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
881 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
882 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
883 setOperationAction(ISD::VSELECT, VT, Expand);
884 setOperationAction(ISD::SELECT_CC, VT, Expand);
885 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
886 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
887 setTruncStoreAction(VT,
888 (MVT::SimpleValueType)InnerVT, Expand);
889 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
890 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
892 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
893 // we have to deal with them whether we ask for Expansion or not. Setting
894 // Expand causes its own optimisation problems though, so leave them legal.
895 if (VT.getVectorElementType() == MVT::i1)
896 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
899 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
900 // with -msoft-float, disable use of MMX as well.
901 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
902 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
903 // No operations on x86mmx supported, everything uses intrinsics.
906 // MMX-sized vectors (other than x86mmx) are expected to be expanded
907 // into smaller operations.
908 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
909 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
910 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
911 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
912 setOperationAction(ISD::AND, MVT::v8i8, Expand);
913 setOperationAction(ISD::AND, MVT::v4i16, Expand);
914 setOperationAction(ISD::AND, MVT::v2i32, Expand);
915 setOperationAction(ISD::AND, MVT::v1i64, Expand);
916 setOperationAction(ISD::OR, MVT::v8i8, Expand);
917 setOperationAction(ISD::OR, MVT::v4i16, Expand);
918 setOperationAction(ISD::OR, MVT::v2i32, Expand);
919 setOperationAction(ISD::OR, MVT::v1i64, Expand);
920 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
921 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
922 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
923 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
924 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
929 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
930 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
931 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
932 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
933 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
936 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
938 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
939 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
941 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
942 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
943 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
944 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
945 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
946 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
947 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
948 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
949 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
950 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
951 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
952 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
955 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
956 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
958 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
959 // registers cannot be used even for integer operations.
960 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
961 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
962 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
963 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
965 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
966 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
967 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
968 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
969 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
970 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
971 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
972 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
974 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
975 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
976 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
977 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
978 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
979 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
980 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
981 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
982 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
983 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
984 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
985 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
986 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
988 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
990 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
991 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
993 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
999 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1000 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1001 MVT VT = (MVT::SimpleValueType)i;
1002 // Do not attempt to custom lower non-power-of-2 vectors
1003 if (!isPowerOf2_32(VT.getVectorNumElements()))
1005 // Do not attempt to custom lower non-128-bit vectors
1006 if (!VT.is128BitVector())
1008 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1009 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1010 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1013 // We support custom legalizing of sext and anyext loads for specific
1014 // memory vector types which we can load as a scalar (or sequence of
1015 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1016 // loads these must work with a single scalar load.
1017 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1018 if (Subtarget->is64Bit()) {
1019 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1020 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1022 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1029 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1030 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1031 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1032 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1033 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1034 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1036 if (Subtarget->is64Bit()) {
1037 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1038 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1041 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1042 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1043 MVT VT = (MVT::SimpleValueType)i;
1045 // Do not attempt to promote non-128-bit vectors
1046 if (!VT.is128BitVector())
1049 setOperationAction(ISD::AND, VT, Promote);
1050 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1051 setOperationAction(ISD::OR, VT, Promote);
1052 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1053 setOperationAction(ISD::XOR, VT, Promote);
1054 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1055 setOperationAction(ISD::LOAD, VT, Promote);
1056 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1057 setOperationAction(ISD::SELECT, VT, Promote);
1058 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1061 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1531 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1534 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1535 // of this type with custom code.
1536 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1537 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1538 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1542 // We want to custom lower some of our intrinsics.
1543 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1544 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1545 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1546 if (!Subtarget->is64Bit())
1547 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1549 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1550 // handle type legalization for these operations here.
1552 // FIXME: We really should do custom legalization for addition and
1553 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1554 // than generic legalization for 64-bit multiplication-with-overflow, though.
1555 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1556 // Add/Sub/Mul with overflow operations are custom lowered.
1558 setOperationAction(ISD::SADDO, VT, Custom);
1559 setOperationAction(ISD::UADDO, VT, Custom);
1560 setOperationAction(ISD::SSUBO, VT, Custom);
1561 setOperationAction(ISD::USUBO, VT, Custom);
1562 setOperationAction(ISD::SMULO, VT, Custom);
1563 setOperationAction(ISD::UMULO, VT, Custom);
1566 // There are no 8-bit 3-address imul/mul instructions
1567 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1568 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1570 if (!Subtarget->is64Bit()) {
1571 // These libcalls are not available in 32-bit.
1572 setLibcallName(RTLIB::SHL_I128, nullptr);
1573 setLibcallName(RTLIB::SRL_I128, nullptr);
1574 setLibcallName(RTLIB::SRA_I128, nullptr);
1577 // Combine sin / cos into one node or libcall if possible.
1578 if (Subtarget->hasSinCos()) {
1579 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1580 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1581 if (Subtarget->isTargetDarwin()) {
1582 // For MacOSX, we don't want to the normal expansion of a libcall to
1583 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1585 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1586 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1590 if (Subtarget->isTargetWin64()) {
1591 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1592 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1593 setOperationAction(ISD::SREM, MVT::i128, Custom);
1594 setOperationAction(ISD::UREM, MVT::i128, Custom);
1595 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1596 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1599 // We have target-specific dag combine patterns for the following nodes:
1600 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1601 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1602 setTargetDAGCombine(ISD::VSELECT);
1603 setTargetDAGCombine(ISD::SELECT);
1604 setTargetDAGCombine(ISD::SHL);
1605 setTargetDAGCombine(ISD::SRA);
1606 setTargetDAGCombine(ISD::SRL);
1607 setTargetDAGCombine(ISD::OR);
1608 setTargetDAGCombine(ISD::AND);
1609 setTargetDAGCombine(ISD::ADD);
1610 setTargetDAGCombine(ISD::FADD);
1611 setTargetDAGCombine(ISD::FSUB);
1612 setTargetDAGCombine(ISD::FMA);
1613 setTargetDAGCombine(ISD::SUB);
1614 setTargetDAGCombine(ISD::LOAD);
1615 setTargetDAGCombine(ISD::STORE);
1616 setTargetDAGCombine(ISD::ZERO_EXTEND);
1617 setTargetDAGCombine(ISD::ANY_EXTEND);
1618 setTargetDAGCombine(ISD::SIGN_EXTEND);
1619 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1620 setTargetDAGCombine(ISD::TRUNCATE);
1621 setTargetDAGCombine(ISD::SINT_TO_FP);
1622 setTargetDAGCombine(ISD::SETCC);
1623 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1624 setTargetDAGCombine(ISD::BUILD_VECTOR);
1625 if (Subtarget->is64Bit())
1626 setTargetDAGCombine(ISD::MUL);
1627 setTargetDAGCombine(ISD::XOR);
1629 computeRegisterProperties();
1631 // On Darwin, -Os means optimize for size without hurting performance,
1632 // do not reduce the limit.
1633 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1634 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1635 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1636 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1637 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1638 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1639 setPrefLoopAlignment(4); // 2^4 bytes.
1641 // Predictable cmov don't hurt on atom because it's in-order.
1642 PredictableSelectIsExpensive = !Subtarget->isAtom();
1644 setPrefFunctionAlignment(4); // 2^4 bytes.
1647 // This has so far only been implemented for 64-bit MachO.
1648 bool X86TargetLowering::useLoadStackGuardNode() const {
1649 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1650 Subtarget->is64Bit();
1653 TargetLoweringBase::LegalizeTypeAction
1654 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1655 if (ExperimentalVectorWideningLegalization &&
1656 VT.getVectorNumElements() != 1 &&
1657 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1658 return TypeWidenVector;
1660 return TargetLoweringBase::getPreferredVectorAction(VT);
1663 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1665 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1667 if (Subtarget->hasAVX512())
1668 switch(VT.getVectorNumElements()) {
1669 case 8: return MVT::v8i1;
1670 case 16: return MVT::v16i1;
1673 return VT.changeVectorElementTypeToInteger();
1676 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1677 /// the desired ByVal argument alignment.
1678 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1681 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1682 if (VTy->getBitWidth() == 128)
1684 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1685 unsigned EltAlign = 0;
1686 getMaxByValAlign(ATy->getElementType(), EltAlign);
1687 if (EltAlign > MaxAlign)
1688 MaxAlign = EltAlign;
1689 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1690 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1691 unsigned EltAlign = 0;
1692 getMaxByValAlign(STy->getElementType(i), EltAlign);
1693 if (EltAlign > MaxAlign)
1694 MaxAlign = EltAlign;
1701 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1702 /// function arguments in the caller parameter area. For X86, aggregates
1703 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1704 /// are at 4-byte boundaries.
1705 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1706 if (Subtarget->is64Bit()) {
1707 // Max of 8 and alignment of type.
1708 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1715 if (Subtarget->hasSSE1())
1716 getMaxByValAlign(Ty, Align);
1720 /// getOptimalMemOpType - Returns the target specific optimal type for load
1721 /// and store operations as a result of memset, memcpy, and memmove
1722 /// lowering. If DstAlign is zero that means it's safe to destination
1723 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1724 /// means there isn't a need to check it against alignment requirement,
1725 /// probably because the source does not need to be loaded. If 'IsMemset' is
1726 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1727 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1728 /// source is constant so it does not need to be loaded.
1729 /// It returns EVT::Other if the type should be determined using generic
1730 /// target-independent logic.
1732 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1733 unsigned DstAlign, unsigned SrcAlign,
1734 bool IsMemset, bool ZeroMemset,
1736 MachineFunction &MF) const {
1737 const Function *F = MF.getFunction();
1738 if ((!IsMemset || ZeroMemset) &&
1739 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1740 Attribute::NoImplicitFloat)) {
1742 (Subtarget->isUnalignedMemAccessFast() ||
1743 ((DstAlign == 0 || DstAlign >= 16) &&
1744 (SrcAlign == 0 || SrcAlign >= 16)))) {
1746 if (Subtarget->hasInt256())
1748 if (Subtarget->hasFp256())
1751 if (Subtarget->hasSSE2())
1753 if (Subtarget->hasSSE1())
1755 } else if (!MemcpyStrSrc && Size >= 8 &&
1756 !Subtarget->is64Bit() &&
1757 Subtarget->hasSSE2()) {
1758 // Do not use f64 to lower memcpy if source is string constant. It's
1759 // better to use i32 to avoid the loads.
1763 if (Subtarget->is64Bit() && Size >= 8)
1768 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1770 return X86ScalarSSEf32;
1771 else if (VT == MVT::f64)
1772 return X86ScalarSSEf64;
1777 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1782 *Fast = Subtarget->isUnalignedMemAccessFast();
1786 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1787 /// current function. The returned value is a member of the
1788 /// MachineJumpTableInfo::JTEntryKind enum.
1789 unsigned X86TargetLowering::getJumpTableEncoding() const {
1790 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1792 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1793 Subtarget->isPICStyleGOT())
1794 return MachineJumpTableInfo::EK_Custom32;
1796 // Otherwise, use the normal jump table encoding heuristics.
1797 return TargetLowering::getJumpTableEncoding();
1801 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1802 const MachineBasicBlock *MBB,
1803 unsigned uid,MCContext &Ctx) const{
1804 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1805 Subtarget->isPICStyleGOT());
1806 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1808 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1809 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1812 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1814 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1815 SelectionDAG &DAG) const {
1816 if (!Subtarget->is64Bit())
1817 // This doesn't have SDLoc associated with it, but is not really the
1818 // same as a Register.
1819 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1823 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1824 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1826 const MCExpr *X86TargetLowering::
1827 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1828 MCContext &Ctx) const {
1829 // X86-64 uses RIP relative addressing based on the jump table label.
1830 if (Subtarget->isPICStyleRIPRel())
1831 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1833 // Otherwise, the reference is relative to the PIC base.
1834 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1837 // FIXME: Why this routine is here? Move to RegInfo!
1838 std::pair<const TargetRegisterClass*, uint8_t>
1839 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1840 const TargetRegisterClass *RRC = nullptr;
1842 switch (VT.SimpleTy) {
1844 return TargetLowering::findRepresentativeClass(VT);
1845 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1846 RRC = Subtarget->is64Bit() ?
1847 (const TargetRegisterClass*)&X86::GR64RegClass :
1848 (const TargetRegisterClass*)&X86::GR32RegClass;
1851 RRC = &X86::VR64RegClass;
1853 case MVT::f32: case MVT::f64:
1854 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1855 case MVT::v4f32: case MVT::v2f64:
1856 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1858 RRC = &X86::VR128RegClass;
1861 return std::make_pair(RRC, Cost);
1864 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1865 unsigned &Offset) const {
1866 if (!Subtarget->isTargetLinux())
1869 if (Subtarget->is64Bit()) {
1870 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1872 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1884 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1885 unsigned DestAS) const {
1886 assert(SrcAS != DestAS && "Expected different address spaces!");
1888 return SrcAS < 256 && DestAS < 256;
1891 //===----------------------------------------------------------------------===//
1892 // Return Value Calling Convention Implementation
1893 //===----------------------------------------------------------------------===//
1895 #include "X86GenCallingConv.inc"
1898 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1899 MachineFunction &MF, bool isVarArg,
1900 const SmallVectorImpl<ISD::OutputArg> &Outs,
1901 LLVMContext &Context) const {
1902 SmallVector<CCValAssign, 16> RVLocs;
1903 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1904 return CCInfo.CheckReturn(Outs, RetCC_X86);
1907 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1908 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1913 X86TargetLowering::LowerReturn(SDValue Chain,
1914 CallingConv::ID CallConv, bool isVarArg,
1915 const SmallVectorImpl<ISD::OutputArg> &Outs,
1916 const SmallVectorImpl<SDValue> &OutVals,
1917 SDLoc dl, SelectionDAG &DAG) const {
1918 MachineFunction &MF = DAG.getMachineFunction();
1919 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1921 SmallVector<CCValAssign, 16> RVLocs;
1922 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1923 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1926 SmallVector<SDValue, 6> RetOps;
1927 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1928 // Operand #1 = Bytes To Pop
1929 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1932 // Copy the result values into the output registers.
1933 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1934 CCValAssign &VA = RVLocs[i];
1935 assert(VA.isRegLoc() && "Can only return in registers!");
1936 SDValue ValToCopy = OutVals[i];
1937 EVT ValVT = ValToCopy.getValueType();
1939 // Promote values to the appropriate types
1940 if (VA.getLocInfo() == CCValAssign::SExt)
1941 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1942 else if (VA.getLocInfo() == CCValAssign::ZExt)
1943 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1944 else if (VA.getLocInfo() == CCValAssign::AExt)
1945 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1946 else if (VA.getLocInfo() == CCValAssign::BCvt)
1947 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1949 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1950 "Unexpected FP-extend for return value.");
1952 // If this is x86-64, and we disabled SSE, we can't return FP values,
1953 // or SSE or MMX vectors.
1954 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1955 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1956 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1957 report_fatal_error("SSE register return with SSE disabled");
1959 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1960 // llvm-gcc has never done it right and no one has noticed, so this
1961 // should be OK for now.
1962 if (ValVT == MVT::f64 &&
1963 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1964 report_fatal_error("SSE2 register return with SSE2 disabled");
1966 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1967 // the RET instruction and handled by the FP Stackifier.
1968 if (VA.getLocReg() == X86::FP0 ||
1969 VA.getLocReg() == X86::FP1) {
1970 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1971 // change the value to the FP stack register class.
1972 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1973 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1974 RetOps.push_back(ValToCopy);
1975 // Don't emit a copytoreg.
1979 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1980 // which is returned in RAX / RDX.
1981 if (Subtarget->is64Bit()) {
1982 if (ValVT == MVT::x86mmx) {
1983 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1984 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1985 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1987 // If we don't have SSE2 available, convert to v4f32 so the generated
1988 // register is legal.
1989 if (!Subtarget->hasSSE2())
1990 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1995 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1996 Flag = Chain.getValue(1);
1997 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2000 // The x86-64 ABIs require that for returning structs by value we copy
2001 // the sret argument into %rax/%eax (depending on ABI) for the return.
2002 // Win32 requires us to put the sret argument to %eax as well.
2003 // We saved the argument into a virtual register in the entry block,
2004 // so now we copy the value out and into %rax/%eax.
2005 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2006 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2007 MachineFunction &MF = DAG.getMachineFunction();
2008 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2009 unsigned Reg = FuncInfo->getSRetReturnReg();
2011 "SRetReturnReg should have been set in LowerFormalArguments().");
2012 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2015 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2016 X86::RAX : X86::EAX;
2017 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2018 Flag = Chain.getValue(1);
2020 // RAX/EAX now acts like a return value.
2021 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2024 RetOps[0] = Chain; // Update chain.
2026 // Add the flag if we have it.
2028 RetOps.push_back(Flag);
2030 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2033 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2034 if (N->getNumValues() != 1)
2036 if (!N->hasNUsesOfValue(1, 0))
2039 SDValue TCChain = Chain;
2040 SDNode *Copy = *N->use_begin();
2041 if (Copy->getOpcode() == ISD::CopyToReg) {
2042 // If the copy has a glue operand, we conservatively assume it isn't safe to
2043 // perform a tail call.
2044 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2046 TCChain = Copy->getOperand(0);
2047 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2050 bool HasRet = false;
2051 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2053 if (UI->getOpcode() != X86ISD::RET_FLAG)
2066 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2067 ISD::NodeType ExtendKind) const {
2069 // TODO: Is this also valid on 32-bit?
2070 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2071 ReturnMVT = MVT::i8;
2073 ReturnMVT = MVT::i32;
2075 EVT MinVT = getRegisterType(Context, ReturnMVT);
2076 return VT.bitsLT(MinVT) ? MinVT : VT;
2079 /// LowerCallResult - Lower the result values of a call into the
2080 /// appropriate copies out of appropriate physical registers.
2083 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2084 CallingConv::ID CallConv, bool isVarArg,
2085 const SmallVectorImpl<ISD::InputArg> &Ins,
2086 SDLoc dl, SelectionDAG &DAG,
2087 SmallVectorImpl<SDValue> &InVals) const {
2089 // Assign locations to each value returned by this call.
2090 SmallVector<CCValAssign, 16> RVLocs;
2091 bool Is64Bit = Subtarget->is64Bit();
2092 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2094 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2096 // Copy all of the result registers out of their specified physreg.
2097 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2098 CCValAssign &VA = RVLocs[i];
2099 EVT CopyVT = VA.getValVT();
2101 // If this is x86-64, and we disabled SSE, we can't return FP values
2102 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2103 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2104 report_fatal_error("SSE register return with SSE disabled");
2107 // If we prefer to use the value in xmm registers, copy it out as f80 and
2108 // use a truncate to move it from fp stack reg to xmm reg.
2109 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2110 isScalarFPTypeInSSEReg(VA.getValVT()))
2113 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2114 CopyVT, InFlag).getValue(1);
2115 SDValue Val = Chain.getValue(0);
2117 if (CopyVT != VA.getValVT())
2118 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2119 // This truncation won't change the value.
2120 DAG.getIntPtrConstant(1));
2122 InFlag = Chain.getValue(2);
2123 InVals.push_back(Val);
2129 //===----------------------------------------------------------------------===//
2130 // C & StdCall & Fast Calling Convention implementation
2131 //===----------------------------------------------------------------------===//
2132 // StdCall calling convention seems to be standard for many Windows' API
2133 // routines and around. It differs from C calling convention just a little:
2134 // callee should clean up the stack, not caller. Symbols should be also
2135 // decorated in some fancy way :) It doesn't support any vector arguments.
2136 // For info on fast calling convention see Fast Calling Convention (tail call)
2137 // implementation LowerX86_32FastCCCallTo.
2139 /// CallIsStructReturn - Determines whether a call uses struct return
2141 enum StructReturnType {
2146 static StructReturnType
2147 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2149 return NotStructReturn;
2151 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2152 if (!Flags.isSRet())
2153 return NotStructReturn;
2154 if (Flags.isInReg())
2155 return RegStructReturn;
2156 return StackStructReturn;
2159 /// ArgsAreStructReturn - Determines whether a function uses struct
2160 /// return semantics.
2161 static StructReturnType
2162 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2164 return NotStructReturn;
2166 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2167 if (!Flags.isSRet())
2168 return NotStructReturn;
2169 if (Flags.isInReg())
2170 return RegStructReturn;
2171 return StackStructReturn;
2174 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2175 /// by "Src" to address "Dst" with size and alignment information specified by
2176 /// the specific parameter attribute. The copy will be passed as a byval
2177 /// function parameter.
2179 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2180 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2182 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2184 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2185 /*isVolatile*/false, /*AlwaysInline=*/true,
2186 MachinePointerInfo(), MachinePointerInfo());
2189 /// IsTailCallConvention - Return true if the calling convention is one that
2190 /// supports tail call optimization.
2191 static bool IsTailCallConvention(CallingConv::ID CC) {
2192 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2193 CC == CallingConv::HiPE);
2196 /// \brief Return true if the calling convention is a C calling convention.
2197 static bool IsCCallConvention(CallingConv::ID CC) {
2198 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2199 CC == CallingConv::X86_64_SysV);
2202 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2203 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2207 CallingConv::ID CalleeCC = CS.getCallingConv();
2208 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2214 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2215 /// a tailcall target by changing its ABI.
2216 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2217 bool GuaranteedTailCallOpt) {
2218 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2222 X86TargetLowering::LowerMemArgument(SDValue Chain,
2223 CallingConv::ID CallConv,
2224 const SmallVectorImpl<ISD::InputArg> &Ins,
2225 SDLoc dl, SelectionDAG &DAG,
2226 const CCValAssign &VA,
2227 MachineFrameInfo *MFI,
2229 // Create the nodes corresponding to a load from this parameter slot.
2230 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2231 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2232 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2233 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2236 // If value is passed by pointer we have address passed instead of the value
2238 if (VA.getLocInfo() == CCValAssign::Indirect)
2239 ValVT = VA.getLocVT();
2241 ValVT = VA.getValVT();
2243 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2244 // changed with more analysis.
2245 // In case of tail call optimization mark all arguments mutable. Since they
2246 // could be overwritten by lowering of arguments in case of a tail call.
2247 if (Flags.isByVal()) {
2248 unsigned Bytes = Flags.getByValSize();
2249 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2250 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2251 return DAG.getFrameIndex(FI, getPointerTy());
2253 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2254 VA.getLocMemOffset(), isImmutable);
2255 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2256 return DAG.getLoad(ValVT, dl, Chain, FIN,
2257 MachinePointerInfo::getFixedStack(FI),
2258 false, false, false, 0);
2263 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2264 CallingConv::ID CallConv,
2266 const SmallVectorImpl<ISD::InputArg> &Ins,
2269 SmallVectorImpl<SDValue> &InVals)
2271 MachineFunction &MF = DAG.getMachineFunction();
2272 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2274 const Function* Fn = MF.getFunction();
2275 if (Fn->hasExternalLinkage() &&
2276 Subtarget->isTargetCygMing() &&
2277 Fn->getName() == "main")
2278 FuncInfo->setForceFramePointer(true);
2280 MachineFrameInfo *MFI = MF.getFrameInfo();
2281 bool Is64Bit = Subtarget->is64Bit();
2282 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2284 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2285 "Var args not supported with calling convention fastcc, ghc or hipe");
2287 // Assign locations to all of the incoming arguments.
2288 SmallVector<CCValAssign, 16> ArgLocs;
2289 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2291 // Allocate shadow area for Win64
2293 CCInfo.AllocateStack(32, 8);
2295 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2297 unsigned LastVal = ~0U;
2299 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2300 CCValAssign &VA = ArgLocs[i];
2301 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2303 assert(VA.getValNo() != LastVal &&
2304 "Don't support value assigned to multiple locs yet");
2306 LastVal = VA.getValNo();
2308 if (VA.isRegLoc()) {
2309 EVT RegVT = VA.getLocVT();
2310 const TargetRegisterClass *RC;
2311 if (RegVT == MVT::i32)
2312 RC = &X86::GR32RegClass;
2313 else if (Is64Bit && RegVT == MVT::i64)
2314 RC = &X86::GR64RegClass;
2315 else if (RegVT == MVT::f32)
2316 RC = &X86::FR32RegClass;
2317 else if (RegVT == MVT::f64)
2318 RC = &X86::FR64RegClass;
2319 else if (RegVT.is512BitVector())
2320 RC = &X86::VR512RegClass;
2321 else if (RegVT.is256BitVector())
2322 RC = &X86::VR256RegClass;
2323 else if (RegVT.is128BitVector())
2324 RC = &X86::VR128RegClass;
2325 else if (RegVT == MVT::x86mmx)
2326 RC = &X86::VR64RegClass;
2327 else if (RegVT == MVT::i1)
2328 RC = &X86::VK1RegClass;
2329 else if (RegVT == MVT::v8i1)
2330 RC = &X86::VK8RegClass;
2331 else if (RegVT == MVT::v16i1)
2332 RC = &X86::VK16RegClass;
2333 else if (RegVT == MVT::v32i1)
2334 RC = &X86::VK32RegClass;
2335 else if (RegVT == MVT::v64i1)
2336 RC = &X86::VK64RegClass;
2338 llvm_unreachable("Unknown argument type!");
2340 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2341 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2343 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2344 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2346 if (VA.getLocInfo() == CCValAssign::SExt)
2347 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2348 DAG.getValueType(VA.getValVT()));
2349 else if (VA.getLocInfo() == CCValAssign::ZExt)
2350 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2351 DAG.getValueType(VA.getValVT()));
2352 else if (VA.getLocInfo() == CCValAssign::BCvt)
2353 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2355 if (VA.isExtInLoc()) {
2356 // Handle MMX values passed in XMM regs.
2357 if (RegVT.isVector())
2358 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2360 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2363 assert(VA.isMemLoc());
2364 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2367 // If value is passed via pointer - do a load.
2368 if (VA.getLocInfo() == CCValAssign::Indirect)
2369 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2370 MachinePointerInfo(), false, false, false, 0);
2372 InVals.push_back(ArgValue);
2375 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2376 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2377 // The x86-64 ABIs require that for returning structs by value we copy
2378 // the sret argument into %rax/%eax (depending on ABI) for the return.
2379 // Win32 requires us to put the sret argument to %eax as well.
2380 // Save the argument into a virtual register so that we can access it
2381 // from the return points.
2382 if (Ins[i].Flags.isSRet()) {
2383 unsigned Reg = FuncInfo->getSRetReturnReg();
2385 MVT PtrTy = getPointerTy();
2386 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2387 FuncInfo->setSRetReturnReg(Reg);
2389 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2390 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2396 unsigned StackSize = CCInfo.getNextStackOffset();
2397 // Align stack specially for tail calls.
2398 if (FuncIsMadeTailCallSafe(CallConv,
2399 MF.getTarget().Options.GuaranteedTailCallOpt))
2400 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2402 // If the function takes variable number of arguments, make a frame index for
2403 // the start of the first vararg value... for expansion of llvm.va_start.
2405 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2406 CallConv != CallingConv::X86_ThisCall)) {
2407 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2410 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2412 // FIXME: We should really autogenerate these arrays
2413 static const MCPhysReg GPR64ArgRegsWin64[] = {
2414 X86::RCX, X86::RDX, X86::R8, X86::R9
2416 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2417 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2419 static const MCPhysReg XMMArgRegs64Bit[] = {
2420 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2421 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2423 const MCPhysReg *GPR64ArgRegs;
2424 unsigned NumXMMRegs = 0;
2427 // The XMM registers which might contain var arg parameters are shadowed
2428 // in their paired GPR. So we only need to save the GPR to their home
2430 TotalNumIntRegs = 4;
2431 GPR64ArgRegs = GPR64ArgRegsWin64;
2433 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2434 GPR64ArgRegs = GPR64ArgRegs64Bit;
2436 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2439 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2442 bool NoImplicitFloatOps = Fn->getAttributes().
2443 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2444 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2445 "SSE register cannot be used when SSE is disabled!");
2446 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2447 NoImplicitFloatOps) &&
2448 "SSE register cannot be used when SSE is disabled!");
2449 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2450 !Subtarget->hasSSE1())
2451 // Kernel mode asks for SSE to be disabled, so don't push them
2453 TotalNumXMMRegs = 0;
2456 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2457 // Get to the caller-allocated home save location. Add 8 to account
2458 // for the return address.
2459 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2460 FuncInfo->setRegSaveFrameIndex(
2461 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2462 // Fixup to set vararg frame on shadow area (4 x i64).
2464 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2466 // For X86-64, if there are vararg parameters that are passed via
2467 // registers, then we must store them to their spots on the stack so
2468 // they may be loaded by deferencing the result of va_next.
2469 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2470 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2471 FuncInfo->setRegSaveFrameIndex(
2472 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2476 // Store the integer parameter registers.
2477 SmallVector<SDValue, 8> MemOps;
2478 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2480 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2481 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2482 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2483 DAG.getIntPtrConstant(Offset));
2484 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2485 &X86::GR64RegClass);
2486 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2488 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2489 MachinePointerInfo::getFixedStack(
2490 FuncInfo->getRegSaveFrameIndex(), Offset),
2492 MemOps.push_back(Store);
2496 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2497 // Now store the XMM (fp + vector) parameter registers.
2498 SmallVector<SDValue, 12> SaveXMMOps;
2499 SaveXMMOps.push_back(Chain);
2501 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2502 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2503 SaveXMMOps.push_back(ALVal);
2505 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2506 FuncInfo->getRegSaveFrameIndex()));
2507 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2508 FuncInfo->getVarArgsFPOffset()));
2510 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2511 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2512 &X86::VR128RegClass);
2513 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2514 SaveXMMOps.push_back(Val);
2516 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2517 MVT::Other, SaveXMMOps));
2520 if (!MemOps.empty())
2521 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2525 // Some CCs need callee pop.
2526 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2527 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2528 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2530 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2531 // If this is an sret function, the return should pop the hidden pointer.
2532 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2533 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2534 argsAreStructReturn(Ins) == StackStructReturn)
2535 FuncInfo->setBytesToPopOnReturn(4);
2539 // RegSaveFrameIndex is X86-64 only.
2540 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2541 if (CallConv == CallingConv::X86_FastCall ||
2542 CallConv == CallingConv::X86_ThisCall)
2543 // fastcc functions can't have varargs.
2544 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2547 FuncInfo->setArgumentStackSize(StackSize);
2553 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2554 SDValue StackPtr, SDValue Arg,
2555 SDLoc dl, SelectionDAG &DAG,
2556 const CCValAssign &VA,
2557 ISD::ArgFlagsTy Flags) const {
2558 unsigned LocMemOffset = VA.getLocMemOffset();
2559 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2560 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2561 if (Flags.isByVal())
2562 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2564 return DAG.getStore(Chain, dl, Arg, PtrOff,
2565 MachinePointerInfo::getStack(LocMemOffset),
2569 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2570 /// optimization is performed and it is required.
2572 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2573 SDValue &OutRetAddr, SDValue Chain,
2574 bool IsTailCall, bool Is64Bit,
2575 int FPDiff, SDLoc dl) const {
2576 // Adjust the Return address stack slot.
2577 EVT VT = getPointerTy();
2578 OutRetAddr = getReturnAddressFrameIndex(DAG);
2580 // Load the "old" Return address.
2581 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2582 false, false, false, 0);
2583 return SDValue(OutRetAddr.getNode(), 1);
2586 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2587 /// optimization is performed and it is required (FPDiff!=0).
2588 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2589 SDValue Chain, SDValue RetAddrFrIdx,
2590 EVT PtrVT, unsigned SlotSize,
2591 int FPDiff, SDLoc dl) {
2592 // Store the return address to the appropriate stack slot.
2593 if (!FPDiff) return Chain;
2594 // Calculate the new stack slot for the return address.
2595 int NewReturnAddrFI =
2596 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2598 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2599 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2600 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2606 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2607 SmallVectorImpl<SDValue> &InVals) const {
2608 SelectionDAG &DAG = CLI.DAG;
2610 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2611 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2612 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2613 SDValue Chain = CLI.Chain;
2614 SDValue Callee = CLI.Callee;
2615 CallingConv::ID CallConv = CLI.CallConv;
2616 bool &isTailCall = CLI.IsTailCall;
2617 bool isVarArg = CLI.IsVarArg;
2619 MachineFunction &MF = DAG.getMachineFunction();
2620 bool Is64Bit = Subtarget->is64Bit();
2621 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2622 StructReturnType SR = callIsStructReturn(Outs);
2623 bool IsSibcall = false;
2625 if (MF.getTarget().Options.DisableTailCalls)
2628 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2630 // Force this to be a tail call. The verifier rules are enough to ensure
2631 // that we can lower this successfully without moving the return address
2634 } else if (isTailCall) {
2635 // Check if it's really possible to do a tail call.
2636 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2637 isVarArg, SR != NotStructReturn,
2638 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2639 Outs, OutVals, Ins, DAG);
2641 // Sibcalls are automatically detected tailcalls which do not require
2643 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2650 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2651 "Var args not supported with calling convention fastcc, ghc or hipe");
2653 // Analyze operands of the call, assigning locations to each operand.
2654 SmallVector<CCValAssign, 16> ArgLocs;
2655 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2657 // Allocate shadow area for Win64
2659 CCInfo.AllocateStack(32, 8);
2661 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2663 // Get a count of how many bytes are to be pushed on the stack.
2664 unsigned NumBytes = CCInfo.getNextStackOffset();
2666 // This is a sibcall. The memory operands are available in caller's
2667 // own caller's stack.
2669 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2670 IsTailCallConvention(CallConv))
2671 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2674 if (isTailCall && !IsSibcall && !IsMustTail) {
2675 // Lower arguments at fp - stackoffset + fpdiff.
2676 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2677 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2679 FPDiff = NumBytesCallerPushed - NumBytes;
2681 // Set the delta of movement of the returnaddr stackslot.
2682 // But only set if delta is greater than previous delta.
2683 if (FPDiff < X86Info->getTCReturnAddrDelta())
2684 X86Info->setTCReturnAddrDelta(FPDiff);
2687 unsigned NumBytesToPush = NumBytes;
2688 unsigned NumBytesToPop = NumBytes;
2690 // If we have an inalloca argument, all stack space has already been allocated
2691 // for us and be right at the top of the stack. We don't support multiple
2692 // arguments passed in memory when using inalloca.
2693 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2695 if (!ArgLocs.back().isMemLoc())
2696 report_fatal_error("cannot use inalloca attribute on a register "
2698 if (ArgLocs.back().getLocMemOffset() != 0)
2699 report_fatal_error("any parameter with the inalloca attribute must be "
2700 "the only memory argument");
2704 Chain = DAG.getCALLSEQ_START(
2705 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2707 SDValue RetAddrFrIdx;
2708 // Load return address for tail calls.
2709 if (isTailCall && FPDiff)
2710 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2711 Is64Bit, FPDiff, dl);
2713 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2714 SmallVector<SDValue, 8> MemOpChains;
2717 // Walk the register/memloc assignments, inserting copies/loads. In the case
2718 // of tail call optimization arguments are handle later.
2719 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2720 DAG.getSubtarget().getRegisterInfo());
2721 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2722 // Skip inalloca arguments, they have already been written.
2723 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2724 if (Flags.isInAlloca())
2727 CCValAssign &VA = ArgLocs[i];
2728 EVT RegVT = VA.getLocVT();
2729 SDValue Arg = OutVals[i];
2730 bool isByVal = Flags.isByVal();
2732 // Promote the value if needed.
2733 switch (VA.getLocInfo()) {
2734 default: llvm_unreachable("Unknown loc info!");
2735 case CCValAssign::Full: break;
2736 case CCValAssign::SExt:
2737 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2739 case CCValAssign::ZExt:
2740 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2742 case CCValAssign::AExt:
2743 if (RegVT.is128BitVector()) {
2744 // Special case: passing MMX values in XMM registers.
2745 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2746 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2747 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2749 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2751 case CCValAssign::BCvt:
2752 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2754 case CCValAssign::Indirect: {
2755 // Store the argument.
2756 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2757 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2758 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2759 MachinePointerInfo::getFixedStack(FI),
2766 if (VA.isRegLoc()) {
2767 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2768 if (isVarArg && IsWin64) {
2769 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2770 // shadow reg if callee is a varargs function.
2771 unsigned ShadowReg = 0;
2772 switch (VA.getLocReg()) {
2773 case X86::XMM0: ShadowReg = X86::RCX; break;
2774 case X86::XMM1: ShadowReg = X86::RDX; break;
2775 case X86::XMM2: ShadowReg = X86::R8; break;
2776 case X86::XMM3: ShadowReg = X86::R9; break;
2779 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2781 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2782 assert(VA.isMemLoc());
2783 if (!StackPtr.getNode())
2784 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2786 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2787 dl, DAG, VA, Flags));
2791 if (!MemOpChains.empty())
2792 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2794 if (Subtarget->isPICStyleGOT()) {
2795 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2798 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2799 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2801 // If we are tail calling and generating PIC/GOT style code load the
2802 // address of the callee into ECX. The value in ecx is used as target of
2803 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2804 // for tail calls on PIC/GOT architectures. Normally we would just put the
2805 // address of GOT into ebx and then call target@PLT. But for tail calls
2806 // ebx would be restored (since ebx is callee saved) before jumping to the
2809 // Note: The actual moving to ECX is done further down.
2810 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2811 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2812 !G->getGlobal()->hasProtectedVisibility())
2813 Callee = LowerGlobalAddress(Callee, DAG);
2814 else if (isa<ExternalSymbolSDNode>(Callee))
2815 Callee = LowerExternalSymbol(Callee, DAG);
2819 if (Is64Bit && isVarArg && !IsWin64) {
2820 // From AMD64 ABI document:
2821 // For calls that may call functions that use varargs or stdargs
2822 // (prototype-less calls or calls to functions containing ellipsis (...) in
2823 // the declaration) %al is used as hidden argument to specify the number
2824 // of SSE registers used. The contents of %al do not need to match exactly
2825 // the number of registers, but must be an ubound on the number of SSE
2826 // registers used and is in the range 0 - 8 inclusive.
2828 // Count the number of XMM registers allocated.
2829 static const MCPhysReg XMMArgRegs[] = {
2830 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2831 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2833 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2834 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2835 && "SSE registers cannot be used when SSE is disabled");
2837 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2838 DAG.getConstant(NumXMMRegs, MVT::i8)));
2841 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2842 // don't need this because the eligibility check rejects calls that require
2843 // shuffling arguments passed in memory.
2844 if (!IsSibcall && isTailCall) {
2845 // Force all the incoming stack arguments to be loaded from the stack
2846 // before any new outgoing arguments are stored to the stack, because the
2847 // outgoing stack slots may alias the incoming argument stack slots, and
2848 // the alias isn't otherwise explicit. This is slightly more conservative
2849 // than necessary, because it means that each store effectively depends
2850 // on every argument instead of just those arguments it would clobber.
2851 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2853 SmallVector<SDValue, 8> MemOpChains2;
2856 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2857 CCValAssign &VA = ArgLocs[i];
2860 assert(VA.isMemLoc());
2861 SDValue Arg = OutVals[i];
2862 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2863 // Skip inalloca arguments. They don't require any work.
2864 if (Flags.isInAlloca())
2866 // Create frame index.
2867 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2868 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2869 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2870 FIN = DAG.getFrameIndex(FI, getPointerTy());
2872 if (Flags.isByVal()) {
2873 // Copy relative to framepointer.
2874 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2875 if (!StackPtr.getNode())
2876 StackPtr = DAG.getCopyFromReg(Chain, dl,
2877 RegInfo->getStackRegister(),
2879 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2881 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2885 // Store relative to framepointer.
2886 MemOpChains2.push_back(
2887 DAG.getStore(ArgChain, dl, Arg, FIN,
2888 MachinePointerInfo::getFixedStack(FI),
2893 if (!MemOpChains2.empty())
2894 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2896 // Store the return address to the appropriate stack slot.
2897 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2898 getPointerTy(), RegInfo->getSlotSize(),
2902 // Build a sequence of copy-to-reg nodes chained together with token chain
2903 // and flag operands which copy the outgoing args into registers.
2905 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2906 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2907 RegsToPass[i].second, InFlag);
2908 InFlag = Chain.getValue(1);
2911 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2912 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2913 // In the 64-bit large code model, we have to make all calls
2914 // through a register, since the call instruction's 32-bit
2915 // pc-relative offset may not be large enough to hold the whole
2917 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2918 // If the callee is a GlobalAddress node (quite common, every direct call
2919 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2922 // We should use extra load for direct calls to dllimported functions in
2924 const GlobalValue *GV = G->getGlobal();
2925 if (!GV->hasDLLImportStorageClass()) {
2926 unsigned char OpFlags = 0;
2927 bool ExtraLoad = false;
2928 unsigned WrapperKind = ISD::DELETED_NODE;
2930 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2931 // external symbols most go through the PLT in PIC mode. If the symbol
2932 // has hidden or protected visibility, or if it is static or local, then
2933 // we don't need to use the PLT - we can directly call it.
2934 if (Subtarget->isTargetELF() &&
2935 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
2936 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2937 OpFlags = X86II::MO_PLT;
2938 } else if (Subtarget->isPICStyleStubAny() &&
2939 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2940 (!Subtarget->getTargetTriple().isMacOSX() ||
2941 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2942 // PC-relative references to external symbols should go through $stub,
2943 // unless we're building with the leopard linker or later, which
2944 // automatically synthesizes these stubs.
2945 OpFlags = X86II::MO_DARWIN_STUB;
2946 } else if (Subtarget->isPICStyleRIPRel() &&
2947 isa<Function>(GV) &&
2948 cast<Function>(GV)->getAttributes().
2949 hasAttribute(AttributeSet::FunctionIndex,
2950 Attribute::NonLazyBind)) {
2951 // If the function is marked as non-lazy, generate an indirect call
2952 // which loads from the GOT directly. This avoids runtime overhead
2953 // at the cost of eager binding (and one extra byte of encoding).
2954 OpFlags = X86II::MO_GOTPCREL;
2955 WrapperKind = X86ISD::WrapperRIP;
2959 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2960 G->getOffset(), OpFlags);
2962 // Add a wrapper if needed.
2963 if (WrapperKind != ISD::DELETED_NODE)
2964 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2965 // Add extra indirection if needed.
2967 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2968 MachinePointerInfo::getGOT(),
2969 false, false, false, 0);
2971 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2972 unsigned char OpFlags = 0;
2974 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2975 // external symbols should go through the PLT.
2976 if (Subtarget->isTargetELF() &&
2977 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
2978 OpFlags = X86II::MO_PLT;
2979 } else if (Subtarget->isPICStyleStubAny() &&
2980 (!Subtarget->getTargetTriple().isMacOSX() ||
2981 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2982 // PC-relative references to external symbols should go through $stub,
2983 // unless we're building with the leopard linker or later, which
2984 // automatically synthesizes these stubs.
2985 OpFlags = X86II::MO_DARWIN_STUB;
2988 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2992 // Returns a chain & a flag for retval copy to use.
2993 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2994 SmallVector<SDValue, 8> Ops;
2996 if (!IsSibcall && isTailCall) {
2997 Chain = DAG.getCALLSEQ_END(Chain,
2998 DAG.getIntPtrConstant(NumBytesToPop, true),
2999 DAG.getIntPtrConstant(0, true), InFlag, dl);
3000 InFlag = Chain.getValue(1);
3003 Ops.push_back(Chain);
3004 Ops.push_back(Callee);
3007 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3009 // Add argument registers to the end of the list so that they are known live
3011 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3012 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3013 RegsToPass[i].second.getValueType()));
3015 // Add a register mask operand representing the call-preserved registers.
3016 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3017 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3018 assert(Mask && "Missing call preserved mask for calling convention");
3019 Ops.push_back(DAG.getRegisterMask(Mask));
3021 if (InFlag.getNode())
3022 Ops.push_back(InFlag);
3026 //// If this is the first return lowered for this function, add the regs
3027 //// to the liveout set for the function.
3028 // This isn't right, although it's probably harmless on x86; liveouts
3029 // should be computed from returns not tail calls. Consider a void
3030 // function making a tail call to a function returning int.
3031 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3034 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3035 InFlag = Chain.getValue(1);
3037 // Create the CALLSEQ_END node.
3038 unsigned NumBytesForCalleeToPop;
3039 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3040 DAG.getTarget().Options.GuaranteedTailCallOpt))
3041 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3042 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3043 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3044 SR == StackStructReturn)
3045 // If this is a call to a struct-return function, the callee
3046 // pops the hidden struct pointer, so we have to push it back.
3047 // This is common for Darwin/X86, Linux & Mingw32 targets.
3048 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3049 NumBytesForCalleeToPop = 4;
3051 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3053 // Returns a flag for retval copy to use.
3055 Chain = DAG.getCALLSEQ_END(Chain,
3056 DAG.getIntPtrConstant(NumBytesToPop, true),
3057 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3060 InFlag = Chain.getValue(1);
3063 // Handle result values, copying them out of physregs into vregs that we
3065 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3066 Ins, dl, DAG, InVals);
3069 //===----------------------------------------------------------------------===//
3070 // Fast Calling Convention (tail call) implementation
3071 //===----------------------------------------------------------------------===//
3073 // Like std call, callee cleans arguments, convention except that ECX is
3074 // reserved for storing the tail called function address. Only 2 registers are
3075 // free for argument passing (inreg). Tail call optimization is performed
3077 // * tailcallopt is enabled
3078 // * caller/callee are fastcc
3079 // On X86_64 architecture with GOT-style position independent code only local
3080 // (within module) calls are supported at the moment.
3081 // To keep the stack aligned according to platform abi the function
3082 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3083 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3084 // If a tail called function callee has more arguments than the caller the
3085 // caller needs to make sure that there is room to move the RETADDR to. This is
3086 // achieved by reserving an area the size of the argument delta right after the
3087 // original RETADDR, but before the saved framepointer or the spilled registers
3088 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3100 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3101 /// for a 16 byte align requirement.
3103 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3104 SelectionDAG& DAG) const {
3105 MachineFunction &MF = DAG.getMachineFunction();
3106 const TargetMachine &TM = MF.getTarget();
3107 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3108 TM.getSubtargetImpl()->getRegisterInfo());
3109 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3110 unsigned StackAlignment = TFI.getStackAlignment();
3111 uint64_t AlignMask = StackAlignment - 1;
3112 int64_t Offset = StackSize;
3113 unsigned SlotSize = RegInfo->getSlotSize();
3114 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3115 // Number smaller than 12 so just add the difference.
3116 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3118 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3119 Offset = ((~AlignMask) & Offset) + StackAlignment +
3120 (StackAlignment-SlotSize);
3125 /// MatchingStackOffset - Return true if the given stack call argument is
3126 /// already available in the same position (relatively) of the caller's
3127 /// incoming argument stack.
3129 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3130 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3131 const X86InstrInfo *TII) {
3132 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3134 if (Arg.getOpcode() == ISD::CopyFromReg) {
3135 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3136 if (!TargetRegisterInfo::isVirtualRegister(VR))
3138 MachineInstr *Def = MRI->getVRegDef(VR);
3141 if (!Flags.isByVal()) {
3142 if (!TII->isLoadFromStackSlot(Def, FI))
3145 unsigned Opcode = Def->getOpcode();
3146 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3147 Def->getOperand(1).isFI()) {
3148 FI = Def->getOperand(1).getIndex();
3149 Bytes = Flags.getByValSize();
3153 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3154 if (Flags.isByVal())
3155 // ByVal argument is passed in as a pointer but it's now being
3156 // dereferenced. e.g.
3157 // define @foo(%struct.X* %A) {
3158 // tail call @bar(%struct.X* byval %A)
3161 SDValue Ptr = Ld->getBasePtr();
3162 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3165 FI = FINode->getIndex();
3166 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3167 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3168 FI = FINode->getIndex();
3169 Bytes = Flags.getByValSize();
3173 assert(FI != INT_MAX);
3174 if (!MFI->isFixedObjectIndex(FI))
3176 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3179 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3180 /// for tail call optimization. Targets which want to do tail call
3181 /// optimization should implement this function.
3183 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3184 CallingConv::ID CalleeCC,
3186 bool isCalleeStructRet,
3187 bool isCallerStructRet,
3189 const SmallVectorImpl<ISD::OutputArg> &Outs,
3190 const SmallVectorImpl<SDValue> &OutVals,
3191 const SmallVectorImpl<ISD::InputArg> &Ins,
3192 SelectionDAG &DAG) const {
3193 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3196 // If -tailcallopt is specified, make fastcc functions tail-callable.
3197 const MachineFunction &MF = DAG.getMachineFunction();
3198 const Function *CallerF = MF.getFunction();
3200 // If the function return type is x86_fp80 and the callee return type is not,
3201 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3202 // perform a tailcall optimization here.
3203 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3206 CallingConv::ID CallerCC = CallerF->getCallingConv();
3207 bool CCMatch = CallerCC == CalleeCC;
3208 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3209 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3211 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3212 if (IsTailCallConvention(CalleeCC) && CCMatch)
3217 // Look for obvious safe cases to perform tail call optimization that do not
3218 // require ABI changes. This is what gcc calls sibcall.
3220 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3221 // emit a special epilogue.
3222 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3223 DAG.getSubtarget().getRegisterInfo());
3224 if (RegInfo->needsStackRealignment(MF))
3227 // Also avoid sibcall optimization if either caller or callee uses struct
3228 // return semantics.
3229 if (isCalleeStructRet || isCallerStructRet)
3232 // An stdcall/thiscall caller is expected to clean up its arguments; the
3233 // callee isn't going to do that.
3234 // FIXME: this is more restrictive than needed. We could produce a tailcall
3235 // when the stack adjustment matches. For example, with a thiscall that takes
3236 // only one argument.
3237 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3238 CallerCC == CallingConv::X86_ThisCall))
3241 // Do not sibcall optimize vararg calls unless all arguments are passed via
3243 if (isVarArg && !Outs.empty()) {
3245 // Optimizing for varargs on Win64 is unlikely to be safe without
3246 // additional testing.
3247 if (IsCalleeWin64 || IsCallerWin64)
3250 SmallVector<CCValAssign, 16> ArgLocs;
3251 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3254 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3255 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3256 if (!ArgLocs[i].isRegLoc())
3260 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3261 // stack. Therefore, if it's not used by the call it is not safe to optimize
3262 // this into a sibcall.
3263 bool Unused = false;
3264 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3271 SmallVector<CCValAssign, 16> RVLocs;
3272 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3274 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3275 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3276 CCValAssign &VA = RVLocs[i];
3277 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3282 // If the calling conventions do not match, then we'd better make sure the
3283 // results are returned in the same way as what the caller expects.
3285 SmallVector<CCValAssign, 16> RVLocs1;
3286 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3288 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3290 SmallVector<CCValAssign, 16> RVLocs2;
3291 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3293 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3295 if (RVLocs1.size() != RVLocs2.size())
3297 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3298 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3300 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3302 if (RVLocs1[i].isRegLoc()) {
3303 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3306 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3312 // If the callee takes no arguments then go on to check the results of the
3314 if (!Outs.empty()) {
3315 // Check if stack adjustment is needed. For now, do not do this if any
3316 // argument is passed on the stack.
3317 SmallVector<CCValAssign, 16> ArgLocs;
3318 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3321 // Allocate shadow area for Win64
3323 CCInfo.AllocateStack(32, 8);
3325 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3326 if (CCInfo.getNextStackOffset()) {
3327 MachineFunction &MF = DAG.getMachineFunction();
3328 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3331 // Check if the arguments are already laid out in the right way as
3332 // the caller's fixed stack objects.
3333 MachineFrameInfo *MFI = MF.getFrameInfo();
3334 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3335 const X86InstrInfo *TII =
3336 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3337 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3338 CCValAssign &VA = ArgLocs[i];
3339 SDValue Arg = OutVals[i];
3340 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3341 if (VA.getLocInfo() == CCValAssign::Indirect)
3343 if (!VA.isRegLoc()) {
3344 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3351 // If the tailcall address may be in a register, then make sure it's
3352 // possible to register allocate for it. In 32-bit, the call address can
3353 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3354 // callee-saved registers are restored. These happen to be the same
3355 // registers used to pass 'inreg' arguments so watch out for those.
3356 if (!Subtarget->is64Bit() &&
3357 ((!isa<GlobalAddressSDNode>(Callee) &&
3358 !isa<ExternalSymbolSDNode>(Callee)) ||
3359 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3360 unsigned NumInRegs = 0;
3361 // In PIC we need an extra register to formulate the address computation
3363 unsigned MaxInRegs =
3364 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3366 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3367 CCValAssign &VA = ArgLocs[i];
3370 unsigned Reg = VA.getLocReg();
3373 case X86::EAX: case X86::EDX: case X86::ECX:
3374 if (++NumInRegs == MaxInRegs)
3386 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3387 const TargetLibraryInfo *libInfo) const {
3388 return X86::createFastISel(funcInfo, libInfo);
3391 //===----------------------------------------------------------------------===//
3392 // Other Lowering Hooks
3393 //===----------------------------------------------------------------------===//
3395 static bool MayFoldLoad(SDValue Op) {
3396 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3399 static bool MayFoldIntoStore(SDValue Op) {
3400 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3403 static bool isTargetShuffle(unsigned Opcode) {
3405 default: return false;
3406 case X86ISD::PSHUFB:
3407 case X86ISD::PSHUFD:
3408 case X86ISD::PSHUFHW:
3409 case X86ISD::PSHUFLW:
3411 case X86ISD::PALIGNR:
3412 case X86ISD::MOVLHPS:
3413 case X86ISD::MOVLHPD:
3414 case X86ISD::MOVHLPS:
3415 case X86ISD::MOVLPS:
3416 case X86ISD::MOVLPD:
3417 case X86ISD::MOVSHDUP:
3418 case X86ISD::MOVSLDUP:
3419 case X86ISD::MOVDDUP:
3422 case X86ISD::UNPCKL:
3423 case X86ISD::UNPCKH:
3424 case X86ISD::VPERMILP:
3425 case X86ISD::VPERM2X128:
3426 case X86ISD::VPERMI:
3431 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3432 SDValue V1, SelectionDAG &DAG) {
3434 default: llvm_unreachable("Unknown x86 shuffle node");
3435 case X86ISD::MOVSHDUP:
3436 case X86ISD::MOVSLDUP:
3437 case X86ISD::MOVDDUP:
3438 return DAG.getNode(Opc, dl, VT, V1);
3442 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3443 SDValue V1, unsigned TargetMask,
3444 SelectionDAG &DAG) {
3446 default: llvm_unreachable("Unknown x86 shuffle node");
3447 case X86ISD::PSHUFD:
3448 case X86ISD::PSHUFHW:
3449 case X86ISD::PSHUFLW:
3450 case X86ISD::VPERMILP:
3451 case X86ISD::VPERMI:
3452 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3456 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3457 SDValue V1, SDValue V2, unsigned TargetMask,
3458 SelectionDAG &DAG) {
3460 default: llvm_unreachable("Unknown x86 shuffle node");
3461 case X86ISD::PALIGNR:
3462 case X86ISD::VALIGN:
3464 case X86ISD::VPERM2X128:
3465 return DAG.getNode(Opc, dl, VT, V1, V2,
3466 DAG.getConstant(TargetMask, MVT::i8));
3470 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3471 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3473 default: llvm_unreachable("Unknown x86 shuffle node");
3474 case X86ISD::MOVLHPS:
3475 case X86ISD::MOVLHPD:
3476 case X86ISD::MOVHLPS:
3477 case X86ISD::MOVLPS:
3478 case X86ISD::MOVLPD:
3481 case X86ISD::UNPCKL:
3482 case X86ISD::UNPCKH:
3483 return DAG.getNode(Opc, dl, VT, V1, V2);
3487 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3488 MachineFunction &MF = DAG.getMachineFunction();
3489 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3490 DAG.getSubtarget().getRegisterInfo());
3491 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3492 int ReturnAddrIndex = FuncInfo->getRAIndex();
3494 if (ReturnAddrIndex == 0) {
3495 // Set up a frame object for the return address.
3496 unsigned SlotSize = RegInfo->getSlotSize();
3497 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3500 FuncInfo->setRAIndex(ReturnAddrIndex);
3503 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3506 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3507 bool hasSymbolicDisplacement) {
3508 // Offset should fit into 32 bit immediate field.
3509 if (!isInt<32>(Offset))
3512 // If we don't have a symbolic displacement - we don't have any extra
3514 if (!hasSymbolicDisplacement)
3517 // FIXME: Some tweaks might be needed for medium code model.
3518 if (M != CodeModel::Small && M != CodeModel::Kernel)
3521 // For small code model we assume that latest object is 16MB before end of 31
3522 // bits boundary. We may also accept pretty large negative constants knowing
3523 // that all objects are in the positive half of address space.
3524 if (M == CodeModel::Small && Offset < 16*1024*1024)
3527 // For kernel code model we know that all object resist in the negative half
3528 // of 32bits address space. We may not accept negative offsets, since they may
3529 // be just off and we may accept pretty large positive ones.
3530 if (M == CodeModel::Kernel && Offset > 0)
3536 /// isCalleePop - Determines whether the callee is required to pop its
3537 /// own arguments. Callee pop is necessary to support tail calls.
3538 bool X86::isCalleePop(CallingConv::ID CallingConv,
3539 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3543 switch (CallingConv) {
3546 case CallingConv::X86_StdCall:
3548 case CallingConv::X86_FastCall:
3550 case CallingConv::X86_ThisCall:
3552 case CallingConv::Fast:
3554 case CallingConv::GHC:
3556 case CallingConv::HiPE:
3561 /// \brief Return true if the condition is an unsigned comparison operation.
3562 static bool isX86CCUnsigned(unsigned X86CC) {
3564 default: llvm_unreachable("Invalid integer condition!");
3565 case X86::COND_E: return true;
3566 case X86::COND_G: return false;
3567 case X86::COND_GE: return false;
3568 case X86::COND_L: return false;
3569 case X86::COND_LE: return false;
3570 case X86::COND_NE: return true;
3571 case X86::COND_B: return true;
3572 case X86::COND_A: return true;
3573 case X86::COND_BE: return true;
3574 case X86::COND_AE: return true;
3576 llvm_unreachable("covered switch fell through?!");
3579 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3580 /// specific condition code, returning the condition code and the LHS/RHS of the
3581 /// comparison to make.
3582 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3583 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3585 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3586 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3587 // X > -1 -> X == 0, jump !sign.
3588 RHS = DAG.getConstant(0, RHS.getValueType());
3589 return X86::COND_NS;
3591 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3592 // X < 0 -> X == 0, jump on sign.
3595 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3597 RHS = DAG.getConstant(0, RHS.getValueType());
3598 return X86::COND_LE;
3602 switch (SetCCOpcode) {
3603 default: llvm_unreachable("Invalid integer condition!");
3604 case ISD::SETEQ: return X86::COND_E;
3605 case ISD::SETGT: return X86::COND_G;
3606 case ISD::SETGE: return X86::COND_GE;
3607 case ISD::SETLT: return X86::COND_L;
3608 case ISD::SETLE: return X86::COND_LE;
3609 case ISD::SETNE: return X86::COND_NE;
3610 case ISD::SETULT: return X86::COND_B;
3611 case ISD::SETUGT: return X86::COND_A;
3612 case ISD::SETULE: return X86::COND_BE;
3613 case ISD::SETUGE: return X86::COND_AE;
3617 // First determine if it is required or is profitable to flip the operands.
3619 // If LHS is a foldable load, but RHS is not, flip the condition.
3620 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3621 !ISD::isNON_EXTLoad(RHS.getNode())) {
3622 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3623 std::swap(LHS, RHS);
3626 switch (SetCCOpcode) {
3632 std::swap(LHS, RHS);
3636 // On a floating point condition, the flags are set as follows:
3638 // 0 | 0 | 0 | X > Y
3639 // 0 | 0 | 1 | X < Y
3640 // 1 | 0 | 0 | X == Y
3641 // 1 | 1 | 1 | unordered
3642 switch (SetCCOpcode) {
3643 default: llvm_unreachable("Condcode should be pre-legalized away");
3645 case ISD::SETEQ: return X86::COND_E;
3646 case ISD::SETOLT: // flipped
3648 case ISD::SETGT: return X86::COND_A;
3649 case ISD::SETOLE: // flipped
3651 case ISD::SETGE: return X86::COND_AE;
3652 case ISD::SETUGT: // flipped
3654 case ISD::SETLT: return X86::COND_B;
3655 case ISD::SETUGE: // flipped
3657 case ISD::SETLE: return X86::COND_BE;
3659 case ISD::SETNE: return X86::COND_NE;
3660 case ISD::SETUO: return X86::COND_P;
3661 case ISD::SETO: return X86::COND_NP;
3663 case ISD::SETUNE: return X86::COND_INVALID;
3667 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3668 /// code. Current x86 isa includes the following FP cmov instructions:
3669 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3670 static bool hasFPCMov(unsigned X86CC) {
3686 /// isFPImmLegal - Returns true if the target can instruction select the
3687 /// specified FP immediate natively. If false, the legalizer will
3688 /// materialize the FP immediate as a load from a constant pool.
3689 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3690 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3691 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3697 /// \brief Returns true if it is beneficial to convert a load of a constant
3698 /// to just the constant itself.
3699 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3701 assert(Ty->isIntegerTy());
3703 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3704 if (BitSize == 0 || BitSize > 64)
3709 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3710 /// the specified range (L, H].
3711 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3712 return (Val < 0) || (Val >= Low && Val < Hi);
3715 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3716 /// specified value.
3717 static bool isUndefOrEqual(int Val, int CmpVal) {
3718 return (Val < 0 || Val == CmpVal);
3721 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3722 /// from position Pos and ending in Pos+Size, falls within the specified
3723 /// sequential range (L, L+Pos]. or is undef.
3724 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3725 unsigned Pos, unsigned Size, int Low) {
3726 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3727 if (!isUndefOrEqual(Mask[i], Low))
3732 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3733 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3734 /// the second operand.
3735 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3736 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3737 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3738 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3739 return (Mask[0] < 2 && Mask[1] < 2);
3743 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3744 /// is suitable for input to PSHUFHW.
3745 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3746 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3749 // Lower quadword copied in order or undef.
3750 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3753 // Upper quadword shuffled.
3754 for (unsigned i = 4; i != 8; ++i)
3755 if (!isUndefOrInRange(Mask[i], 4, 8))
3758 if (VT == MVT::v16i16) {
3759 // Lower quadword copied in order or undef.
3760 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3763 // Upper quadword shuffled.
3764 for (unsigned i = 12; i != 16; ++i)
3765 if (!isUndefOrInRange(Mask[i], 12, 16))
3772 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3773 /// is suitable for input to PSHUFLW.
3774 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3775 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3778 // Upper quadword copied in order.
3779 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3782 // Lower quadword shuffled.
3783 for (unsigned i = 0; i != 4; ++i)
3784 if (!isUndefOrInRange(Mask[i], 0, 4))
3787 if (VT == MVT::v16i16) {
3788 // Upper quadword copied in order.
3789 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3792 // Lower quadword shuffled.
3793 for (unsigned i = 8; i != 12; ++i)
3794 if (!isUndefOrInRange(Mask[i], 8, 12))
3801 /// \brief Return true if the mask specifies a shuffle of elements that is
3802 /// suitable for input to intralane (palignr) or interlane (valign) vector
3804 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3805 unsigned NumElts = VT.getVectorNumElements();
3806 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3807 unsigned NumLaneElts = NumElts/NumLanes;
3809 // Do not handle 64-bit element shuffles with palignr.
3810 if (NumLaneElts == 2)
3813 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3815 for (i = 0; i != NumLaneElts; ++i) {
3820 // Lane is all undef, go to next lane
3821 if (i == NumLaneElts)
3824 int Start = Mask[i+l];
3826 // Make sure its in this lane in one of the sources
3827 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3828 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3831 // If not lane 0, then we must match lane 0
3832 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3835 // Correct second source to be contiguous with first source
3836 if (Start >= (int)NumElts)
3837 Start -= NumElts - NumLaneElts;
3839 // Make sure we're shifting in the right direction.
3840 if (Start <= (int)(i+l))
3845 // Check the rest of the elements to see if they are consecutive.
3846 for (++i; i != NumLaneElts; ++i) {
3847 int Idx = Mask[i+l];
3849 // Make sure its in this lane
3850 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3851 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3854 // If not lane 0, then we must match lane 0
3855 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3858 if (Idx >= (int)NumElts)
3859 Idx -= NumElts - NumLaneElts;
3861 if (!isUndefOrEqual(Idx, Start+i))
3870 /// \brief Return true if the node specifies a shuffle of elements that is
3871 /// suitable for input to PALIGNR.
3872 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3873 const X86Subtarget *Subtarget) {
3874 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3875 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
3876 VT.is512BitVector())
3877 // FIXME: Add AVX512BW.
3880 return isAlignrMask(Mask, VT, false);
3883 /// \brief Return true if the node specifies a shuffle of elements that is
3884 /// suitable for input to VALIGN.
3885 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
3886 const X86Subtarget *Subtarget) {
3887 // FIXME: Add AVX512VL.
3888 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
3890 return isAlignrMask(Mask, VT, true);
3893 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3894 /// the two vector operands have swapped position.
3895 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3896 unsigned NumElems) {
3897 for (unsigned i = 0; i != NumElems; ++i) {
3901 else if (idx < (int)NumElems)
3902 Mask[i] = idx + NumElems;
3904 Mask[i] = idx - NumElems;
3908 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3909 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3910 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3911 /// reverse of what x86 shuffles want.
3912 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3914 unsigned NumElems = VT.getVectorNumElements();
3915 unsigned NumLanes = VT.getSizeInBits()/128;
3916 unsigned NumLaneElems = NumElems/NumLanes;
3918 if (NumLaneElems != 2 && NumLaneElems != 4)
3921 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3922 bool symetricMaskRequired =
3923 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3925 // VSHUFPSY divides the resulting vector into 4 chunks.
3926 // The sources are also splitted into 4 chunks, and each destination
3927 // chunk must come from a different source chunk.
3929 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3930 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3932 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3933 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3935 // VSHUFPDY divides the resulting vector into 4 chunks.
3936 // The sources are also splitted into 4 chunks, and each destination
3937 // chunk must come from a different source chunk.
3939 // SRC1 => X3 X2 X1 X0
3940 // SRC2 => Y3 Y2 Y1 Y0
3942 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3944 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3945 unsigned HalfLaneElems = NumLaneElems/2;
3946 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3947 for (unsigned i = 0; i != NumLaneElems; ++i) {
3948 int Idx = Mask[i+l];
3949 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3950 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3952 // For VSHUFPSY, the mask of the second half must be the same as the
3953 // first but with the appropriate offsets. This works in the same way as
3954 // VPERMILPS works with masks.
3955 if (!symetricMaskRequired || Idx < 0)
3957 if (MaskVal[i] < 0) {
3958 MaskVal[i] = Idx - l;
3961 if ((signed)(Idx - l) != MaskVal[i])
3969 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3970 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3971 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3972 if (!VT.is128BitVector())
3975 unsigned NumElems = VT.getVectorNumElements();
3980 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3981 return isUndefOrEqual(Mask[0], 6) &&
3982 isUndefOrEqual(Mask[1], 7) &&
3983 isUndefOrEqual(Mask[2], 2) &&
3984 isUndefOrEqual(Mask[3], 3);
3987 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3988 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3990 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3991 if (!VT.is128BitVector())
3994 unsigned NumElems = VT.getVectorNumElements();
3999 return isUndefOrEqual(Mask[0], 2) &&
4000 isUndefOrEqual(Mask[1], 3) &&
4001 isUndefOrEqual(Mask[2], 2) &&
4002 isUndefOrEqual(Mask[3], 3);
4005 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4006 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4007 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4008 if (!VT.is128BitVector())
4011 unsigned NumElems = VT.getVectorNumElements();
4013 if (NumElems != 2 && NumElems != 4)
4016 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4017 if (!isUndefOrEqual(Mask[i], i + NumElems))
4020 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4021 if (!isUndefOrEqual(Mask[i], i))
4027 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4028 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4029 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4030 if (!VT.is128BitVector())
4033 unsigned NumElems = VT.getVectorNumElements();
4035 if (NumElems != 2 && NumElems != 4)
4038 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4039 if (!isUndefOrEqual(Mask[i], i))
4042 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4043 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4049 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4050 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4051 /// i. e: If all but one element come from the same vector.
4052 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4053 // TODO: Deal with AVX's VINSERTPS
4054 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4057 unsigned CorrectPosV1 = 0;
4058 unsigned CorrectPosV2 = 0;
4059 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4060 if (Mask[i] == -1) {
4068 else if (Mask[i] == i + 4)
4072 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4073 // We have 3 elements (undefs count as elements from any vector) from one
4074 // vector, and one from another.
4081 // Some special combinations that can be optimized.
4084 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4085 SelectionDAG &DAG) {
4086 MVT VT = SVOp->getSimpleValueType(0);
4089 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4092 ArrayRef<int> Mask = SVOp->getMask();
4094 // These are the special masks that may be optimized.
4095 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4096 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4097 bool MatchEvenMask = true;
4098 bool MatchOddMask = true;
4099 for (int i=0; i<8; ++i) {
4100 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4101 MatchEvenMask = false;
4102 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4103 MatchOddMask = false;
4106 if (!MatchEvenMask && !MatchOddMask)
4109 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4111 SDValue Op0 = SVOp->getOperand(0);
4112 SDValue Op1 = SVOp->getOperand(1);
4114 if (MatchEvenMask) {
4115 // Shift the second operand right to 32 bits.
4116 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4117 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4119 // Shift the first operand left to 32 bits.
4120 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4121 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4123 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4124 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4127 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4128 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4129 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4130 bool HasInt256, bool V2IsSplat = false) {
4132 assert(VT.getSizeInBits() >= 128 &&
4133 "Unsupported vector type for unpckl");
4135 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4137 unsigned NumOf256BitLanes;
4138 unsigned NumElts = VT.getVectorNumElements();
4139 if (VT.is256BitVector()) {
4140 if (NumElts != 4 && NumElts != 8 &&
4141 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4144 NumOf256BitLanes = 1;
4145 } else if (VT.is512BitVector()) {
4146 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4147 "Unsupported vector type for unpckh");
4149 NumOf256BitLanes = 2;
4152 NumOf256BitLanes = 1;
4155 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4156 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4158 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4159 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4160 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4161 int BitI = Mask[l256*NumEltsInStride+l+i];
4162 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4163 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4165 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4167 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4175 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4176 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4177 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4178 bool HasInt256, bool V2IsSplat = false) {
4179 assert(VT.getSizeInBits() >= 128 &&
4180 "Unsupported vector type for unpckh");
4182 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4184 unsigned NumOf256BitLanes;
4185 unsigned NumElts = VT.getVectorNumElements();
4186 if (VT.is256BitVector()) {
4187 if (NumElts != 4 && NumElts != 8 &&
4188 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4191 NumOf256BitLanes = 1;
4192 } else if (VT.is512BitVector()) {
4193 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4194 "Unsupported vector type for unpckh");
4196 NumOf256BitLanes = 2;
4199 NumOf256BitLanes = 1;
4202 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4203 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4205 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4206 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4207 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4208 int BitI = Mask[l256*NumEltsInStride+l+i];
4209 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4210 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4212 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4214 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4222 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4223 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4225 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4226 unsigned NumElts = VT.getVectorNumElements();
4227 bool Is256BitVec = VT.is256BitVector();
4229 if (VT.is512BitVector())
4231 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4232 "Unsupported vector type for unpckh");
4234 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4235 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4238 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4239 // FIXME: Need a better way to get rid of this, there's no latency difference
4240 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4241 // the former later. We should also remove the "_undef" special mask.
4242 if (NumElts == 4 && Is256BitVec)
4245 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4246 // independently on 128-bit lanes.
4247 unsigned NumLanes = VT.getSizeInBits()/128;
4248 unsigned NumLaneElts = NumElts/NumLanes;
4250 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4251 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4252 int BitI = Mask[l+i];
4253 int BitI1 = Mask[l+i+1];
4255 if (!isUndefOrEqual(BitI, j))
4257 if (!isUndefOrEqual(BitI1, j))
4265 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4266 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4268 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4269 unsigned NumElts = VT.getVectorNumElements();
4271 if (VT.is512BitVector())
4274 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4275 "Unsupported vector type for unpckh");
4277 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4278 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4281 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4282 // independently on 128-bit lanes.
4283 unsigned NumLanes = VT.getSizeInBits()/128;
4284 unsigned NumLaneElts = NumElts/NumLanes;
4286 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4287 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4288 int BitI = Mask[l+i];
4289 int BitI1 = Mask[l+i+1];
4290 if (!isUndefOrEqual(BitI, j))
4292 if (!isUndefOrEqual(BitI1, j))
4299 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4300 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4301 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4302 if (!VT.is512BitVector())
4305 unsigned NumElts = VT.getVectorNumElements();
4306 unsigned HalfSize = NumElts/2;
4307 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4308 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4313 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4314 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4322 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4323 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4324 /// MOVSD, and MOVD, i.e. setting the lowest element.
4325 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4326 if (VT.getVectorElementType().getSizeInBits() < 32)
4328 if (!VT.is128BitVector())
4331 unsigned NumElts = VT.getVectorNumElements();
4333 if (!isUndefOrEqual(Mask[0], NumElts))
4336 for (unsigned i = 1; i != NumElts; ++i)
4337 if (!isUndefOrEqual(Mask[i], i))
4343 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4344 /// as permutations between 128-bit chunks or halves. As an example: this
4346 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4347 /// The first half comes from the second half of V1 and the second half from the
4348 /// the second half of V2.
4349 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4350 if (!HasFp256 || !VT.is256BitVector())
4353 // The shuffle result is divided into half A and half B. In total the two
4354 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4355 // B must come from C, D, E or F.
4356 unsigned HalfSize = VT.getVectorNumElements()/2;
4357 bool MatchA = false, MatchB = false;
4359 // Check if A comes from one of C, D, E, F.
4360 for (unsigned Half = 0; Half != 4; ++Half) {
4361 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4367 // Check if B comes from one of C, D, E, F.
4368 for (unsigned Half = 0; Half != 4; ++Half) {
4369 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4375 return MatchA && MatchB;
4378 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4379 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4380 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4381 MVT VT = SVOp->getSimpleValueType(0);
4383 unsigned HalfSize = VT.getVectorNumElements()/2;
4385 unsigned FstHalf = 0, SndHalf = 0;
4386 for (unsigned i = 0; i < HalfSize; ++i) {
4387 if (SVOp->getMaskElt(i) > 0) {
4388 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4392 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4393 if (SVOp->getMaskElt(i) > 0) {
4394 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4399 return (FstHalf | (SndHalf << 4));
4402 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4403 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4404 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4408 unsigned NumElts = VT.getVectorNumElements();
4410 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4411 for (unsigned i = 0; i != NumElts; ++i) {
4414 Imm8 |= Mask[i] << (i*2);
4419 unsigned LaneSize = 4;
4420 SmallVector<int, 4> MaskVal(LaneSize, -1);
4422 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4423 for (unsigned i = 0; i != LaneSize; ++i) {
4424 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4428 if (MaskVal[i] < 0) {
4429 MaskVal[i] = Mask[i+l] - l;
4430 Imm8 |= MaskVal[i] << (i*2);
4433 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4440 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4441 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4442 /// Note that VPERMIL mask matching is different depending whether theunderlying
4443 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4444 /// to the same elements of the low, but to the higher half of the source.
4445 /// In VPERMILPD the two lanes could be shuffled independently of each other
4446 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4447 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4448 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4449 if (VT.getSizeInBits() < 256 || EltSize < 32)
4451 bool symetricMaskRequired = (EltSize == 32);
4452 unsigned NumElts = VT.getVectorNumElements();
4454 unsigned NumLanes = VT.getSizeInBits()/128;
4455 unsigned LaneSize = NumElts/NumLanes;
4456 // 2 or 4 elements in one lane
4458 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4459 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4460 for (unsigned i = 0; i != LaneSize; ++i) {
4461 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4463 if (symetricMaskRequired) {
4464 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4465 ExpectedMaskVal[i] = Mask[i+l] - l;
4468 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4476 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4477 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4478 /// element of vector 2 and the other elements to come from vector 1 in order.
4479 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4480 bool V2IsSplat = false, bool V2IsUndef = false) {
4481 if (!VT.is128BitVector())
4484 unsigned NumOps = VT.getVectorNumElements();
4485 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4488 if (!isUndefOrEqual(Mask[0], 0))
4491 for (unsigned i = 1; i != NumOps; ++i)
4492 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4493 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4494 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4500 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4501 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4502 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4503 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4504 const X86Subtarget *Subtarget) {
4505 if (!Subtarget->hasSSE3())
4508 unsigned NumElems = VT.getVectorNumElements();
4510 if ((VT.is128BitVector() && NumElems != 4) ||
4511 (VT.is256BitVector() && NumElems != 8) ||
4512 (VT.is512BitVector() && NumElems != 16))
4515 // "i+1" is the value the indexed mask element must have
4516 for (unsigned i = 0; i != NumElems; i += 2)
4517 if (!isUndefOrEqual(Mask[i], i+1) ||
4518 !isUndefOrEqual(Mask[i+1], i+1))
4524 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4525 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4526 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4527 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4528 const X86Subtarget *Subtarget) {
4529 if (!Subtarget->hasSSE3())
4532 unsigned NumElems = VT.getVectorNumElements();
4534 if ((VT.is128BitVector() && NumElems != 4) ||
4535 (VT.is256BitVector() && NumElems != 8) ||
4536 (VT.is512BitVector() && NumElems != 16))
4539 // "i" is the value the indexed mask element must have
4540 for (unsigned i = 0; i != NumElems; i += 2)
4541 if (!isUndefOrEqual(Mask[i], i) ||
4542 !isUndefOrEqual(Mask[i+1], i))
4548 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4549 /// specifies a shuffle of elements that is suitable for input to 256-bit
4550 /// version of MOVDDUP.
4551 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4552 if (!HasFp256 || !VT.is256BitVector())
4555 unsigned NumElts = VT.getVectorNumElements();
4559 for (unsigned i = 0; i != NumElts/2; ++i)
4560 if (!isUndefOrEqual(Mask[i], 0))
4562 for (unsigned i = NumElts/2; i != NumElts; ++i)
4563 if (!isUndefOrEqual(Mask[i], NumElts/2))
4568 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4569 /// specifies a shuffle of elements that is suitable for input to 128-bit
4570 /// version of MOVDDUP.
4571 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4572 if (!VT.is128BitVector())
4575 unsigned e = VT.getVectorNumElements() / 2;
4576 for (unsigned i = 0; i != e; ++i)
4577 if (!isUndefOrEqual(Mask[i], i))
4579 for (unsigned i = 0; i != e; ++i)
4580 if (!isUndefOrEqual(Mask[e+i], i))
4585 /// isVEXTRACTIndex - Return true if the specified
4586 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4587 /// suitable for instruction that extract 128 or 256 bit vectors
4588 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4589 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4590 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4593 // The index should be aligned on a vecWidth-bit boundary.
4595 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4597 MVT VT = N->getSimpleValueType(0);
4598 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4599 bool Result = (Index * ElSize) % vecWidth == 0;
4604 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4605 /// operand specifies a subvector insert that is suitable for input to
4606 /// insertion of 128 or 256-bit subvectors
4607 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4608 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4609 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4611 // The index should be aligned on a vecWidth-bit boundary.
4613 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4615 MVT VT = N->getSimpleValueType(0);
4616 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4617 bool Result = (Index * ElSize) % vecWidth == 0;
4622 bool X86::isVINSERT128Index(SDNode *N) {
4623 return isVINSERTIndex(N, 128);
4626 bool X86::isVINSERT256Index(SDNode *N) {
4627 return isVINSERTIndex(N, 256);
4630 bool X86::isVEXTRACT128Index(SDNode *N) {
4631 return isVEXTRACTIndex(N, 128);
4634 bool X86::isVEXTRACT256Index(SDNode *N) {
4635 return isVEXTRACTIndex(N, 256);
4638 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4639 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4640 /// Handles 128-bit and 256-bit.
4641 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4642 MVT VT = N->getSimpleValueType(0);
4644 assert((VT.getSizeInBits() >= 128) &&
4645 "Unsupported vector type for PSHUF/SHUFP");
4647 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4648 // independently on 128-bit lanes.
4649 unsigned NumElts = VT.getVectorNumElements();
4650 unsigned NumLanes = VT.getSizeInBits()/128;
4651 unsigned NumLaneElts = NumElts/NumLanes;
4653 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4654 "Only supports 2, 4 or 8 elements per lane");
4656 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4658 for (unsigned i = 0; i != NumElts; ++i) {
4659 int Elt = N->getMaskElt(i);
4660 if (Elt < 0) continue;
4661 Elt &= NumLaneElts - 1;
4662 unsigned ShAmt = (i << Shift) % 8;
4663 Mask |= Elt << ShAmt;
4669 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4670 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4671 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4672 MVT VT = N->getSimpleValueType(0);
4674 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4675 "Unsupported vector type for PSHUFHW");
4677 unsigned NumElts = VT.getVectorNumElements();
4680 for (unsigned l = 0; l != NumElts; l += 8) {
4681 // 8 nodes per lane, but we only care about the last 4.
4682 for (unsigned i = 0; i < 4; ++i) {
4683 int Elt = N->getMaskElt(l+i+4);
4684 if (Elt < 0) continue;
4685 Elt &= 0x3; // only 2-bits.
4686 Mask |= Elt << (i * 2);
4693 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4694 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4695 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4696 MVT VT = N->getSimpleValueType(0);
4698 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4699 "Unsupported vector type for PSHUFHW");
4701 unsigned NumElts = VT.getVectorNumElements();
4704 for (unsigned l = 0; l != NumElts; l += 8) {
4705 // 8 nodes per lane, but we only care about the first 4.
4706 for (unsigned i = 0; i < 4; ++i) {
4707 int Elt = N->getMaskElt(l+i);
4708 if (Elt < 0) continue;
4709 Elt &= 0x3; // only 2-bits
4710 Mask |= Elt << (i * 2);
4717 /// \brief Return the appropriate immediate to shuffle the specified
4718 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4719 /// VALIGN (if Interlane is true) instructions.
4720 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4722 MVT VT = SVOp->getSimpleValueType(0);
4723 unsigned EltSize = InterLane ? 1 :
4724 VT.getVectorElementType().getSizeInBits() >> 3;
4726 unsigned NumElts = VT.getVectorNumElements();
4727 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4728 unsigned NumLaneElts = NumElts/NumLanes;
4732 for (i = 0; i != NumElts; ++i) {
4733 Val = SVOp->getMaskElt(i);
4737 if (Val >= (int)NumElts)
4738 Val -= NumElts - NumLaneElts;
4740 assert(Val - i > 0 && "PALIGNR imm should be positive");
4741 return (Val - i) * EltSize;
4744 /// \brief Return the appropriate immediate to shuffle the specified
4745 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4746 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4747 return getShuffleAlignrImmediate(SVOp, false);
4750 /// \brief Return the appropriate immediate to shuffle the specified
4751 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4752 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4753 return getShuffleAlignrImmediate(SVOp, true);
4757 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4758 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4759 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4760 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4763 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4765 MVT VecVT = N->getOperand(0).getSimpleValueType();
4766 MVT ElVT = VecVT.getVectorElementType();
4768 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4769 return Index / NumElemsPerChunk;
4772 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4773 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4774 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4775 llvm_unreachable("Illegal insert subvector for VINSERT");
4778 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4780 MVT VecVT = N->getSimpleValueType(0);
4781 MVT ElVT = VecVT.getVectorElementType();
4783 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4784 return Index / NumElemsPerChunk;
4787 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4788 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4789 /// and VINSERTI128 instructions.
4790 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4791 return getExtractVEXTRACTImmediate(N, 128);
4794 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4795 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4796 /// and VINSERTI64x4 instructions.
4797 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4798 return getExtractVEXTRACTImmediate(N, 256);
4801 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4802 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4803 /// and VINSERTI128 instructions.
4804 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4805 return getInsertVINSERTImmediate(N, 128);
4808 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4809 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4810 /// and VINSERTI64x4 instructions.
4811 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4812 return getInsertVINSERTImmediate(N, 256);
4815 /// isZero - Returns true if Elt is a constant integer zero
4816 static bool isZero(SDValue V) {
4817 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4818 return C && C->isNullValue();
4821 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4823 bool X86::isZeroNode(SDValue Elt) {
4826 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4827 return CFP->getValueAPF().isPosZero();
4831 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4832 /// match movhlps. The lower half elements should come from upper half of
4833 /// V1 (and in order), and the upper half elements should come from the upper
4834 /// half of V2 (and in order).
4835 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4836 if (!VT.is128BitVector())
4838 if (VT.getVectorNumElements() != 4)
4840 for (unsigned i = 0, e = 2; i != e; ++i)
4841 if (!isUndefOrEqual(Mask[i], i+2))
4843 for (unsigned i = 2; i != 4; ++i)
4844 if (!isUndefOrEqual(Mask[i], i+4))
4849 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4850 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4852 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4853 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4855 N = N->getOperand(0).getNode();
4856 if (!ISD::isNON_EXTLoad(N))
4859 *LD = cast<LoadSDNode>(N);
4863 // Test whether the given value is a vector value which will be legalized
4865 static bool WillBeConstantPoolLoad(SDNode *N) {
4866 if (N->getOpcode() != ISD::BUILD_VECTOR)
4869 // Check for any non-constant elements.
4870 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4871 switch (N->getOperand(i).getNode()->getOpcode()) {
4873 case ISD::ConstantFP:
4880 // Vectors of all-zeros and all-ones are materialized with special
4881 // instructions rather than being loaded.
4882 return !ISD::isBuildVectorAllZeros(N) &&
4883 !ISD::isBuildVectorAllOnes(N);
4886 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4887 /// match movlp{s|d}. The lower half elements should come from lower half of
4888 /// V1 (and in order), and the upper half elements should come from the upper
4889 /// half of V2 (and in order). And since V1 will become the source of the
4890 /// MOVLP, it must be either a vector load or a scalar load to vector.
4891 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4892 ArrayRef<int> Mask, MVT VT) {
4893 if (!VT.is128BitVector())
4896 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4898 // Is V2 is a vector load, don't do this transformation. We will try to use
4899 // load folding shufps op.
4900 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4903 unsigned NumElems = VT.getVectorNumElements();
4905 if (NumElems != 2 && NumElems != 4)
4907 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4908 if (!isUndefOrEqual(Mask[i], i))
4910 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4911 if (!isUndefOrEqual(Mask[i], i+NumElems))
4916 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4917 /// to an zero vector.
4918 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4919 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4920 SDValue V1 = N->getOperand(0);
4921 SDValue V2 = N->getOperand(1);
4922 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4923 for (unsigned i = 0; i != NumElems; ++i) {
4924 int Idx = N->getMaskElt(i);
4925 if (Idx >= (int)NumElems) {
4926 unsigned Opc = V2.getOpcode();
4927 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4929 if (Opc != ISD::BUILD_VECTOR ||
4930 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4932 } else if (Idx >= 0) {
4933 unsigned Opc = V1.getOpcode();
4934 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4936 if (Opc != ISD::BUILD_VECTOR ||
4937 !X86::isZeroNode(V1.getOperand(Idx)))
4944 /// getZeroVector - Returns a vector of specified type with all zero elements.
4946 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4947 SelectionDAG &DAG, SDLoc dl) {
4948 assert(VT.isVector() && "Expected a vector type");
4950 // Always build SSE zero vectors as <4 x i32> bitcasted
4951 // to their dest type. This ensures they get CSE'd.
4953 if (VT.is128BitVector()) { // SSE
4954 if (Subtarget->hasSSE2()) { // SSE2
4955 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4956 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4958 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4959 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4961 } else if (VT.is256BitVector()) { // AVX
4962 if (Subtarget->hasInt256()) { // AVX2
4963 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4964 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4965 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4967 // 256-bit logic and arithmetic instructions in AVX are all
4968 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4969 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4970 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4971 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4973 } else if (VT.is512BitVector()) { // AVX-512
4974 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4975 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4976 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4977 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4978 } else if (VT.getScalarType() == MVT::i1) {
4979 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4980 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4981 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4982 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4984 llvm_unreachable("Unexpected vector type");
4986 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4989 /// getOnesVector - Returns a vector of specified type with all bits set.
4990 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4991 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4992 /// Then bitcast to their original type, ensuring they get CSE'd.
4993 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4995 assert(VT.isVector() && "Expected a vector type");
4997 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4999 if (VT.is256BitVector()) {
5000 if (HasInt256) { // AVX2
5001 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5002 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5004 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5005 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5007 } else if (VT.is128BitVector()) {
5008 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5010 llvm_unreachable("Unexpected vector type");
5012 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5015 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5016 /// that point to V2 points to its first element.
5017 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5018 for (unsigned i = 0; i != NumElems; ++i) {
5019 if (Mask[i] > (int)NumElems) {
5025 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5026 /// operation of specified width.
5027 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5029 unsigned NumElems = VT.getVectorNumElements();
5030 SmallVector<int, 8> Mask;
5031 Mask.push_back(NumElems);
5032 for (unsigned i = 1; i != NumElems; ++i)
5034 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5037 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5038 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5040 unsigned NumElems = VT.getVectorNumElements();
5041 SmallVector<int, 8> Mask;
5042 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5044 Mask.push_back(i + NumElems);
5046 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5049 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5050 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5052 unsigned NumElems = VT.getVectorNumElements();
5053 SmallVector<int, 8> Mask;
5054 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5055 Mask.push_back(i + Half);
5056 Mask.push_back(i + NumElems + Half);
5058 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5061 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5062 // a generic shuffle instruction because the target has no such instructions.
5063 // Generate shuffles which repeat i16 and i8 several times until they can be
5064 // represented by v4f32 and then be manipulated by target suported shuffles.
5065 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5066 MVT VT = V.getSimpleValueType();
5067 int NumElems = VT.getVectorNumElements();
5070 while (NumElems > 4) {
5071 if (EltNo < NumElems/2) {
5072 V = getUnpackl(DAG, dl, VT, V, V);
5074 V = getUnpackh(DAG, dl, VT, V, V);
5075 EltNo -= NumElems/2;
5082 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5083 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5084 MVT VT = V.getSimpleValueType();
5087 if (VT.is128BitVector()) {
5088 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5089 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5090 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5092 } else if (VT.is256BitVector()) {
5093 // To use VPERMILPS to splat scalars, the second half of indicies must
5094 // refer to the higher part, which is a duplication of the lower one,
5095 // because VPERMILPS can only handle in-lane permutations.
5096 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5097 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5099 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5100 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5103 llvm_unreachable("Vector size not supported");
5105 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5108 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5109 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5110 MVT SrcVT = SV->getSimpleValueType(0);
5111 SDValue V1 = SV->getOperand(0);
5114 int EltNo = SV->getSplatIndex();
5115 int NumElems = SrcVT.getVectorNumElements();
5116 bool Is256BitVec = SrcVT.is256BitVector();
5118 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5119 "Unknown how to promote splat for type");
5121 // Extract the 128-bit part containing the splat element and update
5122 // the splat element index when it refers to the higher register.
5124 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5125 if (EltNo >= NumElems/2)
5126 EltNo -= NumElems/2;
5129 // All i16 and i8 vector types can't be used directly by a generic shuffle
5130 // instruction because the target has no such instruction. Generate shuffles
5131 // which repeat i16 and i8 several times until they fit in i32, and then can
5132 // be manipulated by target suported shuffles.
5133 MVT EltVT = SrcVT.getVectorElementType();
5134 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5135 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5137 // Recreate the 256-bit vector and place the same 128-bit vector
5138 // into the low and high part. This is necessary because we want
5139 // to use VPERM* to shuffle the vectors
5141 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5144 return getLegalSplat(DAG, V1, EltNo);
5147 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5148 /// vector of zero or undef vector. This produces a shuffle where the low
5149 /// element of V2 is swizzled into the zero/undef vector, landing at element
5150 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5151 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5153 const X86Subtarget *Subtarget,
5154 SelectionDAG &DAG) {
5155 MVT VT = V2.getSimpleValueType();
5157 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5158 unsigned NumElems = VT.getVectorNumElements();
5159 SmallVector<int, 16> MaskVec;
5160 for (unsigned i = 0; i != NumElems; ++i)
5161 // If this is the insertion idx, put the low elt of V2 here.
5162 MaskVec.push_back(i == Idx ? NumElems : i);
5163 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5166 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5167 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5168 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5169 /// shuffles which use a single input multiple times, and in those cases it will
5170 /// adjust the mask to only have indices within that single input.
5171 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5172 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5173 unsigned NumElems = VT.getVectorNumElements();
5177 bool IsFakeUnary = false;
5178 switch(N->getOpcode()) {
5180 ImmN = N->getOperand(N->getNumOperands()-1);
5181 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5182 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5184 case X86ISD::UNPCKH:
5185 DecodeUNPCKHMask(VT, Mask);
5186 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5188 case X86ISD::UNPCKL:
5189 DecodeUNPCKLMask(VT, Mask);
5190 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5192 case X86ISD::MOVHLPS:
5193 DecodeMOVHLPSMask(NumElems, Mask);
5194 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5196 case X86ISD::MOVLHPS:
5197 DecodeMOVLHPSMask(NumElems, Mask);
5198 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5200 case X86ISD::PALIGNR:
5201 ImmN = N->getOperand(N->getNumOperands()-1);
5202 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5204 case X86ISD::PSHUFD:
5205 case X86ISD::VPERMILP:
5206 ImmN = N->getOperand(N->getNumOperands()-1);
5207 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5210 case X86ISD::PSHUFHW:
5211 ImmN = N->getOperand(N->getNumOperands()-1);
5212 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5215 case X86ISD::PSHUFLW:
5216 ImmN = N->getOperand(N->getNumOperands()-1);
5217 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5220 case X86ISD::PSHUFB: {
5222 SDValue MaskNode = N->getOperand(1);
5223 while (MaskNode->getOpcode() == ISD::BITCAST)
5224 MaskNode = MaskNode->getOperand(0);
5226 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5227 // If we have a build-vector, then things are easy.
5228 EVT VT = MaskNode.getValueType();
5229 assert(VT.isVector() &&
5230 "Can't produce a non-vector with a build_vector!");
5231 if (!VT.isInteger())
5234 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5236 SmallVector<uint64_t, 32> RawMask;
5237 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5238 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5241 APInt MaskElement = CN->getAPIntValue();
5243 // We now have to decode the element which could be any integer size and
5244 // extract each byte of it.
5245 for (int j = 0; j < NumBytesPerElement; ++j) {
5246 // Note that this is x86 and so always little endian: the low byte is
5247 // the first byte of the mask.
5248 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5249 MaskElement = MaskElement.lshr(8);
5252 DecodePSHUFBMask(RawMask, Mask);
5256 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5260 SDValue Ptr = MaskLoad->getBasePtr();
5261 if (Ptr->getOpcode() == X86ISD::Wrapper)
5262 Ptr = Ptr->getOperand(0);
5264 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5265 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5268 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5269 // FIXME: Support AVX-512 here.
5270 if (!C->getType()->isVectorTy() ||
5271 (C->getNumElements() != 16 && C->getNumElements() != 32))
5274 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5275 DecodePSHUFBMask(C, Mask);
5281 case X86ISD::VPERMI:
5282 ImmN = N->getOperand(N->getNumOperands()-1);
5283 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5287 case X86ISD::MOVSD: {
5288 // The index 0 always comes from the first element of the second source,
5289 // this is why MOVSS and MOVSD are used in the first place. The other
5290 // elements come from the other positions of the first source vector
5291 Mask.push_back(NumElems);
5292 for (unsigned i = 1; i != NumElems; ++i) {
5297 case X86ISD::VPERM2X128:
5298 ImmN = N->getOperand(N->getNumOperands()-1);
5299 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5300 if (Mask.empty()) return false;
5302 case X86ISD::MOVDDUP:
5303 case X86ISD::MOVLHPD:
5304 case X86ISD::MOVLPD:
5305 case X86ISD::MOVLPS:
5306 case X86ISD::MOVSHDUP:
5307 case X86ISD::MOVSLDUP:
5308 // Not yet implemented
5310 default: llvm_unreachable("unknown target shuffle node");
5313 // If we have a fake unary shuffle, the shuffle mask is spread across two
5314 // inputs that are actually the same node. Re-map the mask to always point
5315 // into the first input.
5318 if (M >= (int)Mask.size())
5324 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5325 /// element of the result of the vector shuffle.
5326 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5329 return SDValue(); // Limit search depth.
5331 SDValue V = SDValue(N, 0);
5332 EVT VT = V.getValueType();
5333 unsigned Opcode = V.getOpcode();
5335 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5336 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5337 int Elt = SV->getMaskElt(Index);
5340 return DAG.getUNDEF(VT.getVectorElementType());
5342 unsigned NumElems = VT.getVectorNumElements();
5343 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5344 : SV->getOperand(1);
5345 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5348 // Recurse into target specific vector shuffles to find scalars.
5349 if (isTargetShuffle(Opcode)) {
5350 MVT ShufVT = V.getSimpleValueType();
5351 unsigned NumElems = ShufVT.getVectorNumElements();
5352 SmallVector<int, 16> ShuffleMask;
5355 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5358 int Elt = ShuffleMask[Index];
5360 return DAG.getUNDEF(ShufVT.getVectorElementType());
5362 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5364 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5368 // Actual nodes that may contain scalar elements
5369 if (Opcode == ISD::BITCAST) {
5370 V = V.getOperand(0);
5371 EVT SrcVT = V.getValueType();
5372 unsigned NumElems = VT.getVectorNumElements();
5374 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5378 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5379 return (Index == 0) ? V.getOperand(0)
5380 : DAG.getUNDEF(VT.getVectorElementType());
5382 if (V.getOpcode() == ISD::BUILD_VECTOR)
5383 return V.getOperand(Index);
5388 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5389 /// shuffle operation which come from a consecutively from a zero. The
5390 /// search can start in two different directions, from left or right.
5391 /// We count undefs as zeros until PreferredNum is reached.
5392 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5393 unsigned NumElems, bool ZerosFromLeft,
5395 unsigned PreferredNum = -1U) {
5396 unsigned NumZeros = 0;
5397 for (unsigned i = 0; i != NumElems; ++i) {
5398 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5399 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5403 if (X86::isZeroNode(Elt))
5405 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5406 NumZeros = std::min(NumZeros + 1, PreferredNum);
5414 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5415 /// correspond consecutively to elements from one of the vector operands,
5416 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5418 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5419 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5420 unsigned NumElems, unsigned &OpNum) {
5421 bool SeenV1 = false;
5422 bool SeenV2 = false;
5424 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5425 int Idx = SVOp->getMaskElt(i);
5426 // Ignore undef indicies
5430 if (Idx < (int)NumElems)
5435 // Only accept consecutive elements from the same vector
5436 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5440 OpNum = SeenV1 ? 0 : 1;
5444 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5445 /// logical left shift of a vector.
5446 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5447 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5449 SVOp->getSimpleValueType(0).getVectorNumElements();
5450 unsigned NumZeros = getNumOfConsecutiveZeros(
5451 SVOp, NumElems, false /* check zeros from right */, DAG,
5452 SVOp->getMaskElt(0));
5458 // Considering the elements in the mask that are not consecutive zeros,
5459 // check if they consecutively come from only one of the source vectors.
5461 // V1 = {X, A, B, C} 0
5463 // vector_shuffle V1, V2 <1, 2, 3, X>
5465 if (!isShuffleMaskConsecutive(SVOp,
5466 0, // Mask Start Index
5467 NumElems-NumZeros, // Mask End Index(exclusive)
5468 NumZeros, // Where to start looking in the src vector
5469 NumElems, // Number of elements in vector
5470 OpSrc)) // Which source operand ?
5475 ShVal = SVOp->getOperand(OpSrc);
5479 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5480 /// logical left shift of a vector.
5481 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5482 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5484 SVOp->getSimpleValueType(0).getVectorNumElements();
5485 unsigned NumZeros = getNumOfConsecutiveZeros(
5486 SVOp, NumElems, true /* check zeros from left */, DAG,
5487 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5493 // Considering the elements in the mask that are not consecutive zeros,
5494 // check if they consecutively come from only one of the source vectors.
5496 // 0 { A, B, X, X } = V2
5498 // vector_shuffle V1, V2 <X, X, 4, 5>
5500 if (!isShuffleMaskConsecutive(SVOp,
5501 NumZeros, // Mask Start Index
5502 NumElems, // Mask End Index(exclusive)
5503 0, // Where to start looking in the src vector
5504 NumElems, // Number of elements in vector
5505 OpSrc)) // Which source operand ?
5510 ShVal = SVOp->getOperand(OpSrc);
5514 /// isVectorShift - Returns true if the shuffle can be implemented as a
5515 /// logical left or right shift of a vector.
5516 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5517 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5518 // Although the logic below support any bitwidth size, there are no
5519 // shift instructions which handle more than 128-bit vectors.
5520 if (!SVOp->getSimpleValueType(0).is128BitVector())
5523 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5524 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5530 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5532 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5533 unsigned NumNonZero, unsigned NumZero,
5535 const X86Subtarget* Subtarget,
5536 const TargetLowering &TLI) {
5543 for (unsigned i = 0; i < 16; ++i) {
5544 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5545 if (ThisIsNonZero && First) {
5547 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5549 V = DAG.getUNDEF(MVT::v8i16);
5554 SDValue ThisElt, LastElt;
5555 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5556 if (LastIsNonZero) {
5557 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5558 MVT::i16, Op.getOperand(i-1));
5560 if (ThisIsNonZero) {
5561 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5562 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5563 ThisElt, DAG.getConstant(8, MVT::i8));
5565 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5569 if (ThisElt.getNode())
5570 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5571 DAG.getIntPtrConstant(i/2));
5575 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5578 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5580 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5581 unsigned NumNonZero, unsigned NumZero,
5583 const X86Subtarget* Subtarget,
5584 const TargetLowering &TLI) {
5591 for (unsigned i = 0; i < 8; ++i) {
5592 bool isNonZero = (NonZeros & (1 << i)) != 0;
5596 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5598 V = DAG.getUNDEF(MVT::v8i16);
5601 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5602 MVT::v8i16, V, Op.getOperand(i),
5603 DAG.getIntPtrConstant(i));
5610 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5611 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5612 unsigned NonZeros, unsigned NumNonZero,
5613 unsigned NumZero, SelectionDAG &DAG,
5614 const X86Subtarget *Subtarget,
5615 const TargetLowering &TLI) {
5616 // We know there's at least one non-zero element
5617 unsigned FirstNonZeroIdx = 0;
5618 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5619 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5620 X86::isZeroNode(FirstNonZero)) {
5622 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5625 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5626 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5629 SDValue V = FirstNonZero.getOperand(0);
5630 MVT VVT = V.getSimpleValueType();
5631 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5634 unsigned FirstNonZeroDst =
5635 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5636 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5637 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5638 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5640 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5641 SDValue Elem = Op.getOperand(Idx);
5642 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5645 // TODO: What else can be here? Deal with it.
5646 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5649 // TODO: Some optimizations are still possible here
5650 // ex: Getting one element from a vector, and the rest from another.
5651 if (Elem.getOperand(0) != V)
5654 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5657 else if (IncorrectIdx == -1U) {
5661 // There was already one element with an incorrect index.
5662 // We can't optimize this case to an insertps.
5666 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5668 EVT VT = Op.getSimpleValueType();
5669 unsigned ElementMoveMask = 0;
5670 if (IncorrectIdx == -1U)
5671 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5673 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5675 SDValue InsertpsMask =
5676 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5677 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5683 /// getVShift - Return a vector logical shift node.
5685 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5686 unsigned NumBits, SelectionDAG &DAG,
5687 const TargetLowering &TLI, SDLoc dl) {
5688 assert(VT.is128BitVector() && "Unknown type for VShift");
5689 EVT ShVT = MVT::v2i64;
5690 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5691 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5692 return DAG.getNode(ISD::BITCAST, dl, VT,
5693 DAG.getNode(Opc, dl, ShVT, SrcOp,
5694 DAG.getConstant(NumBits,
5695 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5699 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5701 // Check if the scalar load can be widened into a vector load. And if
5702 // the address is "base + cst" see if the cst can be "absorbed" into
5703 // the shuffle mask.
5704 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5705 SDValue Ptr = LD->getBasePtr();
5706 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5708 EVT PVT = LD->getValueType(0);
5709 if (PVT != MVT::i32 && PVT != MVT::f32)
5714 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5715 FI = FINode->getIndex();
5717 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5718 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5719 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5720 Offset = Ptr.getConstantOperandVal(1);
5721 Ptr = Ptr.getOperand(0);
5726 // FIXME: 256-bit vector instructions don't require a strict alignment,
5727 // improve this code to support it better.
5728 unsigned RequiredAlign = VT.getSizeInBits()/8;
5729 SDValue Chain = LD->getChain();
5730 // Make sure the stack object alignment is at least 16 or 32.
5731 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5732 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5733 if (MFI->isFixedObjectIndex(FI)) {
5734 // Can't change the alignment. FIXME: It's possible to compute
5735 // the exact stack offset and reference FI + adjust offset instead.
5736 // If someone *really* cares about this. That's the way to implement it.
5739 MFI->setObjectAlignment(FI, RequiredAlign);
5743 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5744 // Ptr + (Offset & ~15).
5747 if ((Offset % RequiredAlign) & 3)
5749 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5751 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5752 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5754 int EltNo = (Offset - StartOffset) >> 2;
5755 unsigned NumElems = VT.getVectorNumElements();
5757 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5758 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5759 LD->getPointerInfo().getWithOffset(StartOffset),
5760 false, false, false, 0);
5762 SmallVector<int, 8> Mask;
5763 for (unsigned i = 0; i != NumElems; ++i)
5764 Mask.push_back(EltNo);
5766 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5772 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5773 /// vector of type 'VT', see if the elements can be replaced by a single large
5774 /// load which has the same value as a build_vector whose operands are 'elts'.
5776 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5778 /// FIXME: we'd also like to handle the case where the last elements are zero
5779 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5780 /// There's even a handy isZeroNode for that purpose.
5781 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5782 SDLoc &DL, SelectionDAG &DAG,
5783 bool isAfterLegalize) {
5784 EVT EltVT = VT.getVectorElementType();
5785 unsigned NumElems = Elts.size();
5787 LoadSDNode *LDBase = nullptr;
5788 unsigned LastLoadedElt = -1U;
5790 // For each element in the initializer, see if we've found a load or an undef.
5791 // If we don't find an initial load element, or later load elements are
5792 // non-consecutive, bail out.
5793 for (unsigned i = 0; i < NumElems; ++i) {
5794 SDValue Elt = Elts[i];
5796 if (!Elt.getNode() ||
5797 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5800 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5802 LDBase = cast<LoadSDNode>(Elt.getNode());
5806 if (Elt.getOpcode() == ISD::UNDEF)
5809 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5810 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5815 // If we have found an entire vector of loads and undefs, then return a large
5816 // load of the entire vector width starting at the base pointer. If we found
5817 // consecutive loads for the low half, generate a vzext_load node.
5818 if (LastLoadedElt == NumElems - 1) {
5820 if (isAfterLegalize &&
5821 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5824 SDValue NewLd = SDValue();
5826 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5827 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5828 LDBase->getPointerInfo(),
5829 LDBase->isVolatile(), LDBase->isNonTemporal(),
5830 LDBase->isInvariant(), 0);
5831 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5832 LDBase->getPointerInfo(),
5833 LDBase->isVolatile(), LDBase->isNonTemporal(),
5834 LDBase->isInvariant(), LDBase->getAlignment());
5836 if (LDBase->hasAnyUseOfValue(1)) {
5837 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5839 SDValue(NewLd.getNode(), 1));
5840 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5841 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5842 SDValue(NewLd.getNode(), 1));
5847 if (NumElems == 4 && LastLoadedElt == 1 &&
5848 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5849 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5850 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5852 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5853 LDBase->getPointerInfo(),
5854 LDBase->getAlignment(),
5855 false/*isVolatile*/, true/*ReadMem*/,
5858 // Make sure the newly-created LOAD is in the same position as LDBase in
5859 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5860 // update uses of LDBase's output chain to use the TokenFactor.
5861 if (LDBase->hasAnyUseOfValue(1)) {
5862 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5863 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5864 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5865 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5866 SDValue(ResNode.getNode(), 1));
5869 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5874 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5875 /// to generate a splat value for the following cases:
5876 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5877 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5878 /// a scalar load, or a constant.
5879 /// The VBROADCAST node is returned when a pattern is found,
5880 /// or SDValue() otherwise.
5881 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5882 SelectionDAG &DAG) {
5883 if (!Subtarget->hasFp256())
5886 MVT VT = Op.getSimpleValueType();
5889 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5890 "Unsupported vector type for broadcast.");
5895 switch (Op.getOpcode()) {
5897 // Unknown pattern found.
5900 case ISD::BUILD_VECTOR: {
5901 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5902 BitVector UndefElements;
5903 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5905 // We need a splat of a single value to use broadcast, and it doesn't
5906 // make any sense if the value is only in one element of the vector.
5907 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5911 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5912 Ld.getOpcode() == ISD::ConstantFP);
5914 // Make sure that all of the users of a non-constant load are from the
5915 // BUILD_VECTOR node.
5916 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5921 case ISD::VECTOR_SHUFFLE: {
5922 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5924 // Shuffles must have a splat mask where the first element is
5926 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5929 SDValue Sc = Op.getOperand(0);
5930 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5931 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5933 if (!Subtarget->hasInt256())
5936 // Use the register form of the broadcast instruction available on AVX2.
5937 if (VT.getSizeInBits() >= 256)
5938 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5939 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5942 Ld = Sc.getOperand(0);
5943 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5944 Ld.getOpcode() == ISD::ConstantFP);
5946 // The scalar_to_vector node and the suspected
5947 // load node must have exactly one user.
5948 // Constants may have multiple users.
5950 // AVX-512 has register version of the broadcast
5951 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5952 Ld.getValueType().getSizeInBits() >= 32;
5953 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5960 bool IsGE256 = (VT.getSizeInBits() >= 256);
5962 // Handle the broadcasting a single constant scalar from the constant pool
5963 // into a vector. On Sandybridge it is still better to load a constant vector
5964 // from the constant pool and not to broadcast it from a scalar.
5965 if (ConstSplatVal && Subtarget->hasInt256()) {
5966 EVT CVT = Ld.getValueType();
5967 assert(!CVT.isVector() && "Must not broadcast a vector type");
5968 unsigned ScalarSize = CVT.getSizeInBits();
5970 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5971 const Constant *C = nullptr;
5972 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5973 C = CI->getConstantIntValue();
5974 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5975 C = CF->getConstantFPValue();
5977 assert(C && "Invalid constant type");
5979 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5980 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5981 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5982 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5983 MachinePointerInfo::getConstantPool(),
5984 false, false, false, Alignment);
5986 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5990 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5991 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5993 // Handle AVX2 in-register broadcasts.
5994 if (!IsLoad && Subtarget->hasInt256() &&
5995 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5996 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5998 // The scalar source must be a normal load.
6002 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6003 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6005 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6006 // double since there is no vbroadcastsd xmm
6007 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6008 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6009 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6012 // Unsupported broadcast.
6016 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6017 /// underlying vector and index.
6019 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6021 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6023 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6024 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6027 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6029 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6031 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6032 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6035 // In this case the vector is the extract_subvector expression and the index
6036 // is 2, as specified by the shuffle.
6037 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6038 SDValue ShuffleVec = SVOp->getOperand(0);
6039 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6040 assert(ShuffleVecVT.getVectorElementType() ==
6041 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6043 int ShuffleIdx = SVOp->getMaskElt(Idx);
6044 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6045 ExtractedFromVec = ShuffleVec;
6051 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6052 MVT VT = Op.getSimpleValueType();
6054 // Skip if insert_vec_elt is not supported.
6055 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6056 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6060 unsigned NumElems = Op.getNumOperands();
6064 SmallVector<unsigned, 4> InsertIndices;
6065 SmallVector<int, 8> Mask(NumElems, -1);
6067 for (unsigned i = 0; i != NumElems; ++i) {
6068 unsigned Opc = Op.getOperand(i).getOpcode();
6070 if (Opc == ISD::UNDEF)
6073 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6074 // Quit if more than 1 elements need inserting.
6075 if (InsertIndices.size() > 1)
6078 InsertIndices.push_back(i);
6082 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6083 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6084 // Quit if non-constant index.
6085 if (!isa<ConstantSDNode>(ExtIdx))
6087 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6089 // Quit if extracted from vector of different type.
6090 if (ExtractedFromVec.getValueType() != VT)
6093 if (!VecIn1.getNode())
6094 VecIn1 = ExtractedFromVec;
6095 else if (VecIn1 != ExtractedFromVec) {
6096 if (!VecIn2.getNode())
6097 VecIn2 = ExtractedFromVec;
6098 else if (VecIn2 != ExtractedFromVec)
6099 // Quit if more than 2 vectors to shuffle
6103 if (ExtractedFromVec == VecIn1)
6105 else if (ExtractedFromVec == VecIn2)
6106 Mask[i] = Idx + NumElems;
6109 if (!VecIn1.getNode())
6112 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6113 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6114 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6115 unsigned Idx = InsertIndices[i];
6116 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6117 DAG.getIntPtrConstant(Idx));
6123 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6125 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6127 MVT VT = Op.getSimpleValueType();
6128 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6129 "Unexpected type in LowerBUILD_VECTORvXi1!");
6132 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6133 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6134 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6135 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6138 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6139 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6140 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6141 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6144 bool AllContants = true;
6145 uint64_t Immediate = 0;
6146 int NonConstIdx = -1;
6147 bool IsSplat = true;
6148 unsigned NumNonConsts = 0;
6149 unsigned NumConsts = 0;
6150 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6151 SDValue In = Op.getOperand(idx);
6152 if (In.getOpcode() == ISD::UNDEF)
6154 if (!isa<ConstantSDNode>(In)) {
6155 AllContants = false;
6161 if (cast<ConstantSDNode>(In)->getZExtValue())
6162 Immediate |= (1ULL << idx);
6164 if (In != Op.getOperand(0))
6169 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6170 DAG.getConstant(Immediate, MVT::i16));
6171 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6172 DAG.getIntPtrConstant(0));
6175 if (NumNonConsts == 1 && NonConstIdx != 0) {
6178 SDValue VecAsImm = DAG.getConstant(Immediate,
6179 MVT::getIntegerVT(VT.getSizeInBits()));
6180 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6183 DstVec = DAG.getUNDEF(VT);
6184 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6185 Op.getOperand(NonConstIdx),
6186 DAG.getIntPtrConstant(NonConstIdx));
6188 if (!IsSplat && (NonConstIdx != 0))
6189 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6190 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6193 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6194 DAG.getConstant(-1, SelectVT),
6195 DAG.getConstant(0, SelectVT));
6197 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6198 DAG.getConstant((Immediate | 1), SelectVT),
6199 DAG.getConstant(Immediate, SelectVT));
6200 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6203 /// \brief Return true if \p N implements a horizontal binop and return the
6204 /// operands for the horizontal binop into V0 and V1.
6206 /// This is a helper function of PerformBUILD_VECTORCombine.
6207 /// This function checks that the build_vector \p N in input implements a
6208 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6209 /// operation to match.
6210 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6211 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6212 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6215 /// This function only analyzes elements of \p N whose indices are
6216 /// in range [BaseIdx, LastIdx).
6217 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6219 unsigned BaseIdx, unsigned LastIdx,
6220 SDValue &V0, SDValue &V1) {
6221 EVT VT = N->getValueType(0);
6223 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6224 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6225 "Invalid Vector in input!");
6227 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6228 bool CanFold = true;
6229 unsigned ExpectedVExtractIdx = BaseIdx;
6230 unsigned NumElts = LastIdx - BaseIdx;
6231 V0 = DAG.getUNDEF(VT);
6232 V1 = DAG.getUNDEF(VT);
6234 // Check if N implements a horizontal binop.
6235 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6236 SDValue Op = N->getOperand(i + BaseIdx);
6239 if (Op->getOpcode() == ISD::UNDEF) {
6240 // Update the expected vector extract index.
6241 if (i * 2 == NumElts)
6242 ExpectedVExtractIdx = BaseIdx;
6243 ExpectedVExtractIdx += 2;
6247 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6252 SDValue Op0 = Op.getOperand(0);
6253 SDValue Op1 = Op.getOperand(1);
6255 // Try to match the following pattern:
6256 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6257 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6258 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6259 Op0.getOperand(0) == Op1.getOperand(0) &&
6260 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6261 isa<ConstantSDNode>(Op1.getOperand(1)));
6265 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6266 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6268 if (i * 2 < NumElts) {
6269 if (V0.getOpcode() == ISD::UNDEF)
6270 V0 = Op0.getOperand(0);
6272 if (V1.getOpcode() == ISD::UNDEF)
6273 V1 = Op0.getOperand(0);
6274 if (i * 2 == NumElts)
6275 ExpectedVExtractIdx = BaseIdx;
6278 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6279 if (I0 == ExpectedVExtractIdx)
6280 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6281 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6282 // Try to match the following dag sequence:
6283 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6284 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6288 ExpectedVExtractIdx += 2;
6294 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6295 /// a concat_vector.
6297 /// This is a helper function of PerformBUILD_VECTORCombine.
6298 /// This function expects two 256-bit vectors called V0 and V1.
6299 /// At first, each vector is split into two separate 128-bit vectors.
6300 /// Then, the resulting 128-bit vectors are used to implement two
6301 /// horizontal binary operations.
6303 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6305 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6306 /// the two new horizontal binop.
6307 /// When Mode is set, the first horizontal binop dag node would take as input
6308 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6309 /// horizontal binop dag node would take as input the lower 128-bit of V1
6310 /// and the upper 128-bit of V1.
6312 /// HADD V0_LO, V0_HI
6313 /// HADD V1_LO, V1_HI
6315 /// Otherwise, the first horizontal binop dag node takes as input the lower
6316 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6317 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6319 /// HADD V0_LO, V1_LO
6320 /// HADD V0_HI, V1_HI
6322 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6323 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6324 /// the upper 128-bits of the result.
6325 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6326 SDLoc DL, SelectionDAG &DAG,
6327 unsigned X86Opcode, bool Mode,
6328 bool isUndefLO, bool isUndefHI) {
6329 EVT VT = V0.getValueType();
6330 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6331 "Invalid nodes in input!");
6333 unsigned NumElts = VT.getVectorNumElements();
6334 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6335 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6336 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6337 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6338 EVT NewVT = V0_LO.getValueType();
6340 SDValue LO = DAG.getUNDEF(NewVT);
6341 SDValue HI = DAG.getUNDEF(NewVT);
6344 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6345 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6346 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6347 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6348 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6350 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6351 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6352 V1_LO->getOpcode() != ISD::UNDEF))
6353 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6355 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6356 V1_HI->getOpcode() != ISD::UNDEF))
6357 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6360 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6363 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6364 /// sequence of 'vadd + vsub + blendi'.
6365 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6366 const X86Subtarget *Subtarget) {
6368 EVT VT = BV->getValueType(0);
6369 unsigned NumElts = VT.getVectorNumElements();
6370 SDValue InVec0 = DAG.getUNDEF(VT);
6371 SDValue InVec1 = DAG.getUNDEF(VT);
6373 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6374 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6376 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6378 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6381 // Odd-numbered elements in the input build vector are obtained from
6382 // adding two integer/float elements.
6383 // Even-numbered elements in the input build vector are obtained from
6384 // subtracting two integer/float elements.
6385 unsigned ExpectedOpcode = ISD::FSUB;
6386 unsigned NextExpectedOpcode = ISD::FADD;
6387 bool AddFound = false;
6388 bool SubFound = false;
6390 for (unsigned i = 0, e = NumElts; i != e; i++) {
6391 SDValue Op = BV->getOperand(i);
6393 // Skip 'undef' values.
6394 unsigned Opcode = Op.getOpcode();
6395 if (Opcode == ISD::UNDEF) {
6396 std::swap(ExpectedOpcode, NextExpectedOpcode);
6400 // Early exit if we found an unexpected opcode.
6401 if (Opcode != ExpectedOpcode)
6404 SDValue Op0 = Op.getOperand(0);
6405 SDValue Op1 = Op.getOperand(1);
6407 // Try to match the following pattern:
6408 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6409 // Early exit if we cannot match that sequence.
6410 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6411 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6412 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6413 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6414 Op0.getOperand(1) != Op1.getOperand(1))
6417 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6421 // We found a valid add/sub node. Update the information accordingly.
6427 // Update InVec0 and InVec1.
6428 if (InVec0.getOpcode() == ISD::UNDEF)
6429 InVec0 = Op0.getOperand(0);
6430 if (InVec1.getOpcode() == ISD::UNDEF)
6431 InVec1 = Op1.getOperand(0);
6433 // Make sure that operands in input to each add/sub node always
6434 // come from a same pair of vectors.
6435 if (InVec0 != Op0.getOperand(0)) {
6436 if (ExpectedOpcode == ISD::FSUB)
6439 // FADD is commutable. Try to commute the operands
6440 // and then test again.
6441 std::swap(Op0, Op1);
6442 if (InVec0 != Op0.getOperand(0))
6446 if (InVec1 != Op1.getOperand(0))
6449 // Update the pair of expected opcodes.
6450 std::swap(ExpectedOpcode, NextExpectedOpcode);
6453 // Don't try to fold this build_vector into a VSELECT if it has
6454 // too many UNDEF operands.
6455 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6456 InVec1.getOpcode() != ISD::UNDEF) {
6457 // Emit a sequence of vector add and sub followed by a VSELECT.
6458 // The new VSELECT will be lowered into a BLENDI.
6459 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6460 // and emit a single ADDSUB instruction.
6461 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6462 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6464 // Construct the VSELECT mask.
6465 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6466 EVT SVT = MaskVT.getVectorElementType();
6467 unsigned SVTBits = SVT.getSizeInBits();
6468 SmallVector<SDValue, 8> Ops;
6470 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6471 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6472 APInt::getAllOnesValue(SVTBits);
6473 SDValue Constant = DAG.getConstant(Value, SVT);
6474 Ops.push_back(Constant);
6477 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6478 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6484 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6485 const X86Subtarget *Subtarget) {
6487 EVT VT = N->getValueType(0);
6488 unsigned NumElts = VT.getVectorNumElements();
6489 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6490 SDValue InVec0, InVec1;
6492 // Try to match an ADDSUB.
6493 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6494 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6495 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6496 if (Value.getNode())
6500 // Try to match horizontal ADD/SUB.
6501 unsigned NumUndefsLO = 0;
6502 unsigned NumUndefsHI = 0;
6503 unsigned Half = NumElts/2;
6505 // Count the number of UNDEF operands in the build_vector in input.
6506 for (unsigned i = 0, e = Half; i != e; ++i)
6507 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6510 for (unsigned i = Half, e = NumElts; i != e; ++i)
6511 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6514 // Early exit if this is either a build_vector of all UNDEFs or all the
6515 // operands but one are UNDEF.
6516 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6519 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6520 // Try to match an SSE3 float HADD/HSUB.
6521 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6522 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6524 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6525 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6526 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6527 // Try to match an SSSE3 integer HADD/HSUB.
6528 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6529 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6531 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6532 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6535 if (!Subtarget->hasAVX())
6538 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6539 // Try to match an AVX horizontal add/sub of packed single/double
6540 // precision floating point values from 256-bit vectors.
6541 SDValue InVec2, InVec3;
6542 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6543 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6544 ((InVec0.getOpcode() == ISD::UNDEF ||
6545 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6546 ((InVec1.getOpcode() == ISD::UNDEF ||
6547 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6548 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6550 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6551 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6552 ((InVec0.getOpcode() == ISD::UNDEF ||
6553 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6554 ((InVec1.getOpcode() == ISD::UNDEF ||
6555 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6556 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6557 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6558 // Try to match an AVX2 horizontal add/sub of signed integers.
6559 SDValue InVec2, InVec3;
6561 bool CanFold = true;
6563 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6564 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6565 ((InVec0.getOpcode() == ISD::UNDEF ||
6566 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6567 ((InVec1.getOpcode() == ISD::UNDEF ||
6568 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6569 X86Opcode = X86ISD::HADD;
6570 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6571 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6572 ((InVec0.getOpcode() == ISD::UNDEF ||
6573 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6574 ((InVec1.getOpcode() == ISD::UNDEF ||
6575 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6576 X86Opcode = X86ISD::HSUB;
6581 // Fold this build_vector into a single horizontal add/sub.
6582 // Do this only if the target has AVX2.
6583 if (Subtarget->hasAVX2())
6584 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6586 // Do not try to expand this build_vector into a pair of horizontal
6587 // add/sub if we can emit a pair of scalar add/sub.
6588 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6591 // Convert this build_vector into a pair of horizontal binop followed by
6593 bool isUndefLO = NumUndefsLO == Half;
6594 bool isUndefHI = NumUndefsHI == Half;
6595 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6596 isUndefLO, isUndefHI);
6600 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6601 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6603 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6604 X86Opcode = X86ISD::HADD;
6605 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6606 X86Opcode = X86ISD::HSUB;
6607 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6608 X86Opcode = X86ISD::FHADD;
6609 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6610 X86Opcode = X86ISD::FHSUB;
6614 // Don't try to expand this build_vector into a pair of horizontal add/sub
6615 // if we can simply emit a pair of scalar add/sub.
6616 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6619 // Convert this build_vector into two horizontal add/sub followed by
6621 bool isUndefLO = NumUndefsLO == Half;
6622 bool isUndefHI = NumUndefsHI == Half;
6623 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6624 isUndefLO, isUndefHI);
6631 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6634 MVT VT = Op.getSimpleValueType();
6635 MVT ExtVT = VT.getVectorElementType();
6636 unsigned NumElems = Op.getNumOperands();
6638 // Generate vectors for predicate vectors.
6639 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6640 return LowerBUILD_VECTORvXi1(Op, DAG);
6642 // Vectors containing all zeros can be matched by pxor and xorps later
6643 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6644 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6645 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6646 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6649 return getZeroVector(VT, Subtarget, DAG, dl);
6652 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6653 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6654 // vpcmpeqd on 256-bit vectors.
6655 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6656 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6659 if (!VT.is512BitVector())
6660 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6663 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6664 if (Broadcast.getNode())
6667 unsigned EVTBits = ExtVT.getSizeInBits();
6669 unsigned NumZero = 0;
6670 unsigned NumNonZero = 0;
6671 unsigned NonZeros = 0;
6672 bool IsAllConstants = true;
6673 SmallSet<SDValue, 8> Values;
6674 for (unsigned i = 0; i < NumElems; ++i) {
6675 SDValue Elt = Op.getOperand(i);
6676 if (Elt.getOpcode() == ISD::UNDEF)
6679 if (Elt.getOpcode() != ISD::Constant &&
6680 Elt.getOpcode() != ISD::ConstantFP)
6681 IsAllConstants = false;
6682 if (X86::isZeroNode(Elt))
6685 NonZeros |= (1 << i);
6690 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6691 if (NumNonZero == 0)
6692 return DAG.getUNDEF(VT);
6694 // Special case for single non-zero, non-undef, element.
6695 if (NumNonZero == 1) {
6696 unsigned Idx = countTrailingZeros(NonZeros);
6697 SDValue Item = Op.getOperand(Idx);
6699 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6700 // the value are obviously zero, truncate the value to i32 and do the
6701 // insertion that way. Only do this if the value is non-constant or if the
6702 // value is a constant being inserted into element 0. It is cheaper to do
6703 // a constant pool load than it is to do a movd + shuffle.
6704 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6705 (!IsAllConstants || Idx == 0)) {
6706 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6708 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6709 EVT VecVT = MVT::v4i32;
6710 unsigned VecElts = 4;
6712 // Truncate the value (which may itself be a constant) to i32, and
6713 // convert it to a vector with movd (S2V+shuffle to zero extend).
6714 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6715 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6716 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6718 // Now we have our 32-bit value zero extended in the low element of
6719 // a vector. If Idx != 0, swizzle it into place.
6721 SmallVector<int, 4> Mask;
6722 Mask.push_back(Idx);
6723 for (unsigned i = 1; i != VecElts; ++i)
6725 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6728 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6732 // If we have a constant or non-constant insertion into the low element of
6733 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6734 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6735 // depending on what the source datatype is.
6738 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6740 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6741 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6742 if (VT.is256BitVector() || VT.is512BitVector()) {
6743 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6744 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6745 Item, DAG.getIntPtrConstant(0));
6747 assert(VT.is128BitVector() && "Expected an SSE value type!");
6748 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6749 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6750 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6753 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6754 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6755 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6756 if (VT.is256BitVector()) {
6757 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6758 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6760 assert(VT.is128BitVector() && "Expected an SSE value type!");
6761 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6763 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6767 // Is it a vector logical left shift?
6768 if (NumElems == 2 && Idx == 1 &&
6769 X86::isZeroNode(Op.getOperand(0)) &&
6770 !X86::isZeroNode(Op.getOperand(1))) {
6771 unsigned NumBits = VT.getSizeInBits();
6772 return getVShift(true, VT,
6773 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6774 VT, Op.getOperand(1)),
6775 NumBits/2, DAG, *this, dl);
6778 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6781 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6782 // is a non-constant being inserted into an element other than the low one,
6783 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6784 // movd/movss) to move this into the low element, then shuffle it into
6786 if (EVTBits == 32) {
6787 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6789 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6790 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6791 SmallVector<int, 8> MaskVec;
6792 for (unsigned i = 0; i != NumElems; ++i)
6793 MaskVec.push_back(i == Idx ? 0 : 1);
6794 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6798 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6799 if (Values.size() == 1) {
6800 if (EVTBits == 32) {
6801 // Instead of a shuffle like this:
6802 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6803 // Check if it's possible to issue this instead.
6804 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6805 unsigned Idx = countTrailingZeros(NonZeros);
6806 SDValue Item = Op.getOperand(Idx);
6807 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6808 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6813 // A vector full of immediates; various special cases are already
6814 // handled, so this is best done with a single constant-pool load.
6818 // For AVX-length vectors, build the individual 128-bit pieces and use
6819 // shuffles to put them in place.
6820 if (VT.is256BitVector() || VT.is512BitVector()) {
6821 SmallVector<SDValue, 64> V;
6822 for (unsigned i = 0; i != NumElems; ++i)
6823 V.push_back(Op.getOperand(i));
6825 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6827 // Build both the lower and upper subvector.
6828 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6829 makeArrayRef(&V[0], NumElems/2));
6830 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6831 makeArrayRef(&V[NumElems / 2], NumElems/2));
6833 // Recreate the wider vector with the lower and upper part.
6834 if (VT.is256BitVector())
6835 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6836 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6839 // Let legalizer expand 2-wide build_vectors.
6840 if (EVTBits == 64) {
6841 if (NumNonZero == 1) {
6842 // One half is zero or undef.
6843 unsigned Idx = countTrailingZeros(NonZeros);
6844 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6845 Op.getOperand(Idx));
6846 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6851 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6852 if (EVTBits == 8 && NumElems == 16) {
6853 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6855 if (V.getNode()) return V;
6858 if (EVTBits == 16 && NumElems == 8) {
6859 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6861 if (V.getNode()) return V;
6864 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6865 if (EVTBits == 32 && NumElems == 4) {
6866 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6867 NumZero, DAG, Subtarget, *this);
6872 // If element VT is == 32 bits, turn it into a number of shuffles.
6873 SmallVector<SDValue, 8> V(NumElems);
6874 if (NumElems == 4 && NumZero > 0) {
6875 for (unsigned i = 0; i < 4; ++i) {
6876 bool isZero = !(NonZeros & (1 << i));
6878 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6880 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6883 for (unsigned i = 0; i < 2; ++i) {
6884 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6887 V[i] = V[i*2]; // Must be a zero vector.
6890 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6893 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6896 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6901 bool Reverse1 = (NonZeros & 0x3) == 2;
6902 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6906 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6907 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6909 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6912 if (Values.size() > 1 && VT.is128BitVector()) {
6913 // Check for a build vector of consecutive loads.
6914 for (unsigned i = 0; i < NumElems; ++i)
6915 V[i] = Op.getOperand(i);
6917 // Check for elements which are consecutive loads.
6918 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6922 // Check for a build vector from mostly shuffle plus few inserting.
6923 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6927 // For SSE 4.1, use insertps to put the high elements into the low element.
6928 if (getSubtarget()->hasSSE41()) {
6930 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6931 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6933 Result = DAG.getUNDEF(VT);
6935 for (unsigned i = 1; i < NumElems; ++i) {
6936 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6937 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6938 Op.getOperand(i), DAG.getIntPtrConstant(i));
6943 // Otherwise, expand into a number of unpckl*, start by extending each of
6944 // our (non-undef) elements to the full vector width with the element in the
6945 // bottom slot of the vector (which generates no code for SSE).
6946 for (unsigned i = 0; i < NumElems; ++i) {
6947 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6948 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6950 V[i] = DAG.getUNDEF(VT);
6953 // Next, we iteratively mix elements, e.g. for v4f32:
6954 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6955 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6956 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6957 unsigned EltStride = NumElems >> 1;
6958 while (EltStride != 0) {
6959 for (unsigned i = 0; i < EltStride; ++i) {
6960 // If V[i+EltStride] is undef and this is the first round of mixing,
6961 // then it is safe to just drop this shuffle: V[i] is already in the
6962 // right place, the one element (since it's the first round) being
6963 // inserted as undef can be dropped. This isn't safe for successive
6964 // rounds because they will permute elements within both vectors.
6965 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6966 EltStride == NumElems/2)
6969 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6978 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6979 // to create 256-bit vectors from two other 128-bit ones.
6980 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6982 MVT ResVT = Op.getSimpleValueType();
6984 assert((ResVT.is256BitVector() ||
6985 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6987 SDValue V1 = Op.getOperand(0);
6988 SDValue V2 = Op.getOperand(1);
6989 unsigned NumElems = ResVT.getVectorNumElements();
6990 if(ResVT.is256BitVector())
6991 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6993 if (Op.getNumOperands() == 4) {
6994 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6995 ResVT.getVectorNumElements()/2);
6996 SDValue V3 = Op.getOperand(2);
6997 SDValue V4 = Op.getOperand(3);
6998 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6999 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7001 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7004 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7005 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7006 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7007 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7008 Op.getNumOperands() == 4)));
7010 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7011 // from two other 128-bit ones.
7013 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7014 return LowerAVXCONCAT_VECTORS(Op, DAG);
7018 //===----------------------------------------------------------------------===//
7019 // Vector shuffle lowering
7021 // This is an experimental code path for lowering vector shuffles on x86. It is
7022 // designed to handle arbitrary vector shuffles and blends, gracefully
7023 // degrading performance as necessary. It works hard to recognize idiomatic
7024 // shuffles and lower them to optimal instruction patterns without leaving
7025 // a framework that allows reasonably efficient handling of all vector shuffle
7027 //===----------------------------------------------------------------------===//
7029 /// \brief Tiny helper function to identify a no-op mask.
7031 /// This is a somewhat boring predicate function. It checks whether the mask
7032 /// array input, which is assumed to be a single-input shuffle mask of the kind
7033 /// used by the X86 shuffle instructions (not a fully general
7034 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7035 /// in-place shuffle are 'no-op's.
7036 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7037 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7038 if (Mask[i] != -1 && Mask[i] != i)
7043 /// \brief Helper function to classify a mask as a single-input mask.
7045 /// This isn't a generic single-input test because in the vector shuffle
7046 /// lowering we canonicalize single inputs to be the first input operand. This
7047 /// means we can more quickly test for a single input by only checking whether
7048 /// an input from the second operand exists. We also assume that the size of
7049 /// mask corresponds to the size of the input vectors which isn't true in the
7050 /// fully general case.
7051 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7053 if (M >= (int)Mask.size())
7058 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7060 /// This helper function produces an 8-bit shuffle immediate corresponding to
7061 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7062 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7065 /// NB: We rely heavily on "undef" masks preserving the input lane.
7066 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7067 SelectionDAG &DAG) {
7068 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7069 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7070 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7071 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7072 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7075 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7076 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7077 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7078 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7079 return DAG.getConstant(Imm, MVT::i8);
7082 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7084 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7085 /// support for floating point shuffles but not integer shuffles. These
7086 /// instructions will incur a domain crossing penalty on some chips though so
7087 /// it is better to avoid lowering through this for integer vectors where
7089 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7090 const X86Subtarget *Subtarget,
7091 SelectionDAG &DAG) {
7093 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7094 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7095 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7096 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7097 ArrayRef<int> Mask = SVOp->getMask();
7098 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7100 if (isSingleInputShuffleMask(Mask)) {
7101 // Straight shuffle of a single input vector. Simulate this by using the
7102 // single input as both of the "inputs" to this instruction..
7103 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7104 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7105 DAG.getConstant(SHUFPDMask, MVT::i8));
7107 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7108 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7110 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7111 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7112 DAG.getConstant(SHUFPDMask, MVT::i8));
7115 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7117 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7118 /// the integer unit to minimize domain crossing penalties. However, for blends
7119 /// it falls back to the floating point shuffle operation with appropriate bit
7121 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7122 const X86Subtarget *Subtarget,
7123 SelectionDAG &DAG) {
7125 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7126 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7127 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7128 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7129 ArrayRef<int> Mask = SVOp->getMask();
7130 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7132 if (isSingleInputShuffleMask(Mask)) {
7133 // Straight shuffle of a single input vector. For everything from SSE2
7134 // onward this has a single fast instruction with no scary immediates.
7135 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7136 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7137 int WidenedMask[4] = {
7138 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7139 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7141 ISD::BITCAST, DL, MVT::v2i64,
7142 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7143 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7146 // We implement this with SHUFPD which is pretty lame because it will likely
7147 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7148 // However, all the alternatives are still more cycles and newer chips don't
7149 // have this problem. It would be really nice if x86 had better shuffles here.
7150 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7151 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7152 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7153 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7156 /// \brief Lower 4-lane 32-bit floating point shuffles.
7158 /// Uses instructions exclusively from the floating point unit to minimize
7159 /// domain crossing penalties, as these are sufficient to implement all v4f32
7161 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7162 const X86Subtarget *Subtarget,
7163 SelectionDAG &DAG) {
7165 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7166 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7167 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7168 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7169 ArrayRef<int> Mask = SVOp->getMask();
7170 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7172 SDValue LowV = V1, HighV = V2;
7173 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7176 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7178 if (NumV2Elements == 0)
7179 // Straight shuffle of a single input vector. We pass the input vector to
7180 // both operands to simulate this with a SHUFPS.
7181 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7182 getV4X86ShuffleImm8ForMask(Mask, DAG));
7184 if (NumV2Elements == 1) {
7186 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7188 // Compute the index adjacent to V2Index and in the same half by toggling
7190 int V2AdjIndex = V2Index ^ 1;
7192 if (Mask[V2AdjIndex] == -1) {
7193 // Handles all the cases where we have a single V2 element and an undef.
7194 // This will only ever happen in the high lanes because we commute the
7195 // vector otherwise.
7197 std::swap(LowV, HighV);
7198 NewMask[V2Index] -= 4;
7200 // Handle the case where the V2 element ends up adjacent to a V1 element.
7201 // To make this work, blend them together as the first step.
7202 int V1Index = V2AdjIndex;
7203 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7204 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7205 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7207 // Now proceed to reconstruct the final blend as we have the necessary
7208 // high or low half formed.
7215 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7216 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7218 } else if (NumV2Elements == 2) {
7219 if (Mask[0] < 4 && Mask[1] < 4) {
7220 // Handle the easy case where we have V1 in the low lanes and V2 in the
7221 // high lanes. We never see this reversed because we sort the shuffle.
7225 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7226 // trying to place elements directly, just blend them and set up the final
7227 // shuffle to place them.
7229 // The first two blend mask elements are for V1, the second two are for
7231 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7232 Mask[2] < 4 ? Mask[2] : Mask[3],
7233 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7234 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7235 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7236 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7238 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7241 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7242 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7243 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7244 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7247 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7248 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7251 /// \brief Lower 4-lane i32 vector shuffles.
7253 /// We try to handle these with integer-domain shuffles where we can, but for
7254 /// blends we use the floating point domain blend instructions.
7255 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7256 const X86Subtarget *Subtarget,
7257 SelectionDAG &DAG) {
7259 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7260 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7261 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7262 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7263 ArrayRef<int> Mask = SVOp->getMask();
7264 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7266 if (isSingleInputShuffleMask(Mask))
7267 // Straight shuffle of a single input vector. For everything from SSE2
7268 // onward this has a single fast instruction with no scary immediates.
7269 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7270 getV4X86ShuffleImm8ForMask(Mask, DAG));
7272 // We implement this with SHUFPS because it can blend from two vectors.
7273 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7274 // up the inputs, bypassing domain shift penalties that we would encur if we
7275 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7277 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7278 DAG.getVectorShuffle(
7280 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7281 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7284 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7285 /// shuffle lowering, and the most complex part.
7287 /// The lowering strategy is to try to form pairs of input lanes which are
7288 /// targeted at the same half of the final vector, and then use a dword shuffle
7289 /// to place them onto the right half, and finally unpack the paired lanes into
7290 /// their final position.
7292 /// The exact breakdown of how to form these dword pairs and align them on the
7293 /// correct sides is really tricky. See the comments within the function for
7294 /// more of the details.
7295 static SDValue lowerV8I16SingleInputVectorShuffle(
7296 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7297 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7298 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7299 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7300 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7302 SmallVector<int, 4> LoInputs;
7303 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7304 [](int M) { return M >= 0; });
7305 std::sort(LoInputs.begin(), LoInputs.end());
7306 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7307 SmallVector<int, 4> HiInputs;
7308 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7309 [](int M) { return M >= 0; });
7310 std::sort(HiInputs.begin(), HiInputs.end());
7311 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7313 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7314 int NumHToL = LoInputs.size() - NumLToL;
7316 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7317 int NumHToH = HiInputs.size() - NumLToH;
7318 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7319 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7320 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7321 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7323 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7324 // such inputs we can swap two of the dwords across the half mark and end up
7325 // with <=2 inputs to each half in each half. Once there, we can fall through
7326 // to the generic code below. For example:
7328 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7329 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7331 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7332 // and an existing 2-into-2 on the other half. In this case we may have to
7333 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7334 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7335 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7336 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7337 // half than the one we target for fixing) will be fixed when we re-enter this
7338 // path. We will also combine away any sequence of PSHUFD instructions that
7339 // result into a single instruction. Here is an example of the tricky case:
7341 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7342 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7344 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7346 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7347 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7349 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7350 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7352 // The result is fine to be handled by the generic logic.
7353 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7354 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7355 int AOffset, int BOffset) {
7356 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7357 "Must call this with A having 3 or 1 inputs from the A half.");
7358 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7359 "Must call this with B having 1 or 3 inputs from the B half.");
7360 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7361 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7363 // Compute the index of dword with only one word among the three inputs in
7364 // a half by taking the sum of the half with three inputs and subtracting
7365 // the sum of the actual three inputs. The difference is the remaining
7368 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7369 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7370 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7371 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7372 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7373 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7374 int TripleNonInputIdx =
7375 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7376 TripleDWord = TripleNonInputIdx / 2;
7378 // We use xor with one to compute the adjacent DWord to whichever one the
7380 OneInputDWord = (OneInput / 2) ^ 1;
7382 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7383 // and BToA inputs. If there is also such a problem with the BToB and AToB
7384 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
7385 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
7386 // is essential that we don't *create* a 3<-1 as then we might oscillate.
7387 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7388 // Compute how many inputs will be flipped by swapping these DWords. We
7390 // to balance this to ensure we don't form a 3-1 shuffle in the other
7392 int NumFlippedAToBInputs =
7393 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
7394 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
7395 int NumFlippedBToBInputs =
7396 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
7397 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
7398 if ((NumFlippedAToBInputs == 1 &&
7399 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
7400 (NumFlippedBToBInputs == 1 &&
7401 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
7402 // We choose whether to fix the A half or B half based on whether that
7403 // half has zero flipped inputs. At zero, we may not be able to fix it
7404 // with that half. We also bias towards fixing the B half because that
7405 // will more commonly be the high half, and we have to bias one way.
7406 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
7407 ArrayRef<int> Inputs) {
7408 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
7409 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
7410 PinnedIdx ^ 1) != Inputs.end();
7411 // Determine whether the free index is in the flipped dword or the
7412 // unflipped dword based on where the pinned index is. We use this bit
7413 // in an xor to conditionally select the adjacent dword.
7414 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
7415 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7416 FixFreeIdx) != Inputs.end();
7417 if (IsFixIdxInput == IsFixFreeIdxInput)
7419 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7420 FixFreeIdx) != Inputs.end();
7421 assert(IsFixIdxInput != IsFixFreeIdxInput &&
7422 "We need to be changing the number of flipped inputs!");
7423 int PSHUFHalfMask[] = {0, 1, 2, 3};
7424 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
7425 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
7427 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
7430 if (M != -1 && M == FixIdx)
7432 else if (M != -1 && M == FixFreeIdx)
7435 if (NumFlippedBToBInputs != 0) {
7437 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7438 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
7440 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
7442 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7443 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
7448 int PSHUFDMask[] = {0, 1, 2, 3};
7449 PSHUFDMask[ADWord] = BDWord;
7450 PSHUFDMask[BDWord] = ADWord;
7451 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7452 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7453 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7454 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7456 // Adjust the mask to match the new locations of A and B.
7458 if (M != -1 && M/2 == ADWord)
7459 M = 2 * BDWord + M % 2;
7460 else if (M != -1 && M/2 == BDWord)
7461 M = 2 * ADWord + M % 2;
7463 // Recurse back into this routine to re-compute state now that this isn't
7464 // a 3 and 1 problem.
7465 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7468 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
7469 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
7470 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
7471 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
7473 // At this point there are at most two inputs to the low and high halves from
7474 // each half. That means the inputs can always be grouped into dwords and
7475 // those dwords can then be moved to the correct half with a dword shuffle.
7476 // We use at most one low and one high word shuffle to collect these paired
7477 // inputs into dwords, and finally a dword shuffle to place them.
7478 int PSHUFLMask[4] = {-1, -1, -1, -1};
7479 int PSHUFHMask[4] = {-1, -1, -1, -1};
7480 int PSHUFDMask[4] = {-1, -1, -1, -1};
7482 // First fix the masks for all the inputs that are staying in their
7483 // original halves. This will then dictate the targets of the cross-half
7485 auto fixInPlaceInputs =
7486 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
7487 MutableArrayRef<int> SourceHalfMask,
7488 MutableArrayRef<int> HalfMask, int HalfOffset) {
7489 if (InPlaceInputs.empty())
7491 if (InPlaceInputs.size() == 1) {
7492 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7493 InPlaceInputs[0] - HalfOffset;
7494 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7497 if (IncomingInputs.empty()) {
7498 // Just fix all of the in place inputs.
7499 for (int Input : InPlaceInputs) {
7500 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
7501 PSHUFDMask[Input / 2] = Input / 2;
7506 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7507 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7508 InPlaceInputs[0] - HalfOffset;
7509 // Put the second input next to the first so that they are packed into
7510 // a dword. We find the adjacent index by toggling the low bit.
7511 int AdjIndex = InPlaceInputs[0] ^ 1;
7512 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7513 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7514 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7516 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
7517 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
7519 // Now gather the cross-half inputs and place them into a free dword of
7520 // their target half.
7521 // FIXME: This operation could almost certainly be simplified dramatically to
7522 // look more like the 3-1 fixing operation.
7523 auto moveInputsToRightHalf = [&PSHUFDMask](
7524 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7525 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7526 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
7528 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7529 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7531 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7533 int LowWord = Word & ~1;
7534 int HighWord = Word | 1;
7535 return isWordClobbered(SourceHalfMask, LowWord) ||
7536 isWordClobbered(SourceHalfMask, HighWord);
7539 if (IncomingInputs.empty())
7542 if (ExistingInputs.empty()) {
7543 // Map any dwords with inputs from them into the right half.
7544 for (int Input : IncomingInputs) {
7545 // If the source half mask maps over the inputs, turn those into
7546 // swaps and use the swapped lane.
7547 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7548 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7549 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7550 Input - SourceOffset;
7551 // We have to swap the uses in our half mask in one sweep.
7552 for (int &M : HalfMask)
7553 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
7555 else if (M == Input)
7556 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7558 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7559 Input - SourceOffset &&
7560 "Previous placement doesn't match!");
7562 // Note that this correctly re-maps both when we do a swap and when
7563 // we observe the other side of the swap above. We rely on that to
7564 // avoid swapping the members of the input list directly.
7565 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7568 // Map the input's dword into the correct half.
7569 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7570 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7572 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7574 "Previous placement doesn't match!");
7577 // And just directly shift any other-half mask elements to be same-half
7578 // as we will have mirrored the dword containing the element into the
7579 // same position within that half.
7580 for (int &M : HalfMask)
7581 if (M >= SourceOffset && M < SourceOffset + 4) {
7582 M = M - SourceOffset + DestOffset;
7583 assert(M >= 0 && "This should never wrap below zero!");
7588 // Ensure we have the input in a viable dword of its current half. This
7589 // is particularly tricky because the original position may be clobbered
7590 // by inputs being moved and *staying* in that half.
7591 if (IncomingInputs.size() == 1) {
7592 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7593 int InputFixed = std::find(std::begin(SourceHalfMask),
7594 std::end(SourceHalfMask), -1) -
7595 std::begin(SourceHalfMask) + SourceOffset;
7596 SourceHalfMask[InputFixed - SourceOffset] =
7597 IncomingInputs[0] - SourceOffset;
7598 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7600 IncomingInputs[0] = InputFixed;
7602 } else if (IncomingInputs.size() == 2) {
7603 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7604 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7605 // We have two non-adjacent or clobbered inputs we need to extract from
7606 // the source half. To do this, we need to map them into some adjacent
7607 // dword slot in the source mask.
7608 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
7609 IncomingInputs[1] - SourceOffset};
7611 // If there is a free slot in the source half mask adjacent to one of
7612 // the inputs, place the other input in it. We use (Index XOR 1) to
7613 // compute an adjacent index.
7614 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
7615 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
7616 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
7617 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7618 InputsFixed[1] = InputsFixed[0] ^ 1;
7619 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
7620 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
7621 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
7622 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
7623 InputsFixed[0] = InputsFixed[1] ^ 1;
7624 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
7625 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
7626 // The two inputs are in the same DWord but it is clobbered and the
7627 // adjacent DWord isn't used at all. Move both inputs to the free
7629 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
7630 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
7631 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
7632 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
7634 // The only way we hit this point is if there is no clobbering
7635 // (because there are no off-half inputs to this half) and there is no
7636 // free slot adjacent to one of the inputs. In this case, we have to
7637 // swap an input with a non-input.
7638 for (int i = 0; i < 4; ++i)
7639 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
7640 "We can't handle any clobbers here!");
7641 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
7642 "Cannot have adjacent inputs here!");
7644 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7645 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
7647 // We also have to update the final source mask in this case because
7648 // it may need to undo the above swap.
7649 for (int &M : FinalSourceHalfMask)
7650 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
7651 M = InputsFixed[1] + SourceOffset;
7652 else if (M == InputsFixed[1] + SourceOffset)
7653 M = (InputsFixed[0] ^ 1) + SourceOffset;
7655 InputsFixed[1] = InputsFixed[0] ^ 1;
7658 // Point everything at the fixed inputs.
7659 for (int &M : HalfMask)
7660 if (M == IncomingInputs[0])
7661 M = InputsFixed[0] + SourceOffset;
7662 else if (M == IncomingInputs[1])
7663 M = InputsFixed[1] + SourceOffset;
7665 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
7666 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
7669 llvm_unreachable("Unhandled input size!");
7672 // Now hoist the DWord down to the right half.
7673 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
7674 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
7675 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
7676 for (int &M : HalfMask)
7677 for (int Input : IncomingInputs)
7679 M = FreeDWord * 2 + Input % 2;
7681 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
7682 /*SourceOffset*/ 4, /*DestOffset*/ 0);
7683 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
7684 /*SourceOffset*/ 0, /*DestOffset*/ 4);
7686 // Now enact all the shuffles we've computed to move the inputs into their
7688 if (!isNoopShuffleMask(PSHUFLMask))
7689 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7690 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
7691 if (!isNoopShuffleMask(PSHUFHMask))
7692 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7693 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
7694 if (!isNoopShuffleMask(PSHUFDMask))
7695 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7696 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7697 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7698 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7700 // At this point, each half should contain all its inputs, and we can then
7701 // just shuffle them into their final position.
7702 assert(std::count_if(LoMask.begin(), LoMask.end(),
7703 [](int M) { return M >= 4; }) == 0 &&
7704 "Failed to lift all the high half inputs to the low mask!");
7705 assert(std::count_if(HiMask.begin(), HiMask.end(),
7706 [](int M) { return M >= 0 && M < 4; }) == 0 &&
7707 "Failed to lift all the low half inputs to the high mask!");
7709 // Do a half shuffle for the low mask.
7710 if (!isNoopShuffleMask(LoMask))
7711 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7712 getV4X86ShuffleImm8ForMask(LoMask, DAG));
7714 // Do a half shuffle with the high mask after shifting its values down.
7715 for (int &M : HiMask)
7718 if (!isNoopShuffleMask(HiMask))
7719 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7720 getV4X86ShuffleImm8ForMask(HiMask, DAG));
7725 /// \brief Detect whether the mask pattern should be lowered through
7728 /// This essentially tests whether viewing the mask as an interleaving of two
7729 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
7730 /// lowering it through interleaving is a significantly better strategy.
7731 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
7732 int NumEvenInputs[2] = {0, 0};
7733 int NumOddInputs[2] = {0, 0};
7734 int NumLoInputs[2] = {0, 0};
7735 int NumHiInputs[2] = {0, 0};
7736 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7740 int InputIdx = Mask[i] >= Size;
7743 ++NumLoInputs[InputIdx];
7745 ++NumHiInputs[InputIdx];
7748 ++NumEvenInputs[InputIdx];
7750 ++NumOddInputs[InputIdx];
7753 // The minimum number of cross-input results for both the interleaved and
7754 // split cases. If interleaving results in fewer cross-input results, return
7756 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
7757 NumEvenInputs[0] + NumOddInputs[1]);
7758 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
7759 NumLoInputs[0] + NumHiInputs[1]);
7760 return InterleavedCrosses < SplitCrosses;
7763 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
7765 /// This strategy only works when the inputs from each vector fit into a single
7766 /// half of that vector, and generally there are not so many inputs as to leave
7767 /// the in-place shuffles required highly constrained (and thus expensive). It
7768 /// shifts all the inputs into a single side of both input vectors and then
7769 /// uses an unpack to interleave these inputs in a single vector. At that
7770 /// point, we will fall back on the generic single input shuffle lowering.
7771 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
7773 MutableArrayRef<int> Mask,
7774 const X86Subtarget *Subtarget,
7775 SelectionDAG &DAG) {
7776 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7777 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7778 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
7779 for (int i = 0; i < 8; ++i)
7780 if (Mask[i] >= 0 && Mask[i] < 4)
7781 LoV1Inputs.push_back(i);
7782 else if (Mask[i] >= 4 && Mask[i] < 8)
7783 HiV1Inputs.push_back(i);
7784 else if (Mask[i] >= 8 && Mask[i] < 12)
7785 LoV2Inputs.push_back(i);
7786 else if (Mask[i] >= 12)
7787 HiV2Inputs.push_back(i);
7789 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
7790 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
7793 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
7794 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
7795 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
7797 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
7798 HiV1Inputs.size() + HiV2Inputs.size();
7800 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
7801 ArrayRef<int> HiInputs, bool MoveToLo,
7803 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
7804 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
7805 if (BadInputs.empty())
7808 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7809 int MoveOffset = MoveToLo ? 0 : 4;
7811 if (GoodInputs.empty()) {
7812 for (int BadInput : BadInputs) {
7813 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
7814 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
7817 if (GoodInputs.size() == 2) {
7818 // If the low inputs are spread across two dwords, pack them into
7820 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
7821 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
7822 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
7823 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
7825 // Otherwise pin the good inputs.
7826 for (int GoodInput : GoodInputs)
7827 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
7830 if (BadInputs.size() == 2) {
7831 // If we have two bad inputs then there may be either one or two good
7832 // inputs fixed in place. Find a fixed input, and then find the *other*
7833 // two adjacent indices by using modular arithmetic.
7835 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
7836 [](int M) { return M >= 0; }) -
7837 std::begin(MoveMask);
7839 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
7840 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
7841 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
7842 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7843 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
7844 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7845 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
7847 assert(BadInputs.size() == 1 && "All sizes handled");
7848 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
7849 std::end(MoveMask), -1) -
7850 std::begin(MoveMask);
7851 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7852 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7856 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7859 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
7861 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
7864 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
7865 // cross-half traffic in the final shuffle.
7867 // Munge the mask to be a single-input mask after the unpack merges the
7871 M = 2 * (M % 4) + (M / 8);
7873 return DAG.getVectorShuffle(
7874 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7875 DL, MVT::v8i16, V1, V2),
7876 DAG.getUNDEF(MVT::v8i16), Mask);
7879 /// \brief Generic lowering of 8-lane i16 shuffles.
7881 /// This handles both single-input shuffles and combined shuffle/blends with
7882 /// two inputs. The single input shuffles are immediately delegated to
7883 /// a dedicated lowering routine.
7885 /// The blends are lowered in one of three fundamental ways. If there are few
7886 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
7887 /// of the input is significantly cheaper when lowered as an interleaving of
7888 /// the two inputs, try to interleave them. Otherwise, blend the low and high
7889 /// halves of the inputs separately (making them have relatively few inputs)
7890 /// and then concatenate them.
7891 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7892 const X86Subtarget *Subtarget,
7893 SelectionDAG &DAG) {
7895 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
7896 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7897 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7898 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7899 ArrayRef<int> OrigMask = SVOp->getMask();
7900 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7901 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
7902 MutableArrayRef<int> Mask(MaskStorage);
7904 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
7906 auto isV1 = [](int M) { return M >= 0 && M < 8; };
7907 auto isV2 = [](int M) { return M >= 8; };
7909 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
7910 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
7912 if (NumV2Inputs == 0)
7913 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
7915 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
7916 "to be V1-input shuffles.");
7918 if (NumV1Inputs + NumV2Inputs <= 4)
7919 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
7921 // Check whether an interleaving lowering is likely to be more efficient.
7922 // This isn't perfect but it is a strong heuristic that tends to work well on
7923 // the kinds of shuffles that show up in practice.
7925 // FIXME: Handle 1x, 2x, and 4x interleaving.
7926 if (shouldLowerAsInterleaving(Mask)) {
7927 // FIXME: Figure out whether we should pack these into the low or high
7930 int EMask[8], OMask[8];
7931 for (int i = 0; i < 4; ++i) {
7932 EMask[i] = Mask[2*i];
7933 OMask[i] = Mask[2*i + 1];
7938 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
7939 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
7941 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
7944 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7945 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7947 for (int i = 0; i < 4; ++i) {
7948 LoBlendMask[i] = Mask[i];
7949 HiBlendMask[i] = Mask[i + 4];
7952 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7953 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7954 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
7955 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
7957 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7958 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
7961 /// \brief Check whether a compaction lowering can be done by dropping even
7962 /// elements and compute how many times even elements must be dropped.
7964 /// This handles shuffles which take every Nth element where N is a power of
7965 /// two. Example shuffle masks:
7967 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
7968 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
7969 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
7970 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
7971 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
7972 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
7974 /// Any of these lanes can of course be undef.
7976 /// This routine only supports N <= 3.
7977 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
7980 /// \returns N above, or the number of times even elements must be dropped if
7981 /// there is such a number. Otherwise returns zero.
7982 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
7983 // Figure out whether we're looping over two inputs or just one.
7984 bool IsSingleInput = isSingleInputShuffleMask(Mask);
7986 // The modulus for the shuffle vector entries is based on whether this is
7987 // a single input or not.
7988 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
7989 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
7990 "We should only be called with masks with a power-of-2 size!");
7992 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
7994 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
7995 // and 2^3 simultaneously. This is because we may have ambiguity with
7996 // partially undef inputs.
7997 bool ViableForN[3] = {true, true, true};
7999 for (int i = 0, e = Mask.size(); i < e; ++i) {
8000 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8005 bool IsAnyViable = false;
8006 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8007 if (ViableForN[j]) {
8010 // The shuffle mask must be equal to (i * 2^N) % M.
8011 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8014 ViableForN[j] = false;
8016 // Early exit if we exhaust the possible powers of two.
8021 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8025 // Return 0 as there is no viable power of two.
8029 /// \brief Generic lowering of v16i8 shuffles.
8031 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8032 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8033 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8034 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8036 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8037 const X86Subtarget *Subtarget,
8038 SelectionDAG &DAG) {
8040 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8041 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8042 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8043 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8044 ArrayRef<int> OrigMask = SVOp->getMask();
8045 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8046 int MaskStorage[16] = {
8047 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8048 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8049 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8050 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8051 MutableArrayRef<int> Mask(MaskStorage);
8052 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8053 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8055 // For single-input shuffles, there are some nicer lowering tricks we can use.
8056 if (isSingleInputShuffleMask(Mask)) {
8057 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8058 // Notably, this handles splat and partial-splat shuffles more efficiently.
8059 // However, it only makes sense if the pre-duplication shuffle simplifies
8060 // things significantly. Currently, this means we need to be able to
8061 // express the pre-duplication shuffle as an i16 shuffle.
8063 // FIXME: We should check for other patterns which can be widened into an
8064 // i16 shuffle as well.
8065 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8066 for (int i = 0; i < 16; i += 2) {
8067 if (Mask[i] != Mask[i + 1])
8072 auto tryToWidenViaDuplication = [&]() -> SDValue {
8073 if (!canWidenViaDuplication(Mask))
8075 SmallVector<int, 4> LoInputs;
8076 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8077 [](int M) { return M >= 0 && M < 8; });
8078 std::sort(LoInputs.begin(), LoInputs.end());
8079 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8081 SmallVector<int, 4> HiInputs;
8082 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8083 [](int M) { return M >= 8; });
8084 std::sort(HiInputs.begin(), HiInputs.end());
8085 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8088 bool TargetLo = LoInputs.size() >= HiInputs.size();
8089 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8090 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8092 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8093 SmallDenseMap<int, int, 8> LaneMap;
8094 for (int I : InPlaceInputs) {
8095 PreDupI16Shuffle[I/2] = I/2;
8098 int j = TargetLo ? 0 : 4, je = j + 4;
8099 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8100 // Check if j is already a shuffle of this input. This happens when
8101 // there are two adjacent bytes after we move the low one.
8102 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8103 // If we haven't yet mapped the input, search for a slot into which
8105 while (j < je && PreDupI16Shuffle[j] != -1)
8109 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8112 // Map this input with the i16 shuffle.
8113 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8116 // Update the lane map based on the mapping we ended up with.
8117 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8120 ISD::BITCAST, DL, MVT::v16i8,
8121 DAG.getVectorShuffle(MVT::v8i16, DL,
8122 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8123 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8125 // Unpack the bytes to form the i16s that will be shuffled into place.
8126 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8127 MVT::v16i8, V1, V1);
8129 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8130 for (int i = 0; i < 16; i += 2) {
8132 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8133 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8136 ISD::BITCAST, DL, MVT::v16i8,
8137 DAG.getVectorShuffle(MVT::v8i16, DL,
8138 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8139 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8141 if (SDValue V = tryToWidenViaDuplication())
8145 // Check whether an interleaving lowering is likely to be more efficient.
8146 // This isn't perfect but it is a strong heuristic that tends to work well on
8147 // the kinds of shuffles that show up in practice.
8149 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8150 if (shouldLowerAsInterleaving(Mask)) {
8151 // FIXME: Figure out whether we should pack these into the low or high
8154 int EMask[16], OMask[16];
8155 for (int i = 0; i < 8; ++i) {
8156 EMask[i] = Mask[2*i];
8157 OMask[i] = Mask[2*i + 1];
8162 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8163 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8165 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8168 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8169 // with PSHUFB. It is important to do this before we attempt to generate any
8170 // blends but after all of the single-input lowerings. If the single input
8171 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8172 // want to preserve that and we can DAG combine any longer sequences into
8173 // a PSHUFB in the end. But once we start blending from multiple inputs,
8174 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8175 // and there are *very* few patterns that would actually be faster than the
8176 // PSHUFB approach because of its ability to zero lanes.
8178 // FIXME: The only exceptions to the above are blends which are exact
8179 // interleavings with direct instructions supporting them. We currently don't
8180 // handle those well here.
8181 if (Subtarget->hasSSSE3()) {
8184 for (int i = 0; i < 16; ++i)
8185 if (Mask[i] == -1) {
8186 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
8188 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
8190 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
8192 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
8193 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8194 if (isSingleInputShuffleMask(Mask))
8195 return V1; // Single inputs are easy.
8197 // Otherwise, blend the two.
8198 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
8199 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8200 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8203 // Check whether a compaction lowering can be done. This handles shuffles
8204 // which take every Nth element for some even N. See the helper function for
8207 // We special case these as they can be particularly efficiently handled with
8208 // the PACKUSB instruction on x86 and they show up in common patterns of
8209 // rearranging bytes to truncate wide elements.
8210 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8211 // NumEvenDrops is the power of two stride of the elements. Another way of
8212 // thinking about it is that we need to drop the even elements this many
8213 // times to get the original input.
8214 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8216 // First we need to zero all the dropped bytes.
8217 assert(NumEvenDrops <= 3 &&
8218 "No support for dropping even elements more than 3 times.");
8219 // We use the mask type to pick which bytes are preserved based on how many
8220 // elements are dropped.
8221 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8222 SDValue ByteClearMask =
8223 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8224 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8225 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8227 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8229 // Now pack things back together.
8230 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8231 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8232 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8233 for (int i = 1; i < NumEvenDrops; ++i) {
8234 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8235 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8241 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8242 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8243 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8244 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8246 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
8247 MutableArrayRef<int> V1HalfBlendMask,
8248 MutableArrayRef<int> V2HalfBlendMask) {
8249 for (int i = 0; i < 8; ++i)
8250 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
8251 V1HalfBlendMask[i] = HalfMask[i];
8253 } else if (HalfMask[i] >= 16) {
8254 V2HalfBlendMask[i] = HalfMask[i] - 16;
8255 HalfMask[i] = i + 8;
8258 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
8259 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
8261 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8263 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
8264 MutableArrayRef<int> HiBlendMask) {
8266 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8267 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8269 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
8270 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8271 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
8272 [](int M) { return M >= 0 && M % 2 == 1; })) {
8273 // Use a mask to drop the high bytes.
8274 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8275 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
8276 DAG.getConstant(0x00FF, MVT::v8i16));
8278 // This will be a single vector shuffle instead of a blend so nuke V2.
8279 V2 = DAG.getUNDEF(MVT::v8i16);
8281 // Squash the masks to point directly into V1.
8282 for (int &M : LoBlendMask)
8285 for (int &M : HiBlendMask)
8289 // Otherwise just unpack the low half of V into V1 and the high half into
8290 // V2 so that we can blend them as i16s.
8291 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8292 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8293 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8294 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8297 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8298 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8299 return std::make_pair(BlendedLo, BlendedHi);
8301 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
8302 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
8303 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
8305 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
8306 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
8308 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8311 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8313 /// This routine breaks down the specific type of 128-bit shuffle and
8314 /// dispatches to the lowering routines accordingly.
8315 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8316 MVT VT, const X86Subtarget *Subtarget,
8317 SelectionDAG &DAG) {
8318 switch (VT.SimpleTy) {
8320 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8322 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8324 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8326 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8328 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8330 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8333 llvm_unreachable("Unimplemented!");
8337 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
8340 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
8341 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
8342 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
8343 /// we encode the logic here for specific shuffle lowering routines to bail to
8344 /// when they exhaust the features avaible to more directly handle the shuffle.
8345 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
8347 const X86Subtarget *Subtarget,
8348 SelectionDAG &DAG) {
8350 MVT VT = Op.getSimpleValueType();
8351 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
8352 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8353 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8354 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8355 ArrayRef<int> Mask = SVOp->getMask();
8357 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
8358 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
8360 int NumElements = VT.getVectorNumElements();
8361 int SplitNumElements = NumElements / 2;
8362 MVT ScalarVT = VT.getScalarType();
8363 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8365 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
8366 DAG.getIntPtrConstant(0));
8367 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
8368 DAG.getIntPtrConstant(SplitNumElements));
8369 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
8370 DAG.getIntPtrConstant(0));
8371 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
8372 DAG.getIntPtrConstant(SplitNumElements));
8374 // Now create two 4-way blends of these half-width vectors.
8375 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
8376 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
8377 for (int i = 0; i < SplitNumElements; ++i) {
8378 int M = HalfMask[i];
8379 if (M >= NumElements) {
8380 V2BlendMask.push_back(M - NumElements);
8381 V1BlendMask.push_back(-1);
8382 BlendMask.push_back(SplitNumElements + i);
8383 } else if (M >= 0) {
8384 V2BlendMask.push_back(-1);
8385 V1BlendMask.push_back(M);
8386 BlendMask.push_back(i);
8388 V2BlendMask.push_back(-1);
8389 V1BlendMask.push_back(-1);
8390 BlendMask.push_back(-1);
8393 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8394 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8395 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
8397 SDValue Lo = HalfBlend(LoMask);
8398 SDValue Hi = HalfBlend(HiMask);
8399 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
8402 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
8404 /// This routine either breaks down the specific type of a 256-bit x86 vector
8405 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
8406 /// together based on the available instructions.
8407 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8408 MVT VT, const X86Subtarget *Subtarget,
8409 SelectionDAG &DAG) {
8410 // FIXME: We should detect symmetric patterns and re-use the 128-bit shuffle
8411 // lowering logic with wider types in that case.
8413 // FIXME: We should detect when we can use AVX2 cross-half shuffles to either
8414 // implement the shuffle completely, more effectively build symmetry, or
8415 // minimize half-blends.
8417 // Fall back to the basic pattern of extracting the high half and forming
8419 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8422 /// \brief Tiny helper function to test whether a shuffle mask could be
8423 /// simplified by widening the elements being shuffled.
8424 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
8425 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8426 if (Mask[i] % 2 != 0 || Mask[i] + 1 != Mask[i+1])
8432 /// \brief Top-level lowering for x86 vector shuffles.
8434 /// This handles decomposition, canonicalization, and lowering of all x86
8435 /// vector shuffles. Most of the specific lowering strategies are encapsulated
8436 /// above in helper routines. The canonicalization attempts to widen shuffles
8437 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
8438 /// s.t. only one of the two inputs needs to be tested, etc.
8439 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
8440 SelectionDAG &DAG) {
8441 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8442 ArrayRef<int> Mask = SVOp->getMask();
8443 SDValue V1 = Op.getOperand(0);
8444 SDValue V2 = Op.getOperand(1);
8445 MVT VT = Op.getSimpleValueType();
8446 int NumElements = VT.getVectorNumElements();
8449 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
8451 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
8452 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8453 if (V1IsUndef && V2IsUndef)
8454 return DAG.getUNDEF(VT);
8456 // When we create a shuffle node we put the UNDEF node to second operand,
8457 // but in some cases the first operand may be transformed to UNDEF.
8458 // In this case we should just commute the node.
8460 return DAG.getCommutedVectorShuffle(*SVOp);
8462 // Check for non-undef masks pointing at an undef vector and make the masks
8463 // undef as well. This makes it easier to match the shuffle based solely on
8467 if (M >= NumElements) {
8468 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
8469 for (int &M : NewMask)
8470 if (M >= NumElements)
8472 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
8475 // For integer vector shuffles, try to collapse them into a shuffle of fewer
8476 // lanes but wider integers. We cap this to not form integers larger than i64
8477 // but it might be interesting to form i128 integers to handle flipping the
8478 // low and high halves of AVX 256-bit vectors.
8479 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
8480 canWidenShuffleElements(Mask)) {
8481 SmallVector<int, 8> NewMask;
8482 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8483 NewMask.push_back(Mask[i] / 2);
8485 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
8486 VT.getVectorNumElements() / 2);
8487 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
8488 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
8489 return DAG.getNode(ISD::BITCAST, dl, VT,
8490 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
8493 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
8494 for (int M : SVOp->getMask())
8497 else if (M < NumElements)
8502 // Commute the shuffle as needed such that more elements come from V1 than
8503 // V2. This allows us to match the shuffle pattern strictly on how many
8504 // elements come from V1 without handling the symmetric cases.
8505 if (NumV2Elements > NumV1Elements)
8506 return DAG.getCommutedVectorShuffle(*SVOp);
8508 // When the number of V1 and V2 elements are the same, try to minimize the
8509 // number of uses of V2 in the low half of the vector.
8510 if (NumV1Elements == NumV2Elements) {
8511 int LowV1Elements = 0, LowV2Elements = 0;
8512 for (int M : SVOp->getMask().slice(0, NumElements / 2))
8513 if (M >= NumElements)
8517 if (LowV2Elements > LowV1Elements)
8518 return DAG.getCommutedVectorShuffle(*SVOp);
8521 // For each vector width, delegate to a specialized lowering routine.
8522 if (VT.getSizeInBits() == 128)
8523 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8525 if (VT.getSizeInBits() == 256)
8526 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8528 llvm_unreachable("Unimplemented!");
8532 //===----------------------------------------------------------------------===//
8533 // Legacy vector shuffle lowering
8535 // This code is the legacy code handling vector shuffles until the above
8536 // replaces its functionality and performance.
8537 //===----------------------------------------------------------------------===//
8539 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
8540 bool hasInt256, unsigned *MaskOut = nullptr) {
8541 MVT EltVT = VT.getVectorElementType();
8543 // There is no blend with immediate in AVX-512.
8544 if (VT.is512BitVector())
8547 if (!hasSSE41 || EltVT == MVT::i8)
8549 if (!hasInt256 && VT == MVT::v16i16)
8552 unsigned MaskValue = 0;
8553 unsigned NumElems = VT.getVectorNumElements();
8554 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
8555 unsigned NumLanes = (NumElems - 1) / 8 + 1;
8556 unsigned NumElemsInLane = NumElems / NumLanes;
8558 // Blend for v16i16 should be symetric for the both lanes.
8559 for (unsigned i = 0; i < NumElemsInLane; ++i) {
8561 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
8562 int EltIdx = MaskVals[i];
8564 if ((EltIdx < 0 || EltIdx == (int)i) &&
8565 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
8568 if (((unsigned)EltIdx == (i + NumElems)) &&
8569 (SndLaneEltIdx < 0 ||
8570 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
8571 MaskValue |= (1 << i);
8577 *MaskOut = MaskValue;
8581 // Try to lower a shuffle node into a simple blend instruction.
8582 // This function assumes isBlendMask returns true for this
8583 // SuffleVectorSDNode
8584 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
8586 const X86Subtarget *Subtarget,
8587 SelectionDAG &DAG) {
8588 MVT VT = SVOp->getSimpleValueType(0);
8589 MVT EltVT = VT.getVectorElementType();
8590 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
8591 Subtarget->hasInt256() && "Trying to lower a "
8592 "VECTOR_SHUFFLE to a Blend but "
8593 "with the wrong mask"));
8594 SDValue V1 = SVOp->getOperand(0);
8595 SDValue V2 = SVOp->getOperand(1);
8597 unsigned NumElems = VT.getVectorNumElements();
8599 // Convert i32 vectors to floating point if it is not AVX2.
8600 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8602 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8603 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8605 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
8606 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8609 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8610 DAG.getConstant(MaskValue, MVT::i32));
8611 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8614 /// In vector type \p VT, return true if the element at index \p InputIdx
8615 /// falls on a different 128-bit lane than \p OutputIdx.
8616 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
8617 unsigned OutputIdx) {
8618 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
8619 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
8622 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
8623 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
8624 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
8625 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
8627 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
8628 SelectionDAG &DAG) {
8629 MVT VT = V1.getSimpleValueType();
8630 assert(VT.is128BitVector() || VT.is256BitVector());
8632 MVT EltVT = VT.getVectorElementType();
8633 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
8634 unsigned NumElts = VT.getVectorNumElements();
8636 SmallVector<SDValue, 32> PshufbMask;
8637 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
8638 int InputIdx = MaskVals[OutputIdx];
8639 unsigned InputByteIdx;
8641 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
8642 InputByteIdx = 0x80;
8644 // Cross lane is not allowed.
8645 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
8647 InputByteIdx = InputIdx * EltSizeInBytes;
8648 // Index is an byte offset within the 128-bit lane.
8649 InputByteIdx &= 0xf;
8652 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
8653 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
8654 if (InputByteIdx != 0x80)
8659 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
8661 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
8662 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
8663 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8666 // v8i16 shuffles - Prefer shuffles in the following order:
8667 // 1. [all] pshuflw, pshufhw, optional move
8668 // 2. [ssse3] 1 x pshufb
8669 // 3. [ssse3] 2 x pshufb + 1 x por
8670 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8672 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
8673 SelectionDAG &DAG) {
8674 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8675 SDValue V1 = SVOp->getOperand(0);
8676 SDValue V2 = SVOp->getOperand(1);
8678 SmallVector<int, 8> MaskVals;
8680 // Determine if more than 1 of the words in each of the low and high quadwords
8681 // of the result come from the same quadword of one of the two inputs. Undef
8682 // mask values count as coming from any quadword, for better codegen.
8684 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
8685 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
8686 unsigned LoQuad[] = { 0, 0, 0, 0 };
8687 unsigned HiQuad[] = { 0, 0, 0, 0 };
8688 // Indices of quads used.
8689 std::bitset<4> InputQuads;
8690 for (unsigned i = 0; i < 8; ++i) {
8691 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
8692 int EltIdx = SVOp->getMaskElt(i);
8693 MaskVals.push_back(EltIdx);
8702 InputQuads.set(EltIdx / 4);
8705 int BestLoQuad = -1;
8706 unsigned MaxQuad = 1;
8707 for (unsigned i = 0; i < 4; ++i) {
8708 if (LoQuad[i] > MaxQuad) {
8710 MaxQuad = LoQuad[i];
8714 int BestHiQuad = -1;
8716 for (unsigned i = 0; i < 4; ++i) {
8717 if (HiQuad[i] > MaxQuad) {
8719 MaxQuad = HiQuad[i];
8723 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
8724 // of the two input vectors, shuffle them into one input vector so only a
8725 // single pshufb instruction is necessary. If there are more than 2 input
8726 // quads, disable the next transformation since it does not help SSSE3.
8727 bool V1Used = InputQuads[0] || InputQuads[1];
8728 bool V2Used = InputQuads[2] || InputQuads[3];
8729 if (Subtarget->hasSSSE3()) {
8730 if (InputQuads.count() == 2 && V1Used && V2Used) {
8731 BestLoQuad = InputQuads[0] ? 0 : 1;
8732 BestHiQuad = InputQuads[2] ? 2 : 3;
8734 if (InputQuads.count() > 2) {
8740 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
8741 // the shuffle mask. If a quad is scored as -1, that means that it contains
8742 // words from all 4 input quadwords.
8744 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
8746 BestLoQuad < 0 ? 0 : BestLoQuad,
8747 BestHiQuad < 0 ? 1 : BestHiQuad
8749 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
8750 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
8751 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8752 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
8754 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
8755 // source words for the shuffle, to aid later transformations.
8756 bool AllWordsInNewV = true;
8757 bool InOrder[2] = { true, true };
8758 for (unsigned i = 0; i != 8; ++i) {
8759 int idx = MaskVals[i];
8761 InOrder[i/4] = false;
8762 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
8764 AllWordsInNewV = false;
8768 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
8769 if (AllWordsInNewV) {
8770 for (int i = 0; i != 8; ++i) {
8771 int idx = MaskVals[i];
8774 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
8775 if ((idx != i) && idx < 4)
8777 if ((idx != i) && idx > 3)
8786 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8787 // pshufhw, that's as cheap as it gets. Return the new shuffle.
8788 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
8789 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
8790 unsigned TargetMask = 0;
8791 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
8792 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
8793 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8794 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
8795 getShufflePSHUFLWImmediate(SVOp);
8796 V1 = NewV.getOperand(0);
8797 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
8801 // Promote splats to a larger type which usually leads to more efficient code.
8802 // FIXME: Is this true if pshufb is available?
8803 if (SVOp->isSplat())
8804 return PromoteSplat(SVOp, DAG);
8806 // If we have SSSE3, and all words of the result are from 1 input vector,
8807 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
8808 // is present, fall back to case 4.
8809 if (Subtarget->hasSSSE3()) {
8810 SmallVector<SDValue,16> pshufbMask;
8812 // If we have elements from both input vectors, set the high bit of the
8813 // shuffle mask element to zero out elements that come from V2 in the V1
8814 // mask, and elements that come from V1 in the V2 mask, so that the two
8815 // results can be OR'd together.
8816 bool TwoInputs = V1Used && V2Used;
8817 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
8819 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8821 // Calculate the shuffle mask for the second input, shuffle it, and
8822 // OR it with the first shuffled input.
8823 CommuteVectorShuffleMask(MaskVals, 8);
8824 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
8825 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8826 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8829 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
8830 // and update MaskVals with new element order.
8831 std::bitset<8> InOrder;
8832 if (BestLoQuad >= 0) {
8833 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
8834 for (int i = 0; i != 4; ++i) {
8835 int idx = MaskVals[i];
8838 } else if ((idx / 4) == BestLoQuad) {
8843 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8846 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8847 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8848 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
8850 getShufflePSHUFLWImmediate(SVOp), DAG);
8854 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
8855 // and update MaskVals with the new element order.
8856 if (BestHiQuad >= 0) {
8857 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
8858 for (unsigned i = 4; i != 8; ++i) {
8859 int idx = MaskVals[i];
8862 } else if ((idx / 4) == BestHiQuad) {
8863 MaskV[i] = (idx & 3) + 4;
8867 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8870 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8871 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8872 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
8874 getShufflePSHUFHWImmediate(SVOp), DAG);
8878 // In case BestHi & BestLo were both -1, which means each quadword has a word
8879 // from each of the four input quadwords, calculate the InOrder bitvector now
8880 // before falling through to the insert/extract cleanup.
8881 if (BestLoQuad == -1 && BestHiQuad == -1) {
8883 for (int i = 0; i != 8; ++i)
8884 if (MaskVals[i] < 0 || MaskVals[i] == i)
8888 // The other elements are put in the right place using pextrw and pinsrw.
8889 for (unsigned i = 0; i != 8; ++i) {
8892 int EltIdx = MaskVals[i];
8895 SDValue ExtOp = (EltIdx < 8) ?
8896 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
8897 DAG.getIntPtrConstant(EltIdx)) :
8898 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
8899 DAG.getIntPtrConstant(EltIdx - 8));
8900 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
8901 DAG.getIntPtrConstant(i));
8906 /// \brief v16i16 shuffles
8908 /// FIXME: We only support generation of a single pshufb currently. We can
8909 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
8910 /// well (e.g 2 x pshufb + 1 x por).
8912 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
8913 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8914 SDValue V1 = SVOp->getOperand(0);
8915 SDValue V2 = SVOp->getOperand(1);
8918 if (V2.getOpcode() != ISD::UNDEF)
8921 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8922 return getPSHUFB(MaskVals, V1, dl, DAG);
8925 // v16i8 shuffles - Prefer shuffles in the following order:
8926 // 1. [ssse3] 1 x pshufb
8927 // 2. [ssse3] 2 x pshufb + 1 x por
8928 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
8929 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
8930 const X86Subtarget* Subtarget,
8931 SelectionDAG &DAG) {
8932 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8933 SDValue V1 = SVOp->getOperand(0);
8934 SDValue V2 = SVOp->getOperand(1);
8936 ArrayRef<int> MaskVals = SVOp->getMask();
8938 // Promote splats to a larger type which usually leads to more efficient code.
8939 // FIXME: Is this true if pshufb is available?
8940 if (SVOp->isSplat())
8941 return PromoteSplat(SVOp, DAG);
8943 // If we have SSSE3, case 1 is generated when all result bytes come from
8944 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
8945 // present, fall back to case 3.
8947 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
8948 if (Subtarget->hasSSSE3()) {
8949 SmallVector<SDValue,16> pshufbMask;
8951 // If all result elements are from one input vector, then only translate
8952 // undef mask values to 0x80 (zero out result) in the pshufb mask.
8954 // Otherwise, we have elements from both input vectors, and must zero out
8955 // elements that come from V2 in the first mask, and V1 in the second mask
8956 // so that we can OR them together.
8957 for (unsigned i = 0; i != 16; ++i) {
8958 int EltIdx = MaskVals[i];
8959 if (EltIdx < 0 || EltIdx >= 16)
8961 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8963 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
8964 DAG.getNode(ISD::BUILD_VECTOR, dl,
8965 MVT::v16i8, pshufbMask));
8967 // As PSHUFB will zero elements with negative indices, it's safe to ignore
8968 // the 2nd operand if it's undefined or zero.
8969 if (V2.getOpcode() == ISD::UNDEF ||
8970 ISD::isBuildVectorAllZeros(V2.getNode()))
8973 // Calculate the shuffle mask for the second input, shuffle it, and
8974 // OR it with the first shuffled input.
8976 for (unsigned i = 0; i != 16; ++i) {
8977 int EltIdx = MaskVals[i];
8978 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
8979 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8981 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
8982 DAG.getNode(ISD::BUILD_VECTOR, dl,
8983 MVT::v16i8, pshufbMask));
8984 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8987 // No SSSE3 - Calculate in place words and then fix all out of place words
8988 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
8989 // the 16 different words that comprise the two doublequadword input vectors.
8990 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8991 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
8993 for (int i = 0; i != 8; ++i) {
8994 int Elt0 = MaskVals[i*2];
8995 int Elt1 = MaskVals[i*2+1];
8997 // This word of the result is all undef, skip it.
8998 if (Elt0 < 0 && Elt1 < 0)
9001 // This word of the result is already in the correct place, skip it.
9002 if ((Elt0 == i*2) && (Elt1 == i*2+1))
9005 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
9006 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
9009 // If Elt0 and Elt1 are defined, are consecutive, and can be load
9010 // using a single extract together, load it and store it.
9011 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
9012 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9013 DAG.getIntPtrConstant(Elt1 / 2));
9014 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9015 DAG.getIntPtrConstant(i));
9019 // If Elt1 is defined, extract it from the appropriate source. If the
9020 // source byte is not also odd, shift the extracted word left 8 bits
9021 // otherwise clear the bottom 8 bits if we need to do an or.
9023 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9024 DAG.getIntPtrConstant(Elt1 / 2));
9025 if ((Elt1 & 1) == 0)
9026 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
9028 TLI.getShiftAmountTy(InsElt.getValueType())));
9030 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
9031 DAG.getConstant(0xFF00, MVT::i16));
9033 // If Elt0 is defined, extract it from the appropriate source. If the
9034 // source byte is not also even, shift the extracted word right 8 bits. If
9035 // Elt1 was also defined, OR the extracted values together before
9036 // inserting them in the result.
9038 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
9039 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
9040 if ((Elt0 & 1) != 0)
9041 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
9043 TLI.getShiftAmountTy(InsElt0.getValueType())));
9045 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
9046 DAG.getConstant(0x00FF, MVT::i16));
9047 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
9050 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9051 DAG.getIntPtrConstant(i));
9053 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
9056 // v32i8 shuffles - Translate to VPSHUFB if possible.
9058 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
9059 const X86Subtarget *Subtarget,
9060 SelectionDAG &DAG) {
9061 MVT VT = SVOp->getSimpleValueType(0);
9062 SDValue V1 = SVOp->getOperand(0);
9063 SDValue V2 = SVOp->getOperand(1);
9065 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9067 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9068 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
9069 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
9071 // VPSHUFB may be generated if
9072 // (1) one of input vector is undefined or zeroinitializer.
9073 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
9074 // And (2) the mask indexes don't cross the 128-bit lane.
9075 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
9076 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
9079 if (V1IsAllZero && !V2IsAllZero) {
9080 CommuteVectorShuffleMask(MaskVals, 32);
9083 return getPSHUFB(MaskVals, V1, dl, DAG);
9086 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
9087 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
9088 /// done when every pair / quad of shuffle mask elements point to elements in
9089 /// the right sequence. e.g.
9090 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
9092 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
9093 SelectionDAG &DAG) {
9094 MVT VT = SVOp->getSimpleValueType(0);
9096 unsigned NumElems = VT.getVectorNumElements();
9099 switch (VT.SimpleTy) {
9100 default: llvm_unreachable("Unexpected!");
9103 return SDValue(SVOp, 0);
9104 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
9105 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
9106 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
9107 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
9108 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
9109 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
9112 SmallVector<int, 8> MaskVec;
9113 for (unsigned i = 0; i != NumElems; i += Scale) {
9115 for (unsigned j = 0; j != Scale; ++j) {
9116 int EltIdx = SVOp->getMaskElt(i+j);
9120 StartIdx = (EltIdx / Scale);
9121 if (EltIdx != (int)(StartIdx*Scale + j))
9124 MaskVec.push_back(StartIdx);
9127 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
9128 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
9129 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
9132 /// getVZextMovL - Return a zero-extending vector move low node.
9134 static SDValue getVZextMovL(MVT VT, MVT OpVT,
9135 SDValue SrcOp, SelectionDAG &DAG,
9136 const X86Subtarget *Subtarget, SDLoc dl) {
9137 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
9138 LoadSDNode *LD = nullptr;
9139 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
9140 LD = dyn_cast<LoadSDNode>(SrcOp);
9142 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
9144 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
9145 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
9146 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
9147 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
9148 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
9150 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
9151 return DAG.getNode(ISD::BITCAST, dl, VT,
9152 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
9153 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
9161 return DAG.getNode(ISD::BITCAST, dl, VT,
9162 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
9163 DAG.getNode(ISD::BITCAST, dl,
9167 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
9168 /// which could not be matched by any known target speficic shuffle
9170 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9172 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
9173 if (NewOp.getNode())
9176 MVT VT = SVOp->getSimpleValueType(0);
9178 unsigned NumElems = VT.getVectorNumElements();
9179 unsigned NumLaneElems = NumElems / 2;
9182 MVT EltVT = VT.getVectorElementType();
9183 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
9186 SmallVector<int, 16> Mask;
9187 for (unsigned l = 0; l < 2; ++l) {
9188 // Build a shuffle mask for the output, discovering on the fly which
9189 // input vectors to use as shuffle operands (recorded in InputUsed).
9190 // If building a suitable shuffle vector proves too hard, then bail
9191 // out with UseBuildVector set.
9192 bool UseBuildVector = false;
9193 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
9194 unsigned LaneStart = l * NumLaneElems;
9195 for (unsigned i = 0; i != NumLaneElems; ++i) {
9196 // The mask element. This indexes into the input.
9197 int Idx = SVOp->getMaskElt(i+LaneStart);
9199 // the mask element does not index into any input vector.
9204 // The input vector this mask element indexes into.
9205 int Input = Idx / NumLaneElems;
9207 // Turn the index into an offset from the start of the input vector.
9208 Idx -= Input * NumLaneElems;
9210 // Find or create a shuffle vector operand to hold this input.
9212 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
9213 if (InputUsed[OpNo] == Input)
9214 // This input vector is already an operand.
9216 if (InputUsed[OpNo] < 0) {
9217 // Create a new operand for this input vector.
9218 InputUsed[OpNo] = Input;
9223 if (OpNo >= array_lengthof(InputUsed)) {
9224 // More than two input vectors used! Give up on trying to create a
9225 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
9226 UseBuildVector = true;
9230 // Add the mask index for the new shuffle vector.
9231 Mask.push_back(Idx + OpNo * NumLaneElems);
9234 if (UseBuildVector) {
9235 SmallVector<SDValue, 16> SVOps;
9236 for (unsigned i = 0; i != NumLaneElems; ++i) {
9237 // The mask element. This indexes into the input.
9238 int Idx = SVOp->getMaskElt(i+LaneStart);
9240 SVOps.push_back(DAG.getUNDEF(EltVT));
9244 // The input vector this mask element indexes into.
9245 int Input = Idx / NumElems;
9247 // Turn the index into an offset from the start of the input vector.
9248 Idx -= Input * NumElems;
9250 // Extract the vector element by hand.
9251 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
9252 SVOp->getOperand(Input),
9253 DAG.getIntPtrConstant(Idx)));
9256 // Construct the output using a BUILD_VECTOR.
9257 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
9258 } else if (InputUsed[0] < 0) {
9259 // No input vectors were used! The result is undefined.
9260 Output[l] = DAG.getUNDEF(NVT);
9262 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
9263 (InputUsed[0] % 2) * NumLaneElems,
9265 // If only one input was used, use an undefined vector for the other.
9266 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
9267 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
9268 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
9269 // At least one input vector was used. Create a new shuffle vector.
9270 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
9276 // Concatenate the result back
9277 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
9280 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
9281 /// 4 elements, and match them with several different shuffle types.
9283 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9284 SDValue V1 = SVOp->getOperand(0);
9285 SDValue V2 = SVOp->getOperand(1);
9287 MVT VT = SVOp->getSimpleValueType(0);
9289 assert(VT.is128BitVector() && "Unsupported vector size");
9291 std::pair<int, int> Locs[4];
9292 int Mask1[] = { -1, -1, -1, -1 };
9293 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
9297 for (unsigned i = 0; i != 4; ++i) {
9298 int Idx = PermMask[i];
9300 Locs[i] = std::make_pair(-1, -1);
9302 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
9304 Locs[i] = std::make_pair(0, NumLo);
9308 Locs[i] = std::make_pair(1, NumHi);
9310 Mask1[2+NumHi] = Idx;
9316 if (NumLo <= 2 && NumHi <= 2) {
9317 // If no more than two elements come from either vector. This can be
9318 // implemented with two shuffles. First shuffle gather the elements.
9319 // The second shuffle, which takes the first shuffle as both of its
9320 // vector operands, put the elements into the right order.
9321 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9323 int Mask2[] = { -1, -1, -1, -1 };
9325 for (unsigned i = 0; i != 4; ++i)
9326 if (Locs[i].first != -1) {
9327 unsigned Idx = (i < 2) ? 0 : 4;
9328 Idx += Locs[i].first * 2 + Locs[i].second;
9332 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
9335 if (NumLo == 3 || NumHi == 3) {
9336 // Otherwise, we must have three elements from one vector, call it X, and
9337 // one element from the other, call it Y. First, use a shufps to build an
9338 // intermediate vector with the one element from Y and the element from X
9339 // that will be in the same half in the final destination (the indexes don't
9340 // matter). Then, use a shufps to build the final vector, taking the half
9341 // containing the element from Y from the intermediate, and the other half
9344 // Normalize it so the 3 elements come from V1.
9345 CommuteVectorShuffleMask(PermMask, 4);
9349 // Find the element from V2.
9351 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
9352 int Val = PermMask[HiIndex];
9359 Mask1[0] = PermMask[HiIndex];
9361 Mask1[2] = PermMask[HiIndex^1];
9363 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9366 Mask1[0] = PermMask[0];
9367 Mask1[1] = PermMask[1];
9368 Mask1[2] = HiIndex & 1 ? 6 : 4;
9369 Mask1[3] = HiIndex & 1 ? 4 : 6;
9370 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9373 Mask1[0] = HiIndex & 1 ? 2 : 0;
9374 Mask1[1] = HiIndex & 1 ? 0 : 2;
9375 Mask1[2] = PermMask[2];
9376 Mask1[3] = PermMask[3];
9381 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
9384 // Break it into (shuffle shuffle_hi, shuffle_lo).
9385 int LoMask[] = { -1, -1, -1, -1 };
9386 int HiMask[] = { -1, -1, -1, -1 };
9388 int *MaskPtr = LoMask;
9389 unsigned MaskIdx = 0;
9392 for (unsigned i = 0; i != 4; ++i) {
9399 int Idx = PermMask[i];
9401 Locs[i] = std::make_pair(-1, -1);
9402 } else if (Idx < 4) {
9403 Locs[i] = std::make_pair(MaskIdx, LoIdx);
9404 MaskPtr[LoIdx] = Idx;
9407 Locs[i] = std::make_pair(MaskIdx, HiIdx);
9408 MaskPtr[HiIdx] = Idx;
9413 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
9414 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
9415 int MaskOps[] = { -1, -1, -1, -1 };
9416 for (unsigned i = 0; i != 4; ++i)
9417 if (Locs[i].first != -1)
9418 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
9419 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
9422 static bool MayFoldVectorLoad(SDValue V) {
9423 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
9424 V = V.getOperand(0);
9426 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
9427 V = V.getOperand(0);
9428 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
9429 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
9430 // BUILD_VECTOR (load), undef
9431 V = V.getOperand(0);
9433 return MayFoldLoad(V);
9437 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
9438 MVT VT = Op.getSimpleValueType();
9440 // Canonizalize to v2f64.
9441 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
9442 return DAG.getNode(ISD::BITCAST, dl, VT,
9443 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
9448 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
9450 SDValue V1 = Op.getOperand(0);
9451 SDValue V2 = Op.getOperand(1);
9452 MVT VT = Op.getSimpleValueType();
9454 assert(VT != MVT::v2i64 && "unsupported shuffle type");
9456 if (HasSSE2 && VT == MVT::v2f64)
9457 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
9459 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
9460 return DAG.getNode(ISD::BITCAST, dl, VT,
9461 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
9462 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
9463 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
9467 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
9468 SDValue V1 = Op.getOperand(0);
9469 SDValue V2 = Op.getOperand(1);
9470 MVT VT = Op.getSimpleValueType();
9472 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
9473 "unsupported shuffle type");
9475 if (V2.getOpcode() == ISD::UNDEF)
9479 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
9483 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
9484 SDValue V1 = Op.getOperand(0);
9485 SDValue V2 = Op.getOperand(1);
9486 MVT VT = Op.getSimpleValueType();
9487 unsigned NumElems = VT.getVectorNumElements();
9489 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
9490 // operand of these instructions is only memory, so check if there's a
9491 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
9493 bool CanFoldLoad = false;
9495 // Trivial case, when V2 comes from a load.
9496 if (MayFoldVectorLoad(V2))
9499 // When V1 is a load, it can be folded later into a store in isel, example:
9500 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
9502 // (MOVLPSmr addr:$src1, VR128:$src2)
9503 // So, recognize this potential and also use MOVLPS or MOVLPD
9504 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
9507 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9509 if (HasSSE2 && NumElems == 2)
9510 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
9513 // If we don't care about the second element, proceed to use movss.
9514 if (SVOp->getMaskElt(1) != -1)
9515 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
9518 // movl and movlp will both match v2i64, but v2i64 is never matched by
9519 // movl earlier because we make it strict to avoid messing with the movlp load
9520 // folding logic (see the code above getMOVLP call). Match it here then,
9521 // this is horrible, but will stay like this until we move all shuffle
9522 // matching to x86 specific nodes. Note that for the 1st condition all
9523 // types are matched with movsd.
9525 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
9526 // as to remove this logic from here, as much as possible
9527 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
9528 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9529 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9532 assert(VT != MVT::v4i32 && "unsupported shuffle type");
9534 // Invert the operand order and use SHUFPS to match it.
9535 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
9536 getShuffleSHUFImmediate(SVOp), DAG);
9539 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
9540 SelectionDAG &DAG) {
9542 MVT VT = Load->getSimpleValueType(0);
9543 MVT EVT = VT.getVectorElementType();
9544 SDValue Addr = Load->getOperand(1);
9545 SDValue NewAddr = DAG.getNode(
9546 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
9547 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
9550 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
9551 DAG.getMachineFunction().getMachineMemOperand(
9552 Load->getMemOperand(), 0, EVT.getStoreSize()));
9556 // It is only safe to call this function if isINSERTPSMask is true for
9557 // this shufflevector mask.
9558 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
9559 SelectionDAG &DAG) {
9560 // Generate an insertps instruction when inserting an f32 from memory onto a
9561 // v4f32 or when copying a member from one v4f32 to another.
9562 // We also use it for transferring i32 from one register to another,
9563 // since it simply copies the same bits.
9564 // If we're transferring an i32 from memory to a specific element in a
9565 // register, we output a generic DAG that will match the PINSRD
9567 MVT VT = SVOp->getSimpleValueType(0);
9568 MVT EVT = VT.getVectorElementType();
9569 SDValue V1 = SVOp->getOperand(0);
9570 SDValue V2 = SVOp->getOperand(1);
9571 auto Mask = SVOp->getMask();
9572 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9573 "unsupported vector type for insertps/pinsrd");
9575 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
9576 auto FromV2Predicate = [](const int &i) { return i >= 4; };
9577 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
9585 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
9588 // If we have 1 element from each vector, we have to check if we're
9589 // changing V1's element's place. If so, we're done. Otherwise, we
9590 // should assume we're changing V2's element's place and behave
9592 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
9593 assert(DestIndex <= INT32_MAX && "truncated destination index");
9594 if (FromV1 == FromV2 &&
9595 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
9599 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9602 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
9603 "More than one element from V1 and from V2, or no elements from one "
9604 "of the vectors. This case should not have returned true from "
9609 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9612 // Get an index into the source vector in the range [0,4) (the mask is
9613 // in the range [0,8) because it can address V1 and V2)
9614 unsigned SrcIndex = Mask[DestIndex] % 4;
9615 if (MayFoldLoad(From)) {
9616 // Trivial case, when From comes from a load and is only used by the
9617 // shuffle. Make it use insertps from the vector that we need from that
9620 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
9621 if (!NewLoad.getNode())
9624 if (EVT == MVT::f32) {
9625 // Create this as a scalar to vector to match the instruction pattern.
9626 SDValue LoadScalarToVector =
9627 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
9628 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
9629 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
9631 } else { // EVT == MVT::i32
9632 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
9633 // instruction, to match the PINSRD instruction, which loads an i32 to a
9634 // certain vector element.
9635 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
9636 DAG.getConstant(DestIndex, MVT::i32));
9640 // Vector-element-to-vector
9641 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
9642 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
9645 // Reduce a vector shuffle to zext.
9646 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
9647 SelectionDAG &DAG) {
9648 // PMOVZX is only available from SSE41.
9649 if (!Subtarget->hasSSE41())
9652 MVT VT = Op.getSimpleValueType();
9654 // Only AVX2 support 256-bit vector integer extending.
9655 if (!Subtarget->hasInt256() && VT.is256BitVector())
9658 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9660 SDValue V1 = Op.getOperand(0);
9661 SDValue V2 = Op.getOperand(1);
9662 unsigned NumElems = VT.getVectorNumElements();
9664 // Extending is an unary operation and the element type of the source vector
9665 // won't be equal to or larger than i64.
9666 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9667 VT.getVectorElementType() == MVT::i64)
9670 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
9671 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9672 while ((1U << Shift) < NumElems) {
9673 if (SVOp->getMaskElt(1U << Shift) == 1)
9676 // The maximal ratio is 8, i.e. from i8 to i64.
9681 // Check the shuffle mask.
9682 unsigned Mask = (1U << Shift) - 1;
9683 for (unsigned i = 0; i != NumElems; ++i) {
9684 int EltIdx = SVOp->getMaskElt(i);
9685 if ((i & Mask) != 0 && EltIdx != -1)
9687 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
9691 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
9692 MVT NeVT = MVT::getIntegerVT(NBits);
9693 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
9695 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
9698 // Simplify the operand as it's prepared to be fed into shuffle.
9699 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
9700 if (V1.getOpcode() == ISD::BITCAST &&
9701 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
9702 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
9703 V1.getOperand(0).getOperand(0)
9704 .getSimpleValueType().getSizeInBits() == SignificantBits) {
9705 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
9706 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
9707 ConstantSDNode *CIdx =
9708 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
9709 // If it's foldable, i.e. normal load with single use, we will let code
9710 // selection to fold it. Otherwise, we will short the conversion sequence.
9711 if (CIdx && CIdx->getZExtValue() == 0 &&
9712 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
9713 MVT FullVT = V.getSimpleValueType();
9714 MVT V1VT = V1.getSimpleValueType();
9715 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
9716 // The "ext_vec_elt" node is wider than the result node.
9717 // In this case we should extract subvector from V.
9718 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
9719 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
9720 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
9721 FullVT.getVectorNumElements()/Ratio);
9722 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
9723 DAG.getIntPtrConstant(0));
9725 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
9729 return DAG.getNode(ISD::BITCAST, DL, VT,
9730 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
9733 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9734 SelectionDAG &DAG) {
9735 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9736 MVT VT = Op.getSimpleValueType();
9738 SDValue V1 = Op.getOperand(0);
9739 SDValue V2 = Op.getOperand(1);
9741 if (isZeroShuffle(SVOp))
9742 return getZeroVector(VT, Subtarget, DAG, dl);
9744 // Handle splat operations
9745 if (SVOp->isSplat()) {
9746 // Use vbroadcast whenever the splat comes from a foldable load
9747 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
9748 if (Broadcast.getNode())
9752 // Check integer expanding shuffles.
9753 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
9754 if (NewOp.getNode())
9757 // If the shuffle can be profitably rewritten as a narrower shuffle, then
9759 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9761 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9762 if (NewOp.getNode())
9763 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
9764 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
9765 // FIXME: Figure out a cleaner way to do this.
9766 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
9767 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9768 if (NewOp.getNode()) {
9769 MVT NewVT = NewOp.getSimpleValueType();
9770 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
9771 NewVT, true, false))
9772 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
9775 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
9776 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9777 if (NewOp.getNode()) {
9778 MVT NewVT = NewOp.getSimpleValueType();
9779 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
9780 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
9789 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
9790 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9791 SDValue V1 = Op.getOperand(0);
9792 SDValue V2 = Op.getOperand(1);
9793 MVT VT = Op.getSimpleValueType();
9795 unsigned NumElems = VT.getVectorNumElements();
9796 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9797 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9798 bool V1IsSplat = false;
9799 bool V2IsSplat = false;
9800 bool HasSSE2 = Subtarget->hasSSE2();
9801 bool HasFp256 = Subtarget->hasFp256();
9802 bool HasInt256 = Subtarget->hasInt256();
9803 MachineFunction &MF = DAG.getMachineFunction();
9804 bool OptForSize = MF.getFunction()->getAttributes().
9805 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
9807 // Check if we should use the experimental vector shuffle lowering. If so,
9808 // delegate completely to that code path.
9809 if (ExperimentalVectorShuffleLowering)
9810 return lowerVectorShuffle(Op, Subtarget, DAG);
9812 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9814 if (V1IsUndef && V2IsUndef)
9815 return DAG.getUNDEF(VT);
9817 // When we create a shuffle node we put the UNDEF node to second operand,
9818 // but in some cases the first operand may be transformed to UNDEF.
9819 // In this case we should just commute the node.
9821 return DAG.getCommutedVectorShuffle(*SVOp);
9823 // Vector shuffle lowering takes 3 steps:
9825 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
9826 // narrowing and commutation of operands should be handled.
9827 // 2) Matching of shuffles with known shuffle masks to x86 target specific
9829 // 3) Rewriting of unmatched masks into new generic shuffle operations,
9830 // so the shuffle can be broken into other shuffles and the legalizer can
9831 // try the lowering again.
9833 // The general idea is that no vector_shuffle operation should be left to
9834 // be matched during isel, all of them must be converted to a target specific
9837 // Normalize the input vectors. Here splats, zeroed vectors, profitable
9838 // narrowing and commutation of operands should be handled. The actual code
9839 // doesn't include all of those, work in progress...
9840 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
9841 if (NewOp.getNode())
9844 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
9846 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
9847 // unpckh_undef). Only use pshufd if speed is more important than size.
9848 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9849 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9850 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9851 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9853 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
9854 V2IsUndef && MayFoldVectorLoad(V1))
9855 return getMOVDDup(Op, dl, V1, DAG);
9857 if (isMOVHLPS_v_undef_Mask(M, VT))
9858 return getMOVHighToLow(Op, dl, DAG);
9860 // Use to match splats
9861 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
9862 (VT == MVT::v2f64 || VT == MVT::v2i64))
9863 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9865 if (isPSHUFDMask(M, VT)) {
9866 // The actual implementation will match the mask in the if above and then
9867 // during isel it can match several different instructions, not only pshufd
9868 // as its name says, sad but true, emulate the behavior for now...
9869 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
9870 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
9872 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
9874 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
9875 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
9877 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
9878 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
9881 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
9885 if (isPALIGNRMask(M, VT, Subtarget))
9886 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
9887 getShufflePALIGNRImmediate(SVOp),
9890 if (isVALIGNMask(M, VT, Subtarget))
9891 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
9892 getShuffleVALIGNImmediate(SVOp),
9895 // Check if this can be converted into a logical shift.
9896 bool isLeft = false;
9899 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
9900 if (isShift && ShVal.hasOneUse()) {
9901 // If the shifted value has multiple uses, it may be cheaper to use
9902 // v_set0 + movlhps or movhlps, etc.
9903 MVT EltVT = VT.getVectorElementType();
9904 ShAmt *= EltVT.getSizeInBits();
9905 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9908 if (isMOVLMask(M, VT)) {
9909 if (ISD::isBuildVectorAllZeros(V1.getNode()))
9910 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
9911 if (!isMOVLPMask(M, VT)) {
9912 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
9913 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9915 if (VT == MVT::v4i32 || VT == MVT::v4f32)
9916 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9920 // FIXME: fold these into legal mask.
9921 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
9922 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
9924 if (isMOVHLPSMask(M, VT))
9925 return getMOVHighToLow(Op, dl, DAG);
9927 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
9928 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
9930 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
9931 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
9933 if (isMOVLPMask(M, VT))
9934 return getMOVLP(Op, dl, DAG, HasSSE2);
9936 if (ShouldXformToMOVHLPS(M, VT) ||
9937 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
9938 return DAG.getCommutedVectorShuffle(*SVOp);
9941 // No better options. Use a vshldq / vsrldq.
9942 MVT EltVT = VT.getVectorElementType();
9943 ShAmt *= EltVT.getSizeInBits();
9944 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9947 bool Commuted = false;
9948 // FIXME: This should also accept a bitcast of a splat? Be careful, not
9949 // 1,1,1,1 -> v8i16 though.
9950 BitVector UndefElements;
9951 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
9952 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9954 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
9955 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9958 // Canonicalize the splat or undef, if present, to be on the RHS.
9959 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
9960 CommuteVectorShuffleMask(M, NumElems);
9962 std::swap(V1IsSplat, V2IsSplat);
9966 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
9967 // Shuffling low element of v1 into undef, just return v1.
9970 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
9971 // the instruction selector will not match, so get a canonical MOVL with
9972 // swapped operands to undo the commute.
9973 return getMOVL(DAG, dl, VT, V2, V1);
9976 if (isUNPCKLMask(M, VT, HasInt256))
9977 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9979 if (isUNPCKHMask(M, VT, HasInt256))
9980 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9983 // Normalize mask so all entries that point to V2 points to its first
9984 // element then try to match unpck{h|l} again. If match, return a
9985 // new vector_shuffle with the corrected mask.p
9986 SmallVector<int, 8> NewMask(M.begin(), M.end());
9987 NormalizeMask(NewMask, NumElems);
9988 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
9989 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9990 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
9991 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9995 // Commute is back and try unpck* again.
9996 // FIXME: this seems wrong.
9997 CommuteVectorShuffleMask(M, NumElems);
9999 std::swap(V1IsSplat, V2IsSplat);
10001 if (isUNPCKLMask(M, VT, HasInt256))
10002 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10004 if (isUNPCKHMask(M, VT, HasInt256))
10005 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10008 // Normalize the node to match x86 shuffle ops if needed
10009 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
10010 return DAG.getCommutedVectorShuffle(*SVOp);
10012 // The checks below are all present in isShuffleMaskLegal, but they are
10013 // inlined here right now to enable us to directly emit target specific
10014 // nodes, and remove one by one until they don't return Op anymore.
10016 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
10017 SVOp->getSplatIndex() == 0 && V2IsUndef) {
10018 if (VT == MVT::v2f64 || VT == MVT::v2i64)
10019 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10022 if (isPSHUFHWMask(M, VT, HasInt256))
10023 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
10024 getShufflePSHUFHWImmediate(SVOp),
10027 if (isPSHUFLWMask(M, VT, HasInt256))
10028 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
10029 getShufflePSHUFLWImmediate(SVOp),
10032 unsigned MaskValue;
10033 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
10035 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
10037 if (isSHUFPMask(M, VT))
10038 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
10039 getShuffleSHUFImmediate(SVOp), DAG);
10041 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10042 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10043 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10044 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10046 //===--------------------------------------------------------------------===//
10047 // Generate target specific nodes for 128 or 256-bit shuffles only
10048 // supported in the AVX instruction set.
10051 // Handle VMOVDDUPY permutations
10052 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
10053 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
10055 // Handle VPERMILPS/D* permutations
10056 if (isVPERMILPMask(M, VT)) {
10057 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
10058 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
10059 getShuffleSHUFImmediate(SVOp), DAG);
10060 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
10061 getShuffleSHUFImmediate(SVOp), DAG);
10065 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
10066 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
10067 Idx*(NumElems/2), DAG, dl);
10069 // Handle VPERM2F128/VPERM2I128 permutations
10070 if (isVPERM2X128Mask(M, VT, HasFp256))
10071 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
10072 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
10074 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
10075 return getINSERTPS(SVOp, dl, DAG);
10078 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
10079 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
10081 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
10082 VT.is512BitVector()) {
10083 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
10084 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
10085 SmallVector<SDValue, 16> permclMask;
10086 for (unsigned i = 0; i != NumElems; ++i) {
10087 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
10090 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
10092 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
10093 return DAG.getNode(X86ISD::VPERMV, dl, VT,
10094 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
10095 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
10096 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
10099 //===--------------------------------------------------------------------===//
10100 // Since no target specific shuffle was selected for this generic one,
10101 // lower it into other known shuffles. FIXME: this isn't true yet, but
10102 // this is the plan.
10105 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
10106 if (VT == MVT::v8i16) {
10107 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
10108 if (NewOp.getNode())
10112 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
10113 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
10114 if (NewOp.getNode())
10118 if (VT == MVT::v16i8) {
10119 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
10120 if (NewOp.getNode())
10124 if (VT == MVT::v32i8) {
10125 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
10126 if (NewOp.getNode())
10130 // Handle all 128-bit wide vectors with 4 elements, and match them with
10131 // several different shuffle types.
10132 if (NumElems == 4 && VT.is128BitVector())
10133 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
10135 // Handle general 256-bit shuffles
10136 if (VT.is256BitVector())
10137 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
10142 // This function assumes its argument is a BUILD_VECTOR of constants or
10143 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10145 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10146 unsigned &MaskValue) {
10148 unsigned NumElems = BuildVector->getNumOperands();
10149 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10150 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10151 unsigned NumElemsInLane = NumElems / NumLanes;
10153 // Blend for v16i16 should be symetric for the both lanes.
10154 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10155 SDValue EltCond = BuildVector->getOperand(i);
10156 SDValue SndLaneEltCond =
10157 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10159 int Lane1Cond = -1, Lane2Cond = -1;
10160 if (isa<ConstantSDNode>(EltCond))
10161 Lane1Cond = !isZero(EltCond);
10162 if (isa<ConstantSDNode>(SndLaneEltCond))
10163 Lane2Cond = !isZero(SndLaneEltCond);
10165 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10166 // Lane1Cond != 0, means we want the first argument.
10167 // Lane1Cond == 0, means we want the second argument.
10168 // The encoding of this argument is 0 for the first argument, 1
10169 // for the second. Therefore, invert the condition.
10170 MaskValue |= !Lane1Cond << i;
10171 else if (Lane1Cond < 0)
10172 MaskValue |= !Lane2Cond << i;
10179 // Try to lower a vselect node into a simple blend instruction.
10180 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
10181 SelectionDAG &DAG) {
10182 SDValue Cond = Op.getOperand(0);
10183 SDValue LHS = Op.getOperand(1);
10184 SDValue RHS = Op.getOperand(2);
10186 MVT VT = Op.getSimpleValueType();
10187 MVT EltVT = VT.getVectorElementType();
10188 unsigned NumElems = VT.getVectorNumElements();
10190 // There is no blend with immediate in AVX-512.
10191 if (VT.is512BitVector())
10194 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
10196 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
10199 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10202 // Check the mask for BLEND and build the value.
10203 unsigned MaskValue = 0;
10204 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
10207 // Convert i32 vectors to floating point if it is not AVX2.
10208 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10210 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10211 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10213 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
10214 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
10217 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
10218 DAG.getConstant(MaskValue, MVT::i32));
10219 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10222 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10223 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
10224 if (BlendOp.getNode())
10227 // Some types for vselect were previously set to Expand, not Legal or
10228 // Custom. Return an empty SDValue so we fall-through to Expand, after
10229 // the Custom lowering phase.
10230 MVT VT = Op.getSimpleValueType();
10231 switch (VT.SimpleTy) {
10239 // We couldn't create a "Blend with immediate" node.
10240 // This node should still be legal, but we'll have to emit a blendv*
10245 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10246 MVT VT = Op.getSimpleValueType();
10249 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10252 if (VT.getSizeInBits() == 8) {
10253 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10254 Op.getOperand(0), Op.getOperand(1));
10255 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10256 DAG.getValueType(VT));
10257 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10260 if (VT.getSizeInBits() == 16) {
10261 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10262 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10264 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10265 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10266 DAG.getNode(ISD::BITCAST, dl,
10269 Op.getOperand(1)));
10270 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10271 Op.getOperand(0), Op.getOperand(1));
10272 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10273 DAG.getValueType(VT));
10274 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10277 if (VT == MVT::f32) {
10278 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10279 // the result back to FR32 register. It's only worth matching if the
10280 // result has a single use which is a store or a bitcast to i32. And in
10281 // the case of a store, it's not worth it if the index is a constant 0,
10282 // because a MOVSSmr can be used instead, which is smaller and faster.
10283 if (!Op.hasOneUse())
10285 SDNode *User = *Op.getNode()->use_begin();
10286 if ((User->getOpcode() != ISD::STORE ||
10287 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10288 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10289 (User->getOpcode() != ISD::BITCAST ||
10290 User->getValueType(0) != MVT::i32))
10292 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10293 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10296 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10299 if (VT == MVT::i32 || VT == MVT::i64) {
10300 // ExtractPS/pextrq works with constant index.
10301 if (isa<ConstantSDNode>(Op.getOperand(1)))
10307 /// Extract one bit from mask vector, like v16i1 or v8i1.
10308 /// AVX-512 feature.
10310 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10311 SDValue Vec = Op.getOperand(0);
10313 MVT VecVT = Vec.getSimpleValueType();
10314 SDValue Idx = Op.getOperand(1);
10315 MVT EltVT = Op.getSimpleValueType();
10317 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10319 // variable index can't be handled in mask registers,
10320 // extend vector to VR512
10321 if (!isa<ConstantSDNode>(Idx)) {
10322 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10323 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10324 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10325 ExtVT.getVectorElementType(), Ext, Idx);
10326 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10329 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10330 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10331 unsigned MaxSift = rc->getSize()*8 - 1;
10332 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10333 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10334 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10335 DAG.getConstant(MaxSift, MVT::i8));
10336 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10337 DAG.getIntPtrConstant(0));
10341 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10342 SelectionDAG &DAG) const {
10344 SDValue Vec = Op.getOperand(0);
10345 MVT VecVT = Vec.getSimpleValueType();
10346 SDValue Idx = Op.getOperand(1);
10348 if (Op.getSimpleValueType() == MVT::i1)
10349 return ExtractBitFromMaskVector(Op, DAG);
10351 if (!isa<ConstantSDNode>(Idx)) {
10352 if (VecVT.is512BitVector() ||
10353 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10354 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10357 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10358 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10359 MaskEltVT.getSizeInBits());
10361 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10362 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10363 getZeroVector(MaskVT, Subtarget, DAG, dl),
10364 Idx, DAG.getConstant(0, getPointerTy()));
10365 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10366 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10367 Perm, DAG.getConstant(0, getPointerTy()));
10372 // If this is a 256-bit vector result, first extract the 128-bit vector and
10373 // then extract the element from the 128-bit vector.
10374 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10376 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10377 // Get the 128-bit vector.
10378 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10379 MVT EltVT = VecVT.getVectorElementType();
10381 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10383 //if (IdxVal >= NumElems/2)
10384 // IdxVal -= NumElems/2;
10385 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10386 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10387 DAG.getConstant(IdxVal, MVT::i32));
10390 assert(VecVT.is128BitVector() && "Unexpected vector length");
10392 if (Subtarget->hasSSE41()) {
10393 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10398 MVT VT = Op.getSimpleValueType();
10399 // TODO: handle v16i8.
10400 if (VT.getSizeInBits() == 16) {
10401 SDValue Vec = Op.getOperand(0);
10402 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10404 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10405 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10406 DAG.getNode(ISD::BITCAST, dl,
10408 Op.getOperand(1)));
10409 // Transform it so it match pextrw which produces a 32-bit result.
10410 MVT EltVT = MVT::i32;
10411 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10412 Op.getOperand(0), Op.getOperand(1));
10413 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10414 DAG.getValueType(VT));
10415 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10418 if (VT.getSizeInBits() == 32) {
10419 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10423 // SHUFPS the element to the lowest double word, then movss.
10424 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10425 MVT VVT = Op.getOperand(0).getSimpleValueType();
10426 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10427 DAG.getUNDEF(VVT), Mask);
10428 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10429 DAG.getIntPtrConstant(0));
10432 if (VT.getSizeInBits() == 64) {
10433 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10434 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10435 // to match extract_elt for f64.
10436 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10440 // UNPCKHPD the element to the lowest double word, then movsd.
10441 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10442 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10443 int Mask[2] = { 1, -1 };
10444 MVT VVT = Op.getOperand(0).getSimpleValueType();
10445 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10446 DAG.getUNDEF(VVT), Mask);
10447 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10448 DAG.getIntPtrConstant(0));
10454 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10455 MVT VT = Op.getSimpleValueType();
10456 MVT EltVT = VT.getVectorElementType();
10459 SDValue N0 = Op.getOperand(0);
10460 SDValue N1 = Op.getOperand(1);
10461 SDValue N2 = Op.getOperand(2);
10463 if (!VT.is128BitVector())
10466 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
10467 isa<ConstantSDNode>(N2)) {
10469 if (VT == MVT::v8i16)
10470 Opc = X86ISD::PINSRW;
10471 else if (VT == MVT::v16i8)
10472 Opc = X86ISD::PINSRB;
10474 Opc = X86ISD::PINSRB;
10476 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10478 if (N1.getValueType() != MVT::i32)
10479 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10480 if (N2.getValueType() != MVT::i32)
10481 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10482 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10485 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
10486 // Bits [7:6] of the constant are the source select. This will always be
10487 // zero here. The DAG Combiner may combine an extract_elt index into these
10488 // bits. For example (insert (extract, 3), 2) could be matched by putting
10489 // the '3' into bits [7:6] of X86ISD::INSERTPS.
10490 // Bits [5:4] of the constant are the destination select. This is the
10491 // value of the incoming immediate.
10492 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10493 // combine either bitwise AND or insert of float 0.0 to set these bits.
10494 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
10495 // Create this as a scalar to vector..
10496 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10497 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10500 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
10501 // PINSR* works with constant index.
10507 /// Insert one bit to mask vector, like v16i1 or v8i1.
10508 /// AVX-512 feature.
10510 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10512 SDValue Vec = Op.getOperand(0);
10513 SDValue Elt = Op.getOperand(1);
10514 SDValue Idx = Op.getOperand(2);
10515 MVT VecVT = Vec.getSimpleValueType();
10517 if (!isa<ConstantSDNode>(Idx)) {
10518 // Non constant index. Extend source and destination,
10519 // insert element and then truncate the result.
10520 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10521 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10522 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10523 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10524 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10525 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10528 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10529 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10530 if (Vec.getOpcode() == ISD::UNDEF)
10531 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10532 DAG.getConstant(IdxVal, MVT::i8));
10533 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10534 unsigned MaxSift = rc->getSize()*8 - 1;
10535 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10536 DAG.getConstant(MaxSift, MVT::i8));
10537 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10538 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10539 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10542 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
10543 MVT VT = Op.getSimpleValueType();
10544 MVT EltVT = VT.getVectorElementType();
10546 if (EltVT == MVT::i1)
10547 return InsertBitToMaskVector(Op, DAG);
10550 SDValue N0 = Op.getOperand(0);
10551 SDValue N1 = Op.getOperand(1);
10552 SDValue N2 = Op.getOperand(2);
10554 // If this is a 256-bit vector result, first extract the 128-bit vector,
10555 // insert the element into the extracted half and then place it back.
10556 if (VT.is256BitVector() || VT.is512BitVector()) {
10557 if (!isa<ConstantSDNode>(N2))
10560 // Get the desired 128-bit vector half.
10561 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
10562 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10564 // Insert the element into the desired half.
10565 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
10566 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
10568 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10569 DAG.getConstant(IdxIn128, MVT::i32));
10571 // Insert the changed part back to the 256-bit vector
10572 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10575 if (Subtarget->hasSSE41())
10576 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
10578 if (EltVT == MVT::i8)
10581 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
10582 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10583 // as its second argument.
10584 if (N1.getValueType() != MVT::i32)
10585 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10586 if (N2.getValueType() != MVT::i32)
10587 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10588 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10593 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10595 MVT OpVT = Op.getSimpleValueType();
10597 // If this is a 256-bit vector result, first insert into a 128-bit
10598 // vector and then insert into the 256-bit vector.
10599 if (!OpVT.is128BitVector()) {
10600 // Insert into a 128-bit vector.
10601 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10602 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10603 OpVT.getVectorNumElements() / SizeFactor);
10605 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10607 // Insert the 128-bit vector.
10608 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10611 if (OpVT == MVT::v1i64 &&
10612 Op.getOperand(0).getValueType() == MVT::i64)
10613 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10615 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10616 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10617 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10618 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10621 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10622 // a simple subregister reference or explicit instructions to grab
10623 // upper bits of a vector.
10624 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10625 SelectionDAG &DAG) {
10627 SDValue In = Op.getOperand(0);
10628 SDValue Idx = Op.getOperand(1);
10629 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10630 MVT ResVT = Op.getSimpleValueType();
10631 MVT InVT = In.getSimpleValueType();
10633 if (Subtarget->hasFp256()) {
10634 if (ResVT.is128BitVector() &&
10635 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10636 isa<ConstantSDNode>(Idx)) {
10637 return Extract128BitVector(In, IdxVal, DAG, dl);
10639 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10640 isa<ConstantSDNode>(Idx)) {
10641 return Extract256BitVector(In, IdxVal, DAG, dl);
10647 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10648 // simple superregister reference or explicit instructions to insert
10649 // the upper bits of a vector.
10650 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10651 SelectionDAG &DAG) {
10652 if (Subtarget->hasFp256()) {
10653 SDLoc dl(Op.getNode());
10654 SDValue Vec = Op.getNode()->getOperand(0);
10655 SDValue SubVec = Op.getNode()->getOperand(1);
10656 SDValue Idx = Op.getNode()->getOperand(2);
10658 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
10659 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
10660 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
10661 isa<ConstantSDNode>(Idx)) {
10662 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10663 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10666 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
10667 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
10668 isa<ConstantSDNode>(Idx)) {
10669 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10670 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10676 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10677 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10678 // one of the above mentioned nodes. It has to be wrapped because otherwise
10679 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10680 // be used to form addressing mode. These wrapped nodes will be selected
10683 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10684 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10686 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10687 // global base reg.
10688 unsigned char OpFlag = 0;
10689 unsigned WrapperKind = X86ISD::Wrapper;
10690 CodeModel::Model M = DAG.getTarget().getCodeModel();
10692 if (Subtarget->isPICStyleRIPRel() &&
10693 (M == CodeModel::Small || M == CodeModel::Kernel))
10694 WrapperKind = X86ISD::WrapperRIP;
10695 else if (Subtarget->isPICStyleGOT())
10696 OpFlag = X86II::MO_GOTOFF;
10697 else if (Subtarget->isPICStyleStubPIC())
10698 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10700 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10701 CP->getAlignment(),
10702 CP->getOffset(), OpFlag);
10704 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10705 // With PIC, the address is actually $g + Offset.
10707 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10708 DAG.getNode(X86ISD::GlobalBaseReg,
10709 SDLoc(), getPointerTy()),
10716 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10717 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10719 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10720 // global base reg.
10721 unsigned char OpFlag = 0;
10722 unsigned WrapperKind = X86ISD::Wrapper;
10723 CodeModel::Model M = DAG.getTarget().getCodeModel();
10725 if (Subtarget->isPICStyleRIPRel() &&
10726 (M == CodeModel::Small || M == CodeModel::Kernel))
10727 WrapperKind = X86ISD::WrapperRIP;
10728 else if (Subtarget->isPICStyleGOT())
10729 OpFlag = X86II::MO_GOTOFF;
10730 else if (Subtarget->isPICStyleStubPIC())
10731 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10733 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10736 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10738 // With PIC, the address is actually $g + Offset.
10740 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10741 DAG.getNode(X86ISD::GlobalBaseReg,
10742 SDLoc(), getPointerTy()),
10749 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10750 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10752 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10753 // global base reg.
10754 unsigned char OpFlag = 0;
10755 unsigned WrapperKind = X86ISD::Wrapper;
10756 CodeModel::Model M = DAG.getTarget().getCodeModel();
10758 if (Subtarget->isPICStyleRIPRel() &&
10759 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10760 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10761 OpFlag = X86II::MO_GOTPCREL;
10762 WrapperKind = X86ISD::WrapperRIP;
10763 } else if (Subtarget->isPICStyleGOT()) {
10764 OpFlag = X86II::MO_GOT;
10765 } else if (Subtarget->isPICStyleStubPIC()) {
10766 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10767 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10768 OpFlag = X86II::MO_DARWIN_NONLAZY;
10771 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10774 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10776 // With PIC, the address is actually $g + Offset.
10777 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10778 !Subtarget->is64Bit()) {
10779 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10780 DAG.getNode(X86ISD::GlobalBaseReg,
10781 SDLoc(), getPointerTy()),
10785 // For symbols that require a load from a stub to get the address, emit the
10787 if (isGlobalStubReference(OpFlag))
10788 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10789 MachinePointerInfo::getGOT(), false, false, false, 0);
10795 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10796 // Create the TargetBlockAddressAddress node.
10797 unsigned char OpFlags =
10798 Subtarget->ClassifyBlockAddressReference();
10799 CodeModel::Model M = DAG.getTarget().getCodeModel();
10800 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10801 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10803 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10806 if (Subtarget->isPICStyleRIPRel() &&
10807 (M == CodeModel::Small || M == CodeModel::Kernel))
10808 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10810 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10812 // With PIC, the address is actually $g + Offset.
10813 if (isGlobalRelativeToPICBase(OpFlags)) {
10814 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10815 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10823 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10824 int64_t Offset, SelectionDAG &DAG) const {
10825 // Create the TargetGlobalAddress node, folding in the constant
10826 // offset if it is legal.
10827 unsigned char OpFlags =
10828 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10829 CodeModel::Model M = DAG.getTarget().getCodeModel();
10831 if (OpFlags == X86II::MO_NO_FLAG &&
10832 X86::isOffsetSuitableForCodeModel(Offset, M)) {
10833 // A direct static reference to a global.
10834 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
10837 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
10840 if (Subtarget->isPICStyleRIPRel() &&
10841 (M == CodeModel::Small || M == CodeModel::Kernel))
10842 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10844 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10846 // With PIC, the address is actually $g + Offset.
10847 if (isGlobalRelativeToPICBase(OpFlags)) {
10848 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10849 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10853 // For globals that require a load from a stub to get the address, emit the
10855 if (isGlobalStubReference(OpFlags))
10856 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
10857 MachinePointerInfo::getGOT(), false, false, false, 0);
10859 // If there was a non-zero offset that we didn't fold, create an explicit
10860 // addition for it.
10862 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
10863 DAG.getConstant(Offset, getPointerTy()));
10869 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
10870 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
10871 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
10872 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
10876 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
10877 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
10878 unsigned char OperandFlags, bool LocalDynamic = false) {
10879 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10880 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10882 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10883 GA->getValueType(0),
10887 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
10891 SDValue Ops[] = { Chain, TGA, *InFlag };
10892 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10894 SDValue Ops[] = { Chain, TGA };
10895 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10898 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
10899 MFI->setAdjustsStack(true);
10901 SDValue Flag = Chain.getValue(1);
10902 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
10905 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
10907 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10910 SDLoc dl(GA); // ? function entry point might be better
10911 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10912 DAG.getNode(X86ISD::GlobalBaseReg,
10913 SDLoc(), PtrVT), InFlag);
10914 InFlag = Chain.getValue(1);
10916 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
10919 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
10921 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10923 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
10924 X86::RAX, X86II::MO_TLSGD);
10927 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
10933 // Get the start address of the TLS block for this module.
10934 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
10935 .getInfo<X86MachineFunctionInfo>();
10936 MFI->incNumLocalDynamicTLSAccesses();
10940 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
10941 X86II::MO_TLSLD, /*LocalDynamic=*/true);
10944 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10945 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
10946 InFlag = Chain.getValue(1);
10947 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
10948 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
10951 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
10955 unsigned char OperandFlags = X86II::MO_DTPOFF;
10956 unsigned WrapperKind = X86ISD::Wrapper;
10957 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10958 GA->getValueType(0),
10959 GA->getOffset(), OperandFlags);
10960 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10962 // Add x@dtpoff with the base.
10963 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
10966 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
10967 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10968 const EVT PtrVT, TLSModel::Model model,
10969 bool is64Bit, bool isPIC) {
10972 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
10973 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
10974 is64Bit ? 257 : 256));
10976 SDValue ThreadPointer =
10977 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
10978 MachinePointerInfo(Ptr), false, false, false, 0);
10980 unsigned char OperandFlags = 0;
10981 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
10983 unsigned WrapperKind = X86ISD::Wrapper;
10984 if (model == TLSModel::LocalExec) {
10985 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
10986 } else if (model == TLSModel::InitialExec) {
10988 OperandFlags = X86II::MO_GOTTPOFF;
10989 WrapperKind = X86ISD::WrapperRIP;
10991 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
10994 llvm_unreachable("Unexpected model");
10997 // emit "addl x@ntpoff,%eax" (local exec)
10998 // or "addl x@indntpoff,%eax" (initial exec)
10999 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11001 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11002 GA->getOffset(), OperandFlags);
11003 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11005 if (model == TLSModel::InitialExec) {
11006 if (isPIC && !is64Bit) {
11007 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11008 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11012 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11013 MachinePointerInfo::getGOT(), false, false, false, 0);
11016 // The address of the thread local variable is the add of the thread
11017 // pointer with the offset of the variable.
11018 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11022 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11024 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11025 const GlobalValue *GV = GA->getGlobal();
11027 if (Subtarget->isTargetELF()) {
11028 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11031 case TLSModel::GeneralDynamic:
11032 if (Subtarget->is64Bit())
11033 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11034 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11035 case TLSModel::LocalDynamic:
11036 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11037 Subtarget->is64Bit());
11038 case TLSModel::InitialExec:
11039 case TLSModel::LocalExec:
11040 return LowerToTLSExecModel(
11041 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11042 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11044 llvm_unreachable("Unknown TLS model.");
11047 if (Subtarget->isTargetDarwin()) {
11048 // Darwin only has one model of TLS. Lower to that.
11049 unsigned char OpFlag = 0;
11050 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11051 X86ISD::WrapperRIP : X86ISD::Wrapper;
11053 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11054 // global base reg.
11055 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11056 !Subtarget->is64Bit();
11058 OpFlag = X86II::MO_TLVP_PIC_BASE;
11060 OpFlag = X86II::MO_TLVP;
11062 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11063 GA->getValueType(0),
11064 GA->getOffset(), OpFlag);
11065 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11067 // With PIC32, the address is actually $g + Offset.
11069 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11070 DAG.getNode(X86ISD::GlobalBaseReg,
11071 SDLoc(), getPointerTy()),
11074 // Lowering the machine isd will make sure everything is in the right
11076 SDValue Chain = DAG.getEntryNode();
11077 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11078 SDValue Args[] = { Chain, Offset };
11079 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11081 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11082 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11083 MFI->setAdjustsStack(true);
11085 // And our return value (tls address) is in the standard call return value
11087 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11088 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11089 Chain.getValue(1));
11092 if (Subtarget->isTargetKnownWindowsMSVC() ||
11093 Subtarget->isTargetWindowsGNU()) {
11094 // Just use the implicit TLS architecture
11095 // Need to generate someting similar to:
11096 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11098 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11099 // mov rcx, qword [rdx+rcx*8]
11100 // mov eax, .tls$:tlsvar
11101 // [rax+rcx] contains the address
11102 // Windows 64bit: gs:0x58
11103 // Windows 32bit: fs:__tls_array
11106 SDValue Chain = DAG.getEntryNode();
11108 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11109 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11110 // use its literal value of 0x2C.
11111 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11112 ? Type::getInt8PtrTy(*DAG.getContext(),
11114 : Type::getInt32PtrTy(*DAG.getContext(),
11118 Subtarget->is64Bit()
11119 ? DAG.getIntPtrConstant(0x58)
11120 : (Subtarget->isTargetWindowsGNU()
11121 ? DAG.getIntPtrConstant(0x2C)
11122 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11124 SDValue ThreadPointer =
11125 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11126 MachinePointerInfo(Ptr), false, false, false, 0);
11128 // Load the _tls_index variable
11129 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11130 if (Subtarget->is64Bit())
11131 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11132 IDX, MachinePointerInfo(), MVT::i32,
11133 false, false, false, 0);
11135 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11136 false, false, false, 0);
11138 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
11140 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11142 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11143 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11144 false, false, false, 0);
11146 // Get the offset of start of .tls section
11147 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11148 GA->getValueType(0),
11149 GA->getOffset(), X86II::MO_SECREL);
11150 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11152 // The address of the thread local variable is the add of the thread
11153 // pointer with the offset of the variable.
11154 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11157 llvm_unreachable("TLS not implemented for this target.");
11160 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11161 /// and take a 2 x i32 value to shift plus a shift amount.
11162 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11163 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11164 MVT VT = Op.getSimpleValueType();
11165 unsigned VTBits = VT.getSizeInBits();
11167 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11168 SDValue ShOpLo = Op.getOperand(0);
11169 SDValue ShOpHi = Op.getOperand(1);
11170 SDValue ShAmt = Op.getOperand(2);
11171 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11172 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11174 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11175 DAG.getConstant(VTBits - 1, MVT::i8));
11176 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11177 DAG.getConstant(VTBits - 1, MVT::i8))
11178 : DAG.getConstant(0, VT);
11180 SDValue Tmp2, Tmp3;
11181 if (Op.getOpcode() == ISD::SHL_PARTS) {
11182 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11183 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11185 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11186 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11189 // If the shift amount is larger or equal than the width of a part we can't
11190 // rely on the results of shld/shrd. Insert a test and select the appropriate
11191 // values for large shift amounts.
11192 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11193 DAG.getConstant(VTBits, MVT::i8));
11194 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11195 AndNode, DAG.getConstant(0, MVT::i8));
11198 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11199 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11200 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11202 if (Op.getOpcode() == ISD::SHL_PARTS) {
11203 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11204 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11206 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11207 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11210 SDValue Ops[2] = { Lo, Hi };
11211 return DAG.getMergeValues(Ops, dl);
11214 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11215 SelectionDAG &DAG) const {
11216 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11218 if (SrcVT.isVector())
11221 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11222 "Unknown SINT_TO_FP to lower!");
11224 // These are really Legal; return the operand so the caller accepts it as
11226 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11228 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11229 Subtarget->is64Bit()) {
11234 unsigned Size = SrcVT.getSizeInBits()/8;
11235 MachineFunction &MF = DAG.getMachineFunction();
11236 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11237 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11238 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11240 MachinePointerInfo::getFixedStack(SSFI),
11242 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11245 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11247 SelectionDAG &DAG) const {
11251 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11253 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11255 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11257 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11259 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11260 MachineMemOperand *MMO;
11262 int SSFI = FI->getIndex();
11264 DAG.getMachineFunction()
11265 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11266 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11268 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11269 StackSlot = StackSlot.getOperand(1);
11271 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11272 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11274 Tys, Ops, SrcVT, MMO);
11277 Chain = Result.getValue(1);
11278 SDValue InFlag = Result.getValue(2);
11280 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11281 // shouldn't be necessary except that RFP cannot be live across
11282 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11283 MachineFunction &MF = DAG.getMachineFunction();
11284 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11285 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11286 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11287 Tys = DAG.getVTList(MVT::Other);
11289 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11291 MachineMemOperand *MMO =
11292 DAG.getMachineFunction()
11293 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11294 MachineMemOperand::MOStore, SSFISize, SSFISize);
11296 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11297 Ops, Op.getValueType(), MMO);
11298 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11299 MachinePointerInfo::getFixedStack(SSFI),
11300 false, false, false, 0);
11306 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11307 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11308 SelectionDAG &DAG) const {
11309 // This algorithm is not obvious. Here it is what we're trying to output:
11312 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11313 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11315 haddpd %xmm0, %xmm0
11317 pshufd $0x4e, %xmm0, %xmm1
11323 LLVMContext *Context = DAG.getContext();
11325 // Build some magic constants.
11326 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11327 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11328 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11330 SmallVector<Constant*,2> CV1;
11332 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11333 APInt(64, 0x4330000000000000ULL))));
11335 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11336 APInt(64, 0x4530000000000000ULL))));
11337 Constant *C1 = ConstantVector::get(CV1);
11338 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11340 // Load the 64-bit value into an XMM register.
11341 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11343 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11344 MachinePointerInfo::getConstantPool(),
11345 false, false, false, 16);
11346 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11347 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11350 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11351 MachinePointerInfo::getConstantPool(),
11352 false, false, false, 16);
11353 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11354 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11357 if (Subtarget->hasSSE3()) {
11358 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11359 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11361 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11362 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11364 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11365 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11369 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11370 DAG.getIntPtrConstant(0));
11373 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11374 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11375 SelectionDAG &DAG) const {
11377 // FP constant to bias correct the final result.
11378 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11381 // Load the 32-bit value into an XMM register.
11382 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11385 // Zero out the upper parts of the register.
11386 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11388 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11389 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11390 DAG.getIntPtrConstant(0));
11392 // Or the load with the bias.
11393 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11394 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11395 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11396 MVT::v2f64, Load)),
11397 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11398 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11399 MVT::v2f64, Bias)));
11400 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11401 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11402 DAG.getIntPtrConstant(0));
11404 // Subtract the bias.
11405 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11407 // Handle final rounding.
11408 EVT DestVT = Op.getValueType();
11410 if (DestVT.bitsLT(MVT::f64))
11411 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11412 DAG.getIntPtrConstant(0));
11413 if (DestVT.bitsGT(MVT::f64))
11414 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11416 // Handle final rounding.
11420 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11421 SelectionDAG &DAG) const {
11422 SDValue N0 = Op.getOperand(0);
11423 MVT SVT = N0.getSimpleValueType();
11426 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
11427 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
11428 "Custom UINT_TO_FP is not supported!");
11430 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11431 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11432 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11435 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11436 SelectionDAG &DAG) const {
11437 SDValue N0 = Op.getOperand(0);
11440 if (Op.getValueType().isVector())
11441 return lowerUINT_TO_FP_vec(Op, DAG);
11443 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11444 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11445 // the optimization here.
11446 if (DAG.SignBitIsZero(N0))
11447 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11449 MVT SrcVT = N0.getSimpleValueType();
11450 MVT DstVT = Op.getSimpleValueType();
11451 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11452 return LowerUINT_TO_FP_i64(Op, DAG);
11453 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11454 return LowerUINT_TO_FP_i32(Op, DAG);
11455 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11458 // Make a 64-bit buffer, and use it to build an FILD.
11459 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11460 if (SrcVT == MVT::i32) {
11461 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11462 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11463 getPointerTy(), StackSlot, WordOff);
11464 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11465 StackSlot, MachinePointerInfo(),
11467 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11468 OffsetSlot, MachinePointerInfo(),
11470 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11474 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11475 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11476 StackSlot, MachinePointerInfo(),
11478 // For i64 source, we need to add the appropriate power of 2 if the input
11479 // was negative. This is the same as the optimization in
11480 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11481 // we must be careful to do the computation in x87 extended precision, not
11482 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11483 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11484 MachineMemOperand *MMO =
11485 DAG.getMachineFunction()
11486 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11487 MachineMemOperand::MOLoad, 8, 8);
11489 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11490 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11491 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11494 APInt FF(32, 0x5F800000ULL);
11496 // Check whether the sign bit is set.
11497 SDValue SignSet = DAG.getSetCC(dl,
11498 getSetCCResultType(*DAG.getContext(), MVT::i64),
11499 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11502 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11503 SDValue FudgePtr = DAG.getConstantPool(
11504 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11507 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11508 SDValue Zero = DAG.getIntPtrConstant(0);
11509 SDValue Four = DAG.getIntPtrConstant(4);
11510 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11512 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11514 // Load the value out, extending it from f32 to f80.
11515 // FIXME: Avoid the extend by constructing the right constant pool?
11516 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11517 FudgePtr, MachinePointerInfo::getConstantPool(),
11518 MVT::f32, false, false, false, 4);
11519 // Extend everything to 80 bits to force it to be done on x87.
11520 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11521 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11524 std::pair<SDValue,SDValue>
11525 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11526 bool IsSigned, bool IsReplace) const {
11529 EVT DstTy = Op.getValueType();
11531 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11532 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11536 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11537 DstTy.getSimpleVT() >= MVT::i16 &&
11538 "Unknown FP_TO_INT to lower!");
11540 // These are really Legal.
11541 if (DstTy == MVT::i32 &&
11542 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11543 return std::make_pair(SDValue(), SDValue());
11544 if (Subtarget->is64Bit() &&
11545 DstTy == MVT::i64 &&
11546 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11547 return std::make_pair(SDValue(), SDValue());
11549 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11550 // stack slot, or into the FTOL runtime function.
11551 MachineFunction &MF = DAG.getMachineFunction();
11552 unsigned MemSize = DstTy.getSizeInBits()/8;
11553 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11554 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11557 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11558 Opc = X86ISD::WIN_FTOL;
11560 switch (DstTy.getSimpleVT().SimpleTy) {
11561 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11562 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11563 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11564 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11567 SDValue Chain = DAG.getEntryNode();
11568 SDValue Value = Op.getOperand(0);
11569 EVT TheVT = Op.getOperand(0).getValueType();
11570 // FIXME This causes a redundant load/store if the SSE-class value is already
11571 // in memory, such as if it is on the callstack.
11572 if (isScalarFPTypeInSSEReg(TheVT)) {
11573 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11574 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11575 MachinePointerInfo::getFixedStack(SSFI),
11577 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11579 Chain, StackSlot, DAG.getValueType(TheVT)
11582 MachineMemOperand *MMO =
11583 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11584 MachineMemOperand::MOLoad, MemSize, MemSize);
11585 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11586 Chain = Value.getValue(1);
11587 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11588 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11591 MachineMemOperand *MMO =
11592 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11593 MachineMemOperand::MOStore, MemSize, MemSize);
11595 if (Opc != X86ISD::WIN_FTOL) {
11596 // Build the FP_TO_INT*_IN_MEM
11597 SDValue Ops[] = { Chain, Value, StackSlot };
11598 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11600 return std::make_pair(FIST, StackSlot);
11602 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11603 DAG.getVTList(MVT::Other, MVT::Glue),
11605 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11606 MVT::i32, ftol.getValue(1));
11607 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11608 MVT::i32, eax.getValue(2));
11609 SDValue Ops[] = { eax, edx };
11610 SDValue pair = IsReplace
11611 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11612 : DAG.getMergeValues(Ops, DL);
11613 return std::make_pair(pair, SDValue());
11617 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11618 const X86Subtarget *Subtarget) {
11619 MVT VT = Op->getSimpleValueType(0);
11620 SDValue In = Op->getOperand(0);
11621 MVT InVT = In.getSimpleValueType();
11624 // Optimize vectors in AVX mode:
11627 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11628 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11629 // Concat upper and lower parts.
11632 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11633 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11634 // Concat upper and lower parts.
11637 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11638 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11639 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11642 if (Subtarget->hasInt256())
11643 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11645 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11646 SDValue Undef = DAG.getUNDEF(InVT);
11647 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11648 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11649 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11651 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11652 VT.getVectorNumElements()/2);
11654 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11655 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11657 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11660 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11661 SelectionDAG &DAG) {
11662 MVT VT = Op->getSimpleValueType(0);
11663 SDValue In = Op->getOperand(0);
11664 MVT InVT = In.getSimpleValueType();
11666 unsigned int NumElts = VT.getVectorNumElements();
11667 if (NumElts != 8 && NumElts != 16)
11670 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11671 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11673 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11674 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11675 // Now we have only mask extension
11676 assert(InVT.getVectorElementType() == MVT::i1);
11677 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11678 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11679 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11680 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11681 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11682 MachinePointerInfo::getConstantPool(),
11683 false, false, false, Alignment);
11685 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11686 if (VT.is512BitVector())
11688 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11691 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11692 SelectionDAG &DAG) {
11693 if (Subtarget->hasFp256()) {
11694 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11702 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11703 SelectionDAG &DAG) {
11705 MVT VT = Op.getSimpleValueType();
11706 SDValue In = Op.getOperand(0);
11707 MVT SVT = In.getSimpleValueType();
11709 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11710 return LowerZERO_EXTEND_AVX512(Op, DAG);
11712 if (Subtarget->hasFp256()) {
11713 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11718 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11719 VT.getVectorNumElements() != SVT.getVectorNumElements());
11723 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11725 MVT VT = Op.getSimpleValueType();
11726 SDValue In = Op.getOperand(0);
11727 MVT InVT = In.getSimpleValueType();
11729 if (VT == MVT::i1) {
11730 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11731 "Invalid scalar TRUNCATE operation");
11732 if (InVT == MVT::i32)
11734 if (InVT.getSizeInBits() == 64)
11735 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
11736 else if (InVT.getSizeInBits() < 32)
11737 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11738 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11740 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11741 "Invalid TRUNCATE operation");
11743 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11744 if (VT.getVectorElementType().getSizeInBits() >=8)
11745 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11747 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11748 unsigned NumElts = InVT.getVectorNumElements();
11749 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11750 if (InVT.getSizeInBits() < 512) {
11751 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11752 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11756 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11757 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11758 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11759 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11760 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11761 MachinePointerInfo::getConstantPool(),
11762 false, false, false, Alignment);
11763 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11764 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11765 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11768 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11769 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11770 if (Subtarget->hasInt256()) {
11771 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11772 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11773 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11775 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11776 DAG.getIntPtrConstant(0));
11779 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11780 DAG.getIntPtrConstant(0));
11781 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11782 DAG.getIntPtrConstant(2));
11783 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11784 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11785 static const int ShufMask[] = {0, 2, 4, 6};
11786 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11789 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11790 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11791 if (Subtarget->hasInt256()) {
11792 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11794 SmallVector<SDValue,32> pshufbMask;
11795 for (unsigned i = 0; i < 2; ++i) {
11796 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11797 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11798 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11799 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11800 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11801 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11802 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11803 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11804 for (unsigned j = 0; j < 8; ++j)
11805 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11807 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11808 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11809 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11811 static const int ShufMask[] = {0, 2, -1, -1};
11812 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11814 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11815 DAG.getIntPtrConstant(0));
11816 return DAG.getNode(ISD::BITCAST, DL, VT, In);
11819 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11820 DAG.getIntPtrConstant(0));
11822 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11823 DAG.getIntPtrConstant(4));
11825 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11826 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11828 // The PSHUFB mask:
11829 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11830 -1, -1, -1, -1, -1, -1, -1, -1};
11832 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11833 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11834 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
11836 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11837 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11839 // The MOVLHPS Mask:
11840 static const int ShufMask2[] = {0, 1, 4, 5};
11841 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
11842 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
11845 // Handle truncation of V256 to V128 using shuffles.
11846 if (!VT.is128BitVector() || !InVT.is256BitVector())
11849 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
11851 unsigned NumElems = VT.getVectorNumElements();
11852 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
11854 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
11855 // Prepare truncation shuffle mask
11856 for (unsigned i = 0; i != NumElems; ++i)
11857 MaskVec[i] = i * 2;
11858 SDValue V = DAG.getVectorShuffle(NVT, DL,
11859 DAG.getNode(ISD::BITCAST, DL, NVT, In),
11860 DAG.getUNDEF(NVT), &MaskVec[0]);
11861 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
11862 DAG.getIntPtrConstant(0));
11865 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
11866 SelectionDAG &DAG) const {
11867 assert(!Op.getSimpleValueType().isVector());
11869 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11870 /*IsSigned=*/ true, /*IsReplace=*/ false);
11871 SDValue FIST = Vals.first, StackSlot = Vals.second;
11872 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
11873 if (!FIST.getNode()) return Op;
11875 if (StackSlot.getNode())
11876 // Load the result.
11877 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11878 FIST, StackSlot, MachinePointerInfo(),
11879 false, false, false, 0);
11881 // The node is the result.
11885 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
11886 SelectionDAG &DAG) const {
11887 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11888 /*IsSigned=*/ false, /*IsReplace=*/ false);
11889 SDValue FIST = Vals.first, StackSlot = Vals.second;
11890 assert(FIST.getNode() && "Unexpected failure");
11892 if (StackSlot.getNode())
11893 // Load the result.
11894 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11895 FIST, StackSlot, MachinePointerInfo(),
11896 false, false, false, 0);
11898 // The node is the result.
11902 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
11904 MVT VT = Op.getSimpleValueType();
11905 SDValue In = Op.getOperand(0);
11906 MVT SVT = In.getSimpleValueType();
11908 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
11910 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
11911 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
11912 In, DAG.getUNDEF(SVT)));
11915 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
11916 LLVMContext *Context = DAG.getContext();
11918 MVT VT = Op.getSimpleValueType();
11920 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11921 if (VT.isVector()) {
11922 EltVT = VT.getVectorElementType();
11923 NumElts = VT.getVectorNumElements();
11926 if (EltVT == MVT::f64)
11927 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11928 APInt(64, ~(1ULL << 63))));
11930 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11931 APInt(32, ~(1U << 31))));
11932 C = ConstantVector::getSplat(NumElts, C);
11933 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11934 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11935 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11936 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11937 MachinePointerInfo::getConstantPool(),
11938 false, false, false, Alignment);
11939 if (VT.isVector()) {
11940 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11941 return DAG.getNode(ISD::BITCAST, dl, VT,
11942 DAG.getNode(ISD::AND, dl, ANDVT,
11943 DAG.getNode(ISD::BITCAST, dl, ANDVT,
11945 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
11947 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
11950 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
11951 LLVMContext *Context = DAG.getContext();
11953 MVT VT = Op.getSimpleValueType();
11955 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11956 if (VT.isVector()) {
11957 EltVT = VT.getVectorElementType();
11958 NumElts = VT.getVectorNumElements();
11961 if (EltVT == MVT::f64)
11962 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11963 APInt(64, 1ULL << 63)));
11965 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11966 APInt(32, 1U << 31)));
11967 C = ConstantVector::getSplat(NumElts, C);
11968 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11969 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11970 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11971 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11972 MachinePointerInfo::getConstantPool(),
11973 false, false, false, Alignment);
11974 if (VT.isVector()) {
11975 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
11976 return DAG.getNode(ISD::BITCAST, dl, VT,
11977 DAG.getNode(ISD::XOR, dl, XORVT,
11978 DAG.getNode(ISD::BITCAST, dl, XORVT,
11980 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
11983 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
11986 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
11987 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11988 LLVMContext *Context = DAG.getContext();
11989 SDValue Op0 = Op.getOperand(0);
11990 SDValue Op1 = Op.getOperand(1);
11992 MVT VT = Op.getSimpleValueType();
11993 MVT SrcVT = Op1.getSimpleValueType();
11995 // If second operand is smaller, extend it first.
11996 if (SrcVT.bitsLT(VT)) {
11997 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12000 // And if it is bigger, shrink it first.
12001 if (SrcVT.bitsGT(VT)) {
12002 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12006 // At this point the operands and the result should have the same
12007 // type, and that won't be f80 since that is not custom lowered.
12009 // First get the sign bit of second operand.
12010 SmallVector<Constant*,4> CV;
12011 if (SrcVT == MVT::f64) {
12012 const fltSemantics &Sem = APFloat::IEEEdouble;
12013 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
12014 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12016 const fltSemantics &Sem = APFloat::IEEEsingle;
12017 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
12018 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12019 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12020 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12022 Constant *C = ConstantVector::get(CV);
12023 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12024 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12025 MachinePointerInfo::getConstantPool(),
12026 false, false, false, 16);
12027 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12029 // Shift sign bit right or left if the two operands have different types.
12030 if (SrcVT.bitsGT(VT)) {
12031 // Op0 is MVT::f32, Op1 is MVT::f64.
12032 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
12033 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
12034 DAG.getConstant(32, MVT::i32));
12035 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
12036 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
12037 DAG.getIntPtrConstant(0));
12040 // Clear first operand sign bit.
12042 if (VT == MVT::f64) {
12043 const fltSemantics &Sem = APFloat::IEEEdouble;
12044 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12045 APInt(64, ~(1ULL << 63)))));
12046 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12048 const fltSemantics &Sem = APFloat::IEEEsingle;
12049 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12050 APInt(32, ~(1U << 31)))));
12051 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12052 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12053 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12055 C = ConstantVector::get(CV);
12056 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12057 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12058 MachinePointerInfo::getConstantPool(),
12059 false, false, false, 16);
12060 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
12062 // Or the value with the sign bit.
12063 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12066 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12067 SDValue N0 = Op.getOperand(0);
12069 MVT VT = Op.getSimpleValueType();
12071 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12072 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12073 DAG.getConstant(1, VT));
12074 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
12077 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
12079 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12080 SelectionDAG &DAG) {
12081 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12083 if (!Subtarget->hasSSE41())
12086 if (!Op->hasOneUse())
12089 SDNode *N = Op.getNode();
12092 SmallVector<SDValue, 8> Opnds;
12093 DenseMap<SDValue, unsigned> VecInMap;
12094 SmallVector<SDValue, 8> VecIns;
12095 EVT VT = MVT::Other;
12097 // Recognize a special case where a vector is casted into wide integer to
12099 Opnds.push_back(N->getOperand(0));
12100 Opnds.push_back(N->getOperand(1));
12102 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12103 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12104 // BFS traverse all OR'd operands.
12105 if (I->getOpcode() == ISD::OR) {
12106 Opnds.push_back(I->getOperand(0));
12107 Opnds.push_back(I->getOperand(1));
12108 // Re-evaluate the number of nodes to be traversed.
12109 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12113 // Quit if a non-EXTRACT_VECTOR_ELT
12114 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12117 // Quit if without a constant index.
12118 SDValue Idx = I->getOperand(1);
12119 if (!isa<ConstantSDNode>(Idx))
12122 SDValue ExtractedFromVec = I->getOperand(0);
12123 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12124 if (M == VecInMap.end()) {
12125 VT = ExtractedFromVec.getValueType();
12126 // Quit if not 128/256-bit vector.
12127 if (!VT.is128BitVector() && !VT.is256BitVector())
12129 // Quit if not the same type.
12130 if (VecInMap.begin() != VecInMap.end() &&
12131 VT != VecInMap.begin()->first.getValueType())
12133 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12134 VecIns.push_back(ExtractedFromVec);
12136 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12139 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12140 "Not extracted from 128-/256-bit vector.");
12142 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12144 for (DenseMap<SDValue, unsigned>::const_iterator
12145 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12146 // Quit if not all elements are used.
12147 if (I->second != FullMask)
12151 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12153 // Cast all vectors into TestVT for PTEST.
12154 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12155 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12157 // If more than one full vectors are evaluated, OR them first before PTEST.
12158 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12159 // Each iteration will OR 2 nodes and append the result until there is only
12160 // 1 node left, i.e. the final OR'd value of all vectors.
12161 SDValue LHS = VecIns[Slot];
12162 SDValue RHS = VecIns[Slot + 1];
12163 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12166 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12167 VecIns.back(), VecIns.back());
12170 /// \brief return true if \c Op has a use that doesn't just read flags.
12171 static bool hasNonFlagsUse(SDValue Op) {
12172 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12174 SDNode *User = *UI;
12175 unsigned UOpNo = UI.getOperandNo();
12176 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12177 // Look pass truncate.
12178 UOpNo = User->use_begin().getOperandNo();
12179 User = *User->use_begin();
12182 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12183 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12189 /// Emit nodes that will be selected as "test Op0,Op0", or something
12191 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12192 SelectionDAG &DAG) const {
12193 if (Op.getValueType() == MVT::i1)
12194 // KORTEST instruction should be selected
12195 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12196 DAG.getConstant(0, Op.getValueType()));
12198 // CF and OF aren't always set the way we want. Determine which
12199 // of these we need.
12200 bool NeedCF = false;
12201 bool NeedOF = false;
12204 case X86::COND_A: case X86::COND_AE:
12205 case X86::COND_B: case X86::COND_BE:
12208 case X86::COND_G: case X86::COND_GE:
12209 case X86::COND_L: case X86::COND_LE:
12210 case X86::COND_O: case X86::COND_NO: {
12211 // Check if we really need to set the
12212 // Overflow flag. If NoSignedWrap is present
12213 // that is not actually needed.
12214 switch (Op->getOpcode()) {
12219 const BinaryWithFlagsSDNode *BinNode =
12220 cast<BinaryWithFlagsSDNode>(Op.getNode());
12221 if (BinNode->hasNoSignedWrap())
12231 // See if we can use the EFLAGS value from the operand instead of
12232 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12233 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12234 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12235 // Emit a CMP with 0, which is the TEST pattern.
12236 //if (Op.getValueType() == MVT::i1)
12237 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12238 // DAG.getConstant(0, MVT::i1));
12239 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12240 DAG.getConstant(0, Op.getValueType()));
12242 unsigned Opcode = 0;
12243 unsigned NumOperands = 0;
12245 // Truncate operations may prevent the merge of the SETCC instruction
12246 // and the arithmetic instruction before it. Attempt to truncate the operands
12247 // of the arithmetic instruction and use a reduced bit-width instruction.
12248 bool NeedTruncation = false;
12249 SDValue ArithOp = Op;
12250 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12251 SDValue Arith = Op->getOperand(0);
12252 // Both the trunc and the arithmetic op need to have one user each.
12253 if (Arith->hasOneUse())
12254 switch (Arith.getOpcode()) {
12261 NeedTruncation = true;
12267 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12268 // which may be the result of a CAST. We use the variable 'Op', which is the
12269 // non-casted variable when we check for possible users.
12270 switch (ArithOp.getOpcode()) {
12272 // Due to an isel shortcoming, be conservative if this add is likely to be
12273 // selected as part of a load-modify-store instruction. When the root node
12274 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12275 // uses of other nodes in the match, such as the ADD in this case. This
12276 // leads to the ADD being left around and reselected, with the result being
12277 // two adds in the output. Alas, even if none our users are stores, that
12278 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12279 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12280 // climbing the DAG back to the root, and it doesn't seem to be worth the
12282 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12283 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12284 if (UI->getOpcode() != ISD::CopyToReg &&
12285 UI->getOpcode() != ISD::SETCC &&
12286 UI->getOpcode() != ISD::STORE)
12289 if (ConstantSDNode *C =
12290 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12291 // An add of one will be selected as an INC.
12292 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12293 Opcode = X86ISD::INC;
12298 // An add of negative one (subtract of one) will be selected as a DEC.
12299 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12300 Opcode = X86ISD::DEC;
12306 // Otherwise use a regular EFLAGS-setting add.
12307 Opcode = X86ISD::ADD;
12312 // If we have a constant logical shift that's only used in a comparison
12313 // against zero turn it into an equivalent AND. This allows turning it into
12314 // a TEST instruction later.
12315 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12316 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12317 EVT VT = Op.getValueType();
12318 unsigned BitWidth = VT.getSizeInBits();
12319 unsigned ShAmt = Op->getConstantOperandVal(1);
12320 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12322 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12323 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12324 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12325 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12327 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12328 DAG.getConstant(Mask, VT));
12329 DAG.ReplaceAllUsesWith(Op, New);
12335 // If the primary and result isn't used, don't bother using X86ISD::AND,
12336 // because a TEST instruction will be better.
12337 if (!hasNonFlagsUse(Op))
12343 // Due to the ISEL shortcoming noted above, be conservative if this op is
12344 // likely to be selected as part of a load-modify-store instruction.
12345 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12346 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12347 if (UI->getOpcode() == ISD::STORE)
12350 // Otherwise use a regular EFLAGS-setting instruction.
12351 switch (ArithOp.getOpcode()) {
12352 default: llvm_unreachable("unexpected operator!");
12353 case ISD::SUB: Opcode = X86ISD::SUB; break;
12354 case ISD::XOR: Opcode = X86ISD::XOR; break;
12355 case ISD::AND: Opcode = X86ISD::AND; break;
12357 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12358 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12359 if (EFLAGS.getNode())
12362 Opcode = X86ISD::OR;
12376 return SDValue(Op.getNode(), 1);
12382 // If we found that truncation is beneficial, perform the truncation and
12384 if (NeedTruncation) {
12385 EVT VT = Op.getValueType();
12386 SDValue WideVal = Op->getOperand(0);
12387 EVT WideVT = WideVal.getValueType();
12388 unsigned ConvertedOp = 0;
12389 // Use a target machine opcode to prevent further DAGCombine
12390 // optimizations that may separate the arithmetic operations
12391 // from the setcc node.
12392 switch (WideVal.getOpcode()) {
12394 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12395 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12396 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12397 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12398 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12402 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12403 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12404 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12405 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12406 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12412 // Emit a CMP with 0, which is the TEST pattern.
12413 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12414 DAG.getConstant(0, Op.getValueType()));
12416 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12417 SmallVector<SDValue, 4> Ops;
12418 for (unsigned i = 0; i != NumOperands; ++i)
12419 Ops.push_back(Op.getOperand(i));
12421 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12422 DAG.ReplaceAllUsesWith(Op, New);
12423 return SDValue(New.getNode(), 1);
12426 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12428 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12429 SDLoc dl, SelectionDAG &DAG) const {
12430 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12431 if (C->getAPIntValue() == 0)
12432 return EmitTest(Op0, X86CC, dl, DAG);
12434 if (Op0.getValueType() == MVT::i1)
12435 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12438 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12439 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12440 // Do the comparison at i32 if it's smaller, besides the Atom case.
12441 // This avoids subregister aliasing issues. Keep the smaller reference
12442 // if we're optimizing for size, however, as that'll allow better folding
12443 // of memory operations.
12444 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12445 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
12446 AttributeSet::FunctionIndex, Attribute::MinSize) &&
12447 !Subtarget->isAtom()) {
12448 unsigned ExtendOp =
12449 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12450 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12451 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12453 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12454 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12455 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12457 return SDValue(Sub.getNode(), 1);
12459 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12462 /// Convert a comparison if required by the subtarget.
12463 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12464 SelectionDAG &DAG) const {
12465 // If the subtarget does not support the FUCOMI instruction, floating-point
12466 // comparisons have to be converted.
12467 if (Subtarget->hasCMov() ||
12468 Cmp.getOpcode() != X86ISD::CMP ||
12469 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12470 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12473 // The instruction selector will select an FUCOM instruction instead of
12474 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12475 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12476 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12478 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12479 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12480 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12481 DAG.getConstant(8, MVT::i8));
12482 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12483 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12486 static bool isAllOnes(SDValue V) {
12487 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12488 return C && C->isAllOnesValue();
12491 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12492 /// if it's possible.
12493 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12494 SDLoc dl, SelectionDAG &DAG) const {
12495 SDValue Op0 = And.getOperand(0);
12496 SDValue Op1 = And.getOperand(1);
12497 if (Op0.getOpcode() == ISD::TRUNCATE)
12498 Op0 = Op0.getOperand(0);
12499 if (Op1.getOpcode() == ISD::TRUNCATE)
12500 Op1 = Op1.getOperand(0);
12503 if (Op1.getOpcode() == ISD::SHL)
12504 std::swap(Op0, Op1);
12505 if (Op0.getOpcode() == ISD::SHL) {
12506 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12507 if (And00C->getZExtValue() == 1) {
12508 // If we looked past a truncate, check that it's only truncating away
12510 unsigned BitWidth = Op0.getValueSizeInBits();
12511 unsigned AndBitWidth = And.getValueSizeInBits();
12512 if (BitWidth > AndBitWidth) {
12514 DAG.computeKnownBits(Op0, Zeros, Ones);
12515 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12519 RHS = Op0.getOperand(1);
12521 } else if (Op1.getOpcode() == ISD::Constant) {
12522 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12523 uint64_t AndRHSVal = AndRHS->getZExtValue();
12524 SDValue AndLHS = Op0;
12526 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12527 LHS = AndLHS.getOperand(0);
12528 RHS = AndLHS.getOperand(1);
12531 // Use BT if the immediate can't be encoded in a TEST instruction.
12532 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12534 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12538 if (LHS.getNode()) {
12539 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12540 // instruction. Since the shift amount is in-range-or-undefined, we know
12541 // that doing a bittest on the i32 value is ok. We extend to i32 because
12542 // the encoding for the i16 version is larger than the i32 version.
12543 // Also promote i16 to i32 for performance / code size reason.
12544 if (LHS.getValueType() == MVT::i8 ||
12545 LHS.getValueType() == MVT::i16)
12546 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12548 // If the operand types disagree, extend the shift amount to match. Since
12549 // BT ignores high bits (like shifts) we can use anyextend.
12550 if (LHS.getValueType() != RHS.getValueType())
12551 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12553 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12554 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12555 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12556 DAG.getConstant(Cond, MVT::i8), BT);
12562 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12564 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12569 // SSE Condition code mapping:
12578 switch (SetCCOpcode) {
12579 default: llvm_unreachable("Unexpected SETCC condition");
12581 case ISD::SETEQ: SSECC = 0; break;
12583 case ISD::SETGT: Swap = true; // Fallthrough
12585 case ISD::SETOLT: SSECC = 1; break;
12587 case ISD::SETGE: Swap = true; // Fallthrough
12589 case ISD::SETOLE: SSECC = 2; break;
12590 case ISD::SETUO: SSECC = 3; break;
12592 case ISD::SETNE: SSECC = 4; break;
12593 case ISD::SETULE: Swap = true; // Fallthrough
12594 case ISD::SETUGE: SSECC = 5; break;
12595 case ISD::SETULT: Swap = true; // Fallthrough
12596 case ISD::SETUGT: SSECC = 6; break;
12597 case ISD::SETO: SSECC = 7; break;
12599 case ISD::SETONE: SSECC = 8; break;
12602 std::swap(Op0, Op1);
12607 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12608 // ones, and then concatenate the result back.
12609 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12610 MVT VT = Op.getSimpleValueType();
12612 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12613 "Unsupported value type for operation");
12615 unsigned NumElems = VT.getVectorNumElements();
12617 SDValue CC = Op.getOperand(2);
12619 // Extract the LHS vectors
12620 SDValue LHS = Op.getOperand(0);
12621 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12622 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12624 // Extract the RHS vectors
12625 SDValue RHS = Op.getOperand(1);
12626 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12627 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12629 // Issue the operation on the smaller types and concatenate the result back
12630 MVT EltVT = VT.getVectorElementType();
12631 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12632 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12633 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12634 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12637 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12638 const X86Subtarget *Subtarget) {
12639 SDValue Op0 = Op.getOperand(0);
12640 SDValue Op1 = Op.getOperand(1);
12641 SDValue CC = Op.getOperand(2);
12642 MVT VT = Op.getSimpleValueType();
12645 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
12646 Op.getValueType().getScalarType() == MVT::i1 &&
12647 "Cannot set masked compare for this operation");
12649 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12651 bool Unsigned = false;
12654 switch (SetCCOpcode) {
12655 default: llvm_unreachable("Unexpected SETCC condition");
12656 case ISD::SETNE: SSECC = 4; break;
12657 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12658 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12659 case ISD::SETLT: Swap = true; //fall-through
12660 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12661 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12662 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12663 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12664 case ISD::SETULE: Unsigned = true; //fall-through
12665 case ISD::SETLE: SSECC = 2; break;
12669 std::swap(Op0, Op1);
12671 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12672 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12673 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12674 DAG.getConstant(SSECC, MVT::i8));
12677 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12678 /// operand \p Op1. If non-trivial (for example because it's not constant)
12679 /// return an empty value.
12680 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12682 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12686 MVT VT = Op1.getSimpleValueType();
12687 MVT EVT = VT.getVectorElementType();
12688 unsigned n = VT.getVectorNumElements();
12689 SmallVector<SDValue, 8> ULTOp1;
12691 for (unsigned i = 0; i < n; ++i) {
12692 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12693 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12696 // Avoid underflow.
12697 APInt Val = Elt->getAPIntValue();
12701 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12704 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12707 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12708 SelectionDAG &DAG) {
12709 SDValue Op0 = Op.getOperand(0);
12710 SDValue Op1 = Op.getOperand(1);
12711 SDValue CC = Op.getOperand(2);
12712 MVT VT = Op.getSimpleValueType();
12713 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12714 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12719 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12720 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12723 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12724 unsigned Opc = X86ISD::CMPP;
12725 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12726 assert(VT.getVectorNumElements() <= 16);
12727 Opc = X86ISD::CMPM;
12729 // In the two special cases we can't handle, emit two comparisons.
12732 unsigned CombineOpc;
12733 if (SetCCOpcode == ISD::SETUEQ) {
12734 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12736 assert(SetCCOpcode == ISD::SETONE);
12737 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12740 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12741 DAG.getConstant(CC0, MVT::i8));
12742 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12743 DAG.getConstant(CC1, MVT::i8));
12744 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12746 // Handle all other FP comparisons here.
12747 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12748 DAG.getConstant(SSECC, MVT::i8));
12751 // Break 256-bit integer vector compare into smaller ones.
12752 if (VT.is256BitVector() && !Subtarget->hasInt256())
12753 return Lower256IntVSETCC(Op, DAG);
12755 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12756 EVT OpVT = Op1.getValueType();
12757 if (Subtarget->hasAVX512()) {
12758 if (Op1.getValueType().is512BitVector() ||
12759 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12760 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12762 // In AVX-512 architecture setcc returns mask with i1 elements,
12763 // But there is no compare instruction for i8 and i16 elements.
12764 // We are not talking about 512-bit operands in this case, these
12765 // types are illegal.
12767 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12768 OpVT.getVectorElementType().getSizeInBits() >= 8))
12769 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12770 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12773 // We are handling one of the integer comparisons here. Since SSE only has
12774 // GT and EQ comparisons for integer, swapping operands and multiple
12775 // operations may be required for some comparisons.
12777 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12778 bool Subus = false;
12780 switch (SetCCOpcode) {
12781 default: llvm_unreachable("Unexpected SETCC condition");
12782 case ISD::SETNE: Invert = true;
12783 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12784 case ISD::SETLT: Swap = true;
12785 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12786 case ISD::SETGE: Swap = true;
12787 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12788 Invert = true; break;
12789 case ISD::SETULT: Swap = true;
12790 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12791 FlipSigns = true; break;
12792 case ISD::SETUGE: Swap = true;
12793 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12794 FlipSigns = true; Invert = true; break;
12797 // Special case: Use min/max operations for SETULE/SETUGE
12798 MVT VET = VT.getVectorElementType();
12800 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12801 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12804 switch (SetCCOpcode) {
12806 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
12807 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
12810 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
12813 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
12814 if (!MinMax && hasSubus) {
12815 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
12817 // t = psubus Op0, Op1
12818 // pcmpeq t, <0..0>
12819 switch (SetCCOpcode) {
12821 case ISD::SETULT: {
12822 // If the comparison is against a constant we can turn this into a
12823 // setule. With psubus, setule does not require a swap. This is
12824 // beneficial because the constant in the register is no longer
12825 // destructed as the destination so it can be hoisted out of a loop.
12826 // Only do this pre-AVX since vpcmp* is no longer destructive.
12827 if (Subtarget->hasAVX())
12829 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
12830 if (ULEOp1.getNode()) {
12832 Subus = true; Invert = false; Swap = false;
12836 // Psubus is better than flip-sign because it requires no inversion.
12837 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
12838 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
12842 Opc = X86ISD::SUBUS;
12848 std::swap(Op0, Op1);
12850 // Check that the operation in question is available (most are plain SSE2,
12851 // but PCMPGTQ and PCMPEQQ have different requirements).
12852 if (VT == MVT::v2i64) {
12853 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
12854 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
12856 // First cast everything to the right type.
12857 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12858 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12860 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12861 // bits of the inputs before performing those operations. The lower
12862 // compare is always unsigned.
12865 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
12867 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
12868 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
12869 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
12870 Sign, Zero, Sign, Zero);
12872 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
12873 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
12875 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
12876 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
12877 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12879 // Create masks for only the low parts/high parts of the 64 bit integers.
12880 static const int MaskHi[] = { 1, 1, 3, 3 };
12881 static const int MaskLo[] = { 0, 0, 2, 2 };
12882 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
12883 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
12884 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
12886 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
12887 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
12890 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12892 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12895 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
12896 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
12897 // pcmpeqd + pshufd + pand.
12898 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
12900 // First cast everything to the right type.
12901 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12902 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12905 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
12907 // Make sure the lower and upper halves are both all-ones.
12908 static const int Mask[] = { 1, 0, 3, 2 };
12909 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
12910 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
12913 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12915 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12919 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12920 // bits of the inputs before performing those operations.
12922 EVT EltVT = VT.getVectorElementType();
12923 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
12924 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
12925 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
12928 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
12930 // If the logical-not of the result is required, perform that now.
12932 Result = DAG.getNOT(dl, Result, VT);
12935 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
12938 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
12939 getZeroVector(VT, Subtarget, DAG, dl));
12944 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
12946 MVT VT = Op.getSimpleValueType();
12948 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
12950 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
12951 && "SetCC type must be 8-bit or 1-bit integer");
12952 SDValue Op0 = Op.getOperand(0);
12953 SDValue Op1 = Op.getOperand(1);
12955 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
12957 // Optimize to BT if possible.
12958 // Lower (X & (1 << N)) == 0 to BT(X, N).
12959 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
12960 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
12961 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
12962 Op1.getOpcode() == ISD::Constant &&
12963 cast<ConstantSDNode>(Op1)->isNullValue() &&
12964 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12965 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
12966 if (NewSetCC.getNode())
12970 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
12972 if (Op1.getOpcode() == ISD::Constant &&
12973 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
12974 cast<ConstantSDNode>(Op1)->isNullValue()) &&
12975 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12977 // If the input is a setcc, then reuse the input setcc or use a new one with
12978 // the inverted condition.
12979 if (Op0.getOpcode() == X86ISD::SETCC) {
12980 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
12981 bool Invert = (CC == ISD::SETNE) ^
12982 cast<ConstantSDNode>(Op1)->isNullValue();
12986 CCode = X86::GetOppositeBranchCondition(CCode);
12987 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12988 DAG.getConstant(CCode, MVT::i8),
12989 Op0.getOperand(1));
12991 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12995 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
12996 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
12997 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12999 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13000 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13003 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13004 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13005 if (X86CC == X86::COND_INVALID)
13008 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13009 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13010 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13011 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13013 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13017 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13018 static bool isX86LogicalCmp(SDValue Op) {
13019 unsigned Opc = Op.getNode()->getOpcode();
13020 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13021 Opc == X86ISD::SAHF)
13023 if (Op.getResNo() == 1 &&
13024 (Opc == X86ISD::ADD ||
13025 Opc == X86ISD::SUB ||
13026 Opc == X86ISD::ADC ||
13027 Opc == X86ISD::SBB ||
13028 Opc == X86ISD::SMUL ||
13029 Opc == X86ISD::UMUL ||
13030 Opc == X86ISD::INC ||
13031 Opc == X86ISD::DEC ||
13032 Opc == X86ISD::OR ||
13033 Opc == X86ISD::XOR ||
13034 Opc == X86ISD::AND))
13037 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13043 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13044 if (V.getOpcode() != ISD::TRUNCATE)
13047 SDValue VOp0 = V.getOperand(0);
13048 unsigned InBits = VOp0.getValueSizeInBits();
13049 unsigned Bits = V.getValueSizeInBits();
13050 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13053 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13054 bool addTest = true;
13055 SDValue Cond = Op.getOperand(0);
13056 SDValue Op1 = Op.getOperand(1);
13057 SDValue Op2 = Op.getOperand(2);
13059 EVT VT = Op1.getValueType();
13062 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13063 // are available. Otherwise fp cmovs get lowered into a less efficient branch
13064 // sequence later on.
13065 if (Cond.getOpcode() == ISD::SETCC &&
13066 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13067 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13068 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13069 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13070 int SSECC = translateX86FSETCC(
13071 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13074 if (Subtarget->hasAVX512()) {
13075 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13076 DAG.getConstant(SSECC, MVT::i8));
13077 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13079 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13080 DAG.getConstant(SSECC, MVT::i8));
13081 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13082 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13083 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13087 if (Cond.getOpcode() == ISD::SETCC) {
13088 SDValue NewCond = LowerSETCC(Cond, DAG);
13089 if (NewCond.getNode())
13093 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13094 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13095 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13096 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13097 if (Cond.getOpcode() == X86ISD::SETCC &&
13098 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13099 isZero(Cond.getOperand(1).getOperand(1))) {
13100 SDValue Cmp = Cond.getOperand(1);
13102 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13104 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13105 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13106 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13108 SDValue CmpOp0 = Cmp.getOperand(0);
13109 // Apply further optimizations for special cases
13110 // (select (x != 0), -1, 0) -> neg & sbb
13111 // (select (x == 0), 0, -1) -> neg & sbb
13112 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13113 if (YC->isNullValue() &&
13114 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13115 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13116 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13117 DAG.getConstant(0, CmpOp0.getValueType()),
13119 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13120 DAG.getConstant(X86::COND_B, MVT::i8),
13121 SDValue(Neg.getNode(), 1));
13125 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13126 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
13127 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13129 SDValue Res = // Res = 0 or -1.
13130 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13131 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
13133 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13134 Res = DAG.getNOT(DL, Res, Res.getValueType());
13136 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13137 if (!N2C || !N2C->isNullValue())
13138 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13143 // Look past (and (setcc_carry (cmp ...)), 1).
13144 if (Cond.getOpcode() == ISD::AND &&
13145 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13146 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13147 if (C && C->getAPIntValue() == 1)
13148 Cond = Cond.getOperand(0);
13151 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13152 // setting operand in place of the X86ISD::SETCC.
13153 unsigned CondOpcode = Cond.getOpcode();
13154 if (CondOpcode == X86ISD::SETCC ||
13155 CondOpcode == X86ISD::SETCC_CARRY) {
13156 CC = Cond.getOperand(0);
13158 SDValue Cmp = Cond.getOperand(1);
13159 unsigned Opc = Cmp.getOpcode();
13160 MVT VT = Op.getSimpleValueType();
13162 bool IllegalFPCMov = false;
13163 if (VT.isFloatingPoint() && !VT.isVector() &&
13164 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13165 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13167 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13168 Opc == X86ISD::BT) { // FIXME
13172 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13173 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13174 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13175 Cond.getOperand(0).getValueType() != MVT::i8)) {
13176 SDValue LHS = Cond.getOperand(0);
13177 SDValue RHS = Cond.getOperand(1);
13178 unsigned X86Opcode;
13181 switch (CondOpcode) {
13182 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13183 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13184 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13185 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13186 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13187 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13188 default: llvm_unreachable("unexpected overflowing operator");
13190 if (CondOpcode == ISD::UMULO)
13191 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13194 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13196 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13198 if (CondOpcode == ISD::UMULO)
13199 Cond = X86Op.getValue(2);
13201 Cond = X86Op.getValue(1);
13203 CC = DAG.getConstant(X86Cond, MVT::i8);
13208 // Look pass the truncate if the high bits are known zero.
13209 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13210 Cond = Cond.getOperand(0);
13212 // We know the result of AND is compared against zero. Try to match
13214 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13215 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13216 if (NewSetCC.getNode()) {
13217 CC = NewSetCC.getOperand(0);
13218 Cond = NewSetCC.getOperand(1);
13225 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13226 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13229 // a < b ? -1 : 0 -> RES = ~setcc_carry
13230 // a < b ? 0 : -1 -> RES = setcc_carry
13231 // a >= b ? -1 : 0 -> RES = setcc_carry
13232 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13233 if (Cond.getOpcode() == X86ISD::SUB) {
13234 Cond = ConvertCmpIfNecessary(Cond, DAG);
13235 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13237 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13238 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13239 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13240 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
13241 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13242 return DAG.getNOT(DL, Res, Res.getValueType());
13247 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13248 // widen the cmov and push the truncate through. This avoids introducing a new
13249 // branch during isel and doesn't add any extensions.
13250 if (Op.getValueType() == MVT::i8 &&
13251 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13252 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13253 if (T1.getValueType() == T2.getValueType() &&
13254 // Blacklist CopyFromReg to avoid partial register stalls.
13255 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13256 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13257 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13258 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13262 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13263 // condition is true.
13264 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13265 SDValue Ops[] = { Op2, Op1, CC, Cond };
13266 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13269 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
13270 MVT VT = Op->getSimpleValueType(0);
13271 SDValue In = Op->getOperand(0);
13272 MVT InVT = In.getSimpleValueType();
13275 unsigned int NumElts = VT.getVectorNumElements();
13276 if (NumElts != 8 && NumElts != 16)
13279 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13280 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13282 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13283 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13285 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13286 Constant *C = ConstantInt::get(*DAG.getContext(),
13287 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13289 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13290 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13291 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13292 MachinePointerInfo::getConstantPool(),
13293 false, false, false, Alignment);
13294 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13295 if (VT.is512BitVector())
13297 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13300 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13301 SelectionDAG &DAG) {
13302 MVT VT = Op->getSimpleValueType(0);
13303 SDValue In = Op->getOperand(0);
13304 MVT InVT = In.getSimpleValueType();
13307 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13308 return LowerSIGN_EXTEND_AVX512(Op, DAG);
13310 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13311 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13312 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13315 if (Subtarget->hasInt256())
13316 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13318 // Optimize vectors in AVX mode
13319 // Sign extend v8i16 to v8i32 and
13322 // Divide input vector into two parts
13323 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13324 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13325 // concat the vectors to original VT
13327 unsigned NumElems = InVT.getVectorNumElements();
13328 SDValue Undef = DAG.getUNDEF(InVT);
13330 SmallVector<int,8> ShufMask1(NumElems, -1);
13331 for (unsigned i = 0; i != NumElems/2; ++i)
13334 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13336 SmallVector<int,8> ShufMask2(NumElems, -1);
13337 for (unsigned i = 0; i != NumElems/2; ++i)
13338 ShufMask2[i] = i + NumElems/2;
13340 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13342 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13343 VT.getVectorNumElements()/2);
13345 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13346 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13348 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13351 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13352 // may emit an illegal shuffle but the expansion is still better than scalar
13353 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13354 // we'll emit a shuffle and a arithmetic shift.
13355 // TODO: It is possible to support ZExt by zeroing the undef values during
13356 // the shuffle phase or after the shuffle.
13357 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13358 SelectionDAG &DAG) {
13359 MVT RegVT = Op.getSimpleValueType();
13360 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13361 assert(RegVT.isInteger() &&
13362 "We only custom lower integer vector sext loads.");
13364 // Nothing useful we can do without SSE2 shuffles.
13365 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13367 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13369 EVT MemVT = Ld->getMemoryVT();
13370 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13371 unsigned RegSz = RegVT.getSizeInBits();
13373 ISD::LoadExtType Ext = Ld->getExtensionType();
13375 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13376 && "Only anyext and sext are currently implemented.");
13377 assert(MemVT != RegVT && "Cannot extend to the same type");
13378 assert(MemVT.isVector() && "Must load a vector from memory");
13380 unsigned NumElems = RegVT.getVectorNumElements();
13381 unsigned MemSz = MemVT.getSizeInBits();
13382 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13384 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13385 // The only way in which we have a legal 256-bit vector result but not the
13386 // integer 256-bit operations needed to directly lower a sextload is if we
13387 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13388 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13389 // correctly legalized. We do this late to allow the canonical form of
13390 // sextload to persist throughout the rest of the DAG combiner -- it wants
13391 // to fold together any extensions it can, and so will fuse a sign_extend
13392 // of an sextload into a sextload targeting a wider value.
13394 if (MemSz == 128) {
13395 // Just switch this to a normal load.
13396 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13397 "it must be a legal 128-bit vector "
13399 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13400 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13401 Ld->isInvariant(), Ld->getAlignment());
13403 assert(MemSz < 128 &&
13404 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13405 // Do an sext load to a 128-bit vector type. We want to use the same
13406 // number of elements, but elements half as wide. This will end up being
13407 // recursively lowered by this routine, but will succeed as we definitely
13408 // have all the necessary features if we're using AVX1.
13410 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13411 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13413 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13414 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13415 Ld->isNonTemporal(), Ld->isInvariant(),
13416 Ld->getAlignment());
13419 // Replace chain users with the new chain.
13420 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13421 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13423 // Finally, do a normal sign-extend to the desired register.
13424 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13427 // All sizes must be a power of two.
13428 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13429 "Non-power-of-two elements are not custom lowered!");
13431 // Attempt to load the original value using scalar loads.
13432 // Find the largest scalar type that divides the total loaded size.
13433 MVT SclrLoadTy = MVT::i8;
13434 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13435 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13436 MVT Tp = (MVT::SimpleValueType)tp;
13437 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13442 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13443 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13445 SclrLoadTy = MVT::f64;
13447 // Calculate the number of scalar loads that we need to perform
13448 // in order to load our vector from memory.
13449 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13451 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13452 "Can only lower sext loads with a single scalar load!");
13454 unsigned loadRegZize = RegSz;
13455 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13458 // Represent our vector as a sequence of elements which are the
13459 // largest scalar that we can load.
13460 EVT LoadUnitVecVT = EVT::getVectorVT(
13461 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13463 // Represent the data using the same element type that is stored in
13464 // memory. In practice, we ''widen'' MemVT.
13466 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13467 loadRegZize / MemVT.getScalarType().getSizeInBits());
13469 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13470 "Invalid vector type");
13472 // We can't shuffle using an illegal type.
13473 assert(TLI.isTypeLegal(WideVecVT) &&
13474 "We only lower types that form legal widened vector types");
13476 SmallVector<SDValue, 8> Chains;
13477 SDValue Ptr = Ld->getBasePtr();
13478 SDValue Increment =
13479 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13480 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13482 for (unsigned i = 0; i < NumLoads; ++i) {
13483 // Perform a single load.
13484 SDValue ScalarLoad =
13485 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13486 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13487 Ld->getAlignment());
13488 Chains.push_back(ScalarLoad.getValue(1));
13489 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13490 // another round of DAGCombining.
13492 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13494 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13495 ScalarLoad, DAG.getIntPtrConstant(i));
13497 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13500 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13502 // Bitcast the loaded value to a vector of the original element type, in
13503 // the size of the target vector type.
13504 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13505 unsigned SizeRatio = RegSz / MemSz;
13507 if (Ext == ISD::SEXTLOAD) {
13508 // If we have SSE4.1, we can directly emit a VSEXT node.
13509 if (Subtarget->hasSSE41()) {
13510 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13511 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13515 // Otherwise we'll shuffle the small elements in the high bits of the
13516 // larger type and perform an arithmetic shift. If the shift is not legal
13517 // it's better to scalarize.
13518 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13519 "We can't implement a sext load without an arithmetic right shift!");
13521 // Redistribute the loaded elements into the different locations.
13522 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13523 for (unsigned i = 0; i != NumElems; ++i)
13524 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13526 SDValue Shuff = DAG.getVectorShuffle(
13527 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13529 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13531 // Build the arithmetic shift.
13532 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13533 MemVT.getVectorElementType().getSizeInBits();
13535 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13537 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13541 // Redistribute the loaded elements into the different locations.
13542 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13543 for (unsigned i = 0; i != NumElems; ++i)
13544 ShuffleVec[i * SizeRatio] = i;
13546 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13547 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13549 // Bitcast to the requested type.
13550 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13551 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13555 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
13556 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
13557 // from the AND / OR.
13558 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
13559 Opc = Op.getOpcode();
13560 if (Opc != ISD::OR && Opc != ISD::AND)
13562 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13563 Op.getOperand(0).hasOneUse() &&
13564 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
13565 Op.getOperand(1).hasOneUse());
13568 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
13569 // 1 and that the SETCC node has a single use.
13570 static bool isXor1OfSetCC(SDValue Op) {
13571 if (Op.getOpcode() != ISD::XOR)
13573 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13574 if (N1C && N1C->getAPIntValue() == 1) {
13575 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13576 Op.getOperand(0).hasOneUse();
13581 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
13582 bool addTest = true;
13583 SDValue Chain = Op.getOperand(0);
13584 SDValue Cond = Op.getOperand(1);
13585 SDValue Dest = Op.getOperand(2);
13588 bool Inverted = false;
13590 if (Cond.getOpcode() == ISD::SETCC) {
13591 // Check for setcc([su]{add,sub,mul}o == 0).
13592 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
13593 isa<ConstantSDNode>(Cond.getOperand(1)) &&
13594 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
13595 Cond.getOperand(0).getResNo() == 1 &&
13596 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
13597 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
13598 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
13599 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
13600 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
13601 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
13603 Cond = Cond.getOperand(0);
13605 SDValue NewCond = LowerSETCC(Cond, DAG);
13606 if (NewCond.getNode())
13611 // FIXME: LowerXALUO doesn't handle these!!
13612 else if (Cond.getOpcode() == X86ISD::ADD ||
13613 Cond.getOpcode() == X86ISD::SUB ||
13614 Cond.getOpcode() == X86ISD::SMUL ||
13615 Cond.getOpcode() == X86ISD::UMUL)
13616 Cond = LowerXALUO(Cond, DAG);
13619 // Look pass (and (setcc_carry (cmp ...)), 1).
13620 if (Cond.getOpcode() == ISD::AND &&
13621 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13622 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13623 if (C && C->getAPIntValue() == 1)
13624 Cond = Cond.getOperand(0);
13627 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13628 // setting operand in place of the X86ISD::SETCC.
13629 unsigned CondOpcode = Cond.getOpcode();
13630 if (CondOpcode == X86ISD::SETCC ||
13631 CondOpcode == X86ISD::SETCC_CARRY) {
13632 CC = Cond.getOperand(0);
13634 SDValue Cmp = Cond.getOperand(1);
13635 unsigned Opc = Cmp.getOpcode();
13636 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
13637 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
13641 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
13645 // These can only come from an arithmetic instruction with overflow,
13646 // e.g. SADDO, UADDO.
13647 Cond = Cond.getNode()->getOperand(1);
13653 CondOpcode = Cond.getOpcode();
13654 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13655 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13656 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13657 Cond.getOperand(0).getValueType() != MVT::i8)) {
13658 SDValue LHS = Cond.getOperand(0);
13659 SDValue RHS = Cond.getOperand(1);
13660 unsigned X86Opcode;
13663 // Keep this in sync with LowerXALUO, otherwise we might create redundant
13664 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
13666 switch (CondOpcode) {
13667 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13669 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13671 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
13674 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13675 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13677 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13679 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
13682 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13683 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13684 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13685 default: llvm_unreachable("unexpected overflowing operator");
13688 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
13689 if (CondOpcode == ISD::UMULO)
13690 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13693 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13695 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
13697 if (CondOpcode == ISD::UMULO)
13698 Cond = X86Op.getValue(2);
13700 Cond = X86Op.getValue(1);
13702 CC = DAG.getConstant(X86Cond, MVT::i8);
13706 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
13707 SDValue Cmp = Cond.getOperand(0).getOperand(1);
13708 if (CondOpc == ISD::OR) {
13709 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
13710 // two branches instead of an explicit OR instruction with a
13712 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13713 isX86LogicalCmp(Cmp)) {
13714 CC = Cond.getOperand(0).getOperand(0);
13715 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13716 Chain, Dest, CC, Cmp);
13717 CC = Cond.getOperand(1).getOperand(0);
13721 } else { // ISD::AND
13722 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
13723 // two branches instead of an explicit AND instruction with a
13724 // separate test. However, we only do this if this block doesn't
13725 // have a fall-through edge, because this requires an explicit
13726 // jmp when the condition is false.
13727 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13728 isX86LogicalCmp(Cmp) &&
13729 Op.getNode()->hasOneUse()) {
13730 X86::CondCode CCode =
13731 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13732 CCode = X86::GetOppositeBranchCondition(CCode);
13733 CC = DAG.getConstant(CCode, MVT::i8);
13734 SDNode *User = *Op.getNode()->use_begin();
13735 // Look for an unconditional branch following this conditional branch.
13736 // We need this because we need to reverse the successors in order
13737 // to implement FCMP_OEQ.
13738 if (User->getOpcode() == ISD::BR) {
13739 SDValue FalseBB = User->getOperand(1);
13741 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13742 assert(NewBR == User);
13746 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13747 Chain, Dest, CC, Cmp);
13748 X86::CondCode CCode =
13749 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
13750 CCode = X86::GetOppositeBranchCondition(CCode);
13751 CC = DAG.getConstant(CCode, MVT::i8);
13757 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
13758 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
13759 // It should be transformed during dag combiner except when the condition
13760 // is set by a arithmetics with overflow node.
13761 X86::CondCode CCode =
13762 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13763 CCode = X86::GetOppositeBranchCondition(CCode);
13764 CC = DAG.getConstant(CCode, MVT::i8);
13765 Cond = Cond.getOperand(0).getOperand(1);
13767 } else if (Cond.getOpcode() == ISD::SETCC &&
13768 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
13769 // For FCMP_OEQ, we can emit
13770 // two branches instead of an explicit AND instruction with a
13771 // separate test. However, we only do this if this block doesn't
13772 // have a fall-through edge, because this requires an explicit
13773 // jmp when the condition is false.
13774 if (Op.getNode()->hasOneUse()) {
13775 SDNode *User = *Op.getNode()->use_begin();
13776 // Look for an unconditional branch following this conditional branch.
13777 // We need this because we need to reverse the successors in order
13778 // to implement FCMP_OEQ.
13779 if (User->getOpcode() == ISD::BR) {
13780 SDValue FalseBB = User->getOperand(1);
13782 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13783 assert(NewBR == User);
13787 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13788 Cond.getOperand(0), Cond.getOperand(1));
13789 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13790 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13791 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13792 Chain, Dest, CC, Cmp);
13793 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13798 } else if (Cond.getOpcode() == ISD::SETCC &&
13799 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13800 // For FCMP_UNE, we can emit
13801 // two branches instead of an explicit AND instruction with a
13802 // separate test. However, we only do this if this block doesn't
13803 // have a fall-through edge, because this requires an explicit
13804 // jmp when the condition is false.
13805 if (Op.getNode()->hasOneUse()) {
13806 SDNode *User = *Op.getNode()->use_begin();
13807 // Look for an unconditional branch following this conditional branch.
13808 // We need this because we need to reverse the successors in order
13809 // to implement FCMP_UNE.
13810 if (User->getOpcode() == ISD::BR) {
13811 SDValue FalseBB = User->getOperand(1);
13813 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13814 assert(NewBR == User);
13817 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13818 Cond.getOperand(0), Cond.getOperand(1));
13819 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13820 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13821 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13822 Chain, Dest, CC, Cmp);
13823 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13833 // Look pass the truncate if the high bits are known zero.
13834 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13835 Cond = Cond.getOperand(0);
13837 // We know the result of AND is compared against zero. Try to match
13839 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13840 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
13841 if (NewSetCC.getNode()) {
13842 CC = NewSetCC.getOperand(0);
13843 Cond = NewSetCC.getOperand(1);
13850 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
13851 CC = DAG.getConstant(X86Cond, MVT::i8);
13852 Cond = EmitTest(Cond, X86Cond, dl, DAG);
13854 Cond = ConvertCmpIfNecessary(Cond, DAG);
13855 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13856 Chain, Dest, CC, Cond);
13859 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
13860 // Calls to _alloca are needed to probe the stack when allocating more than 4k
13861 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
13862 // that the guard pages used by the OS virtual memory manager are allocated in
13863 // correct sequence.
13865 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
13866 SelectionDAG &DAG) const {
13867 MachineFunction &MF = DAG.getMachineFunction();
13868 bool SplitStack = MF.shouldSplitStack();
13869 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
13874 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13875 SDNode* Node = Op.getNode();
13877 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
13878 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
13879 " not tell us which reg is the stack pointer!");
13880 EVT VT = Node->getValueType(0);
13881 SDValue Tmp1 = SDValue(Node, 0);
13882 SDValue Tmp2 = SDValue(Node, 1);
13883 SDValue Tmp3 = Node->getOperand(2);
13884 SDValue Chain = Tmp1.getOperand(0);
13886 // Chain the dynamic stack allocation so that it doesn't modify the stack
13887 // pointer when other instructions are using the stack.
13888 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
13891 SDValue Size = Tmp2.getOperand(1);
13892 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
13893 Chain = SP.getValue(1);
13894 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
13895 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
13896 unsigned StackAlign = TFI.getStackAlignment();
13897 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
13898 if (Align > StackAlign)
13899 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
13900 DAG.getConstant(-(uint64_t)Align, VT));
13901 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
13903 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
13904 DAG.getIntPtrConstant(0, true), SDValue(),
13907 SDValue Ops[2] = { Tmp1, Tmp2 };
13908 return DAG.getMergeValues(Ops, dl);
13912 SDValue Chain = Op.getOperand(0);
13913 SDValue Size = Op.getOperand(1);
13914 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
13915 EVT VT = Op.getNode()->getValueType(0);
13917 bool Is64Bit = Subtarget->is64Bit();
13918 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
13921 MachineRegisterInfo &MRI = MF.getRegInfo();
13924 // The 64 bit implementation of segmented stacks needs to clobber both r10
13925 // r11. This makes it impossible to use it along with nested parameters.
13926 const Function *F = MF.getFunction();
13928 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
13930 if (I->hasNestAttr())
13931 report_fatal_error("Cannot use segmented stacks with functions that "
13932 "have nested arguments.");
13935 const TargetRegisterClass *AddrRegClass =
13936 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
13937 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
13938 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
13939 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
13940 DAG.getRegister(Vreg, SPTy));
13941 SDValue Ops1[2] = { Value, Chain };
13942 return DAG.getMergeValues(Ops1, dl);
13945 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
13947 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
13948 Flag = Chain.getValue(1);
13949 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13951 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
13953 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
13954 DAG.getSubtarget().getRegisterInfo());
13955 unsigned SPReg = RegInfo->getStackRegister();
13956 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
13957 Chain = SP.getValue(1);
13960 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
13961 DAG.getConstant(-(uint64_t)Align, VT));
13962 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
13965 SDValue Ops1[2] = { SP, Chain };
13966 return DAG.getMergeValues(Ops1, dl);
13970 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
13971 MachineFunction &MF = DAG.getMachineFunction();
13972 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
13974 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13977 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
13978 // vastart just stores the address of the VarArgsFrameIndex slot into the
13979 // memory location argument.
13980 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13982 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
13983 MachinePointerInfo(SV), false, false, 0);
13987 // gp_offset (0 - 6 * 8)
13988 // fp_offset (48 - 48 + 8 * 16)
13989 // overflow_arg_area (point to parameters coming in memory).
13991 SmallVector<SDValue, 8> MemOps;
13992 SDValue FIN = Op.getOperand(1);
13994 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
13995 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
13997 FIN, MachinePointerInfo(SV), false, false, 0);
13998 MemOps.push_back(Store);
14001 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14002 FIN, DAG.getIntPtrConstant(4));
14003 Store = DAG.getStore(Op.getOperand(0), DL,
14004 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14006 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14007 MemOps.push_back(Store);
14009 // Store ptr to overflow_arg_area
14010 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14011 FIN, DAG.getIntPtrConstant(4));
14012 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14014 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14015 MachinePointerInfo(SV, 8),
14017 MemOps.push_back(Store);
14019 // Store ptr to reg_save_area.
14020 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14021 FIN, DAG.getIntPtrConstant(8));
14022 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14024 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14025 MachinePointerInfo(SV, 16), false, false, 0);
14026 MemOps.push_back(Store);
14027 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14030 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14031 assert(Subtarget->is64Bit() &&
14032 "LowerVAARG only handles 64-bit va_arg!");
14033 assert((Subtarget->isTargetLinux() ||
14034 Subtarget->isTargetDarwin()) &&
14035 "Unhandled target in LowerVAARG");
14036 assert(Op.getNode()->getNumOperands() == 4);
14037 SDValue Chain = Op.getOperand(0);
14038 SDValue SrcPtr = Op.getOperand(1);
14039 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14040 unsigned Align = Op.getConstantOperandVal(3);
14043 EVT ArgVT = Op.getNode()->getValueType(0);
14044 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14045 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14048 // Decide which area this value should be read from.
14049 // TODO: Implement the AMD64 ABI in its entirety. This simple
14050 // selection mechanism works only for the basic types.
14051 if (ArgVT == MVT::f80) {
14052 llvm_unreachable("va_arg for f80 not yet implemented");
14053 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14054 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14055 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14056 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14058 llvm_unreachable("Unhandled argument type in LowerVAARG");
14061 if (ArgMode == 2) {
14062 // Sanity Check: Make sure using fp_offset makes sense.
14063 assert(!DAG.getTarget().Options.UseSoftFloat &&
14064 !(DAG.getMachineFunction()
14065 .getFunction()->getAttributes()
14066 .hasAttribute(AttributeSet::FunctionIndex,
14067 Attribute::NoImplicitFloat)) &&
14068 Subtarget->hasSSE1());
14071 // Insert VAARG_64 node into the DAG
14072 // VAARG_64 returns two values: Variable Argument Address, Chain
14073 SmallVector<SDValue, 11> InstOps;
14074 InstOps.push_back(Chain);
14075 InstOps.push_back(SrcPtr);
14076 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
14077 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
14078 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
14079 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14080 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14081 VTs, InstOps, MVT::i64,
14082 MachinePointerInfo(SV),
14084 /*Volatile=*/false,
14086 /*WriteMem=*/true);
14087 Chain = VAARG.getValue(1);
14089 // Load the next argument and return it
14090 return DAG.getLoad(ArgVT, dl,
14093 MachinePointerInfo(),
14094 false, false, false, 0);
14097 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14098 SelectionDAG &DAG) {
14099 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14100 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14101 SDValue Chain = Op.getOperand(0);
14102 SDValue DstPtr = Op.getOperand(1);
14103 SDValue SrcPtr = Op.getOperand(2);
14104 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14105 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14108 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14109 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
14111 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14114 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14115 // amount is a constant. Takes immediate version of shift as input.
14116 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14117 SDValue SrcOp, uint64_t ShiftAmt,
14118 SelectionDAG &DAG) {
14119 MVT ElementType = VT.getVectorElementType();
14121 // Fold this packed shift into its first operand if ShiftAmt is 0.
14125 // Check for ShiftAmt >= element width
14126 if (ShiftAmt >= ElementType.getSizeInBits()) {
14127 if (Opc == X86ISD::VSRAI)
14128 ShiftAmt = ElementType.getSizeInBits() - 1;
14130 return DAG.getConstant(0, VT);
14133 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14134 && "Unknown target vector shift-by-constant node");
14136 // Fold this packed vector shift into a build vector if SrcOp is a
14137 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14138 if (VT == SrcOp.getSimpleValueType() &&
14139 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14140 SmallVector<SDValue, 8> Elts;
14141 unsigned NumElts = SrcOp->getNumOperands();
14142 ConstantSDNode *ND;
14145 default: llvm_unreachable(nullptr);
14146 case X86ISD::VSHLI:
14147 for (unsigned i=0; i!=NumElts; ++i) {
14148 SDValue CurrentOp = SrcOp->getOperand(i);
14149 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14150 Elts.push_back(CurrentOp);
14153 ND = cast<ConstantSDNode>(CurrentOp);
14154 const APInt &C = ND->getAPIntValue();
14155 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
14158 case X86ISD::VSRLI:
14159 for (unsigned i=0; i!=NumElts; ++i) {
14160 SDValue CurrentOp = SrcOp->getOperand(i);
14161 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14162 Elts.push_back(CurrentOp);
14165 ND = cast<ConstantSDNode>(CurrentOp);
14166 const APInt &C = ND->getAPIntValue();
14167 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
14170 case X86ISD::VSRAI:
14171 for (unsigned i=0; i!=NumElts; ++i) {
14172 SDValue CurrentOp = SrcOp->getOperand(i);
14173 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14174 Elts.push_back(CurrentOp);
14177 ND = cast<ConstantSDNode>(CurrentOp);
14178 const APInt &C = ND->getAPIntValue();
14179 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
14184 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14187 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
14190 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14191 // may or may not be a constant. Takes immediate version of shift as input.
14192 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14193 SDValue SrcOp, SDValue ShAmt,
14194 SelectionDAG &DAG) {
14195 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
14197 // Catch shift-by-constant.
14198 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14199 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14200 CShAmt->getZExtValue(), DAG);
14202 // Change opcode to non-immediate version
14204 default: llvm_unreachable("Unknown target vector shift node");
14205 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14206 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14207 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14210 // Need to build a vector containing shift amount
14211 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
14214 ShOps[1] = DAG.getConstant(0, MVT::i32);
14215 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
14216 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
14218 // The return type has to be a 128-bit type with the same element
14219 // type as the input type.
14220 MVT EltVT = VT.getVectorElementType();
14221 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14223 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14224 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14227 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
14228 /// necessary casting for \p Mask when lowering masking intrinsics.
14229 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14230 SDValue PreservedSrc, SelectionDAG &DAG) {
14231 EVT VT = Op.getValueType();
14232 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14233 MVT::i1, VT.getVectorNumElements());
14236 assert(MaskVT.isSimple() && "invalid mask type");
14237 return DAG.getNode(ISD::VSELECT, dl, VT,
14238 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
14242 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
14244 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14245 case Intrinsic::x86_fma_vfmadd_ps:
14246 case Intrinsic::x86_fma_vfmadd_pd:
14247 case Intrinsic::x86_fma_vfmadd_ps_256:
14248 case Intrinsic::x86_fma_vfmadd_pd_256:
14249 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
14250 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
14251 return X86ISD::FMADD;
14252 case Intrinsic::x86_fma_vfmsub_ps:
14253 case Intrinsic::x86_fma_vfmsub_pd:
14254 case Intrinsic::x86_fma_vfmsub_ps_256:
14255 case Intrinsic::x86_fma_vfmsub_pd_256:
14256 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
14257 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
14258 return X86ISD::FMSUB;
14259 case Intrinsic::x86_fma_vfnmadd_ps:
14260 case Intrinsic::x86_fma_vfnmadd_pd:
14261 case Intrinsic::x86_fma_vfnmadd_ps_256:
14262 case Intrinsic::x86_fma_vfnmadd_pd_256:
14263 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
14264 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
14265 return X86ISD::FNMADD;
14266 case Intrinsic::x86_fma_vfnmsub_ps:
14267 case Intrinsic::x86_fma_vfnmsub_pd:
14268 case Intrinsic::x86_fma_vfnmsub_ps_256:
14269 case Intrinsic::x86_fma_vfnmsub_pd_256:
14270 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
14271 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
14272 return X86ISD::FNMSUB;
14273 case Intrinsic::x86_fma_vfmaddsub_ps:
14274 case Intrinsic::x86_fma_vfmaddsub_pd:
14275 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14276 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14277 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
14278 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
14279 return X86ISD::FMADDSUB;
14280 case Intrinsic::x86_fma_vfmsubadd_ps:
14281 case Intrinsic::x86_fma_vfmsubadd_pd:
14282 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14283 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14284 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
14285 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
14286 return X86ISD::FMSUBADD;
14290 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
14292 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14294 default: return SDValue(); // Don't custom lower most intrinsics.
14295 // Comparison intrinsics.
14296 case Intrinsic::x86_sse_comieq_ss:
14297 case Intrinsic::x86_sse_comilt_ss:
14298 case Intrinsic::x86_sse_comile_ss:
14299 case Intrinsic::x86_sse_comigt_ss:
14300 case Intrinsic::x86_sse_comige_ss:
14301 case Intrinsic::x86_sse_comineq_ss:
14302 case Intrinsic::x86_sse_ucomieq_ss:
14303 case Intrinsic::x86_sse_ucomilt_ss:
14304 case Intrinsic::x86_sse_ucomile_ss:
14305 case Intrinsic::x86_sse_ucomigt_ss:
14306 case Intrinsic::x86_sse_ucomige_ss:
14307 case Intrinsic::x86_sse_ucomineq_ss:
14308 case Intrinsic::x86_sse2_comieq_sd:
14309 case Intrinsic::x86_sse2_comilt_sd:
14310 case Intrinsic::x86_sse2_comile_sd:
14311 case Intrinsic::x86_sse2_comigt_sd:
14312 case Intrinsic::x86_sse2_comige_sd:
14313 case Intrinsic::x86_sse2_comineq_sd:
14314 case Intrinsic::x86_sse2_ucomieq_sd:
14315 case Intrinsic::x86_sse2_ucomilt_sd:
14316 case Intrinsic::x86_sse2_ucomile_sd:
14317 case Intrinsic::x86_sse2_ucomigt_sd:
14318 case Intrinsic::x86_sse2_ucomige_sd:
14319 case Intrinsic::x86_sse2_ucomineq_sd: {
14323 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14324 case Intrinsic::x86_sse_comieq_ss:
14325 case Intrinsic::x86_sse2_comieq_sd:
14326 Opc = X86ISD::COMI;
14329 case Intrinsic::x86_sse_comilt_ss:
14330 case Intrinsic::x86_sse2_comilt_sd:
14331 Opc = X86ISD::COMI;
14334 case Intrinsic::x86_sse_comile_ss:
14335 case Intrinsic::x86_sse2_comile_sd:
14336 Opc = X86ISD::COMI;
14339 case Intrinsic::x86_sse_comigt_ss:
14340 case Intrinsic::x86_sse2_comigt_sd:
14341 Opc = X86ISD::COMI;
14344 case Intrinsic::x86_sse_comige_ss:
14345 case Intrinsic::x86_sse2_comige_sd:
14346 Opc = X86ISD::COMI;
14349 case Intrinsic::x86_sse_comineq_ss:
14350 case Intrinsic::x86_sse2_comineq_sd:
14351 Opc = X86ISD::COMI;
14354 case Intrinsic::x86_sse_ucomieq_ss:
14355 case Intrinsic::x86_sse2_ucomieq_sd:
14356 Opc = X86ISD::UCOMI;
14359 case Intrinsic::x86_sse_ucomilt_ss:
14360 case Intrinsic::x86_sse2_ucomilt_sd:
14361 Opc = X86ISD::UCOMI;
14364 case Intrinsic::x86_sse_ucomile_ss:
14365 case Intrinsic::x86_sse2_ucomile_sd:
14366 Opc = X86ISD::UCOMI;
14369 case Intrinsic::x86_sse_ucomigt_ss:
14370 case Intrinsic::x86_sse2_ucomigt_sd:
14371 Opc = X86ISD::UCOMI;
14374 case Intrinsic::x86_sse_ucomige_ss:
14375 case Intrinsic::x86_sse2_ucomige_sd:
14376 Opc = X86ISD::UCOMI;
14379 case Intrinsic::x86_sse_ucomineq_ss:
14380 case Intrinsic::x86_sse2_ucomineq_sd:
14381 Opc = X86ISD::UCOMI;
14386 SDValue LHS = Op.getOperand(1);
14387 SDValue RHS = Op.getOperand(2);
14388 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14389 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14390 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
14391 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14392 DAG.getConstant(X86CC, MVT::i8), Cond);
14393 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14396 // Arithmetic intrinsics.
14397 case Intrinsic::x86_sse2_pmulu_dq:
14398 case Intrinsic::x86_avx2_pmulu_dq:
14399 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
14400 Op.getOperand(1), Op.getOperand(2));
14402 case Intrinsic::x86_sse41_pmuldq:
14403 case Intrinsic::x86_avx2_pmul_dq:
14404 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
14405 Op.getOperand(1), Op.getOperand(2));
14407 case Intrinsic::x86_sse2_pmulhu_w:
14408 case Intrinsic::x86_avx2_pmulhu_w:
14409 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
14410 Op.getOperand(1), Op.getOperand(2));
14412 case Intrinsic::x86_sse2_pmulh_w:
14413 case Intrinsic::x86_avx2_pmulh_w:
14414 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
14415 Op.getOperand(1), Op.getOperand(2));
14417 // SSE2/AVX2 sub with unsigned saturation intrinsics
14418 case Intrinsic::x86_sse2_psubus_b:
14419 case Intrinsic::x86_sse2_psubus_w:
14420 case Intrinsic::x86_avx2_psubus_b:
14421 case Intrinsic::x86_avx2_psubus_w:
14422 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
14423 Op.getOperand(1), Op.getOperand(2));
14425 // SSE3/AVX horizontal add/sub intrinsics
14426 case Intrinsic::x86_sse3_hadd_ps:
14427 case Intrinsic::x86_sse3_hadd_pd:
14428 case Intrinsic::x86_avx_hadd_ps_256:
14429 case Intrinsic::x86_avx_hadd_pd_256:
14430 case Intrinsic::x86_sse3_hsub_ps:
14431 case Intrinsic::x86_sse3_hsub_pd:
14432 case Intrinsic::x86_avx_hsub_ps_256:
14433 case Intrinsic::x86_avx_hsub_pd_256:
14434 case Intrinsic::x86_ssse3_phadd_w_128:
14435 case Intrinsic::x86_ssse3_phadd_d_128:
14436 case Intrinsic::x86_avx2_phadd_w:
14437 case Intrinsic::x86_avx2_phadd_d:
14438 case Intrinsic::x86_ssse3_phsub_w_128:
14439 case Intrinsic::x86_ssse3_phsub_d_128:
14440 case Intrinsic::x86_avx2_phsub_w:
14441 case Intrinsic::x86_avx2_phsub_d: {
14444 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14445 case Intrinsic::x86_sse3_hadd_ps:
14446 case Intrinsic::x86_sse3_hadd_pd:
14447 case Intrinsic::x86_avx_hadd_ps_256:
14448 case Intrinsic::x86_avx_hadd_pd_256:
14449 Opcode = X86ISD::FHADD;
14451 case Intrinsic::x86_sse3_hsub_ps:
14452 case Intrinsic::x86_sse3_hsub_pd:
14453 case Intrinsic::x86_avx_hsub_ps_256:
14454 case Intrinsic::x86_avx_hsub_pd_256:
14455 Opcode = X86ISD::FHSUB;
14457 case Intrinsic::x86_ssse3_phadd_w_128:
14458 case Intrinsic::x86_ssse3_phadd_d_128:
14459 case Intrinsic::x86_avx2_phadd_w:
14460 case Intrinsic::x86_avx2_phadd_d:
14461 Opcode = X86ISD::HADD;
14463 case Intrinsic::x86_ssse3_phsub_w_128:
14464 case Intrinsic::x86_ssse3_phsub_d_128:
14465 case Intrinsic::x86_avx2_phsub_w:
14466 case Intrinsic::x86_avx2_phsub_d:
14467 Opcode = X86ISD::HSUB;
14470 return DAG.getNode(Opcode, dl, Op.getValueType(),
14471 Op.getOperand(1), Op.getOperand(2));
14474 // SSE2/SSE41/AVX2 integer max/min intrinsics.
14475 case Intrinsic::x86_sse2_pmaxu_b:
14476 case Intrinsic::x86_sse41_pmaxuw:
14477 case Intrinsic::x86_sse41_pmaxud:
14478 case Intrinsic::x86_avx2_pmaxu_b:
14479 case Intrinsic::x86_avx2_pmaxu_w:
14480 case Intrinsic::x86_avx2_pmaxu_d:
14481 case Intrinsic::x86_sse2_pminu_b:
14482 case Intrinsic::x86_sse41_pminuw:
14483 case Intrinsic::x86_sse41_pminud:
14484 case Intrinsic::x86_avx2_pminu_b:
14485 case Intrinsic::x86_avx2_pminu_w:
14486 case Intrinsic::x86_avx2_pminu_d:
14487 case Intrinsic::x86_sse41_pmaxsb:
14488 case Intrinsic::x86_sse2_pmaxs_w:
14489 case Intrinsic::x86_sse41_pmaxsd:
14490 case Intrinsic::x86_avx2_pmaxs_b:
14491 case Intrinsic::x86_avx2_pmaxs_w:
14492 case Intrinsic::x86_avx2_pmaxs_d:
14493 case Intrinsic::x86_sse41_pminsb:
14494 case Intrinsic::x86_sse2_pmins_w:
14495 case Intrinsic::x86_sse41_pminsd:
14496 case Intrinsic::x86_avx2_pmins_b:
14497 case Intrinsic::x86_avx2_pmins_w:
14498 case Intrinsic::x86_avx2_pmins_d: {
14501 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14502 case Intrinsic::x86_sse2_pmaxu_b:
14503 case Intrinsic::x86_sse41_pmaxuw:
14504 case Intrinsic::x86_sse41_pmaxud:
14505 case Intrinsic::x86_avx2_pmaxu_b:
14506 case Intrinsic::x86_avx2_pmaxu_w:
14507 case Intrinsic::x86_avx2_pmaxu_d:
14508 Opcode = X86ISD::UMAX;
14510 case Intrinsic::x86_sse2_pminu_b:
14511 case Intrinsic::x86_sse41_pminuw:
14512 case Intrinsic::x86_sse41_pminud:
14513 case Intrinsic::x86_avx2_pminu_b:
14514 case Intrinsic::x86_avx2_pminu_w:
14515 case Intrinsic::x86_avx2_pminu_d:
14516 Opcode = X86ISD::UMIN;
14518 case Intrinsic::x86_sse41_pmaxsb:
14519 case Intrinsic::x86_sse2_pmaxs_w:
14520 case Intrinsic::x86_sse41_pmaxsd:
14521 case Intrinsic::x86_avx2_pmaxs_b:
14522 case Intrinsic::x86_avx2_pmaxs_w:
14523 case Intrinsic::x86_avx2_pmaxs_d:
14524 Opcode = X86ISD::SMAX;
14526 case Intrinsic::x86_sse41_pminsb:
14527 case Intrinsic::x86_sse2_pmins_w:
14528 case Intrinsic::x86_sse41_pminsd:
14529 case Intrinsic::x86_avx2_pmins_b:
14530 case Intrinsic::x86_avx2_pmins_w:
14531 case Intrinsic::x86_avx2_pmins_d:
14532 Opcode = X86ISD::SMIN;
14535 return DAG.getNode(Opcode, dl, Op.getValueType(),
14536 Op.getOperand(1), Op.getOperand(2));
14539 // SSE/SSE2/AVX floating point max/min intrinsics.
14540 case Intrinsic::x86_sse_max_ps:
14541 case Intrinsic::x86_sse2_max_pd:
14542 case Intrinsic::x86_avx_max_ps_256:
14543 case Intrinsic::x86_avx_max_pd_256:
14544 case Intrinsic::x86_sse_min_ps:
14545 case Intrinsic::x86_sse2_min_pd:
14546 case Intrinsic::x86_avx_min_ps_256:
14547 case Intrinsic::x86_avx_min_pd_256: {
14550 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14551 case Intrinsic::x86_sse_max_ps:
14552 case Intrinsic::x86_sse2_max_pd:
14553 case Intrinsic::x86_avx_max_ps_256:
14554 case Intrinsic::x86_avx_max_pd_256:
14555 Opcode = X86ISD::FMAX;
14557 case Intrinsic::x86_sse_min_ps:
14558 case Intrinsic::x86_sse2_min_pd:
14559 case Intrinsic::x86_avx_min_ps_256:
14560 case Intrinsic::x86_avx_min_pd_256:
14561 Opcode = X86ISD::FMIN;
14564 return DAG.getNode(Opcode, dl, Op.getValueType(),
14565 Op.getOperand(1), Op.getOperand(2));
14568 // AVX2 variable shift intrinsics
14569 case Intrinsic::x86_avx2_psllv_d:
14570 case Intrinsic::x86_avx2_psllv_q:
14571 case Intrinsic::x86_avx2_psllv_d_256:
14572 case Intrinsic::x86_avx2_psllv_q_256:
14573 case Intrinsic::x86_avx2_psrlv_d:
14574 case Intrinsic::x86_avx2_psrlv_q:
14575 case Intrinsic::x86_avx2_psrlv_d_256:
14576 case Intrinsic::x86_avx2_psrlv_q_256:
14577 case Intrinsic::x86_avx2_psrav_d:
14578 case Intrinsic::x86_avx2_psrav_d_256: {
14581 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14582 case Intrinsic::x86_avx2_psllv_d:
14583 case Intrinsic::x86_avx2_psllv_q:
14584 case Intrinsic::x86_avx2_psllv_d_256:
14585 case Intrinsic::x86_avx2_psllv_q_256:
14588 case Intrinsic::x86_avx2_psrlv_d:
14589 case Intrinsic::x86_avx2_psrlv_q:
14590 case Intrinsic::x86_avx2_psrlv_d_256:
14591 case Intrinsic::x86_avx2_psrlv_q_256:
14594 case Intrinsic::x86_avx2_psrav_d:
14595 case Intrinsic::x86_avx2_psrav_d_256:
14599 return DAG.getNode(Opcode, dl, Op.getValueType(),
14600 Op.getOperand(1), Op.getOperand(2));
14603 case Intrinsic::x86_sse2_packssdw_128:
14604 case Intrinsic::x86_sse2_packsswb_128:
14605 case Intrinsic::x86_avx2_packssdw:
14606 case Intrinsic::x86_avx2_packsswb:
14607 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
14608 Op.getOperand(1), Op.getOperand(2));
14610 case Intrinsic::x86_sse2_packuswb_128:
14611 case Intrinsic::x86_sse41_packusdw:
14612 case Intrinsic::x86_avx2_packuswb:
14613 case Intrinsic::x86_avx2_packusdw:
14614 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
14615 Op.getOperand(1), Op.getOperand(2));
14617 case Intrinsic::x86_ssse3_pshuf_b_128:
14618 case Intrinsic::x86_avx2_pshuf_b:
14619 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
14620 Op.getOperand(1), Op.getOperand(2));
14622 case Intrinsic::x86_sse2_pshuf_d:
14623 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
14624 Op.getOperand(1), Op.getOperand(2));
14626 case Intrinsic::x86_sse2_pshufl_w:
14627 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
14628 Op.getOperand(1), Op.getOperand(2));
14630 case Intrinsic::x86_sse2_pshufh_w:
14631 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
14632 Op.getOperand(1), Op.getOperand(2));
14634 case Intrinsic::x86_ssse3_psign_b_128:
14635 case Intrinsic::x86_ssse3_psign_w_128:
14636 case Intrinsic::x86_ssse3_psign_d_128:
14637 case Intrinsic::x86_avx2_psign_b:
14638 case Intrinsic::x86_avx2_psign_w:
14639 case Intrinsic::x86_avx2_psign_d:
14640 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
14641 Op.getOperand(1), Op.getOperand(2));
14643 case Intrinsic::x86_sse41_insertps:
14644 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
14645 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14647 case Intrinsic::x86_avx_vperm2f128_ps_256:
14648 case Intrinsic::x86_avx_vperm2f128_pd_256:
14649 case Intrinsic::x86_avx_vperm2f128_si_256:
14650 case Intrinsic::x86_avx2_vperm2i128:
14651 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
14652 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14654 case Intrinsic::x86_avx2_permd:
14655 case Intrinsic::x86_avx2_permps:
14656 // Operands intentionally swapped. Mask is last operand to intrinsic,
14657 // but second operand for node/instruction.
14658 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
14659 Op.getOperand(2), Op.getOperand(1));
14661 case Intrinsic::x86_sse_sqrt_ps:
14662 case Intrinsic::x86_sse2_sqrt_pd:
14663 case Intrinsic::x86_avx_sqrt_ps_256:
14664 case Intrinsic::x86_avx_sqrt_pd_256:
14665 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
14667 case Intrinsic::x86_avx512_mask_valign_q_512:
14668 case Intrinsic::x86_avx512_mask_valign_d_512:
14669 // Vector source operands are swapped.
14670 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
14671 Op.getValueType(), Op.getOperand(2),
14674 Op.getOperand(5), Op.getOperand(4), DAG);
14676 // ptest and testp intrinsics. The intrinsic these come from are designed to
14677 // return an integer value, not just an instruction so lower it to the ptest
14678 // or testp pattern and a setcc for the result.
14679 case Intrinsic::x86_sse41_ptestz:
14680 case Intrinsic::x86_sse41_ptestc:
14681 case Intrinsic::x86_sse41_ptestnzc:
14682 case Intrinsic::x86_avx_ptestz_256:
14683 case Intrinsic::x86_avx_ptestc_256:
14684 case Intrinsic::x86_avx_ptestnzc_256:
14685 case Intrinsic::x86_avx_vtestz_ps:
14686 case Intrinsic::x86_avx_vtestc_ps:
14687 case Intrinsic::x86_avx_vtestnzc_ps:
14688 case Intrinsic::x86_avx_vtestz_pd:
14689 case Intrinsic::x86_avx_vtestc_pd:
14690 case Intrinsic::x86_avx_vtestnzc_pd:
14691 case Intrinsic::x86_avx_vtestz_ps_256:
14692 case Intrinsic::x86_avx_vtestc_ps_256:
14693 case Intrinsic::x86_avx_vtestnzc_ps_256:
14694 case Intrinsic::x86_avx_vtestz_pd_256:
14695 case Intrinsic::x86_avx_vtestc_pd_256:
14696 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14697 bool IsTestPacked = false;
14700 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14701 case Intrinsic::x86_avx_vtestz_ps:
14702 case Intrinsic::x86_avx_vtestz_pd:
14703 case Intrinsic::x86_avx_vtestz_ps_256:
14704 case Intrinsic::x86_avx_vtestz_pd_256:
14705 IsTestPacked = true; // Fallthrough
14706 case Intrinsic::x86_sse41_ptestz:
14707 case Intrinsic::x86_avx_ptestz_256:
14709 X86CC = X86::COND_E;
14711 case Intrinsic::x86_avx_vtestc_ps:
14712 case Intrinsic::x86_avx_vtestc_pd:
14713 case Intrinsic::x86_avx_vtestc_ps_256:
14714 case Intrinsic::x86_avx_vtestc_pd_256:
14715 IsTestPacked = true; // Fallthrough
14716 case Intrinsic::x86_sse41_ptestc:
14717 case Intrinsic::x86_avx_ptestc_256:
14719 X86CC = X86::COND_B;
14721 case Intrinsic::x86_avx_vtestnzc_ps:
14722 case Intrinsic::x86_avx_vtestnzc_pd:
14723 case Intrinsic::x86_avx_vtestnzc_ps_256:
14724 case Intrinsic::x86_avx_vtestnzc_pd_256:
14725 IsTestPacked = true; // Fallthrough
14726 case Intrinsic::x86_sse41_ptestnzc:
14727 case Intrinsic::x86_avx_ptestnzc_256:
14729 X86CC = X86::COND_A;
14733 SDValue LHS = Op.getOperand(1);
14734 SDValue RHS = Op.getOperand(2);
14735 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14736 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14737 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14738 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14739 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14741 case Intrinsic::x86_avx512_kortestz_w:
14742 case Intrinsic::x86_avx512_kortestc_w: {
14743 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14744 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14745 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14746 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14747 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14748 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
14749 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14752 // SSE/AVX shift intrinsics
14753 case Intrinsic::x86_sse2_psll_w:
14754 case Intrinsic::x86_sse2_psll_d:
14755 case Intrinsic::x86_sse2_psll_q:
14756 case Intrinsic::x86_avx2_psll_w:
14757 case Intrinsic::x86_avx2_psll_d:
14758 case Intrinsic::x86_avx2_psll_q:
14759 case Intrinsic::x86_sse2_psrl_w:
14760 case Intrinsic::x86_sse2_psrl_d:
14761 case Intrinsic::x86_sse2_psrl_q:
14762 case Intrinsic::x86_avx2_psrl_w:
14763 case Intrinsic::x86_avx2_psrl_d:
14764 case Intrinsic::x86_avx2_psrl_q:
14765 case Intrinsic::x86_sse2_psra_w:
14766 case Intrinsic::x86_sse2_psra_d:
14767 case Intrinsic::x86_avx2_psra_w:
14768 case Intrinsic::x86_avx2_psra_d: {
14771 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14772 case Intrinsic::x86_sse2_psll_w:
14773 case Intrinsic::x86_sse2_psll_d:
14774 case Intrinsic::x86_sse2_psll_q:
14775 case Intrinsic::x86_avx2_psll_w:
14776 case Intrinsic::x86_avx2_psll_d:
14777 case Intrinsic::x86_avx2_psll_q:
14778 Opcode = X86ISD::VSHL;
14780 case Intrinsic::x86_sse2_psrl_w:
14781 case Intrinsic::x86_sse2_psrl_d:
14782 case Intrinsic::x86_sse2_psrl_q:
14783 case Intrinsic::x86_avx2_psrl_w:
14784 case Intrinsic::x86_avx2_psrl_d:
14785 case Intrinsic::x86_avx2_psrl_q:
14786 Opcode = X86ISD::VSRL;
14788 case Intrinsic::x86_sse2_psra_w:
14789 case Intrinsic::x86_sse2_psra_d:
14790 case Intrinsic::x86_avx2_psra_w:
14791 case Intrinsic::x86_avx2_psra_d:
14792 Opcode = X86ISD::VSRA;
14795 return DAG.getNode(Opcode, dl, Op.getValueType(),
14796 Op.getOperand(1), Op.getOperand(2));
14799 // SSE/AVX immediate shift intrinsics
14800 case Intrinsic::x86_sse2_pslli_w:
14801 case Intrinsic::x86_sse2_pslli_d:
14802 case Intrinsic::x86_sse2_pslli_q:
14803 case Intrinsic::x86_avx2_pslli_w:
14804 case Intrinsic::x86_avx2_pslli_d:
14805 case Intrinsic::x86_avx2_pslli_q:
14806 case Intrinsic::x86_sse2_psrli_w:
14807 case Intrinsic::x86_sse2_psrli_d:
14808 case Intrinsic::x86_sse2_psrli_q:
14809 case Intrinsic::x86_avx2_psrli_w:
14810 case Intrinsic::x86_avx2_psrli_d:
14811 case Intrinsic::x86_avx2_psrli_q:
14812 case Intrinsic::x86_sse2_psrai_w:
14813 case Intrinsic::x86_sse2_psrai_d:
14814 case Intrinsic::x86_avx2_psrai_w:
14815 case Intrinsic::x86_avx2_psrai_d: {
14818 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14819 case Intrinsic::x86_sse2_pslli_w:
14820 case Intrinsic::x86_sse2_pslli_d:
14821 case Intrinsic::x86_sse2_pslli_q:
14822 case Intrinsic::x86_avx2_pslli_w:
14823 case Intrinsic::x86_avx2_pslli_d:
14824 case Intrinsic::x86_avx2_pslli_q:
14825 Opcode = X86ISD::VSHLI;
14827 case Intrinsic::x86_sse2_psrli_w:
14828 case Intrinsic::x86_sse2_psrli_d:
14829 case Intrinsic::x86_sse2_psrli_q:
14830 case Intrinsic::x86_avx2_psrli_w:
14831 case Intrinsic::x86_avx2_psrli_d:
14832 case Intrinsic::x86_avx2_psrli_q:
14833 Opcode = X86ISD::VSRLI;
14835 case Intrinsic::x86_sse2_psrai_w:
14836 case Intrinsic::x86_sse2_psrai_d:
14837 case Intrinsic::x86_avx2_psrai_w:
14838 case Intrinsic::x86_avx2_psrai_d:
14839 Opcode = X86ISD::VSRAI;
14842 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
14843 Op.getOperand(1), Op.getOperand(2), DAG);
14846 case Intrinsic::x86_sse42_pcmpistria128:
14847 case Intrinsic::x86_sse42_pcmpestria128:
14848 case Intrinsic::x86_sse42_pcmpistric128:
14849 case Intrinsic::x86_sse42_pcmpestric128:
14850 case Intrinsic::x86_sse42_pcmpistrio128:
14851 case Intrinsic::x86_sse42_pcmpestrio128:
14852 case Intrinsic::x86_sse42_pcmpistris128:
14853 case Intrinsic::x86_sse42_pcmpestris128:
14854 case Intrinsic::x86_sse42_pcmpistriz128:
14855 case Intrinsic::x86_sse42_pcmpestriz128: {
14859 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14860 case Intrinsic::x86_sse42_pcmpistria128:
14861 Opcode = X86ISD::PCMPISTRI;
14862 X86CC = X86::COND_A;
14864 case Intrinsic::x86_sse42_pcmpestria128:
14865 Opcode = X86ISD::PCMPESTRI;
14866 X86CC = X86::COND_A;
14868 case Intrinsic::x86_sse42_pcmpistric128:
14869 Opcode = X86ISD::PCMPISTRI;
14870 X86CC = X86::COND_B;
14872 case Intrinsic::x86_sse42_pcmpestric128:
14873 Opcode = X86ISD::PCMPESTRI;
14874 X86CC = X86::COND_B;
14876 case Intrinsic::x86_sse42_pcmpistrio128:
14877 Opcode = X86ISD::PCMPISTRI;
14878 X86CC = X86::COND_O;
14880 case Intrinsic::x86_sse42_pcmpestrio128:
14881 Opcode = X86ISD::PCMPESTRI;
14882 X86CC = X86::COND_O;
14884 case Intrinsic::x86_sse42_pcmpistris128:
14885 Opcode = X86ISD::PCMPISTRI;
14886 X86CC = X86::COND_S;
14888 case Intrinsic::x86_sse42_pcmpestris128:
14889 Opcode = X86ISD::PCMPESTRI;
14890 X86CC = X86::COND_S;
14892 case Intrinsic::x86_sse42_pcmpistriz128:
14893 Opcode = X86ISD::PCMPISTRI;
14894 X86CC = X86::COND_E;
14896 case Intrinsic::x86_sse42_pcmpestriz128:
14897 Opcode = X86ISD::PCMPESTRI;
14898 X86CC = X86::COND_E;
14901 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14902 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14903 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
14904 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14905 DAG.getConstant(X86CC, MVT::i8),
14906 SDValue(PCMP.getNode(), 1));
14907 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14910 case Intrinsic::x86_sse42_pcmpistri128:
14911 case Intrinsic::x86_sse42_pcmpestri128: {
14913 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
14914 Opcode = X86ISD::PCMPISTRI;
14916 Opcode = X86ISD::PCMPESTRI;
14918 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14919 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14920 return DAG.getNode(Opcode, dl, VTs, NewOps);
14923 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
14924 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
14925 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
14926 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
14927 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
14928 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
14929 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
14930 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
14931 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
14932 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
14933 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
14934 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
14935 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
14936 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
14937 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
14938 dl, Op.getValueType(),
14942 Op.getOperand(4), Op.getOperand(1), DAG);
14947 case Intrinsic::x86_fma_vfmadd_ps:
14948 case Intrinsic::x86_fma_vfmadd_pd:
14949 case Intrinsic::x86_fma_vfmsub_ps:
14950 case Intrinsic::x86_fma_vfmsub_pd:
14951 case Intrinsic::x86_fma_vfnmadd_ps:
14952 case Intrinsic::x86_fma_vfnmadd_pd:
14953 case Intrinsic::x86_fma_vfnmsub_ps:
14954 case Intrinsic::x86_fma_vfnmsub_pd:
14955 case Intrinsic::x86_fma_vfmaddsub_ps:
14956 case Intrinsic::x86_fma_vfmaddsub_pd:
14957 case Intrinsic::x86_fma_vfmsubadd_ps:
14958 case Intrinsic::x86_fma_vfmsubadd_pd:
14959 case Intrinsic::x86_fma_vfmadd_ps_256:
14960 case Intrinsic::x86_fma_vfmadd_pd_256:
14961 case Intrinsic::x86_fma_vfmsub_ps_256:
14962 case Intrinsic::x86_fma_vfmsub_pd_256:
14963 case Intrinsic::x86_fma_vfnmadd_ps_256:
14964 case Intrinsic::x86_fma_vfnmadd_pd_256:
14965 case Intrinsic::x86_fma_vfnmsub_ps_256:
14966 case Intrinsic::x86_fma_vfnmsub_pd_256:
14967 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14968 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14969 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14970 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14971 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
14972 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14976 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14977 SDValue Src, SDValue Mask, SDValue Base,
14978 SDValue Index, SDValue ScaleOp, SDValue Chain,
14979 const X86Subtarget * Subtarget) {
14981 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14982 assert(C && "Invalid scale type");
14983 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14984 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14985 Index.getSimpleValueType().getVectorNumElements());
14987 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14989 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14991 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14992 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
14993 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14994 SDValue Segment = DAG.getRegister(0, MVT::i32);
14995 if (Src.getOpcode() == ISD::UNDEF)
14996 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
14997 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14998 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14999 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15000 return DAG.getMergeValues(RetOps, dl);
15003 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15004 SDValue Src, SDValue Mask, SDValue Base,
15005 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15007 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15008 assert(C && "Invalid scale type");
15009 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15010 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15011 SDValue Segment = DAG.getRegister(0, MVT::i32);
15012 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15013 Index.getSimpleValueType().getVectorNumElements());
15015 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15017 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15019 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15020 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15021 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15022 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15023 return SDValue(Res, 1);
15026 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15027 SDValue Mask, SDValue Base, SDValue Index,
15028 SDValue ScaleOp, SDValue Chain) {
15030 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15031 assert(C && "Invalid scale type");
15032 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15033 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15034 SDValue Segment = DAG.getRegister(0, MVT::i32);
15036 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15038 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15040 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15042 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15043 //SDVTList VTs = DAG.getVTList(MVT::Other);
15044 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15045 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15046 return SDValue(Res, 0);
15049 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15050 // read performance monitor counters (x86_rdpmc).
15051 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15052 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15053 SmallVectorImpl<SDValue> &Results) {
15054 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15055 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15058 // The ECX register is used to select the index of the performance counter
15060 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15062 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15064 // Reads the content of a 64-bit performance counter and returns it in the
15065 // registers EDX:EAX.
15066 if (Subtarget->is64Bit()) {
15067 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15068 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15071 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15072 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15075 Chain = HI.getValue(1);
15077 if (Subtarget->is64Bit()) {
15078 // The EAX register is loaded with the low-order 32 bits. The EDX register
15079 // is loaded with the supported high-order bits of the counter.
15080 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15081 DAG.getConstant(32, MVT::i8));
15082 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15083 Results.push_back(Chain);
15087 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15088 SDValue Ops[] = { LO, HI };
15089 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15090 Results.push_back(Pair);
15091 Results.push_back(Chain);
15094 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15095 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15096 // also used to custom lower READCYCLECOUNTER nodes.
15097 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15098 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15099 SmallVectorImpl<SDValue> &Results) {
15100 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15101 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15104 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15105 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15106 // and the EAX register is loaded with the low-order 32 bits.
15107 if (Subtarget->is64Bit()) {
15108 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15109 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15112 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15113 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15116 SDValue Chain = HI.getValue(1);
15118 if (Opcode == X86ISD::RDTSCP_DAG) {
15119 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15121 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15122 // the ECX register. Add 'ecx' explicitly to the chain.
15123 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15125 // Explicitly store the content of ECX at the location passed in input
15126 // to the 'rdtscp' intrinsic.
15127 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15128 MachinePointerInfo(), false, false, 0);
15131 if (Subtarget->is64Bit()) {
15132 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15133 // the EAX register is loaded with the low-order 32 bits.
15134 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15135 DAG.getConstant(32, MVT::i8));
15136 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15137 Results.push_back(Chain);
15141 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15142 SDValue Ops[] = { LO, HI };
15143 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15144 Results.push_back(Pair);
15145 Results.push_back(Chain);
15148 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15149 SelectionDAG &DAG) {
15150 SmallVector<SDValue, 2> Results;
15152 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15154 return DAG.getMergeValues(Results, DL);
15157 enum IntrinsicType {
15158 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
15161 struct IntrinsicData {
15162 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
15163 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
15164 IntrinsicType Type;
15169 std::map < unsigned, IntrinsicData> IntrMap;
15170 static void InitIntinsicsMap() {
15171 static bool Initialized = false;
15174 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
15175 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
15176 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
15177 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
15178 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
15179 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
15180 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
15181 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
15182 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
15183 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
15184 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
15185 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
15186 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
15187 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
15188 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
15189 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
15190 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
15191 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
15193 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
15194 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
15195 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
15196 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
15197 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
15198 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
15199 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
15200 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
15201 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
15202 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
15203 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
15204 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
15205 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
15206 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
15207 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
15208 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
15210 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
15211 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
15212 X86::VGATHERPF1QPSm)));
15213 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
15214 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
15215 X86::VGATHERPF1QPDm)));
15216 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
15217 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
15218 X86::VGATHERPF1DPDm)));
15219 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
15220 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
15221 X86::VGATHERPF1DPSm)));
15222 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
15223 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
15224 X86::VSCATTERPF1QPSm)));
15225 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
15226 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
15227 X86::VSCATTERPF1QPDm)));
15228 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
15229 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
15230 X86::VSCATTERPF1DPDm)));
15231 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
15232 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
15233 X86::VSCATTERPF1DPSm)));
15234 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
15235 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15236 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
15237 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15238 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
15239 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15240 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
15241 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15242 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
15243 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15244 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
15245 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15246 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
15247 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
15248 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
15249 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
15250 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
15251 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
15252 IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
15253 IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
15254 Initialized = true;
15257 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15258 SelectionDAG &DAG) {
15259 InitIntinsicsMap();
15260 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15261 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
15262 if (itr == IntrMap.end())
15266 IntrinsicData Intr = itr->second;
15267 switch(Intr.Type) {
15270 // Emit the node with the right value type.
15271 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15272 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
15274 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15275 // Otherwise return the value from Rand, which is always 0, casted to i32.
15276 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15277 DAG.getConstant(1, Op->getValueType(1)),
15278 DAG.getConstant(X86::COND_B, MVT::i32),
15279 SDValue(Result.getNode(), 1) };
15280 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15281 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15284 // Return { result, isValid, chain }.
15285 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15286 SDValue(Result.getNode(), 2));
15289 //gather(v1, mask, index, base, scale);
15290 SDValue Chain = Op.getOperand(0);
15291 SDValue Src = Op.getOperand(2);
15292 SDValue Base = Op.getOperand(3);
15293 SDValue Index = Op.getOperand(4);
15294 SDValue Mask = Op.getOperand(5);
15295 SDValue Scale = Op.getOperand(6);
15296 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15300 //scatter(base, mask, index, v1, scale);
15301 SDValue Chain = Op.getOperand(0);
15302 SDValue Base = Op.getOperand(2);
15303 SDValue Mask = Op.getOperand(3);
15304 SDValue Index = Op.getOperand(4);
15305 SDValue Src = Op.getOperand(5);
15306 SDValue Scale = Op.getOperand(6);
15307 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15310 SDValue Hint = Op.getOperand(6);
15312 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
15313 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
15314 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
15315 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
15316 SDValue Chain = Op.getOperand(0);
15317 SDValue Mask = Op.getOperand(2);
15318 SDValue Index = Op.getOperand(3);
15319 SDValue Base = Op.getOperand(4);
15320 SDValue Scale = Op.getOperand(5);
15321 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15323 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15325 SmallVector<SDValue, 2> Results;
15326 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
15327 return DAG.getMergeValues(Results, dl);
15329 // Read Performance Monitoring Counters.
15331 SmallVector<SDValue, 2> Results;
15332 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15333 return DAG.getMergeValues(Results, dl);
15335 // XTEST intrinsics.
15337 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15338 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
15339 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15340 DAG.getConstant(X86::COND_NE, MVT::i8),
15342 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15343 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15344 Ret, SDValue(InTrans.getNode(), 1));
15347 llvm_unreachable("Unknown Intrinsic Type");
15350 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15351 SelectionDAG &DAG) const {
15352 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15353 MFI->setReturnAddressIsTaken(true);
15355 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15358 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15360 EVT PtrVT = getPointerTy();
15363 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15364 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15365 DAG.getSubtarget().getRegisterInfo());
15366 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15367 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15368 DAG.getNode(ISD::ADD, dl, PtrVT,
15369 FrameAddr, Offset),
15370 MachinePointerInfo(), false, false, false, 0);
15373 // Just load the return address.
15374 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15375 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15376 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15379 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15380 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15381 MFI->setFrameAddressIsTaken(true);
15383 EVT VT = Op.getValueType();
15384 SDLoc dl(Op); // FIXME probably not meaningful
15385 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15386 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15387 DAG.getSubtarget().getRegisterInfo());
15388 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15389 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15390 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15391 "Invalid Frame Register!");
15392 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15394 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15395 MachinePointerInfo(),
15396 false, false, false, 0);
15400 // FIXME? Maybe this could be a TableGen attribute on some registers and
15401 // this table could be generated automatically from RegInfo.
15402 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15404 unsigned Reg = StringSwitch<unsigned>(RegName)
15405 .Case("esp", X86::ESP)
15406 .Case("rsp", X86::RSP)
15410 report_fatal_error("Invalid register name global variable");
15413 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15414 SelectionDAG &DAG) const {
15415 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15416 DAG.getSubtarget().getRegisterInfo());
15417 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15420 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15421 SDValue Chain = Op.getOperand(0);
15422 SDValue Offset = Op.getOperand(1);
15423 SDValue Handler = Op.getOperand(2);
15426 EVT PtrVT = getPointerTy();
15427 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15428 DAG.getSubtarget().getRegisterInfo());
15429 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15430 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15431 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15432 "Invalid Frame Register!");
15433 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15434 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15436 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15437 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15438 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15439 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15441 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15443 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15444 DAG.getRegister(StoreAddrReg, PtrVT));
15447 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15448 SelectionDAG &DAG) const {
15450 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15451 DAG.getVTList(MVT::i32, MVT::Other),
15452 Op.getOperand(0), Op.getOperand(1));
15455 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15456 SelectionDAG &DAG) const {
15458 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15459 Op.getOperand(0), Op.getOperand(1));
15462 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15463 return Op.getOperand(0);
15466 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15467 SelectionDAG &DAG) const {
15468 SDValue Root = Op.getOperand(0);
15469 SDValue Trmp = Op.getOperand(1); // trampoline
15470 SDValue FPtr = Op.getOperand(2); // nested function
15471 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15474 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15475 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
15477 if (Subtarget->is64Bit()) {
15478 SDValue OutChains[6];
15480 // Large code-model.
15481 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15482 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15484 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15485 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15487 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15489 // Load the pointer to the nested function into R11.
15490 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15491 SDValue Addr = Trmp;
15492 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15493 Addr, MachinePointerInfo(TrmpAddr),
15496 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15497 DAG.getConstant(2, MVT::i64));
15498 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15499 MachinePointerInfo(TrmpAddr, 2),
15502 // Load the 'nest' parameter value into R10.
15503 // R10 is specified in X86CallingConv.td
15504 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15505 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15506 DAG.getConstant(10, MVT::i64));
15507 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15508 Addr, MachinePointerInfo(TrmpAddr, 10),
15511 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15512 DAG.getConstant(12, MVT::i64));
15513 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15514 MachinePointerInfo(TrmpAddr, 12),
15517 // Jump to the nested function.
15518 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15519 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15520 DAG.getConstant(20, MVT::i64));
15521 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15522 Addr, MachinePointerInfo(TrmpAddr, 20),
15525 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15526 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15527 DAG.getConstant(22, MVT::i64));
15528 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15529 MachinePointerInfo(TrmpAddr, 22),
15532 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15534 const Function *Func =
15535 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15536 CallingConv::ID CC = Func->getCallingConv();
15541 llvm_unreachable("Unsupported calling convention");
15542 case CallingConv::C:
15543 case CallingConv::X86_StdCall: {
15544 // Pass 'nest' parameter in ECX.
15545 // Must be kept in sync with X86CallingConv.td
15546 NestReg = X86::ECX;
15548 // Check that ECX wasn't needed by an 'inreg' parameter.
15549 FunctionType *FTy = Func->getFunctionType();
15550 const AttributeSet &Attrs = Func->getAttributes();
15552 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15553 unsigned InRegCount = 0;
15556 for (FunctionType::param_iterator I = FTy->param_begin(),
15557 E = FTy->param_end(); I != E; ++I, ++Idx)
15558 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15559 // FIXME: should only count parameters that are lowered to integers.
15560 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15562 if (InRegCount > 2) {
15563 report_fatal_error("Nest register in use - reduce number of inreg"
15569 case CallingConv::X86_FastCall:
15570 case CallingConv::X86_ThisCall:
15571 case CallingConv::Fast:
15572 // Pass 'nest' parameter in EAX.
15573 // Must be kept in sync with X86CallingConv.td
15574 NestReg = X86::EAX;
15578 SDValue OutChains[4];
15579 SDValue Addr, Disp;
15581 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15582 DAG.getConstant(10, MVT::i32));
15583 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15585 // This is storing the opcode for MOV32ri.
15586 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15587 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15588 OutChains[0] = DAG.getStore(Root, dl,
15589 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15590 Trmp, MachinePointerInfo(TrmpAddr),
15593 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15594 DAG.getConstant(1, MVT::i32));
15595 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15596 MachinePointerInfo(TrmpAddr, 1),
15599 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15600 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15601 DAG.getConstant(5, MVT::i32));
15602 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15603 MachinePointerInfo(TrmpAddr, 5),
15606 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15607 DAG.getConstant(6, MVT::i32));
15608 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15609 MachinePointerInfo(TrmpAddr, 6),
15612 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15616 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15617 SelectionDAG &DAG) const {
15619 The rounding mode is in bits 11:10 of FPSR, and has the following
15621 00 Round to nearest
15626 FLT_ROUNDS, on the other hand, expects the following:
15633 To perform the conversion, we do:
15634 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15637 MachineFunction &MF = DAG.getMachineFunction();
15638 const TargetMachine &TM = MF.getTarget();
15639 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
15640 unsigned StackAlignment = TFI.getStackAlignment();
15641 MVT VT = Op.getSimpleValueType();
15644 // Save FP Control Word to stack slot
15645 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15646 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15648 MachineMemOperand *MMO =
15649 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15650 MachineMemOperand::MOStore, 2, 2);
15652 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15653 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15654 DAG.getVTList(MVT::Other),
15655 Ops, MVT::i16, MMO);
15657 // Load FP Control Word from stack slot
15658 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15659 MachinePointerInfo(), false, false, false, 0);
15661 // Transform as necessary
15663 DAG.getNode(ISD::SRL, DL, MVT::i16,
15664 DAG.getNode(ISD::AND, DL, MVT::i16,
15665 CWD, DAG.getConstant(0x800, MVT::i16)),
15666 DAG.getConstant(11, MVT::i8));
15668 DAG.getNode(ISD::SRL, DL, MVT::i16,
15669 DAG.getNode(ISD::AND, DL, MVT::i16,
15670 CWD, DAG.getConstant(0x400, MVT::i16)),
15671 DAG.getConstant(9, MVT::i8));
15674 DAG.getNode(ISD::AND, DL, MVT::i16,
15675 DAG.getNode(ISD::ADD, DL, MVT::i16,
15676 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15677 DAG.getConstant(1, MVT::i16)),
15678 DAG.getConstant(3, MVT::i16));
15680 return DAG.getNode((VT.getSizeInBits() < 16 ?
15681 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15684 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15685 MVT VT = Op.getSimpleValueType();
15687 unsigned NumBits = VT.getSizeInBits();
15690 Op = Op.getOperand(0);
15691 if (VT == MVT::i8) {
15692 // Zero extend to i32 since there is not an i8 bsr.
15694 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15697 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15698 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15699 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15701 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15704 DAG.getConstant(NumBits+NumBits-1, OpVT),
15705 DAG.getConstant(X86::COND_E, MVT::i8),
15708 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15710 // Finally xor with NumBits-1.
15711 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15714 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15718 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15719 MVT VT = Op.getSimpleValueType();
15721 unsigned NumBits = VT.getSizeInBits();
15724 Op = Op.getOperand(0);
15725 if (VT == MVT::i8) {
15726 // Zero extend to i32 since there is not an i8 bsr.
15728 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15731 // Issue a bsr (scan bits in reverse).
15732 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15733 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15735 // And xor with NumBits-1.
15736 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15739 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15743 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15744 MVT VT = Op.getSimpleValueType();
15745 unsigned NumBits = VT.getSizeInBits();
15747 Op = Op.getOperand(0);
15749 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15750 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15751 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15753 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15756 DAG.getConstant(NumBits, VT),
15757 DAG.getConstant(X86::COND_E, MVT::i8),
15760 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15763 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15764 // ones, and then concatenate the result back.
15765 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15766 MVT VT = Op.getSimpleValueType();
15768 assert(VT.is256BitVector() && VT.isInteger() &&
15769 "Unsupported value type for operation");
15771 unsigned NumElems = VT.getVectorNumElements();
15774 // Extract the LHS vectors
15775 SDValue LHS = Op.getOperand(0);
15776 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15777 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15779 // Extract the RHS vectors
15780 SDValue RHS = Op.getOperand(1);
15781 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15782 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15784 MVT EltVT = VT.getVectorElementType();
15785 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15787 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15788 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15789 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15792 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15793 assert(Op.getSimpleValueType().is256BitVector() &&
15794 Op.getSimpleValueType().isInteger() &&
15795 "Only handle AVX 256-bit vector integer operation");
15796 return Lower256IntArith(Op, DAG);
15799 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15800 assert(Op.getSimpleValueType().is256BitVector() &&
15801 Op.getSimpleValueType().isInteger() &&
15802 "Only handle AVX 256-bit vector integer operation");
15803 return Lower256IntArith(Op, DAG);
15806 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15807 SelectionDAG &DAG) {
15809 MVT VT = Op.getSimpleValueType();
15811 // Decompose 256-bit ops into smaller 128-bit ops.
15812 if (VT.is256BitVector() && !Subtarget->hasInt256())
15813 return Lower256IntArith(Op, DAG);
15815 SDValue A = Op.getOperand(0);
15816 SDValue B = Op.getOperand(1);
15818 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15819 if (VT == MVT::v4i32) {
15820 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15821 "Should not custom lower when pmuldq is available!");
15823 // Extract the odd parts.
15824 static const int UnpackMask[] = { 1, -1, 3, -1 };
15825 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15826 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15828 // Multiply the even parts.
15829 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15830 // Now multiply odd parts.
15831 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15833 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15834 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15836 // Merge the two vectors back together with a shuffle. This expands into 2
15838 static const int ShufMask[] = { 0, 4, 2, 6 };
15839 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15842 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15843 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15845 // Ahi = psrlqi(a, 32);
15846 // Bhi = psrlqi(b, 32);
15848 // AloBlo = pmuludq(a, b);
15849 // AloBhi = pmuludq(a, Bhi);
15850 // AhiBlo = pmuludq(Ahi, b);
15852 // AloBhi = psllqi(AloBhi, 32);
15853 // AhiBlo = psllqi(AhiBlo, 32);
15854 // return AloBlo + AloBhi + AhiBlo;
15856 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15857 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15859 // Bit cast to 32-bit vectors for MULUDQ
15860 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15861 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15862 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15863 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15864 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15865 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15867 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15868 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15869 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15871 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15872 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15874 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15875 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15878 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15879 assert(Subtarget->isTargetWin64() && "Unexpected target");
15880 EVT VT = Op.getValueType();
15881 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15882 "Unexpected return type for lowering");
15886 switch (Op->getOpcode()) {
15887 default: llvm_unreachable("Unexpected request for libcall!");
15888 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15889 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15890 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15891 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15892 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15893 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15897 SDValue InChain = DAG.getEntryNode();
15899 TargetLowering::ArgListTy Args;
15900 TargetLowering::ArgListEntry Entry;
15901 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15902 EVT ArgVT = Op->getOperand(i).getValueType();
15903 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15904 "Unexpected argument type for lowering");
15905 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15906 Entry.Node = StackPtr;
15907 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15909 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15910 Entry.Ty = PointerType::get(ArgTy,0);
15911 Entry.isSExt = false;
15912 Entry.isZExt = false;
15913 Args.push_back(Entry);
15916 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15919 TargetLowering::CallLoweringInfo CLI(DAG);
15920 CLI.setDebugLoc(dl).setChain(InChain)
15921 .setCallee(getLibcallCallingConv(LC),
15922 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15923 Callee, std::move(Args), 0)
15924 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15926 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15927 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15930 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
15931 SelectionDAG &DAG) {
15932 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
15933 EVT VT = Op0.getValueType();
15936 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
15937 (VT == MVT::v8i32 && Subtarget->hasInt256()));
15939 // PMULxD operations multiply each even value (starting at 0) of LHS with
15940 // the related value of RHS and produce a widen result.
15941 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15942 // => <2 x i64> <ae|cg>
15944 // In other word, to have all the results, we need to perform two PMULxD:
15945 // 1. one with the even values.
15946 // 2. one with the odd values.
15947 // To achieve #2, with need to place the odd values at an even position.
15949 // Place the odd value at an even position (basically, shift all values 1
15950 // step to the left):
15951 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
15952 // <a|b|c|d> => <b|undef|d|undef>
15953 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
15954 // <e|f|g|h> => <f|undef|h|undef>
15955 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
15957 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
15959 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15960 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
15962 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
15963 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15964 // => <2 x i64> <ae|cg>
15965 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
15966 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
15967 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
15968 // => <2 x i64> <bf|dh>
15969 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
15970 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
15972 // Shuffle it back into the right order.
15973 SDValue Highs, Lows;
15974 if (VT == MVT::v8i32) {
15975 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
15976 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15977 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
15978 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15980 const int HighMask[] = {1, 5, 3, 7};
15981 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15982 const int LowMask[] = {0, 4, 2, 6};
15983 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15986 // If we have a signed multiply but no PMULDQ fix up the high parts of a
15987 // unsigned multiply.
15988 if (IsSigned && !Subtarget->hasSSE41()) {
15990 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
15991 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
15992 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
15993 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
15994 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
15996 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
15997 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16000 // The first result of MUL_LOHI is actually the low value, followed by the
16002 SDValue Ops[] = {Lows, Highs};
16003 return DAG.getMergeValues(Ops, dl);
16006 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16007 const X86Subtarget *Subtarget) {
16008 MVT VT = Op.getSimpleValueType();
16010 SDValue R = Op.getOperand(0);
16011 SDValue Amt = Op.getOperand(1);
16013 // Optimize shl/srl/sra with constant shift amount.
16014 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16015 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16016 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16018 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16019 (Subtarget->hasInt256() &&
16020 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16021 (Subtarget->hasAVX512() &&
16022 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16023 if (Op.getOpcode() == ISD::SHL)
16024 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16026 if (Op.getOpcode() == ISD::SRL)
16027 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16029 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16030 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16034 if (VT == MVT::v16i8) {
16035 if (Op.getOpcode() == ISD::SHL) {
16036 // Make a large shift.
16037 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16038 MVT::v8i16, R, ShiftAmt,
16040 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16041 // Zero out the rightmost bits.
16042 SmallVector<SDValue, 16> V(16,
16043 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16045 return DAG.getNode(ISD::AND, dl, VT, SHL,
16046 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16048 if (Op.getOpcode() == ISD::SRL) {
16049 // Make a large shift.
16050 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16051 MVT::v8i16, R, ShiftAmt,
16053 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16054 // Zero out the leftmost bits.
16055 SmallVector<SDValue, 16> V(16,
16056 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16058 return DAG.getNode(ISD::AND, dl, VT, SRL,
16059 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16061 if (Op.getOpcode() == ISD::SRA) {
16062 if (ShiftAmt == 7) {
16063 // R s>> 7 === R s< 0
16064 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16065 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16068 // R s>> a === ((R u>> a) ^ m) - m
16069 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16070 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16072 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16073 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16074 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16077 llvm_unreachable("Unknown shift opcode.");
16080 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16081 if (Op.getOpcode() == ISD::SHL) {
16082 // Make a large shift.
16083 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16084 MVT::v16i16, R, ShiftAmt,
16086 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16087 // Zero out the rightmost bits.
16088 SmallVector<SDValue, 32> V(32,
16089 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16091 return DAG.getNode(ISD::AND, dl, VT, SHL,
16092 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16094 if (Op.getOpcode() == ISD::SRL) {
16095 // Make a large shift.
16096 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16097 MVT::v16i16, R, ShiftAmt,
16099 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16100 // Zero out the leftmost bits.
16101 SmallVector<SDValue, 32> V(32,
16102 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16104 return DAG.getNode(ISD::AND, dl, VT, SRL,
16105 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16107 if (Op.getOpcode() == ISD::SRA) {
16108 if (ShiftAmt == 7) {
16109 // R s>> 7 === R s< 0
16110 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16111 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16114 // R s>> a === ((R u>> a) ^ m) - m
16115 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16116 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16118 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16119 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16120 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16123 llvm_unreachable("Unknown shift opcode.");
16128 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16129 if (!Subtarget->is64Bit() &&
16130 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16131 Amt.getOpcode() == ISD::BITCAST &&
16132 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16133 Amt = Amt.getOperand(0);
16134 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16135 VT.getVectorNumElements();
16136 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16137 uint64_t ShiftAmt = 0;
16138 for (unsigned i = 0; i != Ratio; ++i) {
16139 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16143 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16145 // Check remaining shift amounts.
16146 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16147 uint64_t ShAmt = 0;
16148 for (unsigned j = 0; j != Ratio; ++j) {
16149 ConstantSDNode *C =
16150 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16154 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16156 if (ShAmt != ShiftAmt)
16159 switch (Op.getOpcode()) {
16161 llvm_unreachable("Unknown shift opcode!");
16163 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16166 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16169 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16177 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16178 const X86Subtarget* Subtarget) {
16179 MVT VT = Op.getSimpleValueType();
16181 SDValue R = Op.getOperand(0);
16182 SDValue Amt = Op.getOperand(1);
16184 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16185 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16186 (Subtarget->hasInt256() &&
16187 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16188 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16189 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16191 EVT EltVT = VT.getVectorElementType();
16193 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16194 unsigned NumElts = VT.getVectorNumElements();
16196 for (i = 0; i != NumElts; ++i) {
16197 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16201 for (j = i; j != NumElts; ++j) {
16202 SDValue Arg = Amt.getOperand(j);
16203 if (Arg.getOpcode() == ISD::UNDEF) continue;
16204 if (Arg != Amt.getOperand(i))
16207 if (i != NumElts && j == NumElts)
16208 BaseShAmt = Amt.getOperand(i);
16210 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16211 Amt = Amt.getOperand(0);
16212 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16213 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16214 SDValue InVec = Amt.getOperand(0);
16215 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16216 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16218 for (; i != NumElts; ++i) {
16219 SDValue Arg = InVec.getOperand(i);
16220 if (Arg.getOpcode() == ISD::UNDEF) continue;
16224 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16225 if (ConstantSDNode *C =
16226 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16227 unsigned SplatIdx =
16228 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16229 if (C->getZExtValue() == SplatIdx)
16230 BaseShAmt = InVec.getOperand(1);
16233 if (!BaseShAmt.getNode())
16234 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16235 DAG.getIntPtrConstant(0));
16239 if (BaseShAmt.getNode()) {
16240 if (EltVT.bitsGT(MVT::i32))
16241 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16242 else if (EltVT.bitsLT(MVT::i32))
16243 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16245 switch (Op.getOpcode()) {
16247 llvm_unreachable("Unknown shift opcode!");
16249 switch (VT.SimpleTy) {
16250 default: return SDValue();
16259 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16262 switch (VT.SimpleTy) {
16263 default: return SDValue();
16270 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16273 switch (VT.SimpleTy) {
16274 default: return SDValue();
16283 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16289 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16290 if (!Subtarget->is64Bit() &&
16291 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16292 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16293 Amt.getOpcode() == ISD::BITCAST &&
16294 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16295 Amt = Amt.getOperand(0);
16296 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16297 VT.getVectorNumElements();
16298 std::vector<SDValue> Vals(Ratio);
16299 for (unsigned i = 0; i != Ratio; ++i)
16300 Vals[i] = Amt.getOperand(i);
16301 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16302 for (unsigned j = 0; j != Ratio; ++j)
16303 if (Vals[j] != Amt.getOperand(i + j))
16306 switch (Op.getOpcode()) {
16308 llvm_unreachable("Unknown shift opcode!");
16310 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16312 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16314 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16321 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16322 SelectionDAG &DAG) {
16323 MVT VT = Op.getSimpleValueType();
16325 SDValue R = Op.getOperand(0);
16326 SDValue Amt = Op.getOperand(1);
16329 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16330 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16332 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16336 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16340 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16342 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16343 if (Subtarget->hasInt256()) {
16344 if (Op.getOpcode() == ISD::SRL &&
16345 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16346 VT == MVT::v4i64 || VT == MVT::v8i32))
16348 if (Op.getOpcode() == ISD::SHL &&
16349 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16350 VT == MVT::v4i64 || VT == MVT::v8i32))
16352 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16356 // If possible, lower this packed shift into a vector multiply instead of
16357 // expanding it into a sequence of scalar shifts.
16358 // Do this only if the vector shift count is a constant build_vector.
16359 if (Op.getOpcode() == ISD::SHL &&
16360 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16361 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16362 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16363 SmallVector<SDValue, 8> Elts;
16364 EVT SVT = VT.getScalarType();
16365 unsigned SVTBits = SVT.getSizeInBits();
16366 const APInt &One = APInt(SVTBits, 1);
16367 unsigned NumElems = VT.getVectorNumElements();
16369 for (unsigned i=0; i !=NumElems; ++i) {
16370 SDValue Op = Amt->getOperand(i);
16371 if (Op->getOpcode() == ISD::UNDEF) {
16372 Elts.push_back(Op);
16376 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16377 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16378 uint64_t ShAmt = C.getZExtValue();
16379 if (ShAmt >= SVTBits) {
16380 Elts.push_back(DAG.getUNDEF(SVT));
16383 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16385 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16386 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16389 // Lower SHL with variable shift amount.
16390 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16391 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16393 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16394 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16395 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16396 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16399 // If possible, lower this shift as a sequence of two shifts by
16400 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16402 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16404 // Could be rewritten as:
16405 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16407 // The advantage is that the two shifts from the example would be
16408 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16409 // the vector shift into four scalar shifts plus four pairs of vector
16411 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16412 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16413 unsigned TargetOpcode = X86ISD::MOVSS;
16414 bool CanBeSimplified;
16415 // The splat value for the first packed shift (the 'X' from the example).
16416 SDValue Amt1 = Amt->getOperand(0);
16417 // The splat value for the second packed shift (the 'Y' from the example).
16418 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16419 Amt->getOperand(2);
16421 // See if it is possible to replace this node with a sequence of
16422 // two shifts followed by a MOVSS/MOVSD
16423 if (VT == MVT::v4i32) {
16424 // Check if it is legal to use a MOVSS.
16425 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16426 Amt2 == Amt->getOperand(3);
16427 if (!CanBeSimplified) {
16428 // Otherwise, check if we can still simplify this node using a MOVSD.
16429 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16430 Amt->getOperand(2) == Amt->getOperand(3);
16431 TargetOpcode = X86ISD::MOVSD;
16432 Amt2 = Amt->getOperand(2);
16435 // Do similar checks for the case where the machine value type
16437 CanBeSimplified = Amt1 == Amt->getOperand(1);
16438 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16439 CanBeSimplified = Amt2 == Amt->getOperand(i);
16441 if (!CanBeSimplified) {
16442 TargetOpcode = X86ISD::MOVSD;
16443 CanBeSimplified = true;
16444 Amt2 = Amt->getOperand(4);
16445 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16446 CanBeSimplified = Amt1 == Amt->getOperand(i);
16447 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16448 CanBeSimplified = Amt2 == Amt->getOperand(j);
16452 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16453 isa<ConstantSDNode>(Amt2)) {
16454 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16455 EVT CastVT = MVT::v4i32;
16457 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16458 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16460 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16461 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16462 if (TargetOpcode == X86ISD::MOVSD)
16463 CastVT = MVT::v2i64;
16464 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16465 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16466 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16468 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16472 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16473 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16476 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16477 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16479 // Turn 'a' into a mask suitable for VSELECT
16480 SDValue VSelM = DAG.getConstant(0x80, VT);
16481 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16482 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16484 SDValue CM1 = DAG.getConstant(0x0f, VT);
16485 SDValue CM2 = DAG.getConstant(0x3f, VT);
16487 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16488 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16489 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16490 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16491 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16494 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16495 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16496 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16498 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16499 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16500 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16501 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16502 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16505 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16506 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16507 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16509 // return VSELECT(r, r+r, a);
16510 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16511 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16515 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16516 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16517 // solution better.
16518 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16519 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16521 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16522 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16523 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16524 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16525 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16528 // Decompose 256-bit shifts into smaller 128-bit shifts.
16529 if (VT.is256BitVector()) {
16530 unsigned NumElems = VT.getVectorNumElements();
16531 MVT EltVT = VT.getVectorElementType();
16532 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16534 // Extract the two vectors
16535 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16536 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16538 // Recreate the shift amount vectors
16539 SDValue Amt1, Amt2;
16540 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16541 // Constant shift amount
16542 SmallVector<SDValue, 4> Amt1Csts;
16543 SmallVector<SDValue, 4> Amt2Csts;
16544 for (unsigned i = 0; i != NumElems/2; ++i)
16545 Amt1Csts.push_back(Amt->getOperand(i));
16546 for (unsigned i = NumElems/2; i != NumElems; ++i)
16547 Amt2Csts.push_back(Amt->getOperand(i));
16549 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16550 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16552 // Variable shift amount
16553 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16554 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16557 // Issue new vector shifts for the smaller types
16558 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16559 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16561 // Concatenate the result back
16562 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16568 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16569 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16570 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16571 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16572 // has only one use.
16573 SDNode *N = Op.getNode();
16574 SDValue LHS = N->getOperand(0);
16575 SDValue RHS = N->getOperand(1);
16576 unsigned BaseOp = 0;
16579 switch (Op.getOpcode()) {
16580 default: llvm_unreachable("Unknown ovf instruction!");
16582 // A subtract of one will be selected as a INC. Note that INC doesn't
16583 // set CF, so we can't do this for UADDO.
16584 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16586 BaseOp = X86ISD::INC;
16587 Cond = X86::COND_O;
16590 BaseOp = X86ISD::ADD;
16591 Cond = X86::COND_O;
16594 BaseOp = X86ISD::ADD;
16595 Cond = X86::COND_B;
16598 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16599 // set CF, so we can't do this for USUBO.
16600 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16602 BaseOp = X86ISD::DEC;
16603 Cond = X86::COND_O;
16606 BaseOp = X86ISD::SUB;
16607 Cond = X86::COND_O;
16610 BaseOp = X86ISD::SUB;
16611 Cond = X86::COND_B;
16614 BaseOp = X86ISD::SMUL;
16615 Cond = X86::COND_O;
16617 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16618 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16620 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16623 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16624 DAG.getConstant(X86::COND_O, MVT::i32),
16625 SDValue(Sum.getNode(), 2));
16627 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16631 // Also sets EFLAGS.
16632 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16633 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16636 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16637 DAG.getConstant(Cond, MVT::i32),
16638 SDValue(Sum.getNode(), 1));
16640 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16643 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
16644 SelectionDAG &DAG) const {
16646 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
16647 MVT VT = Op.getSimpleValueType();
16649 if (!Subtarget->hasSSE2() || !VT.isVector())
16652 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
16653 ExtraVT.getScalarType().getSizeInBits();
16655 switch (VT.SimpleTy) {
16656 default: return SDValue();
16659 if (!Subtarget->hasFp256())
16661 if (!Subtarget->hasInt256()) {
16662 // needs to be split
16663 unsigned NumElems = VT.getVectorNumElements();
16665 // Extract the LHS vectors
16666 SDValue LHS = Op.getOperand(0);
16667 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16668 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16670 MVT EltVT = VT.getVectorElementType();
16671 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16673 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16674 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
16675 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
16677 SDValue Extra = DAG.getValueType(ExtraVT);
16679 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
16680 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
16682 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
16687 SDValue Op0 = Op.getOperand(0);
16688 SDValue Op00 = Op0.getOperand(0);
16690 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
16691 if (Op0.getOpcode() == ISD::BITCAST &&
16692 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
16693 // (sext (vzext x)) -> (vsext x)
16694 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
16695 if (Tmp1.getNode()) {
16696 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16697 // This folding is only valid when the in-reg type is a vector of i8,
16699 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
16700 ExtraEltVT == MVT::i32) {
16701 SDValue Tmp1Op0 = Tmp1.getOperand(0);
16702 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
16703 "This optimization is invalid without a VZEXT.");
16704 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
16710 // If the above didn't work, then just use Shift-Left + Shift-Right.
16711 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
16713 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
16719 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16720 SelectionDAG &DAG) {
16722 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16723 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16724 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16725 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16727 // The only fence that needs an instruction is a sequentially-consistent
16728 // cross-thread fence.
16729 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16730 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16731 // no-sse2). There isn't any reason to disable it if the target processor
16733 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
16734 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16736 SDValue Chain = Op.getOperand(0);
16737 SDValue Zero = DAG.getConstant(0, MVT::i32);
16739 DAG.getRegister(X86::ESP, MVT::i32), // Base
16740 DAG.getTargetConstant(1, MVT::i8), // Scale
16741 DAG.getRegister(0, MVT::i32), // Index
16742 DAG.getTargetConstant(0, MVT::i32), // Disp
16743 DAG.getRegister(0, MVT::i32), // Segment.
16747 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16748 return SDValue(Res, 0);
16751 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16752 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16755 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16756 SelectionDAG &DAG) {
16757 MVT T = Op.getSimpleValueType();
16761 switch(T.SimpleTy) {
16762 default: llvm_unreachable("Invalid value type!");
16763 case MVT::i8: Reg = X86::AL; size = 1; break;
16764 case MVT::i16: Reg = X86::AX; size = 2; break;
16765 case MVT::i32: Reg = X86::EAX; size = 4; break;
16767 assert(Subtarget->is64Bit() && "Node not type legal!");
16768 Reg = X86::RAX; size = 8;
16771 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16772 Op.getOperand(2), SDValue());
16773 SDValue Ops[] = { cpIn.getValue(0),
16776 DAG.getTargetConstant(size, MVT::i8),
16777 cpIn.getValue(1) };
16778 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16779 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16780 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16784 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16785 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16786 MVT::i32, cpOut.getValue(2));
16787 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16788 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16790 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16791 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16792 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16796 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16797 SelectionDAG &DAG) {
16798 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16799 MVT DstVT = Op.getSimpleValueType();
16801 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16802 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16803 if (DstVT != MVT::f64)
16804 // This conversion needs to be expanded.
16807 SDValue InVec = Op->getOperand(0);
16809 unsigned NumElts = SrcVT.getVectorNumElements();
16810 EVT SVT = SrcVT.getVectorElementType();
16812 // Widen the vector in input in the case of MVT::v2i32.
16813 // Example: from MVT::v2i32 to MVT::v4i32.
16814 SmallVector<SDValue, 16> Elts;
16815 for (unsigned i = 0, e = NumElts; i != e; ++i)
16816 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16817 DAG.getIntPtrConstant(i)));
16819 // Explicitly mark the extra elements as Undef.
16820 SDValue Undef = DAG.getUNDEF(SVT);
16821 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
16822 Elts.push_back(Undef);
16824 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16825 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16826 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16827 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16828 DAG.getIntPtrConstant(0));
16831 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16832 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16833 assert((DstVT == MVT::i64 ||
16834 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16835 "Unexpected custom BITCAST");
16836 // i64 <=> MMX conversions are Legal.
16837 if (SrcVT==MVT::i64 && DstVT.isVector())
16839 if (DstVT==MVT::i64 && SrcVT.isVector())
16841 // MMX <=> MMX conversions are Legal.
16842 if (SrcVT.isVector() && DstVT.isVector())
16844 // All other conversions need to be expanded.
16848 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16849 SDNode *Node = Op.getNode();
16851 EVT T = Node->getValueType(0);
16852 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16853 DAG.getConstant(0, T), Node->getOperand(2));
16854 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16855 cast<AtomicSDNode>(Node)->getMemoryVT(),
16856 Node->getOperand(0),
16857 Node->getOperand(1), negOp,
16858 cast<AtomicSDNode>(Node)->getMemOperand(),
16859 cast<AtomicSDNode>(Node)->getOrdering(),
16860 cast<AtomicSDNode>(Node)->getSynchScope());
16863 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16864 SDNode *Node = Op.getNode();
16866 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16868 // Convert seq_cst store -> xchg
16869 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16870 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16871 // (The only way to get a 16-byte store is cmpxchg16b)
16872 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16873 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16874 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16875 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16876 cast<AtomicSDNode>(Node)->getMemoryVT(),
16877 Node->getOperand(0),
16878 Node->getOperand(1), Node->getOperand(2),
16879 cast<AtomicSDNode>(Node)->getMemOperand(),
16880 cast<AtomicSDNode>(Node)->getOrdering(),
16881 cast<AtomicSDNode>(Node)->getSynchScope());
16882 return Swap.getValue(1);
16884 // Other atomic stores have a simple pattern.
16888 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
16889 EVT VT = Op.getNode()->getSimpleValueType(0);
16891 // Let legalize expand this if it isn't a legal type yet.
16892 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16895 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16898 bool ExtraOp = false;
16899 switch (Op.getOpcode()) {
16900 default: llvm_unreachable("Invalid code");
16901 case ISD::ADDC: Opc = X86ISD::ADD; break;
16902 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16903 case ISD::SUBC: Opc = X86ISD::SUB; break;
16904 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
16908 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16910 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16911 Op.getOperand(1), Op.getOperand(2));
16914 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
16915 SelectionDAG &DAG) {
16916 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
16918 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
16919 // which returns the values as { float, float } (in XMM0) or
16920 // { double, double } (which is returned in XMM0, XMM1).
16922 SDValue Arg = Op.getOperand(0);
16923 EVT ArgVT = Arg.getValueType();
16924 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16926 TargetLowering::ArgListTy Args;
16927 TargetLowering::ArgListEntry Entry;
16931 Entry.isSExt = false;
16932 Entry.isZExt = false;
16933 Args.push_back(Entry);
16935 bool isF64 = ArgVT == MVT::f64;
16936 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
16937 // the small struct {f32, f32} is returned in (eax, edx). For f64,
16938 // the results are returned via SRet in memory.
16939 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
16940 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16941 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
16943 Type *RetTy = isF64
16944 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
16945 : (Type*)VectorType::get(ArgTy, 4);
16947 TargetLowering::CallLoweringInfo CLI(DAG);
16948 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
16949 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
16951 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
16954 // Returned in xmm0 and xmm1.
16955 return CallResult.first;
16957 // Returned in bits 0:31 and 32:64 xmm0.
16958 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16959 CallResult.first, DAG.getIntPtrConstant(0));
16960 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16961 CallResult.first, DAG.getIntPtrConstant(1));
16962 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
16963 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
16966 /// LowerOperation - Provide custom lowering hooks for some operations.
16968 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
16969 switch (Op.getOpcode()) {
16970 default: llvm_unreachable("Should not custom lower this!");
16971 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
16972 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
16973 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
16974 return LowerCMP_SWAP(Op, Subtarget, DAG);
16975 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
16976 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
16977 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16978 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
16979 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
16980 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
16981 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
16982 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
16983 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
16984 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
16985 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
16986 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
16987 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
16988 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
16989 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
16990 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
16991 case ISD::SHL_PARTS:
16992 case ISD::SRA_PARTS:
16993 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
16994 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
16995 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
16996 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
16997 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
16998 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
16999 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17000 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17001 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17002 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17003 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17004 case ISD::FABS: return LowerFABS(Op, DAG);
17005 case ISD::FNEG: return LowerFNEG(Op, DAG);
17006 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17007 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17008 case ISD::SETCC: return LowerSETCC(Op, DAG);
17009 case ISD::SELECT: return LowerSELECT(Op, DAG);
17010 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17011 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17012 case ISD::VASTART: return LowerVASTART(Op, DAG);
17013 case ISD::VAARG: return LowerVAARG(Op, DAG);
17014 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17015 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17016 case ISD::INTRINSIC_VOID:
17017 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17018 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17019 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17020 case ISD::FRAME_TO_ARGS_OFFSET:
17021 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17022 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17023 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17024 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17025 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17026 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17027 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17028 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17029 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17030 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17031 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17032 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17033 case ISD::UMUL_LOHI:
17034 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17037 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17043 case ISD::UMULO: return LowerXALUO(Op, DAG);
17044 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17045 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17049 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17050 case ISD::ADD: return LowerADD(Op, DAG);
17051 case ISD::SUB: return LowerSUB(Op, DAG);
17052 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17056 static void ReplaceATOMIC_LOAD(SDNode *Node,
17057 SmallVectorImpl<SDValue> &Results,
17058 SelectionDAG &DAG) {
17060 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17062 // Convert wide load -> cmpxchg8b/cmpxchg16b
17063 // FIXME: On 32-bit, load -> fild or movq would be more efficient
17064 // (The only way to get a 16-byte load is cmpxchg16b)
17065 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
17066 SDValue Zero = DAG.getConstant(0, VT);
17067 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
17069 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
17070 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
17071 cast<AtomicSDNode>(Node)->getMemOperand(),
17072 cast<AtomicSDNode>(Node)->getOrdering(),
17073 cast<AtomicSDNode>(Node)->getOrdering(),
17074 cast<AtomicSDNode>(Node)->getSynchScope());
17075 Results.push_back(Swap.getValue(0));
17076 Results.push_back(Swap.getValue(2));
17079 /// ReplaceNodeResults - Replace a node with an illegal result type
17080 /// with a new node built out of custom code.
17081 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17082 SmallVectorImpl<SDValue>&Results,
17083 SelectionDAG &DAG) const {
17085 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17086 switch (N->getOpcode()) {
17088 llvm_unreachable("Do not know how to custom type legalize this operation!");
17089 case ISD::SIGN_EXTEND_INREG:
17094 // We don't want to expand or promote these.
17101 case ISD::UDIVREM: {
17102 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17103 Results.push_back(V);
17106 case ISD::FP_TO_SINT:
17107 case ISD::FP_TO_UINT: {
17108 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17110 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17113 std::pair<SDValue,SDValue> Vals =
17114 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17115 SDValue FIST = Vals.first, StackSlot = Vals.second;
17116 if (FIST.getNode()) {
17117 EVT VT = N->getValueType(0);
17118 // Return a load from the stack slot.
17119 if (StackSlot.getNode())
17120 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17121 MachinePointerInfo(),
17122 false, false, false, 0));
17124 Results.push_back(FIST);
17128 case ISD::UINT_TO_FP: {
17129 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17130 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17131 N->getValueType(0) != MVT::v2f32)
17133 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17135 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17137 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17138 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17139 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17140 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17141 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17142 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17145 case ISD::FP_ROUND: {
17146 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17148 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17149 Results.push_back(V);
17152 case ISD::INTRINSIC_W_CHAIN: {
17153 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17155 default : llvm_unreachable("Do not know how to custom type "
17156 "legalize this intrinsic operation!");
17157 case Intrinsic::x86_rdtsc:
17158 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17160 case Intrinsic::x86_rdtscp:
17161 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17163 case Intrinsic::x86_rdpmc:
17164 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17167 case ISD::READCYCLECOUNTER: {
17168 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17171 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17172 EVT T = N->getValueType(0);
17173 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17174 bool Regs64bit = T == MVT::i128;
17175 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17176 SDValue cpInL, cpInH;
17177 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17178 DAG.getConstant(0, HalfT));
17179 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17180 DAG.getConstant(1, HalfT));
17181 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17182 Regs64bit ? X86::RAX : X86::EAX,
17184 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17185 Regs64bit ? X86::RDX : X86::EDX,
17186 cpInH, cpInL.getValue(1));
17187 SDValue swapInL, swapInH;
17188 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17189 DAG.getConstant(0, HalfT));
17190 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17191 DAG.getConstant(1, HalfT));
17192 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17193 Regs64bit ? X86::RBX : X86::EBX,
17194 swapInL, cpInH.getValue(1));
17195 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17196 Regs64bit ? X86::RCX : X86::ECX,
17197 swapInH, swapInL.getValue(1));
17198 SDValue Ops[] = { swapInH.getValue(0),
17200 swapInH.getValue(1) };
17201 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17202 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17203 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17204 X86ISD::LCMPXCHG8_DAG;
17205 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17206 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17207 Regs64bit ? X86::RAX : X86::EAX,
17208 HalfT, Result.getValue(1));
17209 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17210 Regs64bit ? X86::RDX : X86::EDX,
17211 HalfT, cpOutL.getValue(2));
17212 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17214 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17215 MVT::i32, cpOutH.getValue(2));
17217 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17218 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17219 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17221 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17222 Results.push_back(Success);
17223 Results.push_back(EFLAGS.getValue(1));
17226 case ISD::ATOMIC_SWAP:
17227 case ISD::ATOMIC_LOAD_ADD:
17228 case ISD::ATOMIC_LOAD_SUB:
17229 case ISD::ATOMIC_LOAD_AND:
17230 case ISD::ATOMIC_LOAD_OR:
17231 case ISD::ATOMIC_LOAD_XOR:
17232 case ISD::ATOMIC_LOAD_NAND:
17233 case ISD::ATOMIC_LOAD_MIN:
17234 case ISD::ATOMIC_LOAD_MAX:
17235 case ISD::ATOMIC_LOAD_UMIN:
17236 case ISD::ATOMIC_LOAD_UMAX:
17237 // Delegate to generic TypeLegalization. Situations we can really handle
17238 // should have already been dealt with by X86AtomicExpandPass.cpp.
17240 case ISD::ATOMIC_LOAD: {
17241 ReplaceATOMIC_LOAD(N, Results, DAG);
17244 case ISD::BITCAST: {
17245 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17246 EVT DstVT = N->getValueType(0);
17247 EVT SrcVT = N->getOperand(0)->getValueType(0);
17249 if (SrcVT != MVT::f64 ||
17250 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17253 unsigned NumElts = DstVT.getVectorNumElements();
17254 EVT SVT = DstVT.getVectorElementType();
17255 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17256 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17257 MVT::v2f64, N->getOperand(0));
17258 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17260 if (ExperimentalVectorWideningLegalization) {
17261 // If we are legalizing vectors by widening, we already have the desired
17262 // legal vector type, just return it.
17263 Results.push_back(ToVecInt);
17267 SmallVector<SDValue, 8> Elts;
17268 for (unsigned i = 0, e = NumElts; i != e; ++i)
17269 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17270 ToVecInt, DAG.getIntPtrConstant(i)));
17272 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17277 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17279 default: return nullptr;
17280 case X86ISD::BSF: return "X86ISD::BSF";
17281 case X86ISD::BSR: return "X86ISD::BSR";
17282 case X86ISD::SHLD: return "X86ISD::SHLD";
17283 case X86ISD::SHRD: return "X86ISD::SHRD";
17284 case X86ISD::FAND: return "X86ISD::FAND";
17285 case X86ISD::FANDN: return "X86ISD::FANDN";
17286 case X86ISD::FOR: return "X86ISD::FOR";
17287 case X86ISD::FXOR: return "X86ISD::FXOR";
17288 case X86ISD::FSRL: return "X86ISD::FSRL";
17289 case X86ISD::FILD: return "X86ISD::FILD";
17290 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17291 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17292 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17293 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17294 case X86ISD::FLD: return "X86ISD::FLD";
17295 case X86ISD::FST: return "X86ISD::FST";
17296 case X86ISD::CALL: return "X86ISD::CALL";
17297 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17298 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17299 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17300 case X86ISD::BT: return "X86ISD::BT";
17301 case X86ISD::CMP: return "X86ISD::CMP";
17302 case X86ISD::COMI: return "X86ISD::COMI";
17303 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17304 case X86ISD::CMPM: return "X86ISD::CMPM";
17305 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17306 case X86ISD::SETCC: return "X86ISD::SETCC";
17307 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17308 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17309 case X86ISD::CMOV: return "X86ISD::CMOV";
17310 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17311 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17312 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17313 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17314 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17315 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17316 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17317 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17318 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17319 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17320 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17321 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17322 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17323 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17324 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17325 case X86ISD::BLENDV: return "X86ISD::BLENDV";
17326 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17327 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17328 case X86ISD::HADD: return "X86ISD::HADD";
17329 case X86ISD::HSUB: return "X86ISD::HSUB";
17330 case X86ISD::FHADD: return "X86ISD::FHADD";
17331 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17332 case X86ISD::UMAX: return "X86ISD::UMAX";
17333 case X86ISD::UMIN: return "X86ISD::UMIN";
17334 case X86ISD::SMAX: return "X86ISD::SMAX";
17335 case X86ISD::SMIN: return "X86ISD::SMIN";
17336 case X86ISD::FMAX: return "X86ISD::FMAX";
17337 case X86ISD::FMIN: return "X86ISD::FMIN";
17338 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17339 case X86ISD::FMINC: return "X86ISD::FMINC";
17340 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17341 case X86ISD::FRCP: return "X86ISD::FRCP";
17342 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17343 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17344 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17345 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17346 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17347 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17348 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17349 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17350 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17351 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17352 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17353 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17354 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17355 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17356 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17357 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17358 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17359 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17360 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17361 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17362 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17363 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17364 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17365 case X86ISD::VSHL: return "X86ISD::VSHL";
17366 case X86ISD::VSRL: return "X86ISD::VSRL";
17367 case X86ISD::VSRA: return "X86ISD::VSRA";
17368 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17369 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17370 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17371 case X86ISD::CMPP: return "X86ISD::CMPP";
17372 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17373 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17374 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17375 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17376 case X86ISD::ADD: return "X86ISD::ADD";
17377 case X86ISD::SUB: return "X86ISD::SUB";
17378 case X86ISD::ADC: return "X86ISD::ADC";
17379 case X86ISD::SBB: return "X86ISD::SBB";
17380 case X86ISD::SMUL: return "X86ISD::SMUL";
17381 case X86ISD::UMUL: return "X86ISD::UMUL";
17382 case X86ISD::INC: return "X86ISD::INC";
17383 case X86ISD::DEC: return "X86ISD::DEC";
17384 case X86ISD::OR: return "X86ISD::OR";
17385 case X86ISD::XOR: return "X86ISD::XOR";
17386 case X86ISD::AND: return "X86ISD::AND";
17387 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17388 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17389 case X86ISD::PTEST: return "X86ISD::PTEST";
17390 case X86ISD::TESTP: return "X86ISD::TESTP";
17391 case X86ISD::TESTM: return "X86ISD::TESTM";
17392 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17393 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17394 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17395 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17396 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17397 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17398 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17399 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17400 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17401 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17402 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17403 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17404 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17405 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17406 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17407 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17408 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17409 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17410 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17411 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17412 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17413 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17414 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17415 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17416 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17417 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
17418 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17419 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17420 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17421 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17422 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17423 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17424 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17425 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17426 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17427 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17428 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17429 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17430 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17431 case X86ISD::SAHF: return "X86ISD::SAHF";
17432 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17433 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17434 case X86ISD::FMADD: return "X86ISD::FMADD";
17435 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17436 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17437 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17438 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17439 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17440 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17441 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17442 case X86ISD::XTEST: return "X86ISD::XTEST";
17446 // isLegalAddressingMode - Return true if the addressing mode represented
17447 // by AM is legal for this target, for a load/store of the specified type.
17448 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17450 // X86 supports extremely general addressing modes.
17451 CodeModel::Model M = getTargetMachine().getCodeModel();
17452 Reloc::Model R = getTargetMachine().getRelocationModel();
17454 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17455 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17460 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17462 // If a reference to this global requires an extra load, we can't fold it.
17463 if (isGlobalStubReference(GVFlags))
17466 // If BaseGV requires a register for the PIC base, we cannot also have a
17467 // BaseReg specified.
17468 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17471 // If lower 4G is not available, then we must use rip-relative addressing.
17472 if ((M != CodeModel::Small || R != Reloc::Static) &&
17473 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17477 switch (AM.Scale) {
17483 // These scales always work.
17488 // These scales are formed with basereg+scalereg. Only accept if there is
17493 default: // Other stuff never works.
17500 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17501 unsigned Bits = Ty->getScalarSizeInBits();
17503 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17504 // particularly cheaper than those without.
17508 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17509 // variable shifts just as cheap as scalar ones.
17510 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17513 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17514 // fully general vector.
17518 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17519 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17521 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17522 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17523 return NumBits1 > NumBits2;
17526 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17527 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17530 if (!isTypeLegal(EVT::getEVT(Ty1)))
17533 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17535 // Assuming the caller doesn't have a zeroext or signext return parameter,
17536 // truncation all the way down to i1 is valid.
17540 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17541 return isInt<32>(Imm);
17544 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17545 // Can also use sub to handle negated immediates.
17546 return isInt<32>(Imm);
17549 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17550 if (!VT1.isInteger() || !VT2.isInteger())
17552 unsigned NumBits1 = VT1.getSizeInBits();
17553 unsigned NumBits2 = VT2.getSizeInBits();
17554 return NumBits1 > NumBits2;
17557 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17558 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17559 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17562 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17563 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17564 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17567 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17568 EVT VT1 = Val.getValueType();
17569 if (isZExtFree(VT1, VT2))
17572 if (Val.getOpcode() != ISD::LOAD)
17575 if (!VT1.isSimple() || !VT1.isInteger() ||
17576 !VT2.isSimple() || !VT2.isInteger())
17579 switch (VT1.getSimpleVT().SimpleTy) {
17584 // X86 has 8, 16, and 32-bit zero-extending loads.
17592 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17593 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17596 VT = VT.getScalarType();
17598 if (!VT.isSimple())
17601 switch (VT.getSimpleVT().SimpleTy) {
17612 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17613 // i16 instructions are longer (0x66 prefix) and potentially slower.
17614 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17617 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17618 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17619 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17620 /// are assumed to be legal.
17622 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17624 if (!VT.isSimple())
17627 MVT SVT = VT.getSimpleVT();
17629 // Very little shuffling can be done for 64-bit vectors right now.
17630 if (VT.getSizeInBits() == 64)
17633 // If this is a single-input shuffle with no 128 bit lane crossings we can
17634 // lower it into pshufb.
17635 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
17636 (SVT.is256BitVector() && Subtarget->hasInt256())) {
17637 bool isLegal = true;
17638 for (unsigned I = 0, E = M.size(); I != E; ++I) {
17639 if (M[I] >= (int)SVT.getVectorNumElements() ||
17640 ShuffleCrosses128bitLane(SVT, I, M[I])) {
17649 // FIXME: blends, shifts.
17650 return (SVT.getVectorNumElements() == 2 ||
17651 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
17652 isMOVLMask(M, SVT) ||
17653 isMOVHLPSMask(M, SVT) ||
17654 isSHUFPMask(M, SVT) ||
17655 isPSHUFDMask(M, SVT) ||
17656 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
17657 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
17658 isPALIGNRMask(M, SVT, Subtarget) ||
17659 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
17660 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
17661 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17662 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17663 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
17667 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17669 if (!VT.isSimple())
17672 MVT SVT = VT.getSimpleVT();
17673 unsigned NumElts = SVT.getVectorNumElements();
17674 // FIXME: This collection of masks seems suspect.
17677 if (NumElts == 4 && SVT.is128BitVector()) {
17678 return (isMOVLMask(Mask, SVT) ||
17679 isCommutedMOVLMask(Mask, SVT, true) ||
17680 isSHUFPMask(Mask, SVT) ||
17681 isSHUFPMask(Mask, SVT, /* Commuted */ true));
17686 //===----------------------------------------------------------------------===//
17687 // X86 Scheduler Hooks
17688 //===----------------------------------------------------------------------===//
17690 /// Utility function to emit xbegin specifying the start of an RTM region.
17691 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17692 const TargetInstrInfo *TII) {
17693 DebugLoc DL = MI->getDebugLoc();
17695 const BasicBlock *BB = MBB->getBasicBlock();
17696 MachineFunction::iterator I = MBB;
17699 // For the v = xbegin(), we generate
17710 MachineBasicBlock *thisMBB = MBB;
17711 MachineFunction *MF = MBB->getParent();
17712 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17713 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17714 MF->insert(I, mainMBB);
17715 MF->insert(I, sinkMBB);
17717 // Transfer the remainder of BB and its successor edges to sinkMBB.
17718 sinkMBB->splice(sinkMBB->begin(), MBB,
17719 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17720 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17724 // # fallthrough to mainMBB
17725 // # abortion to sinkMBB
17726 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17727 thisMBB->addSuccessor(mainMBB);
17728 thisMBB->addSuccessor(sinkMBB);
17732 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17733 mainMBB->addSuccessor(sinkMBB);
17736 // EAX is live into the sinkMBB
17737 sinkMBB->addLiveIn(X86::EAX);
17738 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17739 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17742 MI->eraseFromParent();
17746 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17747 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17748 // in the .td file.
17749 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17750 const TargetInstrInfo *TII) {
17752 switch (MI->getOpcode()) {
17753 default: llvm_unreachable("illegal opcode!");
17754 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17755 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17756 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17757 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17758 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17759 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17760 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17761 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17764 DebugLoc dl = MI->getDebugLoc();
17765 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17767 unsigned NumArgs = MI->getNumOperands();
17768 for (unsigned i = 1; i < NumArgs; ++i) {
17769 MachineOperand &Op = MI->getOperand(i);
17770 if (!(Op.isReg() && Op.isImplicit()))
17771 MIB.addOperand(Op);
17773 if (MI->hasOneMemOperand())
17774 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17776 BuildMI(*BB, MI, dl,
17777 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17778 .addReg(X86::XMM0);
17780 MI->eraseFromParent();
17784 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17785 // defs in an instruction pattern
17786 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17787 const TargetInstrInfo *TII) {
17789 switch (MI->getOpcode()) {
17790 default: llvm_unreachable("illegal opcode!");
17791 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17792 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17793 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17794 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17795 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17796 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17797 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17798 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17801 DebugLoc dl = MI->getDebugLoc();
17802 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17804 unsigned NumArgs = MI->getNumOperands(); // remove the results
17805 for (unsigned i = 1; i < NumArgs; ++i) {
17806 MachineOperand &Op = MI->getOperand(i);
17807 if (!(Op.isReg() && Op.isImplicit()))
17808 MIB.addOperand(Op);
17810 if (MI->hasOneMemOperand())
17811 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17813 BuildMI(*BB, MI, dl,
17814 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17817 MI->eraseFromParent();
17821 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17822 const TargetInstrInfo *TII,
17823 const X86Subtarget* Subtarget) {
17824 DebugLoc dl = MI->getDebugLoc();
17826 // Address into RAX/EAX, other two args into ECX, EDX.
17827 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17828 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17829 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
17830 for (int i = 0; i < X86::AddrNumOperands; ++i)
17831 MIB.addOperand(MI->getOperand(i));
17833 unsigned ValOps = X86::AddrNumOperands;
17834 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
17835 .addReg(MI->getOperand(ValOps).getReg());
17836 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
17837 .addReg(MI->getOperand(ValOps+1).getReg());
17839 // The instruction doesn't actually take any operands though.
17840 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
17842 MI->eraseFromParent(); // The pseudo is gone now.
17846 MachineBasicBlock *
17847 X86TargetLowering::EmitVAARG64WithCustomInserter(
17849 MachineBasicBlock *MBB) const {
17850 // Emit va_arg instruction on X86-64.
17852 // Operands to this pseudo-instruction:
17853 // 0 ) Output : destination address (reg)
17854 // 1-5) Input : va_list address (addr, i64mem)
17855 // 6 ) ArgSize : Size (in bytes) of vararg type
17856 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17857 // 8 ) Align : Alignment of type
17858 // 9 ) EFLAGS (implicit-def)
17860 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17861 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17863 unsigned DestReg = MI->getOperand(0).getReg();
17864 MachineOperand &Base = MI->getOperand(1);
17865 MachineOperand &Scale = MI->getOperand(2);
17866 MachineOperand &Index = MI->getOperand(3);
17867 MachineOperand &Disp = MI->getOperand(4);
17868 MachineOperand &Segment = MI->getOperand(5);
17869 unsigned ArgSize = MI->getOperand(6).getImm();
17870 unsigned ArgMode = MI->getOperand(7).getImm();
17871 unsigned Align = MI->getOperand(8).getImm();
17873 // Memory Reference
17874 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17875 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17876 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17878 // Machine Information
17879 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
17880 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17881 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17882 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17883 DebugLoc DL = MI->getDebugLoc();
17885 // struct va_list {
17888 // i64 overflow_area (address)
17889 // i64 reg_save_area (address)
17891 // sizeof(va_list) = 24
17892 // alignment(va_list) = 8
17894 unsigned TotalNumIntRegs = 6;
17895 unsigned TotalNumXMMRegs = 8;
17896 bool UseGPOffset = (ArgMode == 1);
17897 bool UseFPOffset = (ArgMode == 2);
17898 unsigned MaxOffset = TotalNumIntRegs * 8 +
17899 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17901 /* Align ArgSize to a multiple of 8 */
17902 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17903 bool NeedsAlign = (Align > 8);
17905 MachineBasicBlock *thisMBB = MBB;
17906 MachineBasicBlock *overflowMBB;
17907 MachineBasicBlock *offsetMBB;
17908 MachineBasicBlock *endMBB;
17910 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17911 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17912 unsigned OffsetReg = 0;
17914 if (!UseGPOffset && !UseFPOffset) {
17915 // If we only pull from the overflow region, we don't create a branch.
17916 // We don't need to alter control flow.
17917 OffsetDestReg = 0; // unused
17918 OverflowDestReg = DestReg;
17920 offsetMBB = nullptr;
17921 overflowMBB = thisMBB;
17924 // First emit code to check if gp_offset (or fp_offset) is below the bound.
17925 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17926 // If not, pull from overflow_area. (branch to overflowMBB)
17931 // offsetMBB overflowMBB
17936 // Registers for the PHI in endMBB
17937 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17938 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17940 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17941 MachineFunction *MF = MBB->getParent();
17942 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17943 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17944 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17946 MachineFunction::iterator MBBIter = MBB;
17949 // Insert the new basic blocks
17950 MF->insert(MBBIter, offsetMBB);
17951 MF->insert(MBBIter, overflowMBB);
17952 MF->insert(MBBIter, endMBB);
17954 // Transfer the remainder of MBB and its successor edges to endMBB.
17955 endMBB->splice(endMBB->begin(), thisMBB,
17956 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
17957 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
17959 // Make offsetMBB and overflowMBB successors of thisMBB
17960 thisMBB->addSuccessor(offsetMBB);
17961 thisMBB->addSuccessor(overflowMBB);
17963 // endMBB is a successor of both offsetMBB and overflowMBB
17964 offsetMBB->addSuccessor(endMBB);
17965 overflowMBB->addSuccessor(endMBB);
17967 // Load the offset value into a register
17968 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17969 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
17973 .addDisp(Disp, UseFPOffset ? 4 : 0)
17974 .addOperand(Segment)
17975 .setMemRefs(MMOBegin, MMOEnd);
17977 // Check if there is enough room left to pull this argument.
17978 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
17980 .addImm(MaxOffset + 8 - ArgSizeA8);
17982 // Branch to "overflowMBB" if offset >= max
17983 // Fall through to "offsetMBB" otherwise
17984 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
17985 .addMBB(overflowMBB);
17988 // In offsetMBB, emit code to use the reg_save_area.
17990 assert(OffsetReg != 0);
17992 // Read the reg_save_area address.
17993 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
17994 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
17999 .addOperand(Segment)
18000 .setMemRefs(MMOBegin, MMOEnd);
18002 // Zero-extend the offset
18003 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18004 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18007 .addImm(X86::sub_32bit);
18009 // Add the offset to the reg_save_area to get the final address.
18010 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18011 .addReg(OffsetReg64)
18012 .addReg(RegSaveReg);
18014 // Compute the offset for the next argument
18015 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18016 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18018 .addImm(UseFPOffset ? 16 : 8);
18020 // Store it back into the va_list.
18021 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18025 .addDisp(Disp, UseFPOffset ? 4 : 0)
18026 .addOperand(Segment)
18027 .addReg(NextOffsetReg)
18028 .setMemRefs(MMOBegin, MMOEnd);
18031 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18036 // Emit code to use overflow area
18039 // Load the overflow_area address into a register.
18040 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18041 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18046 .addOperand(Segment)
18047 .setMemRefs(MMOBegin, MMOEnd);
18049 // If we need to align it, do so. Otherwise, just copy the address
18050 // to OverflowDestReg.
18052 // Align the overflow address
18053 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18054 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18056 // aligned_addr = (addr + (align-1)) & ~(align-1)
18057 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18058 .addReg(OverflowAddrReg)
18061 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18063 .addImm(~(uint64_t)(Align-1));
18065 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18066 .addReg(OverflowAddrReg);
18069 // Compute the next overflow address after this argument.
18070 // (the overflow address should be kept 8-byte aligned)
18071 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18072 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18073 .addReg(OverflowDestReg)
18074 .addImm(ArgSizeA8);
18076 // Store the new overflow address.
18077 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18082 .addOperand(Segment)
18083 .addReg(NextAddrReg)
18084 .setMemRefs(MMOBegin, MMOEnd);
18086 // If we branched, emit the PHI to the front of endMBB.
18088 BuildMI(*endMBB, endMBB->begin(), DL,
18089 TII->get(X86::PHI), DestReg)
18090 .addReg(OffsetDestReg).addMBB(offsetMBB)
18091 .addReg(OverflowDestReg).addMBB(overflowMBB);
18094 // Erase the pseudo instruction
18095 MI->eraseFromParent();
18100 MachineBasicBlock *
18101 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18103 MachineBasicBlock *MBB) const {
18104 // Emit code to save XMM registers to the stack. The ABI says that the
18105 // number of registers to save is given in %al, so it's theoretically
18106 // possible to do an indirect jump trick to avoid saving all of them,
18107 // however this code takes a simpler approach and just executes all
18108 // of the stores if %al is non-zero. It's less code, and it's probably
18109 // easier on the hardware branch predictor, and stores aren't all that
18110 // expensive anyway.
18112 // Create the new basic blocks. One block contains all the XMM stores,
18113 // and one block is the final destination regardless of whether any
18114 // stores were performed.
18115 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18116 MachineFunction *F = MBB->getParent();
18117 MachineFunction::iterator MBBIter = MBB;
18119 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18120 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18121 F->insert(MBBIter, XMMSaveMBB);
18122 F->insert(MBBIter, EndMBB);
18124 // Transfer the remainder of MBB and its successor edges to EndMBB.
18125 EndMBB->splice(EndMBB->begin(), MBB,
18126 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18127 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18129 // The original block will now fall through to the XMM save block.
18130 MBB->addSuccessor(XMMSaveMBB);
18131 // The XMMSaveMBB will fall through to the end block.
18132 XMMSaveMBB->addSuccessor(EndMBB);
18134 // Now add the instructions.
18135 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18136 DebugLoc DL = MI->getDebugLoc();
18138 unsigned CountReg = MI->getOperand(0).getReg();
18139 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18140 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18142 if (!Subtarget->isTargetWin64()) {
18143 // If %al is 0, branch around the XMM save block.
18144 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18145 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18146 MBB->addSuccessor(EndMBB);
18149 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18150 // that was just emitted, but clearly shouldn't be "saved".
18151 assert((MI->getNumOperands() <= 3 ||
18152 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18153 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18154 && "Expected last argument to be EFLAGS");
18155 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18156 // In the XMM save block, save all the XMM argument registers.
18157 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18158 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18159 MachineMemOperand *MMO =
18160 F->getMachineMemOperand(
18161 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18162 MachineMemOperand::MOStore,
18163 /*Size=*/16, /*Align=*/16);
18164 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18165 .addFrameIndex(RegSaveFrameIndex)
18166 .addImm(/*Scale=*/1)
18167 .addReg(/*IndexReg=*/0)
18168 .addImm(/*Disp=*/Offset)
18169 .addReg(/*Segment=*/0)
18170 .addReg(MI->getOperand(i).getReg())
18171 .addMemOperand(MMO);
18174 MI->eraseFromParent(); // The pseudo instruction is gone now.
18179 // The EFLAGS operand of SelectItr might be missing a kill marker
18180 // because there were multiple uses of EFLAGS, and ISel didn't know
18181 // which to mark. Figure out whether SelectItr should have had a
18182 // kill marker, and set it if it should. Returns the correct kill
18184 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18185 MachineBasicBlock* BB,
18186 const TargetRegisterInfo* TRI) {
18187 // Scan forward through BB for a use/def of EFLAGS.
18188 MachineBasicBlock::iterator miI(std::next(SelectItr));
18189 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18190 const MachineInstr& mi = *miI;
18191 if (mi.readsRegister(X86::EFLAGS))
18193 if (mi.definesRegister(X86::EFLAGS))
18194 break; // Should have kill-flag - update below.
18197 // If we hit the end of the block, check whether EFLAGS is live into a
18199 if (miI == BB->end()) {
18200 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18201 sEnd = BB->succ_end();
18202 sItr != sEnd; ++sItr) {
18203 MachineBasicBlock* succ = *sItr;
18204 if (succ->isLiveIn(X86::EFLAGS))
18209 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18210 // out. SelectMI should have a kill flag on EFLAGS.
18211 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18215 MachineBasicBlock *
18216 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18217 MachineBasicBlock *BB) const {
18218 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18219 DebugLoc DL = MI->getDebugLoc();
18221 // To "insert" a SELECT_CC instruction, we actually have to insert the
18222 // diamond control-flow pattern. The incoming instruction knows the
18223 // destination vreg to set, the condition code register to branch on, the
18224 // true/false values to select between, and a branch opcode to use.
18225 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18226 MachineFunction::iterator It = BB;
18232 // cmpTY ccX, r1, r2
18234 // fallthrough --> copy0MBB
18235 MachineBasicBlock *thisMBB = BB;
18236 MachineFunction *F = BB->getParent();
18237 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18238 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18239 F->insert(It, copy0MBB);
18240 F->insert(It, sinkMBB);
18242 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18243 // live into the sink and copy blocks.
18244 const TargetRegisterInfo *TRI =
18245 BB->getParent()->getSubtarget().getRegisterInfo();
18246 if (!MI->killsRegister(X86::EFLAGS) &&
18247 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
18248 copy0MBB->addLiveIn(X86::EFLAGS);
18249 sinkMBB->addLiveIn(X86::EFLAGS);
18252 // Transfer the remainder of BB and its successor edges to sinkMBB.
18253 sinkMBB->splice(sinkMBB->begin(), BB,
18254 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18255 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18257 // Add the true and fallthrough blocks as its successors.
18258 BB->addSuccessor(copy0MBB);
18259 BB->addSuccessor(sinkMBB);
18261 // Create the conditional branch instruction.
18263 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18264 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18267 // %FalseValue = ...
18268 // # fallthrough to sinkMBB
18269 copy0MBB->addSuccessor(sinkMBB);
18272 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18274 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18275 TII->get(X86::PHI), MI->getOperand(0).getReg())
18276 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18277 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18279 MI->eraseFromParent(); // The pseudo instruction is gone now.
18283 MachineBasicBlock *
18284 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
18285 bool Is64Bit) const {
18286 MachineFunction *MF = BB->getParent();
18287 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18288 DebugLoc DL = MI->getDebugLoc();
18289 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18291 assert(MF->shouldSplitStack());
18293 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18294 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
18297 // ... [Till the alloca]
18298 // If stacklet is not large enough, jump to mallocMBB
18301 // Allocate by subtracting from RSP
18302 // Jump to continueMBB
18305 // Allocate by call to runtime
18309 // [rest of original BB]
18312 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18313 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18314 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18316 MachineRegisterInfo &MRI = MF->getRegInfo();
18317 const TargetRegisterClass *AddrRegClass =
18318 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
18320 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18321 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18322 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18323 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18324 sizeVReg = MI->getOperand(1).getReg(),
18325 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
18327 MachineFunction::iterator MBBIter = BB;
18330 MF->insert(MBBIter, bumpMBB);
18331 MF->insert(MBBIter, mallocMBB);
18332 MF->insert(MBBIter, continueMBB);
18334 continueMBB->splice(continueMBB->begin(), BB,
18335 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18336 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18338 // Add code to the main basic block to check if the stack limit has been hit,
18339 // and if so, jump to mallocMBB otherwise to bumpMBB.
18340 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18341 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18342 .addReg(tmpSPVReg).addReg(sizeVReg);
18343 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
18344 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18345 .addReg(SPLimitVReg);
18346 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
18348 // bumpMBB simply decreases the stack pointer, since we know the current
18349 // stacklet has enough space.
18350 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18351 .addReg(SPLimitVReg);
18352 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18353 .addReg(SPLimitVReg);
18354 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18356 // Calls into a routine in libgcc to allocate more space from the heap.
18357 const uint32_t *RegMask = MF->getTarget()
18358 .getSubtargetImpl()
18359 ->getRegisterInfo()
18360 ->getCallPreservedMask(CallingConv::C);
18362 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18364 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18365 .addExternalSymbol("__morestack_allocate_stack_space")
18366 .addRegMask(RegMask)
18367 .addReg(X86::RDI, RegState::Implicit)
18368 .addReg(X86::RAX, RegState::ImplicitDefine);
18370 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18372 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18373 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18374 .addExternalSymbol("__morestack_allocate_stack_space")
18375 .addRegMask(RegMask)
18376 .addReg(X86::EAX, RegState::ImplicitDefine);
18380 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18383 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18384 .addReg(Is64Bit ? X86::RAX : X86::EAX);
18385 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18387 // Set up the CFG correctly.
18388 BB->addSuccessor(bumpMBB);
18389 BB->addSuccessor(mallocMBB);
18390 mallocMBB->addSuccessor(continueMBB);
18391 bumpMBB->addSuccessor(continueMBB);
18393 // Take care of the PHI nodes.
18394 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18395 MI->getOperand(0).getReg())
18396 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18397 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18399 // Delete the original pseudo instruction.
18400 MI->eraseFromParent();
18403 return continueMBB;
18406 MachineBasicBlock *
18407 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18408 MachineBasicBlock *BB) const {
18409 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18410 DebugLoc DL = MI->getDebugLoc();
18412 assert(!Subtarget->isTargetMacho());
18414 // The lowering is pretty easy: we're just emitting the call to _alloca. The
18415 // non-trivial part is impdef of ESP.
18417 if (Subtarget->isTargetWin64()) {
18418 if (Subtarget->isTargetCygMing()) {
18419 // ___chkstk(Mingw64):
18420 // Clobbers R10, R11, RAX and EFLAGS.
18422 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18423 .addExternalSymbol("___chkstk")
18424 .addReg(X86::RAX, RegState::Implicit)
18425 .addReg(X86::RSP, RegState::Implicit)
18426 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
18427 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
18428 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18430 // __chkstk(MSVCRT): does not update stack pointer.
18431 // Clobbers R10, R11 and EFLAGS.
18432 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18433 .addExternalSymbol("__chkstk")
18434 .addReg(X86::RAX, RegState::Implicit)
18435 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18436 // RAX has the offset to be subtracted from RSP.
18437 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
18442 const char *StackProbeSymbol =
18443 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
18445 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
18446 .addExternalSymbol(StackProbeSymbol)
18447 .addReg(X86::EAX, RegState::Implicit)
18448 .addReg(X86::ESP, RegState::Implicit)
18449 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
18450 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
18451 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18454 MI->eraseFromParent(); // The pseudo instruction is gone now.
18458 MachineBasicBlock *
18459 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18460 MachineBasicBlock *BB) const {
18461 // This is pretty easy. We're taking the value that we received from
18462 // our load from the relocation, sticking it in either RDI (x86-64)
18463 // or EAX and doing an indirect call. The return value will then
18464 // be in the normal return register.
18465 MachineFunction *F = BB->getParent();
18466 const X86InstrInfo *TII =
18467 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
18468 DebugLoc DL = MI->getDebugLoc();
18470 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18471 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18473 // Get a register mask for the lowered call.
18474 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18475 // proper register mask.
18476 const uint32_t *RegMask = F->getTarget()
18477 .getSubtargetImpl()
18478 ->getRegisterInfo()
18479 ->getCallPreservedMask(CallingConv::C);
18480 if (Subtarget->is64Bit()) {
18481 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18482 TII->get(X86::MOV64rm), X86::RDI)
18484 .addImm(0).addReg(0)
18485 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18486 MI->getOperand(3).getTargetFlags())
18488 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18489 addDirectMem(MIB, X86::RDI);
18490 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18491 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18492 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18493 TII->get(X86::MOV32rm), X86::EAX)
18495 .addImm(0).addReg(0)
18496 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18497 MI->getOperand(3).getTargetFlags())
18499 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18500 addDirectMem(MIB, X86::EAX);
18501 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18503 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18504 TII->get(X86::MOV32rm), X86::EAX)
18505 .addReg(TII->getGlobalBaseReg(F))
18506 .addImm(0).addReg(0)
18507 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18508 MI->getOperand(3).getTargetFlags())
18510 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18511 addDirectMem(MIB, X86::EAX);
18512 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18515 MI->eraseFromParent(); // The pseudo instruction is gone now.
18519 MachineBasicBlock *
18520 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18521 MachineBasicBlock *MBB) const {
18522 DebugLoc DL = MI->getDebugLoc();
18523 MachineFunction *MF = MBB->getParent();
18524 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18525 MachineRegisterInfo &MRI = MF->getRegInfo();
18527 const BasicBlock *BB = MBB->getBasicBlock();
18528 MachineFunction::iterator I = MBB;
18531 // Memory Reference
18532 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18533 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18536 unsigned MemOpndSlot = 0;
18538 unsigned CurOp = 0;
18540 DstReg = MI->getOperand(CurOp++).getReg();
18541 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18542 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18543 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18544 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18546 MemOpndSlot = CurOp;
18548 MVT PVT = getPointerTy();
18549 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18550 "Invalid Pointer Size!");
18552 // For v = setjmp(buf), we generate
18555 // buf[LabelOffset] = restoreMBB
18556 // SjLjSetup restoreMBB
18562 // v = phi(main, restore)
18567 MachineBasicBlock *thisMBB = MBB;
18568 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18569 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18570 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18571 MF->insert(I, mainMBB);
18572 MF->insert(I, sinkMBB);
18573 MF->push_back(restoreMBB);
18575 MachineInstrBuilder MIB;
18577 // Transfer the remainder of BB and its successor edges to sinkMBB.
18578 sinkMBB->splice(sinkMBB->begin(), MBB,
18579 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18580 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18583 unsigned PtrStoreOpc = 0;
18584 unsigned LabelReg = 0;
18585 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18586 Reloc::Model RM = MF->getTarget().getRelocationModel();
18587 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18588 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18590 // Prepare IP either in reg or imm.
18591 if (!UseImmLabel) {
18592 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18593 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18594 LabelReg = MRI.createVirtualRegister(PtrRC);
18595 if (Subtarget->is64Bit()) {
18596 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18600 .addMBB(restoreMBB)
18603 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18604 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18605 .addReg(XII->getGlobalBaseReg(MF))
18608 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18612 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18614 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18615 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18616 if (i == X86::AddrDisp)
18617 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18619 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18622 MIB.addReg(LabelReg);
18624 MIB.addMBB(restoreMBB);
18625 MIB.setMemRefs(MMOBegin, MMOEnd);
18627 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18628 .addMBB(restoreMBB);
18630 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18631 MF->getSubtarget().getRegisterInfo());
18632 MIB.addRegMask(RegInfo->getNoPreservedMask());
18633 thisMBB->addSuccessor(mainMBB);
18634 thisMBB->addSuccessor(restoreMBB);
18638 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18639 mainMBB->addSuccessor(sinkMBB);
18642 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18643 TII->get(X86::PHI), DstReg)
18644 .addReg(mainDstReg).addMBB(mainMBB)
18645 .addReg(restoreDstReg).addMBB(restoreMBB);
18648 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18649 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
18650 restoreMBB->addSuccessor(sinkMBB);
18652 MI->eraseFromParent();
18656 MachineBasicBlock *
18657 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18658 MachineBasicBlock *MBB) const {
18659 DebugLoc DL = MI->getDebugLoc();
18660 MachineFunction *MF = MBB->getParent();
18661 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18662 MachineRegisterInfo &MRI = MF->getRegInfo();
18664 // Memory Reference
18665 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18666 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18668 MVT PVT = getPointerTy();
18669 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18670 "Invalid Pointer Size!");
18672 const TargetRegisterClass *RC =
18673 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18674 unsigned Tmp = MRI.createVirtualRegister(RC);
18675 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18676 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18677 MF->getSubtarget().getRegisterInfo());
18678 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18679 unsigned SP = RegInfo->getStackRegister();
18681 MachineInstrBuilder MIB;
18683 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18684 const int64_t SPOffset = 2 * PVT.getStoreSize();
18686 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18687 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18690 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18691 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18692 MIB.addOperand(MI->getOperand(i));
18693 MIB.setMemRefs(MMOBegin, MMOEnd);
18695 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18696 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18697 if (i == X86::AddrDisp)
18698 MIB.addDisp(MI->getOperand(i), LabelOffset);
18700 MIB.addOperand(MI->getOperand(i));
18702 MIB.setMemRefs(MMOBegin, MMOEnd);
18704 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18705 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18706 if (i == X86::AddrDisp)
18707 MIB.addDisp(MI->getOperand(i), SPOffset);
18709 MIB.addOperand(MI->getOperand(i));
18711 MIB.setMemRefs(MMOBegin, MMOEnd);
18713 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
18715 MI->eraseFromParent();
18719 // Replace 213-type (isel default) FMA3 instructions with 231-type for
18720 // accumulator loops. Writing back to the accumulator allows the coalescer
18721 // to remove extra copies in the loop.
18722 MachineBasicBlock *
18723 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
18724 MachineBasicBlock *MBB) const {
18725 MachineOperand &AddendOp = MI->getOperand(3);
18727 // Bail out early if the addend isn't a register - we can't switch these.
18728 if (!AddendOp.isReg())
18731 MachineFunction &MF = *MBB->getParent();
18732 MachineRegisterInfo &MRI = MF.getRegInfo();
18734 // Check whether the addend is defined by a PHI:
18735 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
18736 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
18737 if (!AddendDef.isPHI())
18740 // Look for the following pattern:
18742 // %addend = phi [%entry, 0], [%loop, %result]
18744 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
18748 // %addend = phi [%entry, 0], [%loop, %result]
18750 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
18752 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
18753 assert(AddendDef.getOperand(i).isReg());
18754 MachineOperand PHISrcOp = AddendDef.getOperand(i);
18755 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
18756 if (&PHISrcInst == MI) {
18757 // Found a matching instruction.
18758 unsigned NewFMAOpc = 0;
18759 switch (MI->getOpcode()) {
18760 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
18761 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
18762 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
18763 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
18764 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
18765 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
18766 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
18767 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
18768 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
18769 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
18770 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
18771 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
18772 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
18773 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
18774 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
18775 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18776 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18777 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18778 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18779 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18780 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18781 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18782 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18783 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18784 default: llvm_unreachable("Unrecognized FMA variant.");
18787 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
18788 MachineInstrBuilder MIB =
18789 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18790 .addOperand(MI->getOperand(0))
18791 .addOperand(MI->getOperand(3))
18792 .addOperand(MI->getOperand(2))
18793 .addOperand(MI->getOperand(1));
18794 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18795 MI->eraseFromParent();
18802 MachineBasicBlock *
18803 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
18804 MachineBasicBlock *BB) const {
18805 switch (MI->getOpcode()) {
18806 default: llvm_unreachable("Unexpected instr type to insert");
18807 case X86::TAILJMPd64:
18808 case X86::TAILJMPr64:
18809 case X86::TAILJMPm64:
18810 llvm_unreachable("TAILJMP64 would not be touched here.");
18811 case X86::TCRETURNdi64:
18812 case X86::TCRETURNri64:
18813 case X86::TCRETURNmi64:
18815 case X86::WIN_ALLOCA:
18816 return EmitLoweredWinAlloca(MI, BB);
18817 case X86::SEG_ALLOCA_32:
18818 return EmitLoweredSegAlloca(MI, BB, false);
18819 case X86::SEG_ALLOCA_64:
18820 return EmitLoweredSegAlloca(MI, BB, true);
18821 case X86::TLSCall_32:
18822 case X86::TLSCall_64:
18823 return EmitLoweredTLSCall(MI, BB);
18824 case X86::CMOV_GR8:
18825 case X86::CMOV_FR32:
18826 case X86::CMOV_FR64:
18827 case X86::CMOV_V4F32:
18828 case X86::CMOV_V2F64:
18829 case X86::CMOV_V2I64:
18830 case X86::CMOV_V8F32:
18831 case X86::CMOV_V4F64:
18832 case X86::CMOV_V4I64:
18833 case X86::CMOV_V16F32:
18834 case X86::CMOV_V8F64:
18835 case X86::CMOV_V8I64:
18836 case X86::CMOV_GR16:
18837 case X86::CMOV_GR32:
18838 case X86::CMOV_RFP32:
18839 case X86::CMOV_RFP64:
18840 case X86::CMOV_RFP80:
18841 return EmitLoweredSelect(MI, BB);
18843 case X86::FP32_TO_INT16_IN_MEM:
18844 case X86::FP32_TO_INT32_IN_MEM:
18845 case X86::FP32_TO_INT64_IN_MEM:
18846 case X86::FP64_TO_INT16_IN_MEM:
18847 case X86::FP64_TO_INT32_IN_MEM:
18848 case X86::FP64_TO_INT64_IN_MEM:
18849 case X86::FP80_TO_INT16_IN_MEM:
18850 case X86::FP80_TO_INT32_IN_MEM:
18851 case X86::FP80_TO_INT64_IN_MEM: {
18852 MachineFunction *F = BB->getParent();
18853 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
18854 DebugLoc DL = MI->getDebugLoc();
18856 // Change the floating point control register to use "round towards zero"
18857 // mode when truncating to an integer value.
18858 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18859 addFrameReference(BuildMI(*BB, MI, DL,
18860 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18862 // Load the old value of the high byte of the control word...
18864 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18865 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18868 // Set the high part to be round to zero...
18869 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18872 // Reload the modified control word now...
18873 addFrameReference(BuildMI(*BB, MI, DL,
18874 TII->get(X86::FLDCW16m)), CWFrameIdx);
18876 // Restore the memory image of control word to original value
18877 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18880 // Get the X86 opcode to use.
18882 switch (MI->getOpcode()) {
18883 default: llvm_unreachable("illegal opcode!");
18884 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18885 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18886 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18887 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18888 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18889 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18890 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18891 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18892 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18896 MachineOperand &Op = MI->getOperand(0);
18898 AM.BaseType = X86AddressMode::RegBase;
18899 AM.Base.Reg = Op.getReg();
18901 AM.BaseType = X86AddressMode::FrameIndexBase;
18902 AM.Base.FrameIndex = Op.getIndex();
18904 Op = MI->getOperand(1);
18906 AM.Scale = Op.getImm();
18907 Op = MI->getOperand(2);
18909 AM.IndexReg = Op.getImm();
18910 Op = MI->getOperand(3);
18911 if (Op.isGlobal()) {
18912 AM.GV = Op.getGlobal();
18914 AM.Disp = Op.getImm();
18916 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18917 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18919 // Reload the original control word now.
18920 addFrameReference(BuildMI(*BB, MI, DL,
18921 TII->get(X86::FLDCW16m)), CWFrameIdx);
18923 MI->eraseFromParent(); // The pseudo instruction is gone now.
18926 // String/text processing lowering.
18927 case X86::PCMPISTRM128REG:
18928 case X86::VPCMPISTRM128REG:
18929 case X86::PCMPISTRM128MEM:
18930 case X86::VPCMPISTRM128MEM:
18931 case X86::PCMPESTRM128REG:
18932 case X86::VPCMPESTRM128REG:
18933 case X86::PCMPESTRM128MEM:
18934 case X86::VPCMPESTRM128MEM:
18935 assert(Subtarget->hasSSE42() &&
18936 "Target must have SSE4.2 or AVX features enabled");
18937 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18939 // String/text processing lowering.
18940 case X86::PCMPISTRIREG:
18941 case X86::VPCMPISTRIREG:
18942 case X86::PCMPISTRIMEM:
18943 case X86::VPCMPISTRIMEM:
18944 case X86::PCMPESTRIREG:
18945 case X86::VPCMPESTRIREG:
18946 case X86::PCMPESTRIMEM:
18947 case X86::VPCMPESTRIMEM:
18948 assert(Subtarget->hasSSE42() &&
18949 "Target must have SSE4.2 or AVX features enabled");
18950 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18952 // Thread synchronization.
18954 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
18959 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18961 case X86::VASTART_SAVE_XMM_REGS:
18962 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
18964 case X86::VAARG_64:
18965 return EmitVAARG64WithCustomInserter(MI, BB);
18967 case X86::EH_SjLj_SetJmp32:
18968 case X86::EH_SjLj_SetJmp64:
18969 return emitEHSjLjSetJmp(MI, BB);
18971 case X86::EH_SjLj_LongJmp32:
18972 case X86::EH_SjLj_LongJmp64:
18973 return emitEHSjLjLongJmp(MI, BB);
18975 case TargetOpcode::STACKMAP:
18976 case TargetOpcode::PATCHPOINT:
18977 return emitPatchPoint(MI, BB);
18979 case X86::VFMADDPDr213r:
18980 case X86::VFMADDPSr213r:
18981 case X86::VFMADDSDr213r:
18982 case X86::VFMADDSSr213r:
18983 case X86::VFMSUBPDr213r:
18984 case X86::VFMSUBPSr213r:
18985 case X86::VFMSUBSDr213r:
18986 case X86::VFMSUBSSr213r:
18987 case X86::VFNMADDPDr213r:
18988 case X86::VFNMADDPSr213r:
18989 case X86::VFNMADDSDr213r:
18990 case X86::VFNMADDSSr213r:
18991 case X86::VFNMSUBPDr213r:
18992 case X86::VFNMSUBPSr213r:
18993 case X86::VFNMSUBSDr213r:
18994 case X86::VFNMSUBSSr213r:
18995 case X86::VFMADDPDr213rY:
18996 case X86::VFMADDPSr213rY:
18997 case X86::VFMSUBPDr213rY:
18998 case X86::VFMSUBPSr213rY:
18999 case X86::VFNMADDPDr213rY:
19000 case X86::VFNMADDPSr213rY:
19001 case X86::VFNMSUBPDr213rY:
19002 case X86::VFNMSUBPSr213rY:
19003 return emitFMA3Instr(MI, BB);
19007 //===----------------------------------------------------------------------===//
19008 // X86 Optimization Hooks
19009 //===----------------------------------------------------------------------===//
19011 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19014 const SelectionDAG &DAG,
19015 unsigned Depth) const {
19016 unsigned BitWidth = KnownZero.getBitWidth();
19017 unsigned Opc = Op.getOpcode();
19018 assert((Opc >= ISD::BUILTIN_OP_END ||
19019 Opc == ISD::INTRINSIC_WO_CHAIN ||
19020 Opc == ISD::INTRINSIC_W_CHAIN ||
19021 Opc == ISD::INTRINSIC_VOID) &&
19022 "Should use MaskedValueIsZero if you don't know whether Op"
19023 " is a target node!");
19025 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19039 // These nodes' second result is a boolean.
19040 if (Op.getResNo() == 0)
19043 case X86ISD::SETCC:
19044 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19046 case ISD::INTRINSIC_WO_CHAIN: {
19047 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19048 unsigned NumLoBits = 0;
19051 case Intrinsic::x86_sse_movmsk_ps:
19052 case Intrinsic::x86_avx_movmsk_ps_256:
19053 case Intrinsic::x86_sse2_movmsk_pd:
19054 case Intrinsic::x86_avx_movmsk_pd_256:
19055 case Intrinsic::x86_mmx_pmovmskb:
19056 case Intrinsic::x86_sse2_pmovmskb_128:
19057 case Intrinsic::x86_avx2_pmovmskb: {
19058 // High bits of movmskp{s|d}, pmovmskb are known zero.
19060 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19061 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19062 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19063 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19064 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19065 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19066 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19067 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19069 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19078 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19080 const SelectionDAG &,
19081 unsigned Depth) const {
19082 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19083 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19084 return Op.getValueType().getScalarType().getSizeInBits();
19090 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19091 /// node is a GlobalAddress + offset.
19092 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19093 const GlobalValue* &GA,
19094 int64_t &Offset) const {
19095 if (N->getOpcode() == X86ISD::Wrapper) {
19096 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19097 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19098 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19102 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19105 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19106 /// same as extracting the high 128-bit part of 256-bit vector and then
19107 /// inserting the result into the low part of a new 256-bit vector
19108 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19109 EVT VT = SVOp->getValueType(0);
19110 unsigned NumElems = VT.getVectorNumElements();
19112 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19113 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19114 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19115 SVOp->getMaskElt(j) >= 0)
19121 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19122 /// same as extracting the low 128-bit part of 256-bit vector and then
19123 /// inserting the result into the high part of a new 256-bit vector
19124 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19125 EVT VT = SVOp->getValueType(0);
19126 unsigned NumElems = VT.getVectorNumElements();
19128 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19129 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19130 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19131 SVOp->getMaskElt(j) >= 0)
19137 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19138 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19139 TargetLowering::DAGCombinerInfo &DCI,
19140 const X86Subtarget* Subtarget) {
19142 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19143 SDValue V1 = SVOp->getOperand(0);
19144 SDValue V2 = SVOp->getOperand(1);
19145 EVT VT = SVOp->getValueType(0);
19146 unsigned NumElems = VT.getVectorNumElements();
19148 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19149 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19153 // V UNDEF BUILD_VECTOR UNDEF
19155 // CONCAT_VECTOR CONCAT_VECTOR
19158 // RESULT: V + zero extended
19160 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19161 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19162 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19165 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19168 // To match the shuffle mask, the first half of the mask should
19169 // be exactly the first vector, and all the rest a splat with the
19170 // first element of the second one.
19171 for (unsigned i = 0; i != NumElems/2; ++i)
19172 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19173 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19176 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19177 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19178 if (Ld->hasNUsesOfValue(1, 0)) {
19179 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19180 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19182 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19184 Ld->getPointerInfo(),
19185 Ld->getAlignment(),
19186 false/*isVolatile*/, true/*ReadMem*/,
19187 false/*WriteMem*/);
19189 // Make sure the newly-created LOAD is in the same position as Ld in
19190 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19191 // and update uses of Ld's output chain to use the TokenFactor.
19192 if (Ld->hasAnyUseOfValue(1)) {
19193 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19194 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19195 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19196 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19197 SDValue(ResNode.getNode(), 1));
19200 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19204 // Emit a zeroed vector and insert the desired subvector on its
19206 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19207 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19208 return DCI.CombineTo(N, InsV);
19211 //===--------------------------------------------------------------------===//
19212 // Combine some shuffles into subvector extracts and inserts:
19215 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19216 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19217 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19218 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19219 return DCI.CombineTo(N, InsV);
19222 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19223 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19224 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19225 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19226 return DCI.CombineTo(N, InsV);
19232 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19235 /// This is the leaf of the recursive combinine below. When we have found some
19236 /// chain of single-use x86 shuffle instructions and accumulated the combined
19237 /// shuffle mask represented by them, this will try to pattern match that mask
19238 /// into either a single instruction if there is a special purpose instruction
19239 /// for this operation, or into a PSHUFB instruction which is a fully general
19240 /// instruction but should only be used to replace chains over a certain depth.
19241 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19242 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19243 TargetLowering::DAGCombinerInfo &DCI,
19244 const X86Subtarget *Subtarget) {
19245 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19247 // Find the operand that enters the chain. Note that multiple uses are OK
19248 // here, we're not going to remove the operand we find.
19249 SDValue Input = Op.getOperand(0);
19250 while (Input.getOpcode() == ISD::BITCAST)
19251 Input = Input.getOperand(0);
19253 MVT VT = Input.getSimpleValueType();
19254 MVT RootVT = Root.getSimpleValueType();
19257 // Just remove no-op shuffle masks.
19258 if (Mask.size() == 1) {
19259 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19264 // Use the float domain if the operand type is a floating point type.
19265 bool FloatDomain = VT.isFloatingPoint();
19267 // If we don't have access to VEX encodings, the generic PSHUF instructions
19268 // are preferable to some of the specialized forms despite requiring one more
19269 // byte to encode because they can implicitly copy.
19271 // IF we *do* have VEX encodings, than we can use shorter, more specific
19272 // shuffle instructions freely as they can copy due to the extra register
19274 if (Subtarget->hasAVX()) {
19275 // We have both floating point and integer variants of shuffles that dup
19276 // either the low or high half of the vector.
19277 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
19278 bool Lo = Mask.equals(0, 0);
19279 unsigned Shuffle = FloatDomain ? (Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS)
19280 : (Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH);
19281 if (Depth == 1 && Root->getOpcode() == Shuffle)
19282 return false; // Nothing to do!
19283 MVT ShuffleVT = FloatDomain ? MVT::v4f32 : MVT::v2i64;
19284 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19285 DCI.AddToWorklist(Op.getNode());
19286 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19287 DCI.AddToWorklist(Op.getNode());
19288 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19293 // FIXME: We should match UNPCKLPS and UNPCKHPS here.
19295 // For the integer domain we have specialized instructions for duplicating
19296 // any element size from the low or high half.
19297 if (!FloatDomain &&
19298 (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3) ||
19299 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
19300 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
19301 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
19302 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
19304 bool Lo = Mask[0] == 0;
19305 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19306 if (Depth == 1 && Root->getOpcode() == Shuffle)
19307 return false; // Nothing to do!
19309 switch (Mask.size()) {
19310 case 4: ShuffleVT = MVT::v4i32; break;
19311 case 8: ShuffleVT = MVT::v8i16; break;
19312 case 16: ShuffleVT = MVT::v16i8; break;
19314 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19315 DCI.AddToWorklist(Op.getNode());
19316 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19317 DCI.AddToWorklist(Op.getNode());
19318 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19324 // Don't try to re-form single instruction chains under any circumstances now
19325 // that we've done encoding canonicalization for them.
19329 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19330 // can replace them with a single PSHUFB instruction profitably. Intel's
19331 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19332 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19333 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19334 SmallVector<SDValue, 16> PSHUFBMask;
19335 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
19336 int Ratio = 16 / Mask.size();
19337 for (unsigned i = 0; i < 16; ++i) {
19338 int M = Ratio * Mask[i / Ratio] + i % Ratio;
19339 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19341 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
19342 DCI.AddToWorklist(Op.getNode());
19343 SDValue PSHUFBMaskOp =
19344 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
19345 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19346 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
19347 DCI.AddToWorklist(Op.getNode());
19348 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19353 // Failed to find any combines.
19357 /// \brief Fully generic combining of x86 shuffle instructions.
19359 /// This should be the last combine run over the x86 shuffle instructions. Once
19360 /// they have been fully optimized, this will recursively consider all chains
19361 /// of single-use shuffle instructions, build a generic model of the cumulative
19362 /// shuffle operation, and check for simpler instructions which implement this
19363 /// operation. We use this primarily for two purposes:
19365 /// 1) Collapse generic shuffles to specialized single instructions when
19366 /// equivalent. In most cases, this is just an encoding size win, but
19367 /// sometimes we will collapse multiple generic shuffles into a single
19368 /// special-purpose shuffle.
19369 /// 2) Look for sequences of shuffle instructions with 3 or more total
19370 /// instructions, and replace them with the slightly more expensive SSSE3
19371 /// PSHUFB instruction if available. We do this as the last combining step
19372 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19373 /// a suitable short sequence of other instructions. The PHUFB will either
19374 /// use a register or have to read from memory and so is slightly (but only
19375 /// slightly) more expensive than the other shuffle instructions.
19377 /// Because this is inherently a quadratic operation (for each shuffle in
19378 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19379 /// This should never be an issue in practice as the shuffle lowering doesn't
19380 /// produce sequences of more than 8 instructions.
19382 /// FIXME: We will currently miss some cases where the redundant shuffling
19383 /// would simplify under the threshold for PSHUFB formation because of
19384 /// combine-ordering. To fix this, we should do the redundant instruction
19385 /// combining in this recursive walk.
19386 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19387 ArrayRef<int> IncomingMask, int Depth,
19388 bool HasPSHUFB, SelectionDAG &DAG,
19389 TargetLowering::DAGCombinerInfo &DCI,
19390 const X86Subtarget *Subtarget) {
19391 // Bound the depth of our recursive combine because this is ultimately
19392 // quadratic in nature.
19396 // Directly rip through bitcasts to find the underlying operand.
19397 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19398 Op = Op.getOperand(0);
19400 MVT VT = Op.getSimpleValueType();
19401 if (!VT.isVector())
19402 return false; // Bail if we hit a non-vector.
19403 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
19404 // version should be added.
19405 if (VT.getSizeInBits() != 128)
19408 assert(Root.getSimpleValueType().isVector() &&
19409 "Shuffles operate on vector types!");
19410 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19411 "Can only combine shuffles of the same vector register size.");
19413 if (!isTargetShuffle(Op.getOpcode()))
19415 SmallVector<int, 16> OpMask;
19417 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19418 // We only can combine unary shuffles which we can decode the mask for.
19419 if (!HaveMask || !IsUnary)
19422 assert(VT.getVectorNumElements() == OpMask.size() &&
19423 "Different mask size from vector size!");
19425 SmallVector<int, 16> Mask;
19426 Mask.reserve(std::max(OpMask.size(), IncomingMask.size()));
19428 // Merge this shuffle operation's mask into our accumulated mask. This is
19429 // a bit tricky as the shuffle may have a different size from the root.
19430 if (OpMask.size() == IncomingMask.size()) {
19431 for (int M : IncomingMask)
19432 Mask.push_back(OpMask[M]);
19433 } else if (OpMask.size() < IncomingMask.size()) {
19434 assert(IncomingMask.size() % OpMask.size() == 0 &&
19435 "The smaller number of elements must divide the larger.");
19436 int Ratio = IncomingMask.size() / OpMask.size();
19437 for (int M : IncomingMask)
19438 Mask.push_back(Ratio * OpMask[M / Ratio] + M % Ratio);
19440 assert(OpMask.size() > IncomingMask.size() && "All other cases handled!");
19441 assert(OpMask.size() % IncomingMask.size() == 0 &&
19442 "The smaller number of elements must divide the larger.");
19443 int Ratio = OpMask.size() / IncomingMask.size();
19444 for (int i = 0, e = OpMask.size(); i < e; ++i)
19445 Mask.push_back(OpMask[Ratio * IncomingMask[i / Ratio] + i % Ratio]);
19448 // See if we can recurse into the operand to combine more things.
19449 switch (Op.getOpcode()) {
19450 case X86ISD::PSHUFB:
19452 case X86ISD::PSHUFD:
19453 case X86ISD::PSHUFHW:
19454 case X86ISD::PSHUFLW:
19455 if (Op.getOperand(0).hasOneUse() &&
19456 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19457 HasPSHUFB, DAG, DCI, Subtarget))
19461 case X86ISD::UNPCKL:
19462 case X86ISD::UNPCKH:
19463 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19464 // We can't check for single use, we have to check that this shuffle is the only user.
19465 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19466 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19467 HasPSHUFB, DAG, DCI, Subtarget))
19472 // Minor canonicalization of the accumulated shuffle mask to make it easier
19473 // to match below. All this does is detect masks with squential pairs of
19474 // elements, and shrink them to the half-width mask. It does this in a loop
19475 // so it will reduce the size of the mask to the minimal width mask which
19476 // performs an equivalent shuffle.
19477 while (Mask.size() > 1) {
19478 SmallVector<int, 16> NewMask;
19479 for (int i = 0, e = Mask.size()/2; i < e; ++i) {
19480 if (Mask[2*i] % 2 != 0 || Mask[2*i] != Mask[2*i + 1] + 1) {
19484 NewMask.push_back(Mask[2*i] / 2);
19486 if (NewMask.empty())
19488 Mask.swap(NewMask);
19491 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19495 /// \brief Get the PSHUF-style mask from PSHUF node.
19497 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19498 /// PSHUF-style masks that can be reused with such instructions.
19499 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19500 SmallVector<int, 4> Mask;
19502 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
19506 switch (N.getOpcode()) {
19507 case X86ISD::PSHUFD:
19509 case X86ISD::PSHUFLW:
19512 case X86ISD::PSHUFHW:
19513 Mask.erase(Mask.begin(), Mask.begin() + 4);
19514 for (int &M : Mask)
19518 llvm_unreachable("No valid shuffle instruction found!");
19522 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19524 /// We walk up the chain and look for a combinable shuffle, skipping over
19525 /// shuffles that we could hoist this shuffle's transformation past without
19526 /// altering anything.
19527 static bool combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19529 TargetLowering::DAGCombinerInfo &DCI) {
19530 assert(N.getOpcode() == X86ISD::PSHUFD &&
19531 "Called with something other than an x86 128-bit half shuffle!");
19534 // Walk up a single-use chain looking for a combinable shuffle.
19535 SDValue V = N.getOperand(0);
19536 for (; V.hasOneUse(); V = V.getOperand(0)) {
19537 switch (V.getOpcode()) {
19539 return false; // Nothing combined!
19542 // Skip bitcasts as we always know the type for the target specific
19546 case X86ISD::PSHUFD:
19547 // Found another dword shuffle.
19550 case X86ISD::PSHUFLW:
19551 // Check that the low words (being shuffled) are the identity in the
19552 // dword shuffle, and the high words are self-contained.
19553 if (Mask[0] != 0 || Mask[1] != 1 ||
19554 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19559 case X86ISD::PSHUFHW:
19560 // Check that the high words (being shuffled) are the identity in the
19561 // dword shuffle, and the low words are self-contained.
19562 if (Mask[2] != 2 || Mask[3] != 3 ||
19563 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19568 case X86ISD::UNPCKL:
19569 case X86ISD::UNPCKH:
19570 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19571 // shuffle into a preceding word shuffle.
19572 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
19575 // Search for a half-shuffle which we can combine with.
19576 unsigned CombineOp =
19577 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19578 if (V.getOperand(0) != V.getOperand(1) ||
19579 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19581 V = V.getOperand(0);
19583 switch (V.getOpcode()) {
19585 return false; // Nothing to combine.
19587 case X86ISD::PSHUFLW:
19588 case X86ISD::PSHUFHW:
19589 if (V.getOpcode() == CombineOp)
19594 V = V.getOperand(0);
19598 } while (V.hasOneUse());
19601 // Break out of the loop if we break out of the switch.
19605 if (!V.hasOneUse())
19606 // We fell out of the loop without finding a viable combining instruction.
19609 // Record the old value to use in RAUW-ing.
19612 // Merge this node's mask and our incoming mask.
19613 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19614 for (int &M : Mask)
19616 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
19617 getV4X86ShuffleImm8ForMask(Mask, DAG));
19619 // It is possible that one of the combinable shuffles was completely absorbed
19620 // by the other, just replace it and revisit all users in that case.
19621 if (Old.getNode() == V.getNode()) {
19622 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo=*/true);
19626 // Replace N with its operand as we're going to combine that shuffle away.
19627 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
19629 // Replace the combinable shuffle with the combined one, updating all users
19630 // so that we re-evaluate the chain here.
19631 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19635 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
19637 /// We walk up the chain, skipping shuffles of the other half and looking
19638 /// through shuffles which switch halves trying to find a shuffle of the same
19639 /// pair of dwords.
19640 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
19642 TargetLowering::DAGCombinerInfo &DCI) {
19644 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
19645 "Called with something other than an x86 128-bit half shuffle!");
19647 unsigned CombineOpcode = N.getOpcode();
19649 // Walk up a single-use chain looking for a combinable shuffle.
19650 SDValue V = N.getOperand(0);
19651 for (; V.hasOneUse(); V = V.getOperand(0)) {
19652 switch (V.getOpcode()) {
19654 return false; // Nothing combined!
19657 // Skip bitcasts as we always know the type for the target specific
19661 case X86ISD::PSHUFLW:
19662 case X86ISD::PSHUFHW:
19663 if (V.getOpcode() == CombineOpcode)
19666 // Other-half shuffles are no-ops.
19669 // Break out of the loop if we break out of the switch.
19673 if (!V.hasOneUse())
19674 // We fell out of the loop without finding a viable combining instruction.
19677 // Combine away the bottom node as its shuffle will be accumulated into
19678 // a preceding shuffle.
19679 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19681 // Record the old value.
19684 // Merge this node's mask and our incoming mask (adjusted to account for all
19685 // the pshufd instructions encountered).
19686 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19687 for (int &M : Mask)
19689 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
19690 getV4X86ShuffleImm8ForMask(Mask, DAG));
19692 // Check that the shuffles didn't cancel each other out. If not, we need to
19693 // combine to the new one.
19695 // Replace the combinable shuffle with the combined one, updating all users
19696 // so that we re-evaluate the chain here.
19697 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19702 /// \brief Try to combine x86 target specific shuffles.
19703 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
19704 TargetLowering::DAGCombinerInfo &DCI,
19705 const X86Subtarget *Subtarget) {
19707 MVT VT = N.getSimpleValueType();
19708 SmallVector<int, 4> Mask;
19710 switch (N.getOpcode()) {
19711 case X86ISD::PSHUFD:
19712 case X86ISD::PSHUFLW:
19713 case X86ISD::PSHUFHW:
19714 Mask = getPSHUFShuffleMask(N);
19715 assert(Mask.size() == 4);
19721 // Nuke no-op shuffles that show up after combining.
19722 if (isNoopShuffleMask(Mask))
19723 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19725 // Look for simplifications involving one or two shuffle instructions.
19726 SDValue V = N.getOperand(0);
19727 switch (N.getOpcode()) {
19730 case X86ISD::PSHUFLW:
19731 case X86ISD::PSHUFHW:
19732 assert(VT == MVT::v8i16);
19735 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
19736 return SDValue(); // We combined away this shuffle, so we're done.
19738 // See if this reduces to a PSHUFD which is no more expensive and can
19739 // combine with more operations.
19740 if (canWidenShuffleElements(Mask)) {
19741 int DMask[] = {-1, -1, -1, -1};
19742 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
19743 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
19744 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
19745 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
19746 DCI.AddToWorklist(V.getNode());
19747 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
19748 getV4X86ShuffleImm8ForMask(DMask, DAG));
19749 DCI.AddToWorklist(V.getNode());
19750 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
19753 // Look for shuffle patterns which can be implemented as a single unpack.
19754 // FIXME: This doesn't handle the location of the PSHUFD generically, and
19755 // only works when we have a PSHUFD followed by two half-shuffles.
19756 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
19757 (V.getOpcode() == X86ISD::PSHUFLW ||
19758 V.getOpcode() == X86ISD::PSHUFHW) &&
19759 V.getOpcode() != N.getOpcode() &&
19761 SDValue D = V.getOperand(0);
19762 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
19763 D = D.getOperand(0);
19764 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
19765 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19766 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
19767 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19768 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19770 for (int i = 0; i < 4; ++i) {
19771 WordMask[i + NOffset] = Mask[i] + NOffset;
19772 WordMask[i + VOffset] = VMask[i] + VOffset;
19774 // Map the word mask through the DWord mask.
19776 for (int i = 0; i < 8; ++i)
19777 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
19778 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
19779 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
19780 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
19781 std::begin(UnpackLoMask)) ||
19782 std::equal(std::begin(MappedMask), std::end(MappedMask),
19783 std::begin(UnpackHiMask))) {
19784 // We can replace all three shuffles with an unpack.
19785 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
19786 DCI.AddToWorklist(V.getNode());
19787 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
19789 DL, MVT::v8i16, V, V);
19796 case X86ISD::PSHUFD:
19797 if (combineRedundantDWordShuffle(N, Mask, DAG, DCI))
19798 return SDValue(); // We combined away this shuffle.
19806 /// PerformShuffleCombine - Performs several different shuffle combines.
19807 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
19808 TargetLowering::DAGCombinerInfo &DCI,
19809 const X86Subtarget *Subtarget) {
19811 SDValue N0 = N->getOperand(0);
19812 SDValue N1 = N->getOperand(1);
19813 EVT VT = N->getValueType(0);
19815 // Don't create instructions with illegal types after legalize types has run.
19816 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19817 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
19820 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
19821 if (Subtarget->hasFp256() && VT.is256BitVector() &&
19822 N->getOpcode() == ISD::VECTOR_SHUFFLE)
19823 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
19825 // During Type Legalization, when promoting illegal vector types,
19826 // the backend might introduce new shuffle dag nodes and bitcasts.
19828 // This code performs the following transformation:
19829 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
19830 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
19832 // We do this only if both the bitcast and the BINOP dag nodes have
19833 // one use. Also, perform this transformation only if the new binary
19834 // operation is legal. This is to avoid introducing dag nodes that
19835 // potentially need to be further expanded (or custom lowered) into a
19836 // less optimal sequence of dag nodes.
19837 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
19838 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
19839 N0.getOpcode() == ISD::BITCAST) {
19840 SDValue BC0 = N0.getOperand(0);
19841 EVT SVT = BC0.getValueType();
19842 unsigned Opcode = BC0.getOpcode();
19843 unsigned NumElts = VT.getVectorNumElements();
19845 if (BC0.hasOneUse() && SVT.isVector() &&
19846 SVT.getVectorNumElements() * 2 == NumElts &&
19847 TLI.isOperationLegal(Opcode, VT)) {
19848 bool CanFold = false;
19860 unsigned SVTNumElts = SVT.getVectorNumElements();
19861 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19862 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
19863 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
19864 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
19865 CanFold = SVOp->getMaskElt(i) < 0;
19868 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
19869 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
19870 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
19871 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
19876 // Only handle 128 wide vector from here on.
19877 if (!VT.is128BitVector())
19880 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
19881 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
19882 // consecutive, non-overlapping, and in the right order.
19883 SmallVector<SDValue, 16> Elts;
19884 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
19885 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
19887 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
19891 if (isTargetShuffle(N->getOpcode())) {
19893 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
19894 if (Shuffle.getNode())
19897 // Try recursively combining arbitrary sequences of x86 shuffle
19898 // instructions into higher-order shuffles. We do this after combining
19899 // specific PSHUF instruction sequences into their minimal form so that we
19900 // can evaluate how many specialized shuffle instructions are involved in
19901 // a particular chain.
19902 SmallVector<int, 1> NonceMask; // Just a placeholder.
19903 NonceMask.push_back(0);
19904 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
19905 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
19907 return SDValue(); // This routine will use CombineTo to replace N.
19913 /// PerformTruncateCombine - Converts truncate operation to
19914 /// a sequence of vector shuffle operations.
19915 /// It is possible when we truncate 256-bit vector to 128-bit vector
19916 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
19917 TargetLowering::DAGCombinerInfo &DCI,
19918 const X86Subtarget *Subtarget) {
19922 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
19923 /// specific shuffle of a load can be folded into a single element load.
19924 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
19925 /// shuffles have been customed lowered so we need to handle those here.
19926 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
19927 TargetLowering::DAGCombinerInfo &DCI) {
19928 if (DCI.isBeforeLegalizeOps())
19931 SDValue InVec = N->getOperand(0);
19932 SDValue EltNo = N->getOperand(1);
19934 if (!isa<ConstantSDNode>(EltNo))
19937 EVT VT = InVec.getValueType();
19939 bool HasShuffleIntoBitcast = false;
19940 if (InVec.getOpcode() == ISD::BITCAST) {
19941 // Don't duplicate a load with other uses.
19942 if (!InVec.hasOneUse())
19944 EVT BCVT = InVec.getOperand(0).getValueType();
19945 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
19947 InVec = InVec.getOperand(0);
19948 HasShuffleIntoBitcast = true;
19951 if (!isTargetShuffle(InVec.getOpcode()))
19954 // Don't duplicate a load with other uses.
19955 if (!InVec.hasOneUse())
19958 SmallVector<int, 16> ShuffleMask;
19960 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
19964 // Select the input vector, guarding against out of range extract vector.
19965 unsigned NumElems = VT.getVectorNumElements();
19966 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
19967 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
19968 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
19969 : InVec.getOperand(1);
19971 // If inputs to shuffle are the same for both ops, then allow 2 uses
19972 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
19974 if (LdNode.getOpcode() == ISD::BITCAST) {
19975 // Don't duplicate a load with other uses.
19976 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
19979 AllowedUses = 1; // only allow 1 load use if we have a bitcast
19980 LdNode = LdNode.getOperand(0);
19983 if (!ISD::isNormalLoad(LdNode.getNode()))
19986 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
19988 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
19991 if (HasShuffleIntoBitcast) {
19992 // If there's a bitcast before the shuffle, check if the load type and
19993 // alignment is valid.
19994 unsigned Align = LN0->getAlignment();
19995 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19996 unsigned NewAlign = TLI.getDataLayout()->
19997 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
19999 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
20003 // All checks match so transform back to vector_shuffle so that DAG combiner
20004 // can finish the job
20007 // Create shuffle node taking into account the case that its a unary shuffle
20008 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
20009 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
20010 InVec.getOperand(0), Shuffle,
20012 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
20013 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20017 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20018 /// generation and convert it from being a bunch of shuffles and extracts
20019 /// to a simple store and scalar loads to extract the elements.
20020 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20021 TargetLowering::DAGCombinerInfo &DCI) {
20022 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20023 if (NewOp.getNode())
20026 SDValue InputVector = N->getOperand(0);
20028 // Detect whether we are trying to convert from mmx to i32 and the bitcast
20029 // from mmx to v2i32 has a single usage.
20030 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
20031 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
20032 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
20033 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20034 N->getValueType(0),
20035 InputVector.getNode()->getOperand(0));
20037 // Only operate on vectors of 4 elements, where the alternative shuffling
20038 // gets to be more expensive.
20039 if (InputVector.getValueType() != MVT::v4i32)
20042 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20043 // single use which is a sign-extend or zero-extend, and all elements are
20045 SmallVector<SDNode *, 4> Uses;
20046 unsigned ExtractedElements = 0;
20047 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20048 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20049 if (UI.getUse().getResNo() != InputVector.getResNo())
20052 SDNode *Extract = *UI;
20053 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20056 if (Extract->getValueType(0) != MVT::i32)
20058 if (!Extract->hasOneUse())
20060 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20061 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20063 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20066 // Record which element was extracted.
20067 ExtractedElements |=
20068 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20070 Uses.push_back(Extract);
20073 // If not all the elements were used, this may not be worthwhile.
20074 if (ExtractedElements != 15)
20077 // Ok, we've now decided to do the transformation.
20078 SDLoc dl(InputVector);
20080 // Store the value to a temporary stack slot.
20081 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20082 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20083 MachinePointerInfo(), false, false, 0);
20085 // Replace each use (extract) with a load of the appropriate element.
20086 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20087 UE = Uses.end(); UI != UE; ++UI) {
20088 SDNode *Extract = *UI;
20090 // cOMpute the element's address.
20091 SDValue Idx = Extract->getOperand(1);
20093 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
20094 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
20095 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20096 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20098 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20099 StackPtr, OffsetVal);
20101 // Load the scalar.
20102 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
20103 ScalarAddr, MachinePointerInfo(),
20104 false, false, false, 0);
20106 // Replace the exact with the load.
20107 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
20110 // The replacement was made in place; don't return anything.
20114 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20115 static std::pair<unsigned, bool>
20116 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20117 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20118 if (!VT.isVector())
20119 return std::make_pair(0, false);
20121 bool NeedSplit = false;
20122 switch (VT.getSimpleVT().SimpleTy) {
20123 default: return std::make_pair(0, false);
20127 if (!Subtarget->hasAVX2())
20129 if (!Subtarget->hasAVX())
20130 return std::make_pair(0, false);
20135 if (!Subtarget->hasSSE2())
20136 return std::make_pair(0, false);
20139 // SSE2 has only a small subset of the operations.
20140 bool hasUnsigned = Subtarget->hasSSE41() ||
20141 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20142 bool hasSigned = Subtarget->hasSSE41() ||
20143 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20145 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20148 // Check for x CC y ? x : y.
20149 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20150 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20155 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20158 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20161 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20164 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20166 // Check for x CC y ? y : x -- a min/max with reversed arms.
20167 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20168 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20173 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20176 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20179 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20182 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20186 return std::make_pair(Opc, NeedSplit);
20190 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20191 const X86Subtarget *Subtarget) {
20193 SDValue Cond = N->getOperand(0);
20194 SDValue LHS = N->getOperand(1);
20195 SDValue RHS = N->getOperand(2);
20197 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20198 SDValue CondSrc = Cond->getOperand(0);
20199 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20200 Cond = CondSrc->getOperand(0);
20203 MVT VT = N->getSimpleValueType(0);
20204 MVT EltVT = VT.getVectorElementType();
20205 unsigned NumElems = VT.getVectorNumElements();
20206 // There is no blend with immediate in AVX-512.
20207 if (VT.is512BitVector())
20210 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
20212 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
20215 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20218 unsigned MaskValue = 0;
20219 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20222 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20223 for (unsigned i = 0; i < NumElems; ++i) {
20224 // Be sure we emit undef where we can.
20225 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20226 ShuffleMask[i] = -1;
20228 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20231 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20234 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20236 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20237 TargetLowering::DAGCombinerInfo &DCI,
20238 const X86Subtarget *Subtarget) {
20240 SDValue Cond = N->getOperand(0);
20241 // Get the LHS/RHS of the select.
20242 SDValue LHS = N->getOperand(1);
20243 SDValue RHS = N->getOperand(2);
20244 EVT VT = LHS.getValueType();
20245 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20247 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20248 // instructions match the semantics of the common C idiom x<y?x:y but not
20249 // x<=y?x:y, because of how they handle negative zero (which can be
20250 // ignored in unsafe-math mode).
20251 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20252 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
20253 (Subtarget->hasSSE2() ||
20254 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20255 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20257 unsigned Opcode = 0;
20258 // Check for x CC y ? x : y.
20259 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20260 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20264 // Converting this to a min would handle NaNs incorrectly, and swapping
20265 // the operands would cause it to handle comparisons between positive
20266 // and negative zero incorrectly.
20267 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20268 if (!DAG.getTarget().Options.UnsafeFPMath &&
20269 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20271 std::swap(LHS, RHS);
20273 Opcode = X86ISD::FMIN;
20276 // Converting this to a min would handle comparisons between positive
20277 // and negative zero incorrectly.
20278 if (!DAG.getTarget().Options.UnsafeFPMath &&
20279 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20281 Opcode = X86ISD::FMIN;
20284 // Converting this to a min would handle both negative zeros and NaNs
20285 // incorrectly, but we can swap the operands to fix both.
20286 std::swap(LHS, RHS);
20290 Opcode = X86ISD::FMIN;
20294 // Converting this to a max would handle comparisons between positive
20295 // and negative zero incorrectly.
20296 if (!DAG.getTarget().Options.UnsafeFPMath &&
20297 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20299 Opcode = X86ISD::FMAX;
20302 // Converting this to a max would handle NaNs incorrectly, and swapping
20303 // the operands would cause it to handle comparisons between positive
20304 // and negative zero incorrectly.
20305 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20306 if (!DAG.getTarget().Options.UnsafeFPMath &&
20307 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20309 std::swap(LHS, RHS);
20311 Opcode = X86ISD::FMAX;
20314 // Converting this to a max would handle both negative zeros and NaNs
20315 // incorrectly, but we can swap the operands to fix both.
20316 std::swap(LHS, RHS);
20320 Opcode = X86ISD::FMAX;
20323 // Check for x CC y ? y : x -- a min/max with reversed arms.
20324 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20325 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20329 // Converting this to a min would handle comparisons between positive
20330 // and negative zero incorrectly, and swapping the operands would
20331 // cause it to handle NaNs incorrectly.
20332 if (!DAG.getTarget().Options.UnsafeFPMath &&
20333 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20334 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20336 std::swap(LHS, RHS);
20338 Opcode = X86ISD::FMIN;
20341 // Converting this to a min would handle NaNs incorrectly.
20342 if (!DAG.getTarget().Options.UnsafeFPMath &&
20343 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20345 Opcode = X86ISD::FMIN;
20348 // Converting this to a min would handle both negative zeros and NaNs
20349 // incorrectly, but we can swap the operands to fix both.
20350 std::swap(LHS, RHS);
20354 Opcode = X86ISD::FMIN;
20358 // Converting this to a max would handle NaNs incorrectly.
20359 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20361 Opcode = X86ISD::FMAX;
20364 // Converting this to a max would handle comparisons between positive
20365 // and negative zero incorrectly, and swapping the operands would
20366 // cause it to handle NaNs incorrectly.
20367 if (!DAG.getTarget().Options.UnsafeFPMath &&
20368 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20369 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20371 std::swap(LHS, RHS);
20373 Opcode = X86ISD::FMAX;
20376 // Converting this to a max would handle both negative zeros and NaNs
20377 // incorrectly, but we can swap the operands to fix both.
20378 std::swap(LHS, RHS);
20382 Opcode = X86ISD::FMAX;
20388 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20391 EVT CondVT = Cond.getValueType();
20392 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20393 CondVT.getVectorElementType() == MVT::i1) {
20394 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20395 // lowering on AVX-512. In this case we convert it to
20396 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20397 // The same situation for all 128 and 256-bit vectors of i8 and i16
20398 EVT OpVT = LHS.getValueType();
20399 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20400 (OpVT.getVectorElementType() == MVT::i8 ||
20401 OpVT.getVectorElementType() == MVT::i16)) {
20402 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20403 DCI.AddToWorklist(Cond.getNode());
20404 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20407 // If this is a select between two integer constants, try to do some
20409 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20410 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20411 // Don't do this for crazy integer types.
20412 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20413 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20414 // so that TrueC (the true value) is larger than FalseC.
20415 bool NeedsCondInvert = false;
20417 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20418 // Efficiently invertible.
20419 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20420 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20421 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20422 NeedsCondInvert = true;
20423 std::swap(TrueC, FalseC);
20426 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20427 if (FalseC->getAPIntValue() == 0 &&
20428 TrueC->getAPIntValue().isPowerOf2()) {
20429 if (NeedsCondInvert) // Invert the condition if needed.
20430 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20431 DAG.getConstant(1, Cond.getValueType()));
20433 // Zero extend the condition if needed.
20434 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20436 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20437 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20438 DAG.getConstant(ShAmt, MVT::i8));
20441 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20442 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20443 if (NeedsCondInvert) // Invert the condition if needed.
20444 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20445 DAG.getConstant(1, Cond.getValueType()));
20447 // Zero extend the condition if needed.
20448 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20449 FalseC->getValueType(0), Cond);
20450 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20451 SDValue(FalseC, 0));
20454 // Optimize cases that will turn into an LEA instruction. This requires
20455 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20456 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20457 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20458 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20460 bool isFastMultiplier = false;
20462 switch ((unsigned char)Diff) {
20464 case 1: // result = add base, cond
20465 case 2: // result = lea base( , cond*2)
20466 case 3: // result = lea base(cond, cond*2)
20467 case 4: // result = lea base( , cond*4)
20468 case 5: // result = lea base(cond, cond*4)
20469 case 8: // result = lea base( , cond*8)
20470 case 9: // result = lea base(cond, cond*8)
20471 isFastMultiplier = true;
20476 if (isFastMultiplier) {
20477 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20478 if (NeedsCondInvert) // Invert the condition if needed.
20479 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20480 DAG.getConstant(1, Cond.getValueType()));
20482 // Zero extend the condition if needed.
20483 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20485 // Scale the condition by the difference.
20487 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20488 DAG.getConstant(Diff, Cond.getValueType()));
20490 // Add the base if non-zero.
20491 if (FalseC->getAPIntValue() != 0)
20492 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20493 SDValue(FalseC, 0));
20500 // Canonicalize max and min:
20501 // (x > y) ? x : y -> (x >= y) ? x : y
20502 // (x < y) ? x : y -> (x <= y) ? x : y
20503 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
20504 // the need for an extra compare
20505 // against zero. e.g.
20506 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
20508 // testl %edi, %edi
20510 // cmovgl %edi, %eax
20514 // cmovsl %eax, %edi
20515 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
20516 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20517 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20518 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20523 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
20524 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
20525 Cond.getOperand(0), Cond.getOperand(1), NewCC);
20526 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
20531 // Early exit check
20532 if (!TLI.isTypeLegal(VT))
20535 // Match VSELECTs into subs with unsigned saturation.
20536 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20537 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
20538 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
20539 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
20540 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20542 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
20543 // left side invert the predicate to simplify logic below.
20545 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
20547 CC = ISD::getSetCCInverse(CC, true);
20548 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
20552 if (Other.getNode() && Other->getNumOperands() == 2 &&
20553 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
20554 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
20555 SDValue CondRHS = Cond->getOperand(1);
20557 // Look for a general sub with unsigned saturation first.
20558 // x >= y ? x-y : 0 --> subus x, y
20559 // x > y ? x-y : 0 --> subus x, y
20560 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
20561 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
20562 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
20564 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
20565 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
20566 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
20567 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
20568 // If the RHS is a constant we have to reverse the const
20569 // canonicalization.
20570 // x > C-1 ? x+-C : 0 --> subus x, C
20571 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
20572 CondRHSConst->getAPIntValue() ==
20573 (-OpRHSConst->getAPIntValue() - 1))
20574 return DAG.getNode(
20575 X86ISD::SUBUS, DL, VT, OpLHS,
20576 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
20578 // Another special case: If C was a sign bit, the sub has been
20579 // canonicalized into a xor.
20580 // FIXME: Would it be better to use computeKnownBits to determine
20581 // whether it's safe to decanonicalize the xor?
20582 // x s< 0 ? x^C : 0 --> subus x, C
20583 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
20584 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
20585 OpRHSConst->getAPIntValue().isSignBit())
20586 // Note that we have to rebuild the RHS constant here to ensure we
20587 // don't rely on particular values of undef lanes.
20588 return DAG.getNode(
20589 X86ISD::SUBUS, DL, VT, OpLHS,
20590 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
20595 // Try to match a min/max vector operation.
20596 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
20597 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
20598 unsigned Opc = ret.first;
20599 bool NeedSplit = ret.second;
20601 if (Opc && NeedSplit) {
20602 unsigned NumElems = VT.getVectorNumElements();
20603 // Extract the LHS vectors
20604 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
20605 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
20607 // Extract the RHS vectors
20608 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
20609 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
20611 // Create min/max for each subvector
20612 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
20613 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
20615 // Merge the result
20616 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
20618 return DAG.getNode(Opc, DL, VT, LHS, RHS);
20621 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
20622 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20623 // Check if SETCC has already been promoted
20624 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
20625 // Check that condition value type matches vselect operand type
20628 assert(Cond.getValueType().isVector() &&
20629 "vector select expects a vector selector!");
20631 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
20632 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
20634 if (!TValIsAllOnes && !FValIsAllZeros) {
20635 // Try invert the condition if true value is not all 1s and false value
20637 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
20638 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
20640 if (TValIsAllZeros || FValIsAllOnes) {
20641 SDValue CC = Cond.getOperand(2);
20642 ISD::CondCode NewCC =
20643 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
20644 Cond.getOperand(0).getValueType().isInteger());
20645 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
20646 std::swap(LHS, RHS);
20647 TValIsAllOnes = FValIsAllOnes;
20648 FValIsAllZeros = TValIsAllZeros;
20652 if (TValIsAllOnes || FValIsAllZeros) {
20655 if (TValIsAllOnes && FValIsAllZeros)
20657 else if (TValIsAllOnes)
20658 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
20659 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
20660 else if (FValIsAllZeros)
20661 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
20662 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
20664 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
20668 // Try to fold this VSELECT into a MOVSS/MOVSD
20669 if (N->getOpcode() == ISD::VSELECT &&
20670 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
20671 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
20672 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
20673 bool CanFold = false;
20674 unsigned NumElems = Cond.getNumOperands();
20678 if (isZero(Cond.getOperand(0))) {
20681 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
20682 // fold (vselect <0,-1> -> (movsd A, B)
20683 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20684 CanFold = isAllOnes(Cond.getOperand(i));
20685 } else if (isAllOnes(Cond.getOperand(0))) {
20689 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
20690 // fold (vselect <-1,0> -> (movsd B, A)
20691 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20692 CanFold = isZero(Cond.getOperand(i));
20696 if (VT == MVT::v4i32 || VT == MVT::v4f32)
20697 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
20698 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
20701 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
20702 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
20703 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
20704 // (v2i64 (bitcast B)))))
20706 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
20707 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
20708 // (v2f64 (bitcast B)))))
20710 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
20711 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
20712 // (v2i64 (bitcast A)))))
20714 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
20715 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
20716 // (v2f64 (bitcast A)))))
20718 CanFold = (isZero(Cond.getOperand(0)) &&
20719 isZero(Cond.getOperand(1)) &&
20720 isAllOnes(Cond.getOperand(2)) &&
20721 isAllOnes(Cond.getOperand(3)));
20723 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
20724 isAllOnes(Cond.getOperand(1)) &&
20725 isZero(Cond.getOperand(2)) &&
20726 isZero(Cond.getOperand(3))) {
20728 std::swap(LHS, RHS);
20732 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
20733 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
20734 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
20735 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
20737 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
20743 // If we know that this node is legal then we know that it is going to be
20744 // matched by one of the SSE/AVX BLEND instructions. These instructions only
20745 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
20746 // to simplify previous instructions.
20747 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
20748 !DCI.isBeforeLegalize() &&
20749 // We explicitly check against v8i16 and v16i16 because, although
20750 // they're marked as Custom, they might only be legal when Cond is a
20751 // build_vector of constants. This will be taken care in a later
20753 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
20754 VT != MVT::v8i16)) {
20755 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
20757 // Don't optimize vector selects that map to mask-registers.
20761 // Check all uses of that condition operand to check whether it will be
20762 // consumed by non-BLEND instructions, which may depend on all bits are set
20764 for (SDNode::use_iterator I = Cond->use_begin(),
20765 E = Cond->use_end(); I != E; ++I)
20766 if (I->getOpcode() != ISD::VSELECT)
20767 // TODO: Add other opcodes eventually lowered into BLEND.
20770 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
20771 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
20773 APInt KnownZero, KnownOne;
20774 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
20775 DCI.isBeforeLegalizeOps());
20776 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
20777 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
20778 DCI.CommitTargetLoweringOpt(TLO);
20781 // We should generate an X86ISD::BLENDI from a vselect if its argument
20782 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
20783 // constants. This specific pattern gets generated when we split a
20784 // selector for a 512 bit vector in a machine without AVX512 (but with
20785 // 256-bit vectors), during legalization:
20787 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20789 // Iff we find this pattern and the build_vectors are built from
20790 // constants, we translate the vselect into a shuffle_vector that we
20791 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
20792 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
20793 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
20794 if (Shuffle.getNode())
20801 // Check whether a boolean test is testing a boolean value generated by
20802 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
20805 // Simplify the following patterns:
20806 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
20807 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
20808 // to (Op EFLAGS Cond)
20810 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
20811 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
20812 // to (Op EFLAGS !Cond)
20814 // where Op could be BRCOND or CMOV.
20816 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
20817 // Quit if not CMP and SUB with its value result used.
20818 if (Cmp.getOpcode() != X86ISD::CMP &&
20819 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
20822 // Quit if not used as a boolean value.
20823 if (CC != X86::COND_E && CC != X86::COND_NE)
20826 // Check CMP operands. One of them should be 0 or 1 and the other should be
20827 // an SetCC or extended from it.
20828 SDValue Op1 = Cmp.getOperand(0);
20829 SDValue Op2 = Cmp.getOperand(1);
20832 const ConstantSDNode* C = nullptr;
20833 bool needOppositeCond = (CC == X86::COND_E);
20834 bool checkAgainstTrue = false; // Is it a comparison against 1?
20836 if ((C = dyn_cast<ConstantSDNode>(Op1)))
20838 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
20840 else // Quit if all operands are not constants.
20843 if (C->getZExtValue() == 1) {
20844 needOppositeCond = !needOppositeCond;
20845 checkAgainstTrue = true;
20846 } else if (C->getZExtValue() != 0)
20847 // Quit if the constant is neither 0 or 1.
20850 bool truncatedToBoolWithAnd = false;
20851 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
20852 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
20853 SetCC.getOpcode() == ISD::TRUNCATE ||
20854 SetCC.getOpcode() == ISD::AND) {
20855 if (SetCC.getOpcode() == ISD::AND) {
20857 ConstantSDNode *CS;
20858 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
20859 CS->getZExtValue() == 1)
20861 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
20862 CS->getZExtValue() == 1)
20866 SetCC = SetCC.getOperand(OpIdx);
20867 truncatedToBoolWithAnd = true;
20869 SetCC = SetCC.getOperand(0);
20872 switch (SetCC.getOpcode()) {
20873 case X86ISD::SETCC_CARRY:
20874 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
20875 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
20876 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
20877 // truncated to i1 using 'and'.
20878 if (checkAgainstTrue && !truncatedToBoolWithAnd)
20880 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
20881 "Invalid use of SETCC_CARRY!");
20883 case X86ISD::SETCC:
20884 // Set the condition code or opposite one if necessary.
20885 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
20886 if (needOppositeCond)
20887 CC = X86::GetOppositeBranchCondition(CC);
20888 return SetCC.getOperand(1);
20889 case X86ISD::CMOV: {
20890 // Check whether false/true value has canonical one, i.e. 0 or 1.
20891 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
20892 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
20893 // Quit if true value is not a constant.
20896 // Quit if false value is not a constant.
20898 SDValue Op = SetCC.getOperand(0);
20899 // Skip 'zext' or 'trunc' node.
20900 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
20901 Op.getOpcode() == ISD::TRUNCATE)
20902 Op = Op.getOperand(0);
20903 // A special case for rdrand/rdseed, where 0 is set if false cond is
20905 if ((Op.getOpcode() != X86ISD::RDRAND &&
20906 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
20909 // Quit if false value is not the constant 0 or 1.
20910 bool FValIsFalse = true;
20911 if (FVal && FVal->getZExtValue() != 0) {
20912 if (FVal->getZExtValue() != 1)
20914 // If FVal is 1, opposite cond is needed.
20915 needOppositeCond = !needOppositeCond;
20916 FValIsFalse = false;
20918 // Quit if TVal is not the constant opposite of FVal.
20919 if (FValIsFalse && TVal->getZExtValue() != 1)
20921 if (!FValIsFalse && TVal->getZExtValue() != 0)
20923 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
20924 if (needOppositeCond)
20925 CC = X86::GetOppositeBranchCondition(CC);
20926 return SetCC.getOperand(3);
20933 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
20934 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
20935 TargetLowering::DAGCombinerInfo &DCI,
20936 const X86Subtarget *Subtarget) {
20939 // If the flag operand isn't dead, don't touch this CMOV.
20940 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
20943 SDValue FalseOp = N->getOperand(0);
20944 SDValue TrueOp = N->getOperand(1);
20945 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
20946 SDValue Cond = N->getOperand(3);
20948 if (CC == X86::COND_E || CC == X86::COND_NE) {
20949 switch (Cond.getOpcode()) {
20953 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
20954 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
20955 return (CC == X86::COND_E) ? FalseOp : TrueOp;
20961 Flags = checkBoolTestSetCCCombine(Cond, CC);
20962 if (Flags.getNode() &&
20963 // Extra check as FCMOV only supports a subset of X86 cond.
20964 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
20965 SDValue Ops[] = { FalseOp, TrueOp,
20966 DAG.getConstant(CC, MVT::i8), Flags };
20967 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
20970 // If this is a select between two integer constants, try to do some
20971 // optimizations. Note that the operands are ordered the opposite of SELECT
20973 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
20974 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
20975 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
20976 // larger than FalseC (the false value).
20977 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
20978 CC = X86::GetOppositeBranchCondition(CC);
20979 std::swap(TrueC, FalseC);
20980 std::swap(TrueOp, FalseOp);
20983 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
20984 // This is efficient for any integer data type (including i8/i16) and
20986 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
20987 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20988 DAG.getConstant(CC, MVT::i8), Cond);
20990 // Zero extend the condition if needed.
20991 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
20993 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20994 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
20995 DAG.getConstant(ShAmt, MVT::i8));
20996 if (N->getNumValues() == 2) // Dead flag value?
20997 return DCI.CombineTo(N, Cond, SDValue());
21001 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21002 // for any integer data type, including i8/i16.
21003 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21004 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21005 DAG.getConstant(CC, MVT::i8), Cond);
21007 // Zero extend the condition if needed.
21008 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21009 FalseC->getValueType(0), Cond);
21010 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21011 SDValue(FalseC, 0));
21013 if (N->getNumValues() == 2) // Dead flag value?
21014 return DCI.CombineTo(N, Cond, SDValue());
21018 // Optimize cases that will turn into an LEA instruction. This requires
21019 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21020 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21021 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21022 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21024 bool isFastMultiplier = false;
21026 switch ((unsigned char)Diff) {
21028 case 1: // result = add base, cond
21029 case 2: // result = lea base( , cond*2)
21030 case 3: // result = lea base(cond, cond*2)
21031 case 4: // result = lea base( , cond*4)
21032 case 5: // result = lea base(cond, cond*4)
21033 case 8: // result = lea base( , cond*8)
21034 case 9: // result = lea base(cond, cond*8)
21035 isFastMultiplier = true;
21040 if (isFastMultiplier) {
21041 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21042 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21043 DAG.getConstant(CC, MVT::i8), Cond);
21044 // Zero extend the condition if needed.
21045 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21047 // Scale the condition by the difference.
21049 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21050 DAG.getConstant(Diff, Cond.getValueType()));
21052 // Add the base if non-zero.
21053 if (FalseC->getAPIntValue() != 0)
21054 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21055 SDValue(FalseC, 0));
21056 if (N->getNumValues() == 2) // Dead flag value?
21057 return DCI.CombineTo(N, Cond, SDValue());
21064 // Handle these cases:
21065 // (select (x != c), e, c) -> select (x != c), e, x),
21066 // (select (x == c), c, e) -> select (x == c), x, e)
21067 // where the c is an integer constant, and the "select" is the combination
21068 // of CMOV and CMP.
21070 // The rationale for this change is that the conditional-move from a constant
21071 // needs two instructions, however, conditional-move from a register needs
21072 // only one instruction.
21074 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21075 // some instruction-combining opportunities. This opt needs to be
21076 // postponed as late as possible.
21078 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21079 // the DCI.xxxx conditions are provided to postpone the optimization as
21080 // late as possible.
21082 ConstantSDNode *CmpAgainst = nullptr;
21083 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21084 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21085 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21087 if (CC == X86::COND_NE &&
21088 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21089 CC = X86::GetOppositeBranchCondition(CC);
21090 std::swap(TrueOp, FalseOp);
21093 if (CC == X86::COND_E &&
21094 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21095 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21096 DAG.getConstant(CC, MVT::i8), Cond };
21097 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21105 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21106 const X86Subtarget *Subtarget) {
21107 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21109 default: return SDValue();
21110 // SSE/AVX/AVX2 blend intrinsics.
21111 case Intrinsic::x86_avx2_pblendvb:
21112 case Intrinsic::x86_avx2_pblendw:
21113 case Intrinsic::x86_avx2_pblendd_128:
21114 case Intrinsic::x86_avx2_pblendd_256:
21115 // Don't try to simplify this intrinsic if we don't have AVX2.
21116 if (!Subtarget->hasAVX2())
21119 case Intrinsic::x86_avx_blend_pd_256:
21120 case Intrinsic::x86_avx_blend_ps_256:
21121 case Intrinsic::x86_avx_blendv_pd_256:
21122 case Intrinsic::x86_avx_blendv_ps_256:
21123 // Don't try to simplify this intrinsic if we don't have AVX.
21124 if (!Subtarget->hasAVX())
21127 case Intrinsic::x86_sse41_pblendw:
21128 case Intrinsic::x86_sse41_blendpd:
21129 case Intrinsic::x86_sse41_blendps:
21130 case Intrinsic::x86_sse41_blendvps:
21131 case Intrinsic::x86_sse41_blendvpd:
21132 case Intrinsic::x86_sse41_pblendvb: {
21133 SDValue Op0 = N->getOperand(1);
21134 SDValue Op1 = N->getOperand(2);
21135 SDValue Mask = N->getOperand(3);
21137 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21138 if (!Subtarget->hasSSE41())
21141 // fold (blend A, A, Mask) -> A
21144 // fold (blend A, B, allZeros) -> A
21145 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21147 // fold (blend A, B, allOnes) -> B
21148 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21151 // Simplify the case where the mask is a constant i32 value.
21152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21153 if (C->isNullValue())
21155 if (C->isAllOnesValue())
21162 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21163 case Intrinsic::x86_sse2_psrai_w:
21164 case Intrinsic::x86_sse2_psrai_d:
21165 case Intrinsic::x86_avx2_psrai_w:
21166 case Intrinsic::x86_avx2_psrai_d:
21167 case Intrinsic::x86_sse2_psra_w:
21168 case Intrinsic::x86_sse2_psra_d:
21169 case Intrinsic::x86_avx2_psra_w:
21170 case Intrinsic::x86_avx2_psra_d: {
21171 SDValue Op0 = N->getOperand(1);
21172 SDValue Op1 = N->getOperand(2);
21173 EVT VT = Op0.getValueType();
21174 assert(VT.isVector() && "Expected a vector type!");
21176 if (isa<BuildVectorSDNode>(Op1))
21177 Op1 = Op1.getOperand(0);
21179 if (!isa<ConstantSDNode>(Op1))
21182 EVT SVT = VT.getVectorElementType();
21183 unsigned SVTBits = SVT.getSizeInBits();
21185 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21186 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21187 uint64_t ShAmt = C.getZExtValue();
21189 // Don't try to convert this shift into a ISD::SRA if the shift
21190 // count is bigger than or equal to the element size.
21191 if (ShAmt >= SVTBits)
21194 // Trivial case: if the shift count is zero, then fold this
21195 // into the first operand.
21199 // Replace this packed shift intrinsic with a target independent
21201 SDValue Splat = DAG.getConstant(C, VT);
21202 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21207 /// PerformMulCombine - Optimize a single multiply with constant into two
21208 /// in order to implement it with two cheaper instructions, e.g.
21209 /// LEA + SHL, LEA + LEA.
21210 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21211 TargetLowering::DAGCombinerInfo &DCI) {
21212 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21215 EVT VT = N->getValueType(0);
21216 if (VT != MVT::i64)
21219 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21222 uint64_t MulAmt = C->getZExtValue();
21223 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21226 uint64_t MulAmt1 = 0;
21227 uint64_t MulAmt2 = 0;
21228 if ((MulAmt % 9) == 0) {
21230 MulAmt2 = MulAmt / 9;
21231 } else if ((MulAmt % 5) == 0) {
21233 MulAmt2 = MulAmt / 5;
21234 } else if ((MulAmt % 3) == 0) {
21236 MulAmt2 = MulAmt / 3;
21239 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21242 if (isPowerOf2_64(MulAmt2) &&
21243 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21244 // If second multiplifer is pow2, issue it first. We want the multiply by
21245 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21247 std::swap(MulAmt1, MulAmt2);
21250 if (isPowerOf2_64(MulAmt1))
21251 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21252 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21254 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21255 DAG.getConstant(MulAmt1, VT));
21257 if (isPowerOf2_64(MulAmt2))
21258 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21259 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21261 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21262 DAG.getConstant(MulAmt2, VT));
21264 // Do not add new nodes to DAG combiner worklist.
21265 DCI.CombineTo(N, NewMul, false);
21270 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21271 SDValue N0 = N->getOperand(0);
21272 SDValue N1 = N->getOperand(1);
21273 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21274 EVT VT = N0.getValueType();
21276 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21277 // since the result of setcc_c is all zero's or all ones.
21278 if (VT.isInteger() && !VT.isVector() &&
21279 N1C && N0.getOpcode() == ISD::AND &&
21280 N0.getOperand(1).getOpcode() == ISD::Constant) {
21281 SDValue N00 = N0.getOperand(0);
21282 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21283 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21284 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21285 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21286 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21287 APInt ShAmt = N1C->getAPIntValue();
21288 Mask = Mask.shl(ShAmt);
21290 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21291 N00, DAG.getConstant(Mask, VT));
21295 // Hardware support for vector shifts is sparse which makes us scalarize the
21296 // vector operations in many cases. Also, on sandybridge ADD is faster than
21298 // (shl V, 1) -> add V,V
21299 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21300 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21301 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21302 // We shift all of the values by one. In many cases we do not have
21303 // hardware support for this operation. This is better expressed as an ADD
21305 if (N1SplatC->getZExtValue() == 1)
21306 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21312 /// \brief Returns a vector of 0s if the node in input is a vector logical
21313 /// shift by a constant amount which is known to be bigger than or equal
21314 /// to the vector element size in bits.
21315 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21316 const X86Subtarget *Subtarget) {
21317 EVT VT = N->getValueType(0);
21319 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21320 (!Subtarget->hasInt256() ||
21321 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21324 SDValue Amt = N->getOperand(1);
21326 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21327 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21328 APInt ShiftAmt = AmtSplat->getAPIntValue();
21329 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21331 // SSE2/AVX2 logical shifts always return a vector of 0s
21332 // if the shift amount is bigger than or equal to
21333 // the element size. The constant shift amount will be
21334 // encoded as a 8-bit immediate.
21335 if (ShiftAmt.trunc(8).uge(MaxAmount))
21336 return getZeroVector(VT, Subtarget, DAG, DL);
21342 /// PerformShiftCombine - Combine shifts.
21343 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21344 TargetLowering::DAGCombinerInfo &DCI,
21345 const X86Subtarget *Subtarget) {
21346 if (N->getOpcode() == ISD::SHL) {
21347 SDValue V = PerformSHLCombine(N, DAG);
21348 if (V.getNode()) return V;
21351 if (N->getOpcode() != ISD::SRA) {
21352 // Try to fold this logical shift into a zero vector.
21353 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21354 if (V.getNode()) return V;
21360 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21361 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21362 // and friends. Likewise for OR -> CMPNEQSS.
21363 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21364 TargetLowering::DAGCombinerInfo &DCI,
21365 const X86Subtarget *Subtarget) {
21368 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21369 // we're requiring SSE2 for both.
21370 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21371 SDValue N0 = N->getOperand(0);
21372 SDValue N1 = N->getOperand(1);
21373 SDValue CMP0 = N0->getOperand(1);
21374 SDValue CMP1 = N1->getOperand(1);
21377 // The SETCCs should both refer to the same CMP.
21378 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21381 SDValue CMP00 = CMP0->getOperand(0);
21382 SDValue CMP01 = CMP0->getOperand(1);
21383 EVT VT = CMP00.getValueType();
21385 if (VT == MVT::f32 || VT == MVT::f64) {
21386 bool ExpectingFlags = false;
21387 // Check for any users that want flags:
21388 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21389 !ExpectingFlags && UI != UE; ++UI)
21390 switch (UI->getOpcode()) {
21395 ExpectingFlags = true;
21397 case ISD::CopyToReg:
21398 case ISD::SIGN_EXTEND:
21399 case ISD::ZERO_EXTEND:
21400 case ISD::ANY_EXTEND:
21404 if (!ExpectingFlags) {
21405 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21406 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21408 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21409 X86::CondCode tmp = cc0;
21414 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21415 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
21416 // FIXME: need symbolic constants for these magic numbers.
21417 // See X86ATTInstPrinter.cpp:printSSECC().
21418 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
21419 if (Subtarget->hasAVX512()) {
21420 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
21421 CMP01, DAG.getConstant(x86cc, MVT::i8));
21422 if (N->getValueType(0) != MVT::i1)
21423 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
21427 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
21428 CMP00.getValueType(), CMP00, CMP01,
21429 DAG.getConstant(x86cc, MVT::i8));
21431 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
21432 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
21434 if (is64BitFP && !Subtarget->is64Bit()) {
21435 // On a 32-bit target, we cannot bitcast the 64-bit float to a
21436 // 64-bit integer, since that's not a legal type. Since
21437 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
21438 // bits, but can do this little dance to extract the lowest 32 bits
21439 // and work with those going forward.
21440 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
21442 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
21444 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
21445 Vector32, DAG.getIntPtrConstant(0));
21449 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
21450 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
21451 DAG.getConstant(1, IntVT));
21452 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
21453 return OneBitOfTruth;
21461 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
21462 /// so it can be folded inside ANDNP.
21463 static bool CanFoldXORWithAllOnes(const SDNode *N) {
21464 EVT VT = N->getValueType(0);
21466 // Match direct AllOnes for 128 and 256-bit vectors
21467 if (ISD::isBuildVectorAllOnes(N))
21470 // Look through a bit convert.
21471 if (N->getOpcode() == ISD::BITCAST)
21472 N = N->getOperand(0).getNode();
21474 // Sometimes the operand may come from a insert_subvector building a 256-bit
21476 if (VT.is256BitVector() &&
21477 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
21478 SDValue V1 = N->getOperand(0);
21479 SDValue V2 = N->getOperand(1);
21481 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
21482 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
21483 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
21484 ISD::isBuildVectorAllOnes(V2.getNode()))
21491 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
21492 // register. In most cases we actually compare or select YMM-sized registers
21493 // and mixing the two types creates horrible code. This method optimizes
21494 // some of the transition sequences.
21495 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
21496 TargetLowering::DAGCombinerInfo &DCI,
21497 const X86Subtarget *Subtarget) {
21498 EVT VT = N->getValueType(0);
21499 if (!VT.is256BitVector())
21502 assert((N->getOpcode() == ISD::ANY_EXTEND ||
21503 N->getOpcode() == ISD::ZERO_EXTEND ||
21504 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
21506 SDValue Narrow = N->getOperand(0);
21507 EVT NarrowVT = Narrow->getValueType(0);
21508 if (!NarrowVT.is128BitVector())
21511 if (Narrow->getOpcode() != ISD::XOR &&
21512 Narrow->getOpcode() != ISD::AND &&
21513 Narrow->getOpcode() != ISD::OR)
21516 SDValue N0 = Narrow->getOperand(0);
21517 SDValue N1 = Narrow->getOperand(1);
21520 // The Left side has to be a trunc.
21521 if (N0.getOpcode() != ISD::TRUNCATE)
21524 // The type of the truncated inputs.
21525 EVT WideVT = N0->getOperand(0)->getValueType(0);
21529 // The right side has to be a 'trunc' or a constant vector.
21530 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
21531 ConstantSDNode *RHSConstSplat = nullptr;
21532 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
21533 RHSConstSplat = RHSBV->getConstantSplatNode();
21534 if (!RHSTrunc && !RHSConstSplat)
21537 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21539 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
21542 // Set N0 and N1 to hold the inputs to the new wide operation.
21543 N0 = N0->getOperand(0);
21544 if (RHSConstSplat) {
21545 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
21546 SDValue(RHSConstSplat, 0));
21547 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
21548 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
21549 } else if (RHSTrunc) {
21550 N1 = N1->getOperand(0);
21553 // Generate the wide operation.
21554 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
21555 unsigned Opcode = N->getOpcode();
21557 case ISD::ANY_EXTEND:
21559 case ISD::ZERO_EXTEND: {
21560 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
21561 APInt Mask = APInt::getAllOnesValue(InBits);
21562 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
21563 return DAG.getNode(ISD::AND, DL, VT,
21564 Op, DAG.getConstant(Mask, VT));
21566 case ISD::SIGN_EXTEND:
21567 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
21568 Op, DAG.getValueType(NarrowVT));
21570 llvm_unreachable("Unexpected opcode");
21574 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
21575 TargetLowering::DAGCombinerInfo &DCI,
21576 const X86Subtarget *Subtarget) {
21577 EVT VT = N->getValueType(0);
21578 if (DCI.isBeforeLegalizeOps())
21581 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21585 // Create BEXTR instructions
21586 // BEXTR is ((X >> imm) & (2**size-1))
21587 if (VT == MVT::i32 || VT == MVT::i64) {
21588 SDValue N0 = N->getOperand(0);
21589 SDValue N1 = N->getOperand(1);
21592 // Check for BEXTR.
21593 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
21594 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
21595 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
21596 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21597 if (MaskNode && ShiftNode) {
21598 uint64_t Mask = MaskNode->getZExtValue();
21599 uint64_t Shift = ShiftNode->getZExtValue();
21600 if (isMask_64(Mask)) {
21601 uint64_t MaskSize = CountPopulation_64(Mask);
21602 if (Shift + MaskSize <= VT.getSizeInBits())
21603 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
21604 DAG.getConstant(Shift | (MaskSize << 8), VT));
21612 // Want to form ANDNP nodes:
21613 // 1) In the hopes of then easily combining them with OR and AND nodes
21614 // to form PBLEND/PSIGN.
21615 // 2) To match ANDN packed intrinsics
21616 if (VT != MVT::v2i64 && VT != MVT::v4i64)
21619 SDValue N0 = N->getOperand(0);
21620 SDValue N1 = N->getOperand(1);
21623 // Check LHS for vnot
21624 if (N0.getOpcode() == ISD::XOR &&
21625 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
21626 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
21627 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
21629 // Check RHS for vnot
21630 if (N1.getOpcode() == ISD::XOR &&
21631 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
21632 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
21633 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
21638 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
21639 TargetLowering::DAGCombinerInfo &DCI,
21640 const X86Subtarget *Subtarget) {
21641 if (DCI.isBeforeLegalizeOps())
21644 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21648 SDValue N0 = N->getOperand(0);
21649 SDValue N1 = N->getOperand(1);
21650 EVT VT = N->getValueType(0);
21652 // look for psign/blend
21653 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
21654 if (!Subtarget->hasSSSE3() ||
21655 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
21658 // Canonicalize pandn to RHS
21659 if (N0.getOpcode() == X86ISD::ANDNP)
21661 // or (and (m, y), (pandn m, x))
21662 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
21663 SDValue Mask = N1.getOperand(0);
21664 SDValue X = N1.getOperand(1);
21666 if (N0.getOperand(0) == Mask)
21667 Y = N0.getOperand(1);
21668 if (N0.getOperand(1) == Mask)
21669 Y = N0.getOperand(0);
21671 // Check to see if the mask appeared in both the AND and ANDNP and
21675 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
21676 // Look through mask bitcast.
21677 if (Mask.getOpcode() == ISD::BITCAST)
21678 Mask = Mask.getOperand(0);
21679 if (X.getOpcode() == ISD::BITCAST)
21680 X = X.getOperand(0);
21681 if (Y.getOpcode() == ISD::BITCAST)
21682 Y = Y.getOperand(0);
21684 EVT MaskVT = Mask.getValueType();
21686 // Validate that the Mask operand is a vector sra node.
21687 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
21688 // there is no psrai.b
21689 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
21690 unsigned SraAmt = ~0;
21691 if (Mask.getOpcode() == ISD::SRA) {
21692 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
21693 if (auto *AmtConst = AmtBV->getConstantSplatNode())
21694 SraAmt = AmtConst->getZExtValue();
21695 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
21696 SDValue SraC = Mask.getOperand(1);
21697 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
21699 if ((SraAmt + 1) != EltBits)
21704 // Now we know we at least have a plendvb with the mask val. See if
21705 // we can form a psignb/w/d.
21706 // psign = x.type == y.type == mask.type && y = sub(0, x);
21707 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
21708 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
21709 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
21710 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
21711 "Unsupported VT for PSIGN");
21712 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
21713 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21715 // PBLENDVB only available on SSE 4.1
21716 if (!Subtarget->hasSSE41())
21719 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
21721 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
21722 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
21723 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
21724 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
21725 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21729 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
21732 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
21733 MachineFunction &MF = DAG.getMachineFunction();
21734 bool OptForSize = MF.getFunction()->getAttributes().
21735 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
21737 // SHLD/SHRD instructions have lower register pressure, but on some
21738 // platforms they have higher latency than the equivalent
21739 // series of shifts/or that would otherwise be generated.
21740 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
21741 // have higher latencies and we are not optimizing for size.
21742 if (!OptForSize && Subtarget->isSHLDSlow())
21745 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
21747 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
21749 if (!N0.hasOneUse() || !N1.hasOneUse())
21752 SDValue ShAmt0 = N0.getOperand(1);
21753 if (ShAmt0.getValueType() != MVT::i8)
21755 SDValue ShAmt1 = N1.getOperand(1);
21756 if (ShAmt1.getValueType() != MVT::i8)
21758 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
21759 ShAmt0 = ShAmt0.getOperand(0);
21760 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
21761 ShAmt1 = ShAmt1.getOperand(0);
21764 unsigned Opc = X86ISD::SHLD;
21765 SDValue Op0 = N0.getOperand(0);
21766 SDValue Op1 = N1.getOperand(0);
21767 if (ShAmt0.getOpcode() == ISD::SUB) {
21768 Opc = X86ISD::SHRD;
21769 std::swap(Op0, Op1);
21770 std::swap(ShAmt0, ShAmt1);
21773 unsigned Bits = VT.getSizeInBits();
21774 if (ShAmt1.getOpcode() == ISD::SUB) {
21775 SDValue Sum = ShAmt1.getOperand(0);
21776 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
21777 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
21778 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
21779 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
21780 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
21781 return DAG.getNode(Opc, DL, VT,
21783 DAG.getNode(ISD::TRUNCATE, DL,
21786 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
21787 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
21789 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
21790 return DAG.getNode(Opc, DL, VT,
21791 N0.getOperand(0), N1.getOperand(0),
21792 DAG.getNode(ISD::TRUNCATE, DL,
21799 // Generate NEG and CMOV for integer abs.
21800 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
21801 EVT VT = N->getValueType(0);
21803 // Since X86 does not have CMOV for 8-bit integer, we don't convert
21804 // 8-bit integer abs to NEG and CMOV.
21805 if (VT.isInteger() && VT.getSizeInBits() == 8)
21808 SDValue N0 = N->getOperand(0);
21809 SDValue N1 = N->getOperand(1);
21812 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
21813 // and change it to SUB and CMOV.
21814 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
21815 N0.getOpcode() == ISD::ADD &&
21816 N0.getOperand(1) == N1 &&
21817 N1.getOpcode() == ISD::SRA &&
21818 N1.getOperand(0) == N0.getOperand(0))
21819 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
21820 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
21821 // Generate SUB & CMOV.
21822 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
21823 DAG.getConstant(0, VT), N0.getOperand(0));
21825 SDValue Ops[] = { N0.getOperand(0), Neg,
21826 DAG.getConstant(X86::COND_GE, MVT::i8),
21827 SDValue(Neg.getNode(), 1) };
21828 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
21833 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
21834 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
21835 TargetLowering::DAGCombinerInfo &DCI,
21836 const X86Subtarget *Subtarget) {
21837 if (DCI.isBeforeLegalizeOps())
21840 if (Subtarget->hasCMov()) {
21841 SDValue RV = performIntegerAbsCombine(N, DAG);
21849 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
21850 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
21851 TargetLowering::DAGCombinerInfo &DCI,
21852 const X86Subtarget *Subtarget) {
21853 LoadSDNode *Ld = cast<LoadSDNode>(N);
21854 EVT RegVT = Ld->getValueType(0);
21855 EVT MemVT = Ld->getMemoryVT();
21857 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21859 // On Sandybridge unaligned 256bit loads are inefficient.
21860 ISD::LoadExtType Ext = Ld->getExtensionType();
21861 unsigned Alignment = Ld->getAlignment();
21862 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
21863 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
21864 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
21865 unsigned NumElems = RegVT.getVectorNumElements();
21869 SDValue Ptr = Ld->getBasePtr();
21870 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
21872 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
21874 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21875 Ld->getPointerInfo(), Ld->isVolatile(),
21876 Ld->isNonTemporal(), Ld->isInvariant(),
21878 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21879 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21880 Ld->getPointerInfo(), Ld->isVolatile(),
21881 Ld->isNonTemporal(), Ld->isInvariant(),
21882 std::min(16U, Alignment));
21883 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21885 Load2.getValue(1));
21887 SDValue NewVec = DAG.getUNDEF(RegVT);
21888 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
21889 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
21890 return DCI.CombineTo(N, NewVec, TF, true);
21896 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
21897 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
21898 const X86Subtarget *Subtarget) {
21899 StoreSDNode *St = cast<StoreSDNode>(N);
21900 EVT VT = St->getValue().getValueType();
21901 EVT StVT = St->getMemoryVT();
21903 SDValue StoredVal = St->getOperand(1);
21904 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21906 // If we are saving a concatenation of two XMM registers, perform two stores.
21907 // On Sandy Bridge, 256-bit memory operations are executed by two
21908 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
21909 // memory operation.
21910 unsigned Alignment = St->getAlignment();
21911 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
21912 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
21913 StVT == VT && !IsAligned) {
21914 unsigned NumElems = VT.getVectorNumElements();
21918 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
21919 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
21921 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
21922 SDValue Ptr0 = St->getBasePtr();
21923 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
21925 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
21926 St->getPointerInfo(), St->isVolatile(),
21927 St->isNonTemporal(), Alignment);
21928 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
21929 St->getPointerInfo(), St->isVolatile(),
21930 St->isNonTemporal(),
21931 std::min(16U, Alignment));
21932 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
21935 // Optimize trunc store (of multiple scalars) to shuffle and store.
21936 // First, pack all of the elements in one place. Next, store to memory
21937 // in fewer chunks.
21938 if (St->isTruncatingStore() && VT.isVector()) {
21939 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21940 unsigned NumElems = VT.getVectorNumElements();
21941 assert(StVT != VT && "Cannot truncate to the same type");
21942 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
21943 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
21945 // From, To sizes and ElemCount must be pow of two
21946 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
21947 // We are going to use the original vector elt for storing.
21948 // Accumulated smaller vector elements must be a multiple of the store size.
21949 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
21951 unsigned SizeRatio = FromSz / ToSz;
21953 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
21955 // Create a type on which we perform the shuffle
21956 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
21957 StVT.getScalarType(), NumElems*SizeRatio);
21959 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
21961 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
21962 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
21963 for (unsigned i = 0; i != NumElems; ++i)
21964 ShuffleVec[i] = i * SizeRatio;
21966 // Can't shuffle using an illegal type.
21967 if (!TLI.isTypeLegal(WideVecVT))
21970 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
21971 DAG.getUNDEF(WideVecVT),
21973 // At this point all of the data is stored at the bottom of the
21974 // register. We now need to save it to mem.
21976 // Find the largest store unit
21977 MVT StoreType = MVT::i8;
21978 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
21979 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
21980 MVT Tp = (MVT::SimpleValueType)tp;
21981 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
21985 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
21986 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
21987 (64 <= NumElems * ToSz))
21988 StoreType = MVT::f64;
21990 // Bitcast the original vector into a vector of store-size units
21991 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
21992 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
21993 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
21994 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
21995 SmallVector<SDValue, 8> Chains;
21996 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
21997 TLI.getPointerTy());
21998 SDValue Ptr = St->getBasePtr();
22000 // Perform one or more big stores into memory.
22001 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22002 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22003 StoreType, ShuffWide,
22004 DAG.getIntPtrConstant(i));
22005 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22006 St->getPointerInfo(), St->isVolatile(),
22007 St->isNonTemporal(), St->getAlignment());
22008 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22009 Chains.push_back(Ch);
22012 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22015 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22016 // the FP state in cases where an emms may be missing.
22017 // A preferable solution to the general problem is to figure out the right
22018 // places to insert EMMS. This qualifies as a quick hack.
22020 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22021 if (VT.getSizeInBits() != 64)
22024 const Function *F = DAG.getMachineFunction().getFunction();
22025 bool NoImplicitFloatOps = F->getAttributes().
22026 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
22027 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22028 && Subtarget->hasSSE2();
22029 if ((VT.isVector() ||
22030 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22031 isa<LoadSDNode>(St->getValue()) &&
22032 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22033 St->getChain().hasOneUse() && !St->isVolatile()) {
22034 SDNode* LdVal = St->getValue().getNode();
22035 LoadSDNode *Ld = nullptr;
22036 int TokenFactorIndex = -1;
22037 SmallVector<SDValue, 8> Ops;
22038 SDNode* ChainVal = St->getChain().getNode();
22039 // Must be a store of a load. We currently handle two cases: the load
22040 // is a direct child, and it's under an intervening TokenFactor. It is
22041 // possible to dig deeper under nested TokenFactors.
22042 if (ChainVal == LdVal)
22043 Ld = cast<LoadSDNode>(St->getChain());
22044 else if (St->getValue().hasOneUse() &&
22045 ChainVal->getOpcode() == ISD::TokenFactor) {
22046 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22047 if (ChainVal->getOperand(i).getNode() == LdVal) {
22048 TokenFactorIndex = i;
22049 Ld = cast<LoadSDNode>(St->getValue());
22051 Ops.push_back(ChainVal->getOperand(i));
22055 if (!Ld || !ISD::isNormalLoad(Ld))
22058 // If this is not the MMX case, i.e. we are just turning i64 load/store
22059 // into f64 load/store, avoid the transformation if there are multiple
22060 // uses of the loaded value.
22061 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22066 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22067 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22069 if (Subtarget->is64Bit() || F64IsLegal) {
22070 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22071 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22072 Ld->getPointerInfo(), Ld->isVolatile(),
22073 Ld->isNonTemporal(), Ld->isInvariant(),
22074 Ld->getAlignment());
22075 SDValue NewChain = NewLd.getValue(1);
22076 if (TokenFactorIndex != -1) {
22077 Ops.push_back(NewChain);
22078 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22080 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22081 St->getPointerInfo(),
22082 St->isVolatile(), St->isNonTemporal(),
22083 St->getAlignment());
22086 // Otherwise, lower to two pairs of 32-bit loads / stores.
22087 SDValue LoAddr = Ld->getBasePtr();
22088 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22089 DAG.getConstant(4, MVT::i32));
22091 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22092 Ld->getPointerInfo(),
22093 Ld->isVolatile(), Ld->isNonTemporal(),
22094 Ld->isInvariant(), Ld->getAlignment());
22095 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22096 Ld->getPointerInfo().getWithOffset(4),
22097 Ld->isVolatile(), Ld->isNonTemporal(),
22099 MinAlign(Ld->getAlignment(), 4));
22101 SDValue NewChain = LoLd.getValue(1);
22102 if (TokenFactorIndex != -1) {
22103 Ops.push_back(LoLd);
22104 Ops.push_back(HiLd);
22105 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22108 LoAddr = St->getBasePtr();
22109 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22110 DAG.getConstant(4, MVT::i32));
22112 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22113 St->getPointerInfo(),
22114 St->isVolatile(), St->isNonTemporal(),
22115 St->getAlignment());
22116 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22117 St->getPointerInfo().getWithOffset(4),
22119 St->isNonTemporal(),
22120 MinAlign(St->getAlignment(), 4));
22121 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22126 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
22127 /// and return the operands for the horizontal operation in LHS and RHS. A
22128 /// horizontal operation performs the binary operation on successive elements
22129 /// of its first operand, then on successive elements of its second operand,
22130 /// returning the resulting values in a vector. For example, if
22131 /// A = < float a0, float a1, float a2, float a3 >
22133 /// B = < float b0, float b1, float b2, float b3 >
22134 /// then the result of doing a horizontal operation on A and B is
22135 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22136 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22137 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22138 /// set to A, RHS to B, and the routine returns 'true'.
22139 /// Note that the binary operation should have the property that if one of the
22140 /// operands is UNDEF then the result is UNDEF.
22141 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22142 // Look for the following pattern: if
22143 // A = < float a0, float a1, float a2, float a3 >
22144 // B = < float b0, float b1, float b2, float b3 >
22146 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22147 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22148 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22149 // which is A horizontal-op B.
22151 // At least one of the operands should be a vector shuffle.
22152 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
22153 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
22156 MVT VT = LHS.getSimpleValueType();
22158 assert((VT.is128BitVector() || VT.is256BitVector()) &&
22159 "Unsupported vector type for horizontal add/sub");
22161 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
22162 // operate independently on 128-bit lanes.
22163 unsigned NumElts = VT.getVectorNumElements();
22164 unsigned NumLanes = VT.getSizeInBits()/128;
22165 unsigned NumLaneElts = NumElts / NumLanes;
22166 assert((NumLaneElts % 2 == 0) &&
22167 "Vector type should have an even number of elements in each lane");
22168 unsigned HalfLaneElts = NumLaneElts/2;
22170 // View LHS in the form
22171 // LHS = VECTOR_SHUFFLE A, B, LMask
22172 // If LHS is not a shuffle then pretend it is the shuffle
22173 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
22174 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
22177 SmallVector<int, 16> LMask(NumElts);
22178 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22179 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
22180 A = LHS.getOperand(0);
22181 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
22182 B = LHS.getOperand(1);
22183 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
22184 std::copy(Mask.begin(), Mask.end(), LMask.begin());
22186 if (LHS.getOpcode() != ISD::UNDEF)
22188 for (unsigned i = 0; i != NumElts; ++i)
22192 // Likewise, view RHS in the form
22193 // RHS = VECTOR_SHUFFLE C, D, RMask
22195 SmallVector<int, 16> RMask(NumElts);
22196 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22197 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
22198 C = RHS.getOperand(0);
22199 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
22200 D = RHS.getOperand(1);
22201 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
22202 std::copy(Mask.begin(), Mask.end(), RMask.begin());
22204 if (RHS.getOpcode() != ISD::UNDEF)
22206 for (unsigned i = 0; i != NumElts; ++i)
22210 // Check that the shuffles are both shuffling the same vectors.
22211 if (!(A == C && B == D) && !(A == D && B == C))
22214 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
22215 if (!A.getNode() && !B.getNode())
22218 // If A and B occur in reverse order in RHS, then "swap" them (which means
22219 // rewriting the mask).
22221 CommuteVectorShuffleMask(RMask, NumElts);
22223 // At this point LHS and RHS are equivalent to
22224 // LHS = VECTOR_SHUFFLE A, B, LMask
22225 // RHS = VECTOR_SHUFFLE A, B, RMask
22226 // Check that the masks correspond to performing a horizontal operation.
22227 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
22228 for (unsigned i = 0; i != NumLaneElts; ++i) {
22229 int LIdx = LMask[i+l], RIdx = RMask[i+l];
22231 // Ignore any UNDEF components.
22232 if (LIdx < 0 || RIdx < 0 ||
22233 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
22234 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
22237 // Check that successive elements are being operated on. If not, this is
22238 // not a horizontal operation.
22239 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
22240 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
22241 if (!(LIdx == Index && RIdx == Index + 1) &&
22242 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
22247 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
22248 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
22252 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
22253 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
22254 const X86Subtarget *Subtarget) {
22255 EVT VT = N->getValueType(0);
22256 SDValue LHS = N->getOperand(0);
22257 SDValue RHS = N->getOperand(1);
22259 // Try to synthesize horizontal adds from adds of shuffles.
22260 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22261 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22262 isHorizontalBinOp(LHS, RHS, true))
22263 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
22267 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
22268 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
22269 const X86Subtarget *Subtarget) {
22270 EVT VT = N->getValueType(0);
22271 SDValue LHS = N->getOperand(0);
22272 SDValue RHS = N->getOperand(1);
22274 // Try to synthesize horizontal subs from subs of shuffles.
22275 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22276 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22277 isHorizontalBinOp(LHS, RHS, false))
22278 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
22282 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
22283 /// X86ISD::FXOR nodes.
22284 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
22285 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
22286 // F[X]OR(0.0, x) -> x
22287 // F[X]OR(x, 0.0) -> x
22288 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22289 if (C->getValueAPF().isPosZero())
22290 return N->getOperand(1);
22291 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22292 if (C->getValueAPF().isPosZero())
22293 return N->getOperand(0);
22297 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
22298 /// X86ISD::FMAX nodes.
22299 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
22300 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
22302 // Only perform optimizations if UnsafeMath is used.
22303 if (!DAG.getTarget().Options.UnsafeFPMath)
22306 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
22307 // into FMINC and FMAXC, which are Commutative operations.
22308 unsigned NewOp = 0;
22309 switch (N->getOpcode()) {
22310 default: llvm_unreachable("unknown opcode");
22311 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
22312 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
22315 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
22316 N->getOperand(0), N->getOperand(1));
22319 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
22320 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
22321 // FAND(0.0, x) -> 0.0
22322 // FAND(x, 0.0) -> 0.0
22323 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22324 if (C->getValueAPF().isPosZero())
22325 return N->getOperand(0);
22326 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22327 if (C->getValueAPF().isPosZero())
22328 return N->getOperand(1);
22332 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
22333 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
22334 // FANDN(x, 0.0) -> 0.0
22335 // FANDN(0.0, x) -> x
22336 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22337 if (C->getValueAPF().isPosZero())
22338 return N->getOperand(1);
22339 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22340 if (C->getValueAPF().isPosZero())
22341 return N->getOperand(1);
22345 static SDValue PerformBTCombine(SDNode *N,
22347 TargetLowering::DAGCombinerInfo &DCI) {
22348 // BT ignores high bits in the bit index operand.
22349 SDValue Op1 = N->getOperand(1);
22350 if (Op1.hasOneUse()) {
22351 unsigned BitWidth = Op1.getValueSizeInBits();
22352 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
22353 APInt KnownZero, KnownOne;
22354 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
22355 !DCI.isBeforeLegalizeOps());
22356 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22357 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
22358 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
22359 DCI.CommitTargetLoweringOpt(TLO);
22364 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
22365 SDValue Op = N->getOperand(0);
22366 if (Op.getOpcode() == ISD::BITCAST)
22367 Op = Op.getOperand(0);
22368 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
22369 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
22370 VT.getVectorElementType().getSizeInBits() ==
22371 OpVT.getVectorElementType().getSizeInBits()) {
22372 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
22377 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
22378 const X86Subtarget *Subtarget) {
22379 EVT VT = N->getValueType(0);
22380 if (!VT.isVector())
22383 SDValue N0 = N->getOperand(0);
22384 SDValue N1 = N->getOperand(1);
22385 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
22388 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
22389 // both SSE and AVX2 since there is no sign-extended shift right
22390 // operation on a vector with 64-bit elements.
22391 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
22392 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
22393 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
22394 N0.getOpcode() == ISD::SIGN_EXTEND)) {
22395 SDValue N00 = N0.getOperand(0);
22397 // EXTLOAD has a better solution on AVX2,
22398 // it may be replaced with X86ISD::VSEXT node.
22399 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
22400 if (!ISD::isNormalLoad(N00.getNode()))
22403 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
22404 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
22406 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
22412 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
22413 TargetLowering::DAGCombinerInfo &DCI,
22414 const X86Subtarget *Subtarget) {
22415 if (!DCI.isBeforeLegalizeOps())
22418 if (!Subtarget->hasFp256())
22421 EVT VT = N->getValueType(0);
22422 if (VT.isVector() && VT.getSizeInBits() == 256) {
22423 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22431 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
22432 const X86Subtarget* Subtarget) {
22434 EVT VT = N->getValueType(0);
22436 // Let legalize expand this if it isn't a legal type yet.
22437 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
22440 EVT ScalarVT = VT.getScalarType();
22441 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
22442 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
22445 SDValue A = N->getOperand(0);
22446 SDValue B = N->getOperand(1);
22447 SDValue C = N->getOperand(2);
22449 bool NegA = (A.getOpcode() == ISD::FNEG);
22450 bool NegB = (B.getOpcode() == ISD::FNEG);
22451 bool NegC = (C.getOpcode() == ISD::FNEG);
22453 // Negative multiplication when NegA xor NegB
22454 bool NegMul = (NegA != NegB);
22456 A = A.getOperand(0);
22458 B = B.getOperand(0);
22460 C = C.getOperand(0);
22464 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
22466 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
22468 return DAG.getNode(Opcode, dl, VT, A, B, C);
22471 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
22472 TargetLowering::DAGCombinerInfo &DCI,
22473 const X86Subtarget *Subtarget) {
22474 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
22475 // (and (i32 x86isd::setcc_carry), 1)
22476 // This eliminates the zext. This transformation is necessary because
22477 // ISD::SETCC is always legalized to i8.
22479 SDValue N0 = N->getOperand(0);
22480 EVT VT = N->getValueType(0);
22482 if (N0.getOpcode() == ISD::AND &&
22484 N0.getOperand(0).hasOneUse()) {
22485 SDValue N00 = N0.getOperand(0);
22486 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22487 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22488 if (!C || C->getZExtValue() != 1)
22490 return DAG.getNode(ISD::AND, dl, VT,
22491 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22492 N00.getOperand(0), N00.getOperand(1)),
22493 DAG.getConstant(1, VT));
22497 if (N0.getOpcode() == ISD::TRUNCATE &&
22499 N0.getOperand(0).hasOneUse()) {
22500 SDValue N00 = N0.getOperand(0);
22501 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22502 return DAG.getNode(ISD::AND, dl, VT,
22503 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22504 N00.getOperand(0), N00.getOperand(1)),
22505 DAG.getConstant(1, VT));
22508 if (VT.is256BitVector()) {
22509 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22517 // Optimize x == -y --> x+y == 0
22518 // x != -y --> x+y != 0
22519 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
22520 const X86Subtarget* Subtarget) {
22521 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
22522 SDValue LHS = N->getOperand(0);
22523 SDValue RHS = N->getOperand(1);
22524 EVT VT = N->getValueType(0);
22527 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
22528 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
22529 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
22530 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22531 LHS.getValueType(), RHS, LHS.getOperand(1));
22532 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22533 addV, DAG.getConstant(0, addV.getValueType()), CC);
22535 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
22536 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
22537 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
22538 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22539 RHS.getValueType(), LHS, RHS.getOperand(1));
22540 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22541 addV, DAG.getConstant(0, addV.getValueType()), CC);
22544 if (VT.getScalarType() == MVT::i1) {
22545 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
22546 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22547 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
22548 if (!IsSEXT0 && !IsVZero0)
22550 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
22551 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22552 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
22554 if (!IsSEXT1 && !IsVZero1)
22557 if (IsSEXT0 && IsVZero1) {
22558 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
22559 if (CC == ISD::SETEQ)
22560 return DAG.getNOT(DL, LHS.getOperand(0), VT);
22561 return LHS.getOperand(0);
22563 if (IsSEXT1 && IsVZero0) {
22564 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
22565 if (CC == ISD::SETEQ)
22566 return DAG.getNOT(DL, RHS.getOperand(0), VT);
22567 return RHS.getOperand(0);
22574 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
22575 const X86Subtarget *Subtarget) {
22577 MVT VT = N->getOperand(1)->getSimpleValueType(0);
22578 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
22579 "X86insertps is only defined for v4x32");
22581 SDValue Ld = N->getOperand(1);
22582 if (MayFoldLoad(Ld)) {
22583 // Extract the countS bits from the immediate so we can get the proper
22584 // address when narrowing the vector load to a specific element.
22585 // When the second source op is a memory address, interps doesn't use
22586 // countS and just gets an f32 from that address.
22587 unsigned DestIndex =
22588 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
22589 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
22593 // Create this as a scalar to vector to match the instruction pattern.
22594 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
22595 // countS bits are ignored when loading from memory on insertps, which
22596 // means we don't need to explicitly set them to 0.
22597 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
22598 LoadScalarToVector, N->getOperand(2));
22601 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
22602 // as "sbb reg,reg", since it can be extended without zext and produces
22603 // an all-ones bit which is more useful than 0/1 in some cases.
22604 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
22607 return DAG.getNode(ISD::AND, DL, VT,
22608 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22609 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
22610 DAG.getConstant(1, VT));
22611 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
22612 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
22613 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22614 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
22617 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
22618 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
22619 TargetLowering::DAGCombinerInfo &DCI,
22620 const X86Subtarget *Subtarget) {
22622 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
22623 SDValue EFLAGS = N->getOperand(1);
22625 if (CC == X86::COND_A) {
22626 // Try to convert COND_A into COND_B in an attempt to facilitate
22627 // materializing "setb reg".
22629 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
22630 // cannot take an immediate as its first operand.
22632 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
22633 EFLAGS.getValueType().isInteger() &&
22634 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
22635 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
22636 EFLAGS.getNode()->getVTList(),
22637 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
22638 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
22639 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
22643 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
22644 // a zext and produces an all-ones bit which is more useful than 0/1 in some
22646 if (CC == X86::COND_B)
22647 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
22651 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22652 if (Flags.getNode()) {
22653 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22654 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
22660 // Optimize branch condition evaluation.
22662 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
22663 TargetLowering::DAGCombinerInfo &DCI,
22664 const X86Subtarget *Subtarget) {
22666 SDValue Chain = N->getOperand(0);
22667 SDValue Dest = N->getOperand(1);
22668 SDValue EFLAGS = N->getOperand(3);
22669 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
22673 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22674 if (Flags.getNode()) {
22675 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22676 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
22683 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
22684 SelectionDAG &DAG) {
22685 // Take advantage of vector comparisons producing 0 or -1 in each lane to
22686 // optimize away operation when it's from a constant.
22688 // The general transformation is:
22689 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
22690 // AND(VECTOR_CMP(x,y), constant2)
22691 // constant2 = UNARYOP(constant)
22693 // Early exit if this isn't a vector operation, the operand of the
22694 // unary operation isn't a bitwise AND, or if the sizes of the operations
22695 // aren't the same.
22696 EVT VT = N->getValueType(0);
22697 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
22698 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
22699 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
22702 // Now check that the other operand of the AND is a constant. We could
22703 // make the transformation for non-constant splats as well, but it's unclear
22704 // that would be a benefit as it would not eliminate any operations, just
22705 // perform one more step in scalar code before moving to the vector unit.
22706 if (BuildVectorSDNode *BV =
22707 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
22708 // Bail out if the vector isn't a constant.
22709 if (!BV->isConstant())
22712 // Everything checks out. Build up the new and improved node.
22714 EVT IntVT = BV->getValueType(0);
22715 // Create a new constant of the appropriate type for the transformed
22717 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
22718 // The AND node needs bitcasts to/from an integer vector type around it.
22719 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
22720 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
22721 N->getOperand(0)->getOperand(0), MaskConst);
22722 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
22729 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
22730 const X86TargetLowering *XTLI) {
22731 // First try to optimize away the conversion entirely when it's
22732 // conditionally from a constant. Vectors only.
22733 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
22734 if (Res != SDValue())
22737 // Now move on to more general possibilities.
22738 SDValue Op0 = N->getOperand(0);
22739 EVT InVT = Op0->getValueType(0);
22741 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
22742 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
22744 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
22745 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
22746 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
22749 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
22750 // a 32-bit target where SSE doesn't support i64->FP operations.
22751 if (Op0.getOpcode() == ISD::LOAD) {
22752 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
22753 EVT VT = Ld->getValueType(0);
22754 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
22755 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
22756 !XTLI->getSubtarget()->is64Bit() &&
22758 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
22759 Ld->getChain(), Op0, DAG);
22760 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
22767 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
22768 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
22769 X86TargetLowering::DAGCombinerInfo &DCI) {
22770 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
22771 // the result is either zero or one (depending on the input carry bit).
22772 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
22773 if (X86::isZeroNode(N->getOperand(0)) &&
22774 X86::isZeroNode(N->getOperand(1)) &&
22775 // We don't have a good way to replace an EFLAGS use, so only do this when
22777 SDValue(N, 1).use_empty()) {
22779 EVT VT = N->getValueType(0);
22780 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
22781 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
22782 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
22783 DAG.getConstant(X86::COND_B,MVT::i8),
22785 DAG.getConstant(1, VT));
22786 return DCI.CombineTo(N, Res1, CarryOut);
22792 // fold (add Y, (sete X, 0)) -> adc 0, Y
22793 // (add Y, (setne X, 0)) -> sbb -1, Y
22794 // (sub (sete X, 0), Y) -> sbb 0, Y
22795 // (sub (setne X, 0), Y) -> adc -1, Y
22796 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
22799 // Look through ZExts.
22800 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
22801 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
22804 SDValue SetCC = Ext.getOperand(0);
22805 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
22808 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
22809 if (CC != X86::COND_E && CC != X86::COND_NE)
22812 SDValue Cmp = SetCC.getOperand(1);
22813 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
22814 !X86::isZeroNode(Cmp.getOperand(1)) ||
22815 !Cmp.getOperand(0).getValueType().isInteger())
22818 SDValue CmpOp0 = Cmp.getOperand(0);
22819 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
22820 DAG.getConstant(1, CmpOp0.getValueType()));
22822 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
22823 if (CC == X86::COND_NE)
22824 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
22825 DL, OtherVal.getValueType(), OtherVal,
22826 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
22827 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
22828 DL, OtherVal.getValueType(), OtherVal,
22829 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
22832 /// PerformADDCombine - Do target-specific dag combines on integer adds.
22833 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
22834 const X86Subtarget *Subtarget) {
22835 EVT VT = N->getValueType(0);
22836 SDValue Op0 = N->getOperand(0);
22837 SDValue Op1 = N->getOperand(1);
22839 // Try to synthesize horizontal adds from adds of shuffles.
22840 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22841 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22842 isHorizontalBinOp(Op0, Op1, true))
22843 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
22845 return OptimizeConditionalInDecrement(N, DAG);
22848 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
22849 const X86Subtarget *Subtarget) {
22850 SDValue Op0 = N->getOperand(0);
22851 SDValue Op1 = N->getOperand(1);
22853 // X86 can't encode an immediate LHS of a sub. See if we can push the
22854 // negation into a preceding instruction.
22855 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
22856 // If the RHS of the sub is a XOR with one use and a constant, invert the
22857 // immediate. Then add one to the LHS of the sub so we can turn
22858 // X-Y -> X+~Y+1, saving one register.
22859 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
22860 isa<ConstantSDNode>(Op1.getOperand(1))) {
22861 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
22862 EVT VT = Op0.getValueType();
22863 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
22865 DAG.getConstant(~XorC, VT));
22866 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
22867 DAG.getConstant(C->getAPIntValue()+1, VT));
22871 // Try to synthesize horizontal adds from adds of shuffles.
22872 EVT VT = N->getValueType(0);
22873 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22874 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22875 isHorizontalBinOp(Op0, Op1, true))
22876 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
22878 return OptimizeConditionalInDecrement(N, DAG);
22881 /// performVZEXTCombine - Performs build vector combines
22882 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
22883 TargetLowering::DAGCombinerInfo &DCI,
22884 const X86Subtarget *Subtarget) {
22885 // (vzext (bitcast (vzext (x)) -> (vzext x)
22886 SDValue In = N->getOperand(0);
22887 while (In.getOpcode() == ISD::BITCAST)
22888 In = In.getOperand(0);
22890 if (In.getOpcode() != X86ISD::VZEXT)
22893 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
22897 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
22898 DAGCombinerInfo &DCI) const {
22899 SelectionDAG &DAG = DCI.DAG;
22900 switch (N->getOpcode()) {
22902 case ISD::EXTRACT_VECTOR_ELT:
22903 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
22905 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
22906 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
22907 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
22908 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
22909 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
22910 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
22913 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
22914 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
22915 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
22916 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
22917 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
22918 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
22919 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
22920 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
22921 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
22923 case X86ISD::FOR: return PerformFORCombine(N, DAG);
22925 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
22926 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
22927 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
22928 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
22929 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
22930 case ISD::ANY_EXTEND:
22931 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
22932 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
22933 case ISD::SIGN_EXTEND_INREG:
22934 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
22935 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
22936 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
22937 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
22938 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
22939 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
22940 case X86ISD::SHUFP: // Handle all target specific shuffles
22941 case X86ISD::PALIGNR:
22942 case X86ISD::UNPCKH:
22943 case X86ISD::UNPCKL:
22944 case X86ISD::MOVHLPS:
22945 case X86ISD::MOVLHPS:
22946 case X86ISD::PSHUFB:
22947 case X86ISD::PSHUFD:
22948 case X86ISD::PSHUFHW:
22949 case X86ISD::PSHUFLW:
22950 case X86ISD::MOVSS:
22951 case X86ISD::MOVSD:
22952 case X86ISD::VPERMILP:
22953 case X86ISD::VPERM2X128:
22954 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
22955 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
22956 case ISD::INTRINSIC_WO_CHAIN:
22957 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
22958 case X86ISD::INSERTPS:
22959 return PerformINSERTPSCombine(N, DAG, Subtarget);
22960 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
22966 /// isTypeDesirableForOp - Return true if the target has native support for
22967 /// the specified value type and it is 'desirable' to use the type for the
22968 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
22969 /// instruction encodings are longer and some i16 instructions are slow.
22970 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
22971 if (!isTypeLegal(VT))
22973 if (VT != MVT::i16)
22980 case ISD::SIGN_EXTEND:
22981 case ISD::ZERO_EXTEND:
22982 case ISD::ANY_EXTEND:
22995 /// IsDesirableToPromoteOp - This method query the target whether it is
22996 /// beneficial for dag combiner to promote the specified node. If true, it
22997 /// should return the desired promotion type by reference.
22998 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
22999 EVT VT = Op.getValueType();
23000 if (VT != MVT::i16)
23003 bool Promote = false;
23004 bool Commute = false;
23005 switch (Op.getOpcode()) {
23008 LoadSDNode *LD = cast<LoadSDNode>(Op);
23009 // If the non-extending load has a single use and it's not live out, then it
23010 // might be folded.
23011 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23012 Op.hasOneUse()*/) {
23013 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23014 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23015 // The only case where we'd want to promote LOAD (rather then it being
23016 // promoted as an operand is when it's only use is liveout.
23017 if (UI->getOpcode() != ISD::CopyToReg)
23024 case ISD::SIGN_EXTEND:
23025 case ISD::ZERO_EXTEND:
23026 case ISD::ANY_EXTEND:
23031 SDValue N0 = Op.getOperand(0);
23032 // Look out for (store (shl (load), x)).
23033 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23046 SDValue N0 = Op.getOperand(0);
23047 SDValue N1 = Op.getOperand(1);
23048 if (!Commute && MayFoldLoad(N1))
23050 // Avoid disabling potential load folding opportunities.
23051 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23053 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
23063 //===----------------------------------------------------------------------===//
23064 // X86 Inline Assembly Support
23065 //===----------------------------------------------------------------------===//
23068 // Helper to match a string separated by whitespace.
23069 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
23070 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
23072 for (unsigned i = 0, e = args.size(); i != e; ++i) {
23073 StringRef piece(*args[i]);
23074 if (!s.startswith(piece)) // Check if the piece matches.
23077 s = s.substr(piece.size());
23078 StringRef::size_type pos = s.find_first_not_of(" \t");
23079 if (pos == 0) // We matched a prefix.
23087 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
23090 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
23092 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
23093 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
23094 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
23095 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
23097 if (AsmPieces.size() == 3)
23099 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
23106 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
23107 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
23109 std::string AsmStr = IA->getAsmString();
23111 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
23112 if (!Ty || Ty->getBitWidth() % 16 != 0)
23115 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
23116 SmallVector<StringRef, 4> AsmPieces;
23117 SplitString(AsmStr, AsmPieces, ";\n");
23119 switch (AsmPieces.size()) {
23120 default: return false;
23122 // FIXME: this should verify that we are targeting a 486 or better. If not,
23123 // we will turn this bswap into something that will be lowered to logical
23124 // ops instead of emitting the bswap asm. For now, we don't support 486 or
23125 // lower so don't worry about this.
23127 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
23128 matchAsm(AsmPieces[0], "bswapl", "$0") ||
23129 matchAsm(AsmPieces[0], "bswapq", "$0") ||
23130 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
23131 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
23132 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
23133 // No need to check constraints, nothing other than the equivalent of
23134 // "=r,0" would be valid here.
23135 return IntrinsicLowering::LowerToByteSwap(CI);
23138 // rorw $$8, ${0:w} --> llvm.bswap.i16
23139 if (CI->getType()->isIntegerTy(16) &&
23140 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23141 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
23142 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
23144 const std::string &ConstraintsStr = IA->getConstraintString();
23145 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23146 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23147 if (clobbersFlagRegisters(AsmPieces))
23148 return IntrinsicLowering::LowerToByteSwap(CI);
23152 if (CI->getType()->isIntegerTy(32) &&
23153 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23154 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
23155 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
23156 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
23158 const std::string &ConstraintsStr = IA->getConstraintString();
23159 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23160 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23161 if (clobbersFlagRegisters(AsmPieces))
23162 return IntrinsicLowering::LowerToByteSwap(CI);
23165 if (CI->getType()->isIntegerTy(64)) {
23166 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
23167 if (Constraints.size() >= 2 &&
23168 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
23169 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
23170 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
23171 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
23172 matchAsm(AsmPieces[1], "bswap", "%edx") &&
23173 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
23174 return IntrinsicLowering::LowerToByteSwap(CI);
23182 /// getConstraintType - Given a constraint letter, return the type of
23183 /// constraint it is for this target.
23184 X86TargetLowering::ConstraintType
23185 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
23186 if (Constraint.size() == 1) {
23187 switch (Constraint[0]) {
23198 return C_RegisterClass;
23222 return TargetLowering::getConstraintType(Constraint);
23225 /// Examine constraint type and operand type and determine a weight value.
23226 /// This object must already have been set up with the operand type
23227 /// and the current alternative constraint selected.
23228 TargetLowering::ConstraintWeight
23229 X86TargetLowering::getSingleConstraintMatchWeight(
23230 AsmOperandInfo &info, const char *constraint) const {
23231 ConstraintWeight weight = CW_Invalid;
23232 Value *CallOperandVal = info.CallOperandVal;
23233 // If we don't have a value, we can't do a match,
23234 // but allow it at the lowest weight.
23235 if (!CallOperandVal)
23237 Type *type = CallOperandVal->getType();
23238 // Look at the constraint type.
23239 switch (*constraint) {
23241 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
23252 if (CallOperandVal->getType()->isIntegerTy())
23253 weight = CW_SpecificReg;
23258 if (type->isFloatingPointTy())
23259 weight = CW_SpecificReg;
23262 if (type->isX86_MMXTy() && Subtarget->hasMMX())
23263 weight = CW_SpecificReg;
23267 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
23268 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
23269 weight = CW_Register;
23272 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
23273 if (C->getZExtValue() <= 31)
23274 weight = CW_Constant;
23278 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23279 if (C->getZExtValue() <= 63)
23280 weight = CW_Constant;
23284 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23285 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
23286 weight = CW_Constant;
23290 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23291 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
23292 weight = CW_Constant;
23296 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23297 if (C->getZExtValue() <= 3)
23298 weight = CW_Constant;
23302 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23303 if (C->getZExtValue() <= 0xff)
23304 weight = CW_Constant;
23309 if (dyn_cast<ConstantFP>(CallOperandVal)) {
23310 weight = CW_Constant;
23314 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23315 if ((C->getSExtValue() >= -0x80000000LL) &&
23316 (C->getSExtValue() <= 0x7fffffffLL))
23317 weight = CW_Constant;
23321 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23322 if (C->getZExtValue() <= 0xffffffff)
23323 weight = CW_Constant;
23330 /// LowerXConstraint - try to replace an X constraint, which matches anything,
23331 /// with another that has more specific requirements based on the type of the
23332 /// corresponding operand.
23333 const char *X86TargetLowering::
23334 LowerXConstraint(EVT ConstraintVT) const {
23335 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
23336 // 'f' like normal targets.
23337 if (ConstraintVT.isFloatingPoint()) {
23338 if (Subtarget->hasSSE2())
23340 if (Subtarget->hasSSE1())
23344 return TargetLowering::LowerXConstraint(ConstraintVT);
23347 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
23348 /// vector. If it is invalid, don't add anything to Ops.
23349 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
23350 std::string &Constraint,
23351 std::vector<SDValue>&Ops,
23352 SelectionDAG &DAG) const {
23355 // Only support length 1 constraints for now.
23356 if (Constraint.length() > 1) return;
23358 char ConstraintLetter = Constraint[0];
23359 switch (ConstraintLetter) {
23362 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23363 if (C->getZExtValue() <= 31) {
23364 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23370 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23371 if (C->getZExtValue() <= 63) {
23372 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23379 if (isInt<8>(C->getSExtValue())) {
23380 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23386 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23387 if (C->getZExtValue() <= 255) {
23388 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23394 // 32-bit signed value
23395 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23396 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23397 C->getSExtValue())) {
23398 // Widen to 64 bits here to get it sign extended.
23399 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
23402 // FIXME gcc accepts some relocatable values here too, but only in certain
23403 // memory models; it's complicated.
23408 // 32-bit unsigned value
23409 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23410 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23411 C->getZExtValue())) {
23412 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23416 // FIXME gcc accepts some relocatable values here too, but only in certain
23417 // memory models; it's complicated.
23421 // Literal immediates are always ok.
23422 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
23423 // Widen to 64 bits here to get it sign extended.
23424 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
23428 // In any sort of PIC mode addresses need to be computed at runtime by
23429 // adding in a register or some sort of table lookup. These can't
23430 // be used as immediates.
23431 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
23434 // If we are in non-pic codegen mode, we allow the address of a global (with
23435 // an optional displacement) to be used with 'i'.
23436 GlobalAddressSDNode *GA = nullptr;
23437 int64_t Offset = 0;
23439 // Match either (GA), (GA+C), (GA+C1+C2), etc.
23441 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
23442 Offset += GA->getOffset();
23444 } else if (Op.getOpcode() == ISD::ADD) {
23445 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23446 Offset += C->getZExtValue();
23447 Op = Op.getOperand(0);
23450 } else if (Op.getOpcode() == ISD::SUB) {
23451 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23452 Offset += -C->getZExtValue();
23453 Op = Op.getOperand(0);
23458 // Otherwise, this isn't something we can handle, reject it.
23462 const GlobalValue *GV = GA->getGlobal();
23463 // If we require an extra load to get this address, as in PIC mode, we
23464 // can't accept it.
23465 if (isGlobalStubReference(
23466 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
23469 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
23470 GA->getValueType(0), Offset);
23475 if (Result.getNode()) {
23476 Ops.push_back(Result);
23479 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
23482 std::pair<unsigned, const TargetRegisterClass*>
23483 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
23485 // First, see if this is a constraint that directly corresponds to an LLVM
23487 if (Constraint.size() == 1) {
23488 // GCC Constraint Letters
23489 switch (Constraint[0]) {
23491 // TODO: Slight differences here in allocation order and leaving
23492 // RIP in the class. Do they matter any more here than they do
23493 // in the normal allocation?
23494 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
23495 if (Subtarget->is64Bit()) {
23496 if (VT == MVT::i32 || VT == MVT::f32)
23497 return std::make_pair(0U, &X86::GR32RegClass);
23498 if (VT == MVT::i16)
23499 return std::make_pair(0U, &X86::GR16RegClass);
23500 if (VT == MVT::i8 || VT == MVT::i1)
23501 return std::make_pair(0U, &X86::GR8RegClass);
23502 if (VT == MVT::i64 || VT == MVT::f64)
23503 return std::make_pair(0U, &X86::GR64RegClass);
23506 // 32-bit fallthrough
23507 case 'Q': // Q_REGS
23508 if (VT == MVT::i32 || VT == MVT::f32)
23509 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
23510 if (VT == MVT::i16)
23511 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
23512 if (VT == MVT::i8 || VT == MVT::i1)
23513 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
23514 if (VT == MVT::i64)
23515 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
23517 case 'r': // GENERAL_REGS
23518 case 'l': // INDEX_REGS
23519 if (VT == MVT::i8 || VT == MVT::i1)
23520 return std::make_pair(0U, &X86::GR8RegClass);
23521 if (VT == MVT::i16)
23522 return std::make_pair(0U, &X86::GR16RegClass);
23523 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
23524 return std::make_pair(0U, &X86::GR32RegClass);
23525 return std::make_pair(0U, &X86::GR64RegClass);
23526 case 'R': // LEGACY_REGS
23527 if (VT == MVT::i8 || VT == MVT::i1)
23528 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
23529 if (VT == MVT::i16)
23530 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
23531 if (VT == MVT::i32 || !Subtarget->is64Bit())
23532 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
23533 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
23534 case 'f': // FP Stack registers.
23535 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
23536 // value to the correct fpstack register class.
23537 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
23538 return std::make_pair(0U, &X86::RFP32RegClass);
23539 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
23540 return std::make_pair(0U, &X86::RFP64RegClass);
23541 return std::make_pair(0U, &X86::RFP80RegClass);
23542 case 'y': // MMX_REGS if MMX allowed.
23543 if (!Subtarget->hasMMX()) break;
23544 return std::make_pair(0U, &X86::VR64RegClass);
23545 case 'Y': // SSE_REGS if SSE2 allowed
23546 if (!Subtarget->hasSSE2()) break;
23548 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
23549 if (!Subtarget->hasSSE1()) break;
23551 switch (VT.SimpleTy) {
23553 // Scalar SSE types.
23556 return std::make_pair(0U, &X86::FR32RegClass);
23559 return std::make_pair(0U, &X86::FR64RegClass);
23567 return std::make_pair(0U, &X86::VR128RegClass);
23575 return std::make_pair(0U, &X86::VR256RegClass);
23580 return std::make_pair(0U, &X86::VR512RegClass);
23586 // Use the default implementation in TargetLowering to convert the register
23587 // constraint into a member of a register class.
23588 std::pair<unsigned, const TargetRegisterClass*> Res;
23589 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
23591 // Not found as a standard register?
23593 // Map st(0) -> st(7) -> ST0
23594 if (Constraint.size() == 7 && Constraint[0] == '{' &&
23595 tolower(Constraint[1]) == 's' &&
23596 tolower(Constraint[2]) == 't' &&
23597 Constraint[3] == '(' &&
23598 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
23599 Constraint[5] == ')' &&
23600 Constraint[6] == '}') {
23602 Res.first = X86::FP0+Constraint[4]-'0';
23603 Res.second = &X86::RFP80RegClass;
23607 // GCC allows "st(0)" to be called just plain "st".
23608 if (StringRef("{st}").equals_lower(Constraint)) {
23609 Res.first = X86::FP0;
23610 Res.second = &X86::RFP80RegClass;
23615 if (StringRef("{flags}").equals_lower(Constraint)) {
23616 Res.first = X86::EFLAGS;
23617 Res.second = &X86::CCRRegClass;
23621 // 'A' means EAX + EDX.
23622 if (Constraint == "A") {
23623 Res.first = X86::EAX;
23624 Res.second = &X86::GR32_ADRegClass;
23630 // Otherwise, check to see if this is a register class of the wrong value
23631 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
23632 // turn into {ax},{dx}.
23633 if (Res.second->hasType(VT))
23634 return Res; // Correct type already, nothing to do.
23636 // All of the single-register GCC register classes map their values onto
23637 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
23638 // really want an 8-bit or 32-bit register, map to the appropriate register
23639 // class and return the appropriate register.
23640 if (Res.second == &X86::GR16RegClass) {
23641 if (VT == MVT::i8 || VT == MVT::i1) {
23642 unsigned DestReg = 0;
23643 switch (Res.first) {
23645 case X86::AX: DestReg = X86::AL; break;
23646 case X86::DX: DestReg = X86::DL; break;
23647 case X86::CX: DestReg = X86::CL; break;
23648 case X86::BX: DestReg = X86::BL; break;
23651 Res.first = DestReg;
23652 Res.second = &X86::GR8RegClass;
23654 } else if (VT == MVT::i32 || VT == MVT::f32) {
23655 unsigned DestReg = 0;
23656 switch (Res.first) {
23658 case X86::AX: DestReg = X86::EAX; break;
23659 case X86::DX: DestReg = X86::EDX; break;
23660 case X86::CX: DestReg = X86::ECX; break;
23661 case X86::BX: DestReg = X86::EBX; break;
23662 case X86::SI: DestReg = X86::ESI; break;
23663 case X86::DI: DestReg = X86::EDI; break;
23664 case X86::BP: DestReg = X86::EBP; break;
23665 case X86::SP: DestReg = X86::ESP; break;
23668 Res.first = DestReg;
23669 Res.second = &X86::GR32RegClass;
23671 } else if (VT == MVT::i64 || VT == MVT::f64) {
23672 unsigned DestReg = 0;
23673 switch (Res.first) {
23675 case X86::AX: DestReg = X86::RAX; break;
23676 case X86::DX: DestReg = X86::RDX; break;
23677 case X86::CX: DestReg = X86::RCX; break;
23678 case X86::BX: DestReg = X86::RBX; break;
23679 case X86::SI: DestReg = X86::RSI; break;
23680 case X86::DI: DestReg = X86::RDI; break;
23681 case X86::BP: DestReg = X86::RBP; break;
23682 case X86::SP: DestReg = X86::RSP; break;
23685 Res.first = DestReg;
23686 Res.second = &X86::GR64RegClass;
23689 } else if (Res.second == &X86::FR32RegClass ||
23690 Res.second == &X86::FR64RegClass ||
23691 Res.second == &X86::VR128RegClass ||
23692 Res.second == &X86::VR256RegClass ||
23693 Res.second == &X86::FR32XRegClass ||
23694 Res.second == &X86::FR64XRegClass ||
23695 Res.second == &X86::VR128XRegClass ||
23696 Res.second == &X86::VR256XRegClass ||
23697 Res.second == &X86::VR512RegClass) {
23698 // Handle references to XMM physical registers that got mapped into the
23699 // wrong class. This can happen with constraints like {xmm0} where the
23700 // target independent register mapper will just pick the first match it can
23701 // find, ignoring the required type.
23703 if (VT == MVT::f32 || VT == MVT::i32)
23704 Res.second = &X86::FR32RegClass;
23705 else if (VT == MVT::f64 || VT == MVT::i64)
23706 Res.second = &X86::FR64RegClass;
23707 else if (X86::VR128RegClass.hasType(VT))
23708 Res.second = &X86::VR128RegClass;
23709 else if (X86::VR256RegClass.hasType(VT))
23710 Res.second = &X86::VR256RegClass;
23711 else if (X86::VR512RegClass.hasType(VT))
23712 Res.second = &X86::VR512RegClass;
23718 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
23720 // Scaling factors are not free at all.
23721 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
23722 // will take 2 allocations in the out of order engine instead of 1
23723 // for plain addressing mode, i.e. inst (reg1).
23725 // vaddps (%rsi,%drx), %ymm0, %ymm1
23726 // Requires two allocations (one for the load, one for the computation)
23728 // vaddps (%rsi), %ymm0, %ymm1
23729 // Requires just 1 allocation, i.e., freeing allocations for other operations
23730 // and having less micro operations to execute.
23732 // For some X86 architectures, this is even worse because for instance for
23733 // stores, the complex addressing mode forces the instruction to use the
23734 // "load" ports instead of the dedicated "store" port.
23735 // E.g., on Haswell:
23736 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
23737 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
23738 if (isLegalAddressingMode(AM, Ty))
23739 // Scale represents reg2 * scale, thus account for 1
23740 // as soon as we use a second register.
23741 return AM.Scale != 0;
23745 bool X86TargetLowering::isTargetFTOL() const {
23746 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();